1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hw.h - DesignWare HS OTG Controller hardware definitions
5 * Copyright 2004-2013 Synopsys, Inc.
11 #define HSOTG_REG(x) (x)
13 #define GOTGCTL HSOTG_REG(0x000)
14 #define GOTGCTL_CHIRPEN BIT(27)
15 #define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
16 #define GOTGCTL_MULT_VALID_BC_SHIFT 22
17 #define GOTGCTL_CURMODE_HOST BIT(21)
18 #define GOTGCTL_OTGVER BIT(20)
19 #define GOTGCTL_BSESVLD BIT(19)
20 #define GOTGCTL_ASESVLD BIT(18)
21 #define GOTGCTL_DBNC_SHORT BIT(17)
22 #define GOTGCTL_CONID_B BIT(16)
23 #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
24 #define GOTGCTL_DEVHNPEN BIT(11)
25 #define GOTGCTL_HSTSETHNPEN BIT(10)
26 #define GOTGCTL_HNPREQ BIT(9)
27 #define GOTGCTL_HSTNEGSCS BIT(8)
28 #define GOTGCTL_BVALOVAL BIT(7)
29 #define GOTGCTL_BVALOEN BIT(6)
30 #define GOTGCTL_AVALOVAL BIT(5)
31 #define GOTGCTL_AVALOEN BIT(4)
32 #define GOTGCTL_VBVALOVAL BIT(3)
33 #define GOTGCTL_VBVALOEN BIT(2)
34 #define GOTGCTL_SESREQ BIT(1)
35 #define GOTGCTL_SESREQSCS BIT(0)
37 #define GOTGINT HSOTG_REG(0x004)
38 #define GOTGINT_DBNCE_DONE BIT(19)
39 #define GOTGINT_A_DEV_TOUT_CHG BIT(18)
40 #define GOTGINT_HST_NEG_DET BIT(17)
41 #define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
42 #define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
43 #define GOTGINT_SES_END_DET BIT(2)
45 #define GAHBCFG HSOTG_REG(0x008)
46 #define GAHBCFG_AHB_SINGLE BIT(23)
47 #define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
48 #define GAHBCFG_REM_MEM_SUPP BIT(21)
49 #define GAHBCFG_P_TXF_EMP_LVL BIT(8)
50 #define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
51 #define GAHBCFG_DMA_EN BIT(5)
52 #define GAHBCFG_HBSTLEN_MASK (0xf << 1)
53 #define GAHBCFG_HBSTLEN_SHIFT 1
54 #define GAHBCFG_HBSTLEN_SINGLE 0
55 #define GAHBCFG_HBSTLEN_INCR 1
56 #define GAHBCFG_HBSTLEN_INCR4 3
57 #define GAHBCFG_HBSTLEN_INCR8 5
58 #define GAHBCFG_HBSTLEN_INCR16 7
59 #define GAHBCFG_GLBL_INTR_EN BIT(0)
60 #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
61 GAHBCFG_NP_TXF_EMP_LVL | \
65 #define GUSBCFG HSOTG_REG(0x00C)
66 #define GUSBCFG_FORCEDEVMODE BIT(30)
67 #define GUSBCFG_FORCEHOSTMODE BIT(29)
68 #define GUSBCFG_TXENDDELAY BIT(28)
69 #define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
70 #define GUSBCFG_ICUSBCAP BIT(26)
71 #define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
72 #define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
73 #define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
74 #define GUSBCFG_TERMSELDLPULSE BIT(22)
75 #define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
76 #define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
77 #define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
78 #define GUSBCFG_ULPI_AUTO_RES BIT(18)
79 #define GUSBCFG_ULPI_FS_LS BIT(17)
80 #define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
81 #define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
82 #define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
83 #define GUSBCFG_USBTRDTIM_SHIFT 10
84 #define GUSBCFG_HNPCAP BIT(9)
85 #define GUSBCFG_SRPCAP BIT(8)
86 #define GUSBCFG_DDRSEL BIT(7)
87 #define GUSBCFG_PHYSEL BIT(6)
88 #define GUSBCFG_FSINTF BIT(5)
89 #define GUSBCFG_ULPI_UTMI_SEL BIT(4)
90 #define GUSBCFG_PHYIF16 BIT(3)
91 #define GUSBCFG_PHYIF8 (0 << 3)
92 #define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
93 #define GUSBCFG_TOUTCAL_SHIFT 0
94 #define GUSBCFG_TOUTCAL_LIMIT 0x7
95 #define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
97 #define GRSTCTL HSOTG_REG(0x010)
98 #define GRSTCTL_AHBIDLE BIT(31)
99 #define GRSTCTL_DMAREQ BIT(30)
100 #define GRSTCTL_CSFTRST_DONE BIT(29)
101 #define GRSTCTL_TXFNUM_MASK (0x1f << 6)
102 #define GRSTCTL_TXFNUM_SHIFT 6
103 #define GRSTCTL_TXFNUM_LIMIT 0x1f
104 #define GRSTCTL_TXFNUM(_x) ((_x) << 6)
105 #define GRSTCTL_TXFFLSH BIT(5)
106 #define GRSTCTL_RXFFLSH BIT(4)
107 #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
108 #define GRSTCTL_FRMCNTRRST BIT(2)
109 #define GRSTCTL_HSFTRST BIT(1)
110 #define GRSTCTL_CSFTRST BIT(0)
112 #define GINTSTS HSOTG_REG(0x014)
113 #define GINTMSK HSOTG_REG(0x018)
114 #define GINTSTS_WKUPINT BIT(31)
115 #define GINTSTS_SESSREQINT BIT(30)
116 #define GINTSTS_DISCONNINT BIT(29)
117 #define GINTSTS_CONIDSTSCHNG BIT(28)
118 #define GINTSTS_LPMTRANRCVD BIT(27)
119 #define GINTSTS_PTXFEMP BIT(26)
120 #define GINTSTS_HCHINT BIT(25)
121 #define GINTSTS_PRTINT BIT(24)
122 #define GINTSTS_RESETDET BIT(23)
123 #define GINTSTS_FET_SUSP BIT(22)
124 #define GINTSTS_INCOMPL_IP BIT(21)
125 #define GINTSTS_INCOMPL_SOOUT BIT(21)
126 #define GINTSTS_INCOMPL_SOIN BIT(20)
127 #define GINTSTS_OEPINT BIT(19)
128 #define GINTSTS_IEPINT BIT(18)
129 #define GINTSTS_EPMIS BIT(17)
130 #define GINTSTS_RESTOREDONE BIT(16)
131 #define GINTSTS_EOPF BIT(15)
132 #define GINTSTS_ISOUTDROP BIT(14)
133 #define GINTSTS_ENUMDONE BIT(13)
134 #define GINTSTS_USBRST BIT(12)
135 #define GINTSTS_USBSUSP BIT(11)
136 #define GINTSTS_ERLYSUSP BIT(10)
137 #define GINTSTS_I2CINT BIT(9)
138 #define GINTSTS_ULPI_CK_INT BIT(8)
139 #define GINTSTS_GOUTNAKEFF BIT(7)
140 #define GINTSTS_GINNAKEFF BIT(6)
141 #define GINTSTS_NPTXFEMP BIT(5)
142 #define GINTSTS_RXFLVL BIT(4)
143 #define GINTSTS_SOF BIT(3)
144 #define GINTSTS_OTGINT BIT(2)
145 #define GINTSTS_MODEMIS BIT(1)
146 #define GINTSTS_CURMODE_HOST BIT(0)
148 #define GRXSTSR HSOTG_REG(0x01C)
149 #define GRXSTSP HSOTG_REG(0x020)
150 #define GRXSTS_FN_MASK (0x7f << 25)
151 #define GRXSTS_FN_SHIFT 25
152 #define GRXSTS_PKTSTS_MASK (0xf << 17)
153 #define GRXSTS_PKTSTS_SHIFT 17
154 #define GRXSTS_PKTSTS_GLOBALOUTNAK 1
155 #define GRXSTS_PKTSTS_OUTRX 2
156 #define GRXSTS_PKTSTS_HCHIN 2
157 #define GRXSTS_PKTSTS_OUTDONE 3
158 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
159 #define GRXSTS_PKTSTS_SETUPDONE 4
160 #define GRXSTS_PKTSTS_DATATOGGLEERR 5
161 #define GRXSTS_PKTSTS_SETUPRX 6
162 #define GRXSTS_PKTSTS_HCHHALTED 7
163 #define GRXSTS_HCHNUM_MASK (0xf << 0)
164 #define GRXSTS_HCHNUM_SHIFT 0
165 #define GRXSTS_DPID_MASK (0x3 << 15)
166 #define GRXSTS_DPID_SHIFT 15
167 #define GRXSTS_BYTECNT_MASK (0x7ff << 4)
168 #define GRXSTS_BYTECNT_SHIFT 4
169 #define GRXSTS_EPNUM_MASK (0xf << 0)
170 #define GRXSTS_EPNUM_SHIFT 0
172 #define GRXFSIZ HSOTG_REG(0x024)
173 #define GRXFSIZ_DEPTH_MASK (0xffff << 0)
174 #define GRXFSIZ_DEPTH_SHIFT 0
176 #define GNPTXFSIZ HSOTG_REG(0x028)
177 /* Use FIFOSIZE_* constants to access this register */
179 #define GNPTXSTS HSOTG_REG(0x02C)
180 #define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
181 #define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
182 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
183 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
184 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
185 #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
186 #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0
187 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
189 #define GI2CCTL HSOTG_REG(0x0030)
190 #define GI2CCTL_BSYDNE BIT(31)
191 #define GI2CCTL_RW BIT(30)
192 #define GI2CCTL_I2CDATSE0 BIT(28)
193 #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
194 #define GI2CCTL_I2CDEVADDR_SHIFT 26
195 #define GI2CCTL_I2CSUSPCTL BIT(25)
196 #define GI2CCTL_ACK BIT(24)
197 #define GI2CCTL_I2CEN BIT(23)
198 #define GI2CCTL_ADDR_MASK (0x7f << 16)
199 #define GI2CCTL_ADDR_SHIFT 16
200 #define GI2CCTL_REGADDR_MASK (0xff << 8)
201 #define GI2CCTL_REGADDR_SHIFT 8
202 #define GI2CCTL_RWDATA_MASK (0xff << 0)
203 #define GI2CCTL_RWDATA_SHIFT 0
205 #define GPVNDCTL HSOTG_REG(0x0034)
206 #define GGPIO HSOTG_REG(0x0038)
207 #define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16)
208 #define GGPIO_STM32_OTG_GCCFG_VBDEN BIT(21)
209 #define GGPIO_STM32_OTG_GCCFG_IDEN BIT(22)
211 #define GUID HSOTG_REG(0x003c)
212 #define GSNPSID HSOTG_REG(0x0040)
213 #define GHWCFG1 HSOTG_REG(0x0044)
214 #define GSNPSID_ID_MASK GENMASK(31, 16)
216 #define GHWCFG2 HSOTG_REG(0x0048)
217 #define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
218 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
219 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
220 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
221 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
222 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
223 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
224 #define GHWCFG2_MULTI_PROC_INT BIT(20)
225 #define GHWCFG2_DYNAMIC_FIFO BIT(19)
226 #define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
227 #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
228 #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
229 #define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
230 #define GHWCFG2_NUM_DEV_EP_SHIFT 10
231 #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
232 #define GHWCFG2_FS_PHY_TYPE_SHIFT 8
233 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
234 #define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
235 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
236 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
237 #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
238 #define GHWCFG2_HS_PHY_TYPE_SHIFT 6
239 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
240 #define GHWCFG2_HS_PHY_TYPE_UTMI 1
241 #define GHWCFG2_HS_PHY_TYPE_ULPI 2
242 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
243 #define GHWCFG2_POINT2POINT BIT(5)
244 #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
245 #define GHWCFG2_ARCHITECTURE_SHIFT 3
246 #define GHWCFG2_SLAVE_ONLY_ARCH 0
247 #define GHWCFG2_EXT_DMA_ARCH 1
248 #define GHWCFG2_INT_DMA_ARCH 2
249 #define GHWCFG2_OP_MODE_MASK (0x7 << 0)
250 #define GHWCFG2_OP_MODE_SHIFT 0
251 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
252 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
253 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
254 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
255 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
256 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
257 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
258 #define GHWCFG2_OP_MODE_UNDEFINED 7
260 #define GHWCFG3 HSOTG_REG(0x004c)
261 #define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
262 #define GHWCFG3_DFIFO_DEPTH_SHIFT 16
263 #define GHWCFG3_OTG_LPM_EN BIT(15)
264 #define GHWCFG3_BC_SUPPORT BIT(14)
265 #define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
266 #define GHWCFG3_ADP_SUPP BIT(12)
267 #define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
268 #define GHWCFG3_OPTIONAL_FEATURES BIT(10)
269 #define GHWCFG3_VENDOR_CTRL_IF BIT(9)
270 #define GHWCFG3_I2C BIT(8)
271 #define GHWCFG3_OTG_FUNC BIT(7)
272 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
273 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
274 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
275 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
277 #define GHWCFG4 HSOTG_REG(0x0050)
278 #define GHWCFG4_DESC_DMA_DYN BIT(31)
279 #define GHWCFG4_DESC_DMA BIT(30)
280 #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
281 #define GHWCFG4_NUM_IN_EPS_SHIFT 26
282 #define GHWCFG4_DED_FIFO_EN BIT(25)
283 #define GHWCFG4_DED_FIFO_SHIFT 25
284 #define GHWCFG4_SESSION_END_FILT_EN BIT(24)
285 #define GHWCFG4_B_VALID_FILT_EN BIT(23)
286 #define GHWCFG4_A_VALID_FILT_EN BIT(22)
287 #define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
288 #define GHWCFG4_IDDIG_FILT_EN BIT(20)
289 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
290 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
291 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
292 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
293 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
294 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
295 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
296 #define GHWCFG4_ACG_SUPPORTED BIT(12)
297 #define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11)
298 #define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10)
299 #define GHWCFG4_XHIBER BIT(7)
300 #define GHWCFG4_HIBER BIT(6)
301 #define GHWCFG4_MIN_AHB_FREQ BIT(5)
302 #define GHWCFG4_POWER_OPTIMIZ BIT(4)
303 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
304 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
306 #define GLPMCFG HSOTG_REG(0x0054)
307 #define GLPMCFG_INVSELHSIC BIT(31)
308 #define GLPMCFG_HSICCON BIT(30)
309 #define GLPMCFG_RSTRSLPSTS BIT(29)
310 #define GLPMCFG_ENBESL BIT(28)
311 #define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25)
312 #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25
313 #define GLPMCFG_SNDLPM BIT(24)
314 #define GLPMCFG_RETRY_CNT_MASK (0x7 << 21)
315 #define GLPMCFG_RETRY_CNT_SHIFT 21
316 #define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21)
317 #define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22)
318 #define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17)
319 #define GLPMCFG_LPM_CHNL_INDX_SHIFT 17
320 #define GLPMCFG_L1RESUMEOK BIT(16)
321 #define GLPMCFG_SLPSTS BIT(15)
322 #define GLPMCFG_COREL1RES_MASK (0x3 << 13)
323 #define GLPMCFG_COREL1RES_SHIFT 13
324 #define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
325 #define GLPMCFG_HIRD_THRES_SHIFT 8
326 #define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
327 #define GLPMCFG_ENBLSLPM BIT(7)
328 #define GLPMCFG_BREMOTEWAKE BIT(6)
329 #define GLPMCFG_HIRD_MASK (0xf << 2)
330 #define GLPMCFG_HIRD_SHIFT 2
331 #define GLPMCFG_APPL1RES BIT(1)
332 #define GLPMCFG_LPMCAP BIT(0)
334 #define GPWRDN HSOTG_REG(0x0058)
335 #define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
336 #define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
337 #define GPWRDN_ADP_INT BIT(23)
338 #define GPWRDN_BSESSVLD BIT(22)
339 #define GPWRDN_IDSTS BIT(21)
340 #define GPWRDN_LINESTATE_MASK (0x3 << 19)
341 #define GPWRDN_LINESTATE_SHIFT 19
342 #define GPWRDN_STS_CHGINT_MSK BIT(18)
343 #define GPWRDN_STS_CHGINT BIT(17)
344 #define GPWRDN_SRP_DET_MSK BIT(16)
345 #define GPWRDN_SRP_DET BIT(15)
346 #define GPWRDN_CONNECT_DET_MSK BIT(14)
347 #define GPWRDN_CONNECT_DET BIT(13)
348 #define GPWRDN_DISCONN_DET_MSK BIT(12)
349 #define GPWRDN_DISCONN_DET BIT(11)
350 #define GPWRDN_RST_DET_MSK BIT(10)
351 #define GPWRDN_RST_DET BIT(9)
352 #define GPWRDN_LNSTSCHG_MSK BIT(8)
353 #define GPWRDN_LNSTSCHG BIT(7)
354 #define GPWRDN_DIS_VBUS BIT(6)
355 #define GPWRDN_PWRDNSWTCH BIT(5)
356 #define GPWRDN_PWRDNRSTN BIT(4)
357 #define GPWRDN_PWRDNCLMP BIT(3)
358 #define GPWRDN_RESTORE BIT(2)
359 #define GPWRDN_PMUACTV BIT(1)
360 #define GPWRDN_PMUINTSEL BIT(0)
362 #define GDFIFOCFG HSOTG_REG(0x005c)
363 #define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
364 #define GDFIFOCFG_EPINFOBASE_SHIFT 16
365 #define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
366 #define GDFIFOCFG_GDFIFOCFG_SHIFT 0
368 #define ADPCTL HSOTG_REG(0x0060)
369 #define ADPCTL_AR_MASK (0x3 << 27)
370 #define ADPCTL_AR_SHIFT 27
371 #define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
372 #define ADPCTL_ADP_SNS_INT_MSK BIT(25)
373 #define ADPCTL_ADP_PRB_INT_MSK BIT(24)
374 #define ADPCTL_ADP_TMOUT_INT BIT(23)
375 #define ADPCTL_ADP_SNS_INT BIT(22)
376 #define ADPCTL_ADP_PRB_INT BIT(21)
377 #define ADPCTL_ADPENA BIT(20)
378 #define ADPCTL_ADPRES BIT(19)
379 #define ADPCTL_ENASNS BIT(18)
380 #define ADPCTL_ENAPRB BIT(17)
381 #define ADPCTL_RTIM_MASK (0x7ff << 6)
382 #define ADPCTL_RTIM_SHIFT 6
383 #define ADPCTL_PRB_PER_MASK (0x3 << 4)
384 #define ADPCTL_PRB_PER_SHIFT 4
385 #define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
386 #define ADPCTL_PRB_DELTA_SHIFT 2
387 #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
388 #define ADPCTL_PRB_DSCHRG_SHIFT 0
390 #define GREFCLK HSOTG_REG(0x0064)
391 #define GREFCLK_REFCLKPER_MASK (0x1ffff << 15)
392 #define GREFCLK_REFCLKPER_SHIFT 15
393 #define GREFCLK_REF_CLK_MODE BIT(14)
394 #define GREFCLK_SOF_CNT_WKUP_ALERT_MASK (0x3ff)
395 #define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT 0
397 #define GINTMSK2 HSOTG_REG(0x0068)
398 #define GINTMSK2_WKUP_ALERT_INT_MSK BIT(0)
400 #define GINTSTS2 HSOTG_REG(0x006c)
401 #define GINTSTS2_WKUP_ALERT_INT BIT(0)
403 #define HPTXFSIZ HSOTG_REG(0x100)
404 /* Use FIFOSIZE_* constants to access this register */
406 #define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
407 /* Use FIFOSIZE_* constants to access this register */
409 /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
410 #define FIFOSIZE_DEPTH_MASK (0xffff << 16)
411 #define FIFOSIZE_DEPTH_SHIFT 16
412 #define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
413 #define FIFOSIZE_STARTADDR_SHIFT 0
414 #define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
416 /* Device mode registers */
418 #define DCFG HSOTG_REG(0x800)
419 #define DCFG_DESCDMA_EN BIT(23)
420 #define DCFG_EPMISCNT_MASK (0x1f << 18)
421 #define DCFG_EPMISCNT_SHIFT 18
422 #define DCFG_EPMISCNT_LIMIT 0x1f
423 #define DCFG_EPMISCNT(_x) ((_x) << 18)
424 #define DCFG_IPG_ISOC_SUPPORDED BIT(17)
425 #define DCFG_PERFRINT_MASK (0x3 << 11)
426 #define DCFG_PERFRINT_SHIFT 11
427 #define DCFG_PERFRINT_LIMIT 0x3
428 #define DCFG_PERFRINT(_x) ((_x) << 11)
429 #define DCFG_DEVADDR_MASK (0x7f << 4)
430 #define DCFG_DEVADDR_SHIFT 4
431 #define DCFG_DEVADDR_LIMIT 0x7f
432 #define DCFG_DEVADDR(_x) ((_x) << 4)
433 #define DCFG_NZ_STS_OUT_HSHK BIT(2)
434 #define DCFG_DEVSPD_MASK (0x3 << 0)
435 #define DCFG_DEVSPD_SHIFT 0
436 #define DCFG_DEVSPD_HS 0
437 #define DCFG_DEVSPD_FS 1
438 #define DCFG_DEVSPD_LS 2
439 #define DCFG_DEVSPD_FS48 3
441 #define DCTL HSOTG_REG(0x804)
442 #define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19)
443 #define DCTL_PWRONPRGDONE BIT(11)
444 #define DCTL_CGOUTNAK BIT(10)
445 #define DCTL_SGOUTNAK BIT(9)
446 #define DCTL_CGNPINNAK BIT(8)
447 #define DCTL_SGNPINNAK BIT(7)
448 #define DCTL_TSTCTL_MASK (0x7 << 4)
449 #define DCTL_TSTCTL_SHIFT 4
450 #define DCTL_GOUTNAKSTS BIT(3)
451 #define DCTL_GNPINNAKSTS BIT(2)
452 #define DCTL_SFTDISCON BIT(1)
453 #define DCTL_RMTWKUPSIG BIT(0)
455 #define DSTS HSOTG_REG(0x808)
456 #define DSTS_SOFFN_MASK (0x3fff << 8)
457 #define DSTS_SOFFN_SHIFT 8
458 #define DSTS_SOFFN_LIMIT 0x3fff
459 #define DSTS_SOFFN(_x) ((_x) << 8)
460 #define DSTS_ERRATICERR BIT(3)
461 #define DSTS_ENUMSPD_MASK (0x3 << 1)
462 #define DSTS_ENUMSPD_SHIFT 1
463 #define DSTS_ENUMSPD_HS 0
464 #define DSTS_ENUMSPD_FS 1
465 #define DSTS_ENUMSPD_LS 2
466 #define DSTS_ENUMSPD_FS48 3
467 #define DSTS_SUSPSTS BIT(0)
469 #define DIEPMSK HSOTG_REG(0x810)
470 #define DIEPMSK_NAKMSK BIT(13)
471 #define DIEPMSK_BNAININTRMSK BIT(9)
472 #define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
473 #define DIEPMSK_TXFIFOEMPTY BIT(7)
474 #define DIEPMSK_INEPNAKEFFMSK BIT(6)
475 #define DIEPMSK_INTKNEPMISMSK BIT(5)
476 #define DIEPMSK_INTKNTXFEMPMSK BIT(4)
477 #define DIEPMSK_TIMEOUTMSK BIT(3)
478 #define DIEPMSK_AHBERRMSK BIT(2)
479 #define DIEPMSK_EPDISBLDMSK BIT(1)
480 #define DIEPMSK_XFERCOMPLMSK BIT(0)
482 #define DOEPMSK HSOTG_REG(0x814)
483 #define DOEPMSK_BNAMSK BIT(9)
484 #define DOEPMSK_BACK2BACKSETUP BIT(6)
485 #define DOEPMSK_STSPHSERCVDMSK BIT(5)
486 #define DOEPMSK_OUTTKNEPDISMSK BIT(4)
487 #define DOEPMSK_SETUPMSK BIT(3)
488 #define DOEPMSK_AHBERRMSK BIT(2)
489 #define DOEPMSK_EPDISBLDMSK BIT(1)
490 #define DOEPMSK_XFERCOMPLMSK BIT(0)
492 #define DAINT HSOTG_REG(0x818)
493 #define DAINTMSK HSOTG_REG(0x81C)
494 #define DAINT_OUTEP_SHIFT 16
495 #define DAINT_OUTEP(_x) (1 << ((_x) + 16))
496 #define DAINT_INEP(_x) (1 << (_x))
498 #define DTKNQR1 HSOTG_REG(0x820)
499 #define DTKNQR2 HSOTG_REG(0x824)
500 #define DTKNQR3 HSOTG_REG(0x830)
501 #define DTKNQR4 HSOTG_REG(0x834)
502 #define DIEPEMPMSK HSOTG_REG(0x834)
504 #define DVBUSDIS HSOTG_REG(0x828)
505 #define DVBUSPULSE HSOTG_REG(0x82C)
507 #define DIEPCTL0 HSOTG_REG(0x900)
508 #define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
510 #define DOEPCTL0 HSOTG_REG(0xB00)
511 #define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
514 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
515 * bits[25..22] - should always be zero, this isn't a periodic endpoint
516 * bits[10..0] - MPS setting different for EP0
518 #define D0EPCTL_MPS_MASK (0x3 << 0)
519 #define D0EPCTL_MPS_SHIFT 0
520 #define D0EPCTL_MPS_64 0
521 #define D0EPCTL_MPS_32 1
522 #define D0EPCTL_MPS_16 2
523 #define D0EPCTL_MPS_8 3
525 #define DXEPCTL_EPENA BIT(31)
526 #define DXEPCTL_EPDIS BIT(30)
527 #define DXEPCTL_SETD1PID BIT(29)
528 #define DXEPCTL_SETODDFR BIT(29)
529 #define DXEPCTL_SETD0PID BIT(28)
530 #define DXEPCTL_SETEVENFR BIT(28)
531 #define DXEPCTL_SNAK BIT(27)
532 #define DXEPCTL_CNAK BIT(26)
533 #define DXEPCTL_TXFNUM_MASK (0xf << 22)
534 #define DXEPCTL_TXFNUM_SHIFT 22
535 #define DXEPCTL_TXFNUM_LIMIT 0xf
536 #define DXEPCTL_TXFNUM(_x) ((_x) << 22)
537 #define DXEPCTL_STALL BIT(21)
538 #define DXEPCTL_SNP BIT(20)
539 #define DXEPCTL_EPTYPE_MASK (0x3 << 18)
540 #define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
541 #define DXEPCTL_EPTYPE_ISO (0x1 << 18)
542 #define DXEPCTL_EPTYPE_BULK (0x2 << 18)
543 #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
545 #define DXEPCTL_NAKSTS BIT(17)
546 #define DXEPCTL_DPID BIT(16)
547 #define DXEPCTL_EOFRNUM BIT(16)
548 #define DXEPCTL_USBACTEP BIT(15)
549 #define DXEPCTL_NEXTEP_MASK (0xf << 11)
550 #define DXEPCTL_NEXTEP_SHIFT 11
551 #define DXEPCTL_NEXTEP_LIMIT 0xf
552 #define DXEPCTL_NEXTEP(_x) ((_x) << 11)
553 #define DXEPCTL_MPS_MASK (0x7ff << 0)
554 #define DXEPCTL_MPS_SHIFT 0
555 #define DXEPCTL_MPS_LIMIT 0x7ff
556 #define DXEPCTL_MPS(_x) ((_x) << 0)
558 #define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
559 #define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
560 #define DXEPINT_SETUP_RCVD BIT(15)
561 #define DXEPINT_NYETINTRPT BIT(14)
562 #define DXEPINT_NAKINTRPT BIT(13)
563 #define DXEPINT_BBLEERRINTRPT BIT(12)
564 #define DXEPINT_PKTDRPSTS BIT(11)
565 #define DXEPINT_BNAINTR BIT(9)
566 #define DXEPINT_TXFIFOUNDRN BIT(8)
567 #define DXEPINT_OUTPKTERR BIT(8)
568 #define DXEPINT_TXFEMP BIT(7)
569 #define DXEPINT_INEPNAKEFF BIT(6)
570 #define DXEPINT_BACK2BACKSETUP BIT(6)
571 #define DXEPINT_INTKNEPMIS BIT(5)
572 #define DXEPINT_STSPHSERCVD BIT(5)
573 #define DXEPINT_INTKNTXFEMP BIT(4)
574 #define DXEPINT_OUTTKNEPDIS BIT(4)
575 #define DXEPINT_TIMEOUT BIT(3)
576 #define DXEPINT_SETUP BIT(3)
577 #define DXEPINT_AHBERR BIT(2)
578 #define DXEPINT_EPDISBLD BIT(1)
579 #define DXEPINT_XFERCOMPL BIT(0)
581 #define DIEPTSIZ0 HSOTG_REG(0x910)
582 #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
583 #define DIEPTSIZ0_PKTCNT_SHIFT 19
584 #define DIEPTSIZ0_PKTCNT_LIMIT 0x3
585 #define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19)
586 #define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
587 #define DIEPTSIZ0_XFERSIZE_SHIFT 0
588 #define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f
589 #define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0)
591 #define DOEPTSIZ0 HSOTG_REG(0xB10)
592 #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
593 #define DOEPTSIZ0_SUPCNT_SHIFT 29
594 #define DOEPTSIZ0_SUPCNT_LIMIT 0x3
595 #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
596 #define DOEPTSIZ0_PKTCNT BIT(19)
597 #define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
598 #define DOEPTSIZ0_XFERSIZE_SHIFT 0
600 #define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
601 #define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
602 #define DXEPTSIZ_MC_MASK (0x3 << 29)
603 #define DXEPTSIZ_MC_SHIFT 29
604 #define DXEPTSIZ_MC_LIMIT 0x3
605 #define DXEPTSIZ_MC(_x) ((_x) << 29)
606 #define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19)
607 #define DXEPTSIZ_PKTCNT_SHIFT 19
608 #define DXEPTSIZ_PKTCNT_LIMIT 0x3ff
609 #define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
610 #define DXEPTSIZ_PKTCNT(_x) ((_x) << 19)
611 #define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
612 #define DXEPTSIZ_XFERSIZE_SHIFT 0
613 #define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff
614 #define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
615 #define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0)
617 #define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
618 #define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
620 #define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
622 #define PCGCTL HSOTG_REG(0x0e00)
623 #define PCGCTL_IF_DEV_MODE BIT(31)
624 #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
625 #define PCGCTL_P2HD_PRT_SPD_SHIFT 29
626 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
627 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
628 #define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
629 #define PCGCTL_MAC_DEV_ADDR_SHIFT 20
630 #define PCGCTL_MAX_TERMSEL BIT(19)
631 #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
632 #define PCGCTL_MAX_XCVRSELECT_SHIFT 17
633 #define PCGCTL_PORT_POWER BIT(16)
634 #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
635 #define PCGCTL_PRT_CLK_SEL_SHIFT 14
636 #define PCGCTL_ESS_REG_RESTORED BIT(13)
637 #define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
638 #define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
639 #define PCGCTL_ENBL_EXTND_HIBER BIT(10)
640 #define PCGCTL_RESTOREMODE BIT(9)
641 #define PCGCTL_RESETAFTSUSP BIT(8)
642 #define PCGCTL_DEEP_SLEEP BIT(7)
643 #define PCGCTL_PHY_IN_SLEEP BIT(6)
644 #define PCGCTL_ENBL_SLEEP_GATING BIT(5)
645 #define PCGCTL_RSTPDWNMODULE BIT(3)
646 #define PCGCTL_PWRCLMP BIT(2)
647 #define PCGCTL_GATEHCLK BIT(1)
648 #define PCGCTL_STOPPCLK BIT(0)
650 #define PCGCCTL1 HSOTG_REG(0xe04)
651 #define PCGCCTL1_TIMER (0x3 << 1)
652 #define PCGCCTL1_GATEEN BIT(0)
654 #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
656 /* Host Mode Registers */
658 #define HCFG HSOTG_REG(0x0400)
659 #define HCFG_MODECHTIMEN BIT(31)
660 #define HCFG_PERSCHEDENA BIT(26)
661 #define HCFG_FRLISTEN_MASK (0x3 << 24)
662 #define HCFG_FRLISTEN_SHIFT 24
663 #define HCFG_FRLISTEN_8 (0 << 24)
664 #define FRLISTEN_8_SIZE 8
665 #define HCFG_FRLISTEN_16 BIT(24)
666 #define FRLISTEN_16_SIZE 16
667 #define HCFG_FRLISTEN_32 (2 << 24)
668 #define FRLISTEN_32_SIZE 32
669 #define HCFG_FRLISTEN_64 (3 << 24)
670 #define FRLISTEN_64_SIZE 64
671 #define HCFG_DESCDMA BIT(23)
672 #define HCFG_RESVALID_MASK (0xff << 8)
673 #define HCFG_RESVALID_SHIFT 8
674 #define HCFG_ENA32KHZ BIT(7)
675 #define HCFG_FSLSSUPP BIT(2)
676 #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
677 #define HCFG_FSLSPCLKSEL_SHIFT 0
678 #define HCFG_FSLSPCLKSEL_30_60_MHZ 0
679 #define HCFG_FSLSPCLKSEL_48_MHZ 1
680 #define HCFG_FSLSPCLKSEL_6_MHZ 2
682 #define HFIR HSOTG_REG(0x0404)
683 #define HFIR_FRINT_MASK (0xffff << 0)
684 #define HFIR_FRINT_SHIFT 0
685 #define HFIR_RLDCTRL BIT(16)
687 #define HFNUM HSOTG_REG(0x0408)
688 #define HFNUM_FRREM_MASK (0xffff << 16)
689 #define HFNUM_FRREM_SHIFT 16
690 #define HFNUM_FRNUM_MASK (0xffff << 0)
691 #define HFNUM_FRNUM_SHIFT 0
692 #define HFNUM_MAX_FRNUM 0x3fff
694 #define HPTXSTS HSOTG_REG(0x0410)
695 #define TXSTS_QTOP_ODD BIT(31)
696 #define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
697 #define TXSTS_QTOP_CHNEP_SHIFT 27
698 #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
699 #define TXSTS_QTOP_TOKEN_SHIFT 25
700 #define TXSTS_QTOP_TERMINATE BIT(24)
701 #define TXSTS_QSPCAVAIL_MASK (0xff << 16)
702 #define TXSTS_QSPCAVAIL_SHIFT 16
703 #define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
704 #define TXSTS_FSPCAVAIL_SHIFT 0
706 #define HAINT HSOTG_REG(0x0414)
707 #define HAINTMSK HSOTG_REG(0x0418)
708 #define HFLBADDR HSOTG_REG(0x041c)
710 #define HPRT0 HSOTG_REG(0x0440)
711 #define HPRT0_SPD_MASK (0x3 << 17)
712 #define HPRT0_SPD_SHIFT 17
713 #define HPRT0_SPD_HIGH_SPEED 0
714 #define HPRT0_SPD_FULL_SPEED 1
715 #define HPRT0_SPD_LOW_SPEED 2
716 #define HPRT0_TSTCTL_MASK (0xf << 13)
717 #define HPRT0_TSTCTL_SHIFT 13
718 #define HPRT0_PWR BIT(12)
719 #define HPRT0_LNSTS_MASK (0x3 << 10)
720 #define HPRT0_LNSTS_SHIFT 10
721 #define HPRT0_RST BIT(8)
722 #define HPRT0_SUSP BIT(7)
723 #define HPRT0_RES BIT(6)
724 #define HPRT0_OVRCURRCHG BIT(5)
725 #define HPRT0_OVRCURRACT BIT(4)
726 #define HPRT0_ENACHG BIT(3)
727 #define HPRT0_ENA BIT(2)
728 #define HPRT0_CONNDET BIT(1)
729 #define HPRT0_CONNSTS BIT(0)
731 #define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
732 #define HCCHAR_CHENA BIT(31)
733 #define HCCHAR_CHDIS BIT(30)
734 #define HCCHAR_ODDFRM BIT(29)
735 #define HCCHAR_DEVADDR_MASK (0x7f << 22)
736 #define HCCHAR_DEVADDR_SHIFT 22
737 #define HCCHAR_MULTICNT_MASK (0x3 << 20)
738 #define HCCHAR_MULTICNT_SHIFT 20
739 #define HCCHAR_EPTYPE_MASK (0x3 << 18)
740 #define HCCHAR_EPTYPE_SHIFT 18
741 #define HCCHAR_LSPDDEV BIT(17)
742 #define HCCHAR_EPDIR BIT(15)
743 #define HCCHAR_EPNUM_MASK (0xf << 11)
744 #define HCCHAR_EPNUM_SHIFT 11
745 #define HCCHAR_MPS_MASK (0x7ff << 0)
746 #define HCCHAR_MPS_SHIFT 0
748 #define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
749 #define HCSPLT_SPLTENA BIT(31)
750 #define HCSPLT_COMPSPLT BIT(16)
751 #define HCSPLT_XACTPOS_MASK (0x3 << 14)
752 #define HCSPLT_XACTPOS_SHIFT 14
753 #define HCSPLT_XACTPOS_MID 0
754 #define HCSPLT_XACTPOS_END 1
755 #define HCSPLT_XACTPOS_BEGIN 2
756 #define HCSPLT_XACTPOS_ALL 3
757 #define HCSPLT_HUBADDR_MASK (0x7f << 7)
758 #define HCSPLT_HUBADDR_SHIFT 7
759 #define HCSPLT_PRTADDR_MASK (0x7f << 0)
760 #define HCSPLT_PRTADDR_SHIFT 0
762 #define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
763 #define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
764 #define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
765 #define HCINTMSK_FRM_LIST_ROLL BIT(13)
766 #define HCINTMSK_XCS_XACT BIT(12)
767 #define HCINTMSK_BNA BIT(11)
768 #define HCINTMSK_DATATGLERR BIT(10)
769 #define HCINTMSK_FRMOVRUN BIT(9)
770 #define HCINTMSK_BBLERR BIT(8)
771 #define HCINTMSK_XACTERR BIT(7)
772 #define HCINTMSK_NYET BIT(6)
773 #define HCINTMSK_ACK BIT(5)
774 #define HCINTMSK_NAK BIT(4)
775 #define HCINTMSK_STALL BIT(3)
776 #define HCINTMSK_AHBERR BIT(2)
777 #define HCINTMSK_CHHLTD BIT(1)
778 #define HCINTMSK_XFERCOMPL BIT(0)
780 #define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
781 #define TSIZ_DOPNG BIT(31)
782 #define TSIZ_SC_MC_PID_MASK (0x3 << 29)
783 #define TSIZ_SC_MC_PID_SHIFT 29
784 #define TSIZ_SC_MC_PID_DATA0 0
785 #define TSIZ_SC_MC_PID_DATA2 1
786 #define TSIZ_SC_MC_PID_DATA1 2
787 #define TSIZ_SC_MC_PID_MDATA 3
788 #define TSIZ_SC_MC_PID_SETUP 3
789 #define TSIZ_PKTCNT_MASK (0x3ff << 19)
790 #define TSIZ_PKTCNT_SHIFT 19
791 #define TSIZ_NTD_MASK (0xff << 8)
792 #define TSIZ_NTD_SHIFT 8
793 #define TSIZ_SCHINFO_MASK (0xff << 0)
794 #define TSIZ_SCHINFO_SHIFT 0
795 #define TSIZ_XFERSIZE_MASK (0x7ffff << 0)
796 #define TSIZ_XFERSIZE_SHIFT 0
798 #define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch))
800 #define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch))
802 #define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch))
805 * struct dwc2_dma_desc - DMA descriptor structure,
806 * used for both host and gadget modes
808 * @status: DMA descriptor status quadlet
809 * @buf: DMA descriptor data buffer pointer
811 * DMA Descriptor structure contains two quadlets:
812 * Status quadlet and Data buffer pointer.
814 struct dwc2_dma_desc {
819 /* Host Mode DMA descriptor status quadlet */
821 #define HOST_DMA_A BIT(31)
822 #define HOST_DMA_STS_MASK (0x3 << 28)
823 #define HOST_DMA_STS_SHIFT 28
824 #define HOST_DMA_STS_PKTERR BIT(28)
825 #define HOST_DMA_EOL BIT(26)
826 #define HOST_DMA_IOC BIT(25)
827 #define HOST_DMA_SUP BIT(24)
828 #define HOST_DMA_ALT_QTD BIT(23)
829 #define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
830 #define HOST_DMA_QTD_OFFSET_SHIFT 17
831 #define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
832 #define HOST_DMA_ISOC_NBYTES_SHIFT 0
833 #define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
834 #define HOST_DMA_NBYTES_SHIFT 0
835 #define HOST_DMA_NBYTES_LIMIT 131071
837 /* Device Mode DMA descriptor status quadlet */
839 #define DEV_DMA_BUFF_STS_MASK (0x3 << 30)
840 #define DEV_DMA_BUFF_STS_SHIFT 30
841 #define DEV_DMA_BUFF_STS_HREADY 0
842 #define DEV_DMA_BUFF_STS_DMABUSY 1
843 #define DEV_DMA_BUFF_STS_DMADONE 2
844 #define DEV_DMA_BUFF_STS_HBUSY 3
845 #define DEV_DMA_STS_MASK (0x3 << 28)
846 #define DEV_DMA_STS_SHIFT 28
847 #define DEV_DMA_STS_SUCC 0
848 #define DEV_DMA_STS_BUFF_FLUSH 1
849 #define DEV_DMA_STS_BUFF_ERR 3
850 #define DEV_DMA_L BIT(27)
851 #define DEV_DMA_SHORT BIT(26)
852 #define DEV_DMA_IOC BIT(25)
853 #define DEV_DMA_SR BIT(24)
854 #define DEV_DMA_MTRF BIT(23)
855 #define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
856 #define DEV_DMA_ISOC_PID_SHIFT 23
857 #define DEV_DMA_ISOC_PID_DATA0 0
858 #define DEV_DMA_ISOC_PID_DATA2 1
859 #define DEV_DMA_ISOC_PID_DATA1 2
860 #define DEV_DMA_ISOC_PID_MDATA 3
861 #define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12)
862 #define DEV_DMA_ISOC_FRNUM_SHIFT 12
863 #define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0)
864 #define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff
865 #define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0)
866 #define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff
867 #define DEV_DMA_ISOC_NBYTES_SHIFT 0
868 #define DEV_DMA_NBYTES_MASK (0xffff << 0)
869 #define DEV_DMA_NBYTES_SHIFT 0
870 #define DEV_DMA_NBYTES_LIMIT 0xffff
872 #define MAX_DMA_DESC_NUM_GENERIC 64
873 #define MAX_DMA_DESC_NUM_HS_ISOC 256
875 #endif /* __DWC2_HW_H__ */