2 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
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19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the interrupt handlers for Host mode
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/spinlock.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
47 #include <linux/usb.h>
49 #include <linux/usb/hcd.h>
50 #include <linux/usb/ch11.h>
55 /* This function is for debug only */
56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
58 u16 curr_frame_number = hsotg->frame_number;
59 u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
61 if (expected != curr_frame_number)
62 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
63 expected, curr_frame_number);
65 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
66 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
67 if (expected != curr_frame_number) {
68 hsotg->frame_num_array[hsotg->frame_num_idx] =
70 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
71 hsotg->last_frame_num;
72 hsotg->frame_num_idx++;
74 } else if (!hsotg->dumped_frame_num_array) {
77 dev_info(hsotg->dev, "Frame Last Frame\n");
78 dev_info(hsotg->dev, "----- ----------\n");
79 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
80 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
81 hsotg->frame_num_array[i],
82 hsotg->last_frame_num_array[i]);
84 hsotg->dumped_frame_num_array = 1;
87 hsotg->last_frame_num = curr_frame_number;
90 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
91 struct dwc2_host_chan *chan,
94 struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
100 if (chan->qh->dev_speed == USB_SPEED_HIGH)
106 usb_urb = qtd->urb->priv;
107 if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
111 * The root hub doesn't really have a TT, but Linux thinks it
112 * does because how could you have a "high speed hub" that
113 * directly talks directly to low speed devices without a TT?
114 * It's all lies. Lies, I tell you.
116 if (usb_urb->dev->tt->hub == root_hub)
119 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
120 chan->qh->tt_buffer_dirty = 1;
121 if (usb_hub_clear_tt_buffer(usb_urb))
122 /* Clear failed; let's hope things work anyway */
123 chan->qh->tt_buffer_dirty = 0;
128 * Handles the start-of-frame interrupt in host mode. Non-periodic
129 * transactions may be queued to the DWC_otg controller for the current
130 * (micro)frame. Periodic transactions may be queued to the controller
131 * for the next (micro)frame.
133 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
135 struct list_head *qh_entry;
137 enum dwc2_transaction_type tr_type;
139 /* Clear interrupt */
140 dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
143 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
146 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
148 dwc2_track_missed_sofs(hsotg);
150 /* Determine whether any periodic QHs should be executed */
151 qh_entry = hsotg->periodic_sched_inactive.next;
152 while (qh_entry != &hsotg->periodic_sched_inactive) {
153 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
154 qh_entry = qh_entry->next;
155 if (dwc2_frame_num_le(qh->next_active_frame,
156 hsotg->frame_number)) {
157 dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
158 qh, hsotg->frame_number,
159 qh->next_active_frame);
162 * Move QH to the ready list to be executed next
165 list_move_tail(&qh->qh_list_entry,
166 &hsotg->periodic_sched_ready);
169 tr_type = dwc2_hcd_select_transactions(hsotg);
170 if (tr_type != DWC2_TRANSACTION_NONE)
171 dwc2_hcd_queue_transactions(hsotg, tr_type);
175 * Handles the Rx FIFO Level Interrupt, which indicates that there is
176 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
177 * memory if the DWC_otg controller is operating in Slave mode.
179 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
181 u32 grxsts, chnum, bcnt, dpid, pktsts;
182 struct dwc2_host_chan *chan;
185 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
187 grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
188 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
189 chan = hsotg->hc_ptr_array[chnum];
191 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
195 bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
196 dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
197 pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
201 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
202 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
203 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
204 chan->data_pid_start);
205 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
209 case GRXSTS_PKTSTS_HCHIN:
210 /* Read the data into the host buffer */
212 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
214 /* Update the HC fields for the next packet received */
215 chan->xfer_count += bcnt;
216 chan->xfer_buf += bcnt;
219 case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
220 case GRXSTS_PKTSTS_DATATOGGLEERR:
221 case GRXSTS_PKTSTS_HCHHALTED:
222 /* Handled in interrupt, just ignore data */
226 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
232 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
233 * data packets may be written to the FIFO for OUT transfers. More requests
234 * may be written to the non-periodic request queue for IN transfers. This
235 * interrupt is enabled only in Slave mode.
237 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
239 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
240 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
244 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
245 * packets may be written to the FIFO for OUT transfers. More requests may be
246 * written to the periodic request queue for IN transfers. This interrupt is
247 * enabled only in Slave mode.
249 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
252 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
253 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
256 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
259 struct dwc2_core_params *params = hsotg->core_params;
267 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
269 /* Every time when port enables calculate HFIR.FrInterval */
270 hfir = dwc2_readl(hsotg->regs + HFIR);
271 hfir &= ~HFIR_FRINT_MASK;
272 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
274 dwc2_writel(hfir, hsotg->regs + HFIR);
276 /* Check if we need to adjust the PHY clock speed for low power */
277 if (!params->host_support_fs_ls_low_power) {
278 /* Port has been enabled, set the reset change flag */
279 hsotg->flags.b.port_reset_change = 1;
283 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
284 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
286 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
288 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
289 /* Set PHY low power clock select for FS/LS devices */
290 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
291 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
295 hcfg = dwc2_readl(hsotg->regs + HCFG);
296 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
297 HCFG_FSLSPCLKSEL_SHIFT;
299 if (prtspd == HPRT0_SPD_LOW_SPEED &&
300 params->host_ls_low_power_phy_clk ==
301 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
304 "FS_PHY programming HCFG to 6 MHz\n");
305 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
306 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
307 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
308 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
309 dwc2_writel(hcfg, hsotg->regs + HCFG);
315 "FS_PHY programming HCFG to 48 MHz\n");
316 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
317 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
318 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
319 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
320 dwc2_writel(hcfg, hsotg->regs + HCFG);
326 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
327 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
328 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
334 *hprt0_modify |= HPRT0_RST;
335 dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0);
336 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
337 msecs_to_jiffies(60));
339 /* Port has been enabled, set the reset change flag */
340 hsotg->flags.b.port_reset_change = 1;
345 * There are multiple conditions that can cause a port interrupt. This function
346 * determines which interrupt conditions have occurred and handles them
349 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
354 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
356 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
357 hprt0_modify = hprt0;
360 * Clear appropriate bits in HPRT0 to clear the interrupt bit in
363 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
367 * Port Connect Detected
368 * Set flag and clear if detected
370 if (hprt0 & HPRT0_CONNDET) {
371 dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0);
374 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
376 dwc2_hcd_connect(hsotg);
379 * The Hub driver asserts a reset when it sees port connect
385 * Port Enable Changed
386 * Clear if detected - Set internal flag if disabled
388 if (hprt0 & HPRT0_ENACHG) {
389 dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0);
391 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
392 hprt0, !!(hprt0 & HPRT0_ENA));
393 if (hprt0 & HPRT0_ENA) {
394 hsotg->new_connection = true;
395 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
397 hsotg->flags.b.port_enable_change = 1;
398 if (hsotg->core_params->dma_desc_fs_enable) {
401 hsotg->core_params->dma_desc_enable = 0;
402 hsotg->new_connection = false;
403 hcfg = dwc2_readl(hsotg->regs + HCFG);
404 hcfg &= ~HCFG_DESCDMA;
405 dwc2_writel(hcfg, hsotg->regs + HCFG);
410 /* Overcurrent Change Interrupt */
411 if (hprt0 & HPRT0_OVRCURRCHG) {
412 dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG,
413 hsotg->regs + HPRT0);
415 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
417 hsotg->flags.b.port_over_current_change = 1;
422 * Gets the actual length of a transfer after the transfer halts. halt_status
423 * holds the reason for the halt.
425 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
426 * is set to 1 upon return if less than the requested number of bytes were
427 * transferred. short_read may also be NULL on entry, in which case it remains
430 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
431 struct dwc2_host_chan *chan, int chnum,
432 struct dwc2_qtd *qtd,
433 enum dwc2_halt_status halt_status,
436 u32 hctsiz, count, length;
438 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
440 if (halt_status == DWC2_HC_XFER_COMPLETE) {
441 if (chan->ep_is_in) {
442 count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
444 length = chan->xfer_len - count;
445 if (short_read != NULL)
446 *short_read = (count != 0);
447 } else if (chan->qh->do_split) {
448 length = qtd->ssplit_out_xfer_count;
450 length = chan->xfer_len;
454 * Must use the hctsiz.pktcnt field to determine how much data
455 * has been transferred. This field reflects the number of
456 * packets that have been transferred via the USB. This is
457 * always an integral number of packets if the transfer was
458 * halted before its normal completion. (Can't use the
459 * hctsiz.xfersize field because that reflects the number of
460 * bytes transferred via the AHB, not the USB).
462 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
463 length = (chan->start_pkt_count - count) * chan->max_packet;
470 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
471 * Complete interrupt on the host channel. Updates the actual_length field
472 * of the URB based on the number of bytes transferred via the host channel.
473 * Sets the URB status if the data transfer is finished.
475 * Return: 1 if the data transfer specified by the URB is completely finished,
478 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
479 struct dwc2_host_chan *chan, int chnum,
480 struct dwc2_hcd_urb *urb,
481 struct dwc2_qtd *qtd)
486 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
487 DWC2_HC_XFER_COMPLETE,
490 if (urb->actual_length + xfer_length > urb->length) {
491 dev_dbg(hsotg->dev, "%s(): trimming xfer length\n", __func__);
492 xfer_length = urb->length - urb->actual_length;
495 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
496 urb->actual_length, xfer_length);
497 urb->actual_length += xfer_length;
499 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
500 (urb->flags & URB_SEND_ZERO_PACKET) &&
501 urb->actual_length >= urb->length &&
502 !(urb->length % chan->max_packet)) {
504 } else if (short_read || urb->actual_length >= urb->length) {
509 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
510 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
511 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
512 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
513 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
514 (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
515 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
516 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
517 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
524 * Save the starting data toggle for the next transfer. The data toggle is
525 * saved in the QH for non-control transfers and it's saved in the QTD for
528 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
529 struct dwc2_host_chan *chan, int chnum,
530 struct dwc2_qtd *qtd)
532 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
533 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
535 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
536 if (WARN(!chan || !chan->qh,
537 "chan->qh must be specified for non-control eps\n"))
540 if (pid == TSIZ_SC_MC_PID_DATA0)
541 chan->qh->data_toggle = DWC2_HC_PID_DATA0;
543 chan->qh->data_toggle = DWC2_HC_PID_DATA1;
546 "qtd must be specified for control eps\n"))
549 if (pid == TSIZ_SC_MC_PID_DATA0)
550 qtd->data_toggle = DWC2_HC_PID_DATA0;
552 qtd->data_toggle = DWC2_HC_PID_DATA1;
557 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
558 * the transfer is stopped for any reason. The fields of the current entry in
559 * the frame descriptor array are set based on the transfer state and the input
560 * halt_status. Completes the Isochronous URB if all the URB frames have been
563 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
564 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
566 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
567 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
568 int chnum, struct dwc2_qtd *qtd,
569 enum dwc2_halt_status halt_status)
571 struct dwc2_hcd_iso_packet_desc *frame_desc;
572 struct dwc2_hcd_urb *urb = qtd->urb;
575 return DWC2_HC_XFER_NO_HALT_STATUS;
577 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
579 switch (halt_status) {
580 case DWC2_HC_XFER_COMPLETE:
581 frame_desc->status = 0;
582 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
583 chan, chnum, qtd, halt_status, NULL);
585 case DWC2_HC_XFER_FRAME_OVERRUN:
588 frame_desc->status = -ENOSR;
590 frame_desc->status = -ECOMM;
591 frame_desc->actual_length = 0;
593 case DWC2_HC_XFER_BABBLE_ERR:
595 frame_desc->status = -EOVERFLOW;
596 /* Don't need to update actual_length in this case */
598 case DWC2_HC_XFER_XACT_ERR:
600 frame_desc->status = -EPROTO;
601 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
602 chan, chnum, qtd, halt_status, NULL);
604 /* Skip whole frame */
605 if (chan->qh->do_split &&
606 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
607 hsotg->core_params->dma_enable > 0) {
608 qtd->complete_split = 0;
609 qtd->isoc_split_offset = 0;
614 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
619 if (++qtd->isoc_frame_index == urb->packet_count) {
621 * urb->status is not used for isoc transfers. The individual
622 * frame_desc statuses are used instead.
624 dwc2_host_complete(hsotg, qtd, 0);
625 halt_status = DWC2_HC_XFER_URB_COMPLETE;
627 halt_status = DWC2_HC_XFER_COMPLETE;
634 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
635 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
636 * still linked to the QH, the QH is added to the end of the inactive
637 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
638 * schedule if no more QTDs are linked to the QH.
640 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
643 int continue_split = 0;
644 struct dwc2_qtd *qtd;
647 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
648 hsotg, qh, free_qtd);
650 if (list_empty(&qh->qtd_list)) {
651 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
655 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
657 if (qtd->complete_split)
659 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
660 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
664 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
670 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
674 * dwc2_release_channel() - Releases a host channel for use by other transfers
676 * @hsotg: The HCD state structure
677 * @chan: The host channel to release
678 * @qtd: The QTD associated with the host channel. This QTD may be
679 * freed if the transfer is complete or an error has occurred.
680 * @halt_status: Reason the channel is being released. This status
681 * determines the actions taken by this function.
683 * Also attempts to select and queue more transactions since at least one host
684 * channel is available.
686 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
687 struct dwc2_host_chan *chan,
688 struct dwc2_qtd *qtd,
689 enum dwc2_halt_status halt_status)
691 enum dwc2_transaction_type tr_type;
696 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
697 __func__, chan->hc_num, halt_status);
699 switch (halt_status) {
700 case DWC2_HC_XFER_URB_COMPLETE:
703 case DWC2_HC_XFER_AHB_ERR:
704 case DWC2_HC_XFER_STALL:
705 case DWC2_HC_XFER_BABBLE_ERR:
708 case DWC2_HC_XFER_XACT_ERR:
709 if (qtd && qtd->error_count >= 3) {
711 " Complete URB with transaction error\n");
713 dwc2_host_complete(hsotg, qtd, -EPROTO);
716 case DWC2_HC_XFER_URB_DEQUEUE:
718 * The QTD has already been removed and the QH has been
719 * deactivated. Don't want to do anything except release the
720 * host channel and try to queue more transfers.
723 case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
724 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
726 dwc2_host_complete(hsotg, qtd, -EIO);
728 case DWC2_HC_XFER_NO_HALT_STATUS:
733 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
737 * Release the host channel for use by other transfers. The cleanup
738 * function clears the channel interrupt enables and conditions, so
739 * there's no need to clear the Channel Halted interrupt separately.
741 if (!list_empty(&chan->hc_list_entry))
742 list_del(&chan->hc_list_entry);
743 dwc2_hc_cleanup(hsotg, chan);
744 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
746 if (hsotg->core_params->uframe_sched > 0) {
747 hsotg->available_host_channels++;
749 switch (chan->ep_type) {
750 case USB_ENDPOINT_XFER_CONTROL:
751 case USB_ENDPOINT_XFER_BULK:
752 hsotg->non_periodic_channels--;
756 * Don't release reservations for periodic channels
757 * here. That's done when a periodic transfer is
758 * descheduled (i.e. when the QH is removed from the
759 * periodic schedule).
765 haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
766 haintmsk &= ~(1 << chan->hc_num);
767 dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
769 /* Try to queue more transfers now that there's a free channel */
770 tr_type = dwc2_hcd_select_transactions(hsotg);
771 if (tr_type != DWC2_TRANSACTION_NONE)
772 dwc2_hcd_queue_transactions(hsotg, tr_type);
776 * Halts a host channel. If the channel cannot be halted immediately because
777 * the request queue is full, this function ensures that the FIFO empty
778 * interrupt for the appropriate queue is enabled so that the halt request can
779 * be queued when there is space in the request queue.
781 * This function may also be called in DMA mode. In that case, the channel is
782 * simply released since the core always halts the channel automatically in
785 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
786 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
787 enum dwc2_halt_status halt_status)
790 dev_vdbg(hsotg->dev, "%s()\n", __func__);
792 if (hsotg->core_params->dma_enable > 0) {
794 dev_vdbg(hsotg->dev, "DMA enabled\n");
795 dwc2_release_channel(hsotg, chan, qtd, halt_status);
799 /* Slave mode processing */
800 dwc2_hc_halt(hsotg, chan, halt_status);
802 if (chan->halt_on_queue) {
805 dev_vdbg(hsotg->dev, "Halt on queue\n");
806 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
807 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
808 dev_vdbg(hsotg->dev, "control/bulk\n");
810 * Make sure the Non-periodic Tx FIFO empty interrupt
811 * is enabled so that the non-periodic schedule will
814 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
815 gintmsk |= GINTSTS_NPTXFEMP;
816 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
818 dev_vdbg(hsotg->dev, "isoc/intr\n");
820 * Move the QH from the periodic queued schedule to
821 * the periodic assigned schedule. This allows the
822 * halt to be queued when the periodic schedule is
825 list_move_tail(&chan->qh->qh_list_entry,
826 &hsotg->periodic_sched_assigned);
829 * Make sure the Periodic Tx FIFO Empty interrupt is
830 * enabled so that the periodic schedule will be
833 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
834 gintmsk |= GINTSTS_PTXFEMP;
835 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
841 * Performs common cleanup for non-periodic transfers after a Transfer
842 * Complete interrupt. This function should be called after any endpoint type
843 * specific handling is finished to release the host channel.
845 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
846 struct dwc2_host_chan *chan,
847 int chnum, struct dwc2_qtd *qtd,
848 enum dwc2_halt_status halt_status)
850 dev_vdbg(hsotg->dev, "%s()\n", __func__);
852 qtd->error_count = 0;
854 if (chan->hcint & HCINTMSK_NYET) {
856 * Got a NYET on the last transaction of the transfer. This
857 * means that the endpoint should be in the PING state at the
858 * beginning of the next transfer.
860 dev_vdbg(hsotg->dev, "got NYET\n");
861 chan->qh->ping_state = 1;
865 * Always halt and release the host channel to make it available for
866 * more transfers. There may still be more phases for a control
867 * transfer or more data packets for a bulk transfer at this point,
868 * but the host channel is still halted. A channel will be reassigned
869 * to the transfer when the non-periodic schedule is processed after
870 * the channel is released. This allows transactions to be queued
871 * properly via dwc2_hcd_queue_transactions, which also enables the
872 * Tx FIFO Empty interrupt if necessary.
874 if (chan->ep_is_in) {
876 * IN transfers in Slave mode require an explicit disable to
877 * halt the channel. (In DMA mode, this call simply releases
880 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
883 * The channel is automatically disabled by the core for OUT
884 * transfers in Slave mode
886 dwc2_release_channel(hsotg, chan, qtd, halt_status);
891 * Performs common cleanup for periodic transfers after a Transfer Complete
892 * interrupt. This function should be called after any endpoint type specific
893 * handling is finished to release the host channel.
895 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
896 struct dwc2_host_chan *chan, int chnum,
897 struct dwc2_qtd *qtd,
898 enum dwc2_halt_status halt_status)
900 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
902 qtd->error_count = 0;
904 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
905 /* Core halts channel in these cases */
906 dwc2_release_channel(hsotg, chan, qtd, halt_status);
908 /* Flush any outstanding requests from the Tx queue */
909 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
912 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
913 struct dwc2_host_chan *chan, int chnum,
914 struct dwc2_qtd *qtd)
916 struct dwc2_hcd_iso_packet_desc *frame_desc;
922 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
923 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
924 DWC2_HC_XFER_COMPLETE, NULL);
925 if (!len && !qtd->isoc_split_offset) {
926 qtd->complete_split = 0;
930 frame_desc->actual_length += len;
932 qtd->isoc_split_offset += len;
934 if (frame_desc->actual_length >= frame_desc->length) {
935 frame_desc->status = 0;
936 qtd->isoc_frame_index++;
937 qtd->complete_split = 0;
938 qtd->isoc_split_offset = 0;
941 if (qtd->isoc_frame_index == qtd->urb->packet_count) {
942 dwc2_host_complete(hsotg, qtd, 0);
943 dwc2_release_channel(hsotg, chan, qtd,
944 DWC2_HC_XFER_URB_COMPLETE);
946 dwc2_release_channel(hsotg, chan, qtd,
947 DWC2_HC_XFER_NO_HALT_STATUS);
950 return 1; /* Indicates that channel released */
954 * Handles a host channel Transfer Complete interrupt. This handler may be
955 * called in either DMA mode or Slave mode.
957 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
958 struct dwc2_host_chan *chan, int chnum,
959 struct dwc2_qtd *qtd)
961 struct dwc2_hcd_urb *urb = qtd->urb;
962 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
968 "--Host Channel %d Interrupt: Transfer Complete--\n",
972 goto handle_xfercomp_done;
974 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
976 if (hsotg->core_params->dma_desc_enable > 0) {
977 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
978 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
979 /* Do not disable the interrupt, just clear it */
981 goto handle_xfercomp_done;
984 /* Handle xfer complete on CSPLIT */
985 if (chan->qh->do_split) {
986 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
987 hsotg->core_params->dma_enable > 0) {
988 if (qtd->complete_split &&
989 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
991 goto handle_xfercomp_done;
993 qtd->complete_split = 0;
997 /* Update the QTD and URB states */
999 case USB_ENDPOINT_XFER_CONTROL:
1000 switch (qtd->control_phase) {
1001 case DWC2_CONTROL_SETUP:
1002 if (urb->length > 0)
1003 qtd->control_phase = DWC2_CONTROL_DATA;
1005 qtd->control_phase = DWC2_CONTROL_STATUS;
1006 dev_vdbg(hsotg->dev,
1007 " Control setup transaction done\n");
1008 halt_status = DWC2_HC_XFER_COMPLETE;
1010 case DWC2_CONTROL_DATA:
1011 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1013 if (urb_xfer_done) {
1014 qtd->control_phase = DWC2_CONTROL_STATUS;
1015 dev_vdbg(hsotg->dev,
1016 " Control data transfer done\n");
1018 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1021 halt_status = DWC2_HC_XFER_COMPLETE;
1023 case DWC2_CONTROL_STATUS:
1024 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1025 if (urb->status == -EINPROGRESS)
1027 dwc2_host_complete(hsotg, qtd, urb->status);
1028 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1032 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1035 case USB_ENDPOINT_XFER_BULK:
1036 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1037 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1039 if (urb_xfer_done) {
1040 dwc2_host_complete(hsotg, qtd, urb->status);
1041 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1043 halt_status = DWC2_HC_XFER_COMPLETE;
1046 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1047 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1050 case USB_ENDPOINT_XFER_INT:
1051 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1052 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1056 * Interrupt URB is done on the first transfer complete
1059 if (urb_xfer_done) {
1060 dwc2_host_complete(hsotg, qtd, urb->status);
1061 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1063 halt_status = DWC2_HC_XFER_COMPLETE;
1066 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1067 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1070 case USB_ENDPOINT_XFER_ISOC:
1072 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1073 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1074 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1075 chnum, qtd, DWC2_HC_XFER_COMPLETE);
1076 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1081 handle_xfercomp_done:
1082 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1086 * Handles a host channel STALL interrupt. This handler may be called in
1087 * either DMA mode or Slave mode.
1089 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1090 struct dwc2_host_chan *chan, int chnum,
1091 struct dwc2_qtd *qtd)
1093 struct dwc2_hcd_urb *urb = qtd->urb;
1096 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1099 if (hsotg->core_params->dma_desc_enable > 0) {
1100 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1101 DWC2_HC_XFER_STALL);
1102 goto handle_stall_done;
1106 goto handle_stall_halt;
1108 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1110 if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1111 dwc2_host_complete(hsotg, qtd, -EPIPE);
1113 if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1114 pipe_type == USB_ENDPOINT_XFER_INT) {
1115 dwc2_host_complete(hsotg, qtd, -EPIPE);
1117 * USB protocol requires resetting the data toggle for bulk
1118 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1119 * setup command is issued to the endpoint. Anticipate the
1120 * CLEAR_FEATURE command since a STALL has occurred and reset
1121 * the data toggle now.
1123 chan->qh->data_toggle = 0;
1127 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1130 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1134 * Updates the state of the URB when a transfer has been stopped due to an
1135 * abnormal condition before the transfer completes. Modifies the
1136 * actual_length field of the URB to reflect the number of bytes that have
1137 * actually been transferred via the host channel.
1139 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1140 struct dwc2_host_chan *chan, int chnum,
1141 struct dwc2_hcd_urb *urb,
1142 struct dwc2_qtd *qtd,
1143 enum dwc2_halt_status halt_status)
1145 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1146 qtd, halt_status, NULL);
1149 if (urb->actual_length + xfer_length > urb->length) {
1150 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1151 xfer_length = urb->length - urb->actual_length;
1154 urb->actual_length += xfer_length;
1156 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1157 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1158 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1159 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1160 chan->start_pkt_count);
1161 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1162 (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1163 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1164 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1166 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1167 urb->actual_length);
1168 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1173 * Handles a host channel NAK interrupt. This handler may be called in either
1174 * DMA mode or Slave mode.
1176 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1177 struct dwc2_host_chan *chan, int chnum,
1178 struct dwc2_qtd *qtd)
1181 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1186 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1191 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1195 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1196 * interrupt. Re-start the SSPLIT transfer.
1198 if (chan->do_split) {
1199 if (chan->complete_split)
1200 qtd->error_count = 0;
1201 qtd->complete_split = 0;
1202 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1203 goto handle_nak_done;
1206 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1207 case USB_ENDPOINT_XFER_CONTROL:
1208 case USB_ENDPOINT_XFER_BULK:
1209 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1211 * NAK interrupts are enabled on bulk/control IN
1212 * transfers in DMA mode for the sole purpose of
1213 * resetting the error count after a transaction error
1214 * occurs. The core will continue transferring data.
1216 qtd->error_count = 0;
1221 * NAK interrupts normally occur during OUT transfers in DMA
1222 * or Slave mode. For IN transfers, more requests will be
1223 * queued as request queue space is available.
1225 qtd->error_count = 0;
1227 if (!chan->qh->ping_state) {
1228 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1229 qtd, DWC2_HC_XFER_NAK);
1230 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1232 if (chan->speed == USB_SPEED_HIGH)
1233 chan->qh->ping_state = 1;
1237 * Halt the channel so the transfer can be re-started from
1238 * the appropriate point or the PING protocol will
1241 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1243 case USB_ENDPOINT_XFER_INT:
1244 qtd->error_count = 0;
1245 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1247 case USB_ENDPOINT_XFER_ISOC:
1248 /* Should never get called for isochronous transfers */
1249 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1254 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1258 * Handles a host channel ACK interrupt. This interrupt is enabled when
1259 * performing the PING protocol in Slave mode, when errors occur during
1260 * either Slave mode or DMA mode, and during Start Split transactions.
1262 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1263 struct dwc2_host_chan *chan, int chnum,
1264 struct dwc2_qtd *qtd)
1266 struct dwc2_hcd_iso_packet_desc *frame_desc;
1269 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1272 if (chan->do_split) {
1273 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1274 if (!chan->ep_is_in &&
1275 chan->data_pid_start != DWC2_HC_PID_SETUP)
1276 qtd->ssplit_out_xfer_count = chan->xfer_len;
1278 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1279 qtd->complete_split = 1;
1280 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1283 switch (chan->xact_pos) {
1284 case DWC2_HCSPLT_XACTPOS_ALL:
1286 case DWC2_HCSPLT_XACTPOS_END:
1287 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1288 qtd->isoc_split_offset = 0;
1290 case DWC2_HCSPLT_XACTPOS_BEGIN:
1291 case DWC2_HCSPLT_XACTPOS_MID:
1293 * For BEGIN or MID, calculate the length for
1294 * the next microframe to determine the correct
1295 * SSPLIT token, either MID or END
1297 frame_desc = &qtd->urb->iso_descs[
1298 qtd->isoc_frame_index];
1299 qtd->isoc_split_offset += 188;
1301 if (frame_desc->length - qtd->isoc_split_offset
1303 qtd->isoc_split_pos =
1304 DWC2_HCSPLT_XACTPOS_END;
1306 qtd->isoc_split_pos =
1307 DWC2_HCSPLT_XACTPOS_MID;
1312 qtd->error_count = 0;
1314 if (chan->qh->ping_state) {
1315 chan->qh->ping_state = 0;
1317 * Halt the channel so the transfer can be re-started
1318 * from the appropriate point. This only happens in
1319 * Slave mode. In DMA mode, the ping_state is cleared
1320 * when the transfer is started because the core
1321 * automatically executes the PING, then the transfer.
1323 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1328 * If the ACK occurred when _not_ in the PING state, let the channel
1329 * continue transferring data after clearing the error count
1331 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1335 * Handles a host channel NYET interrupt. This interrupt should only occur on
1336 * Bulk and Control OUT endpoints and for complete split transactions. If a
1337 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1338 * handled in the xfercomp interrupt handler, not here. This handler may be
1339 * called in either DMA mode or Slave mode.
1341 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1342 struct dwc2_host_chan *chan, int chnum,
1343 struct dwc2_qtd *qtd)
1346 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1351 * re-do the CSPLIT immediately on non-periodic
1353 if (chan->do_split && chan->complete_split) {
1354 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1355 hsotg->core_params->dma_enable > 0) {
1356 qtd->complete_split = 0;
1357 qtd->isoc_split_offset = 0;
1358 qtd->isoc_frame_index++;
1360 qtd->isoc_frame_index == qtd->urb->packet_count) {
1361 dwc2_host_complete(hsotg, qtd, 0);
1362 dwc2_release_channel(hsotg, chan, qtd,
1363 DWC2_HC_XFER_URB_COMPLETE);
1365 dwc2_release_channel(hsotg, chan, qtd,
1366 DWC2_HC_XFER_NO_HALT_STATUS);
1368 goto handle_nyet_done;
1371 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1372 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1373 struct dwc2_qh *qh = chan->qh;
1376 if (hsotg->core_params->uframe_sched <= 0) {
1377 int frnum = dwc2_hcd_get_frame_number(hsotg);
1379 /* Don't have num_hs_transfers; simple logic */
1380 past_end = dwc2_full_frame_num(frnum) !=
1381 dwc2_full_frame_num(qh->next_active_frame);
1386 * Figure out the end frame based on schedule.
1388 * We don't want to go on trying again and again
1389 * forever. Let's stop when we've done all the
1390 * transfers that were scheduled.
1392 * We're going to be comparing start_active_frame
1393 * and next_active_frame, both of which are 1
1394 * before the time the packet goes on the wire,
1395 * so that cancels out. Basically if had 1
1396 * transfer and we saw 1 NYET then we're done.
1397 * We're getting a NYET here so if next >=
1398 * (start + num_transfers) we're done. The
1399 * complexity is that for all but ISOC_OUT we
1402 end_frnum = dwc2_frame_num_inc(
1403 qh->start_active_frame,
1404 qh->num_hs_transfers);
1406 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
1409 dwc2_frame_num_inc(end_frnum, 1);
1411 past_end = dwc2_frame_num_le(
1412 end_frnum, qh->next_active_frame);
1416 /* Treat this as a transaction error. */
1419 * Todo: Fix system performance so this can
1420 * be treated as an error. Right now complete
1421 * splits cannot be scheduled precisely enough
1422 * due to other system activity, so this error
1423 * occurs regularly in Slave mode.
1427 qtd->complete_split = 0;
1428 dwc2_halt_channel(hsotg, chan, qtd,
1429 DWC2_HC_XFER_XACT_ERR);
1430 /* Todo: add support for isoc release */
1431 goto handle_nyet_done;
1435 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1436 goto handle_nyet_done;
1439 chan->qh->ping_state = 1;
1440 qtd->error_count = 0;
1442 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1444 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1447 * Halt the channel and re-start the transfer so the PING protocol
1450 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1453 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1457 * Handles a host channel babble interrupt. This handler may be called in
1458 * either DMA mode or Slave mode.
1460 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1461 struct dwc2_host_chan *chan, int chnum,
1462 struct dwc2_qtd *qtd)
1464 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1467 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1469 if (hsotg->core_params->dma_desc_enable > 0) {
1470 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1471 DWC2_HC_XFER_BABBLE_ERR);
1475 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1476 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1477 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1479 enum dwc2_halt_status halt_status;
1481 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1482 qtd, DWC2_HC_XFER_BABBLE_ERR);
1483 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1487 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1491 * Handles a host channel AHB error interrupt. This handler is only called in
1494 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1495 struct dwc2_host_chan *chan, int chnum,
1496 struct dwc2_qtd *qtd)
1498 struct dwc2_hcd_urb *urb = qtd->urb;
1499 char *pipetype, *speed;
1505 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1509 goto handle_ahberr_halt;
1511 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1513 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1514 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1515 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1516 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1518 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1519 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1520 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1521 dev_err(hsotg->dev, " Device address: %d\n",
1522 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1523 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1524 dwc2_hcd_get_ep_num(&urb->pipe_info),
1525 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1527 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1528 case USB_ENDPOINT_XFER_CONTROL:
1529 pipetype = "CONTROL";
1531 case USB_ENDPOINT_XFER_BULK:
1534 case USB_ENDPOINT_XFER_INT:
1535 pipetype = "INTERRUPT";
1537 case USB_ENDPOINT_XFER_ISOC:
1538 pipetype = "ISOCHRONOUS";
1541 pipetype = "UNKNOWN";
1545 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1547 switch (chan->speed) {
1548 case USB_SPEED_HIGH:
1551 case USB_SPEED_FULL:
1562 dev_err(hsotg->dev, " Speed: %s\n", speed);
1564 dev_err(hsotg->dev, " Max packet size: %d\n",
1565 dwc2_hcd_get_mps(&urb->pipe_info));
1566 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1567 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1568 urb->buf, (unsigned long)urb->dma);
1569 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1570 urb->setup_packet, (unsigned long)urb->setup_dma);
1571 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1573 /* Core halts the channel for Descriptor DMA mode */
1574 if (hsotg->core_params->dma_desc_enable > 0) {
1575 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1576 DWC2_HC_XFER_AHB_ERR);
1577 goto handle_ahberr_done;
1580 dwc2_host_complete(hsotg, qtd, -EIO);
1584 * Force a channel halt. Don't call dwc2_halt_channel because that won't
1585 * write to the HCCHARn register in DMA mode to force the halt.
1587 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1590 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1594 * Handles a host channel transaction error interrupt. This handler may be
1595 * called in either DMA mode or Slave mode.
1597 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1598 struct dwc2_host_chan *chan, int chnum,
1599 struct dwc2_qtd *qtd)
1602 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1604 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1606 if (hsotg->core_params->dma_desc_enable > 0) {
1607 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1608 DWC2_HC_XFER_XACT_ERR);
1609 goto handle_xacterr_done;
1612 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1613 case USB_ENDPOINT_XFER_CONTROL:
1614 case USB_ENDPOINT_XFER_BULK:
1616 if (!chan->qh->ping_state) {
1618 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1619 qtd, DWC2_HC_XFER_XACT_ERR);
1620 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1621 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1622 chan->qh->ping_state = 1;
1626 * Halt the channel so the transfer can be re-started from
1627 * the appropriate point or the PING protocol will start
1629 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1631 case USB_ENDPOINT_XFER_INT:
1633 if (chan->do_split && chan->complete_split)
1634 qtd->complete_split = 0;
1635 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1637 case USB_ENDPOINT_XFER_ISOC:
1639 enum dwc2_halt_status halt_status;
1641 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1642 chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1643 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1648 handle_xacterr_done:
1649 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1653 * Handles a host channel frame overrun interrupt. This handler may be called
1654 * in either DMA mode or Slave mode.
1656 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1657 struct dwc2_host_chan *chan, int chnum,
1658 struct dwc2_qtd *qtd)
1660 enum dwc2_halt_status halt_status;
1663 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1666 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1668 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1669 case USB_ENDPOINT_XFER_CONTROL:
1670 case USB_ENDPOINT_XFER_BULK:
1672 case USB_ENDPOINT_XFER_INT:
1673 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1675 case USB_ENDPOINT_XFER_ISOC:
1676 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1677 qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1678 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1682 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1686 * Handles a host channel data toggle error interrupt. This handler may be
1687 * called in either DMA mode or Slave mode.
1689 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1690 struct dwc2_host_chan *chan, int chnum,
1691 struct dwc2_qtd *qtd)
1694 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1697 qtd->error_count = 0;
1700 "Data Toggle Error on OUT transfer, channel %d\n",
1703 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1704 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1708 * For debug only. It checks that a valid halt status is set and that
1709 * HCCHARn.chdis is clear. If there's a problem, corrective action is
1710 * taken and a warning is issued.
1712 * Return: true if halt status is ok, false otherwise
1714 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1715 struct dwc2_host_chan *chan, int chnum,
1716 struct dwc2_qtd *qtd)
1724 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1726 * This code is here only as a check. This condition should
1727 * never happen. Ignore the halt if it does occur.
1729 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1730 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1731 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1732 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1734 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1737 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1738 chnum, hcchar, hctsiz);
1740 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1741 chan->hcint, hcintmsk, hcsplt);
1743 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1744 qtd->complete_split);
1745 dev_warn(hsotg->dev,
1746 "%s: no halt status, channel %d, ignoring interrupt\n",
1752 * This code is here only as a check. hcchar.chdis should never be set
1753 * when the halt interrupt occurs. Halt the channel again if it does
1756 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1757 if (hcchar & HCCHAR_CHDIS) {
1758 dev_warn(hsotg->dev,
1759 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1761 chan->halt_pending = 0;
1762 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1771 * Handles a host Channel Halted interrupt in DMA mode. This handler
1772 * determines the reason the channel halted and proceeds accordingly.
1774 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1775 struct dwc2_host_chan *chan, int chnum,
1776 struct dwc2_qtd *qtd)
1779 int out_nak_enh = 0;
1782 dev_vdbg(hsotg->dev,
1783 "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1787 * For core with OUT NAK enhancement, the flow for high-speed
1788 * CONTROL/BULK OUT is handled a little differently
1790 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1791 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1792 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1793 chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1798 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1799 (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1800 hsotg->core_params->dma_desc_enable <= 0)) {
1801 if (hsotg->core_params->dma_desc_enable > 0)
1802 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1806 * Just release the channel. A dequeue can happen on a
1807 * transfer timeout. In the case of an AHB Error, the
1808 * channel was forced to halt because there's no way to
1809 * gracefully recover.
1811 dwc2_release_channel(hsotg, chan, qtd,
1816 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1818 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1820 * Todo: This is here because of a possible hardware bug. Spec
1821 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1822 * interrupt w/ACK bit set should occur, but I only see the
1823 * XFERCOMP bit, even with it masked out. This is a workaround
1824 * for that behavior. Should fix this when hardware is fixed.
1826 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1827 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1828 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1829 } else if (chan->hcint & HCINTMSK_STALL) {
1830 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1831 } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1832 hsotg->core_params->dma_desc_enable <= 0) {
1835 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1836 dev_vdbg(hsotg->dev,
1837 "XactErr with NYET/NAK/ACK\n");
1838 qtd->error_count = 0;
1840 dev_vdbg(hsotg->dev,
1841 "XactErr without NYET/NAK/ACK\n");
1846 * Must handle xacterr before nak or ack. Could get a xacterr
1847 * at the same time as either of these on a BULK/CONTROL OUT
1848 * that started with a PING. The xacterr takes precedence.
1850 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1851 } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1852 hsotg->core_params->dma_desc_enable > 0) {
1853 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1854 } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1855 hsotg->core_params->dma_desc_enable > 0) {
1856 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1857 } else if (chan->hcint & HCINTMSK_BBLERR) {
1858 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1859 } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1860 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1861 } else if (!out_nak_enh) {
1862 if (chan->hcint & HCINTMSK_NYET) {
1864 * Must handle nyet before nak or ack. Could get a nyet
1865 * at the same time as either of those on a BULK/CONTROL
1866 * OUT that started with a PING. The nyet takes
1869 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1870 } else if ((chan->hcint & HCINTMSK_NAK) &&
1871 !(hcintmsk & HCINTMSK_NAK)) {
1873 * If nak is not masked, it's because a non-split IN
1874 * transfer is in an error state. In that case, the nak
1875 * is handled by the nak interrupt handler, not here.
1876 * Handle nak here for BULK/CONTROL OUT transfers, which
1877 * halt on a NAK to allow rewinding the buffer pointer.
1879 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1880 } else if ((chan->hcint & HCINTMSK_ACK) &&
1881 !(hcintmsk & HCINTMSK_ACK)) {
1883 * If ack is not masked, it's because a non-split IN
1884 * transfer is in an error state. In that case, the ack
1885 * is handled by the ack interrupt handler, not here.
1886 * Handle ack here for split transfers. Start splits
1889 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1891 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1892 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1894 * A periodic transfer halted with no other
1895 * channel interrupts set. Assume it was halted
1896 * by the core because it could not be completed
1897 * in its scheduled (micro)frame.
1900 "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1902 dwc2_halt_channel(hsotg, chan, qtd,
1903 DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1906 "%s: Channel %d - ChHltd set, but reason is unknown\n",
1909 "hcint 0x%08x, intsts 0x%08x\n",
1911 dwc2_readl(hsotg->regs + GINTSTS));
1916 dev_info(hsotg->dev,
1917 "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1920 /* Failthrough: use 3-strikes rule */
1922 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1923 qtd, DWC2_HC_XFER_XACT_ERR);
1925 * We can get here after a completed transaction
1926 * (urb->actual_length >= urb->length) which was not reported
1927 * as completed. If that is the case, and we do not abort
1928 * the transfer, a transfer of size 0 will be enqueued
1929 * subsequently. If urb->actual_length is not DMA-aligned,
1930 * the buffer will then point to an unaligned address, and
1931 * the resulting behavior is undefined. Bail out in that
1934 if (qtd->urb->actual_length >= qtd->urb->length)
1935 qtd->error_count = 3;
1936 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1937 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1942 * Handles a host channel Channel Halted interrupt
1944 * In slave mode, this handler is called only when the driver specifically
1945 * requests a halt. This occurs during handling other host channel interrupts
1946 * (e.g. nak, xacterr, stall, nyet, etc.).
1948 * In DMA mode, this is the interrupt that occurs when the core has finished
1949 * processing a transfer on a channel. Other host channel interrupts (except
1950 * ahberr) are disabled in DMA mode.
1952 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1953 struct dwc2_host_chan *chan, int chnum,
1954 struct dwc2_qtd *qtd)
1957 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1960 if (hsotg->core_params->dma_enable > 0) {
1961 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1963 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1965 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1970 * Check if the given qtd is still the top of the list (and thus valid).
1972 * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1973 * the qtd from the top of the list, this will return false (otherwise true).
1975 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1977 struct dwc2_qtd *cur_head;
1982 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1984 return (cur_head == qtd);
1987 /* Handles interrupt for a specific Host Channel */
1988 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1990 struct dwc2_qtd *qtd;
1991 struct dwc2_host_chan *chan;
1992 u32 hcint, hcintmsk;
1994 chan = hsotg->hc_ptr_array[chnum];
1996 hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
1997 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1999 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
2000 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2005 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2007 dev_vdbg(hsotg->dev,
2008 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2009 hcint, hcintmsk, hcint & hcintmsk);
2012 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2015 * If we got an interrupt after someone called
2016 * dwc2_hcd_endpoint_disable() we don't want to crash below
2019 dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2023 chan->hcint = hcint;
2027 * If the channel was halted due to a dequeue, the qtd list might
2028 * be empty or at least the first entry will not be the active qtd.
2029 * In this case, take a shortcut and just release the channel.
2031 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2033 * If the channel was halted, this should be the only
2034 * interrupt unmasked
2036 WARN_ON(hcint != HCINTMSK_CHHLTD);
2037 if (hsotg->core_params->dma_desc_enable > 0)
2038 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2041 dwc2_release_channel(hsotg, chan, NULL,
2046 if (list_empty(&chan->qh->qtd_list)) {
2048 * TODO: Will this ever happen with the
2049 * DWC2_HC_XFER_URB_DEQUEUE handling above?
2051 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2054 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2055 chan->hcint, hcintmsk, hcint);
2056 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2057 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2062 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2065 if (hsotg->core_params->dma_enable <= 0) {
2066 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2067 hcint &= ~HCINTMSK_CHHLTD;
2070 if (hcint & HCINTMSK_XFERCOMPL) {
2071 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2073 * If NYET occurred at same time as Xfer Complete, the NYET is
2074 * handled by the Xfer Complete interrupt handler. Don't want
2075 * to call the NYET interrupt handler in this case.
2077 hcint &= ~HCINTMSK_NYET;
2080 if (hcint & HCINTMSK_CHHLTD) {
2081 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2082 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2085 if (hcint & HCINTMSK_AHBERR) {
2086 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2087 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2090 if (hcint & HCINTMSK_STALL) {
2091 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2092 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2095 if (hcint & HCINTMSK_NAK) {
2096 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2097 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2100 if (hcint & HCINTMSK_ACK) {
2101 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2102 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2105 if (hcint & HCINTMSK_NYET) {
2106 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2107 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2110 if (hcint & HCINTMSK_XACTERR) {
2111 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2112 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2115 if (hcint & HCINTMSK_BBLERR) {
2116 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2117 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2120 if (hcint & HCINTMSK_FRMOVRUN) {
2121 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2122 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2125 if (hcint & HCINTMSK_DATATGLERR) {
2126 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2127 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2136 * This interrupt indicates that one or more host channels has a pending
2137 * interrupt. There are multiple conditions that can cause each host channel
2138 * interrupt. This function determines which conditions have occurred for each
2139 * host channel interrupt and handles them appropriately.
2141 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2145 struct dwc2_host_chan *chan, *chan_tmp;
2147 haint = dwc2_readl(hsotg->regs + HAINT);
2149 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2151 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2155 * According to USB 2.0 spec section 11.18.8, a host must
2156 * issue complete-split transactions in a microframe for a
2157 * set of full-/low-speed endpoints in the same relative
2158 * order as the start-splits were issued in a microframe for.
2160 list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2161 split_order_list_entry) {
2162 int hc_num = chan->hc_num;
2164 if (haint & (1 << hc_num)) {
2165 dwc2_hc_n_intr(hsotg, hc_num);
2166 haint &= ~(1 << hc_num);
2170 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2171 if (haint & (1 << i))
2172 dwc2_hc_n_intr(hsotg, i);
2176 /* This function handles interrupts for the HCD */
2177 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2179 u32 gintsts, dbg_gintsts;
2180 irqreturn_t retval = IRQ_NONE;
2182 if (!dwc2_is_controller_alive(hsotg)) {
2183 dev_warn(hsotg->dev, "Controller is dead\n");
2187 spin_lock(&hsotg->lock);
2189 /* Check if HOST Mode */
2190 if (dwc2_is_host_mode(hsotg)) {
2191 gintsts = dwc2_read_core_intr(hsotg);
2193 spin_unlock(&hsotg->lock);
2197 retval = IRQ_HANDLED;
2199 dbg_gintsts = gintsts;
2201 dbg_gintsts &= ~GINTSTS_SOF;
2204 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2207 /* Only print if there are any non-suppressed interrupts left */
2209 dev_vdbg(hsotg->dev,
2210 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2213 if (gintsts & GINTSTS_SOF)
2214 dwc2_sof_intr(hsotg);
2215 if (gintsts & GINTSTS_RXFLVL)
2216 dwc2_rx_fifo_level_intr(hsotg);
2217 if (gintsts & GINTSTS_NPTXFEMP)
2218 dwc2_np_tx_fifo_empty_intr(hsotg);
2219 if (gintsts & GINTSTS_PRTINT)
2220 dwc2_port_intr(hsotg);
2221 if (gintsts & GINTSTS_HCHINT)
2222 dwc2_hc_intr(hsotg);
2223 if (gintsts & GINTSTS_PTXFEMP)
2224 dwc2_perio_tx_fifo_empty_intr(hsotg);
2227 dev_vdbg(hsotg->dev,
2228 "DWC OTG HCD Finished Servicing Interrupts\n");
2229 dev_vdbg(hsotg->dev,
2230 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2231 dwc2_readl(hsotg->regs + GINTSTS),
2232 dwc2_readl(hsotg->regs + GINTMSK));
2236 spin_unlock(&hsotg->lock);