drivers/usb/dwc2/hcd_intr.c

   1 /*
   2  * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the interrupt handlers for Host mode
  39  */
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/io.h>
  46 #include <linux/slab.h>
  47 #include <linux/usb.h>
  48
  49 #include <linux/usb/hcd.h>
  50 #include <linux/usb/ch11.h>
  51
  52 #include "core.h"
  53 #include "hcd.h"
  54
  55 /* This function is for debug only */
  56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
  57 {
  58 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  59         u16 curr_frame_number = hsotg->frame_number;
  60
  61         if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
  62                 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
  63                     curr_frame_number) {
  64                         hsotg->frame_num_array[hsotg->frame_num_idx] =
  65                                         curr_frame_number;
  66                         hsotg->last_frame_num_array[hsotg->frame_num_idx] =
  67                                         hsotg->last_frame_num;
  68                         hsotg->frame_num_idx++;
  69                 }
  70         } else if (!hsotg->dumped_frame_num_array) {
  71                 int i;
  72
  73                 dev_info(hsotg->dev, "Frame     Last Frame\n");
  74                 dev_info(hsotg->dev, "-----     ----------\n");
  75                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
  76                         dev_info(hsotg->dev, "0x%04x    0x%04x\n",
  77                                  hsotg->frame_num_array[i],
  78                                  hsotg->last_frame_num_array[i]);
  79                 }
  80                 hsotg->dumped_frame_num_array = 1;
  81         }
  82         hsotg->last_frame_num = curr_frame_number;
  83 #endif
  84 }
  85
  86 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
  87                                     struct dwc2_host_chan *chan,
  88                                     struct dwc2_qtd *qtd)
  89 {
  90         struct urb *usb_urb;
  91
  92         if (!chan->qh)
  93                 return;
  94
  95         if (chan->qh->dev_speed == USB_SPEED_HIGH)
  96                 return;
  97
  98         if (!qtd->urb)
  99                 return;
 100
 101         usb_urb = qtd->urb->priv;
 102         if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
 103                 return;
 104
 105         if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
 106                 chan->qh->tt_buffer_dirty = 1;
 107                 if (usb_hub_clear_tt_buffer(usb_urb))
 108                         /* Clear failed; let's hope things work anyway */
 109                         chan->qh->tt_buffer_dirty = 0;
 110         }
 111 }
 112
 113 /*
 114  * Handles the start-of-frame interrupt in host mode. Non-periodic
 115  * transactions may be queued to the DWC_otg controller for the current
 116  * (micro)frame. Periodic transactions may be queued to the controller
 117  * for the next (micro)frame.
 118  */
 119 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
 120 {
 121         struct list_head *qh_entry;
 122         struct dwc2_qh *qh;
 123         enum dwc2_transaction_type tr_type;
 124
 125 #ifdef DEBUG_SOF
 126         dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
 127 #endif
 128
 129         hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
 130
 131         dwc2_track_missed_sofs(hsotg);
 132
 133         /* Determine whether any periodic QHs should be executed */
 134         qh_entry = hsotg->periodic_sched_inactive.next;
 135         while (qh_entry != &hsotg->periodic_sched_inactive) {
 136                 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
 137                 qh_entry = qh_entry->next;
 138                 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
 139                         /*
 140                          * Move QH to the ready list to be executed next
 141                          * (micro)frame
 142                          */
 143                         list_move(&qh->qh_list_entry,
 144                                   &hsotg->periodic_sched_ready);
 145         }
 146         tr_type = dwc2_hcd_select_transactions(hsotg);
 147         if (tr_type != DWC2_TRANSACTION_NONE)
 148                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 149
 150         /* Clear interrupt */
 151         dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
 152 }
 153
 154 /*
 155  * Handles the Rx FIFO Level Interrupt, which indicates that there is
 156  * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
 157  * memory if the DWC_otg controller is operating in Slave mode.
 158  */
 159 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
 160 {
 161         u32 grxsts, chnum, bcnt, dpid, pktsts;
 162         struct dwc2_host_chan *chan;
 163
 164         if (dbg_perio())
 165                 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
 166
 167         grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
 168         chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
 169         chan = hsotg->hc_ptr_array[chnum];
 170         if (!chan) {
 171                 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
 172                 return;
 173         }
 174
 175         bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
 176         dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
 177         pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
 178
 179         /* Packet Status */
 180         if (dbg_perio()) {
 181                 dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);
 182                 dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);
 183                 dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
 184                          chan->data_pid_start);
 185                 dev_vdbg(hsotg->dev, "    PStatus = %d\n", pktsts);
 186         }
 187
 188         switch (pktsts) {
 189         case GRXSTS_PKTSTS_HCHIN:
 190                 /* Read the data into the host buffer */
 191                 if (bcnt > 0) {
 192                         dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
 193
 194                         /* Update the HC fields for the next packet received */
 195                         chan->xfer_count += bcnt;
 196                         chan->xfer_buf += bcnt;
 197                 }
 198                 break;
 199         case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
 200         case GRXSTS_PKTSTS_DATATOGGLEERR:
 201         case GRXSTS_PKTSTS_HCHHALTED:
 202                 /* Handled in interrupt, just ignore data */
 203                 break;
 204         default:
 205                 dev_err(hsotg->dev,
 206                         "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
 207                 break;
 208         }
 209 }
 210
 211 /*
 212  * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 213  * data packets may be written to the FIFO for OUT transfers. More requests
 214  * may be written to the non-periodic request queue for IN transfers. This
 215  * interrupt is enabled only in Slave mode.
 216  */
 217 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 218 {
 219         dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 220         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
 221 }
 222
 223 /*
 224  * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 225  * packets may be written to the FIFO for OUT transfers. More requests may be
 226  * written to the periodic request queue for IN transfers. This interrupt is
 227  * enabled only in Slave mode.
 228  */
 229 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 230 {
 231         if (dbg_perio())
 232                 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
 233         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
 234 }
 235
 236 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
 237                               u32 *hprt0_modify)
 238 {
 239         struct dwc2_core_params *params = hsotg->core_params;
 240         int do_reset = 0;
 241         u32 usbcfg;
 242         u32 prtspd;
 243         u32 hcfg;
 244         u32 fslspclksel;
 245         u32 hfir;
 246
 247         dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 248
 249         /* Every time when port enables calculate HFIR.FrInterval */
 250         hfir = dwc2_readl(hsotg->regs + HFIR);
 251         hfir &= ~HFIR_FRINT_MASK;
 252         hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
 253                 HFIR_FRINT_MASK;
 254         dwc2_writel(hfir, hsotg->regs + HFIR);
 255
 256         /* Check if we need to adjust the PHY clock speed for low power */
 257         if (!params->host_support_fs_ls_low_power) {
 258                 /* Port has been enabled, set the reset change flag */
 259                 hsotg->flags.b.port_reset_change = 1;
 260                 return;
 261         }
 262
 263         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 264         prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 265
 266         if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
 267                 /* Low power */
 268                 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
 269                         /* Set PHY low power clock select for FS/LS devices */
 270                         usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
 271                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 272                         do_reset = 1;
 273                 }
 274
 275                 hcfg = dwc2_readl(hsotg->regs + HCFG);
 276                 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
 277                               HCFG_FSLSPCLKSEL_SHIFT;
 278
 279                 if (prtspd == HPRT0_SPD_LOW_SPEED &&
 280                     params->host_ls_low_power_phy_clk ==
 281                     DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 282                         /* 6 MHZ */
 283                         dev_vdbg(hsotg->dev,
 284                                  "FS_PHY programming HCFG to 6 MHz\n");
 285                         if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
 286                                 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
 287                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 288                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 289                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 290                                 do_reset = 1;
 291                         }
 292                 } else {
 293                         /* 48 MHZ */
 294                         dev_vdbg(hsotg->dev,
 295                                  "FS_PHY programming HCFG to 48 MHz\n");
 296                         if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
 297                                 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
 298                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 299                                 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
 300                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
 301                                 do_reset = 1;
 302                         }
 303                 }
 304         } else {
 305                 /* Not low power */
 306                 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
 307                         usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
 308                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 309                         do_reset = 1;
 310                 }
 311         }
 312
 313         if (do_reset) {
 314                 *hprt0_modify |= HPRT0_RST;
 315                 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
 316                                    msecs_to_jiffies(60));
 317         } else {
 318                 /* Port has been enabled, set the reset change flag */
 319                 hsotg->flags.b.port_reset_change = 1;
 320         }
 321 }
 322
 323 /*
 324  * There are multiple conditions that can cause a port interrupt. This function
 325  * determines which interrupt conditions have occurred and handles them
 326  * appropriately.
 327  */
 328 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 329 {
 330         u32 hprt0;
 331         u32 hprt0_modify;
 332
 333         dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 334
 335         hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 336         hprt0_modify = hprt0;
 337
 338         /*
 339          * Clear appropriate bits in HPRT0 to clear the interrupt bit in
 340          * GINTSTS
 341          */
 342         hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
 343                           HPRT0_OVRCURRCHG);
 344
 345         /*
 346          * Port Connect Detected
 347          * Set flag and clear if detected
 348          */
 349         if (hprt0 & HPRT0_CONNDET) {
 350                 dev_vdbg(hsotg->dev,
 351                          "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
 352                          hprt0);
 353                 if (hsotg->lx_state != DWC2_L0)
 354                         usb_hcd_resume_root_hub(hsotg->priv);
 355
 356                 hsotg->flags.b.port_connect_status_change = 1;
 357                 hsotg->flags.b.port_connect_status = 1;
 358                 hprt0_modify |= HPRT0_CONNDET;
 359
 360                 /*
 361                  * The Hub driver asserts a reset when it sees port connect
 362                  * status change flag
 363                  */
 364         }
 365
 366         /*
 367          * Port Enable Changed
 368          * Clear if detected - Set internal flag if disabled
 369          */
 370         if (hprt0 & HPRT0_ENACHG) {
 371                 dev_vdbg(hsotg->dev,
 372                          "  --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
 373                          hprt0, !!(hprt0 & HPRT0_ENA));
 374                 hprt0_modify |= HPRT0_ENACHG;
 375                 if (hprt0 & HPRT0_ENA)
 376                         dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
 377                 else
 378                         hsotg->flags.b.port_enable_change = 1;
 379         }
 380
 381         /* Overcurrent Change Interrupt */
 382         if (hprt0 & HPRT0_OVRCURRCHG) {
 383                 dev_vdbg(hsotg->dev,
 384                          "  --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
 385                          hprt0);
 386                 hsotg->flags.b.port_over_current_change = 1;
 387                 hprt0_modify |= HPRT0_OVRCURRCHG;
 388         }
 389
 390         /* Clear Port Interrupts */
 391         dwc2_writel(hprt0_modify, hsotg->regs + HPRT0);
 392 }
 393
 394 /*
 395  * Gets the actual length of a transfer after the transfer halts. halt_status
 396  * holds the reason for the halt.
 397  *
 398  * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
 399  * is set to 1 upon return if less than the requested number of bytes were
 400  * transferred. short_read may also be NULL on entry, in which case it remains
 401  * unchanged.
 402  */
 403 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
 404                                        struct dwc2_host_chan *chan, int chnum,
 405                                        struct dwc2_qtd *qtd,
 406                                        enum dwc2_halt_status halt_status,
 407                                        int *short_read)
 408 {
 409         u32 hctsiz, count, length;
 410
 411         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 412
 413         if (halt_status == DWC2_HC_XFER_COMPLETE) {
 414                 if (chan->ep_is_in) {
 415                         count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
 416                                 TSIZ_XFERSIZE_SHIFT;
 417                         length = chan->xfer_len - count;
 418                         if (short_read != NULL)
 419                                 *short_read = (count != 0);
 420                 } else if (chan->qh->do_split) {
 421                         length = qtd->ssplit_out_xfer_count;
 422                 } else {
 423                         length = chan->xfer_len;
 424                 }
 425         } else {
 426                 /*
 427                  * Must use the hctsiz.pktcnt field to determine how much data
 428                  * has been transferred. This field reflects the number of
 429                  * packets that have been transferred via the USB. This is
 430                  * always an integral number of packets if the transfer was
 431                  * halted before its normal completion. (Can't use the
 432                  * hctsiz.xfersize field because that reflects the number of
 433                  * bytes transferred via the AHB, not the USB).
 434                  */
 435                 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
 436                 length = (chan->start_pkt_count - count) * chan->max_packet;
 437         }
 438
 439         return length;
 440 }
 441
 442 /**
 443  * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
 444  * Complete interrupt on the host channel. Updates the actual_length field
 445  * of the URB based on the number of bytes transferred via the host channel.
 446  * Sets the URB status if the data transfer is finished.
 447  *
 448  * Return: 1 if the data transfer specified by the URB is completely finished,
 449  * 0 otherwise
 450  */
 451 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
 452                                  struct dwc2_host_chan *chan, int chnum,
 453                                  struct dwc2_hcd_urb *urb,
 454                                  struct dwc2_qtd *qtd)
 455 {
 456         u32 hctsiz;
 457         int xfer_done = 0;
 458         int short_read = 0;
 459         int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 460                                                       DWC2_HC_XFER_COMPLETE,
 461                                                       &short_read);
 462
 463         if (urb->actual_length + xfer_length > urb->length) {
 464                 dev_dbg(hsotg->dev, "%s(): trimming xfer length\n", __func__);
 465                 xfer_length = urb->length - urb->actual_length;
 466         }
 467
 468         /* Non DWORD-aligned buffer case handling */
 469         if (chan->align_buf && xfer_length) {
 470                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 471                 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
 472                                 chan->qh->dw_align_buf_size,
 473                                 chan->ep_is_in ?
 474                                 DMA_FROM_DEVICE : DMA_TO_DEVICE);
 475                 if (chan->ep_is_in)
 476                         memcpy(urb->buf + urb->actual_length,
 477                                         chan->qh->dw_align_buf, xfer_length);
 478         }
 479
 480         dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
 481                  urb->actual_length, xfer_length);
 482         urb->actual_length += xfer_length;
 483
 484         if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
 485             (urb->flags & URB_SEND_ZERO_PACKET) &&
 486             urb->actual_length >= urb->length &&
 487             !(urb->length % chan->max_packet)) {
 488                 xfer_done = 0;
 489         } else if (short_read || urb->actual_length >= urb->length) {
 490                 xfer_done = 1;
 491                 urb->status = 0;
 492         }
 493
 494         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 495         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
 496                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
 497         dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
 498         dev_vdbg(hsotg->dev, "  hctsiz.xfersize %d\n",
 499                  (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
 500         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n", urb->length);
 501         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n", urb->actual_length);
 502         dev_vdbg(hsotg->dev, "  short_read %d, xfer_done %d\n", short_read,
 503                  xfer_done);
 504
 505         return xfer_done;
 506 }
 507
 508 /*
 509  * Save the starting data toggle for the next transfer. The data toggle is
 510  * saved in the QH for non-control transfers and it's saved in the QTD for
 511  * control transfers.
 512  */
 513 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 514                                struct dwc2_host_chan *chan, int chnum,
 515                                struct dwc2_qtd *qtd)
 516 {
 517         u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 518         u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
 519
 520         if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
 521                 if (pid == TSIZ_SC_MC_PID_DATA0)
 522                         chan->qh->data_toggle = DWC2_HC_PID_DATA0;
 523                 else
 524                         chan->qh->data_toggle = DWC2_HC_PID_DATA1;
 525         } else {
 526                 if (pid == TSIZ_SC_MC_PID_DATA0)
 527                         qtd->data_toggle = DWC2_HC_PID_DATA0;
 528                 else
 529                         qtd->data_toggle = DWC2_HC_PID_DATA1;
 530         }
 531 }
 532
 533 /**
 534  * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
 535  * the transfer is stopped for any reason. The fields of the current entry in
 536  * the frame descriptor array are set based on the transfer state and the input
 537  * halt_status. Completes the Isochronous URB if all the URB frames have been
 538  * completed.
 539  *
 540  * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
 541  * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
 542  */
 543 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
 544                 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 545                 int chnum, struct dwc2_qtd *qtd,
 546                 enum dwc2_halt_status halt_status)
 547 {
 548         struct dwc2_hcd_iso_packet_desc *frame_desc;
 549         struct dwc2_hcd_urb *urb = qtd->urb;
 550
 551         if (!urb)
 552                 return DWC2_HC_XFER_NO_HALT_STATUS;
 553
 554         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 555
 556         switch (halt_status) {
 557         case DWC2_HC_XFER_COMPLETE:
 558                 frame_desc->status = 0;
 559                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 560                                         chan, chnum, qtd, halt_status, NULL);
 561
 562                 /* Non DWORD-aligned buffer case handling */
 563                 if (chan->align_buf && frame_desc->actual_length) {
 564                         dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
 565                                  __func__);
 566                         dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
 567                                         chan->qh->dw_align_buf_size,
 568                                         chan->ep_is_in ?
 569                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 570                         if (chan->ep_is_in)
 571                                 memcpy(urb->buf + frame_desc->offset +
 572                                         qtd->isoc_split_offset,
 573                                         chan->qh->dw_align_buf,
 574                                         frame_desc->actual_length);
 575                 }
 576                 break;
 577         case DWC2_HC_XFER_FRAME_OVERRUN:
 578                 urb->error_count++;
 579                 if (chan->ep_is_in)
 580                         frame_desc->status = -ENOSR;
 581                 else
 582                         frame_desc->status = -ECOMM;
 583                 frame_desc->actual_length = 0;
 584                 break;
 585         case DWC2_HC_XFER_BABBLE_ERR:
 586                 urb->error_count++;
 587                 frame_desc->status = -EOVERFLOW;
 588                 /* Don't need to update actual_length in this case */
 589                 break;
 590         case DWC2_HC_XFER_XACT_ERR:
 591                 urb->error_count++;
 592                 frame_desc->status = -EPROTO;
 593                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 594                                         chan, chnum, qtd, halt_status, NULL);
 595
 596                 /* Non DWORD-aligned buffer case handling */
 597                 if (chan->align_buf && frame_desc->actual_length) {
 598                         dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n",
 599                                  __func__);
 600                         dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
 601                                         chan->qh->dw_align_buf_size,
 602                                         chan->ep_is_in ?
 603                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 604                         if (chan->ep_is_in)
 605                                 memcpy(urb->buf + frame_desc->offset +
 606                                         qtd->isoc_split_offset,
 607                                         chan->qh->dw_align_buf,
 608                                         frame_desc->actual_length);
 609                 }
 610
 611                 /* Skip whole frame */
 612                 if (chan->qh->do_split &&
 613                     chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 614                     hsotg->core_params->dma_enable > 0) {
 615                         qtd->complete_split = 0;
 616                         qtd->isoc_split_offset = 0;
 617                 }
 618
 619                 break;
 620         default:
 621                 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
 622                         halt_status);
 623                 break;
 624         }
 625
 626         if (++qtd->isoc_frame_index == urb->packet_count) {
 627                 /*
 628                  * urb->status is not used for isoc transfers. The individual
 629                  * frame_desc statuses are used instead.
 630                  */
 631                 dwc2_host_complete(hsotg, qtd, 0);
 632                 halt_status = DWC2_HC_XFER_URB_COMPLETE;
 633         } else {
 634                 halt_status = DWC2_HC_XFER_COMPLETE;
 635         }
 636
 637         return halt_status;
 638 }
 639
 640 /*
 641  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 642  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 643  * still linked to the QH, the QH is added to the end of the inactive
 644  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 645  * schedule if no more QTDs are linked to the QH.
 646  */
 647 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 648                                int free_qtd)
 649 {
 650         int continue_split = 0;
 651         struct dwc2_qtd *qtd;
 652
 653         if (dbg_qh(qh))
 654                 dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,
 655                          hsotg, qh, free_qtd);
 656
 657         if (list_empty(&qh->qtd_list)) {
 658                 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
 659                 goto no_qtd;
 660         }
 661
 662         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 663
 664         if (qtd->complete_split)
 665                 continue_split = 1;
 666         else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
 667                  qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
 668                 continue_split = 1;
 669
 670         if (free_qtd) {
 671                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 672                 continue_split = 0;
 673         }
 674
 675 no_qtd:
 676         if (qh->channel)
 677                 qh->channel->align_buf = 0;
 678         qh->channel = NULL;
 679         dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
 680 }
 681
 682 /**
 683  * dwc2_release_channel() - Releases a host channel for use by other transfers
 684  *
 685  * @hsotg:       The HCD state structure
 686  * @chan:        The host channel to release
 687  * @qtd:         The QTD associated with the host channel. This QTD may be
 688  *               freed if the transfer is complete or an error has occurred.
 689  * @halt_status: Reason the channel is being released. This status
 690  *               determines the actions taken by this function.
 691  *
 692  * Also attempts to select and queue more transactions since at least one host
 693  * channel is available.
 694  */
 695 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
 696                                  struct dwc2_host_chan *chan,
 697                                  struct dwc2_qtd *qtd,
 698                                  enum dwc2_halt_status halt_status)
 699 {
 700         enum dwc2_transaction_type tr_type;
 701         u32 haintmsk;
 702         int free_qtd = 0;
 703
 704         if (dbg_hc(chan))
 705                 dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
 706                          __func__, chan->hc_num, halt_status);
 707
 708         switch (halt_status) {
 709         case DWC2_HC_XFER_URB_COMPLETE:
 710                 free_qtd = 1;
 711                 break;
 712         case DWC2_HC_XFER_AHB_ERR:
 713         case DWC2_HC_XFER_STALL:
 714         case DWC2_HC_XFER_BABBLE_ERR:
 715                 free_qtd = 1;
 716                 break;
 717         case DWC2_HC_XFER_XACT_ERR:
 718                 if (qtd && qtd->error_count >= 3) {
 719                         dev_vdbg(hsotg->dev,
 720                                  "  Complete URB with transaction error\n");
 721                         free_qtd = 1;
 722                         dwc2_host_complete(hsotg, qtd, -EPROTO);
 723                 }
 724                 break;
 725         case DWC2_HC_XFER_URB_DEQUEUE:
 726                 /*
 727                  * The QTD has already been removed and the QH has been
 728                  * deactivated. Don't want to do anything except release the
 729                  * host channel and try to queue more transfers.
 730                  */
 731                 goto cleanup;
 732         case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
 733                 dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
 734                 free_qtd = 1;
 735                 dwc2_host_complete(hsotg, qtd, -EIO);
 736                 break;
 737         case DWC2_HC_XFER_NO_HALT_STATUS:
 738         default:
 739                 break;
 740         }
 741
 742         dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
 743
 744 cleanup:
 745         /*
 746          * Release the host channel for use by other transfers. The cleanup
 747          * function clears the channel interrupt enables and conditions, so
 748          * there's no need to clear the Channel Halted interrupt separately.
 749          */
 750         if (!list_empty(&chan->hc_list_entry))
 751                 list_del(&chan->hc_list_entry);
 752         dwc2_hc_cleanup(hsotg, chan);
 753         list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 754
 755         if (hsotg->core_params->uframe_sched > 0) {
 756                 hsotg->available_host_channels++;
 757         } else {
 758                 switch (chan->ep_type) {
 759                 case USB_ENDPOINT_XFER_CONTROL:
 760                 case USB_ENDPOINT_XFER_BULK:
 761                         hsotg->non_periodic_channels--;
 762                         break;
 763                 default:
 764                         /*
 765                          * Don't release reservations for periodic channels
 766                          * here. That's done when a periodic transfer is
 767                          * descheduled (i.e. when the QH is removed from the
 768                          * periodic schedule).
 769                          */
 770                         break;
 771                 }
 772         }
 773
 774         haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
 775         haintmsk &= ~(1 << chan->hc_num);
 776         dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
 777
 778         /* Try to queue more transfers now that there's a free channel */
 779         tr_type = dwc2_hcd_select_transactions(hsotg);
 780         if (tr_type != DWC2_TRANSACTION_NONE)
 781                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 782 }
 783
 784 /*
 785  * Halts a host channel. If the channel cannot be halted immediately because
 786  * the request queue is full, this function ensures that the FIFO empty
 787  * interrupt for the appropriate queue is enabled so that the halt request can
 788  * be queued when there is space in the request queue.
 789  *
 790  * This function may also be called in DMA mode. In that case, the channel is
 791  * simply released since the core always halts the channel automatically in
 792  * DMA mode.
 793  */
 794 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
 795                               struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
 796                               enum dwc2_halt_status halt_status)
 797 {
 798         if (dbg_hc(chan))
 799                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 800
 801         if (hsotg->core_params->dma_enable > 0) {
 802                 if (dbg_hc(chan))
 803                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 804                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 805                 return;
 806         }
 807
 808         /* Slave mode processing */
 809         dwc2_hc_halt(hsotg, chan, halt_status);
 810
 811         if (chan->halt_on_queue) {
 812                 u32 gintmsk;
 813
 814                 dev_vdbg(hsotg->dev, "Halt on queue\n");
 815                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 816                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 817                         dev_vdbg(hsotg->dev, "control/bulk\n");
 818                         /*
 819                          * Make sure the Non-periodic Tx FIFO empty interrupt
 820                          * is enabled so that the non-periodic schedule will
 821                          * be processed
 822                          */
 823                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 824                         gintmsk |= GINTSTS_NPTXFEMP;
 825                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 826                 } else {
 827                         dev_vdbg(hsotg->dev, "isoc/intr\n");
 828                         /*
 829                          * Move the QH from the periodic queued schedule to
 830                          * the periodic assigned schedule. This allows the
 831                          * halt to be queued when the periodic schedule is
 832                          * processed.
 833                          */
 834                         list_move(&chan->qh->qh_list_entry,
 835                                   &hsotg->periodic_sched_assigned);
 836
 837                         /*
 838                          * Make sure the Periodic Tx FIFO Empty interrupt is
 839                          * enabled so that the periodic schedule will be
 840                          * processed
 841                          */
 842                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 843                         gintmsk |= GINTSTS_PTXFEMP;
 844                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
 845                 }
 846         }
 847 }
 848
 849 /*
 850  * Performs common cleanup for non-periodic transfers after a Transfer
 851  * Complete interrupt. This function should be called after any endpoint type
 852  * specific handling is finished to release the host channel.
 853  */
 854 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
 855                                             struct dwc2_host_chan *chan,
 856                                             int chnum, struct dwc2_qtd *qtd,
 857                                             enum dwc2_halt_status halt_status)
 858 {
 859         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 860
 861         qtd->error_count = 0;
 862
 863         if (chan->hcint & HCINTMSK_NYET) {
 864                 /*
 865                  * Got a NYET on the last transaction of the transfer. This
 866                  * means that the endpoint should be in the PING state at the
 867                  * beginning of the next transfer.
 868                  */
 869                 dev_vdbg(hsotg->dev, "got NYET\n");
 870                 chan->qh->ping_state = 1;
 871         }
 872
 873         /*
 874          * Always halt and release the host channel to make it available for
 875          * more transfers. There may still be more phases for a control
 876          * transfer or more data packets for a bulk transfer at this point,
 877          * but the host channel is still halted. A channel will be reassigned
 878          * to the transfer when the non-periodic schedule is processed after
 879          * the channel is released. This allows transactions to be queued
 880          * properly via dwc2_hcd_queue_transactions, which also enables the
 881          * Tx FIFO Empty interrupt if necessary.
 882          */
 883         if (chan->ep_is_in) {
 884                 /*
 885                  * IN transfers in Slave mode require an explicit disable to
 886                  * halt the channel. (In DMA mode, this call simply releases
 887                  * the channel.)
 888                  */
 889                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 890         } else {
 891                 /*
 892                  * The channel is automatically disabled by the core for OUT
 893                  * transfers in Slave mode
 894                  */
 895                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 896         }
 897 }
 898
 899 /*
 900  * Performs common cleanup for periodic transfers after a Transfer Complete
 901  * interrupt. This function should be called after any endpoint type specific
 902  * handling is finished to release the host channel.
 903  */
 904 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
 905                                         struct dwc2_host_chan *chan, int chnum,
 906                                         struct dwc2_qtd *qtd,
 907                                         enum dwc2_halt_status halt_status)
 908 {
 909         u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
 910
 911         qtd->error_count = 0;
 912
 913         if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
 914                 /* Core halts channel in these cases */
 915                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 916         else
 917                 /* Flush any outstanding requests from the Tx queue */
 918                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 919 }
 920
 921 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
 922                                        struct dwc2_host_chan *chan, int chnum,
 923                                        struct dwc2_qtd *qtd)
 924 {
 925         struct dwc2_hcd_iso_packet_desc *frame_desc;
 926         u32 len;
 927
 928         if (!qtd->urb)
 929                 return 0;
 930
 931         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
 932         len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 933                                           DWC2_HC_XFER_COMPLETE, NULL);
 934         if (!len && !qtd->isoc_split_offset) {
 935                 qtd->complete_split = 0;
 936                 return 0;
 937         }
 938
 939         frame_desc->actual_length += len;
 940
 941         if (chan->align_buf) {
 942                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 943                 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
 944                                 chan->qh->dw_align_buf_size, DMA_FROM_DEVICE);
 945                 memcpy(qtd->urb->buf + frame_desc->offset +
 946                        qtd->isoc_split_offset, chan->qh->dw_align_buf, len);
 947         }
 948
 949         qtd->isoc_split_offset += len;
 950
 951         if (frame_desc->actual_length >= frame_desc->length) {
 952                 frame_desc->status = 0;
 953                 qtd->isoc_frame_index++;
 954                 qtd->complete_split = 0;
 955                 qtd->isoc_split_offset = 0;
 956         }
 957
 958         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
 959                 dwc2_host_complete(hsotg, qtd, 0);
 960                 dwc2_release_channel(hsotg, chan, qtd,
 961                                      DWC2_HC_XFER_URB_COMPLETE);
 962         } else {
 963                 dwc2_release_channel(hsotg, chan, qtd,
 964                                      DWC2_HC_XFER_NO_HALT_STATUS);
 965         }
 966
 967         return 1;       /* Indicates that channel released */
 968 }
 969
 970 /*
 971  * Handles a host channel Transfer Complete interrupt. This handler may be
 972  * called in either DMA mode or Slave mode.
 973  */
 974 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
 975                                   struct dwc2_host_chan *chan, int chnum,
 976                                   struct dwc2_qtd *qtd)
 977 {
 978         struct dwc2_hcd_urb *urb = qtd->urb;
 979         enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
 980         int pipe_type;
 981         int urb_xfer_done;
 982
 983         if (dbg_hc(chan))
 984                 dev_vdbg(hsotg->dev,
 985                          "--Host Channel %d Interrupt: Transfer Complete--\n",
 986                          chnum);
 987
 988         if (!urb)
 989                 goto handle_xfercomp_done;
 990
 991         pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
 992
 993         if (hsotg->core_params->dma_desc_enable > 0) {
 994                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
 995                 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
 996                         /* Do not disable the interrupt, just clear it */
 997                         return;
 998                 goto handle_xfercomp_done;
 999         }
1000
1001         /* Handle xfer complete on CSPLIT */
1002         if (chan->qh->do_split) {
1003                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
1004                     hsotg->core_params->dma_enable > 0) {
1005                         if (qtd->complete_split &&
1006                             dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1007                                                         qtd))
1008                                 goto handle_xfercomp_done;
1009                 } else {
1010                         qtd->complete_split = 0;
1011                 }
1012         }
1013
1014         /* Update the QTD and URB states */
1015         switch (pipe_type) {
1016         case USB_ENDPOINT_XFER_CONTROL:
1017                 switch (qtd->control_phase) {
1018                 case DWC2_CONTROL_SETUP:
1019                         if (urb->length > 0)
1020                                 qtd->control_phase = DWC2_CONTROL_DATA;
1021                         else
1022                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1023                         dev_vdbg(hsotg->dev,
1024                                  "  Control setup transaction done\n");
1025                         halt_status = DWC2_HC_XFER_COMPLETE;
1026                         break;
1027                 case DWC2_CONTROL_DATA:
1028                         urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1029                                                               chnum, urb, qtd);
1030                         if (urb_xfer_done) {
1031                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1032                                 dev_vdbg(hsotg->dev,
1033                                          "  Control data transfer done\n");
1034                         } else {
1035                                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1036                                                           qtd);
1037                         }
1038                         halt_status = DWC2_HC_XFER_COMPLETE;
1039                         break;
1040                 case DWC2_CONTROL_STATUS:
1041                         dev_vdbg(hsotg->dev, "  Control transfer complete\n");
1042                         if (urb->status == -EINPROGRESS)
1043                                 urb->status = 0;
1044                         dwc2_host_complete(hsotg, qtd, urb->status);
1045                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1046                         break;
1047                 }
1048
1049                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1050                                                 halt_status);
1051                 break;
1052         case USB_ENDPOINT_XFER_BULK:
1053                 dev_vdbg(hsotg->dev, "  Bulk transfer complete\n");
1054                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1055                                                       qtd);
1056                 if (urb_xfer_done) {
1057                         dwc2_host_complete(hsotg, qtd, urb->status);
1058                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1059                 } else {
1060                         halt_status = DWC2_HC_XFER_COMPLETE;
1061                 }
1062
1063                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1064                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1065                                                 halt_status);
1066                 break;
1067         case USB_ENDPOINT_XFER_INT:
1068                 dev_vdbg(hsotg->dev, "  Interrupt transfer complete\n");
1069                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1070                                                       qtd);
1071
1072                 /*
1073                  * Interrupt URB is done on the first transfer complete
1074                  * interrupt
1075                  */
1076                 if (urb_xfer_done) {
1077                         dwc2_host_complete(hsotg, qtd, urb->status);
1078                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1079                 } else {
1080                         halt_status = DWC2_HC_XFER_COMPLETE;
1081                 }
1082
1083                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1084                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1085                                             halt_status);
1086                 break;
1087         case USB_ENDPOINT_XFER_ISOC:
1088                 if (dbg_perio())
1089                         dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");
1090                 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1091                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1092                                         chnum, qtd, DWC2_HC_XFER_COMPLETE);
1093                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1094                                             halt_status);
1095                 break;
1096         }
1097
1098 handle_xfercomp_done:
1099         disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1100 }
1101
1102 /*
1103  * Handles a host channel STALL interrupt. This handler may be called in
1104  * either DMA mode or Slave mode.
1105  */
1106 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1107                                struct dwc2_host_chan *chan, int chnum,
1108                                struct dwc2_qtd *qtd)
1109 {
1110         struct dwc2_hcd_urb *urb = qtd->urb;
1111         int pipe_type;
1112
1113         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1114                 chnum);
1115
1116         if (hsotg->core_params->dma_desc_enable > 0) {
1117                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1118                                             DWC2_HC_XFER_STALL);
1119                 goto handle_stall_done;
1120         }
1121
1122         if (!urb)
1123                 goto handle_stall_halt;
1124
1125         pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1126
1127         if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1128                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1129
1130         if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1131             pipe_type == USB_ENDPOINT_XFER_INT) {
1132                 dwc2_host_complete(hsotg, qtd, -EPIPE);
1133                 /*
1134                  * USB protocol requires resetting the data toggle for bulk
1135                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1136                  * setup command is issued to the endpoint. Anticipate the
1137                  * CLEAR_FEATURE command since a STALL has occurred and reset
1138                  * the data toggle now.
1139                  */
1140                 chan->qh->data_toggle = 0;
1141         }
1142
1143 handle_stall_halt:
1144         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1145
1146 handle_stall_done:
1147         disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1148 }
1149
1150 /*
1151  * Updates the state of the URB when a transfer has been stopped due to an
1152  * abnormal condition before the transfer completes. Modifies the
1153  * actual_length field of the URB to reflect the number of bytes that have
1154  * actually been transferred via the host channel.
1155  */
1156 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1157                                       struct dwc2_host_chan *chan, int chnum,
1158                                       struct dwc2_hcd_urb *urb,
1159                                       struct dwc2_qtd *qtd,
1160                                       enum dwc2_halt_status halt_status)
1161 {
1162         u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1163                                                       qtd, halt_status, NULL);
1164         u32 hctsiz;
1165
1166         if (urb->actual_length + xfer_length > urb->length) {
1167                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1168                 xfer_length = urb->length - urb->actual_length;
1169         }
1170
1171         /* Non DWORD-aligned buffer case handling */
1172         if (chan->align_buf && xfer_length && chan->ep_is_in) {
1173                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1174                 dma_unmap_single(hsotg->dev, chan->qh->dw_align_buf_dma,
1175                                 chan->qh->dw_align_buf_size,
1176                                 chan->ep_is_in ?
1177                                 DMA_FROM_DEVICE : DMA_TO_DEVICE);
1178                 if (chan->ep_is_in)
1179                         memcpy(urb->buf + urb->actual_length,
1180                                         chan->qh->dw_align_buf,
1181                                         xfer_length);
1182         }
1183
1184         urb->actual_length += xfer_length;
1185
1186         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1187         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1188                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1189         dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
1190                  chan->start_pkt_count);
1191         dev_vdbg(hsotg->dev, "  hctsiz.pktcnt %d\n",
1192                  (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1193         dev_vdbg(hsotg->dev, "  chan->max_packet %d\n", chan->max_packet);
1194         dev_vdbg(hsotg->dev, "  bytes_transferred %d\n",
1195                  xfer_length);
1196         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n",
1197                  urb->actual_length);
1198         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n",
1199                  urb->length);
1200 }
1201
1202 /*
1203  * Handles a host channel NAK interrupt. This handler may be called in either
1204  * DMA mode or Slave mode.
1205  */
1206 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1207                              struct dwc2_host_chan *chan, int chnum,
1208                              struct dwc2_qtd *qtd)
1209 {
1210         if (!qtd) {
1211                 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1212                 return;
1213         }
1214
1215         if (!qtd->urb) {
1216                 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1217                 return;
1218         }
1219
1220         if (dbg_hc(chan))
1221                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1222                          chnum);
1223
1224         /*
1225          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1226          * interrupt. Re-start the SSPLIT transfer.
1227          */
1228         if (chan->do_split) {
1229                 if (chan->complete_split)
1230                         qtd->error_count = 0;
1231                 qtd->complete_split = 0;
1232                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1233                 goto handle_nak_done;
1234         }
1235
1236         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1237         case USB_ENDPOINT_XFER_CONTROL:
1238         case USB_ENDPOINT_XFER_BULK:
1239                 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1240                         /*
1241                          * NAK interrupts are enabled on bulk/control IN
1242                          * transfers in DMA mode for the sole purpose of
1243                          * resetting the error count after a transaction error
1244                          * occurs. The core will continue transferring data.
1245                          */
1246                         qtd->error_count = 0;
1247                         break;
1248                 }
1249
1250                 /*
1251                  * NAK interrupts normally occur during OUT transfers in DMA
1252                  * or Slave mode. For IN transfers, more requests will be
1253                  * queued as request queue space is available.
1254                  */
1255                 qtd->error_count = 0;
1256
1257                 if (!chan->qh->ping_state) {
1258                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1259                                                   qtd, DWC2_HC_XFER_NAK);
1260                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1261
1262                         if (chan->speed == USB_SPEED_HIGH)
1263                                 chan->qh->ping_state = 1;
1264                 }
1265
1266                 /*
1267                  * Halt the channel so the transfer can be re-started from
1268                  * the appropriate point or the PING protocol will
1269                  * start/continue
1270                  */
1271                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1272                 break;
1273         case USB_ENDPOINT_XFER_INT:
1274                 qtd->error_count = 0;
1275                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1276                 break;
1277         case USB_ENDPOINT_XFER_ISOC:
1278                 /* Should never get called for isochronous transfers */
1279                 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1280                 break;
1281         }
1282
1283 handle_nak_done:
1284         disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1285 }
1286
1287 /*
1288  * Handles a host channel ACK interrupt. This interrupt is enabled when
1289  * performing the PING protocol in Slave mode, when errors occur during
1290  * either Slave mode or DMA mode, and during Start Split transactions.
1291  */
1292 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1293                              struct dwc2_host_chan *chan, int chnum,
1294                              struct dwc2_qtd *qtd)
1295 {
1296         struct dwc2_hcd_iso_packet_desc *frame_desc;
1297
1298         if (dbg_hc(chan))
1299                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1300                          chnum);
1301
1302         if (chan->do_split) {
1303                 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1304                 if (!chan->ep_is_in &&
1305                     chan->data_pid_start != DWC2_HC_PID_SETUP)
1306                         qtd->ssplit_out_xfer_count = chan->xfer_len;
1307
1308                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1309                         qtd->complete_split = 1;
1310                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1311                 } else {
1312                         /* ISOC OUT */
1313                         switch (chan->xact_pos) {
1314                         case DWC2_HCSPLT_XACTPOS_ALL:
1315                                 break;
1316                         case DWC2_HCSPLT_XACTPOS_END:
1317                                 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1318                                 qtd->isoc_split_offset = 0;
1319                                 break;
1320                         case DWC2_HCSPLT_XACTPOS_BEGIN:
1321                         case DWC2_HCSPLT_XACTPOS_MID:
1322                                 /*
1323                                  * For BEGIN or MID, calculate the length for
1324                                  * the next microframe to determine the correct
1325                                  * SSPLIT token, either MID or END
1326                                  */
1327                                 frame_desc = &qtd->urb->iso_descs[
1328                                                 qtd->isoc_frame_index];
1329                                 qtd->isoc_split_offset += 188;
1330
1331                                 if (frame_desc->length - qtd->isoc_split_offset
1332                                                         <= 188)
1333                                         qtd->isoc_split_pos =
1334                                                         DWC2_HCSPLT_XACTPOS_END;
1335                                 else
1336                                         qtd->isoc_split_pos =
1337                                                         DWC2_HCSPLT_XACTPOS_MID;
1338                                 break;
1339                         }
1340                 }
1341         } else {
1342                 qtd->error_count = 0;
1343
1344                 if (chan->qh->ping_state) {
1345                         chan->qh->ping_state = 0;
1346                         /*
1347                          * Halt the channel so the transfer can be re-started
1348                          * from the appropriate point. This only happens in
1349                          * Slave mode. In DMA mode, the ping_state is cleared
1350                          * when the transfer is started because the core
1351                          * automatically executes the PING, then the transfer.
1352                          */
1353                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1354                 }
1355         }
1356
1357         /*
1358          * If the ACK occurred when _not_ in the PING state, let the channel
1359          * continue transferring data after clearing the error count
1360          */
1361         disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1362 }
1363
1364 /*
1365  * Handles a host channel NYET interrupt. This interrupt should only occur on
1366  * Bulk and Control OUT endpoints and for complete split transactions. If a
1367  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1368  * handled in the xfercomp interrupt handler, not here. This handler may be
1369  * called in either DMA mode or Slave mode.
1370  */
1371 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1372                               struct dwc2_host_chan *chan, int chnum,
1373                               struct dwc2_qtd *qtd)
1374 {
1375         if (dbg_hc(chan))
1376                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1377                          chnum);
1378
1379         /*
1380          * NYET on CSPLIT
1381          * re-do the CSPLIT immediately on non-periodic
1382          */
1383         if (chan->do_split && chan->complete_split) {
1384                 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1385                     hsotg->core_params->dma_enable > 0) {
1386                         qtd->complete_split = 0;
1387                         qtd->isoc_split_offset = 0;
1388                         qtd->isoc_frame_index++;
1389                         if (qtd->urb &&
1390                             qtd->isoc_frame_index == qtd->urb->packet_count) {
1391                                 dwc2_host_complete(hsotg, qtd, 0);
1392                                 dwc2_release_channel(hsotg, chan, qtd,
1393                                                      DWC2_HC_XFER_URB_COMPLETE);
1394                         } else {
1395                                 dwc2_release_channel(hsotg, chan, qtd,
1396                                                 DWC2_HC_XFER_NO_HALT_STATUS);
1397                         }
1398                         goto handle_nyet_done;
1399                 }
1400
1401                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1402                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1403                         int frnum = dwc2_hcd_get_frame_number(hsotg);
1404
1405                         if (dwc2_full_frame_num(frnum) !=
1406                             dwc2_full_frame_num(chan->qh->sched_frame)) {
1407                                 /*
1408                                  * No longer in the same full speed frame.
1409                                  * Treat this as a transaction error.
1410                                  */
1411 #if 0
1412                                 /*
1413                                  * Todo: Fix system performance so this can
1414                                  * be treated as an error. Right now complete
1415                                  * splits cannot be scheduled precisely enough
1416                                  * due to other system activity, so this error
1417                                  * occurs regularly in Slave mode.
1418                                  */
1419                                 qtd->error_count++;
1420 #endif
1421                                 qtd->complete_split = 0;
1422                                 dwc2_halt_channel(hsotg, chan, qtd,
1423                                                   DWC2_HC_XFER_XACT_ERR);
1424                                 /* Todo: add support for isoc release */
1425                                 goto handle_nyet_done;
1426                         }
1427                 }
1428
1429                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1430                 goto handle_nyet_done;
1431         }
1432
1433         chan->qh->ping_state = 1;
1434         qtd->error_count = 0;
1435
1436         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1437                                   DWC2_HC_XFER_NYET);
1438         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1439
1440         /*
1441          * Halt the channel and re-start the transfer so the PING protocol
1442          * will start
1443          */
1444         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1445
1446 handle_nyet_done:
1447         disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1448 }
1449
1450 /*
1451  * Handles a host channel babble interrupt. This handler may be called in
1452  * either DMA mode or Slave mode.
1453  */
1454 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1455                                 struct dwc2_host_chan *chan, int chnum,
1456                                 struct dwc2_qtd *qtd)
1457 {
1458         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1459                 chnum);
1460
1461         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1462
1463         if (hsotg->core_params->dma_desc_enable > 0) {
1464                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1465                                             DWC2_HC_XFER_BABBLE_ERR);
1466                 goto disable_int;
1467         }
1468
1469         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1470                 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1471                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1472         } else {
1473                 enum dwc2_halt_status halt_status;
1474
1475                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1476                                                 qtd, DWC2_HC_XFER_BABBLE_ERR);
1477                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1478         }
1479
1480 disable_int:
1481         disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1482 }
1483
1484 /*
1485  * Handles a host channel AHB error interrupt. This handler is only called in
1486  * DMA mode.
1487  */
1488 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1489                                 struct dwc2_host_chan *chan, int chnum,
1490                                 struct dwc2_qtd *qtd)
1491 {
1492         struct dwc2_hcd_urb *urb = qtd->urb;
1493         char *pipetype, *speed;
1494         u32 hcchar;
1495         u32 hcsplt;
1496         u32 hctsiz;
1497         u32 hc_dma;
1498
1499         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1500                 chnum);
1501
1502         if (!urb)
1503                 goto handle_ahberr_halt;
1504
1505         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1506
1507         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1508         hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1509         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1510         hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1511
1512         dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1513         dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1514         dev_err(hsotg->dev, "  hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1515         dev_err(hsotg->dev, "  Device address: %d\n",
1516                 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1517         dev_err(hsotg->dev, "  Endpoint: %d, %s\n",
1518                 dwc2_hcd_get_ep_num(&urb->pipe_info),
1519                 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1520
1521         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1522         case USB_ENDPOINT_XFER_CONTROL:
1523                 pipetype = "CONTROL";
1524                 break;
1525         case USB_ENDPOINT_XFER_BULK:
1526                 pipetype = "BULK";
1527                 break;
1528         case USB_ENDPOINT_XFER_INT:
1529                 pipetype = "INTERRUPT";
1530                 break;
1531         case USB_ENDPOINT_XFER_ISOC:
1532                 pipetype = "ISOCHRONOUS";
1533                 break;
1534         default:
1535                 pipetype = "UNKNOWN";
1536                 break;
1537         }
1538
1539         dev_err(hsotg->dev, "  Endpoint type: %s\n", pipetype);
1540
1541         switch (chan->speed) {
1542         case USB_SPEED_HIGH:
1543                 speed = "HIGH";
1544                 break;
1545         case USB_SPEED_FULL:
1546                 speed = "FULL";
1547                 break;
1548         case USB_SPEED_LOW:
1549                 speed = "LOW";
1550                 break;
1551         default:
1552                 speed = "UNKNOWN";
1553                 break;
1554         }
1555
1556         dev_err(hsotg->dev, "  Speed: %s\n", speed);
1557
1558         dev_err(hsotg->dev, "  Max packet size: %d\n",
1559                 dwc2_hcd_get_mps(&urb->pipe_info));
1560         dev_err(hsotg->dev, "  Data buffer length: %d\n", urb->length);
1561         dev_err(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
1562                 urb->buf, (unsigned long)urb->dma);
1563         dev_err(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
1564                 urb->setup_packet, (unsigned long)urb->setup_dma);
1565         dev_err(hsotg->dev, "  Interval: %d\n", urb->interval);
1566
1567         /* Core halts the channel for Descriptor DMA mode */
1568         if (hsotg->core_params->dma_desc_enable > 0) {
1569                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1570                                             DWC2_HC_XFER_AHB_ERR);
1571                 goto handle_ahberr_done;
1572         }
1573
1574         dwc2_host_complete(hsotg, qtd, -EIO);
1575
1576 handle_ahberr_halt:
1577         /*
1578          * Force a channel halt. Don't call dwc2_halt_channel because that won't
1579          * write to the HCCHARn register in DMA mode to force the halt.
1580          */
1581         dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1582
1583 handle_ahberr_done:
1584         disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1585 }
1586
1587 /*
1588  * Handles a host channel transaction error interrupt. This handler may be
1589  * called in either DMA mode or Slave mode.
1590  */
1591 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1592                                  struct dwc2_host_chan *chan, int chnum,
1593                                  struct dwc2_qtd *qtd)
1594 {
1595         dev_dbg(hsotg->dev,
1596                 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1597
1598         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1599
1600         if (hsotg->core_params->dma_desc_enable > 0) {
1601                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1602                                             DWC2_HC_XFER_XACT_ERR);
1603                 goto handle_xacterr_done;
1604         }
1605
1606         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1607         case USB_ENDPOINT_XFER_CONTROL:
1608         case USB_ENDPOINT_XFER_BULK:
1609                 qtd->error_count++;
1610                 if (!chan->qh->ping_state) {
1611
1612                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1613                                                   qtd, DWC2_HC_XFER_XACT_ERR);
1614                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1615                         if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1616                                 chan->qh->ping_state = 1;
1617                 }
1618
1619                 /*
1620                  * Halt the channel so the transfer can be re-started from
1621                  * the appropriate point or the PING protocol will start
1622                  */
1623                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1624                 break;
1625         case USB_ENDPOINT_XFER_INT:
1626                 qtd->error_count++;
1627                 if (chan->do_split && chan->complete_split)
1628                         qtd->complete_split = 0;
1629                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1630                 break;
1631         case USB_ENDPOINT_XFER_ISOC:
1632                 {
1633                         enum dwc2_halt_status halt_status;
1634
1635                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1636                                         chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1637                         dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1638                 }
1639                 break;
1640         }
1641
1642 handle_xacterr_done:
1643         disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1644 }
1645
1646 /*
1647  * Handles a host channel frame overrun interrupt. This handler may be called
1648  * in either DMA mode or Slave mode.
1649  */
1650 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1651                                   struct dwc2_host_chan *chan, int chnum,
1652                                   struct dwc2_qtd *qtd)
1653 {
1654         enum dwc2_halt_status halt_status;
1655
1656         if (dbg_hc(chan))
1657                 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1658                         chnum);
1659
1660         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1661
1662         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1663         case USB_ENDPOINT_XFER_CONTROL:
1664         case USB_ENDPOINT_XFER_BULK:
1665                 break;
1666         case USB_ENDPOINT_XFER_INT:
1667                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1668                 break;
1669         case USB_ENDPOINT_XFER_ISOC:
1670                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1671                                         qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1672                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1673                 break;
1674         }
1675
1676         disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1677 }
1678
1679 /*
1680  * Handles a host channel data toggle error interrupt. This handler may be
1681  * called in either DMA mode or Slave mode.
1682  */
1683 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1684                                     struct dwc2_host_chan *chan, int chnum,
1685                                     struct dwc2_qtd *qtd)
1686 {
1687         dev_dbg(hsotg->dev,
1688                 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1689
1690         if (chan->ep_is_in)
1691                 qtd->error_count = 0;
1692         else
1693                 dev_err(hsotg->dev,
1694                         "Data Toggle Error on OUT transfer, channel %d\n",
1695                         chnum);
1696
1697         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1698         disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1699 }
1700
1701 /*
1702  * For debug only. It checks that a valid halt status is set and that
1703  * HCCHARn.chdis is clear. If there's a problem, corrective action is
1704  * taken and a warning is issued.
1705  *
1706  * Return: true if halt status is ok, false otherwise
1707  */
1708 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1709                                 struct dwc2_host_chan *chan, int chnum,
1710                                 struct dwc2_qtd *qtd)
1711 {
1712 #ifdef DEBUG
1713         u32 hcchar;
1714         u32 hctsiz;
1715         u32 hcintmsk;
1716         u32 hcsplt;
1717
1718         if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1719                 /*
1720                  * This code is here only as a check. This condition should
1721                  * never happen. Ignore the halt if it does occur.
1722                  */
1723                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1724                 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1725                 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1726                 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1727                 dev_dbg(hsotg->dev,
1728                         "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1729                          __func__);
1730                 dev_dbg(hsotg->dev,
1731                         "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1732                         chnum, hcchar, hctsiz);
1733                 dev_dbg(hsotg->dev,
1734                         "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1735                         chan->hcint, hcintmsk, hcsplt);
1736                 if (qtd)
1737                         dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1738                                 qtd->complete_split);
1739                 dev_warn(hsotg->dev,
1740                          "%s: no halt status, channel %d, ignoring interrupt\n",
1741                          __func__, chnum);
1742                 return false;
1743         }
1744
1745         /*
1746          * This code is here only as a check. hcchar.chdis should never be set
1747          * when the halt interrupt occurs. Halt the channel again if it does
1748          * occur.
1749          */
1750         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1751         if (hcchar & HCCHAR_CHDIS) {
1752                 dev_warn(hsotg->dev,
1753                          "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1754                          __func__, hcchar);
1755                 chan->halt_pending = 0;
1756                 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1757                 return false;
1758         }
1759 #endif
1760
1761         return true;
1762 }
1763
1764 /*
1765  * Handles a host Channel Halted interrupt in DMA mode. This handler
1766  * determines the reason the channel halted and proceeds accordingly.
1767  */
1768 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1769                                     struct dwc2_host_chan *chan, int chnum,
1770                                     struct dwc2_qtd *qtd)
1771 {
1772         u32 hcintmsk;
1773         int out_nak_enh = 0;
1774
1775         if (dbg_hc(chan))
1776                 dev_vdbg(hsotg->dev,
1777                          "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1778                          chnum);
1779
1780         /*
1781          * For core with OUT NAK enhancement, the flow for high-speed
1782          * CONTROL/BULK OUT is handled a little differently
1783          */
1784         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1785                 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1786                     (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1787                      chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1788                         out_nak_enh = 1;
1789                 }
1790         }
1791
1792         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1793             (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1794              hsotg->core_params->dma_desc_enable <= 0)) {
1795                 if (hsotg->core_params->dma_desc_enable > 0)
1796                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1797                                                     chan->halt_status);
1798                 else
1799                         /*
1800                          * Just release the channel. A dequeue can happen on a
1801                          * transfer timeout. In the case of an AHB Error, the
1802                          * channel was forced to halt because there's no way to
1803                          * gracefully recover.
1804                          */
1805                         dwc2_release_channel(hsotg, chan, qtd,
1806                                              chan->halt_status);
1807                 return;
1808         }
1809
1810         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1811
1812         if (chan->hcint & HCINTMSK_XFERCOMPL) {
1813                 /*
1814                  * Todo: This is here because of a possible hardware bug. Spec
1815                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1816                  * interrupt w/ACK bit set should occur, but I only see the
1817                  * XFERCOMP bit, even with it masked out. This is a workaround
1818                  * for that behavior. Should fix this when hardware is fixed.
1819                  */
1820                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1821                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1822                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1823         } else if (chan->hcint & HCINTMSK_STALL) {
1824                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1825         } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1826                    hsotg->core_params->dma_desc_enable <= 0) {
1827                 if (out_nak_enh) {
1828                         if (chan->hcint &
1829                             (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1830                                 dev_vdbg(hsotg->dev,
1831                                          "XactErr with NYET/NAK/ACK\n");
1832                                 qtd->error_count = 0;
1833                         } else {
1834                                 dev_vdbg(hsotg->dev,
1835                                          "XactErr without NYET/NAK/ACK\n");
1836                         }
1837                 }
1838
1839                 /*
1840                  * Must handle xacterr before nak or ack. Could get a xacterr
1841                  * at the same time as either of these on a BULK/CONTROL OUT
1842                  * that started with a PING. The xacterr takes precedence.
1843                  */
1844                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1845         } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1846                    hsotg->core_params->dma_desc_enable > 0) {
1847                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1848         } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1849                    hsotg->core_params->dma_desc_enable > 0) {
1850                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1851         } else if (chan->hcint & HCINTMSK_BBLERR) {
1852                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1853         } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1854                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1855         } else if (!out_nak_enh) {
1856                 if (chan->hcint & HCINTMSK_NYET) {
1857                         /*
1858                          * Must handle nyet before nak or ack. Could get a nyet
1859                          * at the same time as either of those on a BULK/CONTROL
1860                          * OUT that started with a PING. The nyet takes
1861                          * precedence.
1862                          */
1863                         dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1864                 } else if ((chan->hcint & HCINTMSK_NAK) &&
1865                            !(hcintmsk & HCINTMSK_NAK)) {
1866                         /*
1867                          * If nak is not masked, it's because a non-split IN
1868                          * transfer is in an error state. In that case, the nak
1869                          * is handled by the nak interrupt handler, not here.
1870                          * Handle nak here for BULK/CONTROL OUT transfers, which
1871                          * halt on a NAK to allow rewinding the buffer pointer.
1872                          */
1873                         dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1874                 } else if ((chan->hcint & HCINTMSK_ACK) &&
1875                            !(hcintmsk & HCINTMSK_ACK)) {
1876                         /*
1877                          * If ack is not masked, it's because a non-split IN
1878                          * transfer is in an error state. In that case, the ack
1879                          * is handled by the ack interrupt handler, not here.
1880                          * Handle ack here for split transfers. Start splits
1881                          * halt on ACK.
1882                          */
1883                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1884                 } else {
1885                         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1886                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1887                                 /*
1888                                  * A periodic transfer halted with no other
1889                                  * channel interrupts set. Assume it was halted
1890                                  * by the core because it could not be completed
1891                                  * in its scheduled (micro)frame.
1892                                  */
1893                                 dev_dbg(hsotg->dev,
1894                                         "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1895                                         __func__, chnum);
1896                                 dwc2_halt_channel(hsotg, chan, qtd,
1897                                         DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1898                         } else {
1899                                 dev_err(hsotg->dev,
1900                                         "%s: Channel %d - ChHltd set, but reason is unknown\n",
1901                                         __func__, chnum);
1902                                 dev_err(hsotg->dev,
1903                                         "hcint 0x%08x, intsts 0x%08x\n",
1904                                         chan->hcint,
1905                                         dwc2_readl(hsotg->regs + GINTSTS));
1906                                 goto error;
1907                         }
1908                 }
1909         } else {
1910                 dev_info(hsotg->dev,
1911                          "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1912                          chan->hcint);
1913 error:
1914                 /* Failthrough: use 3-strikes rule */
1915                 qtd->error_count++;
1916                 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1917                                           qtd, DWC2_HC_XFER_XACT_ERR);
1918                 /*
1919                  * We can get here after a completed transaction
1920                  * (urb->actual_length >= urb->length) which was not reported
1921                  * as completed. If that is the case, and we do not abort
1922                  * the transfer, a transfer of size 0 will be enqueued
1923                  * subsequently. If urb->actual_length is not DMA-aligned,
1924                  * the buffer will then point to an unaligned address, and
1925                  * the resulting behavior is undefined. Bail out in that
1926                  * situation.
1927                  */
1928                 if (qtd->urb->actual_length >= qtd->urb->length)
1929                         qtd->error_count = 3;
1930                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1931                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1932         }
1933 }
1934
1935 /*
1936  * Handles a host channel Channel Halted interrupt
1937  *
1938  * In slave mode, this handler is called only when the driver specifically
1939  * requests a halt. This occurs during handling other host channel interrupts
1940  * (e.g. nak, xacterr, stall, nyet, etc.).
1941  *
1942  * In DMA mode, this is the interrupt that occurs when the core has finished
1943  * processing a transfer on a channel. Other host channel interrupts (except
1944  * ahberr) are disabled in DMA mode.
1945  */
1946 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1947                                 struct dwc2_host_chan *chan, int chnum,
1948                                 struct dwc2_qtd *qtd)
1949 {
1950         if (dbg_hc(chan))
1951                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1952                          chnum);
1953
1954         if (hsotg->core_params->dma_enable > 0) {
1955                 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1956         } else {
1957                 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1958                         return;
1959                 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1960         }
1961 }
1962
1963 /*
1964  * Check if the given qtd is still the top of the list (and thus valid).
1965  *
1966  * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1967  * the qtd from the top of the list, this will return false (otherwise true).
1968  */
1969 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1970 {
1971         struct dwc2_qtd *cur_head;
1972
1973         if (qh == NULL)
1974                 return false;
1975
1976         cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1977                                     qtd_list_entry);
1978         return (cur_head == qtd);
1979 }
1980
1981 /* Handles interrupt for a specific Host Channel */
1982 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1983 {
1984         struct dwc2_qtd *qtd;
1985         struct dwc2_host_chan *chan;
1986         u32 hcint, hcintmsk;
1987
1988         chan = hsotg->hc_ptr_array[chnum];
1989
1990         hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
1991         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1992         if (!chan) {
1993                 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1994                 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
1995                 return;
1996         }
1997
1998         if (dbg_hc(chan)) {
1999                 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
2000                          chnum);
2001                 dev_vdbg(hsotg->dev,
2002                          "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2003                          hcint, hcintmsk, hcint & hcintmsk);
2004         }
2005
2006         dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2007         chan->hcint = hcint;
2008         hcint &= hcintmsk;
2009
2010         /*
2011          * If the channel was halted due to a dequeue, the qtd list might
2012          * be empty or at least the first entry will not be the active qtd.
2013          * In this case, take a shortcut and just release the channel.
2014          */
2015         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2016                 /*
2017                  * If the channel was halted, this should be the only
2018                  * interrupt unmasked
2019                  */
2020                 WARN_ON(hcint != HCINTMSK_CHHLTD);
2021                 if (hsotg->core_params->dma_desc_enable > 0)
2022                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2023                                                     chan->halt_status);
2024                 else
2025                         dwc2_release_channel(hsotg, chan, NULL,
2026                                              chan->halt_status);
2027                 return;
2028         }
2029
2030         if (list_empty(&chan->qh->qtd_list)) {
2031                 /*
2032                  * TODO: Will this ever happen with the
2033                  * DWC2_HC_XFER_URB_DEQUEUE handling above?
2034                  */
2035                 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2036                         chnum);
2037                 dev_dbg(hsotg->dev,
2038                         "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2039                         chan->hcint, hcintmsk, hcint);
2040                 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2041                 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2042                 chan->hcint = 0;
2043                 return;
2044         }
2045
2046         qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2047                                qtd_list_entry);
2048
2049         if (hsotg->core_params->dma_enable <= 0) {
2050                 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2051                         hcint &= ~HCINTMSK_CHHLTD;
2052         }
2053
2054         if (hcint & HCINTMSK_XFERCOMPL) {
2055                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2056                 /*
2057                  * If NYET occurred at same time as Xfer Complete, the NYET is
2058                  * handled by the Xfer Complete interrupt handler. Don't want
2059                  * to call the NYET interrupt handler in this case.
2060                  */
2061                 hcint &= ~HCINTMSK_NYET;
2062         }
2063
2064         if (hcint & HCINTMSK_CHHLTD) {
2065                 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2066                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2067                         goto exit;
2068         }
2069         if (hcint & HCINTMSK_AHBERR) {
2070                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2071                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2072                         goto exit;
2073         }
2074         if (hcint & HCINTMSK_STALL) {
2075                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2076                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2077                         goto exit;
2078         }
2079         if (hcint & HCINTMSK_NAK) {
2080                 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2081                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2082                         goto exit;
2083         }
2084         if (hcint & HCINTMSK_ACK) {
2085                 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2086                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2087                         goto exit;
2088         }
2089         if (hcint & HCINTMSK_NYET) {
2090                 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2091                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2092                         goto exit;
2093         }
2094         if (hcint & HCINTMSK_XACTERR) {
2095                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2096                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2097                         goto exit;
2098         }
2099         if (hcint & HCINTMSK_BBLERR) {
2100                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2101                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2102                         goto exit;
2103         }
2104         if (hcint & HCINTMSK_FRMOVRUN) {
2105                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2106                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2107                         goto exit;
2108         }
2109         if (hcint & HCINTMSK_DATATGLERR) {
2110                 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2111                 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2112                         goto exit;
2113         }
2114
2115 exit:
2116         chan->hcint = 0;
2117 }
2118
2119 /*
2120  * This interrupt indicates that one or more host channels has a pending
2121  * interrupt. There are multiple conditions that can cause each host channel
2122  * interrupt. This function determines which conditions have occurred for each
2123  * host channel interrupt and handles them appropriately.
2124  */
2125 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2126 {
2127         u32 haint;
2128         int i;
2129
2130         haint = dwc2_readl(hsotg->regs + HAINT);
2131         if (dbg_perio()) {
2132                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2133
2134                 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2135         }
2136
2137         for (i = 0; i < hsotg->core_params->host_channels; i++) {
2138                 if (haint & (1 << i))
2139                         dwc2_hc_n_intr(hsotg, i);
2140         }
2141 }
2142
2143 /* This function handles interrupts for the HCD */
2144 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2145 {
2146         u32 gintsts, dbg_gintsts;
2147         irqreturn_t retval = IRQ_NONE;
2148
2149         if (!dwc2_is_controller_alive(hsotg)) {
2150                 dev_warn(hsotg->dev, "Controller is dead\n");
2151                 return retval;
2152         }
2153
2154         spin_lock(&hsotg->lock);
2155
2156         /* Check if HOST Mode */
2157         if (dwc2_is_host_mode(hsotg)) {
2158                 gintsts = dwc2_read_core_intr(hsotg);
2159                 if (!gintsts) {
2160                         spin_unlock(&hsotg->lock);
2161                         return retval;
2162                 }
2163
2164                 retval = IRQ_HANDLED;
2165
2166                 dbg_gintsts = gintsts;
2167 #ifndef DEBUG_SOF
2168                 dbg_gintsts &= ~GINTSTS_SOF;
2169 #endif
2170                 if (!dbg_perio())
2171                         dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2172                                          GINTSTS_PTXFEMP);
2173
2174                 /* Only print if there are any non-suppressed interrupts left */
2175                 if (dbg_gintsts)
2176                         dev_vdbg(hsotg->dev,
2177                                  "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2178                                  gintsts);
2179
2180                 if (gintsts & GINTSTS_SOF)
2181                         dwc2_sof_intr(hsotg);
2182                 if (gintsts & GINTSTS_RXFLVL)
2183                         dwc2_rx_fifo_level_intr(hsotg);
2184                 if (gintsts & GINTSTS_NPTXFEMP)
2185                         dwc2_np_tx_fifo_empty_intr(hsotg);
2186                 if (gintsts & GINTSTS_PRTINT)
2187                         dwc2_port_intr(hsotg);
2188                 if (gintsts & GINTSTS_HCHINT)
2189                         dwc2_hc_intr(hsotg);
2190                 if (gintsts & GINTSTS_PTXFEMP)
2191                         dwc2_perio_tx_fifo_empty_intr(hsotg);
2192
2193                 if (dbg_gintsts) {
2194                         dev_vdbg(hsotg->dev,
2195                                  "DWC OTG HCD Finished Servicing Interrupts\n");
2196                         dev_vdbg(hsotg->dev,
2197                                  "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2198                                  dwc2_readl(hsotg->regs + GINTSTS),
2199                                  dwc2_readl(hsotg->regs + GINTMSK));
2200                 }
2201         }
2202
2203         spin_unlock(&hsotg->lock);
2204
2205         return retval;
2206 }