2 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the core HCD code, and implements the Linux hc_driver
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/delay.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
58 * =========================================================================
59 * Host Core Layer Functions
60 * =========================================================================
64 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
65 * used in both device and host modes
67 * @hsotg: Programming view of the DWC_otg controller
69 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
73 /* Clear any pending OTG Interrupts */
74 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
76 /* Clear any pending interrupts */
77 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
79 /* Enable the interrupts in the GINTMSK */
80 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
82 if (hsotg->core_params->dma_enable <= 0)
83 intmsk |= GINTSTS_RXFLVL;
84 if (hsotg->core_params->external_id_pin_ctl <= 0)
85 intmsk |= GINTSTS_CONIDSTSCHNG;
87 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
90 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
94 * Initializes the FSLSPClkSel field of the HCFG register depending on the
97 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
101 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
102 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
103 hsotg->core_params->ulpi_fs_ls > 0) ||
104 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
106 val = HCFG_FSLSPCLKSEL_48_MHZ;
108 /* High speed PHY running at full speed or high speed */
109 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
112 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
113 hcfg = dwc2_readl(hsotg->regs + HCFG);
114 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
115 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
116 dwc2_writel(hcfg, hsotg->regs + HCFG);
119 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
125 * core_init() is now called on every switch so only call the
126 * following for the first time through
129 dev_dbg(hsotg->dev, "FS PHY selected\n");
131 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
132 if (!(usbcfg & GUSBCFG_PHYSEL)) {
133 usbcfg |= GUSBCFG_PHYSEL;
134 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
136 /* Reset after a PHY select */
137 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
141 "%s: Reset failed, aborting", __func__);
148 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
149 * do this on HNP Dev/Host mode switches (done in dev_init and
152 if (dwc2_is_host_mode(hsotg))
153 dwc2_init_fs_ls_pclk_sel(hsotg);
155 if (hsotg->core_params->i2c_enable > 0) {
156 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
158 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
159 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
160 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
161 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
163 /* Program GI2CCTL.I2CEn */
164 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
165 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
166 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
167 i2cctl &= ~GI2CCTL_I2CEN;
168 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
169 i2cctl |= GI2CCTL_I2CEN;
170 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
176 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
178 u32 usbcfg, usbcfg_old;
184 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
188 * HS PHY parameters. These parameters are preserved during soft reset
189 * so only program the first time. Do a soft reset immediately after
192 switch (hsotg->core_params->phy_type) {
193 case DWC2_PHY_TYPE_PARAM_ULPI:
195 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
196 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
197 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
198 if (hsotg->core_params->phy_ulpi_ddr > 0)
199 usbcfg |= GUSBCFG_DDRSEL;
201 case DWC2_PHY_TYPE_PARAM_UTMI:
202 /* UTMI+ interface */
203 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
204 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
205 if (hsotg->core_params->phy_utmi_width == 16)
206 usbcfg |= GUSBCFG_PHYIF16;
209 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
213 if (usbcfg != usbcfg_old) {
214 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
216 /* Reset after setting the PHY parameters */
217 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
220 "%s: Reset failed, aborting", __func__);
228 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
233 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
234 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
235 /* If FS mode with FS PHY */
236 retval = dwc2_fs_phy_init(hsotg, select_phy);
241 retval = dwc2_hs_phy_init(hsotg, select_phy);
246 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
247 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
248 hsotg->core_params->ulpi_fs_ls > 0) {
249 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
250 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
251 usbcfg |= GUSBCFG_ULPI_FS_LS;
252 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
253 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
255 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
256 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
257 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
258 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
264 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
266 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
268 switch (hsotg->hw_params.arch) {
269 case GHWCFG2_EXT_DMA_ARCH:
270 dev_err(hsotg->dev, "External DMA Mode not supported\n");
273 case GHWCFG2_INT_DMA_ARCH:
274 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
275 if (hsotg->core_params->ahbcfg != -1) {
276 ahbcfg &= GAHBCFG_CTRL_MASK;
277 ahbcfg |= hsotg->core_params->ahbcfg &
282 case GHWCFG2_SLAVE_ONLY_ARCH:
284 dev_dbg(hsotg->dev, "Slave Only Mode\n");
288 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
289 hsotg->core_params->dma_enable,
290 hsotg->core_params->dma_desc_enable);
292 if (hsotg->core_params->dma_enable > 0) {
293 if (hsotg->core_params->dma_desc_enable > 0)
294 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
296 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
298 dev_dbg(hsotg->dev, "Using Slave mode\n");
299 hsotg->core_params->dma_desc_enable = 0;
302 if (hsotg->core_params->dma_enable > 0)
303 ahbcfg |= GAHBCFG_DMA_EN;
305 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
310 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
314 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
315 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
317 switch (hsotg->hw_params.op_mode) {
318 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
319 if (hsotg->core_params->otg_cap ==
320 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
321 usbcfg |= GUSBCFG_HNPCAP;
322 if (hsotg->core_params->otg_cap !=
323 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
324 usbcfg |= GUSBCFG_SRPCAP;
327 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
328 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
329 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
330 if (hsotg->core_params->otg_cap !=
331 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
332 usbcfg |= GUSBCFG_SRPCAP;
335 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
336 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
337 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
342 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
346 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
348 * @hsotg: Programming view of DWC_otg controller
350 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
354 dev_dbg(hsotg->dev, "%s()\n", __func__);
356 /* Disable all interrupts */
357 dwc2_writel(0, hsotg->regs + GINTMSK);
358 dwc2_writel(0, hsotg->regs + HAINTMSK);
360 /* Enable the common interrupts */
361 dwc2_enable_common_interrupts(hsotg);
363 /* Enable host mode interrupts without disturbing common interrupts */
364 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
365 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
366 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
370 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
372 * @hsotg: Programming view of DWC_otg controller
374 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
376 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
378 /* Disable host mode interrupts without disturbing common interrupts */
379 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
380 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
381 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
385 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
386 * For system that have a total fifo depth that is smaller than the default
389 * @hsotg: Programming view of DWC_otg controller
391 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
393 struct dwc2_core_params *params = hsotg->core_params;
394 struct dwc2_hw_params *hw = &hsotg->hw_params;
395 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
397 total_fifo_size = hw->total_fifo_size;
398 rxfsiz = params->host_rx_fifo_size;
399 nptxfsiz = params->host_nperio_tx_fifo_size;
400 ptxfsiz = params->host_perio_tx_fifo_size;
403 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
404 * allocation with support for high bandwidth endpoints. Synopsys
405 * defines MPS(Max Packet size) for a periodic EP=1024, and for
406 * non-periodic as 512.
408 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
410 * For Buffer DMA mode/Scatter Gather DMA mode
411 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
412 * with n = number of host channel.
413 * 2 * ((1024/4) + 2) = 516
415 rxfsiz = 516 + hw->host_channels;
418 * min non-periodic tx fifo depth
419 * 2 * (largest non-periodic USB packet used / 4)
425 * min periodic tx fifo depth
426 * (largest packet size*MC)/4
431 params->host_rx_fifo_size = rxfsiz;
432 params->host_nperio_tx_fifo_size = nptxfsiz;
433 params->host_perio_tx_fifo_size = ptxfsiz;
437 * If the summation of RX, NPTX and PTX fifo sizes is still
438 * bigger than the total_fifo_size, then we have a problem.
440 * We won't be able to allocate as many endpoints. Right now,
441 * we're just printing an error message, but ideally this FIFO
442 * allocation algorithm would be improved in the future.
444 * FIXME improve this FIFO allocation algorithm.
446 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
447 dev_err(hsotg->dev, "invalid fifo sizes\n");
450 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
452 struct dwc2_core_params *params = hsotg->core_params;
453 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
455 if (!params->enable_dynamic_fifo)
458 dwc2_calculate_dynamic_fifo(hsotg);
461 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
462 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
463 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
464 grxfsiz |= params->host_rx_fifo_size <<
465 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
466 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
467 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
468 dwc2_readl(hsotg->regs + GRXFSIZ));
470 /* Non-periodic Tx FIFO */
471 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
472 dwc2_readl(hsotg->regs + GNPTXFSIZ));
473 nptxfsiz = params->host_nperio_tx_fifo_size <<
474 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
475 nptxfsiz |= params->host_rx_fifo_size <<
476 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
477 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
478 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
479 dwc2_readl(hsotg->regs + GNPTXFSIZ));
481 /* Periodic Tx FIFO */
482 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
483 dwc2_readl(hsotg->regs + HPTXFSIZ));
484 hptxfsiz = params->host_perio_tx_fifo_size <<
485 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
486 hptxfsiz |= (params->host_rx_fifo_size +
487 params->host_nperio_tx_fifo_size) <<
488 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
489 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
490 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
491 dwc2_readl(hsotg->regs + HPTXFSIZ));
493 if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
494 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
496 * Global DFIFOCFG calculation for Host mode -
497 * include RxFIFO, NPTXFIFO and HPTXFIFO
499 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
500 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
501 dfifocfg |= (params->host_rx_fifo_size +
502 params->host_nperio_tx_fifo_size +
503 params->host_perio_tx_fifo_size) <<
504 GDFIFOCFG_EPINFOBASE_SHIFT &
505 GDFIFOCFG_EPINFOBASE_MASK;
506 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
511 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
512 * the HFIR register according to PHY type and speed
514 * @hsotg: Programming view of DWC_otg controller
516 * NOTE: The caller can modify the value of the HFIR register only after the
517 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
520 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
524 int clock = 60; /* default value */
526 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
527 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
529 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
530 !(usbcfg & GUSBCFG_PHYIF16))
532 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
533 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
535 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
536 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
538 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
539 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
541 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
542 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
544 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
545 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
547 if ((usbcfg & GUSBCFG_PHYSEL) &&
548 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
551 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
552 /* High speed case */
553 return 125 * clock - 1;
556 return 1000 * clock - 1;
560 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
563 * @core_if: Programming view of DWC_otg controller
564 * @dest: Destination buffer for the packet
565 * @bytes: Number of bytes to copy to the destination
567 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
569 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
570 u32 *data_buf = (u32 *)dest;
571 int word_count = (bytes + 3) / 4;
575 * Todo: Account for the case where dest is not dword aligned. This
576 * requires reading data from the FIFO into a u32 temp buffer, then
577 * moving it into the data buffer.
580 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
582 for (i = 0; i < word_count; i++, data_buf++)
583 *data_buf = dwc2_readl(fifo);
587 * dwc2_dump_channel_info() - Prints the state of a host channel
589 * @hsotg: Programming view of DWC_otg controller
590 * @chan: Pointer to the channel to dump
592 * Must be called with interrupt disabled and spinlock held
594 * NOTE: This function will be removed once the peripheral controller code
595 * is integrated and the driver is stable
597 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
598 struct dwc2_host_chan *chan)
601 int num_channels = hsotg->core_params->host_channels;
612 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
613 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
614 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
615 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
617 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
618 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
620 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
622 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
623 chan->dev_addr, chan->ep_num, chan->ep_is_in);
624 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
625 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
626 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
627 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
628 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
629 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
630 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
631 (unsigned long)chan->xfer_dma);
632 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
633 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
634 dev_dbg(hsotg->dev, " NP inactive sched:\n");
635 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
637 dev_dbg(hsotg->dev, " %p\n", qh);
638 dev_dbg(hsotg->dev, " NP active sched:\n");
639 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
641 dev_dbg(hsotg->dev, " %p\n", qh);
642 dev_dbg(hsotg->dev, " Channels:\n");
643 for (i = 0; i < num_channels; i++) {
644 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
646 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
648 #endif /* VERBOSE_DEBUG */
652 * =========================================================================
653 * Low Level Host Channel Access Functions
654 * =========================================================================
657 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
658 struct dwc2_host_chan *chan)
660 u32 hcintmsk = HCINTMSK_CHHLTD;
662 switch (chan->ep_type) {
663 case USB_ENDPOINT_XFER_CONTROL:
664 case USB_ENDPOINT_XFER_BULK:
665 dev_vdbg(hsotg->dev, "control/bulk\n");
666 hcintmsk |= HCINTMSK_XFERCOMPL;
667 hcintmsk |= HCINTMSK_STALL;
668 hcintmsk |= HCINTMSK_XACTERR;
669 hcintmsk |= HCINTMSK_DATATGLERR;
670 if (chan->ep_is_in) {
671 hcintmsk |= HCINTMSK_BBLERR;
673 hcintmsk |= HCINTMSK_NAK;
674 hcintmsk |= HCINTMSK_NYET;
676 hcintmsk |= HCINTMSK_ACK;
679 if (chan->do_split) {
680 hcintmsk |= HCINTMSK_NAK;
681 if (chan->complete_split)
682 hcintmsk |= HCINTMSK_NYET;
684 hcintmsk |= HCINTMSK_ACK;
687 if (chan->error_state)
688 hcintmsk |= HCINTMSK_ACK;
691 case USB_ENDPOINT_XFER_INT:
693 dev_vdbg(hsotg->dev, "intr\n");
694 hcintmsk |= HCINTMSK_XFERCOMPL;
695 hcintmsk |= HCINTMSK_NAK;
696 hcintmsk |= HCINTMSK_STALL;
697 hcintmsk |= HCINTMSK_XACTERR;
698 hcintmsk |= HCINTMSK_DATATGLERR;
699 hcintmsk |= HCINTMSK_FRMOVRUN;
702 hcintmsk |= HCINTMSK_BBLERR;
703 if (chan->error_state)
704 hcintmsk |= HCINTMSK_ACK;
705 if (chan->do_split) {
706 if (chan->complete_split)
707 hcintmsk |= HCINTMSK_NYET;
709 hcintmsk |= HCINTMSK_ACK;
713 case USB_ENDPOINT_XFER_ISOC:
715 dev_vdbg(hsotg->dev, "isoc\n");
716 hcintmsk |= HCINTMSK_XFERCOMPL;
717 hcintmsk |= HCINTMSK_FRMOVRUN;
718 hcintmsk |= HCINTMSK_ACK;
720 if (chan->ep_is_in) {
721 hcintmsk |= HCINTMSK_XACTERR;
722 hcintmsk |= HCINTMSK_BBLERR;
726 dev_err(hsotg->dev, "## Unknown EP type ##\n");
730 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
732 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
735 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
736 struct dwc2_host_chan *chan)
738 u32 hcintmsk = HCINTMSK_CHHLTD;
741 * For Descriptor DMA mode core halts the channel on AHB error.
742 * Interrupt is not required.
744 if (hsotg->core_params->dma_desc_enable <= 0) {
746 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
747 hcintmsk |= HCINTMSK_AHBERR;
750 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
751 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
752 hcintmsk |= HCINTMSK_XFERCOMPL;
755 if (chan->error_state && !chan->do_split &&
756 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
758 dev_vdbg(hsotg->dev, "setting ACK\n");
759 hcintmsk |= HCINTMSK_ACK;
760 if (chan->ep_is_in) {
761 hcintmsk |= HCINTMSK_DATATGLERR;
762 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
763 hcintmsk |= HCINTMSK_NAK;
767 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
769 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
772 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
773 struct dwc2_host_chan *chan)
777 if (hsotg->core_params->dma_enable > 0) {
779 dev_vdbg(hsotg->dev, "DMA enabled\n");
780 dwc2_hc_enable_dma_ints(hsotg, chan);
783 dev_vdbg(hsotg->dev, "DMA disabled\n");
784 dwc2_hc_enable_slave_ints(hsotg, chan);
787 /* Enable the top level host channel interrupt */
788 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
789 intmsk |= 1 << chan->hc_num;
790 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
792 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
794 /* Make sure host channel interrupts are enabled */
795 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
796 intmsk |= GINTSTS_HCHINT;
797 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
799 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
803 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
804 * a specific endpoint
806 * @hsotg: Programming view of DWC_otg controller
807 * @chan: Information needed to initialize the host channel
809 * The HCCHARn register is set up with the characteristics specified in chan.
810 * Host channel interrupts that may need to be serviced while this transfer is
811 * in progress are enabled.
813 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
815 u8 hc_num = chan->hc_num;
821 dev_vdbg(hsotg->dev, "%s()\n", __func__);
823 /* Clear old interrupt conditions for this host channel */
824 hcintmsk = 0xffffffff;
825 hcintmsk &= ~HCINTMSK_RESERVED14_31;
826 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
828 /* Enable channel interrupts required for this transfer */
829 dwc2_hc_enable_ints(hsotg, chan);
832 * Program the HCCHARn register with the endpoint characteristics for
833 * the current transfer
835 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
836 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
838 hcchar |= HCCHAR_EPDIR;
839 if (chan->speed == USB_SPEED_LOW)
840 hcchar |= HCCHAR_LSPDDEV;
841 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
842 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
843 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
845 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
848 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
850 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
852 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
854 dev_vdbg(hsotg->dev, " Is In: %d\n",
856 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
857 chan->speed == USB_SPEED_LOW);
858 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
860 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
864 /* Program the HCSPLT register for SPLITs */
865 if (chan->do_split) {
868 "Programming HC %d with split --> %s\n",
870 chan->complete_split ? "CSPLIT" : "SSPLIT");
871 if (chan->complete_split)
872 hcsplt |= HCSPLT_COMPSPLT;
873 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
875 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
877 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
880 dev_vdbg(hsotg->dev, " comp split %d\n",
881 chan->complete_split);
882 dev_vdbg(hsotg->dev, " xact pos %d\n",
884 dev_vdbg(hsotg->dev, " hub addr %d\n",
886 dev_vdbg(hsotg->dev, " hub port %d\n",
888 dev_vdbg(hsotg->dev, " is_in %d\n",
890 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
892 dev_vdbg(hsotg->dev, " xferlen %d\n",
897 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
901 * dwc2_hc_halt() - Attempts to halt a host channel
903 * @hsotg: Controller register interface
904 * @chan: Host channel to halt
905 * @halt_status: Reason for halting the channel
907 * This function should only be called in Slave mode or to abort a transfer in
908 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
909 * controller halts the channel when the transfer is complete or a condition
910 * occurs that requires application intervention.
912 * In slave mode, checks for a free request queue entry, then sets the Channel
913 * Enable and Channel Disable bits of the Host Channel Characteristics
914 * register of the specified channel to intiate the halt. If there is no free
915 * request queue entry, sets only the Channel Disable bit of the HCCHARn
916 * register to flush requests for this channel. In the latter case, sets a
917 * flag to indicate that the host channel needs to be halted when a request
918 * queue slot is open.
920 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
921 * HCCHARn register. The controller ensures there is space in the request
922 * queue before submitting the halt request.
924 * Some time may elapse before the core flushes any posted requests for this
925 * host channel and halts. The Channel Halted interrupt handler completes the
926 * deactivation of the host channel.
928 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
929 enum dwc2_halt_status halt_status)
931 u32 nptxsts, hptxsts, hcchar;
934 dev_vdbg(hsotg->dev, "%s()\n", __func__);
935 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
936 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
938 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
939 halt_status == DWC2_HC_XFER_AHB_ERR) {
941 * Disable all channel interrupts except Ch Halted. The QTD
942 * and QH state associated with this transfer has been cleared
943 * (in the case of URB_DEQUEUE), so the channel needs to be
944 * shut down carefully to prevent crashes.
946 u32 hcintmsk = HCINTMSK_CHHLTD;
948 dev_vdbg(hsotg->dev, "dequeue/error\n");
949 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
952 * Make sure no other interrupts besides halt are currently
953 * pending. Handling another interrupt could cause a crash due
954 * to the QTD and QH state.
956 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
959 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
960 * even if the channel was already halted for some other
963 chan->halt_status = halt_status;
965 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
966 if (!(hcchar & HCCHAR_CHENA)) {
968 * The channel is either already halted or it hasn't
969 * started yet. In DMA mode, the transfer may halt if
970 * it finishes normally or a condition occurs that
971 * requires driver intervention. Don't want to halt
972 * the channel again. In either Slave or DMA mode,
973 * it's possible that the transfer has been assigned
974 * to a channel, but not started yet when an URB is
975 * dequeued. Don't want to halt a channel that hasn't
981 if (chan->halt_pending) {
983 * A halt has already been issued for this channel. This might
984 * happen when a transfer is aborted by a higher level in
988 "*** %s: Channel %d, chan->halt_pending already set ***\n",
989 __func__, chan->hc_num);
993 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
995 /* No need to set the bit in DDMA for disabling the channel */
996 /* TODO check it everywhere channel is disabled */
997 if (hsotg->core_params->dma_desc_enable <= 0) {
999 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1000 hcchar |= HCCHAR_CHENA;
1003 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1005 hcchar |= HCCHAR_CHDIS;
1007 if (hsotg->core_params->dma_enable <= 0) {
1009 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1010 hcchar |= HCCHAR_CHENA;
1012 /* Check for space in the request queue to issue the halt */
1013 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1014 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1015 dev_vdbg(hsotg->dev, "control/bulk\n");
1016 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1017 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1018 dev_vdbg(hsotg->dev, "Disabling channel\n");
1019 hcchar &= ~HCCHAR_CHENA;
1023 dev_vdbg(hsotg->dev, "isoc/intr\n");
1024 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1025 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1026 hsotg->queuing_high_bandwidth) {
1028 dev_vdbg(hsotg->dev, "Disabling channel\n");
1029 hcchar &= ~HCCHAR_CHENA;
1034 dev_vdbg(hsotg->dev, "DMA enabled\n");
1037 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1038 chan->halt_status = halt_status;
1040 if (hcchar & HCCHAR_CHENA) {
1042 dev_vdbg(hsotg->dev, "Channel enabled\n");
1043 chan->halt_pending = 1;
1044 chan->halt_on_queue = 0;
1047 dev_vdbg(hsotg->dev, "Channel disabled\n");
1048 chan->halt_on_queue = 1;
1052 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1054 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1056 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1057 chan->halt_pending);
1058 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1059 chan->halt_on_queue);
1060 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1066 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1068 * @hsotg: Programming view of DWC_otg controller
1069 * @chan: Identifies the host channel to clean up
1071 * This function is normally called after a transfer is done and the host
1072 * channel is being released
1074 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1078 chan->xfer_started = 0;
1080 list_del_init(&chan->split_order_list_entry);
1083 * Clear channel interrupt enables and any unhandled channel interrupt
1086 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1087 hcintmsk = 0xffffffff;
1088 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1089 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1093 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1094 * which frame a periodic transfer should occur
1096 * @hsotg: Programming view of DWC_otg controller
1097 * @chan: Identifies the host channel to set up and its properties
1098 * @hcchar: Current value of the HCCHAR register for the specified host channel
1100 * This function has no effect on non-periodic transfers
1102 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1103 struct dwc2_host_chan *chan, u32 *hcchar)
1105 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1106 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1116 * Try to figure out if we're an even or odd frame. If we set
1117 * even and the current frame number is even the the transfer
1118 * will happen immediately. Similar if both are odd. If one is
1119 * even and the other is odd then the transfer will happen when
1120 * the frame number ticks.
1122 * There's a bit of a balancing act to get this right.
1123 * Sometimes we may want to send data in the current frame (AK
1124 * right away). We might want to do this if the frame number
1125 * _just_ ticked, but we might also want to do this in order
1126 * to continue a split transaction that happened late in a
1127 * microframe (so we didn't know to queue the next transfer
1128 * until the frame number had ticked). The problem is that we
1129 * need a lot of knowledge to know if there's actually still
1130 * time to send things or if it would be better to wait until
1133 * We can look at how much time is left in the current frame
1134 * and make a guess about whether we'll have time to transfer.
1138 /* Get speed host is running at */
1139 host_speed = (chan->speed != USB_SPEED_HIGH &&
1140 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1142 /* See how many bytes are in the periodic FIFO right now */
1143 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1144 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1145 bytes_in_fifo = sizeof(u32) *
1146 (hsotg->core_params->host_perio_tx_fifo_size -
1150 * Roughly estimate bus time for everything in the periodic
1151 * queue + our new transfer. This is "rough" because we're
1152 * using a function that makes takes into account IN/OUT
1153 * and INT/ISO and we're just slamming in one value for all
1154 * transfers. This should be an over-estimate and that should
1155 * be OK, but we can probably tighten it.
1157 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1158 chan->xfer_len + bytes_in_fifo);
1159 xfer_us = NS_TO_US(xfer_ns);
1161 /* See what frame number we'll be at by the time we finish */
1162 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1164 /* This is when we were scheduled to be on the wire */
1165 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1168 * If we'd finish _after_ the frame we're scheduled in then
1169 * it's hopeless. Just schedule right away and hope for the
1170 * best. Note that it _might_ be wise to call back into the
1171 * scheduler to pick a better frame, but this is better than
1174 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1175 dwc2_sch_vdbg(hsotg,
1176 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1177 chan->qh, wire_frame, frame_number,
1178 dwc2_frame_num_dec(frame_number,
1180 wire_frame = frame_number;
1183 * We picked a different frame number; communicate this
1184 * back to the scheduler so it doesn't try to schedule
1185 * another in the same frame.
1187 * Remember that next_active_frame is 1 before the wire
1190 chan->qh->next_active_frame =
1191 dwc2_frame_num_dec(frame_number, 1);
1195 *hcchar |= HCCHAR_ODDFRM;
1197 *hcchar &= ~HCCHAR_ODDFRM;
1201 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1203 /* Set up the initial PID for the transfer */
1204 if (chan->speed == USB_SPEED_HIGH) {
1205 if (chan->ep_is_in) {
1206 if (chan->multi_count == 1)
1207 chan->data_pid_start = DWC2_HC_PID_DATA0;
1208 else if (chan->multi_count == 2)
1209 chan->data_pid_start = DWC2_HC_PID_DATA1;
1211 chan->data_pid_start = DWC2_HC_PID_DATA2;
1213 if (chan->multi_count == 1)
1214 chan->data_pid_start = DWC2_HC_PID_DATA0;
1216 chan->data_pid_start = DWC2_HC_PID_MDATA;
1219 chan->data_pid_start = DWC2_HC_PID_DATA0;
1224 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1227 * @hsotg: Programming view of DWC_otg controller
1228 * @chan: Information needed to initialize the host channel
1230 * This function should only be called in Slave mode. For a channel associated
1231 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1232 * associated with a periodic EP, the periodic Tx FIFO is written.
1234 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1235 * the number of bytes written to the Tx FIFO.
1237 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1238 struct dwc2_host_chan *chan)
1241 u32 remaining_count;
1244 u32 __iomem *data_fifo;
1245 u32 *data_buf = (u32 *)chan->xfer_buf;
1248 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1250 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1252 remaining_count = chan->xfer_len - chan->xfer_count;
1253 if (remaining_count > chan->max_packet)
1254 byte_count = chan->max_packet;
1256 byte_count = remaining_count;
1258 dword_count = (byte_count + 3) / 4;
1260 if (((unsigned long)data_buf & 0x3) == 0) {
1261 /* xfer_buf is DWORD aligned */
1262 for (i = 0; i < dword_count; i++, data_buf++)
1263 dwc2_writel(*data_buf, data_fifo);
1265 /* xfer_buf is not DWORD aligned */
1266 for (i = 0; i < dword_count; i++, data_buf++) {
1267 u32 data = data_buf[0] | data_buf[1] << 8 |
1268 data_buf[2] << 16 | data_buf[3] << 24;
1269 dwc2_writel(data, data_fifo);
1273 chan->xfer_count += byte_count;
1274 chan->xfer_buf += byte_count;
1278 * dwc2_hc_do_ping() - Starts a PING transfer
1280 * @hsotg: Programming view of DWC_otg controller
1281 * @chan: Information needed to initialize the host channel
1283 * This function should only be called in Slave mode. The Do Ping bit is set in
1284 * the HCTSIZ register, then the channel is enabled.
1286 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1287 struct dwc2_host_chan *chan)
1293 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1296 hctsiz = TSIZ_DOPNG;
1297 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1298 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1300 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1301 hcchar |= HCCHAR_CHENA;
1302 hcchar &= ~HCCHAR_CHDIS;
1303 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1307 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1308 * channel and starts the transfer
1310 * @hsotg: Programming view of DWC_otg controller
1311 * @chan: Information needed to initialize the host channel. The xfer_len value
1312 * may be reduced to accommodate the max widths of the XferSize and
1313 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1314 * changed to reflect the final xfer_len value.
1316 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1317 * the caller must ensure that there is sufficient space in the request queue
1320 * For an OUT transfer in Slave mode, it loads a data packet into the
1321 * appropriate FIFO. If necessary, additional data packets are loaded in the
1324 * For an IN transfer in Slave mode, a data packet is requested. The data
1325 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1326 * additional data packets are requested in the Host ISR.
1328 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1329 * register along with a packet count of 1 and the channel is enabled. This
1330 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1331 * simply set to 0 since no data transfer occurs in this case.
1333 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1334 * all the information required to perform the subsequent data transfer. In
1335 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1336 * controller performs the entire PING protocol, then starts the data
1339 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1340 struct dwc2_host_chan *chan)
1342 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
1343 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
1350 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1352 if (chan->do_ping) {
1353 if (hsotg->core_params->dma_enable <= 0) {
1355 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1356 dwc2_hc_do_ping(hsotg, chan);
1357 chan->xfer_started = 1;
1362 dev_vdbg(hsotg->dev, "ping, DMA\n");
1364 hctsiz |= TSIZ_DOPNG;
1367 if (chan->do_split) {
1369 dev_vdbg(hsotg->dev, "split\n");
1372 if (chan->complete_split && !chan->ep_is_in)
1374 * For CSPLIT OUT Transfer, set the size to 0 so the
1375 * core doesn't expect any data written to the FIFO
1378 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1379 chan->xfer_len = chan->max_packet;
1380 else if (!chan->ep_is_in && chan->xfer_len > 188)
1381 chan->xfer_len = 188;
1383 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1386 /* For split set ec_mc for immediate retries */
1387 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1388 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1394 dev_vdbg(hsotg->dev, "no split\n");
1396 * Ensure that the transfer length and packet count will fit
1397 * in the widths allocated for them in the HCTSIZn register
1399 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1400 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1402 * Make sure the transfer size is no larger than one
1403 * (micro)frame's worth of data. (A check was done
1404 * when the periodic transfer was accepted to ensure
1405 * that a (micro)frame's worth of data can be
1406 * programmed into a channel.)
1408 u32 max_periodic_len =
1409 chan->multi_count * chan->max_packet;
1411 if (chan->xfer_len > max_periodic_len)
1412 chan->xfer_len = max_periodic_len;
1413 } else if (chan->xfer_len > max_hc_xfer_size) {
1415 * Make sure that xfer_len is a multiple of max packet
1419 max_hc_xfer_size - chan->max_packet + 1;
1422 if (chan->xfer_len > 0) {
1423 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1425 if (num_packets > max_hc_pkt_count) {
1426 num_packets = max_hc_pkt_count;
1427 chan->xfer_len = num_packets * chan->max_packet;
1428 } else if (chan->ep_is_in) {
1430 * Always program an integral # of max packets
1432 * Note: This assumes that the input buffer is
1433 * aligned and sized accordingly.
1435 chan->xfer_len = num_packets * chan->max_packet;
1438 /* Need 1 packet for transfer length of 0 */
1442 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1443 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1445 * Make sure that the multi_count field matches the
1446 * actual transfer length
1448 chan->multi_count = num_packets;
1450 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1451 dwc2_set_pid_isoc(chan);
1453 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1456 /* The ec_mc gets the multi_count for non-split */
1457 ec_mc = chan->multi_count;
1460 chan->start_pkt_count = num_packets;
1461 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1462 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1463 TSIZ_SC_MC_PID_MASK;
1464 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1466 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1467 hctsiz, chan->hc_num);
1469 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1471 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1472 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1473 TSIZ_XFERSIZE_SHIFT);
1474 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1475 (hctsiz & TSIZ_PKTCNT_MASK) >>
1477 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1478 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1479 TSIZ_SC_MC_PID_SHIFT);
1482 if (hsotg->core_params->dma_enable > 0) {
1483 dwc2_writel((u32)chan->xfer_dma,
1484 hsotg->regs + HCDMA(chan->hc_num));
1486 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1487 (unsigned long)chan->xfer_dma, chan->hc_num);
1490 /* Start the split */
1491 if (chan->do_split) {
1492 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1494 hcsplt |= HCSPLT_SPLTENA;
1495 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1498 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1499 hcchar &= ~HCCHAR_MULTICNT_MASK;
1500 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1501 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1503 if (hcchar & HCCHAR_CHDIS)
1504 dev_warn(hsotg->dev,
1505 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1506 __func__, chan->hc_num, hcchar);
1508 /* Set host channel enable after all other setup is complete */
1509 hcchar |= HCCHAR_CHENA;
1510 hcchar &= ~HCCHAR_CHDIS;
1513 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1514 (hcchar & HCCHAR_MULTICNT_MASK) >>
1515 HCCHAR_MULTICNT_SHIFT);
1517 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1519 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1522 chan->xfer_started = 1;
1525 if (hsotg->core_params->dma_enable <= 0 &&
1526 !chan->ep_is_in && chan->xfer_len > 0)
1527 /* Load OUT packet into the appropriate Tx FIFO */
1528 dwc2_hc_write_packet(hsotg, chan);
1532 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1533 * host channel and starts the transfer in Descriptor DMA mode
1535 * @hsotg: Programming view of DWC_otg controller
1536 * @chan: Information needed to initialize the host channel
1538 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1539 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1540 * with micro-frame bitmap.
1542 * Initializes HCDMA register with descriptor list address and CTD value then
1543 * starts the transfer via enabling the channel.
1545 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1546 struct dwc2_host_chan *chan)
1552 hctsiz |= TSIZ_DOPNG;
1554 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1555 dwc2_set_pid_isoc(chan);
1557 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1558 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1559 TSIZ_SC_MC_PID_MASK;
1561 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1562 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1564 /* Non-zero only for high-speed interrupt endpoints */
1565 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1568 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1570 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1571 chan->data_pid_start);
1572 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1575 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1577 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1578 chan->desc_list_sz, DMA_TO_DEVICE);
1580 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1583 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1584 &chan->desc_list_addr, chan->hc_num);
1586 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1587 hcchar &= ~HCCHAR_MULTICNT_MASK;
1588 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1589 HCCHAR_MULTICNT_MASK;
1591 if (hcchar & HCCHAR_CHDIS)
1592 dev_warn(hsotg->dev,
1593 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1594 __func__, chan->hc_num, hcchar);
1596 /* Set host channel enable after all other setup is complete */
1597 hcchar |= HCCHAR_CHENA;
1598 hcchar &= ~HCCHAR_CHDIS;
1601 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1602 (hcchar & HCCHAR_MULTICNT_MASK) >>
1603 HCCHAR_MULTICNT_SHIFT);
1605 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1607 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1610 chan->xfer_started = 1;
1615 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1616 * a previous call to dwc2_hc_start_transfer()
1618 * @hsotg: Programming view of DWC_otg controller
1619 * @chan: Information needed to initialize the host channel
1621 * The caller must ensure there is sufficient space in the request queue and Tx
1622 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1623 * the controller acts autonomously to complete transfers programmed to a host
1626 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1627 * if there is any data remaining to be queued. For an IN transfer, another
1628 * data packet is always requested. For the SETUP phase of a control transfer,
1629 * this function does nothing.
1631 * Return: 1 if a new request is queued, 0 if no more requests are required
1634 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1635 struct dwc2_host_chan *chan)
1638 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1642 /* SPLITs always queue just once per channel */
1645 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1646 /* SETUPs are queued only once since they can't be NAK'd */
1649 if (chan->ep_is_in) {
1651 * Always queue another request for other IN transfers. If
1652 * back-to-back INs are issued and NAKs are received for both,
1653 * the driver may still be processing the first NAK when the
1654 * second NAK is received. When the interrupt handler clears
1655 * the NAK interrupt for the first NAK, the second NAK will
1656 * not be seen. So we can't depend on the NAK interrupt
1657 * handler to requeue a NAK'd request. Instead, IN requests
1658 * are issued each time this function is called. When the
1659 * transfer completes, the extra requests for the channel will
1662 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1664 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1665 hcchar |= HCCHAR_CHENA;
1666 hcchar &= ~HCCHAR_CHDIS;
1668 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1670 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1677 if (chan->xfer_count < chan->xfer_len) {
1678 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1679 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1680 u32 hcchar = dwc2_readl(hsotg->regs +
1681 HCCHAR(chan->hc_num));
1683 dwc2_hc_set_even_odd_frame(hsotg, chan,
1687 /* Load OUT packet into the appropriate Tx FIFO */
1688 dwc2_hc_write_packet(hsotg, chan);
1697 * =========================================================================
1699 * =========================================================================
1703 * Processes all the URBs in a single list of QHs. Completes them with
1704 * -ETIMEDOUT and frees the QTD.
1706 * Must be called with interrupt disabled and spinlock held
1708 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1709 struct list_head *qh_list)
1711 struct dwc2_qh *qh, *qh_tmp;
1712 struct dwc2_qtd *qtd, *qtd_tmp;
1714 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1715 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1717 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1718 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1723 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1724 struct list_head *qh_list)
1726 struct dwc2_qtd *qtd, *qtd_tmp;
1727 struct dwc2_qh *qh, *qh_tmp;
1728 unsigned long flags;
1731 /* The list hasn't been initialized yet */
1734 spin_lock_irqsave(&hsotg->lock, flags);
1736 /* Ensure there are no QTDs or URBs left */
1737 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1739 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1740 dwc2_hcd_qh_unlink(hsotg, qh);
1742 /* Free each QTD in the QH's QTD list */
1743 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1745 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1747 if (qh->channel && qh->channel->qh == qh)
1748 qh->channel->qh = NULL;
1750 spin_unlock_irqrestore(&hsotg->lock, flags);
1751 dwc2_hcd_qh_free(hsotg, qh);
1752 spin_lock_irqsave(&hsotg->lock, flags);
1755 spin_unlock_irqrestore(&hsotg->lock, flags);
1759 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1760 * and periodic schedules. The QTD associated with each URB is removed from
1761 * the schedule and freed. This function may be called when a disconnect is
1762 * detected or when the HCD is being stopped.
1764 * Must be called with interrupt disabled and spinlock held
1766 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1768 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1769 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1770 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1771 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1772 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1773 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1777 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1779 * @hsotg: Pointer to struct dwc2_hsotg
1781 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1785 if (hsotg->op_state == OTG_STATE_B_HOST) {
1787 * Reset the port. During a HNP mode switch the reset
1788 * needs to occur within 1ms and have a duration of at
1791 hprt0 = dwc2_read_hprt0(hsotg);
1793 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1796 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1797 msecs_to_jiffies(50));
1800 /* Must be called with interrupt disabled and spinlock held */
1801 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1803 int num_channels = hsotg->core_params->host_channels;
1804 struct dwc2_host_chan *channel;
1808 if (hsotg->core_params->dma_enable <= 0) {
1809 /* Flush out any channel requests in slave mode */
1810 for (i = 0; i < num_channels; i++) {
1811 channel = hsotg->hc_ptr_array[i];
1812 if (!list_empty(&channel->hc_list_entry))
1814 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1815 if (hcchar & HCCHAR_CHENA) {
1816 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1817 hcchar |= HCCHAR_CHDIS;
1818 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1823 for (i = 0; i < num_channels; i++) {
1824 channel = hsotg->hc_ptr_array[i];
1825 if (!list_empty(&channel->hc_list_entry))
1827 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1828 if (hcchar & HCCHAR_CHENA) {
1829 /* Halt the channel */
1830 hcchar |= HCCHAR_CHDIS;
1831 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1834 dwc2_hc_cleanup(hsotg, channel);
1835 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1837 * Added for Descriptor DMA to prevent channel double cleanup in
1838 * release_channel_ddma(), which is called from ep_disable when
1839 * device disconnects
1843 /* All channels have been freed, mark them available */
1844 if (hsotg->core_params->uframe_sched > 0) {
1845 hsotg->available_host_channels =
1846 hsotg->core_params->host_channels;
1848 hsotg->non_periodic_channels = 0;
1849 hsotg->periodic_channels = 0;
1854 * dwc2_hcd_connect() - Handles connect of the HCD
1856 * @hsotg: Pointer to struct dwc2_hsotg
1858 * Must be called with interrupt disabled and spinlock held
1860 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1862 if (hsotg->lx_state != DWC2_L0)
1863 usb_hcd_resume_root_hub(hsotg->priv);
1865 hsotg->flags.b.port_connect_status_change = 1;
1866 hsotg->flags.b.port_connect_status = 1;
1870 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1872 * @hsotg: Pointer to struct dwc2_hsotg
1873 * @force: If true, we won't try to reconnect even if we see device connected.
1875 * Must be called with interrupt disabled and spinlock held
1877 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1882 /* Set status flags for the hub driver */
1883 hsotg->flags.b.port_connect_status_change = 1;
1884 hsotg->flags.b.port_connect_status = 0;
1887 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1888 * interrupt mask and status bits and disabling subsequent host
1889 * channel interrupts.
1891 intr = dwc2_readl(hsotg->regs + GINTMSK);
1892 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1893 dwc2_writel(intr, hsotg->regs + GINTMSK);
1894 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1895 dwc2_writel(intr, hsotg->regs + GINTSTS);
1898 * Turn off the vbus power only if the core has transitioned to device
1899 * mode. If still in host mode, need to keep power on to detect a
1902 if (dwc2_is_device_mode(hsotg)) {
1903 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1904 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1905 dwc2_writel(0, hsotg->regs + HPRT0);
1908 dwc2_disable_host_interrupts(hsotg);
1911 /* Respond with an error status to all URBs in the schedule */
1912 dwc2_kill_all_urbs(hsotg);
1914 if (dwc2_is_host_mode(hsotg))
1915 /* Clean up any host channels that were in use */
1916 dwc2_hcd_cleanup_channels(hsotg);
1918 dwc2_host_disconnect(hsotg);
1921 * Add an extra check here to see if we're actually connected but
1922 * we don't have a detection interrupt pending. This can happen if:
1923 * 1. hardware sees connect
1924 * 2. hardware sees disconnect
1925 * 3. hardware sees connect
1926 * 4. dwc2_port_intr() - clears connect interrupt
1927 * 5. dwc2_handle_common_intr() - calls here
1929 * Without the extra check here we will end calling disconnect
1930 * and won't get any future interrupts to handle the connect.
1933 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1934 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
1935 dwc2_hcd_connect(hsotg);
1940 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1942 * @hsotg: Pointer to struct dwc2_hsotg
1944 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1946 if (hsotg->bus_suspended) {
1947 hsotg->flags.b.port_suspend_change = 1;
1948 usb_hcd_resume_root_hub(hsotg->priv);
1951 if (hsotg->lx_state == DWC2_L1)
1952 hsotg->flags.b.port_l1_change = 1;
1956 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
1958 * @hsotg: Pointer to struct dwc2_hsotg
1960 * Must be called with interrupt disabled and spinlock held
1962 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1964 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1967 * The root hub should be disconnected before this function is called.
1968 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1969 * and the QH lists (via ..._hcd_endpoint_disable).
1972 /* Turn off all host-specific interrupts */
1973 dwc2_disable_host_interrupts(hsotg);
1975 /* Turn off the vbus power */
1976 dev_dbg(hsotg->dev, "PortPower off\n");
1977 dwc2_writel(0, hsotg->regs + HPRT0);
1980 /* Caller must hold driver lock */
1981 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
1982 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
1983 struct dwc2_qtd *qtd)
1989 if (!hsotg->flags.b.port_connect_status) {
1990 /* No longer connected */
1991 dev_err(hsotg->dev, "Not connected\n");
1995 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1997 /* Some configurations cannot support LS traffic on a FS root port */
1998 if ((dev_speed == USB_SPEED_LOW) &&
1999 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2000 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2001 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2002 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2004 if (prtspd == HPRT0_SPD_FULL_SPEED)
2011 dwc2_hcd_qtd_init(qtd, urb);
2012 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2015 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2020 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2021 if (!(intr_mask & GINTSTS_SOF)) {
2022 enum dwc2_transaction_type tr_type;
2024 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2025 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2027 * Do not schedule SG transactions until qtd has
2028 * URB_GIVEBACK_ASAP set
2032 tr_type = dwc2_hcd_select_transactions(hsotg);
2033 if (tr_type != DWC2_TRANSACTION_NONE)
2034 dwc2_hcd_queue_transactions(hsotg, tr_type);
2040 /* Must be called with interrupt disabled and spinlock held */
2041 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2042 struct dwc2_hcd_urb *urb)
2045 struct dwc2_qtd *urb_qtd;
2049 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2055 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2061 if (urb_qtd->in_process && qh->channel) {
2062 dwc2_dump_channel_info(hsotg, qh->channel);
2064 /* The QTD is in process (it has been assigned to a channel) */
2065 if (hsotg->flags.b.port_connect_status)
2067 * If still connected (i.e. in host mode), halt the
2068 * channel so it can be used for other transfers. If
2069 * no longer connected, the host registers can't be
2070 * written to halt the channel since the core is in
2073 dwc2_hc_halt(hsotg, qh->channel,
2074 DWC2_HC_XFER_URB_DEQUEUE);
2078 * Free the QTD and clean up the associated QH. Leave the QH in the
2079 * schedule if it has any remaining QTDs.
2081 if (hsotg->core_params->dma_desc_enable <= 0) {
2082 u8 in_process = urb_qtd->in_process;
2084 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2086 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2088 } else if (list_empty(&qh->qtd_list)) {
2089 dwc2_hcd_qh_unlink(hsotg, qh);
2092 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2098 /* Must NOT be called with interrupt disabled or spinlock held */
2099 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2100 struct usb_host_endpoint *ep, int retry)
2102 struct dwc2_qtd *qtd, *qtd_tmp;
2104 unsigned long flags;
2107 spin_lock_irqsave(&hsotg->lock, flags);
2115 while (!list_empty(&qh->qtd_list) && retry--) {
2118 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2123 spin_unlock_irqrestore(&hsotg->lock, flags);
2124 usleep_range(20000, 40000);
2125 spin_lock_irqsave(&hsotg->lock, flags);
2133 dwc2_hcd_qh_unlink(hsotg, qh);
2135 /* Free each QTD in the QH's QTD list */
2136 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2137 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2141 if (qh->channel && qh->channel->qh == qh)
2142 qh->channel->qh = NULL;
2144 spin_unlock_irqrestore(&hsotg->lock, flags);
2146 dwc2_hcd_qh_free(hsotg, qh);
2152 spin_unlock_irqrestore(&hsotg->lock, flags);
2157 /* Must be called with interrupt disabled and spinlock held */
2158 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2159 struct usb_host_endpoint *ep)
2161 struct dwc2_qh *qh = ep->hcpriv;
2166 qh->data_toggle = DWC2_HC_PID_DATA0;
2172 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2173 * prepares the core for device mode or host mode operation
2175 * @hsotg: Programming view of the DWC_otg controller
2176 * @initial_setup: If true then this is the first init for this instance.
2178 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2183 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2185 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2187 /* Set ULPI External VBUS bit if needed */
2188 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2189 if (hsotg->core_params->phy_ulpi_ext_vbus ==
2190 DWC2_PHY_ULPI_EXTERNAL_VBUS)
2191 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2193 /* Set external TS Dline pulsing bit if needed */
2194 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2195 if (hsotg->core_params->ts_dline > 0)
2196 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2198 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2201 * Reset the Controller
2203 * We only need to reset the controller if this is a re-init.
2204 * For the first init we know for sure that earlier code reset us (it
2205 * needed to in order to properly detect various parameters).
2207 if (!initial_setup) {
2208 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
2210 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2217 * This needs to happen in FS mode before any other programming occurs
2219 retval = dwc2_phy_init(hsotg, initial_setup);
2223 /* Program the GAHBCFG Register */
2224 retval = dwc2_gahbcfg_init(hsotg);
2228 /* Program the GUSBCFG register */
2229 dwc2_gusbcfg_init(hsotg);
2231 /* Program the GOTGCTL register */
2232 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2233 otgctl &= ~GOTGCTL_OTGVER;
2234 if (hsotg->core_params->otg_ver > 0)
2235 otgctl |= GOTGCTL_OTGVER;
2236 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2237 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
2239 /* Clear the SRP success bit for FS-I2c */
2240 hsotg->srp_success = 0;
2242 /* Enable common interrupts */
2243 dwc2_enable_common_interrupts(hsotg);
2246 * Do device or host initialization based on mode during PCD and
2247 * HCD initialization
2249 if (dwc2_is_host_mode(hsotg)) {
2250 dev_dbg(hsotg->dev, "Host Mode\n");
2251 hsotg->op_state = OTG_STATE_A_HOST;
2253 dev_dbg(hsotg->dev, "Device Mode\n");
2254 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2261 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2264 * @hsotg: Programming view of DWC_otg controller
2266 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2267 * request queues. Host channels are reset to ensure that they are ready for
2268 * performing transfers.
2270 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2272 u32 hcfg, hfir, otgctl, usbcfg;
2274 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2276 /* Set HS/FS Timeout Calibration to 7 (max available value).
2277 * The number of PHY clocks that the application programs in
2278 * this field is added to the high/full speed interpacket timeout
2279 * duration in the core to account for any additional delays
2280 * introduced by the PHY. This can be required, because the delay
2281 * introduced by the PHY in generating the linestate condition
2282 * can vary from one PHY to another.
2284 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2285 usbcfg |= GUSBCFG_TOUTCAL(7);
2286 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2288 /* Restart the Phy Clock */
2289 dwc2_writel(0, hsotg->regs + PCGCTL);
2291 /* Initialize Host Configuration Register */
2292 dwc2_init_fs_ls_pclk_sel(hsotg);
2293 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
2294 hcfg = dwc2_readl(hsotg->regs + HCFG);
2295 hcfg |= HCFG_FSLSSUPP;
2296 dwc2_writel(hcfg, hsotg->regs + HCFG);
2300 * This bit allows dynamic reloading of the HFIR register during
2301 * runtime. This bit needs to be programmed during initial configuration
2302 * and its value must not be changed during runtime.
2304 if (hsotg->core_params->reload_ctl > 0) {
2305 hfir = dwc2_readl(hsotg->regs + HFIR);
2306 hfir |= HFIR_RLDCTRL;
2307 dwc2_writel(hfir, hsotg->regs + HFIR);
2310 if (hsotg->core_params->dma_desc_enable > 0) {
2311 u32 op_mode = hsotg->hw_params.op_mode;
2313 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2314 !hsotg->hw_params.dma_desc_enable ||
2315 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2316 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2317 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2319 "Hardware does not support descriptor DMA mode -\n");
2321 "falling back to buffer DMA mode.\n");
2322 hsotg->core_params->dma_desc_enable = 0;
2324 hcfg = dwc2_readl(hsotg->regs + HCFG);
2325 hcfg |= HCFG_DESCDMA;
2326 dwc2_writel(hcfg, hsotg->regs + HCFG);
2330 /* Configure data FIFO sizes */
2331 dwc2_config_fifos(hsotg);
2333 /* TODO - check this */
2334 /* Clear Host Set HNP Enable in the OTG Control Register */
2335 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2336 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2337 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2339 /* Make sure the FIFOs are flushed */
2340 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2341 dwc2_flush_rx_fifo(hsotg);
2343 /* Clear Host Set HNP Enable in the OTG Control Register */
2344 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2345 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2346 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2348 if (hsotg->core_params->dma_desc_enable <= 0) {
2349 int num_channels, i;
2352 /* Flush out any leftover queued requests */
2353 num_channels = hsotg->core_params->host_channels;
2354 for (i = 0; i < num_channels; i++) {
2355 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2356 hcchar &= ~HCCHAR_CHENA;
2357 hcchar |= HCCHAR_CHDIS;
2358 hcchar &= ~HCCHAR_EPDIR;
2359 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2362 /* Halt all channels to put them into a known state */
2363 for (i = 0; i < num_channels; i++) {
2366 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2367 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2368 hcchar &= ~HCCHAR_EPDIR;
2369 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2370 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2373 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2374 if (++count > 1000) {
2376 "Unable to clear enable on channel %d\n",
2381 } while (hcchar & HCCHAR_CHENA);
2385 /* Turn on the vbus power */
2386 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2387 if (hsotg->op_state == OTG_STATE_A_HOST) {
2388 u32 hprt0 = dwc2_read_hprt0(hsotg);
2390 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2391 !!(hprt0 & HPRT0_PWR));
2392 if (!(hprt0 & HPRT0_PWR)) {
2394 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2398 dwc2_enable_host_interrupts(hsotg);
2402 * Initializes dynamic portions of the DWC_otg HCD state
2404 * Must be called with interrupt disabled and spinlock held
2406 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2408 struct dwc2_host_chan *chan, *chan_tmp;
2412 hsotg->flags.d32 = 0;
2413 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2415 if (hsotg->core_params->uframe_sched > 0) {
2416 hsotg->available_host_channels =
2417 hsotg->core_params->host_channels;
2419 hsotg->non_periodic_channels = 0;
2420 hsotg->periodic_channels = 0;
2424 * Put all channels in the free channel list and clean up channel
2427 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2429 list_del_init(&chan->hc_list_entry);
2431 num_channels = hsotg->core_params->host_channels;
2432 for (i = 0; i < num_channels; i++) {
2433 chan = hsotg->hc_ptr_array[i];
2434 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2435 dwc2_hc_cleanup(hsotg, chan);
2438 /* Initialize the DWC core for host mode operation */
2439 dwc2_core_host_init(hsotg);
2442 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2443 struct dwc2_host_chan *chan,
2444 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2446 int hub_addr, hub_port;
2449 chan->xact_pos = qtd->isoc_split_pos;
2450 chan->complete_split = qtd->complete_split;
2451 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2452 chan->hub_addr = (u8)hub_addr;
2453 chan->hub_port = (u8)hub_port;
2456 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2457 struct dwc2_host_chan *chan,
2458 struct dwc2_qtd *qtd)
2460 struct dwc2_hcd_urb *urb = qtd->urb;
2461 struct dwc2_hcd_iso_packet_desc *frame_desc;
2463 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2464 case USB_ENDPOINT_XFER_CONTROL:
2465 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2467 switch (qtd->control_phase) {
2468 case DWC2_CONTROL_SETUP:
2469 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2472 chan->data_pid_start = DWC2_HC_PID_SETUP;
2473 if (hsotg->core_params->dma_enable > 0)
2474 chan->xfer_dma = urb->setup_dma;
2476 chan->xfer_buf = urb->setup_packet;
2480 case DWC2_CONTROL_DATA:
2481 dev_vdbg(hsotg->dev, " Control data transaction\n");
2482 chan->data_pid_start = qtd->data_toggle;
2485 case DWC2_CONTROL_STATUS:
2487 * Direction is opposite of data direction or IN if no
2490 dev_vdbg(hsotg->dev, " Control status transaction\n");
2491 if (urb->length == 0)
2495 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2498 chan->data_pid_start = DWC2_HC_PID_DATA1;
2500 if (hsotg->core_params->dma_enable > 0)
2501 chan->xfer_dma = hsotg->status_buf_dma;
2503 chan->xfer_buf = hsotg->status_buf;
2508 case USB_ENDPOINT_XFER_BULK:
2509 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2512 case USB_ENDPOINT_XFER_INT:
2513 chan->ep_type = USB_ENDPOINT_XFER_INT;
2516 case USB_ENDPOINT_XFER_ISOC:
2517 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2518 if (hsotg->core_params->dma_desc_enable > 0)
2521 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2522 frame_desc->status = 0;
2524 if (hsotg->core_params->dma_enable > 0) {
2525 chan->xfer_dma = urb->dma;
2526 chan->xfer_dma += frame_desc->offset +
2527 qtd->isoc_split_offset;
2529 chan->xfer_buf = urb->buf;
2530 chan->xfer_buf += frame_desc->offset +
2531 qtd->isoc_split_offset;
2534 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2536 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2537 if (chan->xfer_len <= 188)
2538 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2540 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2546 #define DWC2_USB_DMA_ALIGN 4
2548 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2550 void *stored_xfer_buffer;
2552 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2555 /* Restore urb->transfer_buffer from the end of the allocated area */
2556 memcpy(&stored_xfer_buffer,
2557 PTR_ALIGN(urb->transfer_buffer + urb->transfer_buffer_length,
2558 dma_get_cache_alignment()),
2559 sizeof(urb->transfer_buffer));
2561 if (usb_urb_dir_in(urb))
2562 memcpy(stored_xfer_buffer, urb->transfer_buffer,
2563 urb->transfer_buffer_length);
2564 kfree(urb->transfer_buffer);
2565 urb->transfer_buffer = stored_xfer_buffer;
2567 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2570 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2573 size_t kmalloc_size;
2575 if (urb->num_sgs || urb->sg ||
2576 urb->transfer_buffer_length == 0 ||
2577 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2581 * Allocate a buffer with enough padding for original transfer_buffer
2582 * pointer. This allocation is guaranteed to be aligned properly for
2585 kmalloc_size = urb->transfer_buffer_length +
2586 (dma_get_cache_alignment() - 1) +
2587 sizeof(urb->transfer_buffer);
2589 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2594 * Position value of original urb->transfer_buffer pointer to the end
2595 * of allocation for later referencing
2597 memcpy(PTR_ALIGN(kmalloc_ptr + urb->transfer_buffer_length,
2598 dma_get_cache_alignment()),
2599 &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2601 if (usb_urb_dir_out(urb))
2602 memcpy(kmalloc_ptr, urb->transfer_buffer,
2603 urb->transfer_buffer_length);
2604 urb->transfer_buffer = kmalloc_ptr;
2606 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2611 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2616 /* We assume setup_dma is always aligned; warn if not */
2617 WARN_ON_ONCE(urb->setup_dma &&
2618 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2620 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2624 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2626 dwc2_free_dma_aligned_buffer(urb);
2631 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2633 usb_hcd_unmap_urb_for_dma(hcd, urb);
2634 dwc2_free_dma_aligned_buffer(urb);
2638 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2639 * channel and initializes the host channel to perform the transactions. The
2640 * host channel is removed from the free list.
2642 * @hsotg: The HCD state structure
2643 * @qh: Transactions from the first QTD for this QH are selected and assigned
2644 * to a free host channel
2646 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2648 struct dwc2_host_chan *chan;
2649 struct dwc2_hcd_urb *urb;
2650 struct dwc2_qtd *qtd;
2653 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2655 if (list_empty(&qh->qtd_list)) {
2656 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2660 if (list_empty(&hsotg->free_hc_list)) {
2661 dev_dbg(hsotg->dev, "No free channel to assign\n");
2665 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2668 /* Remove host channel from free list */
2669 list_del_init(&chan->hc_list_entry);
2671 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2674 qtd->in_process = 1;
2677 * Use usb_pipedevice to determine device address. This address is
2678 * 0 before the SET_ADDRESS command and the correct address afterward.
2680 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2681 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2682 chan->speed = qh->dev_speed;
2683 chan->max_packet = dwc2_max_packet(qh->maxp);
2685 chan->xfer_started = 0;
2686 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2687 chan->error_state = (qtd->error_count > 0);
2688 chan->halt_on_queue = 0;
2689 chan->halt_pending = 0;
2693 * The following values may be modified in the transfer type section
2694 * below. The xfer_len value may be reduced when the transfer is
2695 * started to accommodate the max widths of the XferSize and PktCnt
2696 * fields in the HCTSIZn register.
2699 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2703 chan->do_ping = qh->ping_state;
2705 chan->data_pid_start = qh->data_toggle;
2706 chan->multi_count = 1;
2708 if (urb->actual_length > urb->length &&
2709 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2710 urb->actual_length = urb->length;
2712 if (hsotg->core_params->dma_enable > 0)
2713 chan->xfer_dma = urb->dma + urb->actual_length;
2715 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2717 chan->xfer_len = urb->length - urb->actual_length;
2718 chan->xfer_count = 0;
2720 /* Set the split attributes if required */
2722 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2726 /* Set the transfer attributes */
2727 dwc2_hc_init_xfer(hsotg, chan, qtd);
2729 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2730 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2732 * This value may be modified when the transfer is started
2733 * to reflect the actual transfer length
2735 chan->multi_count = dwc2_hb_mult(qh->maxp);
2737 if (hsotg->core_params->dma_desc_enable > 0) {
2738 chan->desc_list_addr = qh->desc_list_dma;
2739 chan->desc_list_sz = qh->desc_list_sz;
2742 dwc2_hc_init(hsotg, chan);
2749 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2750 * schedule and assigns them to available host channels. Called from the HCD
2751 * interrupt handler functions.
2753 * @hsotg: The HCD state structure
2755 * Return: The types of new transactions that were assigned to host channels
2757 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2758 struct dwc2_hsotg *hsotg)
2760 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2761 struct list_head *qh_ptr;
2765 #ifdef DWC2_DEBUG_SOF
2766 dev_vdbg(hsotg->dev, " Select Transactions\n");
2769 /* Process entries in the periodic ready list */
2770 qh_ptr = hsotg->periodic_sched_ready.next;
2771 while (qh_ptr != &hsotg->periodic_sched_ready) {
2772 if (list_empty(&hsotg->free_hc_list))
2774 if (hsotg->core_params->uframe_sched > 0) {
2775 if (hsotg->available_host_channels <= 1)
2777 hsotg->available_host_channels--;
2779 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2780 if (dwc2_assign_and_init_hc(hsotg, qh))
2784 * Move the QH from the periodic ready schedule to the
2785 * periodic assigned schedule
2787 qh_ptr = qh_ptr->next;
2788 list_move_tail(&qh->qh_list_entry,
2789 &hsotg->periodic_sched_assigned);
2790 ret_val = DWC2_TRANSACTION_PERIODIC;
2794 * Process entries in the inactive portion of the non-periodic
2795 * schedule. Some free host channels may not be used if they are
2796 * reserved for periodic transfers.
2798 num_channels = hsotg->core_params->host_channels;
2799 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2800 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2801 if (hsotg->core_params->uframe_sched <= 0 &&
2802 hsotg->non_periodic_channels >= num_channels -
2803 hsotg->periodic_channels)
2805 if (list_empty(&hsotg->free_hc_list))
2807 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2808 if (hsotg->core_params->uframe_sched > 0) {
2809 if (hsotg->available_host_channels < 1)
2811 hsotg->available_host_channels--;
2814 if (dwc2_assign_and_init_hc(hsotg, qh))
2818 * Move the QH from the non-periodic inactive schedule to the
2819 * non-periodic active schedule
2821 qh_ptr = qh_ptr->next;
2822 list_move_tail(&qh->qh_list_entry,
2823 &hsotg->non_periodic_sched_active);
2825 if (ret_val == DWC2_TRANSACTION_NONE)
2826 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2828 ret_val = DWC2_TRANSACTION_ALL;
2830 if (hsotg->core_params->uframe_sched <= 0)
2831 hsotg->non_periodic_channels++;
2838 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2839 * a host channel associated with either a periodic or non-periodic transfer
2841 * @hsotg: The HCD state structure
2842 * @chan: Host channel descriptor associated with either a periodic or
2843 * non-periodic transfer
2844 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2845 * for periodic transfers or the non-periodic Tx FIFO
2846 * for non-periodic transfers
2848 * Return: 1 if a request is queued and more requests may be needed to
2849 * complete the transfer, 0 if no more requests are required for this
2850 * transfer, -1 if there is insufficient space in the Tx FIFO
2852 * This function assumes that there is space available in the appropriate
2853 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2854 * it checks whether space is available in the appropriate Tx FIFO.
2856 * Must be called with interrupt disabled and spinlock held
2858 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2859 struct dwc2_host_chan *chan,
2860 u16 fifo_dwords_avail)
2865 /* Put ourselves on the list to keep order straight */
2866 list_move_tail(&chan->split_order_list_entry,
2867 &hsotg->split_order);
2869 if (hsotg->core_params->dma_enable > 0) {
2870 if (hsotg->core_params->dma_desc_enable > 0) {
2871 if (!chan->xfer_started ||
2872 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2873 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2874 chan->qh->ping_state = 0;
2876 } else if (!chan->xfer_started) {
2877 dwc2_hc_start_transfer(hsotg, chan);
2878 chan->qh->ping_state = 0;
2880 } else if (chan->halt_pending) {
2881 /* Don't queue a request if the channel has been halted */
2882 } else if (chan->halt_on_queue) {
2883 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2884 } else if (chan->do_ping) {
2885 if (!chan->xfer_started)
2886 dwc2_hc_start_transfer(hsotg, chan);
2887 } else if (!chan->ep_is_in ||
2888 chan->data_pid_start == DWC2_HC_PID_SETUP) {
2889 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2890 if (!chan->xfer_started) {
2891 dwc2_hc_start_transfer(hsotg, chan);
2894 retval = dwc2_hc_continue_transfer(hsotg, chan);
2900 if (!chan->xfer_started) {
2901 dwc2_hc_start_transfer(hsotg, chan);
2904 retval = dwc2_hc_continue_transfer(hsotg, chan);
2912 * Processes periodic channels for the next frame and queues transactions for
2913 * these channels to the DWC_otg controller. After queueing transactions, the
2914 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2915 * to queue as Periodic Tx FIFO or request queue space becomes available.
2916 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2918 * Must be called with interrupt disabled and spinlock held
2920 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2922 struct list_head *qh_ptr;
2928 bool no_queue_space = false;
2929 bool no_fifo_space = false;
2932 /* If empty list then just adjust interrupt enables */
2933 if (list_empty(&hsotg->periodic_sched_assigned))
2937 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2939 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2940 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2941 TXSTS_QSPCAVAIL_SHIFT;
2942 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2943 TXSTS_FSPCAVAIL_SHIFT;
2946 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
2948 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
2952 qh_ptr = hsotg->periodic_sched_assigned.next;
2953 while (qh_ptr != &hsotg->periodic_sched_assigned) {
2954 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2955 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2956 TXSTS_QSPCAVAIL_SHIFT;
2957 if (qspcavail == 0) {
2962 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2964 qh_ptr = qh_ptr->next;
2968 /* Make sure EP's TT buffer is clean before queueing qtds */
2969 if (qh->tt_buffer_dirty) {
2970 qh_ptr = qh_ptr->next;
2975 * Set a flag if we're queuing high-bandwidth in slave mode.
2976 * The flag prevents any halts to get into the request queue in
2977 * the middle of multiple high-bandwidth packets getting queued.
2979 if (hsotg->core_params->dma_enable <= 0 &&
2980 qh->channel->multi_count > 1)
2981 hsotg->queuing_high_bandwidth = 1;
2983 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2984 TXSTS_FSPCAVAIL_SHIFT;
2985 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2992 * In Slave mode, stay on the current transfer until there is
2993 * nothing more to do or the high-bandwidth request count is
2994 * reached. In DMA mode, only need to queue one request. The
2995 * controller automatically handles multiple packets for
2996 * high-bandwidth transfers.
2998 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
2999 qh->channel->requests == qh->channel->multi_count) {
3000 qh_ptr = qh_ptr->next;
3002 * Move the QH from the periodic assigned schedule to
3003 * the periodic queued schedule
3005 list_move_tail(&qh->qh_list_entry,
3006 &hsotg->periodic_sched_queued);
3008 /* done queuing high bandwidth */
3009 hsotg->queuing_high_bandwidth = 0;
3014 if (no_queue_space || no_fifo_space ||
3015 (hsotg->core_params->dma_enable <= 0 &&
3016 !list_empty(&hsotg->periodic_sched_assigned))) {
3018 * May need to queue more transactions as the request
3019 * queue or Tx FIFO empties. Enable the periodic Tx
3020 * FIFO empty interrupt. (Always use the half-empty
3021 * level to ensure that new requests are loaded as
3022 * soon as possible.)
3024 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3025 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3026 gintmsk |= GINTSTS_PTXFEMP;
3027 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3031 * Disable the Tx FIFO empty interrupt since there are
3032 * no more transactions that need to be queued right
3033 * now. This function is called from interrupt
3034 * handlers to queue more transactions as transfer
3037 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3038 if (gintmsk & GINTSTS_PTXFEMP) {
3039 gintmsk &= ~GINTSTS_PTXFEMP;
3040 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3046 * Processes active non-periodic channels and queues transactions for these
3047 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3048 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3049 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3050 * FIFO Empty interrupt is disabled.
3052 * Must be called with interrupt disabled and spinlock held
3054 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3056 struct list_head *orig_qh_ptr;
3063 int no_queue_space = 0;
3064 int no_fifo_space = 0;
3067 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3069 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3070 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3071 TXSTS_QSPCAVAIL_SHIFT;
3072 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3073 TXSTS_FSPCAVAIL_SHIFT;
3074 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3076 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3080 * Keep track of the starting point. Skip over the start-of-list
3083 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3084 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3085 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3088 * Process once through the active list or until no more space is
3089 * available in the request queue or the Tx FIFO
3092 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3093 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3094 TXSTS_QSPCAVAIL_SHIFT;
3095 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
3100 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3105 /* Make sure EP's TT buffer is clean before queueing qtds */
3106 if (qh->tt_buffer_dirty)
3109 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3110 TXSTS_FSPCAVAIL_SHIFT;
3111 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3115 } else if (status < 0) {
3120 /* Advance to next QH, skipping start-of-list entry */
3121 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3122 if (hsotg->non_periodic_qh_ptr ==
3123 &hsotg->non_periodic_sched_active)
3124 hsotg->non_periodic_qh_ptr =
3125 hsotg->non_periodic_qh_ptr->next;
3126 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3128 if (hsotg->core_params->dma_enable <= 0) {
3129 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3130 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3131 TXSTS_QSPCAVAIL_SHIFT;
3132 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3133 TXSTS_FSPCAVAIL_SHIFT;
3134 dev_vdbg(hsotg->dev,
3135 " NP Tx Req Queue Space Avail (after queue): %d\n",
3137 dev_vdbg(hsotg->dev,
3138 " NP Tx FIFO Space Avail (after queue): %d\n",
3141 if (more_to_do || no_queue_space || no_fifo_space) {
3143 * May need to queue more transactions as the request
3144 * queue or Tx FIFO empties. Enable the non-periodic
3145 * Tx FIFO empty interrupt. (Always use the half-empty
3146 * level to ensure that new requests are loaded as
3147 * soon as possible.)
3149 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3150 gintmsk |= GINTSTS_NPTXFEMP;
3151 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3154 * Disable the Tx FIFO empty interrupt since there are
3155 * no more transactions that need to be queued right
3156 * now. This function is called from interrupt
3157 * handlers to queue more transactions as transfer
3160 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3161 gintmsk &= ~GINTSTS_NPTXFEMP;
3162 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3168 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3169 * and queues transactions for these channels to the DWC_otg controller. Called
3170 * from the HCD interrupt handler functions.
3172 * @hsotg: The HCD state structure
3173 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3176 * Must be called with interrupt disabled and spinlock held
3178 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3179 enum dwc2_transaction_type tr_type)
3181 #ifdef DWC2_DEBUG_SOF
3182 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3184 /* Process host channels associated with periodic transfers */
3185 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3186 tr_type == DWC2_TRANSACTION_ALL)
3187 dwc2_process_periodic_channels(hsotg);
3189 /* Process host channels associated with non-periodic transfers */
3190 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3191 tr_type == DWC2_TRANSACTION_ALL) {
3192 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3193 dwc2_process_non_periodic_channels(hsotg);
3196 * Ensure NP Tx FIFO empty interrupt is disabled when
3197 * there are no non-periodic transfers to process
3199 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3201 gintmsk &= ~GINTSTS_NPTXFEMP;
3202 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3207 static void dwc2_conn_id_status_change(struct work_struct *work)
3209 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3213 unsigned long flags;
3215 dev_dbg(hsotg->dev, "%s()\n", __func__);
3217 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3218 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3219 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3220 !!(gotgctl & GOTGCTL_CONID_B));
3222 /* B-Device connector (Device Mode) */
3223 if (gotgctl & GOTGCTL_CONID_B) {
3224 /* Wait for switch to device mode */
3225 dev_dbg(hsotg->dev, "connId B\n");
3226 while (!dwc2_is_device_mode(hsotg)) {
3227 dev_info(hsotg->dev,
3228 "Waiting for Peripheral Mode, Mode=%s\n",
3229 dwc2_is_host_mode(hsotg) ? "Host" :
3231 usleep_range(20000, 40000);
3237 "Connection id status change timed out\n");
3238 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3239 dwc2_core_init(hsotg, false);
3240 dwc2_enable_global_interrupts(hsotg);
3241 spin_lock_irqsave(&hsotg->lock, flags);
3242 dwc2_hsotg_core_init_disconnected(hsotg, false);
3243 spin_unlock_irqrestore(&hsotg->lock, flags);
3244 dwc2_hsotg_core_connect(hsotg);
3246 /* A-Device connector (Host Mode) */
3247 dev_dbg(hsotg->dev, "connId A\n");
3248 while (!dwc2_is_host_mode(hsotg)) {
3249 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3250 dwc2_is_host_mode(hsotg) ?
3251 "Host" : "Peripheral");
3252 usleep_range(20000, 40000);
3258 "Connection id status change timed out\n");
3260 spin_lock_irqsave(&hsotg->lock, flags);
3261 dwc2_hsotg_disconnect(hsotg);
3262 spin_unlock_irqrestore(&hsotg->lock, flags);
3264 hsotg->op_state = OTG_STATE_A_HOST;
3265 /* Initialize the Core for Host mode */
3266 dwc2_core_init(hsotg, false);
3267 dwc2_enable_global_interrupts(hsotg);
3268 dwc2_hcd_start(hsotg);
3272 static void dwc2_wakeup_detected(unsigned long data)
3274 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
3277 dev_dbg(hsotg->dev, "%s()\n", __func__);
3280 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3281 * so that OPT tests pass with all PHYs.)
3283 hprt0 = dwc2_read_hprt0(hsotg);
3284 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3285 hprt0 &= ~HPRT0_RES;
3286 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3287 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3288 dwc2_readl(hsotg->regs + HPRT0));
3290 dwc2_hcd_rem_wakeup(hsotg);
3291 hsotg->bus_suspended = 0;
3293 /* Change to L0 state */
3294 hsotg->lx_state = DWC2_L0;
3297 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3299 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3301 return hcd->self.b_hnp_enable;
3304 /* Must NOT be called with interrupt disabled or spinlock held */
3305 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3307 unsigned long flags;
3312 dev_dbg(hsotg->dev, "%s()\n", __func__);
3314 spin_lock_irqsave(&hsotg->lock, flags);
3316 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3317 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3318 gotgctl |= GOTGCTL_HSTSETHNPEN;
3319 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
3320 hsotg->op_state = OTG_STATE_A_SUSPEND;
3323 hprt0 = dwc2_read_hprt0(hsotg);
3324 hprt0 |= HPRT0_SUSP;
3325 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3327 hsotg->bus_suspended = 1;
3330 * If hibernation is supported, Phy clock will be suspended
3331 * after registers are backuped.
3333 if (!hsotg->core_params->hibernation) {
3334 /* Suspend the Phy Clock */
3335 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3336 pcgctl |= PCGCTL_STOPPCLK;
3337 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3341 /* For HNP the bus must be suspended for at least 200ms */
3342 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3343 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3344 pcgctl &= ~PCGCTL_STOPPCLK;
3345 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3347 spin_unlock_irqrestore(&hsotg->lock, flags);
3349 usleep_range(200000, 250000);
3351 spin_unlock_irqrestore(&hsotg->lock, flags);
3355 /* Must NOT be called with interrupt disabled or spinlock held */
3356 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3358 unsigned long flags;
3362 spin_lock_irqsave(&hsotg->lock, flags);
3365 * If hibernation is supported, Phy clock is already resumed
3366 * after registers restore.
3368 if (!hsotg->core_params->hibernation) {
3369 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3370 pcgctl &= ~PCGCTL_STOPPCLK;
3371 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3372 spin_unlock_irqrestore(&hsotg->lock, flags);
3373 usleep_range(20000, 40000);
3374 spin_lock_irqsave(&hsotg->lock, flags);
3377 hprt0 = dwc2_read_hprt0(hsotg);
3379 hprt0 &= ~HPRT0_SUSP;
3380 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3381 spin_unlock_irqrestore(&hsotg->lock, flags);
3383 msleep(USB_RESUME_TIMEOUT);
3385 spin_lock_irqsave(&hsotg->lock, flags);
3386 hprt0 = dwc2_read_hprt0(hsotg);
3387 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3388 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3389 hsotg->bus_suspended = 0;
3390 spin_unlock_irqrestore(&hsotg->lock, flags);
3393 /* Handles hub class-specific requests */
3394 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3395 u16 wvalue, u16 windex, char *buf, u16 wlength)
3397 struct usb_hub_descriptor *hub_desc;
3405 case ClearHubFeature:
3406 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3409 case C_HUB_LOCAL_POWER:
3410 case C_HUB_OVER_CURRENT:
3411 /* Nothing required here */
3417 "ClearHubFeature request %1xh unknown\n",
3422 case ClearPortFeature:
3423 if (wvalue != USB_PORT_FEAT_L1)
3424 if (!windex || windex > 1)
3427 case USB_PORT_FEAT_ENABLE:
3429 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3430 hprt0 = dwc2_read_hprt0(hsotg);
3432 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3435 case USB_PORT_FEAT_SUSPEND:
3437 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3439 if (hsotg->bus_suspended)
3440 dwc2_port_resume(hsotg);
3443 case USB_PORT_FEAT_POWER:
3445 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3446 hprt0 = dwc2_read_hprt0(hsotg);
3447 hprt0 &= ~HPRT0_PWR;
3448 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3451 case USB_PORT_FEAT_INDICATOR:
3453 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3454 /* Port indicator not supported */
3457 case USB_PORT_FEAT_C_CONNECTION:
3459 * Clears driver's internal Connect Status Change flag
3462 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3463 hsotg->flags.b.port_connect_status_change = 0;
3466 case USB_PORT_FEAT_C_RESET:
3467 /* Clears driver's internal Port Reset Change flag */
3469 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3470 hsotg->flags.b.port_reset_change = 0;
3473 case USB_PORT_FEAT_C_ENABLE:
3475 * Clears the driver's internal Port Enable/Disable
3479 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3480 hsotg->flags.b.port_enable_change = 0;
3483 case USB_PORT_FEAT_C_SUSPEND:
3485 * Clears the driver's internal Port Suspend Change
3486 * flag, which is set when resume signaling on the host
3490 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3491 hsotg->flags.b.port_suspend_change = 0;
3494 case USB_PORT_FEAT_C_PORT_L1:
3496 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3497 hsotg->flags.b.port_l1_change = 0;
3500 case USB_PORT_FEAT_C_OVER_CURRENT:
3502 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3503 hsotg->flags.b.port_over_current_change = 0;
3509 "ClearPortFeature request %1xh unknown or unsupported\n",
3514 case GetHubDescriptor:
3515 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3516 hub_desc = (struct usb_hub_descriptor *)buf;
3517 hub_desc->bDescLength = 9;
3518 hub_desc->bDescriptorType = USB_DT_HUB;
3519 hub_desc->bNbrPorts = 1;
3520 hub_desc->wHubCharacteristics =
3521 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3522 HUB_CHAR_INDV_PORT_OCPM);
3523 hub_desc->bPwrOn2PwrGood = 1;
3524 hub_desc->bHubContrCurrent = 0;
3525 hub_desc->u.hs.DeviceRemovable[0] = 0;
3526 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3530 dev_dbg(hsotg->dev, "GetHubStatus\n");
3535 dev_vdbg(hsotg->dev,
3536 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3538 if (!windex || windex > 1)
3542 if (hsotg->flags.b.port_connect_status_change)
3543 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3544 if (hsotg->flags.b.port_enable_change)
3545 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3546 if (hsotg->flags.b.port_suspend_change)
3547 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3548 if (hsotg->flags.b.port_l1_change)
3549 port_status |= USB_PORT_STAT_C_L1 << 16;
3550 if (hsotg->flags.b.port_reset_change)
3551 port_status |= USB_PORT_STAT_C_RESET << 16;
3552 if (hsotg->flags.b.port_over_current_change) {
3553 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3554 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3557 if (!hsotg->flags.b.port_connect_status) {
3559 * The port is disconnected, which means the core is
3560 * either in device mode or it soon will be. Just
3561 * return 0's for the remainder of the port status
3562 * since the port register can't be read if the core
3563 * is in device mode.
3565 *(__le32 *)buf = cpu_to_le32(port_status);
3569 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
3570 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3572 if (hprt0 & HPRT0_CONNSTS)
3573 port_status |= USB_PORT_STAT_CONNECTION;
3574 if (hprt0 & HPRT0_ENA)
3575 port_status |= USB_PORT_STAT_ENABLE;
3576 if (hprt0 & HPRT0_SUSP)
3577 port_status |= USB_PORT_STAT_SUSPEND;
3578 if (hprt0 & HPRT0_OVRCURRACT)
3579 port_status |= USB_PORT_STAT_OVERCURRENT;
3580 if (hprt0 & HPRT0_RST)
3581 port_status |= USB_PORT_STAT_RESET;
3582 if (hprt0 & HPRT0_PWR)
3583 port_status |= USB_PORT_STAT_POWER;
3585 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3586 if (speed == HPRT0_SPD_HIGH_SPEED)
3587 port_status |= USB_PORT_STAT_HIGH_SPEED;
3588 else if (speed == HPRT0_SPD_LOW_SPEED)
3589 port_status |= USB_PORT_STAT_LOW_SPEED;
3591 if (hprt0 & HPRT0_TSTCTL_MASK)
3592 port_status |= USB_PORT_STAT_TEST;
3593 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3595 if (hsotg->core_params->dma_desc_fs_enable) {
3597 * Enable descriptor DMA only if a full speed
3598 * device is connected.
3600 if (hsotg->new_connection &&
3602 (USB_PORT_STAT_CONNECTION |
3603 USB_PORT_STAT_HIGH_SPEED |
3604 USB_PORT_STAT_LOW_SPEED)) ==
3605 USB_PORT_STAT_CONNECTION)) {
3608 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3609 hsotg->core_params->dma_desc_enable = 1;
3610 hcfg = dwc2_readl(hsotg->regs + HCFG);
3611 hcfg |= HCFG_DESCDMA;
3612 dwc2_writel(hcfg, hsotg->regs + HCFG);
3613 hsotg->new_connection = false;
3617 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3618 *(__le32 *)buf = cpu_to_le32(port_status);
3622 dev_dbg(hsotg->dev, "SetHubFeature\n");
3623 /* No HUB features supported */
3626 case SetPortFeature:
3627 dev_dbg(hsotg->dev, "SetPortFeature\n");
3628 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3631 if (!hsotg->flags.b.port_connect_status) {
3633 * The port is disconnected, which means the core is
3634 * either in device mode or it soon will be. Just
3635 * return without doing anything since the port
3636 * register can't be written if the core is in device
3643 case USB_PORT_FEAT_SUSPEND:
3645 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3646 if (windex != hsotg->otg_port)
3648 dwc2_port_suspend(hsotg, windex);
3651 case USB_PORT_FEAT_POWER:
3653 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3654 hprt0 = dwc2_read_hprt0(hsotg);
3656 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3659 case USB_PORT_FEAT_RESET:
3660 hprt0 = dwc2_read_hprt0(hsotg);
3662 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3663 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3664 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3665 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3666 /* ??? Original driver does this */
3667 dwc2_writel(0, hsotg->regs + PCGCTL);
3669 hprt0 = dwc2_read_hprt0(hsotg);
3670 /* Clear suspend bit if resetting from suspend state */
3671 hprt0 &= ~HPRT0_SUSP;
3674 * When B-Host the Port reset bit is set in the Start
3675 * HCD Callback function, so that the reset is started
3676 * within 1ms of the HNP success interrupt
3678 if (!dwc2_hcd_is_b_host(hsotg)) {
3679 hprt0 |= HPRT0_PWR | HPRT0_RST;
3681 "In host mode, hprt0=%08x\n", hprt0);
3682 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3685 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3686 usleep_range(50000, 70000);
3687 hprt0 &= ~HPRT0_RST;
3688 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3689 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3692 case USB_PORT_FEAT_INDICATOR:
3694 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3698 case USB_PORT_FEAT_TEST:
3699 hprt0 = dwc2_read_hprt0(hsotg);
3701 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3702 hprt0 &= ~HPRT0_TSTCTL_MASK;
3703 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3704 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3710 "SetPortFeature %1xh unknown or unsupported\n",
3720 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3721 typereq, windex, wvalue);
3728 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3735 retval = (hsotg->flags.b.port_connect_status_change ||
3736 hsotg->flags.b.port_reset_change ||
3737 hsotg->flags.b.port_enable_change ||
3738 hsotg->flags.b.port_suspend_change ||
3739 hsotg->flags.b.port_over_current_change);
3743 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3744 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3745 hsotg->flags.b.port_connect_status_change);
3746 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3747 hsotg->flags.b.port_reset_change);
3748 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3749 hsotg->flags.b.port_enable_change);
3750 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3751 hsotg->flags.b.port_suspend_change);
3752 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3753 hsotg->flags.b.port_over_current_change);
3759 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3761 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3763 #ifdef DWC2_DEBUG_SOF
3764 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3765 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3767 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3770 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3772 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3773 u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3774 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3775 unsigned int us_per_frame;
3776 unsigned int frame_number;
3777 unsigned int remaining;
3778 unsigned int interval;
3779 unsigned int phy_clks;
3781 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3782 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3784 /* Extract fields */
3785 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3786 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3787 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3790 * Number of phy clocks since the last tick of the frame number after
3793 phy_clks = (interval - remaining) +
3794 DIV_ROUND_UP(interval * us, us_per_frame);
3796 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3799 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3801 return hsotg->op_state == OTG_STATE_B_HOST;
3804 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3808 struct dwc2_hcd_urb *urb;
3809 u32 size = sizeof(*urb) + iso_desc_count *
3810 sizeof(struct dwc2_hcd_iso_packet_desc);
3812 urb = kzalloc(size, mem_flags);
3814 urb->packet_count = iso_desc_count;
3818 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3819 struct dwc2_hcd_urb *urb, u8 dev_addr,
3820 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3823 ep_type == USB_ENDPOINT_XFER_BULK ||
3824 ep_type == USB_ENDPOINT_XFER_CONTROL)
3825 dev_vdbg(hsotg->dev,
3826 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3827 dev_addr, ep_num, ep_dir, ep_type, mps);
3828 urb->pipe_info.dev_addr = dev_addr;
3829 urb->pipe_info.ep_num = ep_num;
3830 urb->pipe_info.pipe_type = ep_type;
3831 urb->pipe_info.pipe_dir = ep_dir;
3832 urb->pipe_info.mps = mps;
3836 * NOTE: This function will be removed once the peripheral controller code
3837 * is integrated and the driver is stable
3839 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3842 struct dwc2_host_chan *chan;
3843 struct dwc2_hcd_urb *urb;
3844 struct dwc2_qtd *qtd;
3850 num_channels = hsotg->core_params->host_channels;
3851 dev_dbg(hsotg->dev, "\n");
3853 "************************************************************\n");
3854 dev_dbg(hsotg->dev, "HCD State:\n");
3855 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3857 for (i = 0; i < num_channels; i++) {
3858 chan = hsotg->hc_ptr_array[i];
3859 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3861 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3862 chan->dev_addr, chan->ep_num, chan->ep_is_in);
3863 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3864 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3865 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3866 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3867 chan->data_pid_start);
3868 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3869 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3870 chan->xfer_started);
3871 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3872 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3873 (unsigned long)chan->xfer_dma);
3874 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3875 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3876 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3877 chan->halt_on_queue);
3878 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3879 chan->halt_pending);
3880 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3881 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3882 dev_dbg(hsotg->dev, " complete_split: %d\n",
3883 chan->complete_split);
3884 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3885 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3886 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3887 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3888 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3890 if (chan->xfer_started) {
3891 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3893 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3894 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
3895 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
3896 hcint = dwc2_readl(hsotg->regs + HCINT(i));
3897 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
3898 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
3899 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
3900 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
3901 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
3902 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
3905 if (!(chan->xfer_started && chan->qh))
3908 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
3909 if (!qtd->in_process)
3912 dev_dbg(hsotg->dev, " URB Info:\n");
3913 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
3917 " Dev: %d, EP: %d %s\n",
3918 dwc2_hcd_get_dev_addr(&urb->pipe_info),
3919 dwc2_hcd_get_ep_num(&urb->pipe_info),
3920 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
3923 " Max packet size: %d\n",
3924 dwc2_hcd_get_mps(&urb->pipe_info));
3926 " transfer_buffer: %p\n",
3929 " transfer_dma: %08lx\n",
3930 (unsigned long)urb->dma);
3932 " transfer_buffer_length: %d\n",
3934 dev_dbg(hsotg->dev, " actual_length: %d\n",
3935 urb->actual_length);
3940 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
3941 hsotg->non_periodic_channels);
3942 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
3943 hsotg->periodic_channels);
3944 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
3945 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3946 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
3947 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3948 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
3949 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3950 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3951 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
3952 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3953 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
3954 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3955 dwc2_hcd_dump_frrem(hsotg);
3956 dwc2_dump_global_registers(hsotg);
3957 dwc2_dump_host_registers(hsotg);
3959 "************************************************************\n");
3960 dev_dbg(hsotg->dev, "\n");
3965 * NOTE: This function will be removed once the peripheral controller code
3966 * is integrated and the driver is stable
3968 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
3970 #ifdef DWC2_DUMP_FRREM
3971 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
3972 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3973 hsotg->frrem_samples, hsotg->frrem_accum,
3974 hsotg->frrem_samples > 0 ?
3975 hsotg->frrem_accum / hsotg->frrem_samples : 0);
3976 dev_dbg(hsotg->dev, "\n");
3977 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
3978 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3979 hsotg->hfnum_7_samples,
3980 hsotg->hfnum_7_frrem_accum,
3981 hsotg->hfnum_7_samples > 0 ?
3982 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
3983 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
3984 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3985 hsotg->hfnum_0_samples,
3986 hsotg->hfnum_0_frrem_accum,
3987 hsotg->hfnum_0_samples > 0 ?
3988 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
3989 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
3990 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3991 hsotg->hfnum_other_samples,
3992 hsotg->hfnum_other_frrem_accum,
3993 hsotg->hfnum_other_samples > 0 ?
3994 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
3996 dev_dbg(hsotg->dev, "\n");
3997 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
3998 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3999 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
4000 hsotg->hfnum_7_samples_a > 0 ?
4001 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
4002 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
4003 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4004 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
4005 hsotg->hfnum_0_samples_a > 0 ?
4006 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
4007 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
4008 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4009 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
4010 hsotg->hfnum_other_samples_a > 0 ?
4011 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
4013 dev_dbg(hsotg->dev, "\n");
4014 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
4015 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4016 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
4017 hsotg->hfnum_7_samples_b > 0 ?
4018 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
4019 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
4020 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4021 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
4022 (hsotg->hfnum_0_samples_b > 0) ?
4023 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
4024 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
4025 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4026 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
4027 (hsotg->hfnum_other_samples_b > 0) ?
4028 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
4033 struct wrapper_priv_data {
4034 struct dwc2_hsotg *hsotg;
4037 /* Gets the dwc2_hsotg from a usb_hcd */
4038 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4040 struct wrapper_priv_data *p;
4042 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
4046 static int _dwc2_hcd_start(struct usb_hcd *hcd);
4048 void dwc2_host_start(struct dwc2_hsotg *hsotg)
4050 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
4052 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
4053 _dwc2_hcd_start(hcd);
4056 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
4058 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
4060 hcd->self.is_b_host = 0;
4063 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
4066 struct urb *urb = context;
4069 *hub_addr = urb->dev->tt->hub->devnum;
4072 *hub_port = urb->dev->ttport;
4076 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4078 * This will get the dwc2_tt structure (and ttport) associated with the given
4079 * context (which is really just a struct urb pointer).
4081 * The first time this is called for a given TT we allocate memory for our
4082 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4083 * then the refcount for the structure will go to 0 and we'll free it.
4085 * @hsotg: The HCD state structure for the DWC OTG controller.
4086 * @qh: The QH structure.
4087 * @context: The priv pointer from a struct dwc2_hcd_urb.
4088 * @mem_flags: Flags for allocating memory.
4089 * @ttport: We'll return this device's port number here. That's used to
4090 * reference into the bitmap if we're on a multi_tt hub.
4092 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4093 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4096 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4097 gfp_t mem_flags, int *ttport)
4099 struct urb *urb = context;
4100 struct dwc2_tt *dwc_tt = NULL;
4103 *ttport = urb->dev->ttport;
4105 dwc_tt = urb->dev->tt->hcpriv;
4106 if (dwc_tt == NULL) {
4110 * For single_tt we need one schedule. For multi_tt
4111 * we need one per port.
4113 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4114 sizeof(dwc_tt->periodic_bitmaps[0]);
4115 if (urb->dev->tt->multi)
4116 bitmap_size *= urb->dev->tt->hub->maxchild;
4118 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4123 dwc_tt->usb_tt = urb->dev->tt;
4124 dwc_tt->usb_tt->hcpriv = dwc_tt;
4134 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4136 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4137 * of the structure are done.
4139 * It's OK to call this with NULL.
4141 * @hsotg: The HCD state structure for the DWC OTG controller.
4142 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4144 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4146 /* Model kfree and make put of NULL a no-op */
4150 WARN_ON(dwc_tt->refcount < 1);
4153 if (!dwc_tt->refcount) {
4154 dwc_tt->usb_tt->hcpriv = NULL;
4159 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4161 struct urb *urb = context;
4163 return urb->dev->speed;
4166 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4169 struct usb_bus *bus = hcd_to_bus(hcd);
4172 bus->bandwidth_allocated += bw / urb->interval;
4173 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4174 bus->bandwidth_isoc_reqs++;
4176 bus->bandwidth_int_reqs++;
4179 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4182 struct usb_bus *bus = hcd_to_bus(hcd);
4185 bus->bandwidth_allocated -= bw / urb->interval;
4186 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4187 bus->bandwidth_isoc_reqs--;
4189 bus->bandwidth_int_reqs--;
4193 * Sets the final status of an URB and returns it to the upper layer. Any
4194 * required cleanup of the URB is performed.
4196 * Must be called with interrupt disabled and spinlock held
4198 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4205 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4210 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4214 urb = qtd->urb->priv;
4216 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4220 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4223 dev_vdbg(hsotg->dev,
4224 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4225 __func__, urb, usb_pipedevice(urb->pipe),
4226 usb_pipeendpoint(urb->pipe),
4227 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4228 urb->actual_length);
4231 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4232 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4233 for (i = 0; i < urb->number_of_packets; ++i) {
4234 urb->iso_frame_desc[i].actual_length =
4235 dwc2_hcd_urb_get_iso_desc_actual_length(
4237 urb->iso_frame_desc[i].status =
4238 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4242 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4243 for (i = 0; i < urb->number_of_packets; i++)
4244 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4245 i, urb->iso_frame_desc[i].status);
4248 urb->status = status;
4250 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4251 urb->actual_length < urb->transfer_buffer_length)
4252 urb->status = -EREMOTEIO;
4255 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4256 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4257 struct usb_host_endpoint *ep = urb->ep;
4260 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4261 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4265 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4270 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4274 * Work queue function for starting the HCD when A-Cable is connected
4276 static void dwc2_hcd_start_func(struct work_struct *work)
4278 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4281 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4282 dwc2_host_start(hsotg);
4286 * Reset work queue function
4288 static void dwc2_hcd_reset_func(struct work_struct *work)
4290 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4292 unsigned long flags;
4295 dev_dbg(hsotg->dev, "USB RESET function called\n");
4297 spin_lock_irqsave(&hsotg->lock, flags);
4299 hprt0 = dwc2_read_hprt0(hsotg);
4300 hprt0 &= ~HPRT0_RST;
4301 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4302 hsotg->flags.b.port_reset_change = 1;
4304 spin_unlock_irqrestore(&hsotg->lock, flags);
4308 * =========================================================================
4309 * Linux HC Driver Functions
4310 * =========================================================================
4314 * Initializes the DWC_otg controller and its root hub and prepares it for host
4315 * mode operation. Activates the root port. Returns 0 on success and a negative
4316 * error code on failure.
4318 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4320 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4321 struct usb_bus *bus = hcd_to_bus(hcd);
4322 unsigned long flags;
4324 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4326 spin_lock_irqsave(&hsotg->lock, flags);
4327 hsotg->lx_state = DWC2_L0;
4328 hcd->state = HC_STATE_RUNNING;
4329 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4331 if (dwc2_is_device_mode(hsotg)) {
4332 spin_unlock_irqrestore(&hsotg->lock, flags);
4333 return 0; /* why 0 ?? */
4336 dwc2_hcd_reinit(hsotg);
4338 /* Initialize and connect root hub if one is not already attached */
4339 if (bus->root_hub) {
4340 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4341 /* Inform the HUB driver to resume */
4342 usb_hcd_resume_root_hub(hcd);
4345 spin_unlock_irqrestore(&hsotg->lock, flags);
4350 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4353 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4355 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4356 unsigned long flags;
4358 /* Turn off all host-specific interrupts */
4359 dwc2_disable_host_interrupts(hsotg);
4361 /* Wait for interrupt processing to finish */
4362 synchronize_irq(hcd->irq);
4364 spin_lock_irqsave(&hsotg->lock, flags);
4365 /* Ensure hcd is disconnected */
4366 dwc2_hcd_disconnect(hsotg, true);
4367 dwc2_hcd_stop(hsotg);
4368 hsotg->lx_state = DWC2_L3;
4369 hcd->state = HC_STATE_HALT;
4370 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4371 spin_unlock_irqrestore(&hsotg->lock, flags);
4373 usleep_range(1000, 3000);
4376 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4378 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4379 unsigned long flags;
4383 spin_lock_irqsave(&hsotg->lock, flags);
4385 if (hsotg->lx_state != DWC2_L0)
4388 if (!HCD_HW_ACCESSIBLE(hcd))
4391 if (!hsotg->core_params->hibernation)
4392 goto skip_power_saving;
4395 * Drive USB suspend and disable port Power
4396 * if usb bus is not suspended.
4398 if (!hsotg->bus_suspended) {
4399 hprt0 = dwc2_read_hprt0(hsotg);
4400 hprt0 |= HPRT0_SUSP;
4401 hprt0 &= ~HPRT0_PWR;
4402 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4405 /* Enter hibernation */
4406 ret = dwc2_enter_hibernation(hsotg);
4408 if (ret != -ENOTSUPP)
4410 "enter hibernation failed\n");
4411 goto skip_power_saving;
4414 /* Ask phy to be suspended */
4415 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4416 spin_unlock_irqrestore(&hsotg->lock, flags);
4417 usb_phy_set_suspend(hsotg->uphy, true);
4418 spin_lock_irqsave(&hsotg->lock, flags);
4421 /* After entering hibernation, hardware is no more accessible */
4422 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4425 hsotg->lx_state = DWC2_L2;
4427 spin_unlock_irqrestore(&hsotg->lock, flags);
4432 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4434 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4435 unsigned long flags;
4438 spin_lock_irqsave(&hsotg->lock, flags);
4440 if (hsotg->lx_state != DWC2_L2)
4443 if (!hsotg->core_params->hibernation) {
4444 hsotg->lx_state = DWC2_L0;
4449 * Set HW accessible bit before powering on the controller
4450 * since an interrupt may rise.
4452 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4455 * Enable power if not already done.
4456 * This must not be spinlocked since duration
4457 * of this call is unknown.
4459 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4460 spin_unlock_irqrestore(&hsotg->lock, flags);
4461 usb_phy_set_suspend(hsotg->uphy, false);
4462 spin_lock_irqsave(&hsotg->lock, flags);
4465 /* Exit hibernation */
4466 ret = dwc2_exit_hibernation(hsotg, true);
4467 if (ret && (ret != -ENOTSUPP))
4468 dev_err(hsotg->dev, "exit hibernation failed\n");
4470 hsotg->lx_state = DWC2_L0;
4472 spin_unlock_irqrestore(&hsotg->lock, flags);
4474 if (hsotg->bus_suspended) {
4475 spin_lock_irqsave(&hsotg->lock, flags);
4476 hsotg->flags.b.port_suspend_change = 1;
4477 spin_unlock_irqrestore(&hsotg->lock, flags);
4478 dwc2_port_resume(hsotg);
4480 /* Wait for controller to correctly update D+/D- level */
4481 usleep_range(3000, 5000);
4484 * Clear Port Enable and Port Status changes.
4485 * Enable Port Power.
4487 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4488 HPRT0_ENACHG, hsotg->regs + HPRT0);
4489 /* Wait for controller to detect Port Connect */
4490 usleep_range(5000, 7000);
4495 spin_unlock_irqrestore(&hsotg->lock, flags);
4500 /* Returns the current frame number */
4501 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4503 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4505 return dwc2_hcd_get_frame_number(hsotg);
4508 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4511 #ifdef VERBOSE_DEBUG
4512 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4516 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4517 dev_vdbg(hsotg->dev, " Device address: %d\n",
4518 usb_pipedevice(urb->pipe));
4519 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4520 usb_pipeendpoint(urb->pipe),
4521 usb_pipein(urb->pipe) ? "IN" : "OUT");
4523 switch (usb_pipetype(urb->pipe)) {
4525 pipetype = "CONTROL";
4530 case PIPE_INTERRUPT:
4531 pipetype = "INTERRUPT";
4533 case PIPE_ISOCHRONOUS:
4534 pipetype = "ISOCHRONOUS";
4537 pipetype = "UNKNOWN";
4541 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4542 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4545 switch (urb->dev->speed) {
4546 case USB_SPEED_HIGH:
4549 case USB_SPEED_FULL:
4560 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4561 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4562 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4563 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4564 urb->transfer_buffer_length);
4565 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4566 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4567 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4568 urb->setup_packet, (unsigned long)urb->setup_dma);
4569 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4571 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4574 for (i = 0; i < urb->number_of_packets; i++) {
4575 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4576 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4577 urb->iso_frame_desc[i].offset,
4578 urb->iso_frame_desc[i].length);
4585 * Starts processing a USB transfer request specified by a USB Request Block
4586 * (URB). mem_flags indicates the type of memory allocation to use while
4587 * processing this URB.
4589 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4592 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4593 struct usb_host_endpoint *ep = urb->ep;
4594 struct dwc2_hcd_urb *dwc2_urb;
4597 int alloc_bandwidth = 0;
4601 unsigned long flags;
4603 bool qh_allocated = false;
4604 struct dwc2_qtd *qtd;
4607 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4608 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4614 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4615 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4616 spin_lock_irqsave(&hsotg->lock, flags);
4617 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4618 alloc_bandwidth = 1;
4619 spin_unlock_irqrestore(&hsotg->lock, flags);
4622 switch (usb_pipetype(urb->pipe)) {
4624 ep_type = USB_ENDPOINT_XFER_CONTROL;
4626 case PIPE_ISOCHRONOUS:
4627 ep_type = USB_ENDPOINT_XFER_ISOC;
4630 ep_type = USB_ENDPOINT_XFER_BULK;
4632 case PIPE_INTERRUPT:
4633 ep_type = USB_ENDPOINT_XFER_INT;
4636 dev_warn(hsotg->dev, "Wrong ep type\n");
4639 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4644 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4645 usb_pipeendpoint(urb->pipe), ep_type,
4646 usb_pipein(urb->pipe),
4647 usb_maxpacket(urb->dev, urb->pipe,
4648 !(usb_pipein(urb->pipe))));
4650 buf = urb->transfer_buffer;
4652 if (hcd->self.uses_dma) {
4653 if (!buf && (urb->transfer_dma & 3)) {
4655 "%s: unaligned transfer with no transfer_buffer",
4662 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4663 tflags |= URB_GIVEBACK_ASAP;
4664 if (urb->transfer_flags & URB_ZERO_PACKET)
4665 tflags |= URB_SEND_ZERO_PACKET;
4667 dwc2_urb->priv = urb;
4668 dwc2_urb->buf = buf;
4669 dwc2_urb->dma = urb->transfer_dma;
4670 dwc2_urb->length = urb->transfer_buffer_length;
4671 dwc2_urb->setup_packet = urb->setup_packet;
4672 dwc2_urb->setup_dma = urb->setup_dma;
4673 dwc2_urb->flags = tflags;
4674 dwc2_urb->interval = urb->interval;
4675 dwc2_urb->status = -EINPROGRESS;
4677 for (i = 0; i < urb->number_of_packets; ++i)
4678 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4679 urb->iso_frame_desc[i].offset,
4680 urb->iso_frame_desc[i].length);
4682 urb->hcpriv = dwc2_urb;
4683 qh = (struct dwc2_qh *) ep->hcpriv;
4684 /* Create QH for the endpoint if it doesn't exist */
4686 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4692 qh_allocated = true;
4695 qtd = kzalloc(sizeof(*qtd), mem_flags);
4701 spin_lock_irqsave(&hsotg->lock, flags);
4702 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4706 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4710 if (alloc_bandwidth) {
4711 dwc2_allocate_bus_bandwidth(hcd,
4712 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4716 spin_unlock_irqrestore(&hsotg->lock, flags);
4721 dwc2_urb->priv = NULL;
4722 usb_hcd_unlink_urb_from_ep(hcd, urb);
4723 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4724 qh->channel->qh = NULL;
4726 spin_unlock_irqrestore(&hsotg->lock, flags);
4732 struct dwc2_qtd *qtd2, *qtd2_tmp;
4735 dwc2_hcd_qh_unlink(hsotg, qh);
4736 /* Free each QTD in the QH's QTD list */
4737 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4739 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4740 dwc2_hcd_qh_free(hsotg, qh);
4749 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4751 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4754 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4756 unsigned long flags;
4758 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4759 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4761 spin_lock_irqsave(&hsotg->lock, flags);
4763 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4768 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4772 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4774 usb_hcd_unlink_urb_from_ep(hcd, urb);
4779 /* Higher layer software sets URB status */
4780 spin_unlock(&hsotg->lock);
4781 usb_hcd_giveback_urb(hcd, urb, status);
4782 spin_lock(&hsotg->lock);
4784 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4785 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4787 spin_unlock_irqrestore(&hsotg->lock, flags);
4793 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4794 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4795 * must already be dequeued.
4797 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4798 struct usb_host_endpoint *ep)
4800 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4803 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4804 ep->desc.bEndpointAddress, ep->hcpriv);
4805 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4809 * Resets endpoint specific parameter values, in current version used to reset
4810 * the data toggle (as a WA). This function can be called from usb_clear_halt
4813 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4814 struct usb_host_endpoint *ep)
4816 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4817 unsigned long flags;
4820 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4821 ep->desc.bEndpointAddress);
4823 spin_lock_irqsave(&hsotg->lock, flags);
4824 dwc2_hcd_endpoint_reset(hsotg, ep);
4825 spin_unlock_irqrestore(&hsotg->lock, flags);
4829 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4830 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4833 * This function is called by the USB core when an interrupt occurs
4835 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4837 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4839 return dwc2_handle_hcd_intr(hsotg);
4843 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4844 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4845 * is the status change indicator for the single root port. Returns 1 if either
4846 * change indicator is 1, otherwise returns 0.
4848 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4850 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4852 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4856 /* Handles hub class-specific requests */
4857 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4858 u16 windex, char *buf, u16 wlength)
4860 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4861 wvalue, windex, buf, wlength);
4865 /* Handles hub TT buffer clear completions */
4866 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4867 struct usb_host_endpoint *ep)
4869 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4871 unsigned long flags;
4877 spin_lock_irqsave(&hsotg->lock, flags);
4878 qh->tt_buffer_dirty = 0;
4880 if (hsotg->flags.b.port_connect_status)
4881 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4883 spin_unlock_irqrestore(&hsotg->lock, flags);
4886 static struct hc_driver dwc2_hc_driver = {
4887 .description = "dwc2_hsotg",
4888 .product_desc = "DWC OTG Controller",
4889 .hcd_priv_size = sizeof(struct wrapper_priv_data),
4891 .irq = _dwc2_hcd_irq,
4892 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
4894 .start = _dwc2_hcd_start,
4895 .stop = _dwc2_hcd_stop,
4896 .urb_enqueue = _dwc2_hcd_urb_enqueue,
4897 .urb_dequeue = _dwc2_hcd_urb_dequeue,
4898 .endpoint_disable = _dwc2_hcd_endpoint_disable,
4899 .endpoint_reset = _dwc2_hcd_endpoint_reset,
4900 .get_frame_number = _dwc2_hcd_get_frame_number,
4902 .hub_status_data = _dwc2_hcd_hub_status_data,
4903 .hub_control = _dwc2_hcd_hub_control,
4904 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
4906 .bus_suspend = _dwc2_hcd_suspend,
4907 .bus_resume = _dwc2_hcd_resume,
4909 .map_urb_for_dma = dwc2_map_urb_for_dma,
4910 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
4914 * Frees secondary storage associated with the dwc2_hsotg structure contained
4915 * in the struct usb_hcd field
4917 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4923 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4925 /* Free memory for QH/QTD lists */
4926 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4927 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4928 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4929 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4930 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
4931 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
4933 /* Free memory for the host channels */
4934 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
4935 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
4938 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
4940 hsotg->hc_ptr_array[i] = NULL;
4945 if (hsotg->core_params->dma_enable > 0) {
4946 if (hsotg->status_buf) {
4947 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
4949 hsotg->status_buf_dma);
4950 hsotg->status_buf = NULL;
4953 kfree(hsotg->status_buf);
4954 hsotg->status_buf = NULL;
4957 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
4959 /* Disable all interrupts */
4960 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
4961 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
4962 dwc2_writel(0, hsotg->regs + GINTMSK);
4964 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
4965 dctl = dwc2_readl(hsotg->regs + DCTL);
4966 dctl |= DCTL_SFTDISCON;
4967 dwc2_writel(dctl, hsotg->regs + DCTL);
4970 if (hsotg->wq_otg) {
4971 if (!cancel_work_sync(&hsotg->wf_otg))
4972 flush_workqueue(hsotg->wq_otg);
4973 destroy_workqueue(hsotg->wq_otg);
4976 del_timer(&hsotg->wkp_timer);
4979 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
4981 /* Turn off all host-specific interrupts */
4982 dwc2_disable_host_interrupts(hsotg);
4984 dwc2_hcd_free(hsotg);
4988 * Initializes the HCD. This function allocates memory for and initializes the
4989 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
4990 * USB bus with the core and calls the hc_driver->start() function. It returns
4991 * a negative error on failure.
4993 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
4995 struct usb_hcd *hcd;
4996 struct dwc2_host_chan *channel;
4998 int i, num_channels;
5004 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5008 hcfg = dwc2_readl(hsotg->regs + HCFG);
5009 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5011 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5012 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
5013 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5014 if (!hsotg->frame_num_array)
5016 hsotg->last_frame_num_array = kzalloc(
5017 sizeof(*hsotg->last_frame_num_array) *
5018 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5019 if (!hsotg->last_frame_num_array)
5022 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5024 /* Check if the bus driver or platform code has setup a dma_mask */
5025 if (hsotg->core_params->dma_enable > 0 &&
5026 hsotg->dev->dma_mask == NULL) {
5027 dev_warn(hsotg->dev,
5028 "dma_mask not set, disabling DMA\n");
5029 hsotg->core_params->dma_enable = 0;
5030 hsotg->core_params->dma_desc_enable = 0;
5033 /* Set device flags indicating whether the HCD supports DMA */
5034 if (hsotg->core_params->dma_enable > 0) {
5035 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5036 dev_warn(hsotg->dev, "can't set DMA mask\n");
5037 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5038 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5041 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5045 if (hsotg->core_params->dma_enable <= 0)
5046 hcd->self.uses_dma = 0;
5050 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
5054 * Disable the global interrupt until all the interrupt handlers are
5057 dwc2_disable_global_interrupts(hsotg);
5059 /* Initialize the DWC_otg core, and select the Phy type */
5060 retval = dwc2_core_init(hsotg, true);
5064 /* Create new workqueue and init work */
5066 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5067 if (!hsotg->wq_otg) {
5068 dev_err(hsotg->dev, "Failed to create workqueue\n");
5071 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5073 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
5074 (unsigned long)hsotg);
5076 /* Initialize the non-periodic schedule */
5077 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5078 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5080 /* Initialize the periodic schedule */
5081 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5082 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5083 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5084 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5086 INIT_LIST_HEAD(&hsotg->split_order);
5089 * Create a host channel descriptor for each host channel implemented
5090 * in the controller. Initialize the channel descriptor array.
5092 INIT_LIST_HEAD(&hsotg->free_hc_list);
5093 num_channels = hsotg->core_params->host_channels;
5094 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5096 for (i = 0; i < num_channels; i++) {
5097 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5098 if (channel == NULL)
5100 channel->hc_num = i;
5101 INIT_LIST_HEAD(&channel->split_order_list_entry);
5102 hsotg->hc_ptr_array[i] = channel;
5105 /* Initialize hsotg start work */
5106 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5108 /* Initialize port reset work */
5109 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5112 * Allocate space for storing data on status transactions. Normally no
5113 * data is sent, but this space acts as a bit bucket. This must be
5114 * done after usb_add_hcd since that function allocates the DMA buffer
5117 if (hsotg->core_params->dma_enable > 0)
5118 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5119 DWC2_HCD_STATUS_BUF_SIZE,
5120 &hsotg->status_buf_dma, GFP_KERNEL);
5122 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5125 if (!hsotg->status_buf)
5129 * Create kmem caches to handle descriptor buffers in descriptor
5131 * Alignment must be set to 512 bytes.
5133 if (hsotg->core_params->dma_desc_enable ||
5134 hsotg->core_params->dma_desc_fs_enable) {
5135 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5136 sizeof(struct dwc2_hcd_dma_desc) *
5137 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5139 if (!hsotg->desc_gen_cache) {
5141 "unable to create dwc2 generic desc cache\n");
5144 * Disable descriptor dma mode since it will not be
5147 hsotg->core_params->dma_desc_enable = 0;
5148 hsotg->core_params->dma_desc_fs_enable = 0;
5151 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5152 sizeof(struct dwc2_hcd_dma_desc) *
5153 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5154 if (!hsotg->desc_hsisoc_cache) {
5156 "unable to create dwc2 hs isoc desc cache\n");
5158 kmem_cache_destroy(hsotg->desc_gen_cache);
5161 * Disable descriptor dma mode since it will not be
5164 hsotg->core_params->dma_desc_enable = 0;
5165 hsotg->core_params->dma_desc_fs_enable = 0;
5169 hsotg->otg_port = 1;
5170 hsotg->frame_list = NULL;
5171 hsotg->frame_list_dma = 0;
5172 hsotg->periodic_qh_count = 0;
5174 /* Initiate lx_state to L3 disconnected state */
5175 hsotg->lx_state = DWC2_L3;
5177 hcd->self.otg_port = hsotg->otg_port;
5179 /* Don't support SG list at this point */
5180 hcd->self.sg_tablesize = 0;
5182 if (!IS_ERR_OR_NULL(hsotg->uphy))
5183 otg_set_host(hsotg->uphy->otg, &hcd->self);
5186 * Finish generic HCD initialization and start the HCD. This function
5187 * allocates the DMA buffer pool, registers the USB bus, requests the
5188 * IRQ line, and calls hcd_start method.
5190 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
5194 device_wakeup_enable(hcd->self.controller);
5196 dwc2_hcd_dump_state(hsotg);
5198 dwc2_enable_global_interrupts(hsotg);
5203 kmem_cache_destroy(hsotg->desc_gen_cache);
5204 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5206 dwc2_hcd_release(hsotg);
5211 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5212 kfree(hsotg->last_frame_num_array);
5213 kfree(hsotg->frame_num_array);
5216 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5222 * Frees memory and resources associated with the HCD and deregisters the bus.
5224 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5226 struct usb_hcd *hcd;
5228 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5230 hcd = dwc2_hsotg_to_hcd(hsotg);
5231 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5234 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5239 if (!IS_ERR_OR_NULL(hsotg->uphy))
5240 otg_set_host(hsotg->uphy->otg, NULL);
5242 usb_remove_hcd(hcd);
5245 kmem_cache_destroy(hsotg->desc_gen_cache);
5246 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5248 dwc2_hcd_release(hsotg);
5251 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5252 kfree(hsotg->last_frame_num_array);
5253 kfree(hsotg->frame_num_array);
5258 * dwc2_backup_host_registers() - Backup controller host registers.
5259 * When suspending usb bus, registers needs to be backuped
5260 * if controller power is disabled once suspended.
5262 * @hsotg: Programming view of the DWC_otg controller
5264 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5266 struct dwc2_hregs_backup *hr;
5269 dev_dbg(hsotg->dev, "%s\n", __func__);
5271 /* Backup Host regs */
5272 hr = &hsotg->hr_backup;
5273 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5274 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
5275 for (i = 0; i < hsotg->core_params->host_channels; ++i)
5276 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5278 hr->hprt0 = dwc2_read_hprt0(hsotg);
5279 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5286 * dwc2_restore_host_registers() - Restore controller host registers.
5287 * When resuming usb bus, device registers needs to be restored
5288 * if controller power were disabled.
5290 * @hsotg: Programming view of the DWC_otg controller
5292 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5294 struct dwc2_hregs_backup *hr;
5297 dev_dbg(hsotg->dev, "%s\n", __func__);
5299 /* Restore host regs */
5300 hr = &hsotg->hr_backup;
5302 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5308 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5309 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5311 for (i = 0; i < hsotg->core_params->host_channels; ++i)
5312 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5314 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5315 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5316 hsotg->frame_number = 0;