drivers/usb/dwc2/hcd.c

   1 /*
   2  * hcd.c - DesignWare HS OTG Controller host-mode routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the core HCD code, and implements the Linux hc_driver
  39  * API
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/delay.h>
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/usb.h>
  50
  51 #include <linux/usb/hcd.h>
  52 #include <linux/usb/ch11.h>
  53
  54 #include "core.h"
  55 #include "hcd.h"
  56
  57 /**
  58  * dwc2_dump_channel_info() - Prints the state of a host channel
  59  *
  60  * @hsotg: Programming view of DWC_otg controller
  61  * @chan:  Pointer to the channel to dump
  62  *
  63  * Must be called with interrupt disabled and spinlock held
  64  *
  65  * NOTE: This function will be removed once the peripheral controller code
  66  * is integrated and the driver is stable
  67  */
  68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
  69                                    struct dwc2_host_chan *chan)
  70 {
  71 #ifdef VERBOSE_DEBUG
  72         int num_channels = hsotg->core_params->host_channels;
  73         struct dwc2_qh *qh;
  74         u32 hcchar;
  75         u32 hcsplt;
  76         u32 hctsiz;
  77         u32 hc_dma;
  78         int i;
  79
  80         if (chan == NULL)
  81                 return;
  82
  83         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
  84         hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
  85         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
  86         hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
  87
  88         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
  89         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
  90                 hcchar, hcsplt);
  91         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
  92                 hctsiz, hc_dma);
  93         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
  94                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
  95         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
  96         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
  97         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
  98         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
  99         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 100         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 101         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 102                 (unsigned long)chan->xfer_dma);
 103         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 104         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 105         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 106         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 107                             qh_list_entry)
 108                 dev_dbg(hsotg->dev, "    %p\n", qh);
 109         dev_dbg(hsotg->dev, "  NP active sched:\n");
 110         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 111                             qh_list_entry)
 112                 dev_dbg(hsotg->dev, "    %p\n", qh);
 113         dev_dbg(hsotg->dev, "  Channels:\n");
 114         for (i = 0; i < num_channels; i++) {
 115                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 116
 117                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 118         }
 119 #endif /* VERBOSE_DEBUG */
 120 }
 121
 122 /*
 123  * Processes all the URBs in a single list of QHs. Completes them with
 124  * -ETIMEDOUT and frees the QTD.
 125  *
 126  * Must be called with interrupt disabled and spinlock held
 127  */
 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
 129                                       struct list_head *qh_list)
 130 {
 131         struct dwc2_qh *qh, *qh_tmp;
 132         struct dwc2_qtd *qtd, *qtd_tmp;
 133
 134         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 135                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 136                                          qtd_list_entry) {
 137                         dwc2_host_complete(hsotg, qtd, -ECONNRESET);
 138                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 139                 }
 140         }
 141 }
 142
 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
 144                               struct list_head *qh_list)
 145 {
 146         struct dwc2_qtd *qtd, *qtd_tmp;
 147         struct dwc2_qh *qh, *qh_tmp;
 148         unsigned long flags;
 149
 150         if (!qh_list->next)
 151                 /* The list hasn't been initialized yet */
 152                 return;
 153
 154         spin_lock_irqsave(&hsotg->lock, flags);
 155
 156         /* Ensure there are no QTDs or URBs left */
 157         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
 158
 159         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 160                 dwc2_hcd_qh_unlink(hsotg, qh);
 161
 162                 /* Free each QTD in the QH's QTD list */
 163                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 164                                          qtd_list_entry)
 165                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 166
 167                 spin_unlock_irqrestore(&hsotg->lock, flags);
 168                 dwc2_hcd_qh_free(hsotg, qh);
 169                 spin_lock_irqsave(&hsotg->lock, flags);
 170         }
 171
 172         spin_unlock_irqrestore(&hsotg->lock, flags);
 173 }
 174
 175 /*
 176  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
 177  * and periodic schedules. The QTD associated with each URB is removed from
 178  * the schedule and freed. This function may be called when a disconnect is
 179  * detected or when the HCD is being stopped.
 180  *
 181  * Must be called with interrupt disabled and spinlock held
 182  */
 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
 184 {
 185         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
 186         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
 187         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
 188         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
 189         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
 190         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
 191 }
 192
 193 /**
 194  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
 195  *
 196  * @hsotg: Pointer to struct dwc2_hsotg
 197  */
 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
 199 {
 200         u32 hprt0;
 201
 202         if (hsotg->op_state == OTG_STATE_B_HOST) {
 203                 /*
 204                  * Reset the port. During a HNP mode switch the reset
 205                  * needs to occur within 1ms and have a duration of at
 206                  * least 50ms.
 207                  */
 208                 hprt0 = dwc2_read_hprt0(hsotg);
 209                 hprt0 |= HPRT0_RST;
 210                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
 211         }
 212
 213         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
 214                            msecs_to_jiffies(50));
 215 }
 216
 217 /* Must be called with interrupt disabled and spinlock held */
 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
 219 {
 220         int num_channels = hsotg->core_params->host_channels;
 221         struct dwc2_host_chan *channel;
 222         u32 hcchar;
 223         int i;
 224
 225         if (hsotg->core_params->dma_enable <= 0) {
 226                 /* Flush out any channel requests in slave mode */
 227                 for (i = 0; i < num_channels; i++) {
 228                         channel = hsotg->hc_ptr_array[i];
 229                         if (!list_empty(&channel->hc_list_entry))
 230                                 continue;
 231                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
 232                         if (hcchar & HCCHAR_CHENA) {
 233                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
 234                                 hcchar |= HCCHAR_CHDIS;
 235                                 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
 236                         }
 237                 }
 238         }
 239
 240         for (i = 0; i < num_channels; i++) {
 241                 channel = hsotg->hc_ptr_array[i];
 242                 if (!list_empty(&channel->hc_list_entry))
 243                         continue;
 244                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
 245                 if (hcchar & HCCHAR_CHENA) {
 246                         /* Halt the channel */
 247                         hcchar |= HCCHAR_CHDIS;
 248                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
 249                 }
 250
 251                 dwc2_hc_cleanup(hsotg, channel);
 252                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
 253                 /*
 254                  * Added for Descriptor DMA to prevent channel double cleanup in
 255                  * release_channel_ddma(), which is called from ep_disable when
 256                  * device disconnects
 257                  */
 258                 channel->qh = NULL;
 259         }
 260         /* All channels have been freed, mark them available */
 261         if (hsotg->core_params->uframe_sched > 0) {
 262                 hsotg->available_host_channels =
 263                         hsotg->core_params->host_channels;
 264         } else {
 265                 hsotg->non_periodic_channels = 0;
 266                 hsotg->periodic_channels = 0;
 267         }
 268 }
 269
 270 /**
 271  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
 272  *
 273  * @hsotg: Pointer to struct dwc2_hsotg
 274  *
 275  * Must be called with interrupt disabled and spinlock held
 276  */
 277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
 278 {
 279         u32 intr;
 280
 281         /* Set status flags for the hub driver */
 282         hsotg->flags.b.port_connect_status_change = 1;
 283         hsotg->flags.b.port_connect_status = 0;
 284
 285         /*
 286          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 287          * interrupt mask and status bits and disabling subsequent host
 288          * channel interrupts.
 289          */
 290         intr = dwc2_readl(hsotg->regs + GINTMSK);
 291         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
 292         dwc2_writel(intr, hsotg->regs + GINTMSK);
 293         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
 294         dwc2_writel(intr, hsotg->regs + GINTSTS);
 295
 296         /*
 297          * Turn off the vbus power only if the core has transitioned to device
 298          * mode. If still in host mode, need to keep power on to detect a
 299          * reconnection.
 300          */
 301         if (dwc2_is_device_mode(hsotg)) {
 302                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
 303                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
 304                         dwc2_writel(0, hsotg->regs + HPRT0);
 305                 }
 306
 307                 dwc2_disable_host_interrupts(hsotg);
 308         }
 309
 310         /* Respond with an error status to all URBs in the schedule */
 311         dwc2_kill_all_urbs(hsotg);
 312
 313         if (dwc2_is_host_mode(hsotg))
 314                 /* Clean up any host channels that were in use */
 315                 dwc2_hcd_cleanup_channels(hsotg);
 316
 317         dwc2_host_disconnect(hsotg);
 318 }
 319
 320 /**
 321  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
 322  *
 323  * @hsotg: Pointer to struct dwc2_hsotg
 324  */
 325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
 326 {
 327         if (hsotg->bus_suspended) {
 328                 hsotg->flags.b.port_suspend_change = 1;
 329                 usb_hcd_resume_root_hub(hsotg->priv);
 330         }
 331
 332         if (hsotg->lx_state == DWC2_L1)
 333                 hsotg->flags.b.port_l1_change = 1;
 334 }
 335
 336 /**
 337  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
 338  *
 339  * @hsotg: Pointer to struct dwc2_hsotg
 340  *
 341  * Must be called with interrupt disabled and spinlock held
 342  */
 343 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
 344 {
 345         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
 346
 347         /*
 348          * The root hub should be disconnected before this function is called.
 349          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 350          * and the QH lists (via ..._hcd_endpoint_disable).
 351          */
 352
 353         /* Turn off all host-specific interrupts */
 354         dwc2_disable_host_interrupts(hsotg);
 355
 356         /* Turn off the vbus power */
 357         dev_dbg(hsotg->dev, "PortPower off\n");
 358         dwc2_writel(0, hsotg->regs + HPRT0);
 359 }
 360
 361 /* Caller must hold driver lock */
 362 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
 363                                 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
 364                                 struct dwc2_qtd *qtd)
 365 {
 366         u32 intr_mask;
 367         int retval;
 368         int dev_speed;
 369
 370         if (!hsotg->flags.b.port_connect_status) {
 371                 /* No longer connected */
 372                 dev_err(hsotg->dev, "Not connected\n");
 373                 return -ENODEV;
 374         }
 375
 376         dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
 377
 378         /* Some configurations cannot support LS traffic on a FS root port */
 379         if ((dev_speed == USB_SPEED_LOW) &&
 380             (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
 381             (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
 382                 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 383                 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 384
 385                 if (prtspd == HPRT0_SPD_FULL_SPEED)
 386                         return -ENODEV;
 387         }
 388
 389         if (!qtd)
 390                 return -EINVAL;
 391
 392         dwc2_hcd_qtd_init(qtd, urb);
 393         retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
 394         if (retval) {
 395                 dev_err(hsotg->dev,
 396                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
 397                         retval);
 398                 return retval;
 399         }
 400
 401         intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
 402         if (!(intr_mask & GINTSTS_SOF)) {
 403                 enum dwc2_transaction_type tr_type;
 404
 405                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
 406                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
 407                         /*
 408                          * Do not schedule SG transactions until qtd has
 409                          * URB_GIVEBACK_ASAP set
 410                          */
 411                         return 0;
 412
 413                 tr_type = dwc2_hcd_select_transactions(hsotg);
 414                 if (tr_type != DWC2_TRANSACTION_NONE)
 415                         dwc2_hcd_queue_transactions(hsotg, tr_type);
 416         }
 417
 418         return 0;
 419 }
 420
 421 /* Must be called with interrupt disabled and spinlock held */
 422 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
 423                                 struct dwc2_hcd_urb *urb)
 424 {
 425         struct dwc2_qh *qh;
 426         struct dwc2_qtd *urb_qtd;
 427
 428         urb_qtd = urb->qtd;
 429         if (!urb_qtd) {
 430                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
 431                 return -EINVAL;
 432         }
 433
 434         qh = urb_qtd->qh;
 435         if (!qh) {
 436                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
 437                 return -EINVAL;
 438         }
 439
 440         urb->priv = NULL;
 441
 442         if (urb_qtd->in_process && qh->channel) {
 443                 dwc2_dump_channel_info(hsotg, qh->channel);
 444
 445                 /* The QTD is in process (it has been assigned to a channel) */
 446                 if (hsotg->flags.b.port_connect_status)
 447                         /*
 448                          * If still connected (i.e. in host mode), halt the
 449                          * channel so it can be used for other transfers. If
 450                          * no longer connected, the host registers can't be
 451                          * written to halt the channel since the core is in
 452                          * device mode.
 453                          */
 454                         dwc2_hc_halt(hsotg, qh->channel,
 455                                      DWC2_HC_XFER_URB_DEQUEUE);
 456         }
 457
 458         /*
 459          * Free the QTD and clean up the associated QH. Leave the QH in the
 460          * schedule if it has any remaining QTDs.
 461          */
 462         if (hsotg->core_params->dma_desc_enable <= 0) {
 463                 u8 in_process = urb_qtd->in_process;
 464
 465                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 466                 if (in_process) {
 467                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
 468                         qh->channel = NULL;
 469                 } else if (list_empty(&qh->qtd_list)) {
 470                         dwc2_hcd_qh_unlink(hsotg, qh);
 471                 }
 472         } else {
 473                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 474         }
 475
 476         return 0;
 477 }
 478
 479 /* Must NOT be called with interrupt disabled or spinlock held */
 480 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
 481                                      struct usb_host_endpoint *ep, int retry)
 482 {
 483         struct dwc2_qtd *qtd, *qtd_tmp;
 484         struct dwc2_qh *qh;
 485         unsigned long flags;
 486         int rc;
 487
 488         spin_lock_irqsave(&hsotg->lock, flags);
 489
 490         qh = ep->hcpriv;
 491         if (!qh) {
 492                 rc = -EINVAL;
 493                 goto err;
 494         }
 495
 496         while (!list_empty(&qh->qtd_list) && retry--) {
 497                 if (retry == 0) {
 498                         dev_err(hsotg->dev,
 499                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
 500                         rc = -EBUSY;
 501                         goto err;
 502                 }
 503
 504                 spin_unlock_irqrestore(&hsotg->lock, flags);
 505                 usleep_range(20000, 40000);
 506                 spin_lock_irqsave(&hsotg->lock, flags);
 507                 qh = ep->hcpriv;
 508                 if (!qh) {
 509                         rc = -EINVAL;
 510                         goto err;
 511                 }
 512         }
 513
 514         dwc2_hcd_qh_unlink(hsotg, qh);
 515
 516         /* Free each QTD in the QH's QTD list */
 517         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
 518                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 519
 520         ep->hcpriv = NULL;
 521         spin_unlock_irqrestore(&hsotg->lock, flags);
 522         dwc2_hcd_qh_free(hsotg, qh);
 523
 524         return 0;
 525
 526 err:
 527         ep->hcpriv = NULL;
 528         spin_unlock_irqrestore(&hsotg->lock, flags);
 529
 530         return rc;
 531 }
 532
 533 /* Must be called with interrupt disabled and spinlock held */
 534 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
 535                                    struct usb_host_endpoint *ep)
 536 {
 537         struct dwc2_qh *qh = ep->hcpriv;
 538
 539         if (!qh)
 540                 return -EINVAL;
 541
 542         qh->data_toggle = DWC2_HC_PID_DATA0;
 543
 544         return 0;
 545 }
 546
 547 /*
 548  * Initializes dynamic portions of the DWC_otg HCD state
 549  *
 550  * Must be called with interrupt disabled and spinlock held
 551  */
 552 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
 553 {
 554         struct dwc2_host_chan *chan, *chan_tmp;
 555         int num_channels;
 556         int i;
 557
 558         hsotg->flags.d32 = 0;
 559         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
 560
 561         if (hsotg->core_params->uframe_sched > 0) {
 562                 hsotg->available_host_channels =
 563                         hsotg->core_params->host_channels;
 564         } else {
 565                 hsotg->non_periodic_channels = 0;
 566                 hsotg->periodic_channels = 0;
 567         }
 568
 569         /*
 570          * Put all channels in the free channel list and clean up channel
 571          * states
 572          */
 573         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
 574                                  hc_list_entry)
 575                 list_del_init(&chan->hc_list_entry);
 576
 577         num_channels = hsotg->core_params->host_channels;
 578         for (i = 0; i < num_channels; i++) {
 579                 chan = hsotg->hc_ptr_array[i];
 580                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 581                 dwc2_hc_cleanup(hsotg, chan);
 582         }
 583
 584         /* Initialize the DWC core for host mode operation */
 585         dwc2_core_host_init(hsotg);
 586 }
 587
 588 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
 589                                struct dwc2_host_chan *chan,
 590                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
 591 {
 592         int hub_addr, hub_port;
 593
 594         chan->do_split = 1;
 595         chan->xact_pos = qtd->isoc_split_pos;
 596         chan->complete_split = qtd->complete_split;
 597         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
 598         chan->hub_addr = (u8)hub_addr;
 599         chan->hub_port = (u8)hub_port;
 600 }
 601
 602 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
 603                                struct dwc2_host_chan *chan,
 604                                struct dwc2_qtd *qtd, void *bufptr)
 605 {
 606         struct dwc2_hcd_urb *urb = qtd->urb;
 607         struct dwc2_hcd_iso_packet_desc *frame_desc;
 608
 609         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
 610         case USB_ENDPOINT_XFER_CONTROL:
 611                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
 612
 613                 switch (qtd->control_phase) {
 614                 case DWC2_CONTROL_SETUP:
 615                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
 616                         chan->do_ping = 0;
 617                         chan->ep_is_in = 0;
 618                         chan->data_pid_start = DWC2_HC_PID_SETUP;
 619                         if (hsotg->core_params->dma_enable > 0)
 620                                 chan->xfer_dma = urb->setup_dma;
 621                         else
 622                                 chan->xfer_buf = urb->setup_packet;
 623                         chan->xfer_len = 8;
 624                         bufptr = NULL;
 625                         break;
 626
 627                 case DWC2_CONTROL_DATA:
 628                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
 629                         chan->data_pid_start = qtd->data_toggle;
 630                         break;
 631
 632                 case DWC2_CONTROL_STATUS:
 633                         /*
 634                          * Direction is opposite of data direction or IN if no
 635                          * data
 636                          */
 637                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
 638                         if (urb->length == 0)
 639                                 chan->ep_is_in = 1;
 640                         else
 641                                 chan->ep_is_in =
 642                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
 643                         if (chan->ep_is_in)
 644                                 chan->do_ping = 0;
 645                         chan->data_pid_start = DWC2_HC_PID_DATA1;
 646                         chan->xfer_len = 0;
 647                         if (hsotg->core_params->dma_enable > 0)
 648                                 chan->xfer_dma = hsotg->status_buf_dma;
 649                         else
 650                                 chan->xfer_buf = hsotg->status_buf;
 651                         bufptr = NULL;
 652                         break;
 653                 }
 654                 break;
 655
 656         case USB_ENDPOINT_XFER_BULK:
 657                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
 658                 break;
 659
 660         case USB_ENDPOINT_XFER_INT:
 661                 chan->ep_type = USB_ENDPOINT_XFER_INT;
 662                 break;
 663
 664         case USB_ENDPOINT_XFER_ISOC:
 665                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
 666                 if (hsotg->core_params->dma_desc_enable > 0)
 667                         break;
 668
 669                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 670                 frame_desc->status = 0;
 671
 672                 if (hsotg->core_params->dma_enable > 0) {
 673                         chan->xfer_dma = urb->dma;
 674                         chan->xfer_dma += frame_desc->offset +
 675                                         qtd->isoc_split_offset;
 676                 } else {
 677                         chan->xfer_buf = urb->buf;
 678                         chan->xfer_buf += frame_desc->offset +
 679                                         qtd->isoc_split_offset;
 680                 }
 681
 682                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
 683
 684                 /* For non-dword aligned buffers */
 685                 if (hsotg->core_params->dma_enable > 0 &&
 686                     (chan->xfer_dma & 0x3))
 687                         bufptr = (u8 *)urb->buf + frame_desc->offset +
 688                                         qtd->isoc_split_offset;
 689                 else
 690                         bufptr = NULL;
 691
 692                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
 693                         if (chan->xfer_len <= 188)
 694                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
 695                         else
 696                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
 697                 }
 698                 break;
 699         }
 700
 701         return bufptr;
 702 }
 703
 704 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 705                                    struct dwc2_host_chan *chan,
 706                                    struct dwc2_hcd_urb *urb, void *bufptr)
 707 {
 708         u32 buf_size;
 709         struct urb *usb_urb;
 710         struct usb_hcd *hcd;
 711
 712         if (!qh->dw_align_buf) {
 713                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
 714                         buf_size = hsotg->core_params->max_transfer_size;
 715                 else
 716                         /* 3072 = 3 max-size Isoc packets */
 717                         buf_size = 3072;
 718
 719                 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA);
 720                 if (!qh->dw_align_buf)
 721                         return -ENOMEM;
 722                 qh->dw_align_buf_size = buf_size;
 723         }
 724
 725         if (chan->xfer_len) {
 726                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 727                 usb_urb = urb->priv;
 728
 729                 if (usb_urb) {
 730                         if (usb_urb->transfer_flags &
 731                             (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
 732                              URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
 733                                 hcd = dwc2_hsotg_to_hcd(hsotg);
 734                                 usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
 735                         }
 736                         if (!chan->ep_is_in)
 737                                 memcpy(qh->dw_align_buf, bufptr,
 738                                        chan->xfer_len);
 739                 } else {
 740                         dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
 741                 }
 742         }
 743
 744         qh->dw_align_buf_dma = dma_map_single(hsotg->dev,
 745                         qh->dw_align_buf, qh->dw_align_buf_size,
 746                         chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
 747         if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
 748                 dev_err(hsotg->dev, "can't map align_buf\n");
 749                 chan->align_buf = 0;
 750                 return -EINVAL;
 751         }
 752
 753         chan->align_buf = qh->dw_align_buf_dma;
 754         return 0;
 755 }
 756
 757 /**
 758  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
 759  * channel and initializes the host channel to perform the transactions. The
 760  * host channel is removed from the free list.
 761  *
 762  * @hsotg: The HCD state structure
 763  * @qh:    Transactions from the first QTD for this QH are selected and assigned
 764  *         to a free host channel
 765  */
 766 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
 767 {
 768         struct dwc2_host_chan *chan;
 769         struct dwc2_hcd_urb *urb;
 770         struct dwc2_qtd *qtd;
 771         void *bufptr = NULL;
 772
 773         if (dbg_qh(qh))
 774                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
 775
 776         if (list_empty(&qh->qtd_list)) {
 777                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
 778                 return -ENOMEM;
 779         }
 780
 781         if (list_empty(&hsotg->free_hc_list)) {
 782                 dev_dbg(hsotg->dev, "No free channel to assign\n");
 783                 return -ENOMEM;
 784         }
 785
 786         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
 787                                 hc_list_entry);
 788
 789         /* Remove host channel from free list */
 790         list_del_init(&chan->hc_list_entry);
 791
 792         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 793         urb = qtd->urb;
 794         qh->channel = chan;
 795         qtd->in_process = 1;
 796
 797         /*
 798          * Use usb_pipedevice to determine device address. This address is
 799          * 0 before the SET_ADDRESS command and the correct address afterward.
 800          */
 801         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
 802         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
 803         chan->speed = qh->dev_speed;
 804         chan->max_packet = dwc2_max_packet(qh->maxp);
 805
 806         chan->xfer_started = 0;
 807         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
 808         chan->error_state = (qtd->error_count > 0);
 809         chan->halt_on_queue = 0;
 810         chan->halt_pending = 0;
 811         chan->requests = 0;
 812
 813         /*
 814          * The following values may be modified in the transfer type section
 815          * below. The xfer_len value may be reduced when the transfer is
 816          * started to accommodate the max widths of the XferSize and PktCnt
 817          * fields in the HCTSIZn register.
 818          */
 819
 820         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
 821         if (chan->ep_is_in)
 822                 chan->do_ping = 0;
 823         else
 824                 chan->do_ping = qh->ping_state;
 825
 826         chan->data_pid_start = qh->data_toggle;
 827         chan->multi_count = 1;
 828
 829         if (urb->actual_length > urb->length &&
 830                 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
 831                 urb->actual_length = urb->length;
 832
 833         if (hsotg->core_params->dma_enable > 0) {
 834                 chan->xfer_dma = urb->dma + urb->actual_length;
 835
 836                 /* For non-dword aligned case */
 837                 if (hsotg->core_params->dma_desc_enable <= 0 &&
 838                     (chan->xfer_dma & 0x3))
 839                         bufptr = (u8 *)urb->buf + urb->actual_length;
 840         } else {
 841                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
 842         }
 843
 844         chan->xfer_len = urb->length - urb->actual_length;
 845         chan->xfer_count = 0;
 846
 847         /* Set the split attributes if required */
 848         if (qh->do_split)
 849                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
 850         else
 851                 chan->do_split = 0;
 852
 853         /* Set the transfer attributes */
 854         bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
 855
 856         /* Non DWORD-aligned buffer case */
 857         if (bufptr) {
 858                 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
 859                 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
 860                         dev_err(hsotg->dev,
 861                                 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
 862                                 __func__);
 863                         /* Add channel back to free list */
 864                         chan->align_buf = 0;
 865                         chan->multi_count = 0;
 866                         list_add_tail(&chan->hc_list_entry,
 867                                       &hsotg->free_hc_list);
 868                         qtd->in_process = 0;
 869                         qh->channel = NULL;
 870                         return -ENOMEM;
 871                 }
 872         } else {
 873                 chan->align_buf = 0;
 874         }
 875
 876         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
 877             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 878                 /*
 879                  * This value may be modified when the transfer is started
 880                  * to reflect the actual transfer length
 881                  */
 882                 chan->multi_count = dwc2_hb_mult(qh->maxp);
 883
 884         if (hsotg->core_params->dma_desc_enable > 0)
 885                 chan->desc_list_addr = qh->desc_list_dma;
 886
 887         dwc2_hc_init(hsotg, chan);
 888         chan->qh = qh;
 889
 890         return 0;
 891 }
 892
 893 /**
 894  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
 895  * schedule and assigns them to available host channels. Called from the HCD
 896  * interrupt handler functions.
 897  *
 898  * @hsotg: The HCD state structure
 899  *
 900  * Return: The types of new transactions that were assigned to host channels
 901  */
 902 enum dwc2_transaction_type dwc2_hcd_select_transactions(
 903                 struct dwc2_hsotg *hsotg)
 904 {
 905         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
 906         struct list_head *qh_ptr;
 907         struct dwc2_qh *qh;
 908         int num_channels;
 909
 910 #ifdef DWC2_DEBUG_SOF
 911         dev_vdbg(hsotg->dev, "  Select Transactions\n");
 912 #endif
 913
 914         /* Process entries in the periodic ready list */
 915         qh_ptr = hsotg->periodic_sched_ready.next;
 916         while (qh_ptr != &hsotg->periodic_sched_ready) {
 917                 if (list_empty(&hsotg->free_hc_list))
 918                         break;
 919                 if (hsotg->core_params->uframe_sched > 0) {
 920                         if (hsotg->available_host_channels <= 1)
 921                                 break;
 922                         hsotg->available_host_channels--;
 923                 }
 924                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 925                 if (dwc2_assign_and_init_hc(hsotg, qh))
 926                         break;
 927
 928                 /*
 929                  * Move the QH from the periodic ready schedule to the
 930                  * periodic assigned schedule
 931                  */
 932                 qh_ptr = qh_ptr->next;
 933                 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
 934                 ret_val = DWC2_TRANSACTION_PERIODIC;
 935         }
 936
 937         /*
 938          * Process entries in the inactive portion of the non-periodic
 939          * schedule. Some free host channels may not be used if they are
 940          * reserved for periodic transfers.
 941          */
 942         num_channels = hsotg->core_params->host_channels;
 943         qh_ptr = hsotg->non_periodic_sched_inactive.next;
 944         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
 945                 if (hsotg->core_params->uframe_sched <= 0 &&
 946                     hsotg->non_periodic_channels >= num_channels -
 947                                                 hsotg->periodic_channels)
 948                         break;
 949                 if (list_empty(&hsotg->free_hc_list))
 950                         break;
 951                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 952                 if (hsotg->core_params->uframe_sched > 0) {
 953                         if (hsotg->available_host_channels < 1)
 954                                 break;
 955                         hsotg->available_host_channels--;
 956                 }
 957
 958                 if (dwc2_assign_and_init_hc(hsotg, qh))
 959                         break;
 960
 961                 /*
 962                  * Move the QH from the non-periodic inactive schedule to the
 963                  * non-periodic active schedule
 964                  */
 965                 qh_ptr = qh_ptr->next;
 966                 list_move(&qh->qh_list_entry,
 967                           &hsotg->non_periodic_sched_active);
 968
 969                 if (ret_val == DWC2_TRANSACTION_NONE)
 970                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
 971                 else
 972                         ret_val = DWC2_TRANSACTION_ALL;
 973
 974                 if (hsotg->core_params->uframe_sched <= 0)
 975                         hsotg->non_periodic_channels++;
 976         }
 977
 978         return ret_val;
 979 }
 980
 981 /**
 982  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
 983  * a host channel associated with either a periodic or non-periodic transfer
 984  *
 985  * @hsotg: The HCD state structure
 986  * @chan:  Host channel descriptor associated with either a periodic or
 987  *         non-periodic transfer
 988  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
 989  *                     for periodic transfers or the non-periodic Tx FIFO
 990  *                     for non-periodic transfers
 991  *
 992  * Return: 1 if a request is queued and more requests may be needed to
 993  * complete the transfer, 0 if no more requests are required for this
 994  * transfer, -1 if there is insufficient space in the Tx FIFO
 995  *
 996  * This function assumes that there is space available in the appropriate
 997  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
 998  * it checks whether space is available in the appropriate Tx FIFO.
 999  *
1000  * Must be called with interrupt disabled and spinlock held
1001  */
1002 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1003                                   struct dwc2_host_chan *chan,
1004                                   u16 fifo_dwords_avail)
1005 {
1006         int retval = 0;
1007
1008         if (hsotg->core_params->dma_enable > 0) {
1009                 if (hsotg->core_params->dma_desc_enable > 0) {
1010                         if (!chan->xfer_started ||
1011                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1012                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1013                                 chan->qh->ping_state = 0;
1014                         }
1015                 } else if (!chan->xfer_started) {
1016                         dwc2_hc_start_transfer(hsotg, chan);
1017                         chan->qh->ping_state = 0;
1018                 }
1019         } else if (chan->halt_pending) {
1020                 /* Don't queue a request if the channel has been halted */
1021         } else if (chan->halt_on_queue) {
1022                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1023         } else if (chan->do_ping) {
1024                 if (!chan->xfer_started)
1025                         dwc2_hc_start_transfer(hsotg, chan);
1026         } else if (!chan->ep_is_in ||
1027                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
1028                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1029                         if (!chan->xfer_started) {
1030                                 dwc2_hc_start_transfer(hsotg, chan);
1031                                 retval = 1;
1032                         } else {
1033                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
1034                         }
1035                 } else {
1036                         retval = -1;
1037                 }
1038         } else {
1039                 if (!chan->xfer_started) {
1040                         dwc2_hc_start_transfer(hsotg, chan);
1041                         retval = 1;
1042                 } else {
1043                         retval = dwc2_hc_continue_transfer(hsotg, chan);
1044                 }
1045         }
1046
1047         return retval;
1048 }
1049
1050 /*
1051  * Processes periodic channels for the next frame and queues transactions for
1052  * these channels to the DWC_otg controller. After queueing transactions, the
1053  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1054  * to queue as Periodic Tx FIFO or request queue space becomes available.
1055  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1056  *
1057  * Must be called with interrupt disabled and spinlock held
1058  */
1059 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1060 {
1061         struct list_head *qh_ptr;
1062         struct dwc2_qh *qh;
1063         u32 tx_status;
1064         u32 fspcavail;
1065         u32 gintmsk;
1066         int status;
1067         int no_queue_space = 0;
1068         int no_fifo_space = 0;
1069         u32 qspcavail;
1070
1071         if (dbg_perio())
1072                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1073
1074         tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1075         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1076                     TXSTS_QSPCAVAIL_SHIFT;
1077         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1078                     TXSTS_FSPCAVAIL_SHIFT;
1079
1080         if (dbg_perio()) {
1081                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
1082                          qspcavail);
1083                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
1084                          fspcavail);
1085         }
1086
1087         qh_ptr = hsotg->periodic_sched_assigned.next;
1088         while (qh_ptr != &hsotg->periodic_sched_assigned) {
1089                 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1090                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1091                             TXSTS_QSPCAVAIL_SHIFT;
1092                 if (qspcavail == 0) {
1093                         no_queue_space = 1;
1094                         break;
1095                 }
1096
1097                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1098                 if (!qh->channel) {
1099                         qh_ptr = qh_ptr->next;
1100                         continue;
1101                 }
1102
1103                 /* Make sure EP's TT buffer is clean before queueing qtds */
1104                 if (qh->tt_buffer_dirty) {
1105                         qh_ptr = qh_ptr->next;
1106                         continue;
1107                 }
1108
1109                 /*
1110                  * Set a flag if we're queuing high-bandwidth in slave mode.
1111                  * The flag prevents any halts to get into the request queue in
1112                  * the middle of multiple high-bandwidth packets getting queued.
1113                  */
1114                 if (hsotg->core_params->dma_enable <= 0 &&
1115                                 qh->channel->multi_count > 1)
1116                         hsotg->queuing_high_bandwidth = 1;
1117
1118                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1119                             TXSTS_FSPCAVAIL_SHIFT;
1120                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1121                 if (status < 0) {
1122                         no_fifo_space = 1;
1123                         break;
1124                 }
1125
1126                 /*
1127                  * In Slave mode, stay on the current transfer until there is
1128                  * nothing more to do or the high-bandwidth request count is
1129                  * reached. In DMA mode, only need to queue one request. The
1130                  * controller automatically handles multiple packets for
1131                  * high-bandwidth transfers.
1132                  */
1133                 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1134                     qh->channel->requests == qh->channel->multi_count) {
1135                         qh_ptr = qh_ptr->next;
1136                         /*
1137                          * Move the QH from the periodic assigned schedule to
1138                          * the periodic queued schedule
1139                          */
1140                         list_move(&qh->qh_list_entry,
1141                                   &hsotg->periodic_sched_queued);
1142
1143                         /* done queuing high bandwidth */
1144                         hsotg->queuing_high_bandwidth = 0;
1145                 }
1146         }
1147
1148         if (hsotg->core_params->dma_enable <= 0) {
1149                 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1150                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1151                             TXSTS_QSPCAVAIL_SHIFT;
1152                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1153                             TXSTS_FSPCAVAIL_SHIFT;
1154                 if (dbg_perio()) {
1155                         dev_vdbg(hsotg->dev,
1156                                  "  P Tx Req Queue Space Avail (after queue): %d\n",
1157                                  qspcavail);
1158                         dev_vdbg(hsotg->dev,
1159                                  "  P Tx FIFO Space Avail (after queue): %d\n",
1160                                  fspcavail);
1161                 }
1162
1163                 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1164                     no_queue_space || no_fifo_space) {
1165                         /*
1166                          * May need to queue more transactions as the request
1167                          * queue or Tx FIFO empties. Enable the periodic Tx
1168                          * FIFO empty interrupt. (Always use the half-empty
1169                          * level to ensure that new requests are loaded as
1170                          * soon as possible.)
1171                          */
1172                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1173                         gintmsk |= GINTSTS_PTXFEMP;
1174                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1175                 } else {
1176                         /*
1177                          * Disable the Tx FIFO empty interrupt since there are
1178                          * no more transactions that need to be queued right
1179                          * now. This function is called from interrupt
1180                          * handlers to queue more transactions as transfer
1181                          * states change.
1182                          */
1183                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1184                         gintmsk &= ~GINTSTS_PTXFEMP;
1185                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1186                 }
1187         }
1188 }
1189
1190 /*
1191  * Processes active non-periodic channels and queues transactions for these
1192  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1193  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1194  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1195  * FIFO Empty interrupt is disabled.
1196  *
1197  * Must be called with interrupt disabled and spinlock held
1198  */
1199 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1200 {
1201         struct list_head *orig_qh_ptr;
1202         struct dwc2_qh *qh;
1203         u32 tx_status;
1204         u32 qspcavail;
1205         u32 fspcavail;
1206         u32 gintmsk;
1207         int status;
1208         int no_queue_space = 0;
1209         int no_fifo_space = 0;
1210         int more_to_do = 0;
1211
1212         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1213
1214         tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1215         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1216                     TXSTS_QSPCAVAIL_SHIFT;
1217         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1218                     TXSTS_FSPCAVAIL_SHIFT;
1219         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
1220                  qspcavail);
1221         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
1222                  fspcavail);
1223
1224         /*
1225          * Keep track of the starting point. Skip over the start-of-list
1226          * entry.
1227          */
1228         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1229                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1230         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1231
1232         /*
1233          * Process once through the active list or until no more space is
1234          * available in the request queue or the Tx FIFO
1235          */
1236         do {
1237                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1238                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1239                             TXSTS_QSPCAVAIL_SHIFT;
1240                 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1241                         no_queue_space = 1;
1242                         break;
1243                 }
1244
1245                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1246                                 qh_list_entry);
1247                 if (!qh->channel)
1248                         goto next;
1249
1250                 /* Make sure EP's TT buffer is clean before queueing qtds */
1251                 if (qh->tt_buffer_dirty)
1252                         goto next;
1253
1254                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1255                             TXSTS_FSPCAVAIL_SHIFT;
1256                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1257
1258                 if (status > 0) {
1259                         more_to_do = 1;
1260                 } else if (status < 0) {
1261                         no_fifo_space = 1;
1262                         break;
1263                 }
1264 next:
1265                 /* Advance to next QH, skipping start-of-list entry */
1266                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1267                 if (hsotg->non_periodic_qh_ptr ==
1268                                 &hsotg->non_periodic_sched_active)
1269                         hsotg->non_periodic_qh_ptr =
1270                                         hsotg->non_periodic_qh_ptr->next;
1271         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1272
1273         if (hsotg->core_params->dma_enable <= 0) {
1274                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1275                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1276                             TXSTS_QSPCAVAIL_SHIFT;
1277                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1278                             TXSTS_FSPCAVAIL_SHIFT;
1279                 dev_vdbg(hsotg->dev,
1280                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
1281                          qspcavail);
1282                 dev_vdbg(hsotg->dev,
1283                          "  NP Tx FIFO Space Avail (after queue): %d\n",
1284                          fspcavail);
1285
1286                 if (more_to_do || no_queue_space || no_fifo_space) {
1287                         /*
1288                          * May need to queue more transactions as the request
1289                          * queue or Tx FIFO empties. Enable the non-periodic
1290                          * Tx FIFO empty interrupt. (Always use the half-empty
1291                          * level to ensure that new requests are loaded as
1292                          * soon as possible.)
1293                          */
1294                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1295                         gintmsk |= GINTSTS_NPTXFEMP;
1296                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1297                 } else {
1298                         /*
1299                          * Disable the Tx FIFO empty interrupt since there are
1300                          * no more transactions that need to be queued right
1301                          * now. This function is called from interrupt
1302                          * handlers to queue more transactions as transfer
1303                          * states change.
1304                          */
1305                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1306                         gintmsk &= ~GINTSTS_NPTXFEMP;
1307                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1308                 }
1309         }
1310 }
1311
1312 /**
1313  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1314  * and queues transactions for these channels to the DWC_otg controller. Called
1315  * from the HCD interrupt handler functions.
1316  *
1317  * @hsotg:   The HCD state structure
1318  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1319  *           or both)
1320  *
1321  * Must be called with interrupt disabled and spinlock held
1322  */
1323 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1324                                  enum dwc2_transaction_type tr_type)
1325 {
1326 #ifdef DWC2_DEBUG_SOF
1327         dev_vdbg(hsotg->dev, "Queue Transactions\n");
1328 #endif
1329         /* Process host channels associated with periodic transfers */
1330         if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1331              tr_type == DWC2_TRANSACTION_ALL) &&
1332             !list_empty(&hsotg->periodic_sched_assigned))
1333                 dwc2_process_periodic_channels(hsotg);
1334
1335         /* Process host channels associated with non-periodic transfers */
1336         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1337             tr_type == DWC2_TRANSACTION_ALL) {
1338                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1339                         dwc2_process_non_periodic_channels(hsotg);
1340                 } else {
1341                         /*
1342                          * Ensure NP Tx FIFO empty interrupt is disabled when
1343                          * there are no non-periodic transfers to process
1344                          */
1345                         u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1346
1347                         gintmsk &= ~GINTSTS_NPTXFEMP;
1348                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1349                 }
1350         }
1351 }
1352
1353 static void dwc2_conn_id_status_change(struct work_struct *work)
1354 {
1355         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1356                                                 wf_otg);
1357         u32 count = 0;
1358         u32 gotgctl;
1359         unsigned long flags;
1360
1361         dev_dbg(hsotg->dev, "%s()\n", __func__);
1362
1363         gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1364         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1365         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1366                 !!(gotgctl & GOTGCTL_CONID_B));
1367
1368         /* B-Device connector (Device Mode) */
1369         if (gotgctl & GOTGCTL_CONID_B) {
1370                 /* Wait for switch to device mode */
1371                 dev_dbg(hsotg->dev, "connId B\n");
1372                 while (!dwc2_is_device_mode(hsotg)) {
1373                         dev_info(hsotg->dev,
1374                                  "Waiting for Peripheral Mode, Mode=%s\n",
1375                                  dwc2_is_host_mode(hsotg) ? "Host" :
1376                                  "Peripheral");
1377                         usleep_range(20000, 40000);
1378                         if (++count > 250)
1379                                 break;
1380                 }
1381                 if (count > 250)
1382                         dev_err(hsotg->dev,
1383                                 "Connection id status change timed out\n");
1384                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1385                 dwc2_core_init(hsotg, false, -1);
1386                 dwc2_enable_global_interrupts(hsotg);
1387                 spin_lock_irqsave(&hsotg->lock, flags);
1388                 dwc2_hsotg_core_init_disconnected(hsotg, false);
1389                 spin_unlock_irqrestore(&hsotg->lock, flags);
1390                 dwc2_hsotg_core_connect(hsotg);
1391         } else {
1392                 /* A-Device connector (Host Mode) */
1393                 dev_dbg(hsotg->dev, "connId A\n");
1394                 while (!dwc2_is_host_mode(hsotg)) {
1395                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1396                                  dwc2_is_host_mode(hsotg) ?
1397                                  "Host" : "Peripheral");
1398                         usleep_range(20000, 40000);
1399                         if (++count > 250)
1400                                 break;
1401                 }
1402                 if (count > 250)
1403                         dev_err(hsotg->dev,
1404                                 "Connection id status change timed out\n");
1405
1406                 spin_lock_irqsave(&hsotg->lock, flags);
1407                 dwc2_hsotg_disconnect(hsotg);
1408                 spin_unlock_irqrestore(&hsotg->lock, flags);
1409
1410                 hsotg->op_state = OTG_STATE_A_HOST;
1411                 /* Initialize the Core for Host mode */
1412                 dwc2_core_init(hsotg, false, -1);
1413                 dwc2_enable_global_interrupts(hsotg);
1414                 dwc2_hcd_start(hsotg);
1415         }
1416 }
1417
1418 static void dwc2_wakeup_detected(unsigned long data)
1419 {
1420         struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1421         u32 hprt0;
1422
1423         dev_dbg(hsotg->dev, "%s()\n", __func__);
1424
1425         /*
1426          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1427          * so that OPT tests pass with all PHYs.)
1428          */
1429         hprt0 = dwc2_read_hprt0(hsotg);
1430         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1431         hprt0 &= ~HPRT0_RES;
1432         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1433         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1434                 dwc2_readl(hsotg->regs + HPRT0));
1435
1436         dwc2_hcd_rem_wakeup(hsotg);
1437         hsotg->bus_suspended = 0;
1438
1439         /* Change to L0 state */
1440         hsotg->lx_state = DWC2_L0;
1441 }
1442
1443 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1444 {
1445         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1446
1447         return hcd->self.b_hnp_enable;
1448 }
1449
1450 /* Must NOT be called with interrupt disabled or spinlock held */
1451 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1452 {
1453         unsigned long flags;
1454         u32 hprt0;
1455         u32 pcgctl;
1456         u32 gotgctl;
1457
1458         dev_dbg(hsotg->dev, "%s()\n", __func__);
1459
1460         spin_lock_irqsave(&hsotg->lock, flags);
1461
1462         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1463                 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1464                 gotgctl |= GOTGCTL_HSTSETHNPEN;
1465                 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1466                 hsotg->op_state = OTG_STATE_A_SUSPEND;
1467         }
1468
1469         hprt0 = dwc2_read_hprt0(hsotg);
1470         hprt0 |= HPRT0_SUSP;
1471         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1472
1473         hsotg->bus_suspended = 1;
1474
1475         /*
1476          * If hibernation is supported, Phy clock will be suspended
1477          * after registers are backuped.
1478          */
1479         if (!hsotg->core_params->hibernation) {
1480                 /* Suspend the Phy Clock */
1481                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1482                 pcgctl |= PCGCTL_STOPPCLK;
1483                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1484                 udelay(10);
1485         }
1486
1487         /* For HNP the bus must be suspended for at least 200ms */
1488         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1489                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1490                 pcgctl &= ~PCGCTL_STOPPCLK;
1491                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1492
1493                 spin_unlock_irqrestore(&hsotg->lock, flags);
1494
1495                 usleep_range(200000, 250000);
1496         } else {
1497                 spin_unlock_irqrestore(&hsotg->lock, flags);
1498         }
1499 }
1500
1501 /* Must NOT be called with interrupt disabled or spinlock held */
1502 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
1503 {
1504         unsigned long flags;
1505         u32 hprt0;
1506         u32 pcgctl;
1507
1508         spin_lock_irqsave(&hsotg->lock, flags);
1509
1510         /*
1511          * If hibernation is supported, Phy clock is already resumed
1512          * after registers restore.
1513          */
1514         if (!hsotg->core_params->hibernation) {
1515                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1516                 pcgctl &= ~PCGCTL_STOPPCLK;
1517                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1518                 spin_unlock_irqrestore(&hsotg->lock, flags);
1519                 usleep_range(20000, 40000);
1520                 spin_lock_irqsave(&hsotg->lock, flags);
1521         }
1522
1523         hprt0 = dwc2_read_hprt0(hsotg);
1524         hprt0 |= HPRT0_RES;
1525         hprt0 &= ~HPRT0_SUSP;
1526         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1527         spin_unlock_irqrestore(&hsotg->lock, flags);
1528
1529         msleep(USB_RESUME_TIMEOUT);
1530
1531         spin_lock_irqsave(&hsotg->lock, flags);
1532         hprt0 = dwc2_read_hprt0(hsotg);
1533         hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
1534         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1535         hsotg->bus_suspended = 0;
1536         spin_unlock_irqrestore(&hsotg->lock, flags);
1537 }
1538
1539 /* Handles hub class-specific requests */
1540 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1541                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
1542 {
1543         struct usb_hub_descriptor *hub_desc;
1544         int retval = 0;
1545         u32 hprt0;
1546         u32 port_status;
1547         u32 speed;
1548         u32 pcgctl;
1549
1550         switch (typereq) {
1551         case ClearHubFeature:
1552                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1553
1554                 switch (wvalue) {
1555                 case C_HUB_LOCAL_POWER:
1556                 case C_HUB_OVER_CURRENT:
1557                         /* Nothing required here */
1558                         break;
1559
1560                 default:
1561                         retval = -EINVAL;
1562                         dev_err(hsotg->dev,
1563                                 "ClearHubFeature request %1xh unknown\n",
1564                                 wvalue);
1565                 }
1566                 break;
1567
1568         case ClearPortFeature:
1569                 if (wvalue != USB_PORT_FEAT_L1)
1570                         if (!windex || windex > 1)
1571                                 goto error;
1572                 switch (wvalue) {
1573                 case USB_PORT_FEAT_ENABLE:
1574                         dev_dbg(hsotg->dev,
1575                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1576                         hprt0 = dwc2_read_hprt0(hsotg);
1577                         hprt0 |= HPRT0_ENA;
1578                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1579                         break;
1580
1581                 case USB_PORT_FEAT_SUSPEND:
1582                         dev_dbg(hsotg->dev,
1583                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1584
1585                         if (hsotg->bus_suspended)
1586                                 dwc2_port_resume(hsotg);
1587                         break;
1588
1589                 case USB_PORT_FEAT_POWER:
1590                         dev_dbg(hsotg->dev,
1591                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1592                         hprt0 = dwc2_read_hprt0(hsotg);
1593                         hprt0 &= ~HPRT0_PWR;
1594                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1595                         break;
1596
1597                 case USB_PORT_FEAT_INDICATOR:
1598                         dev_dbg(hsotg->dev,
1599                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1600                         /* Port indicator not supported */
1601                         break;
1602
1603                 case USB_PORT_FEAT_C_CONNECTION:
1604                         /*
1605                          * Clears driver's internal Connect Status Change flag
1606                          */
1607                         dev_dbg(hsotg->dev,
1608                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1609                         hsotg->flags.b.port_connect_status_change = 0;
1610                         break;
1611
1612                 case USB_PORT_FEAT_C_RESET:
1613                         /* Clears driver's internal Port Reset Change flag */
1614                         dev_dbg(hsotg->dev,
1615                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1616                         hsotg->flags.b.port_reset_change = 0;
1617                         break;
1618
1619                 case USB_PORT_FEAT_C_ENABLE:
1620                         /*
1621                          * Clears the driver's internal Port Enable/Disable
1622                          * Change flag
1623                          */
1624                         dev_dbg(hsotg->dev,
1625                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1626                         hsotg->flags.b.port_enable_change = 0;
1627                         break;
1628
1629                 case USB_PORT_FEAT_C_SUSPEND:
1630                         /*
1631                          * Clears the driver's internal Port Suspend Change
1632                          * flag, which is set when resume signaling on the host
1633                          * port is complete
1634                          */
1635                         dev_dbg(hsotg->dev,
1636                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1637                         hsotg->flags.b.port_suspend_change = 0;
1638                         break;
1639
1640                 case USB_PORT_FEAT_C_PORT_L1:
1641                         dev_dbg(hsotg->dev,
1642                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1643                         hsotg->flags.b.port_l1_change = 0;
1644                         break;
1645
1646                 case USB_PORT_FEAT_C_OVER_CURRENT:
1647                         dev_dbg(hsotg->dev,
1648                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1649                         hsotg->flags.b.port_over_current_change = 0;
1650                         break;
1651
1652                 default:
1653                         retval = -EINVAL;
1654                         dev_err(hsotg->dev,
1655                                 "ClearPortFeature request %1xh unknown or unsupported\n",
1656                                 wvalue);
1657                 }
1658                 break;
1659
1660         case GetHubDescriptor:
1661                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1662                 hub_desc = (struct usb_hub_descriptor *)buf;
1663                 hub_desc->bDescLength = 9;
1664                 hub_desc->bDescriptorType = USB_DT_HUB;
1665                 hub_desc->bNbrPorts = 1;
1666                 hub_desc->wHubCharacteristics =
1667                         cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1668                                     HUB_CHAR_INDV_PORT_OCPM);
1669                 hub_desc->bPwrOn2PwrGood = 1;
1670                 hub_desc->bHubContrCurrent = 0;
1671                 hub_desc->u.hs.DeviceRemovable[0] = 0;
1672                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1673                 break;
1674
1675         case GetHubStatus:
1676                 dev_dbg(hsotg->dev, "GetHubStatus\n");
1677                 memset(buf, 0, 4);
1678                 break;
1679
1680         case GetPortStatus:
1681                 dev_vdbg(hsotg->dev,
1682                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1683                          hsotg->flags.d32);
1684                 if (!windex || windex > 1)
1685                         goto error;
1686
1687                 port_status = 0;
1688                 if (hsotg->flags.b.port_connect_status_change)
1689                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1690                 if (hsotg->flags.b.port_enable_change)
1691                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
1692                 if (hsotg->flags.b.port_suspend_change)
1693                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1694                 if (hsotg->flags.b.port_l1_change)
1695                         port_status |= USB_PORT_STAT_C_L1 << 16;
1696                 if (hsotg->flags.b.port_reset_change)
1697                         port_status |= USB_PORT_STAT_C_RESET << 16;
1698                 if (hsotg->flags.b.port_over_current_change) {
1699                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
1700                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1701                 }
1702
1703                 if (!hsotg->flags.b.port_connect_status) {
1704                         /*
1705                          * The port is disconnected, which means the core is
1706                          * either in device mode or it soon will be. Just
1707                          * return 0's for the remainder of the port status
1708                          * since the port register can't be read if the core
1709                          * is in device mode.
1710                          */
1711                         *(__le32 *)buf = cpu_to_le32(port_status);
1712                         break;
1713                 }
1714
1715                 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1716                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
1717
1718                 if (hprt0 & HPRT0_CONNSTS)
1719                         port_status |= USB_PORT_STAT_CONNECTION;
1720                 if (hprt0 & HPRT0_ENA)
1721                         port_status |= USB_PORT_STAT_ENABLE;
1722                 if (hprt0 & HPRT0_SUSP)
1723                         port_status |= USB_PORT_STAT_SUSPEND;
1724                 if (hprt0 & HPRT0_OVRCURRACT)
1725                         port_status |= USB_PORT_STAT_OVERCURRENT;
1726                 if (hprt0 & HPRT0_RST)
1727                         port_status |= USB_PORT_STAT_RESET;
1728                 if (hprt0 & HPRT0_PWR)
1729                         port_status |= USB_PORT_STAT_POWER;
1730
1731                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1732                 if (speed == HPRT0_SPD_HIGH_SPEED)
1733                         port_status |= USB_PORT_STAT_HIGH_SPEED;
1734                 else if (speed == HPRT0_SPD_LOW_SPEED)
1735                         port_status |= USB_PORT_STAT_LOW_SPEED;
1736
1737                 if (hprt0 & HPRT0_TSTCTL_MASK)
1738                         port_status |= USB_PORT_STAT_TEST;
1739                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1740
1741                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1742                 *(__le32 *)buf = cpu_to_le32(port_status);
1743                 break;
1744
1745         case SetHubFeature:
1746                 dev_dbg(hsotg->dev, "SetHubFeature\n");
1747                 /* No HUB features supported */
1748                 break;
1749
1750         case SetPortFeature:
1751                 dev_dbg(hsotg->dev, "SetPortFeature\n");
1752                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1753                         goto error;
1754
1755                 if (!hsotg->flags.b.port_connect_status) {
1756                         /*
1757                          * The port is disconnected, which means the core is
1758                          * either in device mode or it soon will be. Just
1759                          * return without doing anything since the port
1760                          * register can't be written if the core is in device
1761                          * mode.
1762                          */
1763                         break;
1764                 }
1765
1766                 switch (wvalue) {
1767                 case USB_PORT_FEAT_SUSPEND:
1768                         dev_dbg(hsotg->dev,
1769                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1770                         if (windex != hsotg->otg_port)
1771                                 goto error;
1772                         dwc2_port_suspend(hsotg, windex);
1773                         break;
1774
1775                 case USB_PORT_FEAT_POWER:
1776                         dev_dbg(hsotg->dev,
1777                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1778                         hprt0 = dwc2_read_hprt0(hsotg);
1779                         hprt0 |= HPRT0_PWR;
1780                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1781                         break;
1782
1783                 case USB_PORT_FEAT_RESET:
1784                         hprt0 = dwc2_read_hprt0(hsotg);
1785                         dev_dbg(hsotg->dev,
1786                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1787                         pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1788                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1789                         dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1790                         /* ??? Original driver does this */
1791                         dwc2_writel(0, hsotg->regs + PCGCTL);
1792
1793                         hprt0 = dwc2_read_hprt0(hsotg);
1794                         /* Clear suspend bit if resetting from suspend state */
1795                         hprt0 &= ~HPRT0_SUSP;
1796
1797                         /*
1798                          * When B-Host the Port reset bit is set in the Start
1799                          * HCD Callback function, so that the reset is started
1800                          * within 1ms of the HNP success interrupt
1801                          */
1802                         if (!dwc2_hcd_is_b_host(hsotg)) {
1803                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
1804                                 dev_dbg(hsotg->dev,
1805                                         "In host mode, hprt0=%08x\n", hprt0);
1806                                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1807                         }
1808
1809                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1810                         usleep_range(50000, 70000);
1811                         hprt0 &= ~HPRT0_RST;
1812                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1813                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
1814                         break;
1815
1816                 case USB_PORT_FEAT_INDICATOR:
1817                         dev_dbg(hsotg->dev,
1818                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1819                         /* Not supported */
1820                         break;
1821
1822                 case USB_PORT_FEAT_TEST:
1823                         hprt0 = dwc2_read_hprt0(hsotg);
1824                         dev_dbg(hsotg->dev,
1825                                 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1826                         hprt0 &= ~HPRT0_TSTCTL_MASK;
1827                         hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
1828                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1829                         break;
1830
1831                 default:
1832                         retval = -EINVAL;
1833                         dev_err(hsotg->dev,
1834                                 "SetPortFeature %1xh unknown or unsupported\n",
1835                                 wvalue);
1836                         break;
1837                 }
1838                 break;
1839
1840         default:
1841 error:
1842                 retval = -EINVAL;
1843                 dev_dbg(hsotg->dev,
1844                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1845                         typereq, windex, wvalue);
1846                 break;
1847         }
1848
1849         return retval;
1850 }
1851
1852 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1853 {
1854         int retval;
1855
1856         if (port != 1)
1857                 return -EINVAL;
1858
1859         retval = (hsotg->flags.b.port_connect_status_change ||
1860                   hsotg->flags.b.port_reset_change ||
1861                   hsotg->flags.b.port_enable_change ||
1862                   hsotg->flags.b.port_suspend_change ||
1863                   hsotg->flags.b.port_over_current_change);
1864
1865         if (retval) {
1866                 dev_dbg(hsotg->dev,
1867                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1868                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
1869                         hsotg->flags.b.port_connect_status_change);
1870                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
1871                         hsotg->flags.b.port_reset_change);
1872                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
1873                         hsotg->flags.b.port_enable_change);
1874                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
1875                         hsotg->flags.b.port_suspend_change);
1876                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
1877                         hsotg->flags.b.port_over_current_change);
1878         }
1879
1880         return retval;
1881 }
1882
1883 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1884 {
1885         u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
1886
1887 #ifdef DWC2_DEBUG_SOF
1888         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1889                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1890 #endif
1891         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1892 }
1893
1894 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1895 {
1896         return hsotg->op_state == OTG_STATE_B_HOST;
1897 }
1898
1899 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1900                                                int iso_desc_count,
1901                                                gfp_t mem_flags)
1902 {
1903         struct dwc2_hcd_urb *urb;
1904         u32 size = sizeof(*urb) + iso_desc_count *
1905                    sizeof(struct dwc2_hcd_iso_packet_desc);
1906
1907         urb = kzalloc(size, mem_flags);
1908         if (urb)
1909                 urb->packet_count = iso_desc_count;
1910         return urb;
1911 }
1912
1913 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1914                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
1915                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1916 {
1917         if (dbg_perio() ||
1918             ep_type == USB_ENDPOINT_XFER_BULK ||
1919             ep_type == USB_ENDPOINT_XFER_CONTROL)
1920                 dev_vdbg(hsotg->dev,
1921                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1922                          dev_addr, ep_num, ep_dir, ep_type, mps);
1923         urb->pipe_info.dev_addr = dev_addr;
1924         urb->pipe_info.ep_num = ep_num;
1925         urb->pipe_info.pipe_type = ep_type;
1926         urb->pipe_info.pipe_dir = ep_dir;
1927         urb->pipe_info.mps = mps;
1928 }
1929
1930 /*
1931  * NOTE: This function will be removed once the peripheral controller code
1932  * is integrated and the driver is stable
1933  */
1934 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1935 {
1936 #ifdef DEBUG
1937         struct dwc2_host_chan *chan;
1938         struct dwc2_hcd_urb *urb;
1939         struct dwc2_qtd *qtd;
1940         int num_channels;
1941         u32 np_tx_status;
1942         u32 p_tx_status;
1943         int i;
1944
1945         num_channels = hsotg->core_params->host_channels;
1946         dev_dbg(hsotg->dev, "\n");
1947         dev_dbg(hsotg->dev,
1948                 "************************************************************\n");
1949         dev_dbg(hsotg->dev, "HCD State:\n");
1950         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
1951
1952         for (i = 0; i < num_channels; i++) {
1953                 chan = hsotg->hc_ptr_array[i];
1954                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
1955                 dev_dbg(hsotg->dev,
1956                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1957                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
1958                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
1959                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
1960                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
1961                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
1962                         chan->data_pid_start);
1963                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
1964                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
1965                         chan->xfer_started);
1966                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
1967                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
1968                         (unsigned long)chan->xfer_dma);
1969                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
1970                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
1971                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
1972                         chan->halt_on_queue);
1973                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
1974                         chan->halt_pending);
1975                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
1976                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
1977                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
1978                         chan->complete_split);
1979                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
1980                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
1981                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
1982                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
1983                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
1984
1985                 if (chan->xfer_started) {
1986                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1987
1988                         hfnum = dwc2_readl(hsotg->regs + HFNUM);
1989                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1990                         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
1991                         hcint = dwc2_readl(hsotg->regs + HCINT(i));
1992                         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
1993                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
1994                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
1995                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
1996                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
1997                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
1998                 }
1999
2000                 if (!(chan->xfer_started && chan->qh))
2001                         continue;
2002
2003                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
2004                         if (!qtd->in_process)
2005                                 break;
2006                         urb = qtd->urb;
2007                         dev_dbg(hsotg->dev, "    URB Info:\n");
2008                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
2009                                 qtd, urb);
2010                         if (urb) {
2011                                 dev_dbg(hsotg->dev,
2012                                         "      Dev: %d, EP: %d %s\n",
2013                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
2014                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
2015                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
2016                                         "IN" : "OUT");
2017                                 dev_dbg(hsotg->dev,
2018                                         "      Max packet size: %d\n",
2019                                         dwc2_hcd_get_mps(&urb->pipe_info));
2020                                 dev_dbg(hsotg->dev,
2021                                         "      transfer_buffer: %p\n",
2022                                         urb->buf);
2023                                 dev_dbg(hsotg->dev,
2024                                         "      transfer_dma: %08lx\n",
2025                                         (unsigned long)urb->dma);
2026                                 dev_dbg(hsotg->dev,
2027                                         "      transfer_buffer_length: %d\n",
2028                                         urb->length);
2029                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
2030                                         urb->actual_length);
2031                         }
2032                 }
2033         }
2034
2035         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
2036                 hsotg->non_periodic_channels);
2037         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
2038                 hsotg->periodic_channels);
2039         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
2040         np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2041         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
2042                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2043         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
2044                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2045         p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2046         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
2047                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2048         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
2049                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2050         dwc2_hcd_dump_frrem(hsotg);
2051         dwc2_dump_global_registers(hsotg);
2052         dwc2_dump_host_registers(hsotg);
2053         dev_dbg(hsotg->dev,
2054                 "************************************************************\n");
2055         dev_dbg(hsotg->dev, "\n");
2056 #endif
2057 }
2058
2059 /*
2060  * NOTE: This function will be removed once the peripheral controller code
2061  * is integrated and the driver is stable
2062  */
2063 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2064 {
2065 #ifdef DWC2_DUMP_FRREM
2066         dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2067         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2068                 hsotg->frrem_samples, hsotg->frrem_accum,
2069                 hsotg->frrem_samples > 0 ?
2070                 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2071         dev_dbg(hsotg->dev, "\n");
2072         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2073         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2074                 hsotg->hfnum_7_samples,
2075                 hsotg->hfnum_7_frrem_accum,
2076                 hsotg->hfnum_7_samples > 0 ?
2077                 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2078         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2079         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2080                 hsotg->hfnum_0_samples,
2081                 hsotg->hfnum_0_frrem_accum,
2082                 hsotg->hfnum_0_samples > 0 ?
2083                 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2084         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2085         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2086                 hsotg->hfnum_other_samples,
2087                 hsotg->hfnum_other_frrem_accum,
2088                 hsotg->hfnum_other_samples > 0 ?
2089                 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2090                 0);
2091         dev_dbg(hsotg->dev, "\n");
2092         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2093         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2094                 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2095                 hsotg->hfnum_7_samples_a > 0 ?
2096                 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2097         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2098         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2099                 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2100                 hsotg->hfnum_0_samples_a > 0 ?
2101                 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2102         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2103         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2104                 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2105                 hsotg->hfnum_other_samples_a > 0 ?
2106                 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2107                 : 0);
2108         dev_dbg(hsotg->dev, "\n");
2109         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2110         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2111                 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2112                 hsotg->hfnum_7_samples_b > 0 ?
2113                 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2114         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2115         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2116                 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2117                 (hsotg->hfnum_0_samples_b > 0) ?
2118                 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2119         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2120         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2121                 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2122                 (hsotg->hfnum_other_samples_b > 0) ?
2123                 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2124                 : 0);
2125 #endif
2126 }
2127
2128 struct wrapper_priv_data {
2129         struct dwc2_hsotg *hsotg;
2130 };
2131
2132 /* Gets the dwc2_hsotg from a usb_hcd */
2133 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2134 {
2135         struct wrapper_priv_data *p;
2136
2137         p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2138         return p->hsotg;
2139 }
2140
2141 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2142
2143 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2144 {
2145         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2146
2147         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2148         _dwc2_hcd_start(hcd);
2149 }
2150
2151 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2152 {
2153         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2154
2155         hcd->self.is_b_host = 0;
2156 }
2157
2158 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2159                         int *hub_port)
2160 {
2161         struct urb *urb = context;
2162
2163         if (urb->dev->tt)
2164                 *hub_addr = urb->dev->tt->hub->devnum;
2165         else
2166                 *hub_addr = 0;
2167         *hub_port = urb->dev->ttport;
2168 }
2169
2170 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2171 {
2172         struct urb *urb = context;
2173
2174         return urb->dev->speed;
2175 }
2176
2177 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2178                                         struct urb *urb)
2179 {
2180         struct usb_bus *bus = hcd_to_bus(hcd);
2181
2182         if (urb->interval)
2183                 bus->bandwidth_allocated += bw / urb->interval;
2184         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2185                 bus->bandwidth_isoc_reqs++;
2186         else
2187                 bus->bandwidth_int_reqs++;
2188 }
2189
2190 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2191                                     struct urb *urb)
2192 {
2193         struct usb_bus *bus = hcd_to_bus(hcd);
2194
2195         if (urb->interval)
2196                 bus->bandwidth_allocated -= bw / urb->interval;
2197         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2198                 bus->bandwidth_isoc_reqs--;
2199         else
2200                 bus->bandwidth_int_reqs--;
2201 }
2202
2203 /*
2204  * Sets the final status of an URB and returns it to the upper layer. Any
2205  * required cleanup of the URB is performed.
2206  *
2207  * Must be called with interrupt disabled and spinlock held
2208  */
2209 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2210                         int status)
2211 {
2212         struct urb *urb;
2213         int i;
2214
2215         if (!qtd) {
2216                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2217                 return;
2218         }
2219
2220         if (!qtd->urb) {
2221                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2222                 return;
2223         }
2224
2225         urb = qtd->urb->priv;
2226         if (!urb) {
2227                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2228                 return;
2229         }
2230
2231         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2232
2233         if (dbg_urb(urb))
2234                 dev_vdbg(hsotg->dev,
2235                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2236                          __func__, urb, usb_pipedevice(urb->pipe),
2237                          usb_pipeendpoint(urb->pipe),
2238                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2239                          urb->actual_length);
2240
2241
2242         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2243                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2244                 for (i = 0; i < urb->number_of_packets; ++i) {
2245                         urb->iso_frame_desc[i].actual_length =
2246                                 dwc2_hcd_urb_get_iso_desc_actual_length(
2247                                                 qtd->urb, i);
2248                         urb->iso_frame_desc[i].status =
2249                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2250                 }
2251         }
2252
2253         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2254                 for (i = 0; i < urb->number_of_packets; i++)
2255                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2256                                  i, urb->iso_frame_desc[i].status);
2257         }
2258
2259         urb->status = status;
2260         if (!status) {
2261                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2262                     urb->actual_length < urb->transfer_buffer_length)
2263                         urb->status = -EREMOTEIO;
2264         }
2265
2266         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2267             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2268                 struct usb_host_endpoint *ep = urb->ep;
2269
2270                 if (ep)
2271                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2272                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2273                                         urb);
2274         }
2275
2276         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2277         urb->hcpriv = NULL;
2278         kfree(qtd->urb);
2279         qtd->urb = NULL;
2280
2281         spin_unlock(&hsotg->lock);
2282         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2283         spin_lock(&hsotg->lock);
2284 }
2285
2286 /*
2287  * Work queue function for starting the HCD when A-Cable is connected
2288  */
2289 static void dwc2_hcd_start_func(struct work_struct *work)
2290 {
2291         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2292                                                 start_work.work);
2293
2294         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2295         dwc2_host_start(hsotg);
2296 }
2297
2298 /*
2299  * Reset work queue function
2300  */
2301 static void dwc2_hcd_reset_func(struct work_struct *work)
2302 {
2303         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2304                                                 reset_work.work);
2305         u32 hprt0;
2306
2307         dev_dbg(hsotg->dev, "USB RESET function called\n");
2308         hprt0 = dwc2_read_hprt0(hsotg);
2309         hprt0 &= ~HPRT0_RST;
2310         dwc2_writel(hprt0, hsotg->regs + HPRT0);
2311         hsotg->flags.b.port_reset_change = 1;
2312 }
2313
2314 /*
2315  * =========================================================================
2316  *  Linux HC Driver Functions
2317  * =========================================================================
2318  */
2319
2320 /*
2321  * Initializes the DWC_otg controller and its root hub and prepares it for host
2322  * mode operation. Activates the root port. Returns 0 on success and a negative
2323  * error code on failure.
2324  */
2325 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2326 {
2327         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2328         struct usb_bus *bus = hcd_to_bus(hcd);
2329         unsigned long flags;
2330
2331         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2332
2333         spin_lock_irqsave(&hsotg->lock, flags);
2334         hsotg->lx_state = DWC2_L0;
2335         hcd->state = HC_STATE_RUNNING;
2336         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2337
2338         if (dwc2_is_device_mode(hsotg)) {
2339                 spin_unlock_irqrestore(&hsotg->lock, flags);
2340                 return 0;       /* why 0 ?? */
2341         }
2342
2343         dwc2_hcd_reinit(hsotg);
2344
2345         /* Initialize and connect root hub if one is not already attached */
2346         if (bus->root_hub) {
2347                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2348                 /* Inform the HUB driver to resume */
2349                 usb_hcd_resume_root_hub(hcd);
2350         }
2351
2352         spin_unlock_irqrestore(&hsotg->lock, flags);
2353         return 0;
2354 }
2355
2356 /*
2357  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2358  * stopped.
2359  */
2360 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2361 {
2362         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2363         unsigned long flags;
2364
2365         /* Turn off all host-specific interrupts */
2366         dwc2_disable_host_interrupts(hsotg);
2367
2368         /* Wait for interrupt processing to finish */
2369         synchronize_irq(hcd->irq);
2370
2371         spin_lock_irqsave(&hsotg->lock, flags);
2372         /* Ensure hcd is disconnected */
2373         dwc2_hcd_disconnect(hsotg);
2374         dwc2_hcd_stop(hsotg);
2375         hsotg->lx_state = DWC2_L3;
2376         hcd->state = HC_STATE_HALT;
2377         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2378         spin_unlock_irqrestore(&hsotg->lock, flags);
2379
2380         usleep_range(1000, 3000);
2381 }
2382
2383 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
2384 {
2385         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2386         unsigned long flags;
2387         int ret = 0;
2388         u32 hprt0;
2389
2390         spin_lock_irqsave(&hsotg->lock, flags);
2391
2392         if (hsotg->lx_state != DWC2_L0)
2393                 goto unlock;
2394
2395         if (!HCD_HW_ACCESSIBLE(hcd))
2396                 goto unlock;
2397
2398         if (!hsotg->core_params->hibernation)
2399                 goto skip_power_saving;
2400
2401         /*
2402          * Drive USB suspend and disable port Power
2403          * if usb bus is not suspended.
2404          */
2405         if (!hsotg->bus_suspended) {
2406                 hprt0 = dwc2_read_hprt0(hsotg);
2407                 hprt0 |= HPRT0_SUSP;
2408                 hprt0 &= ~HPRT0_PWR;
2409                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2410         }
2411
2412         /* Enter hibernation */
2413         ret = dwc2_enter_hibernation(hsotg);
2414         if (ret) {
2415                 if (ret != -ENOTSUPP)
2416                         dev_err(hsotg->dev,
2417                                 "enter hibernation failed\n");
2418                 goto skip_power_saving;
2419         }
2420
2421         /* Ask phy to be suspended */
2422         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2423                 spin_unlock_irqrestore(&hsotg->lock, flags);
2424                 usb_phy_set_suspend(hsotg->uphy, true);
2425                 spin_lock_irqsave(&hsotg->lock, flags);
2426         }
2427
2428         /* After entering hibernation, hardware is no more accessible */
2429         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2430
2431 skip_power_saving:
2432         hsotg->lx_state = DWC2_L2;
2433 unlock:
2434         spin_unlock_irqrestore(&hsotg->lock, flags);
2435
2436         return ret;
2437 }
2438
2439 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
2440 {
2441         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2442         unsigned long flags;
2443         int ret = 0;
2444
2445         spin_lock_irqsave(&hsotg->lock, flags);
2446
2447         if (hsotg->lx_state != DWC2_L2)
2448                 goto unlock;
2449
2450         if (!hsotg->core_params->hibernation) {
2451                 hsotg->lx_state = DWC2_L0;
2452                 goto unlock;
2453         }
2454
2455         /*
2456          * Set HW accessible bit before powering on the controller
2457          * since an interrupt may rise.
2458          */
2459         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2460
2461         /*
2462          * Enable power if not already done.
2463          * This must not be spinlocked since duration
2464          * of this call is unknown.
2465          */
2466         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2467                 spin_unlock_irqrestore(&hsotg->lock, flags);
2468                 usb_phy_set_suspend(hsotg->uphy, false);
2469                 spin_lock_irqsave(&hsotg->lock, flags);
2470         }
2471
2472         /* Exit hibernation */
2473         ret = dwc2_exit_hibernation(hsotg, true);
2474         if (ret && (ret != -ENOTSUPP))
2475                 dev_err(hsotg->dev, "exit hibernation failed\n");
2476
2477         hsotg->lx_state = DWC2_L0;
2478
2479         spin_unlock_irqrestore(&hsotg->lock, flags);
2480
2481         if (hsotg->bus_suspended) {
2482                 spin_lock_irqsave(&hsotg->lock, flags);
2483                 hsotg->flags.b.port_suspend_change = 1;
2484                 spin_unlock_irqrestore(&hsotg->lock, flags);
2485                 dwc2_port_resume(hsotg);
2486         } else {
2487                 /* Wait for controller to correctly update D+/D- level */
2488                 usleep_range(3000, 5000);
2489
2490                 /*
2491                  * Clear Port Enable and Port Status changes.
2492                  * Enable Port Power.
2493                  */
2494                 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
2495                                 HPRT0_ENACHG, hsotg->regs + HPRT0);
2496                 /* Wait for controller to detect Port Connect */
2497                 usleep_range(5000, 7000);
2498         }
2499
2500         return ret;
2501 unlock:
2502         spin_unlock_irqrestore(&hsotg->lock, flags);
2503
2504         return ret;
2505 }
2506
2507 /* Returns the current frame number */
2508 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2509 {
2510         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2511
2512         return dwc2_hcd_get_frame_number(hsotg);
2513 }
2514
2515 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2516                                char *fn_name)
2517 {
2518 #ifdef VERBOSE_DEBUG
2519         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2520         char *pipetype;
2521         char *speed;
2522
2523         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2524         dev_vdbg(hsotg->dev, "  Device address: %d\n",
2525                  usb_pipedevice(urb->pipe));
2526         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
2527                  usb_pipeendpoint(urb->pipe),
2528                  usb_pipein(urb->pipe) ? "IN" : "OUT");
2529
2530         switch (usb_pipetype(urb->pipe)) {
2531         case PIPE_CONTROL:
2532                 pipetype = "CONTROL";
2533                 break;
2534         case PIPE_BULK:
2535                 pipetype = "BULK";
2536                 break;
2537         case PIPE_INTERRUPT:
2538                 pipetype = "INTERRUPT";
2539                 break;
2540         case PIPE_ISOCHRONOUS:
2541                 pipetype = "ISOCHRONOUS";
2542                 break;
2543         default:
2544                 pipetype = "UNKNOWN";
2545                 break;
2546         }
2547
2548         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
2549                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2550                  "IN" : "OUT");
2551
2552         switch (urb->dev->speed) {
2553         case USB_SPEED_HIGH:
2554                 speed = "HIGH";
2555                 break;
2556         case USB_SPEED_FULL:
2557                 speed = "FULL";
2558                 break;
2559         case USB_SPEED_LOW:
2560                 speed = "LOW";
2561                 break;
2562         default:
2563                 speed = "UNKNOWN";
2564                 break;
2565         }
2566
2567         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
2568         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
2569                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2570         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
2571                  urb->transfer_buffer_length);
2572         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
2573                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2574         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
2575                  urb->setup_packet, (unsigned long)urb->setup_dma);
2576         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
2577
2578         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2579                 int i;
2580
2581                 for (i = 0; i < urb->number_of_packets; i++) {
2582                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
2583                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
2584                                  urb->iso_frame_desc[i].offset,
2585                                  urb->iso_frame_desc[i].length);
2586                 }
2587         }
2588 #endif
2589 }
2590
2591 /*
2592  * Starts processing a USB transfer request specified by a USB Request Block
2593  * (URB). mem_flags indicates the type of memory allocation to use while
2594  * processing this URB.
2595  */
2596 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2597                                  gfp_t mem_flags)
2598 {
2599         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2600         struct usb_host_endpoint *ep = urb->ep;
2601         struct dwc2_hcd_urb *dwc2_urb;
2602         int i;
2603         int retval;
2604         int alloc_bandwidth = 0;
2605         u8 ep_type = 0;
2606         u32 tflags = 0;
2607         void *buf;
2608         unsigned long flags;
2609         struct dwc2_qh *qh;
2610         bool qh_allocated = false;
2611         struct dwc2_qtd *qtd;
2612
2613         if (dbg_urb(urb)) {
2614                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2615                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2616         }
2617
2618         if (ep == NULL)
2619                 return -EINVAL;
2620
2621         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2622             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2623                 spin_lock_irqsave(&hsotg->lock, flags);
2624                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2625                         alloc_bandwidth = 1;
2626                 spin_unlock_irqrestore(&hsotg->lock, flags);
2627         }
2628
2629         switch (usb_pipetype(urb->pipe)) {
2630         case PIPE_CONTROL:
2631                 ep_type = USB_ENDPOINT_XFER_CONTROL;
2632                 break;
2633         case PIPE_ISOCHRONOUS:
2634                 ep_type = USB_ENDPOINT_XFER_ISOC;
2635                 break;
2636         case PIPE_BULK:
2637                 ep_type = USB_ENDPOINT_XFER_BULK;
2638                 break;
2639         case PIPE_INTERRUPT:
2640                 ep_type = USB_ENDPOINT_XFER_INT;
2641                 break;
2642         default:
2643                 dev_warn(hsotg->dev, "Wrong ep type\n");
2644         }
2645
2646         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2647                                       mem_flags);
2648         if (!dwc2_urb)
2649                 return -ENOMEM;
2650
2651         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2652                                   usb_pipeendpoint(urb->pipe), ep_type,
2653                                   usb_pipein(urb->pipe),
2654                                   usb_maxpacket(urb->dev, urb->pipe,
2655                                                 !(usb_pipein(urb->pipe))));
2656
2657         buf = urb->transfer_buffer;
2658
2659         if (hcd->self.uses_dma) {
2660                 if (!buf && (urb->transfer_dma & 3)) {
2661                         dev_err(hsotg->dev,
2662                                 "%s: unaligned transfer with no transfer_buffer",
2663                                 __func__);
2664                         retval = -EINVAL;
2665                         goto fail0;
2666                 }
2667         }
2668
2669         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2670                 tflags |= URB_GIVEBACK_ASAP;
2671         if (urb->transfer_flags & URB_ZERO_PACKET)
2672                 tflags |= URB_SEND_ZERO_PACKET;
2673
2674         dwc2_urb->priv = urb;
2675         dwc2_urb->buf = buf;
2676         dwc2_urb->dma = urb->transfer_dma;
2677         dwc2_urb->length = urb->transfer_buffer_length;
2678         dwc2_urb->setup_packet = urb->setup_packet;
2679         dwc2_urb->setup_dma = urb->setup_dma;
2680         dwc2_urb->flags = tflags;
2681         dwc2_urb->interval = urb->interval;
2682         dwc2_urb->status = -EINPROGRESS;
2683
2684         for (i = 0; i < urb->number_of_packets; ++i)
2685                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2686                                                  urb->iso_frame_desc[i].offset,
2687                                                  urb->iso_frame_desc[i].length);
2688
2689         urb->hcpriv = dwc2_urb;
2690         qh = (struct dwc2_qh *) ep->hcpriv;
2691         /* Create QH for the endpoint if it doesn't exist */
2692         if (!qh) {
2693                 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
2694                 if (!qh) {
2695                         retval = -ENOMEM;
2696                         goto fail0;
2697                 }
2698                 ep->hcpriv = qh;
2699                 qh_allocated = true;
2700         }
2701
2702         qtd = kzalloc(sizeof(*qtd), mem_flags);
2703         if (!qtd) {
2704                 retval = -ENOMEM;
2705                 goto fail1;
2706         }
2707
2708         spin_lock_irqsave(&hsotg->lock, flags);
2709         retval = usb_hcd_link_urb_to_ep(hcd, urb);
2710         if (retval)
2711                 goto fail2;
2712
2713         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
2714         if (retval)
2715                 goto fail3;
2716
2717         if (alloc_bandwidth) {
2718                 dwc2_allocate_bus_bandwidth(hcd,
2719                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2720                                 urb);
2721         }
2722
2723         spin_unlock_irqrestore(&hsotg->lock, flags);
2724
2725         return 0;
2726
2727 fail3:
2728         dwc2_urb->priv = NULL;
2729         usb_hcd_unlink_urb_from_ep(hcd, urb);
2730 fail2:
2731         spin_unlock_irqrestore(&hsotg->lock, flags);
2732         urb->hcpriv = NULL;
2733         kfree(qtd);
2734 fail1:
2735         if (qh_allocated) {
2736                 struct dwc2_qtd *qtd2, *qtd2_tmp;
2737
2738                 ep->hcpriv = NULL;
2739                 dwc2_hcd_qh_unlink(hsotg, qh);
2740                 /* Free each QTD in the QH's QTD list */
2741                 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
2742                                                          qtd_list_entry)
2743                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
2744                 dwc2_hcd_qh_free(hsotg, qh);
2745         }
2746 fail0:
2747         kfree(dwc2_urb);
2748
2749         return retval;
2750 }
2751
2752 /*
2753  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2754  */
2755 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2756                                  int status)
2757 {
2758         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2759         int rc;
2760         unsigned long flags;
2761
2762         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2763         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2764
2765         spin_lock_irqsave(&hsotg->lock, flags);
2766
2767         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2768         if (rc)
2769                 goto out;
2770
2771         if (!urb->hcpriv) {
2772                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2773                 goto out;
2774         }
2775
2776         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2777
2778         usb_hcd_unlink_urb_from_ep(hcd, urb);
2779
2780         kfree(urb->hcpriv);
2781         urb->hcpriv = NULL;
2782
2783         /* Higher layer software sets URB status */
2784         spin_unlock(&hsotg->lock);
2785         usb_hcd_giveback_urb(hcd, urb, status);
2786         spin_lock(&hsotg->lock);
2787
2788         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2789         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
2790 out:
2791         spin_unlock_irqrestore(&hsotg->lock, flags);
2792
2793         return rc;
2794 }
2795
2796 /*
2797  * Frees resources in the DWC_otg controller related to a given endpoint. Also
2798  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2799  * must already be dequeued.
2800  */
2801 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2802                                        struct usb_host_endpoint *ep)
2803 {
2804         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2805
2806         dev_dbg(hsotg->dev,
2807                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2808                 ep->desc.bEndpointAddress, ep->hcpriv);
2809         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2810 }
2811
2812 /*
2813  * Resets endpoint specific parameter values, in current version used to reset
2814  * the data toggle (as a WA). This function can be called from usb_clear_halt
2815  * routine.
2816  */
2817 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2818                                      struct usb_host_endpoint *ep)
2819 {
2820         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2821         unsigned long flags;
2822
2823         dev_dbg(hsotg->dev,
2824                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2825                 ep->desc.bEndpointAddress);
2826
2827         spin_lock_irqsave(&hsotg->lock, flags);
2828         dwc2_hcd_endpoint_reset(hsotg, ep);
2829         spin_unlock_irqrestore(&hsotg->lock, flags);
2830 }
2831
2832 /*
2833  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2834  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2835  * interrupt.
2836  *
2837  * This function is called by the USB core when an interrupt occurs
2838  */
2839 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2840 {
2841         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2842
2843         return dwc2_handle_hcd_intr(hsotg);
2844 }
2845
2846 /*
2847  * Creates Status Change bitmap for the root hub and root port. The bitmap is
2848  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2849  * is the status change indicator for the single root port. Returns 1 if either
2850  * change indicator is 1, otherwise returns 0.
2851  */
2852 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2853 {
2854         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2855
2856         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2857         return buf[0] != 0;
2858 }
2859
2860 /* Handles hub class-specific requests */
2861 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2862                                  u16 windex, char *buf, u16 wlength)
2863 {
2864         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2865                                           wvalue, windex, buf, wlength);
2866         return retval;
2867 }
2868
2869 /* Handles hub TT buffer clear completions */
2870 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2871                                                struct usb_host_endpoint *ep)
2872 {
2873         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2874         struct dwc2_qh *qh;
2875         unsigned long flags;
2876
2877         qh = ep->hcpriv;
2878         if (!qh)
2879                 return;
2880
2881         spin_lock_irqsave(&hsotg->lock, flags);
2882         qh->tt_buffer_dirty = 0;
2883
2884         if (hsotg->flags.b.port_connect_status)
2885                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2886
2887         spin_unlock_irqrestore(&hsotg->lock, flags);
2888 }
2889
2890 static struct hc_driver dwc2_hc_driver = {
2891         .description = "dwc2_hsotg",
2892         .product_desc = "DWC OTG Controller",
2893         .hcd_priv_size = sizeof(struct wrapper_priv_data),
2894
2895         .irq = _dwc2_hcd_irq,
2896         .flags = HCD_MEMORY | HCD_USB2,
2897
2898         .start = _dwc2_hcd_start,
2899         .stop = _dwc2_hcd_stop,
2900         .urb_enqueue = _dwc2_hcd_urb_enqueue,
2901         .urb_dequeue = _dwc2_hcd_urb_dequeue,
2902         .endpoint_disable = _dwc2_hcd_endpoint_disable,
2903         .endpoint_reset = _dwc2_hcd_endpoint_reset,
2904         .get_frame_number = _dwc2_hcd_get_frame_number,
2905
2906         .hub_status_data = _dwc2_hcd_hub_status_data,
2907         .hub_control = _dwc2_hcd_hub_control,
2908         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2909
2910         .bus_suspend = _dwc2_hcd_suspend,
2911         .bus_resume = _dwc2_hcd_resume,
2912 };
2913
2914 /*
2915  * Frees secondary storage associated with the dwc2_hsotg structure contained
2916  * in the struct usb_hcd field
2917  */
2918 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2919 {
2920         u32 ahbcfg;
2921         u32 dctl;
2922         int i;
2923
2924         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2925
2926         /* Free memory for QH/QTD lists */
2927         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2928         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2929         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2930         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2931         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2932         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2933
2934         /* Free memory for the host channels */
2935         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2936                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2937
2938                 if (chan != NULL) {
2939                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2940                                 i, chan);
2941                         hsotg->hc_ptr_array[i] = NULL;
2942                         kfree(chan);
2943                 }
2944         }
2945
2946         if (hsotg->core_params->dma_enable > 0) {
2947                 if (hsotg->status_buf) {
2948                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2949                                           hsotg->status_buf,
2950                                           hsotg->status_buf_dma);
2951                         hsotg->status_buf = NULL;
2952                 }
2953         } else {
2954                 kfree(hsotg->status_buf);
2955                 hsotg->status_buf = NULL;
2956         }
2957
2958         ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
2959
2960         /* Disable all interrupts */
2961         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2962         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
2963         dwc2_writel(0, hsotg->regs + GINTMSK);
2964
2965         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2966                 dctl = dwc2_readl(hsotg->regs + DCTL);
2967                 dctl |= DCTL_SFTDISCON;
2968                 dwc2_writel(dctl, hsotg->regs + DCTL);
2969         }
2970
2971         if (hsotg->wq_otg) {
2972                 if (!cancel_work_sync(&hsotg->wf_otg))
2973                         flush_workqueue(hsotg->wq_otg);
2974                 destroy_workqueue(hsotg->wq_otg);
2975         }
2976
2977         del_timer(&hsotg->wkp_timer);
2978 }
2979
2980 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2981 {
2982         /* Turn off all host-specific interrupts */
2983         dwc2_disable_host_interrupts(hsotg);
2984
2985         dwc2_hcd_free(hsotg);
2986 }
2987
2988 /*
2989  * Initializes the HCD. This function allocates memory for and initializes the
2990  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2991  * USB bus with the core and calls the hc_driver->start() function. It returns
2992  * a negative error on failure.
2993  */
2994 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
2995 {
2996         struct usb_hcd *hcd;
2997         struct dwc2_host_chan *channel;
2998         u32 hcfg;
2999         int i, num_channels;
3000         int retval;
3001
3002         if (usb_disabled())
3003                 return -ENODEV;
3004
3005         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
3006
3007         retval = -ENOMEM;
3008
3009         hcfg = dwc2_readl(hsotg->regs + HCFG);
3010         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
3011
3012 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3013         hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
3014                                          FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3015         if (!hsotg->frame_num_array)
3016                 goto error1;
3017         hsotg->last_frame_num_array = kzalloc(
3018                         sizeof(*hsotg->last_frame_num_array) *
3019                         FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3020         if (!hsotg->last_frame_num_array)
3021                 goto error1;
3022         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
3023 #endif
3024
3025         /* Check if the bus driver or platform code has setup a dma_mask */
3026         if (hsotg->core_params->dma_enable > 0 &&
3027             hsotg->dev->dma_mask == NULL) {
3028                 dev_warn(hsotg->dev,
3029                          "dma_mask not set, disabling DMA\n");
3030                 hsotg->core_params->dma_enable = 0;
3031                 hsotg->core_params->dma_desc_enable = 0;
3032         }
3033
3034         /* Set device flags indicating whether the HCD supports DMA */
3035         if (hsotg->core_params->dma_enable > 0) {
3036                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3037                         dev_warn(hsotg->dev, "can't set DMA mask\n");
3038                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3039                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
3040         }
3041
3042         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
3043         if (!hcd)
3044                 goto error1;
3045
3046         if (hsotg->core_params->dma_enable <= 0)
3047                 hcd->self.uses_dma = 0;
3048
3049         hcd->has_tt = 1;
3050
3051         ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
3052         hsotg->priv = hcd;
3053
3054         /*
3055          * Disable the global interrupt until all the interrupt handlers are
3056          * installed
3057          */
3058         dwc2_disable_global_interrupts(hsotg);
3059
3060         /* Initialize the DWC_otg core, and select the Phy type */
3061         retval = dwc2_core_init(hsotg, true, irq);
3062         if (retval)
3063                 goto error2;
3064
3065         /* Create new workqueue and init work */
3066         retval = -ENOMEM;
3067         hsotg->wq_otg = create_singlethread_workqueue("dwc2");
3068         if (!hsotg->wq_otg) {
3069                 dev_err(hsotg->dev, "Failed to create workqueue\n");
3070                 goto error2;
3071         }
3072         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
3073
3074         setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
3075                     (unsigned long)hsotg);
3076
3077         /* Initialize the non-periodic schedule */
3078         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
3079         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
3080
3081         /* Initialize the periodic schedule */
3082         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
3083         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
3084         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
3085         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
3086
3087         /*
3088          * Create a host channel descriptor for each host channel implemented
3089          * in the controller. Initialize the channel descriptor array.
3090          */
3091         INIT_LIST_HEAD(&hsotg->free_hc_list);
3092         num_channels = hsotg->core_params->host_channels;
3093         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
3094
3095         for (i = 0; i < num_channels; i++) {
3096                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3097                 if (channel == NULL)
3098                         goto error3;
3099                 channel->hc_num = i;
3100                 hsotg->hc_ptr_array[i] = channel;
3101         }
3102
3103         if (hsotg->core_params->uframe_sched > 0)
3104                 dwc2_hcd_init_usecs(hsotg);
3105
3106         /* Initialize hsotg start work */
3107         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
3108
3109         /* Initialize port reset work */
3110         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
3111
3112         /*
3113          * Allocate space for storing data on status transactions. Normally no
3114          * data is sent, but this space acts as a bit bucket. This must be
3115          * done after usb_add_hcd since that function allocates the DMA buffer
3116          * pool.
3117          */
3118         if (hsotg->core_params->dma_enable > 0)
3119                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
3120                                         DWC2_HCD_STATUS_BUF_SIZE,
3121                                         &hsotg->status_buf_dma, GFP_KERNEL);
3122         else
3123                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
3124                                           GFP_KERNEL);
3125
3126         if (!hsotg->status_buf)
3127                 goto error3;
3128
3129         hsotg->otg_port = 1;
3130         hsotg->frame_list = NULL;
3131         hsotg->frame_list_dma = 0;
3132         hsotg->periodic_qh_count = 0;
3133
3134         /* Initiate lx_state to L3 disconnected state */
3135         hsotg->lx_state = DWC2_L3;
3136
3137         hcd->self.otg_port = hsotg->otg_port;
3138
3139         /* Don't support SG list at this point */
3140         hcd->self.sg_tablesize = 0;
3141
3142         if (!IS_ERR_OR_NULL(hsotg->uphy))
3143                 otg_set_host(hsotg->uphy->otg, &hcd->self);
3144
3145         /*
3146          * Finish generic HCD initialization and start the HCD. This function
3147          * allocates the DMA buffer pool, registers the USB bus, requests the
3148          * IRQ line, and calls hcd_start method.
3149          */
3150         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
3151         if (retval < 0)
3152                 goto error3;
3153
3154         device_wakeup_enable(hcd->self.controller);
3155
3156         dwc2_hcd_dump_state(hsotg);
3157
3158         dwc2_enable_global_interrupts(hsotg);
3159
3160         return 0;
3161
3162 error3:
3163         dwc2_hcd_release(hsotg);
3164 error2:
3165         usb_put_hcd(hcd);
3166 error1:
3167
3168 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3169         kfree(hsotg->last_frame_num_array);
3170         kfree(hsotg->frame_num_array);
3171 #endif
3172
3173         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
3174         return retval;
3175 }
3176
3177 /*
3178  * Removes the HCD.
3179  * Frees memory and resources associated with the HCD and deregisters the bus.
3180  */
3181 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
3182 {
3183         struct usb_hcd *hcd;
3184
3185         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
3186
3187         hcd = dwc2_hsotg_to_hcd(hsotg);
3188         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
3189
3190         if (!hcd) {
3191                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
3192                         __func__);
3193                 return;
3194         }
3195
3196         if (!IS_ERR_OR_NULL(hsotg->uphy))
3197                 otg_set_host(hsotg->uphy->otg, NULL);
3198
3199         usb_remove_hcd(hcd);
3200         hsotg->priv = NULL;
3201         dwc2_hcd_release(hsotg);
3202         usb_put_hcd(hcd);
3203
3204 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3205         kfree(hsotg->last_frame_num_array);
3206         kfree(hsotg->frame_num_array);
3207 #endif
3208 }