2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_platform.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/phy.h>
37 /* conversion functions */
38 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
40 return container_of(req, struct dwc2_hsotg_req, req);
43 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
48 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
50 return container_of(gadget, struct dwc2_hsotg, gadget);
53 static inline void __orr32(void __iomem *ptr, u32 val)
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
58 static inline void __bic32(void __iomem *ptr, u32 val)
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
63 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
67 return hsotg->eps_in[ep_index];
69 return hsotg->eps_out[ep_index];
72 /* forward declaration of functions */
73 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
79 * Return true if we're using DMA.
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
92 * g_using_dma is set depending on dts flag.
94 static inline bool using_dma(struct dwc2_hsotg *hsotg)
96 return hsotg->params.g_dma;
100 * using_desc_dma - return the descriptor DMA status of the driver.
101 * @hsotg: The driver state.
103 * Return true if we're using descriptor DMA.
105 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
107 return hsotg->params.g_dma_desc;
111 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
112 * @hs_ep: The endpoint
113 * @increment: The value to increment by
115 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
116 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
118 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
120 hs_ep->target_frame += hs_ep->interval;
121 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
122 hs_ep->frame_overrun = 1;
123 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
125 hs_ep->frame_overrun = 0;
130 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
131 * @hsotg: The device state
132 * @ints: A bitmask of the interrupts to enable
134 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
136 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
139 new_gsintmsk = gsintmsk | ints;
141 if (new_gsintmsk != gsintmsk) {
142 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
143 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
148 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
149 * @hsotg: The device state
150 * @ints: A bitmask of the interrupts to enable
152 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
154 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
157 new_gsintmsk = gsintmsk & ~ints;
159 if (new_gsintmsk != gsintmsk)
160 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
164 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
165 * @hsotg: The device state
166 * @ep: The endpoint index
167 * @dir_in: True if direction is in.
168 * @en: The enable value, true to enable
170 * Set or clear the mask for an individual endpoint's interrupt
173 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
174 unsigned int ep, unsigned int dir_in,
184 local_irq_save(flags);
185 daint = dwc2_readl(hsotg->regs + DAINTMSK);
190 dwc2_writel(daint, hsotg->regs + DAINTMSK);
191 local_irq_restore(flags);
195 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
197 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
199 if (hsotg->hw_params.en_multiple_tx_fifo)
200 /* In dedicated FIFO mode we need count of IN EPs */
201 return (dwc2_readl(hsotg->regs + GHWCFG4) &
202 GHWCFG4_NUM_IN_EPS_MASK) >> GHWCFG4_NUM_IN_EPS_SHIFT;
204 /* In shared FIFO mode we need count of Periodic IN EPs */
205 return hsotg->hw_params.num_dev_perio_in_ep;
209 * dwc2_hsotg_ep_info_size - return Endpoint Info Control block size in DWORDs
211 static int dwc2_hsotg_ep_info_size(struct dwc2_hsotg *hsotg)
218 * Don't need additional space for ep info control registers in
221 if (!using_dma(hsotg)) {
222 dev_dbg(hsotg->dev, "Buffer DMA ep info size 0\n");
227 * Buffer DMA mode - 1 location per endpoit
228 * Descriptor DMA mode - 4 locations per endpoint
230 ep_dirs = hsotg->hw_params.dev_ep_dirs;
232 for (i = 0; i <= hsotg->hw_params.num_dev_ep; i++) {
233 val += ep_dirs & 3 ? 1 : 2;
237 if (using_desc_dma(hsotg))
244 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
245 * device mode TX FIFOs
247 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
254 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
255 hsotg->params.g_np_tx_fifo_size);
257 /* Get Endpoint Info Control block size in DWORDs. */
258 ep_info_size = dwc2_hsotg_ep_info_size(hsotg);
259 tx_addr_max = hsotg->hw_params.total_fifo_size - ep_info_size;
261 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
262 if (tx_addr_max <= addr)
265 return tx_addr_max - addr;
269 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
272 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
277 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
279 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
282 return tx_fifo_depth;
284 return tx_fifo_depth / tx_fifo_count;
288 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
289 * @hsotg: The device instance.
291 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
297 u32 *txfsz = hsotg->params.g_tx_fifo_size;
299 /* Reset fifo map if not correctly cleared during previous session */
300 WARN_ON(hsotg->fifo_map);
303 /* set RX/NPTX FIFO sizes */
304 dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
305 dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) |
306 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
307 hsotg->regs + GNPTXFSIZ);
310 * arange all the rest of the TX FIFOs, as some versions of this
311 * block have overlapping default addresses. This also ensures
312 * that if the settings have been changed, then they are set to
316 /* start at the end of the GNPTXFSIZ, rounded up */
317 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
320 * Configure fifos sizes from provided configuration and assign
321 * them to endpoints dynamically according to maxpacket size value of
324 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
328 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
329 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
330 "insufficient fifo memory");
333 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
334 val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
337 dwc2_writel(hsotg->hw_params.total_fifo_size |
338 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
339 hsotg->regs + GDFIFOCFG);
341 * according to p428 of the design guide, we need to ensure that
342 * all fifos are flushed before continuing
345 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
346 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
348 /* wait until the fifos are both flushed */
351 val = dwc2_readl(hsotg->regs + GRSTCTL);
353 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
356 if (--timeout == 0) {
358 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
366 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
370 * @ep: USB endpoint to allocate request for.
371 * @flags: Allocation flags
373 * Allocate a new USB request structure appropriate for the specified endpoint
375 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
378 struct dwc2_hsotg_req *req;
380 req = kzalloc(sizeof(*req), flags);
384 INIT_LIST_HEAD(&req->queue);
390 * is_ep_periodic - return true if the endpoint is in periodic mode.
391 * @hs_ep: The endpoint to query.
393 * Returns true if the endpoint is in periodic mode, meaning it is being
394 * used for an Interrupt or ISO transfer.
396 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
398 return hs_ep->periodic;
402 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
403 * @hsotg: The device state.
404 * @hs_ep: The endpoint for the request
405 * @hs_req: The request being processed.
407 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
408 * of a request to ensure the buffer is ready for access by the caller.
410 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
411 struct dwc2_hsotg_ep *hs_ep,
412 struct dwc2_hsotg_req *hs_req)
414 struct usb_request *req = &hs_req->req;
416 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
420 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
421 * for Control endpoint
422 * @hsotg: The device state.
424 * This function will allocate 4 descriptor chains for EP 0: 2 for
425 * Setup stage, per one for IN and OUT data/status transactions.
427 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
429 hsotg->setup_desc[0] =
430 dmam_alloc_coherent(hsotg->dev,
431 sizeof(struct dwc2_dma_desc),
432 &hsotg->setup_desc_dma[0],
434 if (!hsotg->setup_desc[0])
437 hsotg->setup_desc[1] =
438 dmam_alloc_coherent(hsotg->dev,
439 sizeof(struct dwc2_dma_desc),
440 &hsotg->setup_desc_dma[1],
442 if (!hsotg->setup_desc[1])
445 hsotg->ctrl_in_desc =
446 dmam_alloc_coherent(hsotg->dev,
447 sizeof(struct dwc2_dma_desc),
448 &hsotg->ctrl_in_desc_dma,
450 if (!hsotg->ctrl_in_desc)
453 hsotg->ctrl_out_desc =
454 dmam_alloc_coherent(hsotg->dev,
455 sizeof(struct dwc2_dma_desc),
456 &hsotg->ctrl_out_desc_dma,
458 if (!hsotg->ctrl_out_desc)
468 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
469 * @hsotg: The controller state.
470 * @hs_ep: The endpoint we're going to write for.
471 * @hs_req: The request to write data for.
473 * This is called when the TxFIFO has some space in it to hold a new
474 * transmission and we have something to give it. The actual setup of
475 * the data size is done elsewhere, so all we have to do is to actually
478 * The return value is zero if there is more space (or nothing was done)
479 * otherwise -ENOSPC is returned if the FIFO space was used up.
481 * This routine is only needed for PIO
483 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
484 struct dwc2_hsotg_ep *hs_ep,
485 struct dwc2_hsotg_req *hs_req)
487 bool periodic = is_ep_periodic(hs_ep);
488 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
489 int buf_pos = hs_req->req.actual;
490 int to_write = hs_ep->size_loaded;
496 to_write -= (buf_pos - hs_ep->last_load);
498 /* if there's nothing to write, get out early */
502 if (periodic && !hsotg->dedicated_fifos) {
503 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
508 * work out how much data was loaded so we can calculate
509 * how much data is left in the fifo.
512 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
515 * if shared fifo, we cannot write anything until the
516 * previous data has been completely sent.
518 if (hs_ep->fifo_load != 0) {
519 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
523 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
525 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
527 /* how much of the data has moved */
528 size_done = hs_ep->size_loaded - size_left;
530 /* how much data is left in the fifo */
531 can_write = hs_ep->fifo_load - size_done;
532 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
533 __func__, can_write);
535 can_write = hs_ep->fifo_size - can_write;
536 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
537 __func__, can_write);
539 if (can_write <= 0) {
540 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
543 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
544 can_write = dwc2_readl(hsotg->regs +
545 DTXFSTS(hs_ep->fifo_index));
550 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
552 "%s: no queue slots available (0x%08x)\n",
555 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
559 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
560 can_write *= 4; /* fifo size is in 32bit quantities. */
563 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
565 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
566 __func__, gnptxsts, can_write, to_write, max_transfer);
569 * limit to 512 bytes of data, it seems at least on the non-periodic
570 * FIFO, requests of >512 cause the endpoint to get stuck with a
571 * fragment of the end of the transfer in it.
573 if (can_write > 512 && !periodic)
577 * limit the write to one max-packet size worth of data, but allow
578 * the transfer to return that it did not run out of fifo space
581 if (to_write > max_transfer) {
582 to_write = max_transfer;
584 /* it's needed only when we do not use dedicated fifos */
585 if (!hsotg->dedicated_fifos)
586 dwc2_hsotg_en_gsint(hsotg,
587 periodic ? GINTSTS_PTXFEMP :
591 /* see if we can write data */
593 if (to_write > can_write) {
594 to_write = can_write;
595 pkt_round = to_write % max_transfer;
598 * Round the write down to an
599 * exact number of packets.
601 * Note, we do not currently check to see if we can ever
602 * write a full packet or not to the FIFO.
606 to_write -= pkt_round;
609 * enable correct FIFO interrupt to alert us when there
613 /* it's needed only when we do not use dedicated fifos */
614 if (!hsotg->dedicated_fifos)
615 dwc2_hsotg_en_gsint(hsotg,
616 periodic ? GINTSTS_PTXFEMP :
620 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
621 to_write, hs_req->req.length, can_write, buf_pos);
626 hs_req->req.actual = buf_pos + to_write;
627 hs_ep->total_data += to_write;
630 hs_ep->fifo_load += to_write;
632 to_write = DIV_ROUND_UP(to_write, 4);
633 data = hs_req->req.buf + buf_pos;
635 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
637 return (to_write >= can_write) ? -ENOSPC : 0;
641 * get_ep_limit - get the maximum data legnth for this endpoint
642 * @hs_ep: The endpoint
644 * Return the maximum data that can be queued in one go on a given endpoint
645 * so that transfers that are too long can be split.
647 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
649 int index = hs_ep->index;
650 unsigned int maxsize;
654 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
655 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
659 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
664 /* we made the constant loading easier above by using +1 */
669 * constrain by packet count if maxpkts*pktsize is greater
670 * than the length register size.
673 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
674 maxsize = maxpkt * hs_ep->ep.maxpacket;
680 * dwc2_hsotg_read_frameno - read current frame number
681 * @hsotg: The device instance
683 * Return the current frame number
685 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
689 dsts = dwc2_readl(hsotg->regs + DSTS);
690 dsts &= DSTS_SOFFN_MASK;
691 dsts >>= DSTS_SOFFN_SHIFT;
697 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
698 * DMA descriptor chain prepared for specific endpoint
699 * @hs_ep: The endpoint
701 * Return the maximum data that can be queued in one go on a given endpoint
702 * depending on its descriptor chain capacity so that transfers that
703 * are too long can be split.
705 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
707 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
708 int is_isoc = hs_ep->isochronous;
709 unsigned int maxsize;
710 u32 mps = hs_ep->ep.maxpacket;
711 int dir_in = hs_ep->dir_in;
714 maxsize = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
715 DEV_DMA_ISOC_RX_NBYTES_LIMIT;
717 maxsize = DEV_DMA_NBYTES_LIMIT;
719 /* Above size of one descriptor was chosen, multiple it */
720 maxsize *= MAX_DMA_DESC_NUM_GENERIC;
722 /* Interrupt OUT EP with mps not multiple of 4 */
724 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
725 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
731 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
732 * @hs_ep: The endpoint
733 * @mask: RX/TX bytes mask to be defined
735 * Returns maximum data payload for one descriptor after analyzing endpoint
737 * DMA descriptor transfer bytes limit depends on EP type:
739 * Isochronous - descriptor rx/tx bytes bitfield limit,
740 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
741 * have concatenations from various descriptors within one packet.
742 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
743 * to a single descriptor.
745 * Selects corresponding mask for RX/TX bytes as well.
747 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
749 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
750 u32 mps = hs_ep->ep.maxpacket;
751 int dir_in = hs_ep->dir_in;
754 if (!hs_ep->index && !dir_in) {
756 *mask = DEV_DMA_NBYTES_MASK;
757 } else if (hs_ep->isochronous) {
759 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
760 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
762 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
763 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
766 desc_size = DEV_DMA_NBYTES_LIMIT;
767 *mask = DEV_DMA_NBYTES_MASK;
769 /* Round down desc_size to be mps multiple */
770 desc_size -= desc_size % mps;
773 /* Interrupt OUT EP with mps not multiple of 4 */
775 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
777 *mask = DEV_DMA_NBYTES_MASK;
784 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
785 * @hs_ep: The endpoint
786 * @dma_buff: DMA address to use
787 * @len: Length of the transfer
789 * This function will iterate over descriptor chain and fill its entries
790 * with corresponding information based on transfer data.
792 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
796 struct dwc2_hsotg *hsotg = hs_ep->parent;
797 int dir_in = hs_ep->dir_in;
798 struct dwc2_dma_desc *desc = hs_ep->desc_list;
799 u32 mps = hs_ep->ep.maxpacket;
805 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
807 hs_ep->desc_count = (len / maxsize) +
808 ((len % maxsize) ? 1 : 0);
810 hs_ep->desc_count = 1;
812 for (i = 0; i < hs_ep->desc_count; ++i) {
814 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
815 << DEV_DMA_BUFF_STS_SHIFT);
818 if (!hs_ep->index && !dir_in)
819 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
821 desc->status |= (maxsize <<
822 DEV_DMA_NBYTES_SHIFT & mask);
823 desc->buf = dma_buff + offset;
828 desc->status |= (DEV_DMA_L | DEV_DMA_IOC);
831 desc->status |= (len % mps) ? DEV_DMA_SHORT :
832 ((hs_ep->send_zlp) ? DEV_DMA_SHORT : 0);
834 dev_err(hsotg->dev, "wrong len %d\n", len);
837 len << DEV_DMA_NBYTES_SHIFT & mask;
838 desc->buf = dma_buff + offset;
841 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
842 desc->status |= (DEV_DMA_BUFF_STS_HREADY
843 << DEV_DMA_BUFF_STS_SHIFT);
849 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
850 * @hs_ep: The isochronous endpoint.
851 * @dma_buff: usb requests dma buffer.
852 * @len: usb request transfer length.
854 * Finds out index of first free entry either in the bottom or up half of
855 * descriptor chain depend on which is under SW control and not processed
856 * by HW. Then fills that descriptor with the data of the arrived usb request,
857 * frame info, sets Last and IOC bits increments next_desc. If filled
858 * descriptor is not the first one, removes L bit from the previous descriptor
861 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
862 dma_addr_t dma_buff, unsigned int len)
864 struct dwc2_dma_desc *desc;
865 struct dwc2_hsotg *hsotg = hs_ep->parent;
871 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
873 dev_err(hsotg->dev, "wrong len %d\n", len);
878 * If SW has already filled half of chain, then return and wait for
879 * the other chain to be processed by HW.
881 if (hs_ep->next_desc == MAX_DMA_DESC_NUM_GENERIC / 2)
884 /* Increment frame number by interval for IN */
886 dwc2_gadget_incr_frame_num(hs_ep);
888 index = (MAX_DMA_DESC_NUM_GENERIC / 2) * hs_ep->isoc_chain_num +
891 /* Sanity check of calculated index */
892 if ((hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC) ||
893 (!hs_ep->isoc_chain_num && index > MAX_DMA_DESC_NUM_GENERIC / 2)) {
894 dev_err(hsotg->dev, "wrong index %d for iso chain\n", index);
898 desc = &hs_ep->desc_list[index];
900 /* Clear L bit of previous desc if more than one entries in the chain */
901 if (hs_ep->next_desc)
902 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
904 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
905 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
908 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
910 desc->buf = dma_buff;
911 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
912 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
916 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
919 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
920 DEV_DMA_ISOC_PID_MASK) |
921 ((len % hs_ep->ep.maxpacket) ?
923 ((hs_ep->target_frame <<
924 DEV_DMA_ISOC_FRNUM_SHIFT) &
925 DEV_DMA_ISOC_FRNUM_MASK);
928 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
929 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
931 /* Update index of last configured entry in the chain */
938 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
939 * @hs_ep: The isochronous endpoint.
941 * Prepare first descriptor chain for isochronous endpoints. Afterwards
942 * write DMA address to HW and enable the endpoint.
944 * Switch between descriptor chains via isoc_chain_num to give SW opportunity
945 * to prepare second descriptor chain while first one is being processed by HW.
947 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
949 struct dwc2_hsotg *hsotg = hs_ep->parent;
950 struct dwc2_hsotg_req *hs_req, *treq;
951 int index = hs_ep->index;
957 if (list_empty(&hs_ep->queue)) {
958 hs_ep->target_frame = TARGET_FRAME_INITIAL;
959 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
963 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
964 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
967 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
972 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
973 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
975 /* write descriptor chain address to control register */
976 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
978 ctrl = dwc2_readl(hsotg->regs + depctl);
979 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
980 dwc2_writel(ctrl, hsotg->regs + depctl);
982 /* Switch ISOC descriptor chain number being processed by SW*/
983 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
984 hs_ep->next_desc = 0;
988 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
989 * @hsotg: The controller state.
990 * @hs_ep: The endpoint to process a request for
991 * @hs_req: The request to start.
992 * @continuing: True if we are doing more for the current request.
994 * Start the given request running by setting the endpoint registers
995 * appropriately, and writing any data to the FIFOs.
997 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
998 struct dwc2_hsotg_ep *hs_ep,
999 struct dwc2_hsotg_req *hs_req,
1002 struct usb_request *ureq = &hs_req->req;
1003 int index = hs_ep->index;
1004 int dir_in = hs_ep->dir_in;
1009 unsigned int length;
1010 unsigned int packets;
1011 unsigned int maxreq;
1012 unsigned int dma_reg;
1015 if (hs_ep->req && !continuing) {
1016 dev_err(hsotg->dev, "%s: active request\n", __func__);
1019 } else if (hs_ep->req != hs_req && continuing) {
1021 "%s: continue different req\n", __func__);
1027 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1028 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1029 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1031 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1032 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
1033 hs_ep->dir_in ? "in" : "out");
1035 /* If endpoint is stalled, we will restart request later */
1036 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
1038 if (index && ctrl & DXEPCTL_STALL) {
1039 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1043 length = ureq->length - ureq->actual;
1044 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1045 ureq->length, ureq->actual);
1047 if (!using_desc_dma(hsotg))
1048 maxreq = get_ep_limit(hs_ep);
1050 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1052 if (length > maxreq) {
1053 int round = maxreq % hs_ep->ep.maxpacket;
1055 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1056 __func__, length, maxreq, round);
1058 /* round down to multiple of packets */
1066 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1068 packets = 1; /* send one packet if length is zero. */
1070 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1071 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
1075 if (dir_in && index != 0)
1076 if (hs_ep->isochronous)
1077 epsize = DXEPTSIZ_MC(packets);
1079 epsize = DXEPTSIZ_MC(1);
1084 * zero length packet should be programmed on its own and should not
1085 * be counted in DIEPTSIZ.PktCnt with other packets.
1087 if (dir_in && ureq->zero && !continuing) {
1088 /* Test if zlp is actually required. */
1089 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1090 !(ureq->length % hs_ep->ep.maxpacket))
1091 hs_ep->send_zlp = 1;
1094 epsize |= DXEPTSIZ_PKTCNT(packets);
1095 epsize |= DXEPTSIZ_XFERSIZE(length);
1097 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1098 __func__, packets, length, ureq->length, epsize, epsize_reg);
1100 /* store the request as the current one we're doing */
1101 hs_ep->req = hs_req;
1103 if (using_desc_dma(hsotg)) {
1105 u32 mps = hs_ep->ep.maxpacket;
1107 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1111 else if (length % mps)
1112 length += (mps - (length % mps));
1116 offset = ureq->actual;
1118 /* Fill DDMA chain entries */
1119 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1122 /* write descriptor chain address to control register */
1123 dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg);
1125 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1126 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1128 /* write size / packets */
1129 dwc2_writel(epsize, hsotg->regs + epsize_reg);
1131 if (using_dma(hsotg) && !continuing && (length != 0)) {
1133 * write DMA address to control register, buffer
1134 * already synced by dwc2_hsotg_ep_queue().
1137 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
1139 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1140 __func__, &ureq->dma, dma_reg);
1144 if (hs_ep->isochronous && hs_ep->interval == 1) {
1145 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
1146 dwc2_gadget_incr_frame_num(hs_ep);
1148 if (hs_ep->target_frame & 0x1)
1149 ctrl |= DXEPCTL_SETODDFR;
1151 ctrl |= DXEPCTL_SETEVENFR;
1154 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1156 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1158 /* For Setup request do not clear NAK */
1159 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1160 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1162 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1163 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
1166 * set these, it seems that DMA support increments past the end
1167 * of the packet buffer so we need to calculate the length from
1170 hs_ep->size_loaded = length;
1171 hs_ep->last_load = ureq->actual;
1173 if (dir_in && !using_dma(hsotg)) {
1174 /* set these anyway, we may need them for non-periodic in */
1175 hs_ep->fifo_load = 0;
1177 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1181 * Note, trying to clear the NAK here causes problems with transmit
1182 * on the S3C6400 ending up with the TXFIFO becoming full.
1185 /* check ep is enabled */
1186 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
1188 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1189 index, dwc2_readl(hsotg->regs + epctrl_reg));
1191 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1192 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
1194 /* enable ep interrupts */
1195 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1199 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1200 * @hsotg: The device state.
1201 * @hs_ep: The endpoint the request is on.
1202 * @req: The request being processed.
1204 * We've been asked to queue a request, so ensure that the memory buffer
1205 * is correctly setup for DMA. If we've been passed an extant DMA address
1206 * then ensure the buffer has been synced to memory. If our buffer has no
1207 * DMA memory, then we map the memory and mark our request to allow us to
1208 * cleanup on completion.
1210 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1211 struct dwc2_hsotg_ep *hs_ep,
1212 struct usb_request *req)
1216 hs_ep->map_dir = hs_ep->dir_in;
1217 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1224 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1225 __func__, req->buf, req->length);
1230 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1231 struct dwc2_hsotg_ep *hs_ep,
1232 struct dwc2_hsotg_req *hs_req)
1234 void *req_buf = hs_req->req.buf;
1236 /* If dma is not being used or buffer is aligned */
1237 if (!using_dma(hsotg) || !((long)req_buf & 3))
1240 WARN_ON(hs_req->saved_req_buf);
1242 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1243 hs_ep->ep.name, req_buf, hs_req->req.length);
1245 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1246 if (!hs_req->req.buf) {
1247 hs_req->req.buf = req_buf;
1249 "%s: unable to allocate memory for bounce buffer\n",
1254 /* Save actual buffer */
1255 hs_req->saved_req_buf = req_buf;
1258 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1263 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1264 struct dwc2_hsotg_ep *hs_ep,
1265 struct dwc2_hsotg_req *hs_req)
1267 /* If dma is not being used or buffer was aligned */
1268 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1271 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1272 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1274 /* Copy data from bounce buffer on successful out transfer */
1275 if (!hs_ep->dir_in && !hs_req->req.status)
1276 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1277 hs_req->req.actual);
1279 /* Free bounce buffer */
1280 kfree(hs_req->req.buf);
1282 hs_req->req.buf = hs_req->saved_req_buf;
1283 hs_req->saved_req_buf = NULL;
1287 * dwc2_gadget_target_frame_elapsed - Checks target frame
1288 * @hs_ep: The driver endpoint to check
1290 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1291 * corresponding transfer.
1293 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1295 struct dwc2_hsotg *hsotg = hs_ep->parent;
1296 u32 target_frame = hs_ep->target_frame;
1297 u32 current_frame = dwc2_hsotg_read_frameno(hsotg);
1298 bool frame_overrun = hs_ep->frame_overrun;
1300 if (!frame_overrun && current_frame >= target_frame)
1303 if (frame_overrun && current_frame >= target_frame &&
1304 ((current_frame - target_frame) < DSTS_SOFFN_LIMIT / 2))
1311 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1312 * @hsotg: The driver state
1313 * @hs_ep: the ep descriptor chain is for
1315 * Called to update EP0 structure's pointers depend on stage of
1318 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1319 struct dwc2_hsotg_ep *hs_ep)
1321 switch (hsotg->ep0_state) {
1322 case DWC2_EP0_SETUP:
1323 case DWC2_EP0_STATUS_OUT:
1324 hs_ep->desc_list = hsotg->setup_desc[0];
1325 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1327 case DWC2_EP0_DATA_IN:
1328 case DWC2_EP0_STATUS_IN:
1329 hs_ep->desc_list = hsotg->ctrl_in_desc;
1330 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1332 case DWC2_EP0_DATA_OUT:
1333 hs_ep->desc_list = hsotg->ctrl_out_desc;
1334 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1337 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1345 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1348 struct dwc2_hsotg_req *hs_req = our_req(req);
1349 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1350 struct dwc2_hsotg *hs = hs_ep->parent;
1354 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1355 ep->name, req, req->length, req->buf, req->no_interrupt,
1356 req->zero, req->short_not_ok);
1358 /* Prevent new request submission when controller is suspended */
1359 if (hs->lx_state == DWC2_L2) {
1360 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
1365 /* initialise status of the request */
1366 INIT_LIST_HEAD(&hs_req->queue);
1368 req->status = -EINPROGRESS;
1370 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1374 /* if we're using DMA, sync the buffers as necessary */
1375 if (using_dma(hs)) {
1376 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1380 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1381 if (using_desc_dma(hs) && !hs_ep->index) {
1382 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1387 first = list_empty(&hs_ep->queue);
1388 list_add_tail(&hs_req->queue, &hs_ep->queue);
1391 * Handle DDMA isochronous transfers separately - just add new entry
1392 * to the half of descriptor chain that is not processed by HW.
1393 * Transfer will be started once SW gets either one of NAK or
1394 * OutTknEpDis interrupts.
1396 if (using_desc_dma(hs) && hs_ep->isochronous &&
1397 hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1398 ret = dwc2_gadget_fill_isoc_desc(hs_ep, hs_req->req.dma,
1399 hs_req->req.length);
1401 dev_dbg(hs->dev, "%s: ISO desc chain full\n", __func__);
1407 if (!hs_ep->isochronous) {
1408 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1412 while (dwc2_gadget_target_frame_elapsed(hs_ep))
1413 dwc2_gadget_incr_frame_num(hs_ep);
1415 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1416 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1421 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1424 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1425 struct dwc2_hsotg *hs = hs_ep->parent;
1426 unsigned long flags = 0;
1429 spin_lock_irqsave(&hs->lock, flags);
1430 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1431 spin_unlock_irqrestore(&hs->lock, flags);
1436 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1437 struct usb_request *req)
1439 struct dwc2_hsotg_req *hs_req = our_req(req);
1445 * dwc2_hsotg_complete_oursetup - setup completion callback
1446 * @ep: The endpoint the request was on.
1447 * @req: The request completed.
1449 * Called on completion of any requests the driver itself
1450 * submitted that need cleaning up.
1452 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1453 struct usb_request *req)
1455 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1456 struct dwc2_hsotg *hsotg = hs_ep->parent;
1458 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1460 dwc2_hsotg_ep_free_request(ep, req);
1464 * ep_from_windex - convert control wIndex value to endpoint
1465 * @hsotg: The driver state.
1466 * @windex: The control request wIndex field (in host order).
1468 * Convert the given wIndex into a pointer to an driver endpoint
1469 * structure, or return NULL if it is not a valid endpoint.
1471 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1474 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1475 int idx = windex & 0x7F;
1477 if (windex >= 0x100)
1480 if (idx > hsotg->num_of_eps)
1483 return index_to_ep(hsotg, idx, dir);
1487 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1488 * @hsotg: The driver state.
1489 * @testmode: requested usb test mode
1490 * Enable usb Test Mode requested by the Host.
1492 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1494 int dctl = dwc2_readl(hsotg->regs + DCTL);
1496 dctl &= ~DCTL_TSTCTL_MASK;
1503 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1508 dwc2_writel(dctl, hsotg->regs + DCTL);
1513 * dwc2_hsotg_send_reply - send reply to control request
1514 * @hsotg: The device state
1516 * @buff: Buffer for request
1517 * @length: Length of reply.
1519 * Create a request and queue it on the given endpoint. This is useful as
1520 * an internal method of sending replies to certain control requests, etc.
1522 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1523 struct dwc2_hsotg_ep *ep,
1527 struct usb_request *req;
1530 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1532 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1533 hsotg->ep0_reply = req;
1535 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1539 req->buf = hsotg->ep0_buff;
1540 req->length = length;
1542 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1546 req->complete = dwc2_hsotg_complete_oursetup;
1549 memcpy(req->buf, buff, length);
1551 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1553 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1561 * dwc2_hsotg_process_req_status - process request GET_STATUS
1562 * @hsotg: The device state
1563 * @ctrl: USB control request
1565 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1566 struct usb_ctrlrequest *ctrl)
1568 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1569 struct dwc2_hsotg_ep *ep;
1573 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1576 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1580 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1581 case USB_RECIP_DEVICE:
1583 * bit 0 => self powered
1584 * bit 1 => remote wakeup
1586 reply = cpu_to_le16(0);
1589 case USB_RECIP_INTERFACE:
1590 /* currently, the data result should be zero */
1591 reply = cpu_to_le16(0);
1594 case USB_RECIP_ENDPOINT:
1595 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1599 reply = cpu_to_le16(ep->halted ? 1 : 0);
1606 if (le16_to_cpu(ctrl->wLength) != 2)
1609 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1611 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1618 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1621 * get_ep_head - return the first request on the endpoint
1622 * @hs_ep: The controller endpoint to get
1624 * Get the first request on the endpoint.
1626 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1628 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1633 * dwc2_gadget_start_next_request - Starts next request from ep queue
1634 * @hs_ep: Endpoint structure
1636 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1637 * in its handler. Hence we need to unmask it here to be able to do
1638 * resynchronization.
1640 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1643 struct dwc2_hsotg *hsotg = hs_ep->parent;
1644 int dir_in = hs_ep->dir_in;
1645 struct dwc2_hsotg_req *hs_req;
1646 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1648 if (!list_empty(&hs_ep->queue)) {
1649 hs_req = get_ep_head(hs_ep);
1650 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1653 if (!hs_ep->isochronous)
1657 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1660 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1662 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1663 mask |= DOEPMSK_OUTTKNEPDISMSK;
1664 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1669 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1670 * @hsotg: The device state
1671 * @ctrl: USB control request
1673 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1674 struct usb_ctrlrequest *ctrl)
1676 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1677 struct dwc2_hsotg_req *hs_req;
1678 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1679 struct dwc2_hsotg_ep *ep;
1686 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1687 __func__, set ? "SET" : "CLEAR");
1689 wValue = le16_to_cpu(ctrl->wValue);
1690 wIndex = le16_to_cpu(ctrl->wIndex);
1691 recip = ctrl->bRequestType & USB_RECIP_MASK;
1694 case USB_RECIP_DEVICE:
1696 case USB_DEVICE_TEST_MODE:
1697 if ((wIndex & 0xff) != 0)
1702 hsotg->test_mode = wIndex >> 8;
1703 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1706 "%s: failed to send reply\n", __func__);
1715 case USB_RECIP_ENDPOINT:
1716 ep = ep_from_windex(hsotg, wIndex);
1718 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1724 case USB_ENDPOINT_HALT:
1725 halted = ep->halted;
1727 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1729 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1732 "%s: failed to send reply\n", __func__);
1737 * we have to complete all requests for ep if it was
1738 * halted, and the halt was cleared by CLEAR_FEATURE
1741 if (!set && halted) {
1743 * If we have request in progress,
1749 list_del_init(&hs_req->queue);
1750 if (hs_req->req.complete) {
1751 spin_unlock(&hsotg->lock);
1752 usb_gadget_giveback_request(
1753 &ep->ep, &hs_req->req);
1754 spin_lock(&hsotg->lock);
1758 /* If we have pending request, then start it */
1760 dwc2_gadget_start_next_request(ep);
1775 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1778 * dwc2_hsotg_stall_ep0 - stall ep0
1779 * @hsotg: The device state
1781 * Set stall for ep0 as response for setup request.
1783 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1785 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1789 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1790 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1793 * DxEPCTL_Stall will be cleared by EP once it has
1794 * taken effect, so no need to clear later.
1797 ctrl = dwc2_readl(hsotg->regs + reg);
1798 ctrl |= DXEPCTL_STALL;
1799 ctrl |= DXEPCTL_CNAK;
1800 dwc2_writel(ctrl, hsotg->regs + reg);
1803 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1804 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1807 * complete won't be called, so we enqueue
1808 * setup request here
1810 dwc2_hsotg_enqueue_setup(hsotg);
1814 * dwc2_hsotg_process_control - process a control request
1815 * @hsotg: The device state
1816 * @ctrl: The control request received
1818 * The controller has received the SETUP phase of a control request, and
1819 * needs to work out what to do next (and whether to pass it on to the
1822 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1823 struct usb_ctrlrequest *ctrl)
1825 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1830 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1831 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1832 ctrl->wIndex, ctrl->wLength);
1834 if (ctrl->wLength == 0) {
1836 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1837 } else if (ctrl->bRequestType & USB_DIR_IN) {
1839 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1842 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1845 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1846 switch (ctrl->bRequest) {
1847 case USB_REQ_SET_ADDRESS:
1848 hsotg->connected = 1;
1849 dcfg = dwc2_readl(hsotg->regs + DCFG);
1850 dcfg &= ~DCFG_DEVADDR_MASK;
1851 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1852 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1853 dwc2_writel(dcfg, hsotg->regs + DCFG);
1855 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1857 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1860 case USB_REQ_GET_STATUS:
1861 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1864 case USB_REQ_CLEAR_FEATURE:
1865 case USB_REQ_SET_FEATURE:
1866 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1871 /* as a fallback, try delivering it to the driver to deal with */
1873 if (ret == 0 && hsotg->driver) {
1874 spin_unlock(&hsotg->lock);
1875 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1876 spin_lock(&hsotg->lock);
1878 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1882 * the request is either unhandlable, or is not formatted correctly
1883 * so respond with a STALL for the status stage to indicate failure.
1887 dwc2_hsotg_stall_ep0(hsotg);
1891 * dwc2_hsotg_complete_setup - completion of a setup transfer
1892 * @ep: The endpoint the request was on.
1893 * @req: The request completed.
1895 * Called on completion of any requests the driver itself submitted for
1898 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1899 struct usb_request *req)
1901 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1902 struct dwc2_hsotg *hsotg = hs_ep->parent;
1904 if (req->status < 0) {
1905 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1909 spin_lock(&hsotg->lock);
1910 if (req->actual == 0)
1911 dwc2_hsotg_enqueue_setup(hsotg);
1913 dwc2_hsotg_process_control(hsotg, req->buf);
1914 spin_unlock(&hsotg->lock);
1918 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1919 * @hsotg: The device state.
1921 * Enqueue a request on EP0 if necessary to received any SETUP packets
1922 * received from the host.
1924 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1926 struct usb_request *req = hsotg->ctrl_req;
1927 struct dwc2_hsotg_req *hs_req = our_req(req);
1930 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1934 req->buf = hsotg->ctrl_buff;
1935 req->complete = dwc2_hsotg_complete_setup;
1937 if (!list_empty(&hs_req->queue)) {
1938 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1942 hsotg->eps_out[0]->dir_in = 0;
1943 hsotg->eps_out[0]->send_zlp = 0;
1944 hsotg->ep0_state = DWC2_EP0_SETUP;
1946 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1948 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1950 * Don't think there's much we can do other than watch the
1956 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1957 struct dwc2_hsotg_ep *hs_ep)
1960 u8 index = hs_ep->index;
1961 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1962 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1965 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1968 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1970 if (using_desc_dma(hsotg)) {
1971 /* Not specific buffer needed for ep0 ZLP */
1972 dma_addr_t dma = hs_ep->desc_list_dma;
1974 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
1975 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
1977 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1978 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1982 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1983 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1984 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1985 ctrl |= DXEPCTL_USBACTEP;
1986 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1990 * dwc2_hsotg_complete_request - complete a request given to us
1991 * @hsotg: The device state.
1992 * @hs_ep: The endpoint the request was on.
1993 * @hs_req: The request to complete.
1994 * @result: The result code (0 => Ok, otherwise errno)
1996 * The given request has finished, so call the necessary completion
1997 * if it has one and then look to see if we can start a new request
2000 * Note, expects the ep to already be locked as appropriate.
2002 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2003 struct dwc2_hsotg_ep *hs_ep,
2004 struct dwc2_hsotg_req *hs_req,
2008 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2012 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2013 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2016 * only replace the status if we've not already set an error
2017 * from a previous transaction
2020 if (hs_req->req.status == -EINPROGRESS)
2021 hs_req->req.status = result;
2023 if (using_dma(hsotg))
2024 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2026 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2029 list_del_init(&hs_req->queue);
2032 * call the complete request with the locks off, just in case the
2033 * request tries to queue more work for this endpoint.
2036 if (hs_req->req.complete) {
2037 spin_unlock(&hsotg->lock);
2038 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2039 spin_lock(&hsotg->lock);
2042 /* In DDMA don't need to proceed to starting of next ISOC request */
2043 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2047 * Look to see if there is anything else to do. Note, the completion
2048 * of the previous request may have caused a new request to be started
2049 * so be careful when doing this.
2052 if (!hs_ep->req && result >= 0)
2053 dwc2_gadget_start_next_request(hs_ep);
2057 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2058 * @hs_ep: The endpoint the request was on.
2060 * Get first request from the ep queue, determine descriptor on which complete
2061 * happened. SW based on isoc_chain_num discovers which half of the descriptor
2062 * chain is currently in use by HW, adjusts dma_address and calculates index
2063 * of completed descriptor based on the value of DEPDMA register. Update actual
2064 * length of request, giveback to gadget.
2066 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2068 struct dwc2_hsotg *hsotg = hs_ep->parent;
2069 struct dwc2_hsotg_req *hs_req;
2070 struct usb_request *ureq;
2072 dma_addr_t dma_addr;
2078 hs_req = get_ep_head(hs_ep);
2080 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2083 ureq = &hs_req->req;
2085 dma_addr = hs_ep->desc_list_dma;
2088 * If lower half of descriptor chain is currently use by SW,
2089 * that means higher half is being processed by HW, so shift
2090 * DMA address to higher half of descriptor chain.
2092 if (!hs_ep->isoc_chain_num)
2093 dma_addr += sizeof(struct dwc2_dma_desc) *
2094 (MAX_DMA_DESC_NUM_GENERIC / 2);
2096 dma_reg = hs_ep->dir_in ? DIEPDMA(hs_ep->index) : DOEPDMA(hs_ep->index);
2097 depdma = dwc2_readl(hsotg->regs + dma_reg);
2099 index = (depdma - dma_addr) / sizeof(struct dwc2_dma_desc) - 1;
2100 desc_sts = hs_ep->desc_list[index].status;
2102 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2103 DEV_DMA_ISOC_RX_NBYTES_MASK;
2104 ureq->actual = ureq->length -
2105 ((desc_sts & mask) >> DEV_DMA_ISOC_NBYTES_SHIFT);
2107 /* Adjust actual length for ISOC Out if length is not align of 4 */
2108 if (!hs_ep->dir_in && ureq->length & 0x3)
2109 ureq->actual += 4 - (ureq->length & 0x3);
2111 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2115 * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any.
2116 * @hs_ep: The isochronous endpoint to be re-enabled.
2118 * If ep has been disabled due to last descriptor servicing (IN endpoint) or
2119 * BNA (OUT endpoint) check the status of other half of descriptor chain that
2120 * was under SW control till HW was busy and restart the endpoint if needed.
2122 static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
2124 struct dwc2_hsotg *hsotg = hs_ep->parent;
2128 u32 dma_addr = hs_ep->desc_list_dma;
2129 unsigned char index = hs_ep->index;
2131 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
2132 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2134 ctrl = dwc2_readl(hsotg->regs + depctl);
2137 * EP was disabled if HW has processed last descriptor or BNA was set.
2138 * So restart ep if SW has prepared new descriptor chain in ep_queue
2139 * routine while HW was busy.
2141 if (!(ctrl & DXEPCTL_EPENA)) {
2142 if (!hs_ep->next_desc) {
2143 dev_dbg(hsotg->dev, "%s: No more ISOC requests\n",
2148 dma_addr += sizeof(struct dwc2_dma_desc) *
2149 (MAX_DMA_DESC_NUM_GENERIC / 2) *
2150 hs_ep->isoc_chain_num;
2151 dwc2_writel(dma_addr, hsotg->regs + dma_reg);
2153 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
2154 dwc2_writel(ctrl, hsotg->regs + depctl);
2156 /* Switch ISOC descriptor chain number being processed by SW*/
2157 hs_ep->isoc_chain_num = (hs_ep->isoc_chain_num ^ 1) & 0x1;
2158 hs_ep->next_desc = 0;
2160 dev_dbg(hsotg->dev, "%s: Restarted isochronous endpoint\n",
2166 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2167 * @hsotg: The device state.
2168 * @ep_idx: The endpoint index for the data
2169 * @size: The size of data in the fifo, in bytes
2171 * The FIFO status shows there is data to read from the FIFO for a given
2172 * endpoint, so sort out whether we need to read the data into a request
2173 * that has been made for that endpoint.
2175 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2177 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2178 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2179 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
2185 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
2189 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2190 __func__, size, ep_idx, epctl);
2192 /* dump the data from the FIFO, we've nothing we can do */
2193 for (ptr = 0; ptr < size; ptr += 4)
2194 (void)dwc2_readl(fifo);
2200 read_ptr = hs_req->req.actual;
2201 max_req = hs_req->req.length - read_ptr;
2203 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2204 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2206 if (to_read > max_req) {
2208 * more data appeared than we where willing
2209 * to deal with in this request.
2212 /* currently we don't deal this */
2216 hs_ep->total_data += to_read;
2217 hs_req->req.actual += to_read;
2218 to_read = DIV_ROUND_UP(to_read, 4);
2221 * note, we might over-write the buffer end by 3 bytes depending on
2222 * alignment of the data.
2224 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
2228 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2229 * @hsotg: The device instance
2230 * @dir_in: If IN zlp
2232 * Generate a zero-length IN packet request for terminating a SETUP
2235 * Note, since we don't write any data to the TxFIFO, then it is
2236 * currently believed that we do not need to wait for any space in
2239 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2241 /* eps_out[0] is used in both directions */
2242 hsotg->eps_out[0]->dir_in = dir_in;
2243 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2245 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2248 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
2253 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2254 if (ctrl & DXEPCTL_EOFRNUM)
2255 ctrl |= DXEPCTL_SETEVENFR;
2257 ctrl |= DXEPCTL_SETODDFR;
2258 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
2262 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2263 * @hs_ep - The endpoint on which transfer went
2265 * Iterate over endpoints descriptor chain and get info on bytes remained
2266 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2268 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2270 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2271 struct dwc2_hsotg *hsotg = hs_ep->parent;
2272 unsigned int bytes_rem = 0;
2273 unsigned int bytes_rem_correction = 0;
2274 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2277 u32 mps = hs_ep->ep.maxpacket;
2278 int dir_in = hs_ep->dir_in;
2283 /* Interrupt OUT EP with mps not multiple of 4 */
2285 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2286 bytes_rem_correction = 4 - (mps % 4);
2288 for (i = 0; i < hs_ep->desc_count; ++i) {
2289 status = desc->status;
2290 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2291 bytes_rem -= bytes_rem_correction;
2293 if (status & DEV_DMA_STS_MASK)
2294 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2295 i, status & DEV_DMA_STS_MASK);
2297 if (status & DEV_DMA_L)
2307 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2308 * @hsotg: The device instance
2309 * @epnum: The endpoint received from
2311 * The RXFIFO has delivered an OutDone event, which means that the data
2312 * transfer for an OUT endpoint has been completed, either by a short
2313 * packet or by the finish of a transfer.
2315 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2317 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
2318 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2319 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2320 struct usb_request *req = &hs_req->req;
2321 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2325 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2329 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2330 dev_dbg(hsotg->dev, "zlp packet received\n");
2331 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2332 dwc2_hsotg_enqueue_setup(hsotg);
2336 if (using_desc_dma(hsotg))
2337 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2339 if (using_dma(hsotg)) {
2340 unsigned int size_done;
2343 * Calculate the size of the transfer by checking how much
2344 * is left in the endpoint size register and then working it
2345 * out from the amount we loaded for the transfer.
2347 * We need to do this as DMA pointers are always 32bit aligned
2348 * so may overshoot/undershoot the transfer.
2351 size_done = hs_ep->size_loaded - size_left;
2352 size_done += hs_ep->last_load;
2354 req->actual = size_done;
2357 /* if there is more request to do, schedule new transfer */
2358 if (req->actual < req->length && size_left == 0) {
2359 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2363 if (req->actual < req->length && req->short_not_ok) {
2364 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2365 __func__, req->actual, req->length);
2368 * todo - what should we return here? there's no one else
2369 * even bothering to check the status.
2373 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2374 if (!using_desc_dma(hsotg) && epnum == 0 &&
2375 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2376 /* Move to STATUS IN */
2377 dwc2_hsotg_ep0_zlp(hsotg, true);
2382 * Slave mode OUT transfers do not go through XferComplete so
2383 * adjust the ISOC parity here.
2385 if (!using_dma(hsotg)) {
2386 if (hs_ep->isochronous && hs_ep->interval == 1)
2387 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
2388 else if (hs_ep->isochronous && hs_ep->interval > 1)
2389 dwc2_gadget_incr_frame_num(hs_ep);
2392 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2396 * dwc2_hsotg_handle_rx - RX FIFO has data
2397 * @hsotg: The device instance
2399 * The IRQ handler has detected that the RX FIFO has some data in it
2400 * that requires processing, so find out what is in there and do the
2403 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2404 * chunks, so if you have x packets received on an endpoint you'll get x
2405 * FIFO events delivered, each with a packet's worth of data in it.
2407 * When using DMA, we should not be processing events from the RXFIFO
2408 * as the actual data should be sent to the memory directly and we turn
2409 * on the completion interrupts to get notifications of transfer completion.
2411 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2413 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
2414 u32 epnum, status, size;
2416 WARN_ON(using_dma(hsotg));
2418 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2419 status = grxstsr & GRXSTS_PKTSTS_MASK;
2421 size = grxstsr & GRXSTS_BYTECNT_MASK;
2422 size >>= GRXSTS_BYTECNT_SHIFT;
2424 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2425 __func__, grxstsr, size, epnum);
2427 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2428 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2429 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2432 case GRXSTS_PKTSTS_OUTDONE:
2433 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2434 dwc2_hsotg_read_frameno(hsotg));
2436 if (!using_dma(hsotg))
2437 dwc2_hsotg_handle_outdone(hsotg, epnum);
2440 case GRXSTS_PKTSTS_SETUPDONE:
2442 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2443 dwc2_hsotg_read_frameno(hsotg),
2444 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2446 * Call dwc2_hsotg_handle_outdone here if it was not called from
2447 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2448 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2450 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2451 dwc2_hsotg_handle_outdone(hsotg, epnum);
2454 case GRXSTS_PKTSTS_OUTRX:
2455 dwc2_hsotg_rx_data(hsotg, epnum, size);
2458 case GRXSTS_PKTSTS_SETUPRX:
2460 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2461 dwc2_hsotg_read_frameno(hsotg),
2462 dwc2_readl(hsotg->regs + DOEPCTL(0)));
2464 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2466 dwc2_hsotg_rx_data(hsotg, epnum, size);
2470 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2473 dwc2_hsotg_dump(hsotg);
2479 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2480 * @mps: The maximum packet size in bytes.
2482 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2486 return D0EPCTL_MPS_64;
2488 return D0EPCTL_MPS_32;
2490 return D0EPCTL_MPS_16;
2492 return D0EPCTL_MPS_8;
2495 /* bad max packet size, warn and return invalid result */
2501 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2502 * @hsotg: The driver state.
2503 * @ep: The index number of the endpoint
2504 * @mps: The maximum packet size in bytes
2505 * @mc: The multicount value
2507 * Configure the maximum packet size for the given endpoint, updating
2508 * the hardware control registers to reflect this.
2510 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2511 unsigned int ep, unsigned int mps,
2512 unsigned int mc, unsigned int dir_in)
2514 struct dwc2_hsotg_ep *hs_ep;
2515 void __iomem *regs = hsotg->regs;
2518 hs_ep = index_to_ep(hsotg, ep, dir_in);
2523 u32 mps_bytes = mps;
2525 /* EP0 is a special case */
2526 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2529 hs_ep->ep.maxpacket = mps_bytes;
2537 hs_ep->ep.maxpacket = mps;
2541 reg = dwc2_readl(regs + DIEPCTL(ep));
2542 reg &= ~DXEPCTL_MPS_MASK;
2544 dwc2_writel(reg, regs + DIEPCTL(ep));
2546 reg = dwc2_readl(regs + DOEPCTL(ep));
2547 reg &= ~DXEPCTL_MPS_MASK;
2549 dwc2_writel(reg, regs + DOEPCTL(ep));
2555 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2559 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2560 * @hsotg: The driver state
2561 * @idx: The index for the endpoint (0..15)
2563 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2568 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2569 hsotg->regs + GRSTCTL);
2571 /* wait until the fifo is flushed */
2575 val = dwc2_readl(hsotg->regs + GRSTCTL);
2577 if ((val & (GRSTCTL_TXFFLSH)) == 0)
2580 if (--timeout == 0) {
2582 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
2592 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2593 * @hsotg: The driver state
2594 * @hs_ep: The driver endpoint to check.
2596 * Check to see if there is a request that has data to send, and if so
2597 * make an attempt to write data into the FIFO.
2599 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2600 struct dwc2_hsotg_ep *hs_ep)
2602 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2604 if (!hs_ep->dir_in || !hs_req) {
2606 * if request is not enqueued, we disable interrupts
2607 * for endpoints, excepting ep0
2609 if (hs_ep->index != 0)
2610 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2615 if (hs_req->req.actual < hs_req->req.length) {
2616 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2618 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2625 * dwc2_hsotg_complete_in - complete IN transfer
2626 * @hsotg: The device state.
2627 * @hs_ep: The endpoint that has just completed.
2629 * An IN transfer has been completed, update the transfer's state and then
2630 * call the relevant completion routines.
2632 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2633 struct dwc2_hsotg_ep *hs_ep)
2635 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2636 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
2637 int size_left, size_done;
2640 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2644 /* Finish ZLP handling for IN EP0 transactions */
2645 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2646 dev_dbg(hsotg->dev, "zlp packet sent\n");
2649 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2650 * changed to IN. Change back to complete OUT transfer request
2654 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2655 if (hsotg->test_mode) {
2658 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2660 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2662 dwc2_hsotg_stall_ep0(hsotg);
2666 dwc2_hsotg_enqueue_setup(hsotg);
2671 * Calculate the size of the transfer by checking how much is left
2672 * in the endpoint size register and then working it out from
2673 * the amount we loaded for the transfer.
2675 * We do this even for DMA, as the transfer may have incremented
2676 * past the end of the buffer (DMA transfers are always 32bit
2679 if (using_desc_dma(hsotg)) {
2680 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2682 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2685 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2688 size_done = hs_ep->size_loaded - size_left;
2689 size_done += hs_ep->last_load;
2691 if (hs_req->req.actual != size_done)
2692 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2693 __func__, hs_req->req.actual, size_done);
2695 hs_req->req.actual = size_done;
2696 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2697 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2699 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2700 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2701 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2705 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2706 if (hs_ep->send_zlp) {
2707 hs_ep->send_zlp = 0;
2708 if (!using_desc_dma(hsotg)) {
2709 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2710 /* transfer will be completed on next complete interrupt */
2715 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2716 /* Move to STATUS OUT */
2717 dwc2_hsotg_ep0_zlp(hsotg, false);
2721 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2725 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2726 * @hsotg: The device state.
2727 * @idx: Index of ep.
2728 * @dir_in: Endpoint direction 1-in 0-out.
2730 * Reads for endpoint with given index and direction, by masking
2731 * epint_reg with coresponding mask.
2733 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2734 unsigned int idx, int dir_in)
2736 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2737 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2742 mask = dwc2_readl(hsotg->regs + epmsk_reg);
2743 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
2744 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2745 mask |= DXEPINT_SETUP_RCVD;
2747 ints = dwc2_readl(hsotg->regs + epint_reg);
2753 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2754 * @hs_ep: The endpoint on which interrupt is asserted.
2756 * This interrupt indicates that the endpoint has been disabled per the
2757 * application's request.
2759 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2760 * in case of ISOC completes current request.
2762 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2763 * request starts it.
2765 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2767 struct dwc2_hsotg *hsotg = hs_ep->parent;
2768 struct dwc2_hsotg_req *hs_req;
2769 unsigned char idx = hs_ep->index;
2770 int dir_in = hs_ep->dir_in;
2771 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2772 int dctl = dwc2_readl(hsotg->regs + DCTL);
2774 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2777 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2779 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2781 if (hs_ep->isochronous) {
2782 dwc2_hsotg_complete_in(hsotg, hs_ep);
2786 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2787 int dctl = dwc2_readl(hsotg->regs + DCTL);
2789 dctl |= DCTL_CGNPINNAK;
2790 dwc2_writel(dctl, hsotg->regs + DCTL);
2795 if (dctl & DCTL_GOUTNAKSTS) {
2796 dctl |= DCTL_CGOUTNAK;
2797 dwc2_writel(dctl, hsotg->regs + DCTL);
2800 if (!hs_ep->isochronous)
2803 if (list_empty(&hs_ep->queue)) {
2804 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2810 hs_req = get_ep_head(hs_ep);
2812 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2814 dwc2_gadget_incr_frame_num(hs_ep);
2815 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2817 dwc2_gadget_start_next_request(hs_ep);
2821 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2822 * @hs_ep: The endpoint on which interrupt is asserted.
2824 * This is starting point for ISOC-OUT transfer, synchronization done with
2825 * first out token received from host while corresponding EP is disabled.
2827 * Device does not know initial frame in which out token will come. For this
2828 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2829 * getting this interrupt SW starts calculation for next transfer frame.
2831 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2833 struct dwc2_hsotg *hsotg = ep->parent;
2834 int dir_in = ep->dir_in;
2838 if (dir_in || !ep->isochronous)
2842 * Store frame in which irq was asserted here, as
2843 * it can change while completing request below.
2845 tmp = dwc2_hsotg_read_frameno(hsotg);
2847 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA);
2849 if (using_desc_dma(hsotg)) {
2850 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2851 /* Start first ISO Out */
2852 ep->target_frame = tmp;
2853 dwc2_gadget_start_isoc_ddma(ep);
2858 if (ep->interval > 1 &&
2859 ep->target_frame == TARGET_FRAME_INITIAL) {
2863 dsts = dwc2_readl(hsotg->regs + DSTS);
2864 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2865 dwc2_gadget_incr_frame_num(ep);
2867 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2868 if (ep->target_frame & 0x1)
2869 ctrl |= DXEPCTL_SETODDFR;
2871 ctrl |= DXEPCTL_SETEVENFR;
2873 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2876 dwc2_gadget_start_next_request(ep);
2877 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2878 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2879 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2883 * dwc2_gadget_handle_nak - handle NAK interrupt
2884 * @hs_ep: The endpoint on which interrupt is asserted.
2886 * This is starting point for ISOC-IN transfer, synchronization done with
2887 * first IN token received from host while corresponding EP is disabled.
2889 * Device does not know when first one token will arrive from host. On first
2890 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2891 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2892 * sent in response to that as there was no data in FIFO. SW is basing on this
2893 * interrupt to obtain frame in which token has come and then based on the
2894 * interval calculates next frame for transfer.
2896 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2898 struct dwc2_hsotg *hsotg = hs_ep->parent;
2899 int dir_in = hs_ep->dir_in;
2901 if (!dir_in || !hs_ep->isochronous)
2904 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2905 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2907 if (using_desc_dma(hsotg)) {
2908 dwc2_gadget_start_isoc_ddma(hs_ep);
2912 if (hs_ep->interval > 1) {
2913 u32 ctrl = dwc2_readl(hsotg->regs +
2914 DIEPCTL(hs_ep->index));
2915 if (hs_ep->target_frame & 0x1)
2916 ctrl |= DXEPCTL_SETODDFR;
2918 ctrl |= DXEPCTL_SETEVENFR;
2920 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2923 dwc2_hsotg_complete_request(hsotg, hs_ep,
2924 get_ep_head(hs_ep), 0);
2927 dwc2_gadget_incr_frame_num(hs_ep);
2931 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2932 * @hsotg: The driver state
2933 * @idx: The index for the endpoint (0..15)
2934 * @dir_in: Set if this is an IN endpoint
2936 * Process and clear any interrupt pending for an individual endpoint
2938 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2941 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2942 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2943 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2944 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2948 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2949 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2951 /* Clear endpoint interrupts */
2952 dwc2_writel(ints, hsotg->regs + epint_reg);
2955 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2956 __func__, idx, dir_in ? "in" : "out");
2960 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2961 __func__, idx, dir_in ? "in" : "out", ints);
2963 /* Don't process XferCompl interrupt if it is a setup packet */
2964 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2965 ints &= ~DXEPINT_XFERCOMPL;
2968 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2969 * stage and xfercomplete was generated without SETUP phase done
2970 * interrupt. SW should parse received setup packet only after host's
2971 * exit from setup phase of control transfer.
2973 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
2974 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
2975 ints &= ~DXEPINT_XFERCOMPL;
2977 if (ints & DXEPINT_XFERCOMPL) {
2979 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2980 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2981 dwc2_readl(hsotg->regs + epsiz_reg));
2983 /* In DDMA handle isochronous requests separately */
2984 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
2985 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
2986 /* Try to start next isoc request */
2987 dwc2_gadget_start_next_isoc_ddma(hs_ep);
2988 } else if (dir_in) {
2990 * We get OutDone from the FIFO, so we only
2991 * need to look at completing IN requests here
2992 * if operating slave mode
2994 if (hs_ep->isochronous && hs_ep->interval > 1)
2995 dwc2_gadget_incr_frame_num(hs_ep);
2997 dwc2_hsotg_complete_in(hsotg, hs_ep);
2998 if (ints & DXEPINT_NAKINTRPT)
2999 ints &= ~DXEPINT_NAKINTRPT;
3001 if (idx == 0 && !hs_ep->req)
3002 dwc2_hsotg_enqueue_setup(hsotg);
3003 } else if (using_dma(hsotg)) {
3005 * We're using DMA, we need to fire an OutDone here
3006 * as we ignore the RXFIFO.
3008 if (hs_ep->isochronous && hs_ep->interval > 1)
3009 dwc2_gadget_incr_frame_num(hs_ep);
3011 dwc2_hsotg_handle_outdone(hsotg, idx);
3015 if (ints & DXEPINT_EPDISBLD)
3016 dwc2_gadget_handle_ep_disabled(hs_ep);
3018 if (ints & DXEPINT_OUTTKNEPDIS)
3019 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3021 if (ints & DXEPINT_NAKINTRPT)
3022 dwc2_gadget_handle_nak(hs_ep);
3024 if (ints & DXEPINT_AHBERR)
3025 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3027 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3028 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3030 if (using_dma(hsotg) && idx == 0) {
3032 * this is the notification we've received a
3033 * setup packet. In non-DMA mode we'd get this
3034 * from the RXFIFO, instead we need to process
3041 dwc2_hsotg_handle_outdone(hsotg, 0);
3045 if (ints & DXEPINT_STSPHSERCVD) {
3046 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3048 /* Move to STATUS IN for DDMA */
3049 if (using_desc_dma(hsotg))
3050 dwc2_hsotg_ep0_zlp(hsotg, true);
3053 if (ints & DXEPINT_BACK2BACKSETUP)
3054 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3056 if (ints & DXEPINT_BNAINTR) {
3057 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3060 * Try to start next isoc request, if any.
3061 * Sometimes the endpoint remains enabled after BNA interrupt
3062 * assertion, which is not expected, hence we can enter here
3065 if (hs_ep->isochronous)
3066 dwc2_gadget_start_next_isoc_ddma(hs_ep);
3069 if (dir_in && !hs_ep->isochronous) {
3070 /* not sure if this is important, but we'll clear it anyway */
3071 if (ints & DXEPINT_INTKNTXFEMP) {
3072 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3076 /* this probably means something bad is happening */
3077 if (ints & DXEPINT_INTKNEPMIS) {
3078 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3082 /* FIFO has space or is empty (see GAHBCFG) */
3083 if (hsotg->dedicated_fifos &&
3084 ints & DXEPINT_TXFEMP) {
3085 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3087 if (!using_dma(hsotg))
3088 dwc2_hsotg_trytx(hsotg, hs_ep);
3094 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3095 * @hsotg: The device state.
3097 * Handle updating the device settings after the enumeration phase has
3100 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3102 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
3103 int ep0_mps = 0, ep_mps = 8;
3106 * This should signal the finish of the enumeration phase
3107 * of the USB handshaking, so we should now know what rate
3111 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3114 * note, since we're limited by the size of transfer on EP0, and
3115 * it seems IN transfers must be a even number of packets we do
3116 * not advertise a 64byte MPS on EP0.
3119 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3120 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3121 case DSTS_ENUMSPD_FS:
3122 case DSTS_ENUMSPD_FS48:
3123 hsotg->gadget.speed = USB_SPEED_FULL;
3124 ep0_mps = EP0_MPS_LIMIT;
3128 case DSTS_ENUMSPD_HS:
3129 hsotg->gadget.speed = USB_SPEED_HIGH;
3130 ep0_mps = EP0_MPS_LIMIT;
3134 case DSTS_ENUMSPD_LS:
3135 hsotg->gadget.speed = USB_SPEED_LOW;
3139 * note, we don't actually support LS in this driver at the
3140 * moment, and the documentation seems to imply that it isn't
3141 * supported by the PHYs on some of the devices.
3145 dev_info(hsotg->dev, "new device is %s\n",
3146 usb_speed_string(hsotg->gadget.speed));
3149 * we should now know the maximum packet size for an
3150 * endpoint, so set the endpoints to a default value.
3155 /* Initialize ep0 for both in and out directions */
3156 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3157 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3158 for (i = 1; i < hsotg->num_of_eps; i++) {
3159 if (hsotg->eps_in[i])
3160 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3162 if (hsotg->eps_out[i])
3163 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3168 /* ensure after enumeration our EP0 is active */
3170 dwc2_hsotg_enqueue_setup(hsotg);
3172 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3173 dwc2_readl(hsotg->regs + DIEPCTL0),
3174 dwc2_readl(hsotg->regs + DOEPCTL0));
3178 * kill_all_requests - remove all requests from the endpoint's queue
3179 * @hsotg: The device state.
3180 * @ep: The endpoint the requests may be on.
3181 * @result: The result code to use.
3183 * Go through the requests on the given endpoint and mark them
3184 * completed with the given result code.
3186 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3187 struct dwc2_hsotg_ep *ep,
3190 struct dwc2_hsotg_req *req, *treq;
3195 list_for_each_entry_safe(req, treq, &ep->queue, queue)
3196 dwc2_hsotg_complete_request(hsotg, ep, req,
3199 if (!hsotg->dedicated_fifos)
3201 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3202 if (size < ep->fifo_size)
3203 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3207 * dwc2_hsotg_disconnect - disconnect service
3208 * @hsotg: The device state.
3210 * The device has been disconnected. Remove all current
3211 * transactions and signal the gadget driver that this
3214 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3218 if (!hsotg->connected)
3221 hsotg->connected = 0;
3222 hsotg->test_mode = 0;
3224 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3225 if (hsotg->eps_in[ep])
3226 kill_all_requests(hsotg, hsotg->eps_in[ep],
3228 if (hsotg->eps_out[ep])
3229 kill_all_requests(hsotg, hsotg->eps_out[ep],
3233 call_gadget(hsotg, disconnect);
3234 hsotg->lx_state = DWC2_L3;
3238 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3239 * @hsotg: The device state:
3240 * @periodic: True if this is a periodic FIFO interrupt
3242 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3244 struct dwc2_hsotg_ep *ep;
3247 /* look through for any more data to transmit */
3248 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3249 ep = index_to_ep(hsotg, epno, 1);
3257 if ((periodic && !ep->periodic) ||
3258 (!periodic && ep->periodic))
3261 ret = dwc2_hsotg_trytx(hsotg, ep);
3267 /* IRQ flags which will trigger a retry around the IRQ loop */
3268 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3273 * dwc2_hsotg_core_init - issue softreset to the core
3274 * @hsotg: The device state
3276 * Issue a soft reset to the core, and await the core finishing it.
3278 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3286 /* Kill any ep0 requests as controller will be reinitialized */
3287 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3290 if (dwc2_core_reset(hsotg, true))
3294 * we must now enable ep0 ready for host detection and then
3295 * set configuration.
3298 /* keep other bits untouched (so e.g. forced modes are not lost) */
3299 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3300 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3301 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
3303 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
3304 (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
3305 hsotg->params.speed == DWC2_SPEED_PARAM_LOW)) {
3306 /* FS/LS Dedicated Transceiver Interface */
3307 usbcfg |= GUSBCFG_PHYSEL;
3309 /* set the PLL on, remove the HNP/SRP and set the PHY */
3310 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3311 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3312 (val << GUSBCFG_USBTRDTIM_SHIFT);
3314 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3316 dwc2_hsotg_init_fifo(hsotg);
3319 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3321 dcfg |= DCFG_EPMISCNT(1);
3323 switch (hsotg->params.speed) {
3324 case DWC2_SPEED_PARAM_LOW:
3325 dcfg |= DCFG_DEVSPD_LS;
3327 case DWC2_SPEED_PARAM_FULL:
3328 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3329 dcfg |= DCFG_DEVSPD_FS48;
3331 dcfg |= DCFG_DEVSPD_FS;
3334 dcfg |= DCFG_DEVSPD_HS;
3337 dwc2_writel(dcfg, hsotg->regs + DCFG);
3339 /* Clear any pending OTG interrupts */
3340 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
3342 /* Clear any pending interrupts */
3343 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
3344 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3345 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3346 GINTSTS_USBRST | GINTSTS_RESETDET |
3347 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3348 GINTSTS_USBSUSP | GINTSTS_WKUPINT;
3350 if (!using_desc_dma(hsotg))
3351 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3353 if (!hsotg->params.external_id_pin_ctl)
3354 intmsk |= GINTSTS_CONIDSTSCHNG;
3356 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
3358 if (using_dma(hsotg)) {
3359 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3360 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
3361 hsotg->regs + GAHBCFG);
3363 /* Set DDMA mode support in the core if needed */
3364 if (using_desc_dma(hsotg))
3365 __orr32(hsotg->regs + DCFG, DCFG_DESCDMA_EN);
3368 dwc2_writel(((hsotg->dedicated_fifos) ?
3369 (GAHBCFG_NP_TXF_EMP_LVL |
3370 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3371 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
3375 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3376 * when we have no data to transfer. Otherwise we get being flooded by
3380 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3381 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3382 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3383 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3384 hsotg->regs + DIEPMSK);
3387 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3388 * DMA mode we may need this and StsPhseRcvd.
3390 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3391 DOEPMSK_STSPHSERCVDMSK) : 0) |
3392 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3394 hsotg->regs + DOEPMSK);
3396 /* Enable BNA interrupt for DDMA */
3397 if (using_desc_dma(hsotg))
3398 __orr32(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK);
3400 dwc2_writel(0, hsotg->regs + DAINTMSK);
3402 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3403 dwc2_readl(hsotg->regs + DIEPCTL0),
3404 dwc2_readl(hsotg->regs + DOEPCTL0));
3406 /* enable in and out endpoint interrupts */
3407 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3410 * Enable the RXFIFO when in slave mode, as this is how we collect
3411 * the data. In DMA mode, we get events from the FIFO but also
3412 * things we cannot process, so do not use it.
3414 if (!using_dma(hsotg))
3415 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3417 /* Enable interrupts for EP0 in and out */
3418 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3419 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3421 if (!is_usb_reset) {
3422 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3423 udelay(10); /* see openiboot */
3424 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
3427 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
3430 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3431 * writing to the EPCTL register..
3434 /* set to read 1 8byte packet */
3435 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3436 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
3438 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3439 DXEPCTL_CNAK | DXEPCTL_EPENA |
3441 hsotg->regs + DOEPCTL0);
3443 /* enable, but don't activate EP0in */
3444 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3445 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
3447 /* clear global NAKs */
3448 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3450 val |= DCTL_SFTDISCON;
3451 __orr32(hsotg->regs + DCTL, val);
3453 /* must be at-least 3ms to allow bus to see disconnect */
3456 hsotg->lx_state = DWC2_L0;
3458 dwc2_hsotg_enqueue_setup(hsotg);
3460 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3461 dwc2_readl(hsotg->regs + DIEPCTL0),
3462 dwc2_readl(hsotg->regs + DOEPCTL0));
3465 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3467 /* set the soft-disconnect bit */
3468 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3471 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3473 /* remove the soft-disconnect and let's go */
3474 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3478 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3479 * @hsotg: The device state:
3481 * This interrupt indicates one of the following conditions occurred while
3482 * transmitting an ISOC transaction.
3483 * - Corrupted IN Token for ISOC EP.
3484 * - Packet not complete in FIFO.
3486 * The following actions will be taken:
3487 * - Determine the EP
3488 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3490 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3492 struct dwc2_hsotg_ep *hs_ep;
3496 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3498 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3499 hs_ep = hsotg->eps_in[idx];
3500 epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx));
3501 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
3502 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3503 epctrl |= DXEPCTL_SNAK;
3504 epctrl |= DXEPCTL_EPDIS;
3505 dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx));
3509 /* Clear interrupt */
3510 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
3514 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3515 * @hsotg: The device state:
3517 * This interrupt indicates one of the following conditions occurred while
3518 * transmitting an ISOC transaction.
3519 * - Corrupted OUT Token for ISOC EP.
3520 * - Packet not complete in FIFO.
3522 * The following actions will be taken:
3523 * - Determine the EP
3524 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3526 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3531 struct dwc2_hsotg_ep *hs_ep;
3534 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3536 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3537 hs_ep = hsotg->eps_out[idx];
3538 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3539 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous &&
3540 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3541 /* Unmask GOUTNAKEFF interrupt */
3542 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3543 gintmsk |= GINTSTS_GOUTNAKEFF;
3544 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3546 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3547 if (!(gintsts & GINTSTS_GOUTNAKEFF))
3548 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3552 /* Clear interrupt */
3553 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
3557 * dwc2_hsotg_irq - handle device interrupt
3558 * @irq: The IRQ number triggered
3559 * @pw: The pw value when registered the handler.
3561 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3563 struct dwc2_hsotg *hsotg = pw;
3564 int retry_count = 8;
3568 if (!dwc2_is_device_mode(hsotg))
3571 spin_lock(&hsotg->lock);
3573 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
3574 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3576 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3577 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3581 if (gintsts & GINTSTS_RESETDET) {
3582 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3584 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
3586 /* This event must be used only if controller is suspended */
3587 if (hsotg->lx_state == DWC2_L2) {
3588 dwc2_exit_hibernation(hsotg, true);
3589 hsotg->lx_state = DWC2_L0;
3593 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3594 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
3595 u32 connected = hsotg->connected;
3597 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3598 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3599 dwc2_readl(hsotg->regs + GNPTXSTS));
3601 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
3603 /* Report disconnection if it is not already done. */
3604 dwc2_hsotg_disconnect(hsotg);
3606 /* Reset device address to zero */
3607 __bic32(hsotg->regs + DCFG, DCFG_DEVADDR_MASK);
3609 if (usb_status & GOTGCTL_BSESVLD && connected)
3610 dwc2_hsotg_core_init_disconnected(hsotg, true);
3613 if (gintsts & GINTSTS_ENUMDONE) {
3614 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
3616 dwc2_hsotg_irq_enumdone(hsotg);
3619 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3620 u32 daint = dwc2_readl(hsotg->regs + DAINT);
3621 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3622 u32 daint_out, daint_in;
3626 daint_out = daint >> DAINT_OUTEP_SHIFT;
3627 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3629 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3631 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3632 ep++, daint_out >>= 1) {
3634 dwc2_hsotg_epint(hsotg, ep, 0);
3637 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3638 ep++, daint_in >>= 1) {
3640 dwc2_hsotg_epint(hsotg, ep, 1);
3644 /* check both FIFOs */
3646 if (gintsts & GINTSTS_NPTXFEMP) {
3647 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3650 * Disable the interrupt to stop it happening again
3651 * unless one of these endpoint routines decides that
3652 * it needs re-enabling
3655 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3656 dwc2_hsotg_irq_fifoempty(hsotg, false);
3659 if (gintsts & GINTSTS_PTXFEMP) {
3660 dev_dbg(hsotg->dev, "PTxFEmp\n");
3662 /* See note in GINTSTS_NPTxFEmp */
3664 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3665 dwc2_hsotg_irq_fifoempty(hsotg, true);
3668 if (gintsts & GINTSTS_RXFLVL) {
3670 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3671 * we need to retry dwc2_hsotg_handle_rx if this is still
3675 dwc2_hsotg_handle_rx(hsotg);
3678 if (gintsts & GINTSTS_ERLYSUSP) {
3679 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3680 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
3684 * these next two seem to crop-up occasionally causing the core
3685 * to shutdown the USB transfer, so try clearing them and logging
3689 if (gintsts & GINTSTS_GOUTNAKEFF) {
3693 struct dwc2_hsotg_ep *hs_ep;
3695 /* Mask this interrupt */
3696 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3697 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3698 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3700 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3701 for (idx = 1; idx <= hsotg->num_of_eps; idx++) {
3702 hs_ep = hsotg->eps_out[idx];
3703 epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx));
3705 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3706 epctrl |= DXEPCTL_SNAK;
3707 epctrl |= DXEPCTL_EPDIS;
3708 dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx));
3712 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3715 if (gintsts & GINTSTS_GINNAKEFF) {
3716 dev_info(hsotg->dev, "GINNakEff triggered\n");
3718 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3720 dwc2_hsotg_dump(hsotg);
3723 if (gintsts & GINTSTS_INCOMPL_SOIN)
3724 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3726 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3727 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3730 * if we've had fifo events, we should try and go around the
3731 * loop again to see if there's any point in returning yet.
3734 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3737 spin_unlock(&hsotg->lock);
3742 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
3743 u32 bit, u32 timeout)
3747 for (i = 0; i < timeout; i++) {
3748 if (dwc2_readl(hs_otg->regs + reg) & bit)
3756 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3757 struct dwc2_hsotg_ep *hs_ep)
3762 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3763 DOEPCTL(hs_ep->index);
3764 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3765 DOEPINT(hs_ep->index);
3767 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3770 if (hs_ep->dir_in) {
3771 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3772 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
3773 /* Wait for Nak effect */
3774 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3775 DXEPINT_INEPNAKEFF, 100))
3776 dev_warn(hsotg->dev,
3777 "%s: timeout DIEPINT.NAKEFF\n",
3780 __orr32(hsotg->regs + DCTL, DCTL_SGNPINNAK);
3781 /* Wait for Nak effect */
3782 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3783 GINTSTS_GINNAKEFF, 100))
3784 dev_warn(hsotg->dev,
3785 "%s: timeout GINTSTS.GINNAKEFF\n",
3789 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
3790 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3792 /* Wait for global nak to take effect */
3793 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3794 GINTSTS_GOUTNAKEFF, 100))
3795 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3800 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3802 /* Wait for ep to be disabled */
3803 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3804 dev_warn(hsotg->dev,
3805 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3807 /* Clear EPDISBLD interrupt */
3808 __orr32(hsotg->regs + epint_reg, DXEPINT_EPDISBLD);
3810 if (hs_ep->dir_in) {
3811 unsigned short fifo_index;
3813 if (hsotg->dedicated_fifos || hs_ep->periodic)
3814 fifo_index = hs_ep->fifo_index;
3819 dwc2_flush_tx_fifo(hsotg, fifo_index);
3821 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3822 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3823 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
3826 /* Remove global NAKs */
3827 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
3832 * dwc2_hsotg_ep_enable - enable the given endpoint
3833 * @ep: The USB endpint to configure
3834 * @desc: The USB endpoint descriptor to configure with.
3836 * This is called from the USB gadget code's usb_ep_enable().
3838 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
3839 const struct usb_endpoint_descriptor *desc)
3841 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3842 struct dwc2_hsotg *hsotg = hs_ep->parent;
3843 unsigned long flags;
3844 unsigned int index = hs_ep->index;
3850 unsigned int dir_in;
3851 unsigned int i, val, size;
3855 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3856 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
3857 desc->wMaxPacketSize, desc->bInterval);
3859 /* not to be called for EP0 */
3861 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
3865 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
3866 if (dir_in != hs_ep->dir_in) {
3867 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
3871 mps = usb_endpoint_maxp(desc);
3872 mc = usb_endpoint_maxp_mult(desc);
3874 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3876 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
3877 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
3879 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3880 __func__, epctrl, epctrl_reg);
3882 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3883 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
3884 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
3885 MAX_DMA_DESC_NUM_GENERIC *
3886 sizeof(struct dwc2_dma_desc),
3887 &hs_ep->desc_list_dma, GFP_ATOMIC);
3888 if (!hs_ep->desc_list) {
3894 spin_lock_irqsave(&hsotg->lock, flags);
3896 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
3897 epctrl |= DXEPCTL_MPS(mps);
3900 * mark the endpoint as active, otherwise the core may ignore
3901 * transactions entirely for this endpoint
3903 epctrl |= DXEPCTL_USBACTEP;
3905 /* update the endpoint state */
3906 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
3908 /* default, set to non-periodic */
3909 hs_ep->isochronous = 0;
3910 hs_ep->periodic = 0;
3912 hs_ep->interval = desc->bInterval;
3914 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
3915 case USB_ENDPOINT_XFER_ISOC:
3916 epctrl |= DXEPCTL_EPTYPE_ISO;
3917 epctrl |= DXEPCTL_SETEVENFR;
3918 hs_ep->isochronous = 1;
3919 hs_ep->interval = 1 << (desc->bInterval - 1);
3920 hs_ep->target_frame = TARGET_FRAME_INITIAL;
3921 hs_ep->isoc_chain_num = 0;
3922 hs_ep->next_desc = 0;
3924 hs_ep->periodic = 1;
3925 mask = dwc2_readl(hsotg->regs + DIEPMSK);
3926 mask |= DIEPMSK_NAKMSK;
3927 dwc2_writel(mask, hsotg->regs + DIEPMSK);
3929 mask = dwc2_readl(hsotg->regs + DOEPMSK);
3930 mask |= DOEPMSK_OUTTKNEPDISMSK;
3931 dwc2_writel(mask, hsotg->regs + DOEPMSK);
3935 case USB_ENDPOINT_XFER_BULK:
3936 epctrl |= DXEPCTL_EPTYPE_BULK;
3939 case USB_ENDPOINT_XFER_INT:
3941 hs_ep->periodic = 1;
3943 if (hsotg->gadget.speed == USB_SPEED_HIGH)
3944 hs_ep->interval = 1 << (desc->bInterval - 1);
3946 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
3949 case USB_ENDPOINT_XFER_CONTROL:
3950 epctrl |= DXEPCTL_EPTYPE_CONTROL;
3955 * if the hardware has dedicated fifos, we must give each IN EP
3956 * a unique tx-fifo even if it is non-periodic.
3958 if (dir_in && hsotg->dedicated_fifos) {
3959 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
3961 u32 fifo_size = UINT_MAX;
3963 size = hs_ep->ep.maxpacket * hs_ep->mc;
3964 for (i = 1; i <= fifo_count; ++i) {
3965 if (hsotg->fifo_map & (1 << i))
3967 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
3968 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
3971 /* Search for smallest acceptable fifo */
3972 if (val < fifo_size) {
3979 "%s: No suitable fifo found\n", __func__);
3983 hsotg->fifo_map |= 1 << fifo_index;
3984 epctrl |= DXEPCTL_TXFNUM(fifo_index);
3985 hs_ep->fifo_index = fifo_index;
3986 hs_ep->fifo_size = fifo_size;
3989 /* for non control endpoints, set PID to D0 */
3990 if (index && !hs_ep->isochronous)
3991 epctrl |= DXEPCTL_SETD0PID;
3993 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
3996 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
3997 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
3998 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
4000 /* enable the endpoint interrupt */
4001 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4004 spin_unlock_irqrestore(&hsotg->lock, flags);
4007 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4008 dmam_free_coherent(hsotg->dev, MAX_DMA_DESC_NUM_GENERIC *
4009 sizeof(struct dwc2_dma_desc),
4010 hs_ep->desc_list, hs_ep->desc_list_dma);
4011 hs_ep->desc_list = NULL;
4018 * dwc2_hsotg_ep_disable - disable given endpoint
4019 * @ep: The endpoint to disable.
4021 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4023 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4024 struct dwc2_hsotg *hsotg = hs_ep->parent;
4025 int dir_in = hs_ep->dir_in;
4026 int index = hs_ep->index;
4027 unsigned long flags;
4031 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4033 if (ep == &hsotg->eps_out[0]->ep) {
4034 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4038 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4040 spin_lock_irqsave(&hsotg->lock, flags);
4042 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
4044 if (ctrl & DXEPCTL_EPENA)
4045 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4047 ctrl &= ~DXEPCTL_EPENA;
4048 ctrl &= ~DXEPCTL_USBACTEP;
4049 ctrl |= DXEPCTL_SNAK;
4051 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4052 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
4054 /* disable endpoint interrupts */
4055 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4057 /* terminate all requests with shutdown */
4058 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4060 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4061 hs_ep->fifo_index = 0;
4062 hs_ep->fifo_size = 0;
4064 spin_unlock_irqrestore(&hsotg->lock, flags);
4069 * on_list - check request is on the given endpoint
4070 * @ep: The endpoint to check.
4071 * @test: The request to test if it is on the endpoint.
4073 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4075 struct dwc2_hsotg_req *req, *treq;
4077 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4086 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4087 * @ep: The endpoint to dequeue.
4088 * @req: The request to be removed from a queue.
4090 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4092 struct dwc2_hsotg_req *hs_req = our_req(req);
4093 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4094 struct dwc2_hsotg *hs = hs_ep->parent;
4095 unsigned long flags;
4097 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4099 spin_lock_irqsave(&hs->lock, flags);
4101 if (!on_list(hs_ep, hs_req)) {
4102 spin_unlock_irqrestore(&hs->lock, flags);
4106 /* Dequeue already started request */
4107 if (req == &hs_ep->req->req)
4108 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4110 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4111 spin_unlock_irqrestore(&hs->lock, flags);
4117 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4118 * @ep: The endpoint to set halt.
4119 * @value: Set or unset the halt.
4120 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4121 * the endpoint is busy processing requests.
4123 * We need to stall the endpoint immediately if request comes from set_feature
4124 * protocol command handler.
4126 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4128 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4129 struct dwc2_hsotg *hs = hs_ep->parent;
4130 int index = hs_ep->index;
4135 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4139 dwc2_hsotg_stall_ep0(hs);
4142 "%s: can't clear halt on ep0\n", __func__);
4146 if (hs_ep->isochronous) {
4147 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4151 if (!now && value && !list_empty(&hs_ep->queue)) {
4152 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4157 if (hs_ep->dir_in) {
4158 epreg = DIEPCTL(index);
4159 epctl = dwc2_readl(hs->regs + epreg);
4162 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4163 if (epctl & DXEPCTL_EPENA)
4164 epctl |= DXEPCTL_EPDIS;
4166 epctl &= ~DXEPCTL_STALL;
4167 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4168 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4169 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4170 epctl |= DXEPCTL_SETD0PID;
4172 dwc2_writel(epctl, hs->regs + epreg);
4174 epreg = DOEPCTL(index);
4175 epctl = dwc2_readl(hs->regs + epreg);
4178 epctl |= DXEPCTL_STALL;
4180 epctl &= ~DXEPCTL_STALL;
4181 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4182 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4183 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4184 epctl |= DXEPCTL_SETD0PID;
4186 dwc2_writel(epctl, hs->regs + epreg);
4189 hs_ep->halted = value;
4195 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4196 * @ep: The endpoint to set halt.
4197 * @value: Set or unset the halt.
4199 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4201 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4202 struct dwc2_hsotg *hs = hs_ep->parent;
4203 unsigned long flags = 0;
4206 spin_lock_irqsave(&hs->lock, flags);
4207 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4208 spin_unlock_irqrestore(&hs->lock, flags);
4213 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4214 .enable = dwc2_hsotg_ep_enable,
4215 .disable = dwc2_hsotg_ep_disable,
4216 .alloc_request = dwc2_hsotg_ep_alloc_request,
4217 .free_request = dwc2_hsotg_ep_free_request,
4218 .queue = dwc2_hsotg_ep_queue_lock,
4219 .dequeue = dwc2_hsotg_ep_dequeue,
4220 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4221 /* note, don't believe we have any call for the fifo routines */
4225 * dwc2_hsotg_init - initialize the usb core
4226 * @hsotg: The driver state
4228 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4232 /* unmask subset of endpoint interrupts */
4234 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4235 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4236 hsotg->regs + DIEPMSK);
4238 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4239 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4240 hsotg->regs + DOEPMSK);
4242 dwc2_writel(0, hsotg->regs + DAINTMSK);
4244 /* Be in disconnected state until gadget is registered */
4245 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
4249 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4250 dwc2_readl(hsotg->regs + GRXFSIZ),
4251 dwc2_readl(hsotg->regs + GNPTXFSIZ));
4253 dwc2_hsotg_init_fifo(hsotg);
4255 /* keep other bits untouched (so e.g. forced modes are not lost) */
4256 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
4257 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
4258 GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK);
4260 /* set the PLL on, remove the HNP/SRP and set the PHY */
4261 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
4262 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
4263 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
4264 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
4266 if (using_dma(hsotg))
4267 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
4271 * dwc2_hsotg_udc_start - prepare the udc for work
4272 * @gadget: The usb gadget state
4273 * @driver: The usb gadget driver
4275 * Perform initialization to prepare udc device and driver
4278 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4279 struct usb_gadget_driver *driver)
4281 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4282 unsigned long flags;
4286 pr_err("%s: called with no device\n", __func__);
4291 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4295 if (driver->max_speed < USB_SPEED_FULL)
4296 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4298 if (!driver->setup) {
4299 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4303 WARN_ON(hsotg->driver);
4305 driver->driver.bus = NULL;
4306 hsotg->driver = driver;
4307 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4308 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4310 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4311 ret = dwc2_lowlevel_hw_enable(hsotg);
4316 if (!IS_ERR_OR_NULL(hsotg->uphy))
4317 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4319 spin_lock_irqsave(&hsotg->lock, flags);
4320 if (dwc2_hw_is_device(hsotg)) {
4321 dwc2_hsotg_init(hsotg);
4322 dwc2_hsotg_core_init_disconnected(hsotg, false);
4326 spin_unlock_irqrestore(&hsotg->lock, flags);
4328 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4333 hsotg->driver = NULL;
4338 * dwc2_hsotg_udc_stop - stop the udc
4339 * @gadget: The usb gadget state
4340 * @driver: The usb gadget driver
4342 * Stop udc hw block and stay tunned for future transmissions
4344 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4346 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4347 unsigned long flags = 0;
4353 /* all endpoints should be shutdown */
4354 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4355 if (hsotg->eps_in[ep])
4356 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4357 if (hsotg->eps_out[ep])
4358 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4361 spin_lock_irqsave(&hsotg->lock, flags);
4363 hsotg->driver = NULL;
4364 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4367 spin_unlock_irqrestore(&hsotg->lock, flags);
4369 if (!IS_ERR_OR_NULL(hsotg->uphy))
4370 otg_set_peripheral(hsotg->uphy->otg, NULL);
4372 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4373 dwc2_lowlevel_hw_disable(hsotg);
4379 * dwc2_hsotg_gadget_getframe - read the frame number
4380 * @gadget: The usb gadget state
4382 * Read the {micro} frame number
4384 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4386 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4390 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4391 * @gadget: The usb gadget state
4392 * @is_on: Current state of the USB PHY
4394 * Connect/Disconnect the USB PHY pullup
4396 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4398 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4399 unsigned long flags = 0;
4401 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4404 /* Don't modify pullup state while in host mode */
4405 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4406 hsotg->enabled = is_on;
4410 spin_lock_irqsave(&hsotg->lock, flags);
4413 dwc2_hsotg_core_init_disconnected(hsotg, false);
4414 dwc2_hsotg_core_connect(hsotg);
4416 dwc2_hsotg_core_disconnect(hsotg);
4417 dwc2_hsotg_disconnect(hsotg);
4421 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4422 spin_unlock_irqrestore(&hsotg->lock, flags);
4427 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4429 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4430 unsigned long flags;
4432 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4433 spin_lock_irqsave(&hsotg->lock, flags);
4436 * If controller is hibernated, it must exit from hibernation
4437 * before being initialized / de-initialized
4439 if (hsotg->lx_state == DWC2_L2)
4440 dwc2_exit_hibernation(hsotg, false);
4443 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4445 dwc2_hsotg_core_init_disconnected(hsotg, false);
4447 dwc2_hsotg_core_connect(hsotg);
4449 dwc2_hsotg_core_disconnect(hsotg);
4450 dwc2_hsotg_disconnect(hsotg);
4453 spin_unlock_irqrestore(&hsotg->lock, flags);
4458 * dwc2_hsotg_vbus_draw - report bMaxPower field
4459 * @gadget: The usb gadget state
4460 * @mA: Amount of current
4462 * Report how much power the device may consume to the phy.
4464 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4466 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4468 if (IS_ERR_OR_NULL(hsotg->uphy))
4470 return usb_phy_set_power(hsotg->uphy, mA);
4473 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4474 .get_frame = dwc2_hsotg_gadget_getframe,
4475 .udc_start = dwc2_hsotg_udc_start,
4476 .udc_stop = dwc2_hsotg_udc_stop,
4477 .pullup = dwc2_hsotg_pullup,
4478 .vbus_session = dwc2_hsotg_vbus_session,
4479 .vbus_draw = dwc2_hsotg_vbus_draw,
4483 * dwc2_hsotg_initep - initialise a single endpoint
4484 * @hsotg: The device state.
4485 * @hs_ep: The endpoint to be initialised.
4486 * @epnum: The endpoint number
4488 * Initialise the given endpoint (as part of the probe and device state
4489 * creation) to give to the gadget driver. Setup the endpoint name, any
4490 * direction information and other state that may be required.
4492 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4493 struct dwc2_hsotg_ep *hs_ep,
4506 hs_ep->dir_in = dir_in;
4507 hs_ep->index = epnum;
4509 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4511 INIT_LIST_HEAD(&hs_ep->queue);
4512 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4514 /* add to the list of endpoints known by the gadget driver */
4516 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4518 hs_ep->parent = hsotg;
4519 hs_ep->ep.name = hs_ep->name;
4521 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4522 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4524 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4525 epnum ? 1024 : EP0_MPS_LIMIT);
4526 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4529 hs_ep->ep.caps.type_control = true;
4531 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4532 hs_ep->ep.caps.type_iso = true;
4533 hs_ep->ep.caps.type_bulk = true;
4535 hs_ep->ep.caps.type_int = true;
4539 hs_ep->ep.caps.dir_in = true;
4541 hs_ep->ep.caps.dir_out = true;
4544 * if we're using dma, we need to set the next-endpoint pointer
4545 * to be something valid.
4548 if (using_dma(hsotg)) {
4549 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4552 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
4554 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
4559 * dwc2_hsotg_hw_cfg - read HW configuration registers
4560 * @param: The device state
4562 * Read the USB core HW configuration registers
4564 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4570 /* check hardware configuration */
4572 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4575 hsotg->num_of_eps++;
4577 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4578 sizeof(struct dwc2_hsotg_ep),
4580 if (!hsotg->eps_in[0])
4582 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4583 hsotg->eps_out[0] = hsotg->eps_in[0];
4585 cfg = hsotg->hw_params.dev_ep_dirs;
4586 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4588 /* Direction in or both */
4589 if (!(ep_type & 2)) {
4590 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4591 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4592 if (!hsotg->eps_in[i])
4595 /* Direction out or both */
4596 if (!(ep_type & 1)) {
4597 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4598 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4599 if (!hsotg->eps_out[i])
4604 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4605 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4607 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4609 hsotg->dedicated_fifos ? "dedicated" : "shared",
4615 * dwc2_hsotg_dump - dump state of the udc
4616 * @param: The device state
4618 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4621 struct device *dev = hsotg->dev;
4622 void __iomem *regs = hsotg->regs;
4626 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4627 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
4628 dwc2_readl(regs + DIEPMSK));
4630 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4631 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
4633 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4634 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
4636 /* show periodic fifo settings */
4638 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4639 val = dwc2_readl(regs + DPTXFSIZN(idx));
4640 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4641 val >> FIFOSIZE_DEPTH_SHIFT,
4642 val & FIFOSIZE_STARTADDR_MASK);
4645 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4647 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4648 dwc2_readl(regs + DIEPCTL(idx)),
4649 dwc2_readl(regs + DIEPTSIZ(idx)),
4650 dwc2_readl(regs + DIEPDMA(idx)));
4652 val = dwc2_readl(regs + DOEPCTL(idx));
4654 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4655 idx, dwc2_readl(regs + DOEPCTL(idx)),
4656 dwc2_readl(regs + DOEPTSIZ(idx)),
4657 dwc2_readl(regs + DOEPDMA(idx)));
4660 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4661 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
4666 * dwc2_gadget_init - init function for gadget
4667 * @dwc2: The data structure for the DWC2 driver.
4668 * @irq: The IRQ number for the controller.
4670 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
4672 struct device *dev = hsotg->dev;
4676 /* Dump fifo information */
4677 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4678 hsotg->params.g_np_tx_fifo_size);
4679 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4681 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4682 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4683 hsotg->gadget.name = dev_name(dev);
4684 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4685 hsotg->gadget.is_otg = 1;
4686 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4687 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4689 ret = dwc2_hsotg_hw_cfg(hsotg);
4691 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4695 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4696 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4697 if (!hsotg->ctrl_buff)
4700 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4701 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4702 if (!hsotg->ep0_buff)
4705 if (using_desc_dma(hsotg)) {
4706 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4711 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
4712 dev_name(hsotg->dev), hsotg);
4714 dev_err(dev, "cannot claim IRQ for gadget\n");
4718 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4720 if (hsotg->num_of_eps == 0) {
4721 dev_err(dev, "wrong number of EPs (zero)\n");
4725 /* setup endpoint information */
4727 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4728 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4730 /* allocate EP0 request */
4732 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4734 if (!hsotg->ctrl_req) {
4735 dev_err(dev, "failed to allocate ctrl req\n");
4739 /* initialise the endpoints now the core has been initialised */
4740 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4741 if (hsotg->eps_in[epnum])
4742 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4744 if (hsotg->eps_out[epnum])
4745 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
4749 dwc2_hsotg_dump(hsotg);
4755 * dwc2_hsotg_remove - remove function for hsotg driver
4756 * @pdev: The platform information for the driver
4758 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
4760 usb_del_gadget_udc(&hsotg->gadget);
4761 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
4766 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
4768 unsigned long flags;
4770 if (hsotg->lx_state != DWC2_L0)
4773 if (hsotg->driver) {
4776 dev_info(hsotg->dev, "suspending usb gadget %s\n",
4777 hsotg->driver->driver.name);
4779 spin_lock_irqsave(&hsotg->lock, flags);
4781 dwc2_hsotg_core_disconnect(hsotg);
4782 dwc2_hsotg_disconnect(hsotg);
4783 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4784 spin_unlock_irqrestore(&hsotg->lock, flags);
4786 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
4787 if (hsotg->eps_in[ep])
4788 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
4789 if (hsotg->eps_out[ep])
4790 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
4797 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
4799 unsigned long flags;
4801 if (hsotg->lx_state == DWC2_L2)
4804 if (hsotg->driver) {
4805 dev_info(hsotg->dev, "resuming usb gadget %s\n",
4806 hsotg->driver->driver.name);
4808 spin_lock_irqsave(&hsotg->lock, flags);
4809 dwc2_hsotg_core_init_disconnected(hsotg, false);
4811 dwc2_hsotg_core_connect(hsotg);
4812 spin_unlock_irqrestore(&hsotg->lock, flags);
4819 * dwc2_backup_device_registers() - Backup controller device registers.
4820 * When suspending usb bus, registers needs to be backuped
4821 * if controller power is disabled once suspended.
4823 * @hsotg: Programming view of the DWC_otg controller
4825 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
4827 struct dwc2_dregs_backup *dr;
4830 dev_dbg(hsotg->dev, "%s\n", __func__);
4832 /* Backup dev regs */
4833 dr = &hsotg->dr_backup;
4835 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
4836 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
4837 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
4838 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
4839 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
4841 for (i = 0; i < hsotg->num_of_eps; i++) {
4843 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
4845 /* Ensure DATA PID is correctly configured */
4846 if (dr->diepctl[i] & DXEPCTL_DPID)
4847 dr->diepctl[i] |= DXEPCTL_SETD1PID;
4849 dr->diepctl[i] |= DXEPCTL_SETD0PID;
4851 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
4852 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
4854 /* Backup OUT EPs */
4855 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
4857 /* Ensure DATA PID is correctly configured */
4858 if (dr->doepctl[i] & DXEPCTL_DPID)
4859 dr->doepctl[i] |= DXEPCTL_SETD1PID;
4861 dr->doepctl[i] |= DXEPCTL_SETD0PID;
4863 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
4864 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
4871 * dwc2_restore_device_registers() - Restore controller device registers.
4872 * When resuming usb bus, device registers needs to be restored
4873 * if controller power were disabled.
4875 * @hsotg: Programming view of the DWC_otg controller
4877 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
4879 struct dwc2_dregs_backup *dr;
4883 dev_dbg(hsotg->dev, "%s\n", __func__);
4885 /* Restore dev regs */
4886 dr = &hsotg->dr_backup;
4888 dev_err(hsotg->dev, "%s: no device registers to restore\n",
4894 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
4895 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
4896 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
4897 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
4898 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
4900 for (i = 0; i < hsotg->num_of_eps; i++) {
4901 /* Restore IN EPs */
4902 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
4903 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
4904 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
4906 /* Restore OUT EPs */
4907 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
4908 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
4909 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
4912 /* Set the Power-On Programming done bit */
4913 dctl = dwc2_readl(hsotg->regs + DCTL);
4914 dctl |= DCTL_PWRONPRGDONE;
4915 dwc2_writel(dctl, hsotg->regs + DCTL);