1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of_platform.h>
27 #include <linux/usb/ch9.h>
28 #include <linux/usb/gadget.h>
29 #include <linux/usb/phy.h>
30 #include <linux/usb/composite.h>
36 /* conversion functions */
37 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
39 return container_of(req, struct dwc2_hsotg_req, req);
42 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
44 return container_of(ep, struct dwc2_hsotg_ep, ep);
47 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
49 return container_of(gadget, struct dwc2_hsotg, gadget);
52 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
54 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
57 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
59 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
62 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
63 u32 ep_index, u32 dir_in)
66 return hsotg->eps_in[ep_index];
68 return hsotg->eps_out[ep_index];
71 /* forward declaration of functions */
72 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
75 * using_dma - return the DMA status of the driver.
76 * @hsotg: The driver state.
78 * Return true if we're using DMA.
80 * Currently, we have the DMA support code worked into everywhere
81 * that needs it, but the AMBA DMA implementation in the hardware can
82 * only DMA from 32bit aligned addresses. This means that gadgets such
83 * as the CDC Ethernet cannot work as they often pass packets which are
86 * Unfortunately the choice to use DMA or not is global to the controller
87 * and seems to be only settable when the controller is being put through
88 * a core reset. This means we either need to fix the gadgets to take
89 * account of DMA alignment, or add bounce buffers (yuerk).
91 * g_using_dma is set depending on dts flag.
93 static inline bool using_dma(struct dwc2_hsotg *hsotg)
95 return hsotg->params.g_dma;
99 * using_desc_dma - return the descriptor DMA status of the driver.
100 * @hsotg: The driver state.
102 * Return true if we're using descriptor DMA.
104 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
106 return hsotg->params.g_dma_desc;
110 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
111 * @hs_ep: The endpoint
113 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
114 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
116 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
118 struct dwc2_hsotg *hsotg = hs_ep->parent;
119 u16 limit = DSTS_SOFFN_LIMIT;
121 if (hsotg->gadget.speed != USB_SPEED_HIGH)
124 hs_ep->target_frame += hs_ep->interval;
125 if (hs_ep->target_frame > limit) {
126 hs_ep->frame_overrun = true;
127 hs_ep->target_frame &= limit;
129 hs_ep->frame_overrun = false;
134 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
136 * @hs_ep: The endpoint.
138 * This function used in service interval based scheduling flow to calculate
139 * descriptor frame number filed value. For service interval mode frame
140 * number in descriptor should point to last (u)frame in the interval.
143 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
145 struct dwc2_hsotg *hsotg = hs_ep->parent;
146 u16 limit = DSTS_SOFFN_LIMIT;
148 if (hsotg->gadget.speed != USB_SPEED_HIGH)
151 if (hs_ep->target_frame)
152 hs_ep->target_frame -= 1;
154 hs_ep->target_frame = limit;
158 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
159 * @hsotg: The device state
160 * @ints: A bitmask of the interrupts to enable
162 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
164 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
167 new_gsintmsk = gsintmsk | ints;
169 if (new_gsintmsk != gsintmsk) {
170 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
171 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
176 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
177 * @hsotg: The device state
178 * @ints: A bitmask of the interrupts to enable
180 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
182 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
185 new_gsintmsk = gsintmsk & ~ints;
187 if (new_gsintmsk != gsintmsk)
188 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
192 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
193 * @hsotg: The device state
194 * @ep: The endpoint index
195 * @dir_in: True if direction is in.
196 * @en: The enable value, true to enable
198 * Set or clear the mask for an individual endpoint's interrupt
201 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
202 unsigned int ep, unsigned int dir_in,
212 local_irq_save(flags);
213 daint = dwc2_readl(hsotg, DAINTMSK);
218 dwc2_writel(hsotg, daint, DAINTMSK);
219 local_irq_restore(flags);
223 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
225 * @hsotg: Programming view of the DWC_otg controller
227 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
229 if (hsotg->hw_params.en_multiple_tx_fifo)
230 /* In dedicated FIFO mode we need count of IN EPs */
231 return hsotg->hw_params.num_dev_in_eps;
233 /* In shared FIFO mode we need count of Periodic IN EPs */
234 return hsotg->hw_params.num_dev_perio_in_ep;
238 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
239 * device mode TX FIFOs
241 * @hsotg: Programming view of the DWC_otg controller
243 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
249 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
250 hsotg->params.g_np_tx_fifo_size);
252 /* Get Endpoint Info Control block size in DWORDs. */
253 tx_addr_max = hsotg->hw_params.total_fifo_size;
255 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
256 if (tx_addr_max <= addr)
259 return tx_addr_max - addr;
263 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
265 * @hsotg: Programming view of the DWC_otg controller
268 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
273 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
274 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
275 gintsts2 &= gintmsk2;
277 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
278 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
279 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
280 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
285 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
288 * @hsotg: Programming view of the DWC_otg controller
290 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
295 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
297 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
300 return tx_fifo_depth;
302 return tx_fifo_depth / tx_fifo_count;
306 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
307 * @hsotg: The device instance.
309 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
316 u32 *txfsz = hsotg->params.g_tx_fifo_size;
318 /* Reset fifo map if not correctly cleared during previous session */
319 WARN_ON(hsotg->fifo_map);
322 /* set RX/NPTX FIFO sizes */
323 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
324 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
325 FIFOSIZE_STARTADDR_SHIFT) |
326 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
330 * arange all the rest of the TX FIFOs, as some versions of this
331 * block have overlapping default addresses. This also ensures
332 * that if the settings have been changed, then they are set to
336 /* start at the end of the GNPTXFSIZ, rounded up */
337 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
340 * Configure fifos sizes from provided configuration and assign
341 * them to endpoints dynamically according to maxpacket size value of
344 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
348 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
349 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
350 "insufficient fifo memory");
353 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
354 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
357 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
358 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
361 * according to p428 of the design guide, we need to ensure that
362 * all fifos are flushed before continuing
365 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
366 GRSTCTL_RXFFLSH, GRSTCTL);
368 /* wait until the fifos are both flushed */
371 val = dwc2_readl(hsotg, GRSTCTL);
373 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
376 if (--timeout == 0) {
378 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
386 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
390 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
391 * @ep: USB endpoint to allocate request for.
392 * @flags: Allocation flags
394 * Allocate a new USB request structure appropriate for the specified endpoint
396 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
399 struct dwc2_hsotg_req *req;
401 req = kzalloc(sizeof(*req), flags);
405 INIT_LIST_HEAD(&req->queue);
411 * is_ep_periodic - return true if the endpoint is in periodic mode.
412 * @hs_ep: The endpoint to query.
414 * Returns true if the endpoint is in periodic mode, meaning it is being
415 * used for an Interrupt or ISO transfer.
417 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
419 return hs_ep->periodic;
423 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
424 * @hsotg: The device state.
425 * @hs_ep: The endpoint for the request
426 * @hs_req: The request being processed.
428 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
429 * of a request to ensure the buffer is ready for access by the caller.
431 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
432 struct dwc2_hsotg_ep *hs_ep,
433 struct dwc2_hsotg_req *hs_req)
435 struct usb_request *req = &hs_req->req;
437 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
441 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
442 * for Control endpoint
443 * @hsotg: The device state.
445 * This function will allocate 4 descriptor chains for EP 0: 2 for
446 * Setup stage, per one for IN and OUT data/status transactions.
448 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
450 hsotg->setup_desc[0] =
451 dmam_alloc_coherent(hsotg->dev,
452 sizeof(struct dwc2_dma_desc),
453 &hsotg->setup_desc_dma[0],
455 if (!hsotg->setup_desc[0])
458 hsotg->setup_desc[1] =
459 dmam_alloc_coherent(hsotg->dev,
460 sizeof(struct dwc2_dma_desc),
461 &hsotg->setup_desc_dma[1],
463 if (!hsotg->setup_desc[1])
466 hsotg->ctrl_in_desc =
467 dmam_alloc_coherent(hsotg->dev,
468 sizeof(struct dwc2_dma_desc),
469 &hsotg->ctrl_in_desc_dma,
471 if (!hsotg->ctrl_in_desc)
474 hsotg->ctrl_out_desc =
475 dmam_alloc_coherent(hsotg->dev,
476 sizeof(struct dwc2_dma_desc),
477 &hsotg->ctrl_out_desc_dma,
479 if (!hsotg->ctrl_out_desc)
489 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
490 * @hsotg: The controller state.
491 * @hs_ep: The endpoint we're going to write for.
492 * @hs_req: The request to write data for.
494 * This is called when the TxFIFO has some space in it to hold a new
495 * transmission and we have something to give it. The actual setup of
496 * the data size is done elsewhere, so all we have to do is to actually
499 * The return value is zero if there is more space (or nothing was done)
500 * otherwise -ENOSPC is returned if the FIFO space was used up.
502 * This routine is only needed for PIO
504 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
505 struct dwc2_hsotg_ep *hs_ep,
506 struct dwc2_hsotg_req *hs_req)
508 bool periodic = is_ep_periodic(hs_ep);
509 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
510 int buf_pos = hs_req->req.actual;
511 int to_write = hs_ep->size_loaded;
517 to_write -= (buf_pos - hs_ep->last_load);
519 /* if there's nothing to write, get out early */
523 if (periodic && !hsotg->dedicated_fifos) {
524 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
529 * work out how much data was loaded so we can calculate
530 * how much data is left in the fifo.
533 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
536 * if shared fifo, we cannot write anything until the
537 * previous data has been completely sent.
539 if (hs_ep->fifo_load != 0) {
540 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
544 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
546 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
548 /* how much of the data has moved */
549 size_done = hs_ep->size_loaded - size_left;
551 /* how much data is left in the fifo */
552 can_write = hs_ep->fifo_load - size_done;
553 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
554 __func__, can_write);
556 can_write = hs_ep->fifo_size - can_write;
557 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
558 __func__, can_write);
560 if (can_write <= 0) {
561 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
564 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
565 can_write = dwc2_readl(hsotg,
566 DTXFSTS(hs_ep->fifo_index));
571 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
573 "%s: no queue slots available (0x%08x)\n",
576 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
580 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
581 can_write *= 4; /* fifo size is in 32bit quantities. */
584 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
586 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
587 __func__, gnptxsts, can_write, to_write, max_transfer);
590 * limit to 512 bytes of data, it seems at least on the non-periodic
591 * FIFO, requests of >512 cause the endpoint to get stuck with a
592 * fragment of the end of the transfer in it.
594 if (can_write > 512 && !periodic)
598 * limit the write to one max-packet size worth of data, but allow
599 * the transfer to return that it did not run out of fifo space
602 if (to_write > max_transfer) {
603 to_write = max_transfer;
605 /* it's needed only when we do not use dedicated fifos */
606 if (!hsotg->dedicated_fifos)
607 dwc2_hsotg_en_gsint(hsotg,
608 periodic ? GINTSTS_PTXFEMP :
612 /* see if we can write data */
614 if (to_write > can_write) {
615 to_write = can_write;
616 pkt_round = to_write % max_transfer;
619 * Round the write down to an
620 * exact number of packets.
622 * Note, we do not currently check to see if we can ever
623 * write a full packet or not to the FIFO.
627 to_write -= pkt_round;
630 * enable correct FIFO interrupt to alert us when there
634 /* it's needed only when we do not use dedicated fifos */
635 if (!hsotg->dedicated_fifos)
636 dwc2_hsotg_en_gsint(hsotg,
637 periodic ? GINTSTS_PTXFEMP :
641 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
642 to_write, hs_req->req.length, can_write, buf_pos);
647 hs_req->req.actual = buf_pos + to_write;
648 hs_ep->total_data += to_write;
651 hs_ep->fifo_load += to_write;
653 to_write = DIV_ROUND_UP(to_write, 4);
654 data = hs_req->req.buf + buf_pos;
656 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
658 return (to_write >= can_write) ? -ENOSPC : 0;
662 * get_ep_limit - get the maximum data legnth for this endpoint
663 * @hs_ep: The endpoint
665 * Return the maximum data that can be queued in one go on a given endpoint
666 * so that transfers that are too long can be split.
668 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
670 int index = hs_ep->index;
671 unsigned int maxsize;
675 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
676 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
680 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
685 /* we made the constant loading easier above by using +1 */
690 * constrain by packet count if maxpkts*pktsize is greater
691 * than the length register size.
694 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
695 maxsize = maxpkt * hs_ep->ep.maxpacket;
701 * dwc2_hsotg_read_frameno - read current frame number
702 * @hsotg: The device instance
704 * Return the current frame number
706 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
710 dsts = dwc2_readl(hsotg, DSTS);
711 dsts &= DSTS_SOFFN_MASK;
712 dsts >>= DSTS_SOFFN_SHIFT;
718 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
719 * DMA descriptor chain prepared for specific endpoint
720 * @hs_ep: The endpoint
722 * Return the maximum data that can be queued in one go on a given endpoint
723 * depending on its descriptor chain capacity so that transfers that
724 * are too long can be split.
726 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
728 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
729 int is_isoc = hs_ep->isochronous;
730 unsigned int maxsize;
731 u32 mps = hs_ep->ep.maxpacket;
732 int dir_in = hs_ep->dir_in;
735 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
736 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
737 MAX_DMA_DESC_NUM_HS_ISOC;
739 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
741 /* Interrupt OUT EP with mps not multiple of 4 */
743 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
744 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
750 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
751 * @hs_ep: The endpoint
752 * @mask: RX/TX bytes mask to be defined
754 * Returns maximum data payload for one descriptor after analyzing endpoint
756 * DMA descriptor transfer bytes limit depends on EP type:
758 * Isochronous - descriptor rx/tx bytes bitfield limit,
759 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
760 * have concatenations from various descriptors within one packet.
761 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
762 * to a single descriptor.
764 * Selects corresponding mask for RX/TX bytes as well.
766 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
768 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
769 u32 mps = hs_ep->ep.maxpacket;
770 int dir_in = hs_ep->dir_in;
773 if (!hs_ep->index && !dir_in) {
775 *mask = DEV_DMA_NBYTES_MASK;
776 } else if (hs_ep->isochronous) {
778 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
779 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
781 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
782 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
785 desc_size = DEV_DMA_NBYTES_LIMIT;
786 *mask = DEV_DMA_NBYTES_MASK;
788 /* Round down desc_size to be mps multiple */
789 desc_size -= desc_size % mps;
792 /* Interrupt OUT EP with mps not multiple of 4 */
794 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
796 *mask = DEV_DMA_NBYTES_MASK;
802 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
803 struct dwc2_dma_desc **desc,
808 int dir_in = hs_ep->dir_in;
809 u32 mps = hs_ep->ep.maxpacket;
815 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
817 hs_ep->desc_count = (len / maxsize) +
818 ((len % maxsize) ? 1 : 0);
820 hs_ep->desc_count = 1;
822 for (i = 0; i < hs_ep->desc_count; ++i) {
824 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
825 << DEV_DMA_BUFF_STS_SHIFT);
828 if (!hs_ep->index && !dir_in)
829 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
832 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
833 (*desc)->buf = dma_buff + offset;
839 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
842 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
843 ((hs_ep->send_zlp && true_last) ?
847 len << DEV_DMA_NBYTES_SHIFT & mask;
848 (*desc)->buf = dma_buff + offset;
851 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
852 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
853 << DEV_DMA_BUFF_STS_SHIFT);
859 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
860 * @hs_ep: The endpoint
861 * @ureq: Request to transfer
862 * @offset: offset in bytes
863 * @len: Length of the transfer
865 * This function will iterate over descriptor chain and fill its entries
866 * with corresponding information based on transfer data.
868 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
872 struct usb_request *ureq = NULL;
873 struct dwc2_dma_desc *desc = hs_ep->desc_list;
874 struct scatterlist *sg;
879 ureq = &hs_ep->req->req;
881 /* non-DMA sg buffer */
882 if (!ureq || !ureq->num_sgs) {
883 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
884 dma_buff, len, true);
889 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
890 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
891 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
893 desc_count += hs_ep->desc_count;
896 hs_ep->desc_count = desc_count;
900 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
901 * @hs_ep: The isochronous endpoint.
902 * @dma_buff: usb requests dma buffer.
903 * @len: usb request transfer length.
905 * Fills next free descriptor with the data of the arrived usb request,
906 * frame info, sets Last and IOC bits increments next_desc. If filled
907 * descriptor is not the first one, removes L bit from the previous descriptor
910 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
911 dma_addr_t dma_buff, unsigned int len)
913 struct dwc2_dma_desc *desc;
914 struct dwc2_hsotg *hsotg = hs_ep->parent;
919 dwc2_gadget_get_desc_params(hs_ep, &mask);
921 index = hs_ep->next_desc;
922 desc = &hs_ep->desc_list[index];
924 /* Check if descriptor chain full */
925 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
926 DEV_DMA_BUFF_STS_HREADY) {
927 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
931 /* Clear L bit of previous desc if more than one entries in the chain */
932 if (hs_ep->next_desc)
933 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
935 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
936 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
939 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
941 desc->buf = dma_buff;
942 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
943 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
947 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
950 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
951 DEV_DMA_ISOC_PID_MASK) |
952 ((len % hs_ep->ep.maxpacket) ?
954 ((hs_ep->target_frame <<
955 DEV_DMA_ISOC_FRNUM_SHIFT) &
956 DEV_DMA_ISOC_FRNUM_MASK);
959 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
960 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
962 /* Increment frame number by interval for IN */
964 dwc2_gadget_incr_frame_num(hs_ep);
966 /* Update index of last configured entry in the chain */
968 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
969 hs_ep->next_desc = 0;
975 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
976 * @hs_ep: The isochronous endpoint.
978 * Prepare descriptor chain for isochronous endpoints. Afterwards
979 * write DMA address to HW and enable the endpoint.
981 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
983 struct dwc2_hsotg *hsotg = hs_ep->parent;
984 struct dwc2_hsotg_req *hs_req, *treq;
985 int index = hs_ep->index;
991 struct dwc2_dma_desc *desc;
993 if (list_empty(&hs_ep->queue)) {
994 hs_ep->target_frame = TARGET_FRAME_INITIAL;
995 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
999 /* Initialize descriptor chain by Host Busy status */
1000 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1001 desc = &hs_ep->desc_list[i];
1003 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1004 << DEV_DMA_BUFF_STS_SHIFT);
1007 hs_ep->next_desc = 0;
1008 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1009 dma_addr_t dma_addr = hs_req->req.dma;
1011 if (hs_req->req.num_sgs) {
1012 WARN_ON(hs_req->req.num_sgs > 1);
1013 dma_addr = sg_dma_address(hs_req->req.sg);
1015 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1016 hs_req->req.length);
1021 hs_ep->compl_desc = 0;
1022 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1023 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1025 /* write descriptor chain address to control register */
1026 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1028 ctrl = dwc2_readl(hsotg, depctl);
1029 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1030 dwc2_writel(hsotg, ctrl, depctl);
1033 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1034 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1035 struct dwc2_hsotg_ep *hs_ep,
1036 struct dwc2_hsotg_req *hs_req,
1040 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1041 * @hsotg: The controller state.
1042 * @hs_ep: The endpoint to process a request for
1043 * @hs_req: The request to start.
1044 * @continuing: True if we are doing more for the current request.
1046 * Start the given request running by setting the endpoint registers
1047 * appropriately, and writing any data to the FIFOs.
1049 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1050 struct dwc2_hsotg_ep *hs_ep,
1051 struct dwc2_hsotg_req *hs_req,
1054 struct usb_request *ureq = &hs_req->req;
1055 int index = hs_ep->index;
1056 int dir_in = hs_ep->dir_in;
1061 unsigned int length;
1062 unsigned int packets;
1063 unsigned int maxreq;
1064 unsigned int dma_reg;
1067 if (hs_ep->req && !continuing) {
1068 dev_err(hsotg->dev, "%s: active request\n", __func__);
1071 } else if (hs_ep->req != hs_req && continuing) {
1073 "%s: continue different req\n", __func__);
1079 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1080 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1081 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1083 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1084 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1085 hs_ep->dir_in ? "in" : "out");
1087 /* If endpoint is stalled, we will restart request later */
1088 ctrl = dwc2_readl(hsotg, epctrl_reg);
1090 if (index && ctrl & DXEPCTL_STALL) {
1091 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1095 length = ureq->length - ureq->actual;
1096 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1097 ureq->length, ureq->actual);
1099 if (!using_desc_dma(hsotg))
1100 maxreq = get_ep_limit(hs_ep);
1102 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1104 if (length > maxreq) {
1105 int round = maxreq % hs_ep->ep.maxpacket;
1107 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1108 __func__, length, maxreq, round);
1110 /* round down to multiple of packets */
1118 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1120 packets = 1; /* send one packet if length is zero. */
1122 if (dir_in && index != 0)
1123 if (hs_ep->isochronous)
1124 epsize = DXEPTSIZ_MC(packets);
1126 epsize = DXEPTSIZ_MC(1);
1131 * zero length packet should be programmed on its own and should not
1132 * be counted in DIEPTSIZ.PktCnt with other packets.
1134 if (dir_in && ureq->zero && !continuing) {
1135 /* Test if zlp is actually required. */
1136 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1137 !(ureq->length % hs_ep->ep.maxpacket))
1138 hs_ep->send_zlp = 1;
1141 epsize |= DXEPTSIZ_PKTCNT(packets);
1142 epsize |= DXEPTSIZ_XFERSIZE(length);
1144 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1145 __func__, packets, length, ureq->length, epsize, epsize_reg);
1147 /* store the request as the current one we're doing */
1148 hs_ep->req = hs_req;
1150 if (using_desc_dma(hsotg)) {
1152 u32 mps = hs_ep->ep.maxpacket;
1154 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1158 else if (length % mps)
1159 length += (mps - (length % mps));
1163 offset = ureq->actual;
1165 /* Fill DDMA chain entries */
1166 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1169 /* write descriptor chain address to control register */
1170 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1172 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1173 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1175 /* write size / packets */
1176 dwc2_writel(hsotg, epsize, epsize_reg);
1178 if (using_dma(hsotg) && !continuing && (length != 0)) {
1180 * write DMA address to control register, buffer
1181 * already synced by dwc2_hsotg_ep_queue().
1184 dwc2_writel(hsotg, ureq->dma, dma_reg);
1186 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1187 __func__, &ureq->dma, dma_reg);
1191 if (hs_ep->isochronous) {
1192 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1193 if (hs_ep->interval == 1) {
1194 if (hs_ep->target_frame & 0x1)
1195 ctrl |= DXEPCTL_SETODDFR;
1197 ctrl |= DXEPCTL_SETEVENFR;
1199 ctrl |= DXEPCTL_CNAK;
1201 hs_req->req.frame_number = hs_ep->target_frame;
1202 hs_req->req.actual = 0;
1203 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1208 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1210 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1212 /* For Setup request do not clear NAK */
1213 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1214 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1216 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1217 dwc2_writel(hsotg, ctrl, epctrl_reg);
1220 * set these, it seems that DMA support increments past the end
1221 * of the packet buffer so we need to calculate the length from
1224 hs_ep->size_loaded = length;
1225 hs_ep->last_load = ureq->actual;
1227 if (dir_in && !using_dma(hsotg)) {
1228 /* set these anyway, we may need them for non-periodic in */
1229 hs_ep->fifo_load = 0;
1231 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1235 * Note, trying to clear the NAK here causes problems with transmit
1236 * on the S3C6400 ending up with the TXFIFO becoming full.
1239 /* check ep is enabled */
1240 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1242 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1243 index, dwc2_readl(hsotg, epctrl_reg));
1245 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1246 __func__, dwc2_readl(hsotg, epctrl_reg));
1248 /* enable ep interrupts */
1249 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1253 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1254 * @hsotg: The device state.
1255 * @hs_ep: The endpoint the request is on.
1256 * @req: The request being processed.
1258 * We've been asked to queue a request, so ensure that the memory buffer
1259 * is correctly setup for DMA. If we've been passed an extant DMA address
1260 * then ensure the buffer has been synced to memory. If our buffer has no
1261 * DMA memory, then we map the memory and mark our request to allow us to
1262 * cleanup on completion.
1264 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1265 struct dwc2_hsotg_ep *hs_ep,
1266 struct usb_request *req)
1270 hs_ep->map_dir = hs_ep->dir_in;
1271 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1278 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1279 __func__, req->buf, req->length);
1284 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1285 struct dwc2_hsotg_ep *hs_ep,
1286 struct dwc2_hsotg_req *hs_req)
1288 void *req_buf = hs_req->req.buf;
1290 /* If dma is not being used or buffer is aligned */
1291 if (!using_dma(hsotg) || !((long)req_buf & 3))
1294 WARN_ON(hs_req->saved_req_buf);
1296 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1297 hs_ep->ep.name, req_buf, hs_req->req.length);
1299 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1300 if (!hs_req->req.buf) {
1301 hs_req->req.buf = req_buf;
1303 "%s: unable to allocate memory for bounce buffer\n",
1308 /* Save actual buffer */
1309 hs_req->saved_req_buf = req_buf;
1312 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1317 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1318 struct dwc2_hsotg_ep *hs_ep,
1319 struct dwc2_hsotg_req *hs_req)
1321 /* If dma is not being used or buffer was aligned */
1322 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1325 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1326 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1328 /* Copy data from bounce buffer on successful out transfer */
1329 if (!hs_ep->dir_in && !hs_req->req.status)
1330 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1331 hs_req->req.actual);
1333 /* Free bounce buffer */
1334 kfree(hs_req->req.buf);
1336 hs_req->req.buf = hs_req->saved_req_buf;
1337 hs_req->saved_req_buf = NULL;
1341 * dwc2_gadget_target_frame_elapsed - Checks target frame
1342 * @hs_ep: The driver endpoint to check
1344 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1345 * corresponding transfer.
1347 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1349 struct dwc2_hsotg *hsotg = hs_ep->parent;
1350 u32 target_frame = hs_ep->target_frame;
1351 u32 current_frame = hsotg->frame_number;
1352 bool frame_overrun = hs_ep->frame_overrun;
1353 u16 limit = DSTS_SOFFN_LIMIT;
1355 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1358 if (!frame_overrun && current_frame >= target_frame)
1361 if (frame_overrun && current_frame >= target_frame &&
1362 ((current_frame - target_frame) < limit / 2))
1369 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1370 * @hsotg: The driver state
1371 * @hs_ep: the ep descriptor chain is for
1373 * Called to update EP0 structure's pointers depend on stage of
1376 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1377 struct dwc2_hsotg_ep *hs_ep)
1379 switch (hsotg->ep0_state) {
1380 case DWC2_EP0_SETUP:
1381 case DWC2_EP0_STATUS_OUT:
1382 hs_ep->desc_list = hsotg->setup_desc[0];
1383 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1385 case DWC2_EP0_DATA_IN:
1386 case DWC2_EP0_STATUS_IN:
1387 hs_ep->desc_list = hsotg->ctrl_in_desc;
1388 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1390 case DWC2_EP0_DATA_OUT:
1391 hs_ep->desc_list = hsotg->ctrl_out_desc;
1392 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1395 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1403 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1406 struct dwc2_hsotg_req *hs_req = our_req(req);
1407 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1408 struct dwc2_hsotg *hs = hs_ep->parent;
1415 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1416 ep->name, req, req->length, req->buf, req->no_interrupt,
1417 req->zero, req->short_not_ok);
1419 if (hs->lx_state == DWC2_L1) {
1420 dwc2_wakeup_from_lpm_l1(hs, true);
1423 /* Prevent new request submission when controller is suspended */
1424 if (hs->lx_state != DWC2_L0) {
1425 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1430 /* initialise status of the request */
1431 INIT_LIST_HEAD(&hs_req->queue);
1433 req->status = -EINPROGRESS;
1435 /* Don't queue ISOC request if length greater than mps*mc */
1436 if (hs_ep->isochronous &&
1437 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1438 dev_err(hs->dev, "req length > maxpacket*mc\n");
1442 /* In DDMA mode for ISOC's don't queue request if length greater
1443 * than descriptor limits.
1445 if (using_desc_dma(hs) && hs_ep->isochronous) {
1446 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1447 if (hs_ep->dir_in && req->length > maxsize) {
1448 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1449 req->length, maxsize);
1453 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1454 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1455 req->length, hs_ep->ep.maxpacket);
1460 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1464 /* if we're using DMA, sync the buffers as necessary */
1465 if (using_dma(hs)) {
1466 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1470 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1471 if (using_desc_dma(hs) && !hs_ep->index) {
1472 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1477 first = list_empty(&hs_ep->queue);
1478 list_add_tail(&hs_req->queue, &hs_ep->queue);
1481 * Handle DDMA isochronous transfers separately - just add new entry
1482 * to the descriptor chain.
1483 * Transfer will be started once SW gets either one of NAK or
1484 * OutTknEpDis interrupts.
1486 if (using_desc_dma(hs) && hs_ep->isochronous) {
1487 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1488 dma_addr_t dma_addr = hs_req->req.dma;
1490 if (hs_req->req.num_sgs) {
1491 WARN_ON(hs_req->req.num_sgs > 1);
1492 dma_addr = sg_dma_address(hs_req->req.sg);
1494 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1495 hs_req->req.length);
1500 /* Change EP direction if status phase request is after data out */
1501 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1502 hs->ep0_state == DWC2_EP0_DATA_OUT)
1506 if (!hs_ep->isochronous) {
1507 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1511 /* Update current frame number value. */
1512 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1513 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1514 dwc2_gadget_incr_frame_num(hs_ep);
1515 /* Update current frame number value once more as it
1518 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1521 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1522 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1527 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1530 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1531 struct dwc2_hsotg *hs = hs_ep->parent;
1532 unsigned long flags = 0;
1535 spin_lock_irqsave(&hs->lock, flags);
1536 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1537 spin_unlock_irqrestore(&hs->lock, flags);
1542 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1543 struct usb_request *req)
1545 struct dwc2_hsotg_req *hs_req = our_req(req);
1551 * dwc2_hsotg_complete_oursetup - setup completion callback
1552 * @ep: The endpoint the request was on.
1553 * @req: The request completed.
1555 * Called on completion of any requests the driver itself
1556 * submitted that need cleaning up.
1558 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1559 struct usb_request *req)
1561 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1562 struct dwc2_hsotg *hsotg = hs_ep->parent;
1564 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1566 dwc2_hsotg_ep_free_request(ep, req);
1570 * ep_from_windex - convert control wIndex value to endpoint
1571 * @hsotg: The driver state.
1572 * @windex: The control request wIndex field (in host order).
1574 * Convert the given wIndex into a pointer to an driver endpoint
1575 * structure, or return NULL if it is not a valid endpoint.
1577 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1580 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1581 int idx = windex & 0x7F;
1583 if (windex >= 0x100)
1586 if (idx > hsotg->num_of_eps)
1589 return index_to_ep(hsotg, idx, dir);
1593 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1594 * @hsotg: The driver state.
1595 * @testmode: requested usb test mode
1596 * Enable usb Test Mode requested by the Host.
1598 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1600 int dctl = dwc2_readl(hsotg, DCTL);
1602 dctl &= ~DCTL_TSTCTL_MASK;
1606 case USB_TEST_SE0_NAK:
1607 case USB_TEST_PACKET:
1608 case USB_TEST_FORCE_ENABLE:
1609 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1614 dwc2_writel(hsotg, dctl, DCTL);
1619 * dwc2_hsotg_send_reply - send reply to control request
1620 * @hsotg: The device state
1622 * @buff: Buffer for request
1623 * @length: Length of reply.
1625 * Create a request and queue it on the given endpoint. This is useful as
1626 * an internal method of sending replies to certain control requests, etc.
1628 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1629 struct dwc2_hsotg_ep *ep,
1633 struct usb_request *req;
1636 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1638 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1639 hsotg->ep0_reply = req;
1641 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1645 req->buf = hsotg->ep0_buff;
1646 req->length = length;
1648 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1652 req->complete = dwc2_hsotg_complete_oursetup;
1655 memcpy(req->buf, buff, length);
1657 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1659 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1667 * dwc2_hsotg_process_req_status - process request GET_STATUS
1668 * @hsotg: The device state
1669 * @ctrl: USB control request
1671 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1672 struct usb_ctrlrequest *ctrl)
1674 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1675 struct dwc2_hsotg_ep *ep;
1680 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1683 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1687 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1688 case USB_RECIP_DEVICE:
1689 status = hsotg->gadget.is_selfpowered <<
1690 USB_DEVICE_SELF_POWERED;
1691 status |= hsotg->remote_wakeup_allowed <<
1692 USB_DEVICE_REMOTE_WAKEUP;
1693 reply = cpu_to_le16(status);
1696 case USB_RECIP_INTERFACE:
1697 /* currently, the data result should be zero */
1698 reply = cpu_to_le16(0);
1701 case USB_RECIP_ENDPOINT:
1702 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1706 reply = cpu_to_le16(ep->halted ? 1 : 0);
1713 if (le16_to_cpu(ctrl->wLength) != 2)
1716 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1718 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1725 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1728 * get_ep_head - return the first request on the endpoint
1729 * @hs_ep: The controller endpoint to get
1731 * Get the first request on the endpoint.
1733 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1735 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1740 * dwc2_gadget_start_next_request - Starts next request from ep queue
1741 * @hs_ep: Endpoint structure
1743 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1744 * in its handler. Hence we need to unmask it here to be able to do
1745 * resynchronization.
1747 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1749 struct dwc2_hsotg *hsotg = hs_ep->parent;
1750 int dir_in = hs_ep->dir_in;
1751 struct dwc2_hsotg_req *hs_req;
1753 if (!list_empty(&hs_ep->queue)) {
1754 hs_req = get_ep_head(hs_ep);
1755 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1758 if (!hs_ep->isochronous)
1762 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1765 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1771 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1772 * @hsotg: The device state
1773 * @ctrl: USB control request
1775 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1776 struct usb_ctrlrequest *ctrl)
1778 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1779 struct dwc2_hsotg_req *hs_req;
1780 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1781 struct dwc2_hsotg_ep *ep;
1788 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1789 __func__, set ? "SET" : "CLEAR");
1791 wValue = le16_to_cpu(ctrl->wValue);
1792 wIndex = le16_to_cpu(ctrl->wIndex);
1793 recip = ctrl->bRequestType & USB_RECIP_MASK;
1796 case USB_RECIP_DEVICE:
1798 case USB_DEVICE_REMOTE_WAKEUP:
1800 hsotg->remote_wakeup_allowed = 1;
1802 hsotg->remote_wakeup_allowed = 0;
1805 case USB_DEVICE_TEST_MODE:
1806 if ((wIndex & 0xff) != 0)
1811 hsotg->test_mode = wIndex >> 8;
1817 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1820 "%s: failed to send reply\n", __func__);
1825 case USB_RECIP_ENDPOINT:
1826 ep = ep_from_windex(hsotg, wIndex);
1828 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1834 case USB_ENDPOINT_HALT:
1835 halted = ep->halted;
1837 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1839 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1842 "%s: failed to send reply\n", __func__);
1847 * we have to complete all requests for ep if it was
1848 * halted, and the halt was cleared by CLEAR_FEATURE
1851 if (!set && halted) {
1853 * If we have request in progress,
1859 list_del_init(&hs_req->queue);
1860 if (hs_req->req.complete) {
1861 spin_unlock(&hsotg->lock);
1862 usb_gadget_giveback_request(
1863 &ep->ep, &hs_req->req);
1864 spin_lock(&hsotg->lock);
1868 /* If we have pending request, then start it */
1870 dwc2_gadget_start_next_request(ep);
1885 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1888 * dwc2_hsotg_stall_ep0 - stall ep0
1889 * @hsotg: The device state
1891 * Set stall for ep0 as response for setup request.
1893 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1895 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1899 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1900 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1903 * DxEPCTL_Stall will be cleared by EP once it has
1904 * taken effect, so no need to clear later.
1907 ctrl = dwc2_readl(hsotg, reg);
1908 ctrl |= DXEPCTL_STALL;
1909 ctrl |= DXEPCTL_CNAK;
1910 dwc2_writel(hsotg, ctrl, reg);
1913 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1914 ctrl, reg, dwc2_readl(hsotg, reg));
1917 * complete won't be called, so we enqueue
1918 * setup request here
1920 dwc2_hsotg_enqueue_setup(hsotg);
1924 * dwc2_hsotg_process_control - process a control request
1925 * @hsotg: The device state
1926 * @ctrl: The control request received
1928 * The controller has received the SETUP phase of a control request, and
1929 * needs to work out what to do next (and whether to pass it on to the
1932 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1933 struct usb_ctrlrequest *ctrl)
1935 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1940 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1941 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1942 ctrl->wIndex, ctrl->wLength);
1944 if (ctrl->wLength == 0) {
1946 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1947 } else if (ctrl->bRequestType & USB_DIR_IN) {
1949 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1952 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1955 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1956 switch (ctrl->bRequest) {
1957 case USB_REQ_SET_ADDRESS:
1958 hsotg->connected = 1;
1959 dcfg = dwc2_readl(hsotg, DCFG);
1960 dcfg &= ~DCFG_DEVADDR_MASK;
1961 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1962 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1963 dwc2_writel(hsotg, dcfg, DCFG);
1965 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1967 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1970 case USB_REQ_GET_STATUS:
1971 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1974 case USB_REQ_CLEAR_FEATURE:
1975 case USB_REQ_SET_FEATURE:
1976 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1981 /* as a fallback, try delivering it to the driver to deal with */
1983 if (ret == 0 && hsotg->driver) {
1984 spin_unlock(&hsotg->lock);
1985 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1986 spin_lock(&hsotg->lock);
1988 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1991 hsotg->delayed_status = false;
1992 if (ret == USB_GADGET_DELAYED_STATUS)
1993 hsotg->delayed_status = true;
1996 * the request is either unhandlable, or is not formatted correctly
1997 * so respond with a STALL for the status stage to indicate failure.
2001 dwc2_hsotg_stall_ep0(hsotg);
2005 * dwc2_hsotg_complete_setup - completion of a setup transfer
2006 * @ep: The endpoint the request was on.
2007 * @req: The request completed.
2009 * Called on completion of any requests the driver itself submitted for
2012 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2013 struct usb_request *req)
2015 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2016 struct dwc2_hsotg *hsotg = hs_ep->parent;
2018 if (req->status < 0) {
2019 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2023 spin_lock(&hsotg->lock);
2024 if (req->actual == 0)
2025 dwc2_hsotg_enqueue_setup(hsotg);
2027 dwc2_hsotg_process_control(hsotg, req->buf);
2028 spin_unlock(&hsotg->lock);
2032 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2033 * @hsotg: The device state.
2035 * Enqueue a request on EP0 if necessary to received any SETUP packets
2036 * received from the host.
2038 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2040 struct usb_request *req = hsotg->ctrl_req;
2041 struct dwc2_hsotg_req *hs_req = our_req(req);
2044 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2048 req->buf = hsotg->ctrl_buff;
2049 req->complete = dwc2_hsotg_complete_setup;
2051 if (!list_empty(&hs_req->queue)) {
2052 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2056 hsotg->eps_out[0]->dir_in = 0;
2057 hsotg->eps_out[0]->send_zlp = 0;
2058 hsotg->ep0_state = DWC2_EP0_SETUP;
2060 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2062 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2064 * Don't think there's much we can do other than watch the
2070 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2071 struct dwc2_hsotg_ep *hs_ep)
2074 u8 index = hs_ep->index;
2075 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2076 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2079 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2082 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2084 if (using_desc_dma(hsotg)) {
2085 /* Not specific buffer needed for ep0 ZLP */
2086 dma_addr_t dma = hs_ep->desc_list_dma;
2089 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2091 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2093 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2094 DXEPTSIZ_XFERSIZE(0),
2098 ctrl = dwc2_readl(hsotg, epctl_reg);
2099 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2100 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2101 ctrl |= DXEPCTL_USBACTEP;
2102 dwc2_writel(hsotg, ctrl, epctl_reg);
2106 * dwc2_hsotg_complete_request - complete a request given to us
2107 * @hsotg: The device state.
2108 * @hs_ep: The endpoint the request was on.
2109 * @hs_req: The request to complete.
2110 * @result: The result code (0 => Ok, otherwise errno)
2112 * The given request has finished, so call the necessary completion
2113 * if it has one and then look to see if we can start a new request
2116 * Note, expects the ep to already be locked as appropriate.
2118 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2119 struct dwc2_hsotg_ep *hs_ep,
2120 struct dwc2_hsotg_req *hs_req,
2124 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2128 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2129 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2132 * only replace the status if we've not already set an error
2133 * from a previous transaction
2136 if (hs_req->req.status == -EINPROGRESS)
2137 hs_req->req.status = result;
2139 if (using_dma(hsotg))
2140 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2142 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2145 list_del_init(&hs_req->queue);
2148 * call the complete request with the locks off, just in case the
2149 * request tries to queue more work for this endpoint.
2152 if (hs_req->req.complete) {
2153 spin_unlock(&hsotg->lock);
2154 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2155 spin_lock(&hsotg->lock);
2158 /* In DDMA don't need to proceed to starting of next ISOC request */
2159 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2163 * Look to see if there is anything else to do. Note, the completion
2164 * of the previous request may have caused a new request to be started
2165 * so be careful when doing this.
2168 if (!hs_ep->req && result >= 0)
2169 dwc2_gadget_start_next_request(hs_ep);
2173 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2174 * @hs_ep: The endpoint the request was on.
2176 * Get first request from the ep queue, determine descriptor on which complete
2177 * happened. SW discovers which descriptor currently in use by HW, adjusts
2178 * dma_address and calculates index of completed descriptor based on the value
2179 * of DEPDMA register. Update actual length of request, giveback to gadget.
2181 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2183 struct dwc2_hsotg *hsotg = hs_ep->parent;
2184 struct dwc2_hsotg_req *hs_req;
2185 struct usb_request *ureq;
2189 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2191 /* Process only descriptors with buffer status set to DMA done */
2192 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2193 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2195 hs_req = get_ep_head(hs_ep);
2197 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2200 ureq = &hs_req->req;
2202 /* Check completion status */
2203 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2205 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2206 DEV_DMA_ISOC_RX_NBYTES_MASK;
2207 ureq->actual = ureq->length - ((desc_sts & mask) >>
2208 DEV_DMA_ISOC_NBYTES_SHIFT);
2210 /* Adjust actual len for ISOC Out if len is
2213 if (!hs_ep->dir_in && ureq->length & 0x3)
2214 ureq->actual += 4 - (ureq->length & 0x3);
2216 /* Set actual frame number for completed transfers */
2217 ureq->frame_number =
2218 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2219 DEV_DMA_ISOC_FRNUM_SHIFT;
2222 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2224 hs_ep->compl_desc++;
2225 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2226 hs_ep->compl_desc = 0;
2227 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2232 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2233 * @hs_ep: The isochronous endpoint.
2235 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2236 * interrupt. Reset target frame and next_desc to allow to start
2237 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2238 * interrupt for OUT direction.
2240 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2242 struct dwc2_hsotg *hsotg = hs_ep->parent;
2245 dwc2_flush_rx_fifo(hsotg);
2246 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2248 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2249 hs_ep->next_desc = 0;
2250 hs_ep->compl_desc = 0;
2254 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2255 * @hsotg: The device state.
2256 * @ep_idx: The endpoint index for the data
2257 * @size: The size of data in the fifo, in bytes
2259 * The FIFO status shows there is data to read from the FIFO for a given
2260 * endpoint, so sort out whether we need to read the data into a request
2261 * that has been made for that endpoint.
2263 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2265 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2266 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2272 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2276 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2277 __func__, size, ep_idx, epctl);
2279 /* dump the data from the FIFO, we've nothing we can do */
2280 for (ptr = 0; ptr < size; ptr += 4)
2281 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2287 read_ptr = hs_req->req.actual;
2288 max_req = hs_req->req.length - read_ptr;
2290 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2291 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2293 if (to_read > max_req) {
2295 * more data appeared than we where willing
2296 * to deal with in this request.
2299 /* currently we don't deal this */
2303 hs_ep->total_data += to_read;
2304 hs_req->req.actual += to_read;
2305 to_read = DIV_ROUND_UP(to_read, 4);
2308 * note, we might over-write the buffer end by 3 bytes depending on
2309 * alignment of the data.
2311 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2312 hs_req->req.buf + read_ptr, to_read);
2316 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2317 * @hsotg: The device instance
2318 * @dir_in: If IN zlp
2320 * Generate a zero-length IN packet request for terminating a SETUP
2323 * Note, since we don't write any data to the TxFIFO, then it is
2324 * currently believed that we do not need to wait for any space in
2327 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2329 /* eps_out[0] is used in both directions */
2330 hsotg->eps_out[0]->dir_in = dir_in;
2331 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2333 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2337 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2338 * @hs_ep - The endpoint on which transfer went
2340 * Iterate over endpoints descriptor chain and get info on bytes remained
2341 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2343 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2345 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2346 struct dwc2_hsotg *hsotg = hs_ep->parent;
2347 unsigned int bytes_rem = 0;
2348 unsigned int bytes_rem_correction = 0;
2349 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2352 u32 mps = hs_ep->ep.maxpacket;
2353 int dir_in = hs_ep->dir_in;
2358 /* Interrupt OUT EP with mps not multiple of 4 */
2360 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2361 bytes_rem_correction = 4 - (mps % 4);
2363 for (i = 0; i < hs_ep->desc_count; ++i) {
2364 status = desc->status;
2365 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2366 bytes_rem -= bytes_rem_correction;
2368 if (status & DEV_DMA_STS_MASK)
2369 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2370 i, status & DEV_DMA_STS_MASK);
2372 if (status & DEV_DMA_L)
2382 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2383 * @hsotg: The device instance
2384 * @epnum: The endpoint received from
2386 * The RXFIFO has delivered an OutDone event, which means that the data
2387 * transfer for an OUT endpoint has been completed, either by a short
2388 * packet or by the finish of a transfer.
2390 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2392 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2393 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2394 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2395 struct usb_request *req = &hs_req->req;
2396 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2400 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2404 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2405 dev_dbg(hsotg->dev, "zlp packet received\n");
2406 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2407 dwc2_hsotg_enqueue_setup(hsotg);
2411 if (using_desc_dma(hsotg))
2412 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2414 if (using_dma(hsotg)) {
2415 unsigned int size_done;
2418 * Calculate the size of the transfer by checking how much
2419 * is left in the endpoint size register and then working it
2420 * out from the amount we loaded for the transfer.
2422 * We need to do this as DMA pointers are always 32bit aligned
2423 * so may overshoot/undershoot the transfer.
2426 size_done = hs_ep->size_loaded - size_left;
2427 size_done += hs_ep->last_load;
2429 req->actual = size_done;
2432 /* if there is more request to do, schedule new transfer */
2433 if (req->actual < req->length && size_left == 0) {
2434 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2438 if (req->actual < req->length && req->short_not_ok) {
2439 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2440 __func__, req->actual, req->length);
2443 * todo - what should we return here? there's no one else
2444 * even bothering to check the status.
2448 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2449 if (!using_desc_dma(hsotg) && epnum == 0 &&
2450 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2451 /* Move to STATUS IN */
2452 if (!hsotg->delayed_status)
2453 dwc2_hsotg_ep0_zlp(hsotg, true);
2456 /* Set actual frame number for completed transfers */
2457 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2458 req->frame_number = hs_ep->target_frame;
2459 dwc2_gadget_incr_frame_num(hs_ep);
2462 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2466 * dwc2_hsotg_handle_rx - RX FIFO has data
2467 * @hsotg: The device instance
2469 * The IRQ handler has detected that the RX FIFO has some data in it
2470 * that requires processing, so find out what is in there and do the
2473 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2474 * chunks, so if you have x packets received on an endpoint you'll get x
2475 * FIFO events delivered, each with a packet's worth of data in it.
2477 * When using DMA, we should not be processing events from the RXFIFO
2478 * as the actual data should be sent to the memory directly and we turn
2479 * on the completion interrupts to get notifications of transfer completion.
2481 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2483 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2484 u32 epnum, status, size;
2486 WARN_ON(using_dma(hsotg));
2488 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2489 status = grxstsr & GRXSTS_PKTSTS_MASK;
2491 size = grxstsr & GRXSTS_BYTECNT_MASK;
2492 size >>= GRXSTS_BYTECNT_SHIFT;
2494 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2495 __func__, grxstsr, size, epnum);
2497 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2498 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2499 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2502 case GRXSTS_PKTSTS_OUTDONE:
2503 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2504 dwc2_hsotg_read_frameno(hsotg));
2506 if (!using_dma(hsotg))
2507 dwc2_hsotg_handle_outdone(hsotg, epnum);
2510 case GRXSTS_PKTSTS_SETUPDONE:
2512 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2513 dwc2_hsotg_read_frameno(hsotg),
2514 dwc2_readl(hsotg, DOEPCTL(0)));
2516 * Call dwc2_hsotg_handle_outdone here if it was not called from
2517 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2518 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2520 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2521 dwc2_hsotg_handle_outdone(hsotg, epnum);
2524 case GRXSTS_PKTSTS_OUTRX:
2525 dwc2_hsotg_rx_data(hsotg, epnum, size);
2528 case GRXSTS_PKTSTS_SETUPRX:
2530 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2531 dwc2_hsotg_read_frameno(hsotg),
2532 dwc2_readl(hsotg, DOEPCTL(0)));
2534 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2536 dwc2_hsotg_rx_data(hsotg, epnum, size);
2540 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2543 dwc2_hsotg_dump(hsotg);
2549 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2550 * @mps: The maximum packet size in bytes.
2552 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2556 return D0EPCTL_MPS_64;
2558 return D0EPCTL_MPS_32;
2560 return D0EPCTL_MPS_16;
2562 return D0EPCTL_MPS_8;
2565 /* bad max packet size, warn and return invalid result */
2571 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2572 * @hsotg: The driver state.
2573 * @ep: The index number of the endpoint
2574 * @mps: The maximum packet size in bytes
2575 * @mc: The multicount value
2576 * @dir_in: True if direction is in.
2578 * Configure the maximum packet size for the given endpoint, updating
2579 * the hardware control registers to reflect this.
2581 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2582 unsigned int ep, unsigned int mps,
2583 unsigned int mc, unsigned int dir_in)
2585 struct dwc2_hsotg_ep *hs_ep;
2588 hs_ep = index_to_ep(hsotg, ep, dir_in);
2593 u32 mps_bytes = mps;
2595 /* EP0 is a special case */
2596 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2599 hs_ep->ep.maxpacket = mps_bytes;
2607 hs_ep->ep.maxpacket = mps;
2611 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2612 reg &= ~DXEPCTL_MPS_MASK;
2614 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2616 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2617 reg &= ~DXEPCTL_MPS_MASK;
2619 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2625 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2629 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2630 * @hsotg: The driver state
2631 * @idx: The index for the endpoint (0..15)
2633 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2635 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2638 /* wait until the fifo is flushed */
2639 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2640 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2645 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2646 * @hsotg: The driver state
2647 * @hs_ep: The driver endpoint to check.
2649 * Check to see if there is a request that has data to send, and if so
2650 * make an attempt to write data into the FIFO.
2652 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2653 struct dwc2_hsotg_ep *hs_ep)
2655 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2657 if (!hs_ep->dir_in || !hs_req) {
2659 * if request is not enqueued, we disable interrupts
2660 * for endpoints, excepting ep0
2662 if (hs_ep->index != 0)
2663 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2668 if (hs_req->req.actual < hs_req->req.length) {
2669 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2671 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2678 * dwc2_hsotg_complete_in - complete IN transfer
2679 * @hsotg: The device state.
2680 * @hs_ep: The endpoint that has just completed.
2682 * An IN transfer has been completed, update the transfer's state and then
2683 * call the relevant completion routines.
2685 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2686 struct dwc2_hsotg_ep *hs_ep)
2688 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2689 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2690 int size_left, size_done;
2693 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2697 /* Finish ZLP handling for IN EP0 transactions */
2698 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2699 dev_dbg(hsotg->dev, "zlp packet sent\n");
2702 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2703 * changed to IN. Change back to complete OUT transfer request
2707 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2708 if (hsotg->test_mode) {
2711 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2713 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2715 dwc2_hsotg_stall_ep0(hsotg);
2719 dwc2_hsotg_enqueue_setup(hsotg);
2724 * Calculate the size of the transfer by checking how much is left
2725 * in the endpoint size register and then working it out from
2726 * the amount we loaded for the transfer.
2728 * We do this even for DMA, as the transfer may have incremented
2729 * past the end of the buffer (DMA transfers are always 32bit
2732 if (using_desc_dma(hsotg)) {
2733 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2735 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2738 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2741 size_done = hs_ep->size_loaded - size_left;
2742 size_done += hs_ep->last_load;
2744 if (hs_req->req.actual != size_done)
2745 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2746 __func__, hs_req->req.actual, size_done);
2748 hs_req->req.actual = size_done;
2749 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2750 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2752 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2753 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2754 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2758 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2759 if (hs_ep->send_zlp) {
2760 hs_ep->send_zlp = 0;
2761 if (!using_desc_dma(hsotg)) {
2762 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2763 /* transfer will be completed on next complete interrupt */
2768 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2769 /* Move to STATUS OUT */
2770 dwc2_hsotg_ep0_zlp(hsotg, false);
2774 /* Set actual frame number for completed transfers */
2775 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2776 hs_req->req.frame_number = hs_ep->target_frame;
2777 dwc2_gadget_incr_frame_num(hs_ep);
2780 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2784 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2785 * @hsotg: The device state.
2786 * @idx: Index of ep.
2787 * @dir_in: Endpoint direction 1-in 0-out.
2789 * Reads for endpoint with given index and direction, by masking
2790 * epint_reg with coresponding mask.
2792 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2793 unsigned int idx, int dir_in)
2795 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2796 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2801 mask = dwc2_readl(hsotg, epmsk_reg);
2802 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2803 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2804 mask |= DXEPINT_SETUP_RCVD;
2806 ints = dwc2_readl(hsotg, epint_reg);
2812 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2813 * @hs_ep: The endpoint on which interrupt is asserted.
2815 * This interrupt indicates that the endpoint has been disabled per the
2816 * application's request.
2818 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2819 * in case of ISOC completes current request.
2821 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2822 * request starts it.
2824 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2826 struct dwc2_hsotg *hsotg = hs_ep->parent;
2827 struct dwc2_hsotg_req *hs_req;
2828 unsigned char idx = hs_ep->index;
2829 int dir_in = hs_ep->dir_in;
2830 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2831 int dctl = dwc2_readl(hsotg, DCTL);
2833 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2836 int epctl = dwc2_readl(hsotg, epctl_reg);
2838 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2840 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2841 int dctl = dwc2_readl(hsotg, DCTL);
2843 dctl |= DCTL_CGNPINNAK;
2844 dwc2_writel(hsotg, dctl, DCTL);
2848 if (dctl & DCTL_GOUTNAKSTS) {
2849 dctl |= DCTL_CGOUTNAK;
2850 dwc2_writel(hsotg, dctl, DCTL);
2854 if (!hs_ep->isochronous)
2857 if (list_empty(&hs_ep->queue)) {
2858 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2864 hs_req = get_ep_head(hs_ep);
2866 hs_req->req.frame_number = hs_ep->target_frame;
2867 hs_req->req.actual = 0;
2868 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2871 dwc2_gadget_incr_frame_num(hs_ep);
2872 /* Update current frame number value. */
2873 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2874 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2878 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2879 * @ep: The endpoint on which interrupt is asserted.
2881 * This is starting point for ISOC-OUT transfer, synchronization done with
2882 * first out token received from host while corresponding EP is disabled.
2884 * Device does not know initial frame in which out token will come. For this
2885 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2886 * getting this interrupt SW starts calculation for next transfer frame.
2888 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2890 struct dwc2_hsotg *hsotg = ep->parent;
2891 struct dwc2_hsotg_req *hs_req;
2892 int dir_in = ep->dir_in;
2894 if (dir_in || !ep->isochronous)
2897 if (using_desc_dma(hsotg)) {
2898 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2899 /* Start first ISO Out */
2900 ep->target_frame = hsotg->frame_number;
2901 dwc2_gadget_start_isoc_ddma(ep);
2906 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2909 ep->target_frame = hsotg->frame_number;
2910 if (ep->interval > 1) {
2911 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2912 if (ep->target_frame & 0x1)
2913 ctrl |= DXEPCTL_SETODDFR;
2915 ctrl |= DXEPCTL_SETEVENFR;
2917 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2921 while (dwc2_gadget_target_frame_elapsed(ep)) {
2922 hs_req = get_ep_head(ep);
2924 hs_req->req.frame_number = ep->target_frame;
2925 hs_req->req.actual = 0;
2926 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2929 dwc2_gadget_incr_frame_num(ep);
2930 /* Update current frame number value. */
2931 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2935 dwc2_gadget_start_next_request(ep);
2939 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2940 struct dwc2_hsotg_ep *hs_ep);
2943 * dwc2_gadget_handle_nak - handle NAK interrupt
2944 * @hs_ep: The endpoint on which interrupt is asserted.
2946 * This is starting point for ISOC-IN transfer, synchronization done with
2947 * first IN token received from host while corresponding EP is disabled.
2949 * Device does not know when first one token will arrive from host. On first
2950 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2951 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2952 * sent in response to that as there was no data in FIFO. SW is basing on this
2953 * interrupt to obtain frame in which token has come and then based on the
2954 * interval calculates next frame for transfer.
2956 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2958 struct dwc2_hsotg *hsotg = hs_ep->parent;
2959 struct dwc2_hsotg_req *hs_req;
2960 int dir_in = hs_ep->dir_in;
2963 if (!dir_in || !hs_ep->isochronous)
2966 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2968 if (using_desc_dma(hsotg)) {
2969 hs_ep->target_frame = hsotg->frame_number;
2970 dwc2_gadget_incr_frame_num(hs_ep);
2972 /* In service interval mode target_frame must
2973 * be set to last (u)frame of the service interval.
2975 if (hsotg->params.service_interval) {
2976 /* Set target_frame to the first (u)frame of
2977 * the service interval
2979 hs_ep->target_frame &= ~hs_ep->interval + 1;
2981 /* Set target_frame to the last (u)frame of
2982 * the service interval
2984 dwc2_gadget_incr_frame_num(hs_ep);
2985 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2988 dwc2_gadget_start_isoc_ddma(hs_ep);
2992 hs_ep->target_frame = hsotg->frame_number;
2993 if (hs_ep->interval > 1) {
2994 u32 ctrl = dwc2_readl(hsotg,
2995 DIEPCTL(hs_ep->index));
2996 if (hs_ep->target_frame & 0x1)
2997 ctrl |= DXEPCTL_SETODDFR;
2999 ctrl |= DXEPCTL_SETEVENFR;
3001 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
3005 if (using_desc_dma(hsotg))
3008 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3009 if (ctrl & DXEPCTL_EPENA)
3010 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3012 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3014 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3015 hs_req = get_ep_head(hs_ep);
3017 hs_req->req.frame_number = hs_ep->target_frame;
3018 hs_req->req.actual = 0;
3019 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3022 dwc2_gadget_incr_frame_num(hs_ep);
3023 /* Update current frame number value. */
3024 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3028 dwc2_gadget_start_next_request(hs_ep);
3032 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3033 * @hsotg: The driver state
3034 * @idx: The index for the endpoint (0..15)
3035 * @dir_in: Set if this is an IN endpoint
3037 * Process and clear any interrupt pending for an individual endpoint
3039 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3042 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3043 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3044 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3045 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3048 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3050 /* Clear endpoint interrupts */
3051 dwc2_writel(hsotg, ints, epint_reg);
3054 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3055 __func__, idx, dir_in ? "in" : "out");
3059 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3060 __func__, idx, dir_in ? "in" : "out", ints);
3062 /* Don't process XferCompl interrupt if it is a setup packet */
3063 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3064 ints &= ~DXEPINT_XFERCOMPL;
3067 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3068 * stage and xfercomplete was generated without SETUP phase done
3069 * interrupt. SW should parse received setup packet only after host's
3070 * exit from setup phase of control transfer.
3072 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3073 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3074 ints &= ~DXEPINT_XFERCOMPL;
3076 if (ints & DXEPINT_XFERCOMPL) {
3078 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3079 __func__, dwc2_readl(hsotg, epctl_reg),
3080 dwc2_readl(hsotg, epsiz_reg));
3082 /* In DDMA handle isochronous requests separately */
3083 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3084 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3085 } else if (dir_in) {
3087 * We get OutDone from the FIFO, so we only
3088 * need to look at completing IN requests here
3089 * if operating slave mode
3091 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3092 dwc2_hsotg_complete_in(hsotg, hs_ep);
3094 if (idx == 0 && !hs_ep->req)
3095 dwc2_hsotg_enqueue_setup(hsotg);
3096 } else if (using_dma(hsotg)) {
3098 * We're using DMA, we need to fire an OutDone here
3099 * as we ignore the RXFIFO.
3101 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3102 dwc2_hsotg_handle_outdone(hsotg, idx);
3106 if (ints & DXEPINT_EPDISBLD)
3107 dwc2_gadget_handle_ep_disabled(hs_ep);
3109 if (ints & DXEPINT_OUTTKNEPDIS)
3110 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3112 if (ints & DXEPINT_NAKINTRPT)
3113 dwc2_gadget_handle_nak(hs_ep);
3115 if (ints & DXEPINT_AHBERR)
3116 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3118 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3119 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3121 if (using_dma(hsotg) && idx == 0) {
3123 * this is the notification we've received a
3124 * setup packet. In non-DMA mode we'd get this
3125 * from the RXFIFO, instead we need to process
3132 dwc2_hsotg_handle_outdone(hsotg, 0);
3136 if (ints & DXEPINT_STSPHSERCVD) {
3137 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3139 /* Safety check EP0 state when STSPHSERCVD asserted */
3140 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3141 /* Move to STATUS IN for DDMA */
3142 if (using_desc_dma(hsotg)) {
3143 if (!hsotg->delayed_status)
3144 dwc2_hsotg_ep0_zlp(hsotg, true);
3146 /* In case of 3 stage Control Write with delayed
3147 * status, when Status IN transfer started
3148 * before STSPHSERCVD asserted, NAKSTS bit not
3149 * cleared by CNAK in dwc2_hsotg_start_req()
3150 * function. Clear now NAKSTS to allow complete
3153 dwc2_set_bit(hsotg, DIEPCTL(0),
3160 if (ints & DXEPINT_BACK2BACKSETUP)
3161 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3163 if (ints & DXEPINT_BNAINTR) {
3164 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3165 if (hs_ep->isochronous)
3166 dwc2_gadget_handle_isoc_bna(hs_ep);
3169 if (dir_in && !hs_ep->isochronous) {
3170 /* not sure if this is important, but we'll clear it anyway */
3171 if (ints & DXEPINT_INTKNTXFEMP) {
3172 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3176 /* this probably means something bad is happening */
3177 if (ints & DXEPINT_INTKNEPMIS) {
3178 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3182 /* FIFO has space or is empty (see GAHBCFG) */
3183 if (hsotg->dedicated_fifos &&
3184 ints & DXEPINT_TXFEMP) {
3185 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3187 if (!using_dma(hsotg))
3188 dwc2_hsotg_trytx(hsotg, hs_ep);
3194 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3195 * @hsotg: The device state.
3197 * Handle updating the device settings after the enumeration phase has
3200 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3202 u32 dsts = dwc2_readl(hsotg, DSTS);
3203 int ep0_mps = 0, ep_mps = 8;
3206 * This should signal the finish of the enumeration phase
3207 * of the USB handshaking, so we should now know what rate
3211 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3214 * note, since we're limited by the size of transfer on EP0, and
3215 * it seems IN transfers must be a even number of packets we do
3216 * not advertise a 64byte MPS on EP0.
3219 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3220 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3221 case DSTS_ENUMSPD_FS:
3222 case DSTS_ENUMSPD_FS48:
3223 hsotg->gadget.speed = USB_SPEED_FULL;
3224 ep0_mps = EP0_MPS_LIMIT;
3228 case DSTS_ENUMSPD_HS:
3229 hsotg->gadget.speed = USB_SPEED_HIGH;
3230 ep0_mps = EP0_MPS_LIMIT;
3234 case DSTS_ENUMSPD_LS:
3235 hsotg->gadget.speed = USB_SPEED_LOW;
3239 * note, we don't actually support LS in this driver at the
3240 * moment, and the documentation seems to imply that it isn't
3241 * supported by the PHYs on some of the devices.
3245 dev_info(hsotg->dev, "new device is %s\n",
3246 usb_speed_string(hsotg->gadget.speed));
3249 * we should now know the maximum packet size for an
3250 * endpoint, so set the endpoints to a default value.
3255 /* Initialize ep0 for both in and out directions */
3256 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3257 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3258 for (i = 1; i < hsotg->num_of_eps; i++) {
3259 if (hsotg->eps_in[i])
3260 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3262 if (hsotg->eps_out[i])
3263 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3268 /* ensure after enumeration our EP0 is active */
3270 dwc2_hsotg_enqueue_setup(hsotg);
3272 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3273 dwc2_readl(hsotg, DIEPCTL0),
3274 dwc2_readl(hsotg, DOEPCTL0));
3278 * kill_all_requests - remove all requests from the endpoint's queue
3279 * @hsotg: The device state.
3280 * @ep: The endpoint the requests may be on.
3281 * @result: The result code to use.
3283 * Go through the requests on the given endpoint and mark them
3284 * completed with the given result code.
3286 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3287 struct dwc2_hsotg_ep *ep,
3294 while (!list_empty(&ep->queue)) {
3295 struct dwc2_hsotg_req *req = get_ep_head(ep);
3297 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3300 if (!hsotg->dedicated_fifos)
3302 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3303 if (size < ep->fifo_size)
3304 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3308 * dwc2_hsotg_disconnect - disconnect service
3309 * @hsotg: The device state.
3311 * The device has been disconnected. Remove all current
3312 * transactions and signal the gadget driver that this
3315 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3319 if (!hsotg->connected)
3322 hsotg->connected = 0;
3323 hsotg->test_mode = 0;
3325 /* all endpoints should be shutdown */
3326 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3327 if (hsotg->eps_in[ep])
3328 kill_all_requests(hsotg, hsotg->eps_in[ep],
3330 if (hsotg->eps_out[ep])
3331 kill_all_requests(hsotg, hsotg->eps_out[ep],
3335 call_gadget(hsotg, disconnect);
3336 hsotg->lx_state = DWC2_L3;
3338 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3342 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3343 * @hsotg: The device state:
3344 * @periodic: True if this is a periodic FIFO interrupt
3346 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3348 struct dwc2_hsotg_ep *ep;
3351 /* look through for any more data to transmit */
3352 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3353 ep = index_to_ep(hsotg, epno, 1);
3361 if ((periodic && !ep->periodic) ||
3362 (!periodic && ep->periodic))
3365 ret = dwc2_hsotg_trytx(hsotg, ep);
3371 /* IRQ flags which will trigger a retry around the IRQ loop */
3372 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3376 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3378 * dwc2_hsotg_core_init - issue softreset to the core
3379 * @hsotg: The device state
3380 * @is_usb_reset: Usb resetting flag
3382 * Issue a soft reset to the core, and await the core finishing it.
3384 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3393 /* Kill any ep0 requests as controller will be reinitialized */
3394 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3396 if (!is_usb_reset) {
3397 if (dwc2_core_reset(hsotg, true))
3400 /* all endpoints should be shutdown */
3401 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3402 if (hsotg->eps_in[ep])
3403 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3404 if (hsotg->eps_out[ep])
3405 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3410 * we must now enable ep0 ready for host detection and then
3411 * set configuration.
3414 /* keep other bits untouched (so e.g. forced modes are not lost) */
3415 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3416 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3417 usbcfg |= GUSBCFG_TOUTCAL(7);
3419 /* remove the HNP/SRP and set the PHY */
3420 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3421 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3423 dwc2_phy_init(hsotg, true);
3425 dwc2_hsotg_init_fifo(hsotg);
3428 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3430 dcfg |= DCFG_EPMISCNT(1);
3432 switch (hsotg->params.speed) {
3433 case DWC2_SPEED_PARAM_LOW:
3434 dcfg |= DCFG_DEVSPD_LS;
3436 case DWC2_SPEED_PARAM_FULL:
3437 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3438 dcfg |= DCFG_DEVSPD_FS48;
3440 dcfg |= DCFG_DEVSPD_FS;
3443 dcfg |= DCFG_DEVSPD_HS;
3446 if (hsotg->params.ipg_isoc_en)
3447 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3449 dwc2_writel(hsotg, dcfg, DCFG);
3451 /* Clear any pending OTG interrupts */
3452 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3454 /* Clear any pending interrupts */
3455 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3456 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3457 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3458 GINTSTS_USBRST | GINTSTS_RESETDET |
3459 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3460 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3461 GINTSTS_LPMTRANRCVD;
3463 if (!using_desc_dma(hsotg))
3464 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3466 if (!hsotg->params.external_id_pin_ctl)
3467 intmsk |= GINTSTS_CONIDSTSCHNG;
3469 dwc2_writel(hsotg, intmsk, GINTMSK);
3471 if (using_dma(hsotg)) {
3472 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3473 hsotg->params.ahbcfg,
3476 /* Set DDMA mode support in the core if needed */
3477 if (using_desc_dma(hsotg))
3478 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3481 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3482 (GAHBCFG_NP_TXF_EMP_LVL |
3483 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3484 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3488 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3489 * when we have no data to transfer. Otherwise we get being flooded by
3493 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3494 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3495 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3496 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3500 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3501 * DMA mode we may need this and StsPhseRcvd.
3503 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3504 DOEPMSK_STSPHSERCVDMSK) : 0) |
3505 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3509 /* Enable BNA interrupt for DDMA */
3510 if (using_desc_dma(hsotg)) {
3511 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3512 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3515 /* Enable Service Interval mode if supported */
3516 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3517 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3519 dwc2_writel(hsotg, 0, DAINTMSK);
3521 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3522 dwc2_readl(hsotg, DIEPCTL0),
3523 dwc2_readl(hsotg, DOEPCTL0));
3525 /* enable in and out endpoint interrupts */
3526 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3529 * Enable the RXFIFO when in slave mode, as this is how we collect
3530 * the data. In DMA mode, we get events from the FIFO but also
3531 * things we cannot process, so do not use it.
3533 if (!using_dma(hsotg))
3534 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3536 /* Enable interrupts for EP0 in and out */
3537 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3538 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3540 if (!is_usb_reset) {
3541 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3542 udelay(10); /* see openiboot */
3543 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3546 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3549 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3550 * writing to the EPCTL register..
3553 /* set to read 1 8byte packet */
3554 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3555 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3557 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3558 DXEPCTL_CNAK | DXEPCTL_EPENA |
3562 /* enable, but don't activate EP0in */
3563 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3564 DXEPCTL_USBACTEP, DIEPCTL0);
3566 /* clear global NAKs */
3567 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3569 val |= DCTL_SFTDISCON;
3570 dwc2_set_bit(hsotg, DCTL, val);
3572 /* configure the core to support LPM */
3573 dwc2_gadget_init_lpm(hsotg);
3575 /* program GREFCLK register if needed */
3576 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3577 dwc2_gadget_program_ref_clk(hsotg);
3579 /* must be at-least 3ms to allow bus to see disconnect */
3582 hsotg->lx_state = DWC2_L0;
3584 dwc2_hsotg_enqueue_setup(hsotg);
3586 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3587 dwc2_readl(hsotg, DIEPCTL0),
3588 dwc2_readl(hsotg, DOEPCTL0));
3591 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3593 /* set the soft-disconnect bit */
3594 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3597 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3599 /* remove the soft-disconnect and let's go */
3600 if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3601 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3605 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3606 * @hsotg: The device state:
3608 * This interrupt indicates one of the following conditions occurred while
3609 * transmitting an ISOC transaction.
3610 * - Corrupted IN Token for ISOC EP.
3611 * - Packet not complete in FIFO.
3613 * The following actions will be taken:
3614 * - Determine the EP
3615 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3617 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3619 struct dwc2_hsotg_ep *hs_ep;
3624 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3626 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3628 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3629 hs_ep = hsotg->eps_in[idx];
3630 /* Proceed only unmasked ISOC EPs */
3631 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3634 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3635 if ((epctrl & DXEPCTL_EPENA) &&
3636 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3637 epctrl |= DXEPCTL_SNAK;
3638 epctrl |= DXEPCTL_EPDIS;
3639 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3643 /* Clear interrupt */
3644 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3648 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3649 * @hsotg: The device state:
3651 * This interrupt indicates one of the following conditions occurred while
3652 * transmitting an ISOC transaction.
3653 * - Corrupted OUT Token for ISOC EP.
3654 * - Packet not complete in FIFO.
3656 * The following actions will be taken:
3657 * - Determine the EP
3658 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3660 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3666 struct dwc2_hsotg_ep *hs_ep;
3669 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3671 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3672 daintmsk >>= DAINT_OUTEP_SHIFT;
3674 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3675 hs_ep = hsotg->eps_out[idx];
3676 /* Proceed only unmasked ISOC EPs */
3677 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3680 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3681 if ((epctrl & DXEPCTL_EPENA) &&
3682 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3683 /* Unmask GOUTNAKEFF interrupt */
3684 gintmsk = dwc2_readl(hsotg, GINTMSK);
3685 gintmsk |= GINTSTS_GOUTNAKEFF;
3686 dwc2_writel(hsotg, gintmsk, GINTMSK);
3688 gintsts = dwc2_readl(hsotg, GINTSTS);
3689 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3690 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3696 /* Clear interrupt */
3697 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3701 * dwc2_hsotg_irq - handle device interrupt
3702 * @irq: The IRQ number triggered
3703 * @pw: The pw value when registered the handler.
3705 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3707 struct dwc2_hsotg *hsotg = pw;
3708 int retry_count = 8;
3712 if (!dwc2_is_device_mode(hsotg))
3715 spin_lock(&hsotg->lock);
3717 gintsts = dwc2_readl(hsotg, GINTSTS);
3718 gintmsk = dwc2_readl(hsotg, GINTMSK);
3720 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3721 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3725 if (gintsts & GINTSTS_RESETDET) {
3726 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3728 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3730 /* This event must be used only if controller is suspended */
3731 if (hsotg->lx_state == DWC2_L2) {
3732 dwc2_exit_partial_power_down(hsotg, true);
3733 hsotg->lx_state = DWC2_L0;
3737 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3738 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3739 u32 connected = hsotg->connected;
3741 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3742 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3743 dwc2_readl(hsotg, GNPTXSTS));
3745 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3747 /* Report disconnection if it is not already done. */
3748 dwc2_hsotg_disconnect(hsotg);
3750 /* Reset device address to zero */
3751 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3753 if (usb_status & GOTGCTL_BSESVLD && connected)
3754 dwc2_hsotg_core_init_disconnected(hsotg, true);
3757 if (gintsts & GINTSTS_ENUMDONE) {
3758 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3760 dwc2_hsotg_irq_enumdone(hsotg);
3763 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3764 u32 daint = dwc2_readl(hsotg, DAINT);
3765 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3766 u32 daint_out, daint_in;
3770 daint_out = daint >> DAINT_OUTEP_SHIFT;
3771 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3773 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3775 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3776 ep++, daint_out >>= 1) {
3778 dwc2_hsotg_epint(hsotg, ep, 0);
3781 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3782 ep++, daint_in >>= 1) {
3784 dwc2_hsotg_epint(hsotg, ep, 1);
3788 /* check both FIFOs */
3790 if (gintsts & GINTSTS_NPTXFEMP) {
3791 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3794 * Disable the interrupt to stop it happening again
3795 * unless one of these endpoint routines decides that
3796 * it needs re-enabling
3799 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3800 dwc2_hsotg_irq_fifoempty(hsotg, false);
3803 if (gintsts & GINTSTS_PTXFEMP) {
3804 dev_dbg(hsotg->dev, "PTxFEmp\n");
3806 /* See note in GINTSTS_NPTxFEmp */
3808 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3809 dwc2_hsotg_irq_fifoempty(hsotg, true);
3812 if (gintsts & GINTSTS_RXFLVL) {
3814 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3815 * we need to retry dwc2_hsotg_handle_rx if this is still
3819 dwc2_hsotg_handle_rx(hsotg);
3822 if (gintsts & GINTSTS_ERLYSUSP) {
3823 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3824 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3828 * these next two seem to crop-up occasionally causing the core
3829 * to shutdown the USB transfer, so try clearing them and logging
3833 if (gintsts & GINTSTS_GOUTNAKEFF) {
3838 struct dwc2_hsotg_ep *hs_ep;
3840 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3841 daintmsk >>= DAINT_OUTEP_SHIFT;
3842 /* Mask this interrupt */
3843 gintmsk = dwc2_readl(hsotg, GINTMSK);
3844 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3845 dwc2_writel(hsotg, gintmsk, GINTMSK);
3847 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3848 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3849 hs_ep = hsotg->eps_out[idx];
3850 /* Proceed only unmasked ISOC EPs */
3851 if (BIT(idx) & ~daintmsk)
3854 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3857 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3858 epctrl |= DXEPCTL_SNAK;
3859 epctrl |= DXEPCTL_EPDIS;
3860 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3865 if (hs_ep->halted) {
3866 if (!(epctrl & DXEPCTL_EPENA))
3867 epctrl |= DXEPCTL_EPENA;
3868 epctrl |= DXEPCTL_EPDIS;
3869 epctrl |= DXEPCTL_STALL;
3870 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3874 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3877 if (gintsts & GINTSTS_GINNAKEFF) {
3878 dev_info(hsotg->dev, "GINNakEff triggered\n");
3880 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3882 dwc2_hsotg_dump(hsotg);
3885 if (gintsts & GINTSTS_INCOMPL_SOIN)
3886 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3888 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3889 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3892 * if we've had fifo events, we should try and go around the
3893 * loop again to see if there's any point in returning yet.
3896 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3899 /* Check WKUP_ALERT interrupt*/
3900 if (hsotg->params.service_interval)
3901 dwc2_gadget_wkup_alert_handler(hsotg);
3903 spin_unlock(&hsotg->lock);
3908 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3909 struct dwc2_hsotg_ep *hs_ep)
3914 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3915 DOEPCTL(hs_ep->index);
3916 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3917 DOEPINT(hs_ep->index);
3919 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3922 if (hs_ep->dir_in) {
3923 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3924 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3925 /* Wait for Nak effect */
3926 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3927 DXEPINT_INEPNAKEFF, 100))
3928 dev_warn(hsotg->dev,
3929 "%s: timeout DIEPINT.NAKEFF\n",
3932 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3933 /* Wait for Nak effect */
3934 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3935 GINTSTS_GINNAKEFF, 100))
3936 dev_warn(hsotg->dev,
3937 "%s: timeout GINTSTS.GINNAKEFF\n",
3941 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3942 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3944 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3945 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3947 if (!using_dma(hsotg)) {
3948 /* Wait for GINTSTS_RXFLVL interrupt */
3949 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3950 GINTSTS_RXFLVL, 100)) {
3951 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3955 * Pop GLOBAL OUT NAK status packet from RxFIFO
3956 * to assert GOUTNAKEFF interrupt
3958 dwc2_readl(hsotg, GRXSTSP);
3962 /* Wait for global nak to take effect */
3963 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3964 GINTSTS_GOUTNAKEFF, 100))
3965 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3970 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3972 /* Wait for ep to be disabled */
3973 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3974 dev_warn(hsotg->dev,
3975 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3977 /* Clear EPDISBLD interrupt */
3978 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3980 if (hs_ep->dir_in) {
3981 unsigned short fifo_index;
3983 if (hsotg->dedicated_fifos || hs_ep->periodic)
3984 fifo_index = hs_ep->fifo_index;
3989 dwc2_flush_tx_fifo(hsotg, fifo_index);
3991 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3992 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3993 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3996 /* Remove global NAKs */
3997 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
4002 * dwc2_hsotg_ep_enable - enable the given endpoint
4003 * @ep: The USB endpint to configure
4004 * @desc: The USB endpoint descriptor to configure with.
4006 * This is called from the USB gadget code's usb_ep_enable().
4008 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
4009 const struct usb_endpoint_descriptor *desc)
4011 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4012 struct dwc2_hsotg *hsotg = hs_ep->parent;
4013 unsigned long flags;
4014 unsigned int index = hs_ep->index;
4020 unsigned int dir_in;
4021 unsigned int i, val, size;
4023 unsigned char ep_type;
4027 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4028 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4029 desc->wMaxPacketSize, desc->bInterval);
4031 /* not to be called for EP0 */
4033 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4037 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4038 if (dir_in != hs_ep->dir_in) {
4039 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4043 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4044 mps = usb_endpoint_maxp(desc);
4045 mc = usb_endpoint_maxp_mult(desc);
4047 /* ISOC IN in DDMA supported bInterval up to 10 */
4048 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4049 dir_in && desc->bInterval > 10) {
4051 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4055 /* High bandwidth ISOC OUT in DDMA not supported */
4056 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4057 !dir_in && mc > 1) {
4059 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4063 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4065 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4066 epctrl = dwc2_readl(hsotg, epctrl_reg);
4068 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4069 __func__, epctrl, epctrl_reg);
4071 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4072 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4074 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4076 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4077 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4078 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4079 desc_num * sizeof(struct dwc2_dma_desc),
4080 &hs_ep->desc_list_dma, GFP_ATOMIC);
4081 if (!hs_ep->desc_list) {
4087 spin_lock_irqsave(&hsotg->lock, flags);
4089 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4090 epctrl |= DXEPCTL_MPS(mps);
4093 * mark the endpoint as active, otherwise the core may ignore
4094 * transactions entirely for this endpoint
4096 epctrl |= DXEPCTL_USBACTEP;
4098 /* update the endpoint state */
4099 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4101 /* default, set to non-periodic */
4102 hs_ep->isochronous = 0;
4103 hs_ep->periodic = 0;
4105 hs_ep->interval = desc->bInterval;
4108 case USB_ENDPOINT_XFER_ISOC:
4109 epctrl |= DXEPCTL_EPTYPE_ISO;
4110 epctrl |= DXEPCTL_SETEVENFR;
4111 hs_ep->isochronous = 1;
4112 hs_ep->interval = 1 << (desc->bInterval - 1);
4113 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4114 hs_ep->next_desc = 0;
4115 hs_ep->compl_desc = 0;
4117 hs_ep->periodic = 1;
4118 mask = dwc2_readl(hsotg, DIEPMSK);
4119 mask |= DIEPMSK_NAKMSK;
4120 dwc2_writel(hsotg, mask, DIEPMSK);
4122 epctrl |= DXEPCTL_SNAK;
4123 mask = dwc2_readl(hsotg, DOEPMSK);
4124 mask |= DOEPMSK_OUTTKNEPDISMSK;
4125 dwc2_writel(hsotg, mask, DOEPMSK);
4129 case USB_ENDPOINT_XFER_BULK:
4130 epctrl |= DXEPCTL_EPTYPE_BULK;
4133 case USB_ENDPOINT_XFER_INT:
4135 hs_ep->periodic = 1;
4137 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4138 hs_ep->interval = 1 << (desc->bInterval - 1);
4140 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4143 case USB_ENDPOINT_XFER_CONTROL:
4144 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4149 * if the hardware has dedicated fifos, we must give each IN EP
4150 * a unique tx-fifo even if it is non-periodic.
4152 if (dir_in && hsotg->dedicated_fifos) {
4153 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4155 u32 fifo_size = UINT_MAX;
4157 size = hs_ep->ep.maxpacket * hs_ep->mc;
4158 for (i = 1; i <= fifo_count; ++i) {
4159 if (hsotg->fifo_map & (1 << i))
4161 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4162 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4165 /* Search for smallest acceptable fifo */
4166 if (val < fifo_size) {
4173 "%s: No suitable fifo found\n", __func__);
4177 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4178 hsotg->fifo_map |= 1 << fifo_index;
4179 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4180 hs_ep->fifo_index = fifo_index;
4181 hs_ep->fifo_size = fifo_size;
4184 /* for non control endpoints, set PID to D0 */
4185 if (index && !hs_ep->isochronous)
4186 epctrl |= DXEPCTL_SETD0PID;
4188 /* WA for Full speed ISOC IN in DDMA mode.
4189 * By Clear NAK status of EP, core will send ZLP
4190 * to IN token and assert NAK interrupt relying
4191 * on TxFIFO status only
4194 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4195 hs_ep->isochronous && dir_in) {
4196 /* The WA applies only to core versions from 2.72a
4197 * to 4.00a (including both). Also for FS_IOT_1.00a
4200 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4202 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4203 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4204 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4205 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4206 epctrl |= DXEPCTL_CNAK;
4209 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4212 dwc2_writel(hsotg, epctrl, epctrl_reg);
4213 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4214 __func__, dwc2_readl(hsotg, epctrl_reg));
4216 /* enable the endpoint interrupt */
4217 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4220 spin_unlock_irqrestore(&hsotg->lock, flags);
4223 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4224 dmam_free_coherent(hsotg->dev, desc_num *
4225 sizeof(struct dwc2_dma_desc),
4226 hs_ep->desc_list, hs_ep->desc_list_dma);
4227 hs_ep->desc_list = NULL;
4234 * dwc2_hsotg_ep_disable - disable given endpoint
4235 * @ep: The endpoint to disable.
4237 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4239 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4240 struct dwc2_hsotg *hsotg = hs_ep->parent;
4241 int dir_in = hs_ep->dir_in;
4242 int index = hs_ep->index;
4246 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4248 if (ep == &hsotg->eps_out[0]->ep) {
4249 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4253 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4254 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4258 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4260 ctrl = dwc2_readl(hsotg, epctrl_reg);
4262 if (ctrl & DXEPCTL_EPENA)
4263 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4265 ctrl &= ~DXEPCTL_EPENA;
4266 ctrl &= ~DXEPCTL_USBACTEP;
4267 ctrl |= DXEPCTL_SNAK;
4269 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4270 dwc2_writel(hsotg, ctrl, epctrl_reg);
4272 /* disable endpoint interrupts */
4273 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4275 /* terminate all requests with shutdown */
4276 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4278 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4279 hs_ep->fifo_index = 0;
4280 hs_ep->fifo_size = 0;
4285 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4287 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4288 struct dwc2_hsotg *hsotg = hs_ep->parent;
4289 unsigned long flags;
4292 spin_lock_irqsave(&hsotg->lock, flags);
4293 ret = dwc2_hsotg_ep_disable(ep);
4294 spin_unlock_irqrestore(&hsotg->lock, flags);
4299 * on_list - check request is on the given endpoint
4300 * @ep: The endpoint to check.
4301 * @test: The request to test if it is on the endpoint.
4303 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4305 struct dwc2_hsotg_req *req, *treq;
4307 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4316 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4317 * @ep: The endpoint to dequeue.
4318 * @req: The request to be removed from a queue.
4320 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4322 struct dwc2_hsotg_req *hs_req = our_req(req);
4323 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4324 struct dwc2_hsotg *hs = hs_ep->parent;
4325 unsigned long flags;
4327 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4329 spin_lock_irqsave(&hs->lock, flags);
4331 if (!on_list(hs_ep, hs_req)) {
4332 spin_unlock_irqrestore(&hs->lock, flags);
4336 /* Dequeue already started request */
4337 if (req == &hs_ep->req->req)
4338 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4340 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4341 spin_unlock_irqrestore(&hs->lock, flags);
4347 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4348 * @ep: The endpoint to set halt.
4349 * @value: Set or unset the halt.
4350 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4351 * the endpoint is busy processing requests.
4353 * We need to stall the endpoint immediately if request comes from set_feature
4354 * protocol command handler.
4356 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4358 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4359 struct dwc2_hsotg *hs = hs_ep->parent;
4360 int index = hs_ep->index;
4365 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4369 dwc2_hsotg_stall_ep0(hs);
4372 "%s: can't clear halt on ep0\n", __func__);
4376 if (hs_ep->isochronous) {
4377 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4381 if (!now && value && !list_empty(&hs_ep->queue)) {
4382 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4387 if (hs_ep->dir_in) {
4388 epreg = DIEPCTL(index);
4389 epctl = dwc2_readl(hs, epreg);
4392 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4393 if (epctl & DXEPCTL_EPENA)
4394 epctl |= DXEPCTL_EPDIS;
4396 epctl &= ~DXEPCTL_STALL;
4397 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4398 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4399 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4400 epctl |= DXEPCTL_SETD0PID;
4402 dwc2_writel(hs, epctl, epreg);
4404 epreg = DOEPCTL(index);
4405 epctl = dwc2_readl(hs, epreg);
4408 /* Unmask GOUTNAKEFF interrupt */
4409 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4411 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4412 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4413 // STALL bit will be set in GOUTNAKEFF interrupt handler
4415 epctl &= ~DXEPCTL_STALL;
4416 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4417 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4418 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4419 epctl |= DXEPCTL_SETD0PID;
4420 dwc2_writel(hs, epctl, epreg);
4424 hs_ep->halted = value;
4429 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4430 * @ep: The endpoint to set halt.
4431 * @value: Set or unset the halt.
4433 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4435 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4436 struct dwc2_hsotg *hs = hs_ep->parent;
4437 unsigned long flags = 0;
4440 spin_lock_irqsave(&hs->lock, flags);
4441 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4442 spin_unlock_irqrestore(&hs->lock, flags);
4447 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4448 .enable = dwc2_hsotg_ep_enable,
4449 .disable = dwc2_hsotg_ep_disable_lock,
4450 .alloc_request = dwc2_hsotg_ep_alloc_request,
4451 .free_request = dwc2_hsotg_ep_free_request,
4452 .queue = dwc2_hsotg_ep_queue_lock,
4453 .dequeue = dwc2_hsotg_ep_dequeue,
4454 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4455 /* note, don't believe we have any call for the fifo routines */
4459 * dwc2_hsotg_init - initialize the usb core
4460 * @hsotg: The driver state
4462 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4464 /* unmask subset of endpoint interrupts */
4466 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4467 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4470 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4471 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4474 dwc2_writel(hsotg, 0, DAINTMSK);
4476 /* Be in disconnected state until gadget is registered */
4477 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4481 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4482 dwc2_readl(hsotg, GRXFSIZ),
4483 dwc2_readl(hsotg, GNPTXFSIZ));
4485 dwc2_hsotg_init_fifo(hsotg);
4487 if (using_dma(hsotg))
4488 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4492 * dwc2_hsotg_udc_start - prepare the udc for work
4493 * @gadget: The usb gadget state
4494 * @driver: The usb gadget driver
4496 * Perform initialization to prepare udc device and driver
4499 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4500 struct usb_gadget_driver *driver)
4502 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4503 unsigned long flags;
4507 pr_err("%s: called with no device\n", __func__);
4512 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4516 if (driver->max_speed < USB_SPEED_FULL)
4517 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4519 if (!driver->setup) {
4520 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4524 WARN_ON(hsotg->driver);
4526 hsotg->driver = driver;
4527 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4528 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4530 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4531 ret = dwc2_lowlevel_hw_enable(hsotg);
4536 if (!IS_ERR_OR_NULL(hsotg->uphy))
4537 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4539 spin_lock_irqsave(&hsotg->lock, flags);
4540 if (dwc2_hw_is_device(hsotg)) {
4541 dwc2_hsotg_init(hsotg);
4542 dwc2_hsotg_core_init_disconnected(hsotg, false);
4546 spin_unlock_irqrestore(&hsotg->lock, flags);
4548 gadget->sg_supported = using_desc_dma(hsotg);
4549 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4554 hsotg->driver = NULL;
4559 * dwc2_hsotg_udc_stop - stop the udc
4560 * @gadget: The usb gadget state
4562 * Stop udc hw block and stay tunned for future transmissions
4564 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4566 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4567 unsigned long flags = 0;
4573 /* all endpoints should be shutdown */
4574 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4575 if (hsotg->eps_in[ep])
4576 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4577 if (hsotg->eps_out[ep])
4578 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4581 spin_lock_irqsave(&hsotg->lock, flags);
4583 hsotg->driver = NULL;
4584 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4587 spin_unlock_irqrestore(&hsotg->lock, flags);
4589 if (!IS_ERR_OR_NULL(hsotg->uphy))
4590 otg_set_peripheral(hsotg->uphy->otg, NULL);
4592 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4593 dwc2_lowlevel_hw_disable(hsotg);
4599 * dwc2_hsotg_gadget_getframe - read the frame number
4600 * @gadget: The usb gadget state
4602 * Read the {micro} frame number
4604 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4606 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4610 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4611 * @gadget: The usb gadget state
4612 * @is_selfpowered: Whether the device is self-powered
4614 * Set if the device is self or bus powered.
4616 static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4619 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4620 unsigned long flags;
4622 spin_lock_irqsave(&hsotg->lock, flags);
4623 gadget->is_selfpowered = !!is_selfpowered;
4624 spin_unlock_irqrestore(&hsotg->lock, flags);
4630 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4631 * @gadget: The usb gadget state
4632 * @is_on: Current state of the USB PHY
4634 * Connect/Disconnect the USB PHY pullup
4636 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4638 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4639 unsigned long flags = 0;
4641 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4644 /* Don't modify pullup state while in host mode */
4645 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4646 hsotg->enabled = is_on;
4650 spin_lock_irqsave(&hsotg->lock, flags);
4653 dwc2_hsotg_core_init_disconnected(hsotg, false);
4654 /* Enable ACG feature in device mode,if supported */
4655 dwc2_enable_acg(hsotg);
4656 dwc2_hsotg_core_connect(hsotg);
4658 dwc2_hsotg_core_disconnect(hsotg);
4659 dwc2_hsotg_disconnect(hsotg);
4663 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4664 spin_unlock_irqrestore(&hsotg->lock, flags);
4669 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4671 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4672 unsigned long flags;
4674 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4675 spin_lock_irqsave(&hsotg->lock, flags);
4678 * If controller is hibernated, it must exit from power_down
4679 * before being initialized / de-initialized
4681 if (hsotg->lx_state == DWC2_L2)
4682 dwc2_exit_partial_power_down(hsotg, false);
4685 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4687 dwc2_hsotg_core_init_disconnected(hsotg, false);
4688 if (hsotg->enabled) {
4689 /* Enable ACG feature in device mode,if supported */
4690 dwc2_enable_acg(hsotg);
4691 dwc2_hsotg_core_connect(hsotg);
4694 dwc2_hsotg_core_disconnect(hsotg);
4695 dwc2_hsotg_disconnect(hsotg);
4698 spin_unlock_irqrestore(&hsotg->lock, flags);
4703 * dwc2_hsotg_vbus_draw - report bMaxPower field
4704 * @gadget: The usb gadget state
4705 * @mA: Amount of current
4707 * Report how much power the device may consume to the phy.
4709 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4711 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4713 if (IS_ERR_OR_NULL(hsotg->uphy))
4715 return usb_phy_set_power(hsotg->uphy, mA);
4718 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4719 .get_frame = dwc2_hsotg_gadget_getframe,
4720 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4721 .udc_start = dwc2_hsotg_udc_start,
4722 .udc_stop = dwc2_hsotg_udc_stop,
4723 .pullup = dwc2_hsotg_pullup,
4724 .vbus_session = dwc2_hsotg_vbus_session,
4725 .vbus_draw = dwc2_hsotg_vbus_draw,
4729 * dwc2_hsotg_initep - initialise a single endpoint
4730 * @hsotg: The device state.
4731 * @hs_ep: The endpoint to be initialised.
4732 * @epnum: The endpoint number
4733 * @dir_in: True if direction is in.
4735 * Initialise the given endpoint (as part of the probe and device state
4736 * creation) to give to the gadget driver. Setup the endpoint name, any
4737 * direction information and other state that may be required.
4739 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4740 struct dwc2_hsotg_ep *hs_ep,
4753 hs_ep->dir_in = dir_in;
4754 hs_ep->index = epnum;
4756 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4758 INIT_LIST_HEAD(&hs_ep->queue);
4759 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4761 /* add to the list of endpoints known by the gadget driver */
4763 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4765 hs_ep->parent = hsotg;
4766 hs_ep->ep.name = hs_ep->name;
4768 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4769 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4771 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4772 epnum ? 1024 : EP0_MPS_LIMIT);
4773 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4776 hs_ep->ep.caps.type_control = true;
4778 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4779 hs_ep->ep.caps.type_iso = true;
4780 hs_ep->ep.caps.type_bulk = true;
4782 hs_ep->ep.caps.type_int = true;
4786 hs_ep->ep.caps.dir_in = true;
4788 hs_ep->ep.caps.dir_out = true;
4791 * if we're using dma, we need to set the next-endpoint pointer
4792 * to be something valid.
4795 if (using_dma(hsotg)) {
4796 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4799 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4801 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4806 * dwc2_hsotg_hw_cfg - read HW configuration registers
4807 * @hsotg: Programming view of the DWC_otg controller
4809 * Read the USB core HW configuration registers
4811 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4817 /* check hardware configuration */
4819 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4822 hsotg->num_of_eps++;
4824 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4825 sizeof(struct dwc2_hsotg_ep),
4827 if (!hsotg->eps_in[0])
4829 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4830 hsotg->eps_out[0] = hsotg->eps_in[0];
4832 cfg = hsotg->hw_params.dev_ep_dirs;
4833 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4835 /* Direction in or both */
4836 if (!(ep_type & 2)) {
4837 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4838 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4839 if (!hsotg->eps_in[i])
4842 /* Direction out or both */
4843 if (!(ep_type & 1)) {
4844 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4845 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4846 if (!hsotg->eps_out[i])
4851 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4852 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4854 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4856 hsotg->dedicated_fifos ? "dedicated" : "shared",
4862 * dwc2_hsotg_dump - dump state of the udc
4863 * @hsotg: Programming view of the DWC_otg controller
4866 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4869 struct device *dev = hsotg->dev;
4873 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4874 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4875 dwc2_readl(hsotg, DIEPMSK));
4877 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4878 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4880 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4881 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4883 /* show periodic fifo settings */
4885 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4886 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4887 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4888 val >> FIFOSIZE_DEPTH_SHIFT,
4889 val & FIFOSIZE_STARTADDR_MASK);
4892 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4894 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4895 dwc2_readl(hsotg, DIEPCTL(idx)),
4896 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4897 dwc2_readl(hsotg, DIEPDMA(idx)));
4899 val = dwc2_readl(hsotg, DOEPCTL(idx));
4901 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4902 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4903 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4904 dwc2_readl(hsotg, DOEPDMA(idx)));
4907 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4908 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4913 * dwc2_gadget_init - init function for gadget
4914 * @hsotg: Programming view of the DWC_otg controller
4917 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4919 struct device *dev = hsotg->dev;
4923 /* Dump fifo information */
4924 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4925 hsotg->params.g_np_tx_fifo_size);
4926 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4928 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4929 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4930 hsotg->gadget.name = dev_name(dev);
4931 hsotg->remote_wakeup_allowed = 0;
4933 if (hsotg->params.lpm)
4934 hsotg->gadget.lpm_capable = true;
4936 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4937 hsotg->gadget.is_otg = 1;
4938 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4939 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4941 ret = dwc2_hsotg_hw_cfg(hsotg);
4943 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
4947 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
4948 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4949 if (!hsotg->ctrl_buff)
4952 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
4953 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
4954 if (!hsotg->ep0_buff)
4957 if (using_desc_dma(hsotg)) {
4958 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
4963 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
4964 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
4966 dev_err(dev, "cannot claim IRQ for gadget\n");
4970 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4972 if (hsotg->num_of_eps == 0) {
4973 dev_err(dev, "wrong number of EPs (zero)\n");
4977 /* setup endpoint information */
4979 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
4980 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
4982 /* allocate EP0 request */
4984 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
4986 if (!hsotg->ctrl_req) {
4987 dev_err(dev, "failed to allocate ctrl req\n");
4991 /* initialise the endpoints now the core has been initialised */
4992 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
4993 if (hsotg->eps_in[epnum])
4994 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
4996 if (hsotg->eps_out[epnum])
4997 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5001 dwc2_hsotg_dump(hsotg);
5007 * dwc2_hsotg_remove - remove function for hsotg driver
5008 * @hsotg: Programming view of the DWC_otg controller
5011 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5013 usb_del_gadget_udc(&hsotg->gadget);
5014 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5019 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5021 unsigned long flags;
5023 if (hsotg->lx_state != DWC2_L0)
5026 if (hsotg->driver) {
5029 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5030 hsotg->driver->driver.name);
5032 spin_lock_irqsave(&hsotg->lock, flags);
5034 dwc2_hsotg_core_disconnect(hsotg);
5035 dwc2_hsotg_disconnect(hsotg);
5036 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5037 spin_unlock_irqrestore(&hsotg->lock, flags);
5039 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
5040 if (hsotg->eps_in[ep])
5041 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5042 if (hsotg->eps_out[ep])
5043 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5050 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5052 unsigned long flags;
5054 if (hsotg->lx_state == DWC2_L2)
5057 if (hsotg->driver) {
5058 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5059 hsotg->driver->driver.name);
5061 spin_lock_irqsave(&hsotg->lock, flags);
5062 dwc2_hsotg_core_init_disconnected(hsotg, false);
5063 if (hsotg->enabled) {
5064 /* Enable ACG feature in device mode,if supported */
5065 dwc2_enable_acg(hsotg);
5066 dwc2_hsotg_core_connect(hsotg);
5068 spin_unlock_irqrestore(&hsotg->lock, flags);
5075 * dwc2_backup_device_registers() - Backup controller device registers.
5076 * When suspending usb bus, registers needs to be backuped
5077 * if controller power is disabled once suspended.
5079 * @hsotg: Programming view of the DWC_otg controller
5081 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5083 struct dwc2_dregs_backup *dr;
5086 dev_dbg(hsotg->dev, "%s\n", __func__);
5088 /* Backup dev regs */
5089 dr = &hsotg->dr_backup;
5091 dr->dcfg = dwc2_readl(hsotg, DCFG);
5092 dr->dctl = dwc2_readl(hsotg, DCTL);
5093 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5094 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5095 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5097 for (i = 0; i < hsotg->num_of_eps; i++) {
5099 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5101 /* Ensure DATA PID is correctly configured */
5102 if (dr->diepctl[i] & DXEPCTL_DPID)
5103 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5105 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5107 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5108 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5110 /* Backup OUT EPs */
5111 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5113 /* Ensure DATA PID is correctly configured */
5114 if (dr->doepctl[i] & DXEPCTL_DPID)
5115 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5117 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5119 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5120 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5121 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5128 * dwc2_restore_device_registers() - Restore controller device registers.
5129 * When resuming usb bus, device registers needs to be restored
5130 * if controller power were disabled.
5132 * @hsotg: Programming view of the DWC_otg controller
5133 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5135 * Return: 0 if successful, negative error code otherwise
5137 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5139 struct dwc2_dregs_backup *dr;
5142 dev_dbg(hsotg->dev, "%s\n", __func__);
5144 /* Restore dev regs */
5145 dr = &hsotg->dr_backup;
5147 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5154 dwc2_writel(hsotg, dr->dctl, DCTL);
5156 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5157 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5158 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5160 for (i = 0; i < hsotg->num_of_eps; i++) {
5161 /* Restore IN EPs */
5162 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5163 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5164 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5165 /** WA for enabled EPx's IN in DDMA mode. On entering to
5166 * hibernation wrong value read and saved from DIEPDMAx,
5167 * as result BNA interrupt asserted on hibernation exit
5168 * by restoring from saved area.
5170 if (hsotg->params.g_dma_desc &&
5171 (dr->diepctl[i] & DXEPCTL_EPENA))
5172 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5173 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5174 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5175 /* Restore OUT EPs */
5176 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5177 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5178 * hibernation wrong value read and saved from DOEPDMAx,
5179 * as result BNA interrupt asserted on hibernation exit
5180 * by restoring from saved area.
5182 if (hsotg->params.g_dma_desc &&
5183 (dr->doepctl[i] & DXEPCTL_EPENA))
5184 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5185 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5186 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5193 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5195 * @hsotg: Programming view of DWC_otg controller
5198 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5202 if (!hsotg->params.lpm)
5205 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5206 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5207 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5208 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5209 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5210 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5211 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5212 dwc2_writel(hsotg, val, GLPMCFG);
5213 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5215 /* Unmask WKUP_ALERT Interrupt */
5216 if (hsotg->params.service_interval)
5217 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5221 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5223 * @hsotg: Programming view of DWC_otg controller
5226 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5230 val |= GREFCLK_REF_CLK_MODE;
5231 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5232 val |= hsotg->params.sof_cnt_wkup_alert <<
5233 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5235 dwc2_writel(hsotg, val, GREFCLK);
5236 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5240 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5242 * @hsotg: Programming view of the DWC_otg controller
5244 * Return non-zero if failed to enter to hibernation.
5246 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5251 /* Change to L2(suspend) state */
5252 hsotg->lx_state = DWC2_L2;
5253 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5254 ret = dwc2_backup_global_registers(hsotg);
5256 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5260 ret = dwc2_backup_device_registers(hsotg);
5262 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5267 gpwrdn = GPWRDN_PWRDNRSTN;
5268 gpwrdn |= GPWRDN_PMUACTV;
5269 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5272 /* Set flag to indicate that we are in hibernation */
5273 hsotg->hibernated = 1;
5275 /* Enable interrupts from wake up logic */
5276 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5277 gpwrdn |= GPWRDN_PMUINTSEL;
5278 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5281 /* Unmask device mode interrupts in GPWRDN */
5282 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5283 gpwrdn |= GPWRDN_RST_DET_MSK;
5284 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5285 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5286 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5289 /* Enable Power Down Clamp */
5290 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5291 gpwrdn |= GPWRDN_PWRDNCLMP;
5292 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5295 /* Switch off VDD */
5296 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5297 gpwrdn |= GPWRDN_PWRDNSWTCH;
5298 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5301 /* Save gpwrdn register for further usage if stschng interrupt */
5302 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5303 dev_dbg(hsotg->dev, "Hibernation completed\n");
5309 * dwc2_gadget_exit_hibernation()
5310 * This function is for exiting from Device mode hibernation by host initiated
5311 * resume/reset and device initiated remote-wakeup.
5313 * @hsotg: Programming view of the DWC_otg controller
5314 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5315 * @reset: indicates whether resume is initiated by Reset.
5317 * Return non-zero if failed to exit from hibernation.
5319 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5320 int rem_wakeup, int reset)
5326 struct dwc2_gregs_backup *gr;
5327 struct dwc2_dregs_backup *dr;
5329 gr = &hsotg->gr_backup;
5330 dr = &hsotg->dr_backup;
5332 if (!hsotg->hibernated) {
5333 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5337 "%s: called with rem_wakeup = %d reset = %d\n",
5338 __func__, rem_wakeup, reset);
5340 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5343 /* Clear all pending interupts */
5344 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5347 /* De-assert Restore */
5348 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5349 gpwrdn &= ~GPWRDN_RESTORE;
5350 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5354 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5355 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5356 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5359 /* Restore GUSBCFG, DCFG and DCTL */
5360 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5361 dwc2_writel(hsotg, dr->dcfg, DCFG);
5362 dwc2_writel(hsotg, dr->dctl, DCTL);
5364 /* De-assert Wakeup Logic */
5365 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5366 gpwrdn &= ~GPWRDN_PMUACTV;
5367 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5371 /* Start Remote Wakeup Signaling */
5372 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5375 /* Set Device programming done bit */
5376 dctl = dwc2_readl(hsotg, DCTL);
5377 dctl |= DCTL_PWRONPRGDONE;
5378 dwc2_writel(hsotg, dctl, DCTL);
5380 /* Wait for interrupts which must be cleared */
5382 /* Clear all pending interupts */
5383 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5385 /* Restore global registers */
5386 ret = dwc2_restore_global_registers(hsotg);
5388 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5393 /* Restore device registers */
5394 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5396 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5403 dctl = dwc2_readl(hsotg, DCTL);
5404 dctl &= ~DCTL_RMTWKUPSIG;
5405 dwc2_writel(hsotg, dctl, DCTL);
5408 hsotg->hibernated = 0;
5409 hsotg->lx_state = DWC2_L0;
5410 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");