1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
28 #include <linux/usb/phy.h>
29 #include <linux/usb/composite.h>
35 /* conversion functions */
36 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
38 return container_of(req, struct dwc2_hsotg_req, req);
41 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
43 return container_of(ep, struct dwc2_hsotg_ep, ep);
46 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
48 return container_of(gadget, struct dwc2_hsotg, gadget);
51 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
53 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
56 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
58 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
61 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
62 u32 ep_index, u32 dir_in)
65 return hsotg->eps_in[ep_index];
67 return hsotg->eps_out[ep_index];
70 /* forward declaration of functions */
71 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
74 * using_dma - return the DMA status of the driver.
75 * @hsotg: The driver state.
77 * Return true if we're using DMA.
79 * Currently, we have the DMA support code worked into everywhere
80 * that needs it, but the AMBA DMA implementation in the hardware can
81 * only DMA from 32bit aligned addresses. This means that gadgets such
82 * as the CDC Ethernet cannot work as they often pass packets which are
85 * Unfortunately the choice to use DMA or not is global to the controller
86 * and seems to be only settable when the controller is being put through
87 * a core reset. This means we either need to fix the gadgets to take
88 * account of DMA alignment, or add bounce buffers (yuerk).
90 * g_using_dma is set depending on dts flag.
92 static inline bool using_dma(struct dwc2_hsotg *hsotg)
94 return hsotg->params.g_dma;
98 * using_desc_dma - return the descriptor DMA status of the driver.
99 * @hsotg: The driver state.
101 * Return true if we're using descriptor DMA.
103 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
105 return hsotg->params.g_dma_desc;
109 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
110 * @hs_ep: The endpoint
112 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
113 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
117 struct dwc2_hsotg *hsotg = hs_ep->parent;
118 u16 limit = DSTS_SOFFN_LIMIT;
120 if (hsotg->gadget.speed != USB_SPEED_HIGH)
123 hs_ep->target_frame += hs_ep->interval;
124 if (hs_ep->target_frame > limit) {
125 hs_ep->frame_overrun = true;
126 hs_ep->target_frame &= limit;
128 hs_ep->frame_overrun = false;
133 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
135 * @hs_ep: The endpoint.
137 * This function used in service interval based scheduling flow to calculate
138 * descriptor frame number filed value. For service interval mode frame
139 * number in descriptor should point to last (u)frame in the interval.
142 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
144 struct dwc2_hsotg *hsotg = hs_ep->parent;
145 u16 limit = DSTS_SOFFN_LIMIT;
147 if (hsotg->gadget.speed != USB_SPEED_HIGH)
150 if (hs_ep->target_frame)
151 hs_ep->target_frame -= 1;
153 hs_ep->target_frame = limit;
157 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
158 * @hsotg: The device state
159 * @ints: A bitmask of the interrupts to enable
161 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
163 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
166 new_gsintmsk = gsintmsk | ints;
168 if (new_gsintmsk != gsintmsk) {
169 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
170 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
175 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
176 * @hsotg: The device state
177 * @ints: A bitmask of the interrupts to enable
179 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
181 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
184 new_gsintmsk = gsintmsk & ~ints;
186 if (new_gsintmsk != gsintmsk)
187 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
191 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
192 * @hsotg: The device state
193 * @ep: The endpoint index
194 * @dir_in: True if direction is in.
195 * @en: The enable value, true to enable
197 * Set or clear the mask for an individual endpoint's interrupt
200 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
201 unsigned int ep, unsigned int dir_in,
211 local_irq_save(flags);
212 daint = dwc2_readl(hsotg, DAINTMSK);
217 dwc2_writel(hsotg, daint, DAINTMSK);
218 local_irq_restore(flags);
222 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
224 * @hsotg: Programming view of the DWC_otg controller
226 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
228 if (hsotg->hw_params.en_multiple_tx_fifo)
229 /* In dedicated FIFO mode we need count of IN EPs */
230 return hsotg->hw_params.num_dev_in_eps;
232 /* In shared FIFO mode we need count of Periodic IN EPs */
233 return hsotg->hw_params.num_dev_perio_in_ep;
237 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
238 * device mode TX FIFOs
240 * @hsotg: Programming view of the DWC_otg controller
242 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
248 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
249 hsotg->params.g_np_tx_fifo_size);
251 /* Get Endpoint Info Control block size in DWORDs. */
252 tx_addr_max = hsotg->hw_params.total_fifo_size;
254 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
255 if (tx_addr_max <= addr)
258 return tx_addr_max - addr;
262 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
264 * @hsotg: Programming view of the DWC_otg controller
267 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
272 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
273 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
274 gintsts2 &= gintmsk2;
276 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
277 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
278 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
279 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
284 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
287 * @hsotg: Programming view of the DWC_otg controller
289 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
294 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
296 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
299 return tx_fifo_depth;
301 return tx_fifo_depth / tx_fifo_count;
305 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
306 * @hsotg: The device instance.
308 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
315 u32 *txfsz = hsotg->params.g_tx_fifo_size;
317 /* Reset fifo map if not correctly cleared during previous session */
318 WARN_ON(hsotg->fifo_map);
321 /* set RX/NPTX FIFO sizes */
322 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
323 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
324 FIFOSIZE_STARTADDR_SHIFT) |
325 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
329 * arange all the rest of the TX FIFOs, as some versions of this
330 * block have overlapping default addresses. This also ensures
331 * that if the settings have been changed, then they are set to
335 /* start at the end of the GNPTXFSIZ, rounded up */
336 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
339 * Configure fifos sizes from provided configuration and assign
340 * them to endpoints dynamically according to maxpacket size value of
343 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
347 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
348 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
349 "insufficient fifo memory");
352 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
353 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
356 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
357 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
360 * according to p428 of the design guide, we need to ensure that
361 * all fifos are flushed before continuing
364 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
365 GRSTCTL_RXFFLSH, GRSTCTL);
367 /* wait until the fifos are both flushed */
370 val = dwc2_readl(hsotg, GRSTCTL);
372 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
375 if (--timeout == 0) {
377 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
385 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
389 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
390 * @ep: USB endpoint to allocate request for.
391 * @flags: Allocation flags
393 * Allocate a new USB request structure appropriate for the specified endpoint
395 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
398 struct dwc2_hsotg_req *req;
400 req = kzalloc(sizeof(*req), flags);
404 INIT_LIST_HEAD(&req->queue);
410 * is_ep_periodic - return true if the endpoint is in periodic mode.
411 * @hs_ep: The endpoint to query.
413 * Returns true if the endpoint is in periodic mode, meaning it is being
414 * used for an Interrupt or ISO transfer.
416 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
418 return hs_ep->periodic;
422 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
423 * @hsotg: The device state.
424 * @hs_ep: The endpoint for the request
425 * @hs_req: The request being processed.
427 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
428 * of a request to ensure the buffer is ready for access by the caller.
430 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
431 struct dwc2_hsotg_ep *hs_ep,
432 struct dwc2_hsotg_req *hs_req)
434 struct usb_request *req = &hs_req->req;
436 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
440 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
441 * for Control endpoint
442 * @hsotg: The device state.
444 * This function will allocate 4 descriptor chains for EP 0: 2 for
445 * Setup stage, per one for IN and OUT data/status transactions.
447 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
449 hsotg->setup_desc[0] =
450 dmam_alloc_coherent(hsotg->dev,
451 sizeof(struct dwc2_dma_desc),
452 &hsotg->setup_desc_dma[0],
454 if (!hsotg->setup_desc[0])
457 hsotg->setup_desc[1] =
458 dmam_alloc_coherent(hsotg->dev,
459 sizeof(struct dwc2_dma_desc),
460 &hsotg->setup_desc_dma[1],
462 if (!hsotg->setup_desc[1])
465 hsotg->ctrl_in_desc =
466 dmam_alloc_coherent(hsotg->dev,
467 sizeof(struct dwc2_dma_desc),
468 &hsotg->ctrl_in_desc_dma,
470 if (!hsotg->ctrl_in_desc)
473 hsotg->ctrl_out_desc =
474 dmam_alloc_coherent(hsotg->dev,
475 sizeof(struct dwc2_dma_desc),
476 &hsotg->ctrl_out_desc_dma,
478 if (!hsotg->ctrl_out_desc)
488 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
489 * @hsotg: The controller state.
490 * @hs_ep: The endpoint we're going to write for.
491 * @hs_req: The request to write data for.
493 * This is called when the TxFIFO has some space in it to hold a new
494 * transmission and we have something to give it. The actual setup of
495 * the data size is done elsewhere, so all we have to do is to actually
498 * The return value is zero if there is more space (or nothing was done)
499 * otherwise -ENOSPC is returned if the FIFO space was used up.
501 * This routine is only needed for PIO
503 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
504 struct dwc2_hsotg_ep *hs_ep,
505 struct dwc2_hsotg_req *hs_req)
507 bool periodic = is_ep_periodic(hs_ep);
508 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
509 int buf_pos = hs_req->req.actual;
510 int to_write = hs_ep->size_loaded;
516 to_write -= (buf_pos - hs_ep->last_load);
518 /* if there's nothing to write, get out early */
522 if (periodic && !hsotg->dedicated_fifos) {
523 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
528 * work out how much data was loaded so we can calculate
529 * how much data is left in the fifo.
532 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
535 * if shared fifo, we cannot write anything until the
536 * previous data has been completely sent.
538 if (hs_ep->fifo_load != 0) {
539 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
543 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
545 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
547 /* how much of the data has moved */
548 size_done = hs_ep->size_loaded - size_left;
550 /* how much data is left in the fifo */
551 can_write = hs_ep->fifo_load - size_done;
552 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
553 __func__, can_write);
555 can_write = hs_ep->fifo_size - can_write;
556 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
557 __func__, can_write);
559 if (can_write <= 0) {
560 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
563 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
564 can_write = dwc2_readl(hsotg,
565 DTXFSTS(hs_ep->fifo_index));
570 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
572 "%s: no queue slots available (0x%08x)\n",
575 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
579 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
580 can_write *= 4; /* fifo size is in 32bit quantities. */
583 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
585 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
586 __func__, gnptxsts, can_write, to_write, max_transfer);
589 * limit to 512 bytes of data, it seems at least on the non-periodic
590 * FIFO, requests of >512 cause the endpoint to get stuck with a
591 * fragment of the end of the transfer in it.
593 if (can_write > 512 && !periodic)
597 * limit the write to one max-packet size worth of data, but allow
598 * the transfer to return that it did not run out of fifo space
601 if (to_write > max_transfer) {
602 to_write = max_transfer;
604 /* it's needed only when we do not use dedicated fifos */
605 if (!hsotg->dedicated_fifos)
606 dwc2_hsotg_en_gsint(hsotg,
607 periodic ? GINTSTS_PTXFEMP :
611 /* see if we can write data */
613 if (to_write > can_write) {
614 to_write = can_write;
615 pkt_round = to_write % max_transfer;
618 * Round the write down to an
619 * exact number of packets.
621 * Note, we do not currently check to see if we can ever
622 * write a full packet or not to the FIFO.
626 to_write -= pkt_round;
629 * enable correct FIFO interrupt to alert us when there
633 /* it's needed only when we do not use dedicated fifos */
634 if (!hsotg->dedicated_fifos)
635 dwc2_hsotg_en_gsint(hsotg,
636 periodic ? GINTSTS_PTXFEMP :
640 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
641 to_write, hs_req->req.length, can_write, buf_pos);
646 hs_req->req.actual = buf_pos + to_write;
647 hs_ep->total_data += to_write;
650 hs_ep->fifo_load += to_write;
652 to_write = DIV_ROUND_UP(to_write, 4);
653 data = hs_req->req.buf + buf_pos;
655 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
657 return (to_write >= can_write) ? -ENOSPC : 0;
661 * get_ep_limit - get the maximum data legnth for this endpoint
662 * @hs_ep: The endpoint
664 * Return the maximum data that can be queued in one go on a given endpoint
665 * so that transfers that are too long can be split.
667 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
669 int index = hs_ep->index;
670 unsigned int maxsize;
674 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
675 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
679 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
684 /* we made the constant loading easier above by using +1 */
689 * constrain by packet count if maxpkts*pktsize is greater
690 * than the length register size.
693 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
694 maxsize = maxpkt * hs_ep->ep.maxpacket;
700 * dwc2_hsotg_read_frameno - read current frame number
701 * @hsotg: The device instance
703 * Return the current frame number
705 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
709 dsts = dwc2_readl(hsotg, DSTS);
710 dsts &= DSTS_SOFFN_MASK;
711 dsts >>= DSTS_SOFFN_SHIFT;
717 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
718 * DMA descriptor chain prepared for specific endpoint
719 * @hs_ep: The endpoint
721 * Return the maximum data that can be queued in one go on a given endpoint
722 * depending on its descriptor chain capacity so that transfers that
723 * are too long can be split.
725 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
727 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
728 int is_isoc = hs_ep->isochronous;
729 unsigned int maxsize;
730 u32 mps = hs_ep->ep.maxpacket;
731 int dir_in = hs_ep->dir_in;
734 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
735 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
736 MAX_DMA_DESC_NUM_HS_ISOC;
738 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
740 /* Interrupt OUT EP with mps not multiple of 4 */
742 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
743 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
749 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
750 * @hs_ep: The endpoint
751 * @mask: RX/TX bytes mask to be defined
753 * Returns maximum data payload for one descriptor after analyzing endpoint
755 * DMA descriptor transfer bytes limit depends on EP type:
757 * Isochronous - descriptor rx/tx bytes bitfield limit,
758 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
759 * have concatenations from various descriptors within one packet.
760 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
761 * to a single descriptor.
763 * Selects corresponding mask for RX/TX bytes as well.
765 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
767 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
768 u32 mps = hs_ep->ep.maxpacket;
769 int dir_in = hs_ep->dir_in;
772 if (!hs_ep->index && !dir_in) {
774 *mask = DEV_DMA_NBYTES_MASK;
775 } else if (hs_ep->isochronous) {
777 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
778 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
780 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
781 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
784 desc_size = DEV_DMA_NBYTES_LIMIT;
785 *mask = DEV_DMA_NBYTES_MASK;
787 /* Round down desc_size to be mps multiple */
788 desc_size -= desc_size % mps;
791 /* Interrupt OUT EP with mps not multiple of 4 */
793 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
795 *mask = DEV_DMA_NBYTES_MASK;
801 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
802 struct dwc2_dma_desc **desc,
807 int dir_in = hs_ep->dir_in;
808 u32 mps = hs_ep->ep.maxpacket;
814 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
816 hs_ep->desc_count = (len / maxsize) +
817 ((len % maxsize) ? 1 : 0);
819 hs_ep->desc_count = 1;
821 for (i = 0; i < hs_ep->desc_count; ++i) {
823 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
824 << DEV_DMA_BUFF_STS_SHIFT);
827 if (!hs_ep->index && !dir_in)
828 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
831 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
832 (*desc)->buf = dma_buff + offset;
838 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
841 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
842 ((hs_ep->send_zlp && true_last) ?
846 len << DEV_DMA_NBYTES_SHIFT & mask;
847 (*desc)->buf = dma_buff + offset;
850 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
851 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
852 << DEV_DMA_BUFF_STS_SHIFT);
858 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
859 * @hs_ep: The endpoint
860 * @ureq: Request to transfer
861 * @offset: offset in bytes
862 * @len: Length of the transfer
864 * This function will iterate over descriptor chain and fill its entries
865 * with corresponding information based on transfer data.
867 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
871 struct usb_request *ureq = NULL;
872 struct dwc2_dma_desc *desc = hs_ep->desc_list;
873 struct scatterlist *sg;
878 ureq = &hs_ep->req->req;
880 /* non-DMA sg buffer */
881 if (!ureq || !ureq->num_sgs) {
882 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
883 dma_buff, len, true);
888 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
889 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
890 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
892 desc_count += hs_ep->desc_count;
895 hs_ep->desc_count = desc_count;
899 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
900 * @hs_ep: The isochronous endpoint.
901 * @dma_buff: usb requests dma buffer.
902 * @len: usb request transfer length.
904 * Fills next free descriptor with the data of the arrived usb request,
905 * frame info, sets Last and IOC bits increments next_desc. If filled
906 * descriptor is not the first one, removes L bit from the previous descriptor
909 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
910 dma_addr_t dma_buff, unsigned int len)
912 struct dwc2_dma_desc *desc;
913 struct dwc2_hsotg *hsotg = hs_ep->parent;
918 dwc2_gadget_get_desc_params(hs_ep, &mask);
920 index = hs_ep->next_desc;
921 desc = &hs_ep->desc_list[index];
923 /* Check if descriptor chain full */
924 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
925 DEV_DMA_BUFF_STS_HREADY) {
926 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
930 /* Clear L bit of previous desc if more than one entries in the chain */
931 if (hs_ep->next_desc)
932 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
934 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
935 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
938 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
940 desc->buf = dma_buff;
941 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
942 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
946 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
949 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
950 DEV_DMA_ISOC_PID_MASK) |
951 ((len % hs_ep->ep.maxpacket) ?
953 ((hs_ep->target_frame <<
954 DEV_DMA_ISOC_FRNUM_SHIFT) &
955 DEV_DMA_ISOC_FRNUM_MASK);
958 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
959 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
961 /* Increment frame number by interval for IN */
963 dwc2_gadget_incr_frame_num(hs_ep);
965 /* Update index of last configured entry in the chain */
967 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
968 hs_ep->next_desc = 0;
974 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
975 * @hs_ep: The isochronous endpoint.
977 * Prepare descriptor chain for isochronous endpoints. Afterwards
978 * write DMA address to HW and enable the endpoint.
980 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
982 struct dwc2_hsotg *hsotg = hs_ep->parent;
983 struct dwc2_hsotg_req *hs_req, *treq;
984 int index = hs_ep->index;
990 struct dwc2_dma_desc *desc;
992 if (list_empty(&hs_ep->queue)) {
993 hs_ep->target_frame = TARGET_FRAME_INITIAL;
994 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
998 /* Initialize descriptor chain by Host Busy status */
999 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1000 desc = &hs_ep->desc_list[i];
1002 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1003 << DEV_DMA_BUFF_STS_SHIFT);
1006 hs_ep->next_desc = 0;
1007 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1008 dma_addr_t dma_addr = hs_req->req.dma;
1010 if (hs_req->req.num_sgs) {
1011 WARN_ON(hs_req->req.num_sgs > 1);
1012 dma_addr = sg_dma_address(hs_req->req.sg);
1014 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1015 hs_req->req.length);
1020 hs_ep->compl_desc = 0;
1021 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1022 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1024 /* write descriptor chain address to control register */
1025 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1027 ctrl = dwc2_readl(hsotg, depctl);
1028 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1029 dwc2_writel(hsotg, ctrl, depctl);
1032 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1033 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1034 struct dwc2_hsotg_ep *hs_ep,
1035 struct dwc2_hsotg_req *hs_req,
1039 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1040 * @hsotg: The controller state.
1041 * @hs_ep: The endpoint to process a request for
1042 * @hs_req: The request to start.
1043 * @continuing: True if we are doing more for the current request.
1045 * Start the given request running by setting the endpoint registers
1046 * appropriately, and writing any data to the FIFOs.
1048 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1049 struct dwc2_hsotg_ep *hs_ep,
1050 struct dwc2_hsotg_req *hs_req,
1053 struct usb_request *ureq = &hs_req->req;
1054 int index = hs_ep->index;
1055 int dir_in = hs_ep->dir_in;
1060 unsigned int length;
1061 unsigned int packets;
1062 unsigned int maxreq;
1063 unsigned int dma_reg;
1066 if (hs_ep->req && !continuing) {
1067 dev_err(hsotg->dev, "%s: active request\n", __func__);
1070 } else if (hs_ep->req != hs_req && continuing) {
1072 "%s: continue different req\n", __func__);
1078 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1079 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1080 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1082 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1083 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1084 hs_ep->dir_in ? "in" : "out");
1086 /* If endpoint is stalled, we will restart request later */
1087 ctrl = dwc2_readl(hsotg, epctrl_reg);
1089 if (index && ctrl & DXEPCTL_STALL) {
1090 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1094 length = ureq->length - ureq->actual;
1095 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1096 ureq->length, ureq->actual);
1098 if (!using_desc_dma(hsotg))
1099 maxreq = get_ep_limit(hs_ep);
1101 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1103 if (length > maxreq) {
1104 int round = maxreq % hs_ep->ep.maxpacket;
1106 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1107 __func__, length, maxreq, round);
1109 /* round down to multiple of packets */
1117 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1119 packets = 1; /* send one packet if length is zero. */
1121 if (dir_in && index != 0)
1122 if (hs_ep->isochronous)
1123 epsize = DXEPTSIZ_MC(packets);
1125 epsize = DXEPTSIZ_MC(1);
1130 * zero length packet should be programmed on its own and should not
1131 * be counted in DIEPTSIZ.PktCnt with other packets.
1133 if (dir_in && ureq->zero && !continuing) {
1134 /* Test if zlp is actually required. */
1135 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1136 !(ureq->length % hs_ep->ep.maxpacket))
1137 hs_ep->send_zlp = 1;
1140 epsize |= DXEPTSIZ_PKTCNT(packets);
1141 epsize |= DXEPTSIZ_XFERSIZE(length);
1143 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1144 __func__, packets, length, ureq->length, epsize, epsize_reg);
1146 /* store the request as the current one we're doing */
1147 hs_ep->req = hs_req;
1149 if (using_desc_dma(hsotg)) {
1151 u32 mps = hs_ep->ep.maxpacket;
1153 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1157 else if (length % mps)
1158 length += (mps - (length % mps));
1162 offset = ureq->actual;
1164 /* Fill DDMA chain entries */
1165 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1168 /* write descriptor chain address to control register */
1169 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1171 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1172 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1174 /* write size / packets */
1175 dwc2_writel(hsotg, epsize, epsize_reg);
1177 if (using_dma(hsotg) && !continuing && (length != 0)) {
1179 * write DMA address to control register, buffer
1180 * already synced by dwc2_hsotg_ep_queue().
1183 dwc2_writel(hsotg, ureq->dma, dma_reg);
1185 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1186 __func__, &ureq->dma, dma_reg);
1190 if (hs_ep->isochronous) {
1191 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1192 if (hs_ep->interval == 1) {
1193 if (hs_ep->target_frame & 0x1)
1194 ctrl |= DXEPCTL_SETODDFR;
1196 ctrl |= DXEPCTL_SETEVENFR;
1198 ctrl |= DXEPCTL_CNAK;
1200 hs_req->req.frame_number = hs_ep->target_frame;
1201 hs_req->req.actual = 0;
1202 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1207 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1209 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1211 /* For Setup request do not clear NAK */
1212 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1213 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1215 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1216 dwc2_writel(hsotg, ctrl, epctrl_reg);
1219 * set these, it seems that DMA support increments past the end
1220 * of the packet buffer so we need to calculate the length from
1223 hs_ep->size_loaded = length;
1224 hs_ep->last_load = ureq->actual;
1226 if (dir_in && !using_dma(hsotg)) {
1227 /* set these anyway, we may need them for non-periodic in */
1228 hs_ep->fifo_load = 0;
1230 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1234 * Note, trying to clear the NAK here causes problems with transmit
1235 * on the S3C6400 ending up with the TXFIFO becoming full.
1238 /* check ep is enabled */
1239 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1241 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1242 index, dwc2_readl(hsotg, epctrl_reg));
1244 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1245 __func__, dwc2_readl(hsotg, epctrl_reg));
1247 /* enable ep interrupts */
1248 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1252 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1253 * @hsotg: The device state.
1254 * @hs_ep: The endpoint the request is on.
1255 * @req: The request being processed.
1257 * We've been asked to queue a request, so ensure that the memory buffer
1258 * is correctly setup for DMA. If we've been passed an extant DMA address
1259 * then ensure the buffer has been synced to memory. If our buffer has no
1260 * DMA memory, then we map the memory and mark our request to allow us to
1261 * cleanup on completion.
1263 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1264 struct dwc2_hsotg_ep *hs_ep,
1265 struct usb_request *req)
1269 hs_ep->map_dir = hs_ep->dir_in;
1270 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1277 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1278 __func__, req->buf, req->length);
1283 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1284 struct dwc2_hsotg_ep *hs_ep,
1285 struct dwc2_hsotg_req *hs_req)
1287 void *req_buf = hs_req->req.buf;
1289 /* If dma is not being used or buffer is aligned */
1290 if (!using_dma(hsotg) || !((long)req_buf & 3))
1293 WARN_ON(hs_req->saved_req_buf);
1295 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1296 hs_ep->ep.name, req_buf, hs_req->req.length);
1298 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1299 if (!hs_req->req.buf) {
1300 hs_req->req.buf = req_buf;
1302 "%s: unable to allocate memory for bounce buffer\n",
1307 /* Save actual buffer */
1308 hs_req->saved_req_buf = req_buf;
1311 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1316 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1317 struct dwc2_hsotg_ep *hs_ep,
1318 struct dwc2_hsotg_req *hs_req)
1320 /* If dma is not being used or buffer was aligned */
1321 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1324 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1325 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1327 /* Copy data from bounce buffer on successful out transfer */
1328 if (!hs_ep->dir_in && !hs_req->req.status)
1329 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1330 hs_req->req.actual);
1332 /* Free bounce buffer */
1333 kfree(hs_req->req.buf);
1335 hs_req->req.buf = hs_req->saved_req_buf;
1336 hs_req->saved_req_buf = NULL;
1340 * dwc2_gadget_target_frame_elapsed - Checks target frame
1341 * @hs_ep: The driver endpoint to check
1343 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1344 * corresponding transfer.
1346 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1348 struct dwc2_hsotg *hsotg = hs_ep->parent;
1349 u32 target_frame = hs_ep->target_frame;
1350 u32 current_frame = hsotg->frame_number;
1351 bool frame_overrun = hs_ep->frame_overrun;
1352 u16 limit = DSTS_SOFFN_LIMIT;
1354 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1357 if (!frame_overrun && current_frame >= target_frame)
1360 if (frame_overrun && current_frame >= target_frame &&
1361 ((current_frame - target_frame) < limit / 2))
1368 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1369 * @hsotg: The driver state
1370 * @hs_ep: the ep descriptor chain is for
1372 * Called to update EP0 structure's pointers depend on stage of
1375 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1376 struct dwc2_hsotg_ep *hs_ep)
1378 switch (hsotg->ep0_state) {
1379 case DWC2_EP0_SETUP:
1380 case DWC2_EP0_STATUS_OUT:
1381 hs_ep->desc_list = hsotg->setup_desc[0];
1382 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1384 case DWC2_EP0_DATA_IN:
1385 case DWC2_EP0_STATUS_IN:
1386 hs_ep->desc_list = hsotg->ctrl_in_desc;
1387 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1389 case DWC2_EP0_DATA_OUT:
1390 hs_ep->desc_list = hsotg->ctrl_out_desc;
1391 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1394 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1402 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1405 struct dwc2_hsotg_req *hs_req = our_req(req);
1406 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1407 struct dwc2_hsotg *hs = hs_ep->parent;
1414 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1415 ep->name, req, req->length, req->buf, req->no_interrupt,
1416 req->zero, req->short_not_ok);
1418 /* Prevent new request submission when controller is suspended */
1419 if (hs->lx_state != DWC2_L0) {
1420 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1425 /* initialise status of the request */
1426 INIT_LIST_HEAD(&hs_req->queue);
1428 req->status = -EINPROGRESS;
1430 /* Don't queue ISOC request if length greater than mps*mc */
1431 if (hs_ep->isochronous &&
1432 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1433 dev_err(hs->dev, "req length > maxpacket*mc\n");
1437 /* In DDMA mode for ISOC's don't queue request if length greater
1438 * than descriptor limits.
1440 if (using_desc_dma(hs) && hs_ep->isochronous) {
1441 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1442 if (hs_ep->dir_in && req->length > maxsize) {
1443 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1444 req->length, maxsize);
1448 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1449 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1450 req->length, hs_ep->ep.maxpacket);
1455 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1459 /* if we're using DMA, sync the buffers as necessary */
1460 if (using_dma(hs)) {
1461 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1465 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1466 if (using_desc_dma(hs) && !hs_ep->index) {
1467 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1472 first = list_empty(&hs_ep->queue);
1473 list_add_tail(&hs_req->queue, &hs_ep->queue);
1476 * Handle DDMA isochronous transfers separately - just add new entry
1477 * to the descriptor chain.
1478 * Transfer will be started once SW gets either one of NAK or
1479 * OutTknEpDis interrupts.
1481 if (using_desc_dma(hs) && hs_ep->isochronous) {
1482 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1483 dma_addr_t dma_addr = hs_req->req.dma;
1485 if (hs_req->req.num_sgs) {
1486 WARN_ON(hs_req->req.num_sgs > 1);
1487 dma_addr = sg_dma_address(hs_req->req.sg);
1489 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1490 hs_req->req.length);
1495 /* Change EP direction if status phase request is after data out */
1496 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1497 hs->ep0_state == DWC2_EP0_DATA_OUT)
1501 if (!hs_ep->isochronous) {
1502 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1506 /* Update current frame number value. */
1507 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1508 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1509 dwc2_gadget_incr_frame_num(hs_ep);
1510 /* Update current frame number value once more as it
1513 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1516 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1517 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1522 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1525 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1526 struct dwc2_hsotg *hs = hs_ep->parent;
1527 unsigned long flags;
1530 spin_lock_irqsave(&hs->lock, flags);
1531 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1532 spin_unlock_irqrestore(&hs->lock, flags);
1537 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1538 struct usb_request *req)
1540 struct dwc2_hsotg_req *hs_req = our_req(req);
1546 * dwc2_hsotg_complete_oursetup - setup completion callback
1547 * @ep: The endpoint the request was on.
1548 * @req: The request completed.
1550 * Called on completion of any requests the driver itself
1551 * submitted that need cleaning up.
1553 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1554 struct usb_request *req)
1556 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1557 struct dwc2_hsotg *hsotg = hs_ep->parent;
1559 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1561 dwc2_hsotg_ep_free_request(ep, req);
1565 * ep_from_windex - convert control wIndex value to endpoint
1566 * @hsotg: The driver state.
1567 * @windex: The control request wIndex field (in host order).
1569 * Convert the given wIndex into a pointer to an driver endpoint
1570 * structure, or return NULL if it is not a valid endpoint.
1572 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1575 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1576 int idx = windex & 0x7F;
1578 if (windex >= 0x100)
1581 if (idx > hsotg->num_of_eps)
1584 return index_to_ep(hsotg, idx, dir);
1588 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1589 * @hsotg: The driver state.
1590 * @testmode: requested usb test mode
1591 * Enable usb Test Mode requested by the Host.
1593 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1595 int dctl = dwc2_readl(hsotg, DCTL);
1597 dctl &= ~DCTL_TSTCTL_MASK;
1601 case USB_TEST_SE0_NAK:
1602 case USB_TEST_PACKET:
1603 case USB_TEST_FORCE_ENABLE:
1604 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1609 dwc2_writel(hsotg, dctl, DCTL);
1614 * dwc2_hsotg_send_reply - send reply to control request
1615 * @hsotg: The device state
1617 * @buff: Buffer for request
1618 * @length: Length of reply.
1620 * Create a request and queue it on the given endpoint. This is useful as
1621 * an internal method of sending replies to certain control requests, etc.
1623 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1624 struct dwc2_hsotg_ep *ep,
1628 struct usb_request *req;
1631 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1633 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1634 hsotg->ep0_reply = req;
1636 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1640 req->buf = hsotg->ep0_buff;
1641 req->length = length;
1643 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1647 req->complete = dwc2_hsotg_complete_oursetup;
1650 memcpy(req->buf, buff, length);
1652 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1654 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1662 * dwc2_hsotg_process_req_status - process request GET_STATUS
1663 * @hsotg: The device state
1664 * @ctrl: USB control request
1666 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1667 struct usb_ctrlrequest *ctrl)
1669 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1670 struct dwc2_hsotg_ep *ep;
1675 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1678 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1682 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1683 case USB_RECIP_DEVICE:
1684 status = hsotg->gadget.is_selfpowered <<
1685 USB_DEVICE_SELF_POWERED;
1686 status |= hsotg->remote_wakeup_allowed <<
1687 USB_DEVICE_REMOTE_WAKEUP;
1688 reply = cpu_to_le16(status);
1691 case USB_RECIP_INTERFACE:
1692 /* currently, the data result should be zero */
1693 reply = cpu_to_le16(0);
1696 case USB_RECIP_ENDPOINT:
1697 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1701 reply = cpu_to_le16(ep->halted ? 1 : 0);
1708 if (le16_to_cpu(ctrl->wLength) != 2)
1711 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1713 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1720 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1723 * get_ep_head - return the first request on the endpoint
1724 * @hs_ep: The controller endpoint to get
1726 * Get the first request on the endpoint.
1728 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1730 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1735 * dwc2_gadget_start_next_request - Starts next request from ep queue
1736 * @hs_ep: Endpoint structure
1738 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1739 * in its handler. Hence we need to unmask it here to be able to do
1740 * resynchronization.
1742 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1744 struct dwc2_hsotg *hsotg = hs_ep->parent;
1745 int dir_in = hs_ep->dir_in;
1746 struct dwc2_hsotg_req *hs_req;
1748 if (!list_empty(&hs_ep->queue)) {
1749 hs_req = get_ep_head(hs_ep);
1750 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1753 if (!hs_ep->isochronous)
1757 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1760 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1766 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1767 * @hsotg: The device state
1768 * @ctrl: USB control request
1770 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1771 struct usb_ctrlrequest *ctrl)
1773 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1774 struct dwc2_hsotg_req *hs_req;
1775 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1776 struct dwc2_hsotg_ep *ep;
1783 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1784 __func__, set ? "SET" : "CLEAR");
1786 wValue = le16_to_cpu(ctrl->wValue);
1787 wIndex = le16_to_cpu(ctrl->wIndex);
1788 recip = ctrl->bRequestType & USB_RECIP_MASK;
1791 case USB_RECIP_DEVICE:
1793 case USB_DEVICE_REMOTE_WAKEUP:
1795 hsotg->remote_wakeup_allowed = 1;
1797 hsotg->remote_wakeup_allowed = 0;
1800 case USB_DEVICE_TEST_MODE:
1801 if ((wIndex & 0xff) != 0)
1806 hsotg->test_mode = wIndex >> 8;
1812 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1815 "%s: failed to send reply\n", __func__);
1820 case USB_RECIP_ENDPOINT:
1821 ep = ep_from_windex(hsotg, wIndex);
1823 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1829 case USB_ENDPOINT_HALT:
1830 halted = ep->halted;
1833 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1835 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1838 "%s: failed to send reply\n", __func__);
1843 * we have to complete all requests for ep if it was
1844 * halted, and the halt was cleared by CLEAR_FEATURE
1847 if (!set && halted) {
1849 * If we have request in progress,
1855 list_del_init(&hs_req->queue);
1856 if (hs_req->req.complete) {
1857 spin_unlock(&hsotg->lock);
1858 usb_gadget_giveback_request(
1859 &ep->ep, &hs_req->req);
1860 spin_lock(&hsotg->lock);
1864 /* If we have pending request, then start it */
1866 dwc2_gadget_start_next_request(ep);
1881 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1884 * dwc2_hsotg_stall_ep0 - stall ep0
1885 * @hsotg: The device state
1887 * Set stall for ep0 as response for setup request.
1889 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1891 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1895 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1896 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1899 * DxEPCTL_Stall will be cleared by EP once it has
1900 * taken effect, so no need to clear later.
1903 ctrl = dwc2_readl(hsotg, reg);
1904 ctrl |= DXEPCTL_STALL;
1905 ctrl |= DXEPCTL_CNAK;
1906 dwc2_writel(hsotg, ctrl, reg);
1909 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1910 ctrl, reg, dwc2_readl(hsotg, reg));
1913 * complete won't be called, so we enqueue
1914 * setup request here
1916 dwc2_hsotg_enqueue_setup(hsotg);
1920 * dwc2_hsotg_process_control - process a control request
1921 * @hsotg: The device state
1922 * @ctrl: The control request received
1924 * The controller has received the SETUP phase of a control request, and
1925 * needs to work out what to do next (and whether to pass it on to the
1928 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1929 struct usb_ctrlrequest *ctrl)
1931 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1936 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1937 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1938 ctrl->wIndex, ctrl->wLength);
1940 if (ctrl->wLength == 0) {
1942 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1943 } else if (ctrl->bRequestType & USB_DIR_IN) {
1945 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1948 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1951 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1952 switch (ctrl->bRequest) {
1953 case USB_REQ_SET_ADDRESS:
1954 hsotg->connected = 1;
1955 dcfg = dwc2_readl(hsotg, DCFG);
1956 dcfg &= ~DCFG_DEVADDR_MASK;
1957 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1958 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1959 dwc2_writel(hsotg, dcfg, DCFG);
1961 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1963 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1966 case USB_REQ_GET_STATUS:
1967 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1970 case USB_REQ_CLEAR_FEATURE:
1971 case USB_REQ_SET_FEATURE:
1972 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1977 /* as a fallback, try delivering it to the driver to deal with */
1979 if (ret == 0 && hsotg->driver) {
1980 spin_unlock(&hsotg->lock);
1981 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1982 spin_lock(&hsotg->lock);
1984 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1987 hsotg->delayed_status = false;
1988 if (ret == USB_GADGET_DELAYED_STATUS)
1989 hsotg->delayed_status = true;
1992 * the request is either unhandlable, or is not formatted correctly
1993 * so respond with a STALL for the status stage to indicate failure.
1997 dwc2_hsotg_stall_ep0(hsotg);
2001 * dwc2_hsotg_complete_setup - completion of a setup transfer
2002 * @ep: The endpoint the request was on.
2003 * @req: The request completed.
2005 * Called on completion of any requests the driver itself submitted for
2008 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2009 struct usb_request *req)
2011 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2012 struct dwc2_hsotg *hsotg = hs_ep->parent;
2014 if (req->status < 0) {
2015 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2019 spin_lock(&hsotg->lock);
2020 if (req->actual == 0)
2021 dwc2_hsotg_enqueue_setup(hsotg);
2023 dwc2_hsotg_process_control(hsotg, req->buf);
2024 spin_unlock(&hsotg->lock);
2028 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2029 * @hsotg: The device state.
2031 * Enqueue a request on EP0 if necessary to received any SETUP packets
2032 * received from the host.
2034 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2036 struct usb_request *req = hsotg->ctrl_req;
2037 struct dwc2_hsotg_req *hs_req = our_req(req);
2040 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2044 req->buf = hsotg->ctrl_buff;
2045 req->complete = dwc2_hsotg_complete_setup;
2047 if (!list_empty(&hs_req->queue)) {
2048 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2052 hsotg->eps_out[0]->dir_in = 0;
2053 hsotg->eps_out[0]->send_zlp = 0;
2054 hsotg->ep0_state = DWC2_EP0_SETUP;
2056 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2058 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2060 * Don't think there's much we can do other than watch the
2066 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2067 struct dwc2_hsotg_ep *hs_ep)
2070 u8 index = hs_ep->index;
2071 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2072 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2075 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2078 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2080 if (using_desc_dma(hsotg)) {
2081 /* Not specific buffer needed for ep0 ZLP */
2082 dma_addr_t dma = hs_ep->desc_list_dma;
2085 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2087 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2089 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2090 DXEPTSIZ_XFERSIZE(0),
2094 ctrl = dwc2_readl(hsotg, epctl_reg);
2095 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2096 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2097 ctrl |= DXEPCTL_USBACTEP;
2098 dwc2_writel(hsotg, ctrl, epctl_reg);
2102 * dwc2_hsotg_complete_request - complete a request given to us
2103 * @hsotg: The device state.
2104 * @hs_ep: The endpoint the request was on.
2105 * @hs_req: The request to complete.
2106 * @result: The result code (0 => Ok, otherwise errno)
2108 * The given request has finished, so call the necessary completion
2109 * if it has one and then look to see if we can start a new request
2112 * Note, expects the ep to already be locked as appropriate.
2114 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2115 struct dwc2_hsotg_ep *hs_ep,
2116 struct dwc2_hsotg_req *hs_req,
2120 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2124 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2125 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2128 * only replace the status if we've not already set an error
2129 * from a previous transaction
2132 if (hs_req->req.status == -EINPROGRESS)
2133 hs_req->req.status = result;
2135 if (using_dma(hsotg))
2136 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2138 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2141 list_del_init(&hs_req->queue);
2144 * call the complete request with the locks off, just in case the
2145 * request tries to queue more work for this endpoint.
2148 if (hs_req->req.complete) {
2149 spin_unlock(&hsotg->lock);
2150 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2151 spin_lock(&hsotg->lock);
2154 /* In DDMA don't need to proceed to starting of next ISOC request */
2155 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2159 * Look to see if there is anything else to do. Note, the completion
2160 * of the previous request may have caused a new request to be started
2161 * so be careful when doing this.
2164 if (!hs_ep->req && result >= 0)
2165 dwc2_gadget_start_next_request(hs_ep);
2169 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2170 * @hs_ep: The endpoint the request was on.
2172 * Get first request from the ep queue, determine descriptor on which complete
2173 * happened. SW discovers which descriptor currently in use by HW, adjusts
2174 * dma_address and calculates index of completed descriptor based on the value
2175 * of DEPDMA register. Update actual length of request, giveback to gadget.
2177 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2179 struct dwc2_hsotg *hsotg = hs_ep->parent;
2180 struct dwc2_hsotg_req *hs_req;
2181 struct usb_request *ureq;
2185 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2187 /* Process only descriptors with buffer status set to DMA done */
2188 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2189 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2191 hs_req = get_ep_head(hs_ep);
2193 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2196 ureq = &hs_req->req;
2198 /* Check completion status */
2199 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2201 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2202 DEV_DMA_ISOC_RX_NBYTES_MASK;
2203 ureq->actual = ureq->length - ((desc_sts & mask) >>
2204 DEV_DMA_ISOC_NBYTES_SHIFT);
2206 /* Adjust actual len for ISOC Out if len is
2209 if (!hs_ep->dir_in && ureq->length & 0x3)
2210 ureq->actual += 4 - (ureq->length & 0x3);
2212 /* Set actual frame number for completed transfers */
2213 ureq->frame_number =
2214 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2215 DEV_DMA_ISOC_FRNUM_SHIFT;
2218 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2220 hs_ep->compl_desc++;
2221 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2222 hs_ep->compl_desc = 0;
2223 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2228 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2229 * @hs_ep: The isochronous endpoint.
2231 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2232 * interrupt. Reset target frame and next_desc to allow to start
2233 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2234 * interrupt for OUT direction.
2236 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2238 struct dwc2_hsotg *hsotg = hs_ep->parent;
2241 dwc2_flush_rx_fifo(hsotg);
2242 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2244 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2245 hs_ep->next_desc = 0;
2246 hs_ep->compl_desc = 0;
2250 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2251 * @hsotg: The device state.
2252 * @ep_idx: The endpoint index for the data
2253 * @size: The size of data in the fifo, in bytes
2255 * The FIFO status shows there is data to read from the FIFO for a given
2256 * endpoint, so sort out whether we need to read the data into a request
2257 * that has been made for that endpoint.
2259 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2261 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2262 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2268 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2272 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2273 __func__, size, ep_idx, epctl);
2275 /* dump the data from the FIFO, we've nothing we can do */
2276 for (ptr = 0; ptr < size; ptr += 4)
2277 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2283 read_ptr = hs_req->req.actual;
2284 max_req = hs_req->req.length - read_ptr;
2286 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2287 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2289 if (to_read > max_req) {
2291 * more data appeared than we where willing
2292 * to deal with in this request.
2295 /* currently we don't deal this */
2299 hs_ep->total_data += to_read;
2300 hs_req->req.actual += to_read;
2301 to_read = DIV_ROUND_UP(to_read, 4);
2304 * note, we might over-write the buffer end by 3 bytes depending on
2305 * alignment of the data.
2307 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2308 hs_req->req.buf + read_ptr, to_read);
2312 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2313 * @hsotg: The device instance
2314 * @dir_in: If IN zlp
2316 * Generate a zero-length IN packet request for terminating a SETUP
2319 * Note, since we don't write any data to the TxFIFO, then it is
2320 * currently believed that we do not need to wait for any space in
2323 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2325 /* eps_out[0] is used in both directions */
2326 hsotg->eps_out[0]->dir_in = dir_in;
2327 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2329 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2333 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2334 * @hs_ep - The endpoint on which transfer went
2336 * Iterate over endpoints descriptor chain and get info on bytes remained
2337 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2339 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2341 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2342 struct dwc2_hsotg *hsotg = hs_ep->parent;
2343 unsigned int bytes_rem = 0;
2344 unsigned int bytes_rem_correction = 0;
2345 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2348 u32 mps = hs_ep->ep.maxpacket;
2349 int dir_in = hs_ep->dir_in;
2354 /* Interrupt OUT EP with mps not multiple of 4 */
2356 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2357 bytes_rem_correction = 4 - (mps % 4);
2359 for (i = 0; i < hs_ep->desc_count; ++i) {
2360 status = desc->status;
2361 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2362 bytes_rem -= bytes_rem_correction;
2364 if (status & DEV_DMA_STS_MASK)
2365 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2366 i, status & DEV_DMA_STS_MASK);
2368 if (status & DEV_DMA_L)
2378 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2379 * @hsotg: The device instance
2380 * @epnum: The endpoint received from
2382 * The RXFIFO has delivered an OutDone event, which means that the data
2383 * transfer for an OUT endpoint has been completed, either by a short
2384 * packet or by the finish of a transfer.
2386 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2388 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2389 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2390 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2391 struct usb_request *req = &hs_req->req;
2392 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2396 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2400 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2401 dev_dbg(hsotg->dev, "zlp packet received\n");
2402 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2403 dwc2_hsotg_enqueue_setup(hsotg);
2407 if (using_desc_dma(hsotg))
2408 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2410 if (using_dma(hsotg)) {
2411 unsigned int size_done;
2414 * Calculate the size of the transfer by checking how much
2415 * is left in the endpoint size register and then working it
2416 * out from the amount we loaded for the transfer.
2418 * We need to do this as DMA pointers are always 32bit aligned
2419 * so may overshoot/undershoot the transfer.
2422 size_done = hs_ep->size_loaded - size_left;
2423 size_done += hs_ep->last_load;
2425 req->actual = size_done;
2428 /* if there is more request to do, schedule new transfer */
2429 if (req->actual < req->length && size_left == 0) {
2430 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2434 if (req->actual < req->length && req->short_not_ok) {
2435 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2436 __func__, req->actual, req->length);
2439 * todo - what should we return here? there's no one else
2440 * even bothering to check the status.
2444 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2445 if (!using_desc_dma(hsotg) && epnum == 0 &&
2446 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2447 /* Move to STATUS IN */
2448 if (!hsotg->delayed_status)
2449 dwc2_hsotg_ep0_zlp(hsotg, true);
2452 /* Set actual frame number for completed transfers */
2453 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2454 req->frame_number = hs_ep->target_frame;
2455 dwc2_gadget_incr_frame_num(hs_ep);
2458 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2462 * dwc2_hsotg_handle_rx - RX FIFO has data
2463 * @hsotg: The device instance
2465 * The IRQ handler has detected that the RX FIFO has some data in it
2466 * that requires processing, so find out what is in there and do the
2469 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2470 * chunks, so if you have x packets received on an endpoint you'll get x
2471 * FIFO events delivered, each with a packet's worth of data in it.
2473 * When using DMA, we should not be processing events from the RXFIFO
2474 * as the actual data should be sent to the memory directly and we turn
2475 * on the completion interrupts to get notifications of transfer completion.
2477 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2479 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2480 u32 epnum, status, size;
2482 WARN_ON(using_dma(hsotg));
2484 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2485 status = grxstsr & GRXSTS_PKTSTS_MASK;
2487 size = grxstsr & GRXSTS_BYTECNT_MASK;
2488 size >>= GRXSTS_BYTECNT_SHIFT;
2490 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2491 __func__, grxstsr, size, epnum);
2493 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2494 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2495 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2498 case GRXSTS_PKTSTS_OUTDONE:
2499 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2500 dwc2_hsotg_read_frameno(hsotg));
2502 if (!using_dma(hsotg))
2503 dwc2_hsotg_handle_outdone(hsotg, epnum);
2506 case GRXSTS_PKTSTS_SETUPDONE:
2508 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2509 dwc2_hsotg_read_frameno(hsotg),
2510 dwc2_readl(hsotg, DOEPCTL(0)));
2512 * Call dwc2_hsotg_handle_outdone here if it was not called from
2513 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2514 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2516 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2517 dwc2_hsotg_handle_outdone(hsotg, epnum);
2520 case GRXSTS_PKTSTS_OUTRX:
2521 dwc2_hsotg_rx_data(hsotg, epnum, size);
2524 case GRXSTS_PKTSTS_SETUPRX:
2526 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2527 dwc2_hsotg_read_frameno(hsotg),
2528 dwc2_readl(hsotg, DOEPCTL(0)));
2530 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2532 dwc2_hsotg_rx_data(hsotg, epnum, size);
2536 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2539 dwc2_hsotg_dump(hsotg);
2545 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2546 * @mps: The maximum packet size in bytes.
2548 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2552 return D0EPCTL_MPS_64;
2554 return D0EPCTL_MPS_32;
2556 return D0EPCTL_MPS_16;
2558 return D0EPCTL_MPS_8;
2561 /* bad max packet size, warn and return invalid result */
2567 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2568 * @hsotg: The driver state.
2569 * @ep: The index number of the endpoint
2570 * @mps: The maximum packet size in bytes
2571 * @mc: The multicount value
2572 * @dir_in: True if direction is in.
2574 * Configure the maximum packet size for the given endpoint, updating
2575 * the hardware control registers to reflect this.
2577 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2578 unsigned int ep, unsigned int mps,
2579 unsigned int mc, unsigned int dir_in)
2581 struct dwc2_hsotg_ep *hs_ep;
2584 hs_ep = index_to_ep(hsotg, ep, dir_in);
2589 u32 mps_bytes = mps;
2591 /* EP0 is a special case */
2592 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2595 hs_ep->ep.maxpacket = mps_bytes;
2603 hs_ep->ep.maxpacket = mps;
2607 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2608 reg &= ~DXEPCTL_MPS_MASK;
2610 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2612 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2613 reg &= ~DXEPCTL_MPS_MASK;
2615 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2621 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2625 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2626 * @hsotg: The driver state
2627 * @idx: The index for the endpoint (0..15)
2629 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2631 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2634 /* wait until the fifo is flushed */
2635 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2636 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2641 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2642 * @hsotg: The driver state
2643 * @hs_ep: The driver endpoint to check.
2645 * Check to see if there is a request that has data to send, and if so
2646 * make an attempt to write data into the FIFO.
2648 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2649 struct dwc2_hsotg_ep *hs_ep)
2651 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2653 if (!hs_ep->dir_in || !hs_req) {
2655 * if request is not enqueued, we disable interrupts
2656 * for endpoints, excepting ep0
2658 if (hs_ep->index != 0)
2659 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2664 if (hs_req->req.actual < hs_req->req.length) {
2665 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2667 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2674 * dwc2_hsotg_complete_in - complete IN transfer
2675 * @hsotg: The device state.
2676 * @hs_ep: The endpoint that has just completed.
2678 * An IN transfer has been completed, update the transfer's state and then
2679 * call the relevant completion routines.
2681 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2682 struct dwc2_hsotg_ep *hs_ep)
2684 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2685 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2686 int size_left, size_done;
2689 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2693 /* Finish ZLP handling for IN EP0 transactions */
2694 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2695 dev_dbg(hsotg->dev, "zlp packet sent\n");
2698 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2699 * changed to IN. Change back to complete OUT transfer request
2703 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2704 if (hsotg->test_mode) {
2707 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2709 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2711 dwc2_hsotg_stall_ep0(hsotg);
2715 dwc2_hsotg_enqueue_setup(hsotg);
2720 * Calculate the size of the transfer by checking how much is left
2721 * in the endpoint size register and then working it out from
2722 * the amount we loaded for the transfer.
2724 * We do this even for DMA, as the transfer may have incremented
2725 * past the end of the buffer (DMA transfers are always 32bit
2728 if (using_desc_dma(hsotg)) {
2729 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2731 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2734 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2737 size_done = hs_ep->size_loaded - size_left;
2738 size_done += hs_ep->last_load;
2740 if (hs_req->req.actual != size_done)
2741 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2742 __func__, hs_req->req.actual, size_done);
2744 hs_req->req.actual = size_done;
2745 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2746 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2748 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2749 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2750 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2754 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2755 if (hs_ep->send_zlp) {
2756 hs_ep->send_zlp = 0;
2757 if (!using_desc_dma(hsotg)) {
2758 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2759 /* transfer will be completed on next complete interrupt */
2764 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2765 /* Move to STATUS OUT */
2766 dwc2_hsotg_ep0_zlp(hsotg, false);
2770 /* Set actual frame number for completed transfers */
2771 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2772 hs_req->req.frame_number = hs_ep->target_frame;
2773 dwc2_gadget_incr_frame_num(hs_ep);
2776 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2780 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2781 * @hsotg: The device state.
2782 * @idx: Index of ep.
2783 * @dir_in: Endpoint direction 1-in 0-out.
2785 * Reads for endpoint with given index and direction, by masking
2786 * epint_reg with coresponding mask.
2788 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2789 unsigned int idx, int dir_in)
2791 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2792 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2797 mask = dwc2_readl(hsotg, epmsk_reg);
2798 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2799 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2800 mask |= DXEPINT_SETUP_RCVD;
2802 ints = dwc2_readl(hsotg, epint_reg);
2808 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2809 * @hs_ep: The endpoint on which interrupt is asserted.
2811 * This interrupt indicates that the endpoint has been disabled per the
2812 * application's request.
2814 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2815 * in case of ISOC completes current request.
2817 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2818 * request starts it.
2820 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2822 struct dwc2_hsotg *hsotg = hs_ep->parent;
2823 struct dwc2_hsotg_req *hs_req;
2824 unsigned char idx = hs_ep->index;
2825 int dir_in = hs_ep->dir_in;
2826 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2827 int dctl = dwc2_readl(hsotg, DCTL);
2829 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2832 int epctl = dwc2_readl(hsotg, epctl_reg);
2834 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2836 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2837 int dctl = dwc2_readl(hsotg, DCTL);
2839 dctl |= DCTL_CGNPINNAK;
2840 dwc2_writel(hsotg, dctl, DCTL);
2844 if (dctl & DCTL_GOUTNAKSTS) {
2845 dctl |= DCTL_CGOUTNAK;
2846 dwc2_writel(hsotg, dctl, DCTL);
2850 if (!hs_ep->isochronous)
2853 if (list_empty(&hs_ep->queue)) {
2854 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2860 hs_req = get_ep_head(hs_ep);
2862 hs_req->req.frame_number = hs_ep->target_frame;
2863 hs_req->req.actual = 0;
2864 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2867 dwc2_gadget_incr_frame_num(hs_ep);
2868 /* Update current frame number value. */
2869 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2870 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2874 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2875 * @ep: The endpoint on which interrupt is asserted.
2877 * This is starting point for ISOC-OUT transfer, synchronization done with
2878 * first out token received from host while corresponding EP is disabled.
2880 * Device does not know initial frame in which out token will come. For this
2881 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2882 * getting this interrupt SW starts calculation for next transfer frame.
2884 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2886 struct dwc2_hsotg *hsotg = ep->parent;
2887 struct dwc2_hsotg_req *hs_req;
2888 int dir_in = ep->dir_in;
2890 if (dir_in || !ep->isochronous)
2893 if (using_desc_dma(hsotg)) {
2894 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2895 /* Start first ISO Out */
2896 ep->target_frame = hsotg->frame_number;
2897 dwc2_gadget_start_isoc_ddma(ep);
2902 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2905 ep->target_frame = hsotg->frame_number;
2906 if (ep->interval > 1) {
2907 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2908 if (ep->target_frame & 0x1)
2909 ctrl |= DXEPCTL_SETODDFR;
2911 ctrl |= DXEPCTL_SETEVENFR;
2913 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2917 while (dwc2_gadget_target_frame_elapsed(ep)) {
2918 hs_req = get_ep_head(ep);
2920 hs_req->req.frame_number = ep->target_frame;
2921 hs_req->req.actual = 0;
2922 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2925 dwc2_gadget_incr_frame_num(ep);
2926 /* Update current frame number value. */
2927 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2931 dwc2_gadget_start_next_request(ep);
2935 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2936 struct dwc2_hsotg_ep *hs_ep);
2939 * dwc2_gadget_handle_nak - handle NAK interrupt
2940 * @hs_ep: The endpoint on which interrupt is asserted.
2942 * This is starting point for ISOC-IN transfer, synchronization done with
2943 * first IN token received from host while corresponding EP is disabled.
2945 * Device does not know when first one token will arrive from host. On first
2946 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2947 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2948 * sent in response to that as there was no data in FIFO. SW is basing on this
2949 * interrupt to obtain frame in which token has come and then based on the
2950 * interval calculates next frame for transfer.
2952 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2954 struct dwc2_hsotg *hsotg = hs_ep->parent;
2955 struct dwc2_hsotg_req *hs_req;
2956 int dir_in = hs_ep->dir_in;
2959 if (!dir_in || !hs_ep->isochronous)
2962 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2964 if (using_desc_dma(hsotg)) {
2965 hs_ep->target_frame = hsotg->frame_number;
2966 dwc2_gadget_incr_frame_num(hs_ep);
2968 /* In service interval mode target_frame must
2969 * be set to last (u)frame of the service interval.
2971 if (hsotg->params.service_interval) {
2972 /* Set target_frame to the first (u)frame of
2973 * the service interval
2975 hs_ep->target_frame &= ~hs_ep->interval + 1;
2977 /* Set target_frame to the last (u)frame of
2978 * the service interval
2980 dwc2_gadget_incr_frame_num(hs_ep);
2981 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2984 dwc2_gadget_start_isoc_ddma(hs_ep);
2988 hs_ep->target_frame = hsotg->frame_number;
2989 if (hs_ep->interval > 1) {
2990 u32 ctrl = dwc2_readl(hsotg,
2991 DIEPCTL(hs_ep->index));
2992 if (hs_ep->target_frame & 0x1)
2993 ctrl |= DXEPCTL_SETODDFR;
2995 ctrl |= DXEPCTL_SETEVENFR;
2997 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
3001 if (using_desc_dma(hsotg))
3004 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3005 if (ctrl & DXEPCTL_EPENA)
3006 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3008 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3010 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3011 hs_req = get_ep_head(hs_ep);
3013 hs_req->req.frame_number = hs_ep->target_frame;
3014 hs_req->req.actual = 0;
3015 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3018 dwc2_gadget_incr_frame_num(hs_ep);
3019 /* Update current frame number value. */
3020 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3024 dwc2_gadget_start_next_request(hs_ep);
3028 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3029 * @hsotg: The driver state
3030 * @idx: The index for the endpoint (0..15)
3031 * @dir_in: Set if this is an IN endpoint
3033 * Process and clear any interrupt pending for an individual endpoint
3035 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3038 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3039 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3040 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3041 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3044 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3046 /* Clear endpoint interrupts */
3047 dwc2_writel(hsotg, ints, epint_reg);
3050 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3051 __func__, idx, dir_in ? "in" : "out");
3055 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3056 __func__, idx, dir_in ? "in" : "out", ints);
3058 /* Don't process XferCompl interrupt if it is a setup packet */
3059 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3060 ints &= ~DXEPINT_XFERCOMPL;
3063 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3064 * stage and xfercomplete was generated without SETUP phase done
3065 * interrupt. SW should parse received setup packet only after host's
3066 * exit from setup phase of control transfer.
3068 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3069 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3070 ints &= ~DXEPINT_XFERCOMPL;
3072 if (ints & DXEPINT_XFERCOMPL) {
3074 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3075 __func__, dwc2_readl(hsotg, epctl_reg),
3076 dwc2_readl(hsotg, epsiz_reg));
3078 /* In DDMA handle isochronous requests separately */
3079 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3080 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3081 } else if (dir_in) {
3083 * We get OutDone from the FIFO, so we only
3084 * need to look at completing IN requests here
3085 * if operating slave mode
3087 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3088 dwc2_hsotg_complete_in(hsotg, hs_ep);
3090 if (idx == 0 && !hs_ep->req)
3091 dwc2_hsotg_enqueue_setup(hsotg);
3092 } else if (using_dma(hsotg)) {
3094 * We're using DMA, we need to fire an OutDone here
3095 * as we ignore the RXFIFO.
3097 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3098 dwc2_hsotg_handle_outdone(hsotg, idx);
3102 if (ints & DXEPINT_EPDISBLD)
3103 dwc2_gadget_handle_ep_disabled(hs_ep);
3105 if (ints & DXEPINT_OUTTKNEPDIS)
3106 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3108 if (ints & DXEPINT_NAKINTRPT)
3109 dwc2_gadget_handle_nak(hs_ep);
3111 if (ints & DXEPINT_AHBERR)
3112 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3114 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3115 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3117 if (using_dma(hsotg) && idx == 0) {
3119 * this is the notification we've received a
3120 * setup packet. In non-DMA mode we'd get this
3121 * from the RXFIFO, instead we need to process
3128 dwc2_hsotg_handle_outdone(hsotg, 0);
3132 if (ints & DXEPINT_STSPHSERCVD) {
3133 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3135 /* Safety check EP0 state when STSPHSERCVD asserted */
3136 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3137 /* Move to STATUS IN for DDMA */
3138 if (using_desc_dma(hsotg)) {
3139 if (!hsotg->delayed_status)
3140 dwc2_hsotg_ep0_zlp(hsotg, true);
3142 /* In case of 3 stage Control Write with delayed
3143 * status, when Status IN transfer started
3144 * before STSPHSERCVD asserted, NAKSTS bit not
3145 * cleared by CNAK in dwc2_hsotg_start_req()
3146 * function. Clear now NAKSTS to allow complete
3149 dwc2_set_bit(hsotg, DIEPCTL(0),
3156 if (ints & DXEPINT_BACK2BACKSETUP)
3157 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3159 if (ints & DXEPINT_BNAINTR) {
3160 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3161 if (hs_ep->isochronous)
3162 dwc2_gadget_handle_isoc_bna(hs_ep);
3165 if (dir_in && !hs_ep->isochronous) {
3166 /* not sure if this is important, but we'll clear it anyway */
3167 if (ints & DXEPINT_INTKNTXFEMP) {
3168 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3172 /* this probably means something bad is happening */
3173 if (ints & DXEPINT_INTKNEPMIS) {
3174 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3178 /* FIFO has space or is empty (see GAHBCFG) */
3179 if (hsotg->dedicated_fifos &&
3180 ints & DXEPINT_TXFEMP) {
3181 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3183 if (!using_dma(hsotg))
3184 dwc2_hsotg_trytx(hsotg, hs_ep);
3190 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3191 * @hsotg: The device state.
3193 * Handle updating the device settings after the enumeration phase has
3196 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3198 u32 dsts = dwc2_readl(hsotg, DSTS);
3199 int ep0_mps = 0, ep_mps = 8;
3202 * This should signal the finish of the enumeration phase
3203 * of the USB handshaking, so we should now know what rate
3207 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3210 * note, since we're limited by the size of transfer on EP0, and
3211 * it seems IN transfers must be a even number of packets we do
3212 * not advertise a 64byte MPS on EP0.
3215 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3216 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3217 case DSTS_ENUMSPD_FS:
3218 case DSTS_ENUMSPD_FS48:
3219 hsotg->gadget.speed = USB_SPEED_FULL;
3220 ep0_mps = EP0_MPS_LIMIT;
3224 case DSTS_ENUMSPD_HS:
3225 hsotg->gadget.speed = USB_SPEED_HIGH;
3226 ep0_mps = EP0_MPS_LIMIT;
3230 case DSTS_ENUMSPD_LS:
3231 hsotg->gadget.speed = USB_SPEED_LOW;
3235 * note, we don't actually support LS in this driver at the
3236 * moment, and the documentation seems to imply that it isn't
3237 * supported by the PHYs on some of the devices.
3241 dev_info(hsotg->dev, "new device is %s\n",
3242 usb_speed_string(hsotg->gadget.speed));
3245 * we should now know the maximum packet size for an
3246 * endpoint, so set the endpoints to a default value.
3251 /* Initialize ep0 for both in and out directions */
3252 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3253 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3254 for (i = 1; i < hsotg->num_of_eps; i++) {
3255 if (hsotg->eps_in[i])
3256 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3258 if (hsotg->eps_out[i])
3259 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3264 /* ensure after enumeration our EP0 is active */
3266 dwc2_hsotg_enqueue_setup(hsotg);
3268 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3269 dwc2_readl(hsotg, DIEPCTL0),
3270 dwc2_readl(hsotg, DOEPCTL0));
3274 * kill_all_requests - remove all requests from the endpoint's queue
3275 * @hsotg: The device state.
3276 * @ep: The endpoint the requests may be on.
3277 * @result: The result code to use.
3279 * Go through the requests on the given endpoint and mark them
3280 * completed with the given result code.
3282 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3283 struct dwc2_hsotg_ep *ep,
3290 while (!list_empty(&ep->queue)) {
3291 struct dwc2_hsotg_req *req = get_ep_head(ep);
3293 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3296 if (!hsotg->dedicated_fifos)
3298 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3299 if (size < ep->fifo_size)
3300 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3304 * dwc2_hsotg_disconnect - disconnect service
3305 * @hsotg: The device state.
3307 * The device has been disconnected. Remove all current
3308 * transactions and signal the gadget driver that this
3311 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3315 if (!hsotg->connected)
3318 hsotg->connected = 0;
3319 hsotg->test_mode = 0;
3321 /* all endpoints should be shutdown */
3322 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3323 if (hsotg->eps_in[ep])
3324 kill_all_requests(hsotg, hsotg->eps_in[ep],
3326 if (hsotg->eps_out[ep])
3327 kill_all_requests(hsotg, hsotg->eps_out[ep],
3331 call_gadget(hsotg, disconnect);
3332 hsotg->lx_state = DWC2_L3;
3334 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3338 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3339 * @hsotg: The device state:
3340 * @periodic: True if this is a periodic FIFO interrupt
3342 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3344 struct dwc2_hsotg_ep *ep;
3347 /* look through for any more data to transmit */
3348 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3349 ep = index_to_ep(hsotg, epno, 1);
3357 if ((periodic && !ep->periodic) ||
3358 (!periodic && ep->periodic))
3361 ret = dwc2_hsotg_trytx(hsotg, ep);
3367 /* IRQ flags which will trigger a retry around the IRQ loop */
3368 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3372 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3374 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3375 * @hsotg: The device state
3376 * @is_usb_reset: Usb resetting flag
3378 * Issue a soft reset to the core, and await the core finishing it.
3380 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3389 /* Kill any ep0 requests as controller will be reinitialized */
3390 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3392 if (!is_usb_reset) {
3393 if (dwc2_core_reset(hsotg, true))
3396 /* all endpoints should be shutdown */
3397 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3398 if (hsotg->eps_in[ep])
3399 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3400 if (hsotg->eps_out[ep])
3401 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3406 * we must now enable ep0 ready for host detection and then
3407 * set configuration.
3410 /* keep other bits untouched (so e.g. forced modes are not lost) */
3411 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3412 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3413 usbcfg |= GUSBCFG_TOUTCAL(7);
3415 /* remove the HNP/SRP and set the PHY */
3416 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3417 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3419 dwc2_phy_init(hsotg, true);
3421 dwc2_hsotg_init_fifo(hsotg);
3424 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3426 dcfg |= DCFG_EPMISCNT(1);
3428 switch (hsotg->params.speed) {
3429 case DWC2_SPEED_PARAM_LOW:
3430 dcfg |= DCFG_DEVSPD_LS;
3432 case DWC2_SPEED_PARAM_FULL:
3433 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3434 dcfg |= DCFG_DEVSPD_FS48;
3436 dcfg |= DCFG_DEVSPD_FS;
3439 dcfg |= DCFG_DEVSPD_HS;
3442 if (hsotg->params.ipg_isoc_en)
3443 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3445 dwc2_writel(hsotg, dcfg, DCFG);
3447 /* Clear any pending OTG interrupts */
3448 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3450 /* Clear any pending interrupts */
3451 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3452 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3453 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3454 GINTSTS_USBRST | GINTSTS_RESETDET |
3455 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3456 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3457 GINTSTS_LPMTRANRCVD;
3459 if (!using_desc_dma(hsotg))
3460 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3462 if (!hsotg->params.external_id_pin_ctl)
3463 intmsk |= GINTSTS_CONIDSTSCHNG;
3465 dwc2_writel(hsotg, intmsk, GINTMSK);
3467 if (using_dma(hsotg)) {
3468 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3469 hsotg->params.ahbcfg,
3472 /* Set DDMA mode support in the core if needed */
3473 if (using_desc_dma(hsotg))
3474 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3477 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3478 (GAHBCFG_NP_TXF_EMP_LVL |
3479 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3480 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3484 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3485 * when we have no data to transfer. Otherwise we get being flooded by
3489 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3490 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3491 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3492 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3496 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3497 * DMA mode we may need this and StsPhseRcvd.
3499 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3500 DOEPMSK_STSPHSERCVDMSK) : 0) |
3501 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3505 /* Enable BNA interrupt for DDMA */
3506 if (using_desc_dma(hsotg)) {
3507 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3508 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3511 /* Enable Service Interval mode if supported */
3512 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3513 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3515 dwc2_writel(hsotg, 0, DAINTMSK);
3517 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3518 dwc2_readl(hsotg, DIEPCTL0),
3519 dwc2_readl(hsotg, DOEPCTL0));
3521 /* enable in and out endpoint interrupts */
3522 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3525 * Enable the RXFIFO when in slave mode, as this is how we collect
3526 * the data. In DMA mode, we get events from the FIFO but also
3527 * things we cannot process, so do not use it.
3529 if (!using_dma(hsotg))
3530 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3532 /* Enable interrupts for EP0 in and out */
3533 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3534 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3536 if (!is_usb_reset) {
3537 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3538 udelay(10); /* see openiboot */
3539 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3542 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3545 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3546 * writing to the EPCTL register..
3549 /* set to read 1 8byte packet */
3550 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3551 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3553 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3554 DXEPCTL_CNAK | DXEPCTL_EPENA |
3558 /* enable, but don't activate EP0in */
3559 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3560 DXEPCTL_USBACTEP, DIEPCTL0);
3562 /* clear global NAKs */
3563 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3565 val |= DCTL_SFTDISCON;
3566 dwc2_set_bit(hsotg, DCTL, val);
3568 /* configure the core to support LPM */
3569 dwc2_gadget_init_lpm(hsotg);
3571 /* program GREFCLK register if needed */
3572 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3573 dwc2_gadget_program_ref_clk(hsotg);
3575 /* must be at-least 3ms to allow bus to see disconnect */
3578 hsotg->lx_state = DWC2_L0;
3580 dwc2_hsotg_enqueue_setup(hsotg);
3582 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3583 dwc2_readl(hsotg, DIEPCTL0),
3584 dwc2_readl(hsotg, DOEPCTL0));
3587 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3589 /* set the soft-disconnect bit */
3590 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3593 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3595 /* remove the soft-disconnect and let's go */
3596 if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3597 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3601 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3602 * @hsotg: The device state:
3604 * This interrupt indicates one of the following conditions occurred while
3605 * transmitting an ISOC transaction.
3606 * - Corrupted IN Token for ISOC EP.
3607 * - Packet not complete in FIFO.
3609 * The following actions will be taken:
3610 * - Determine the EP
3611 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3613 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3615 struct dwc2_hsotg_ep *hs_ep;
3620 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3622 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3624 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3625 hs_ep = hsotg->eps_in[idx];
3626 /* Proceed only unmasked ISOC EPs */
3627 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3630 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3631 if ((epctrl & DXEPCTL_EPENA) &&
3632 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3633 epctrl |= DXEPCTL_SNAK;
3634 epctrl |= DXEPCTL_EPDIS;
3635 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3639 /* Clear interrupt */
3640 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3644 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3645 * @hsotg: The device state:
3647 * This interrupt indicates one of the following conditions occurred while
3648 * transmitting an ISOC transaction.
3649 * - Corrupted OUT Token for ISOC EP.
3650 * - Packet not complete in FIFO.
3652 * The following actions will be taken:
3653 * - Determine the EP
3654 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3656 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3662 struct dwc2_hsotg_ep *hs_ep;
3665 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3667 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3668 daintmsk >>= DAINT_OUTEP_SHIFT;
3670 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3671 hs_ep = hsotg->eps_out[idx];
3672 /* Proceed only unmasked ISOC EPs */
3673 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3676 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3677 if ((epctrl & DXEPCTL_EPENA) &&
3678 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3679 /* Unmask GOUTNAKEFF interrupt */
3680 gintmsk = dwc2_readl(hsotg, GINTMSK);
3681 gintmsk |= GINTSTS_GOUTNAKEFF;
3682 dwc2_writel(hsotg, gintmsk, GINTMSK);
3684 gintsts = dwc2_readl(hsotg, GINTSTS);
3685 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3686 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3692 /* Clear interrupt */
3693 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3697 * dwc2_hsotg_irq - handle device interrupt
3698 * @irq: The IRQ number triggered
3699 * @pw: The pw value when registered the handler.
3701 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3703 struct dwc2_hsotg *hsotg = pw;
3704 int retry_count = 8;
3708 if (!dwc2_is_device_mode(hsotg))
3711 spin_lock(&hsotg->lock);
3713 gintsts = dwc2_readl(hsotg, GINTSTS);
3714 gintmsk = dwc2_readl(hsotg, GINTMSK);
3716 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3717 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3721 if (gintsts & GINTSTS_RESETDET) {
3722 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3724 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3726 /* This event must be used only if controller is suspended */
3727 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3728 dwc2_exit_partial_power_down(hsotg, 0, true);
3730 hsotg->lx_state = DWC2_L0;
3733 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3734 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3735 u32 connected = hsotg->connected;
3737 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3738 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3739 dwc2_readl(hsotg, GNPTXSTS));
3741 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3743 /* Report disconnection if it is not already done. */
3744 dwc2_hsotg_disconnect(hsotg);
3746 /* Reset device address to zero */
3747 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3749 if (usb_status & GOTGCTL_BSESVLD && connected)
3750 dwc2_hsotg_core_init_disconnected(hsotg, true);
3753 if (gintsts & GINTSTS_ENUMDONE) {
3754 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3756 dwc2_hsotg_irq_enumdone(hsotg);
3759 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3760 u32 daint = dwc2_readl(hsotg, DAINT);
3761 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3762 u32 daint_out, daint_in;
3766 daint_out = daint >> DAINT_OUTEP_SHIFT;
3767 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3769 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3771 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3772 ep++, daint_out >>= 1) {
3774 dwc2_hsotg_epint(hsotg, ep, 0);
3777 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3778 ep++, daint_in >>= 1) {
3780 dwc2_hsotg_epint(hsotg, ep, 1);
3784 /* check both FIFOs */
3786 if (gintsts & GINTSTS_NPTXFEMP) {
3787 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3790 * Disable the interrupt to stop it happening again
3791 * unless one of these endpoint routines decides that
3792 * it needs re-enabling
3795 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3796 dwc2_hsotg_irq_fifoempty(hsotg, false);
3799 if (gintsts & GINTSTS_PTXFEMP) {
3800 dev_dbg(hsotg->dev, "PTxFEmp\n");
3802 /* See note in GINTSTS_NPTxFEmp */
3804 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3805 dwc2_hsotg_irq_fifoempty(hsotg, true);
3808 if (gintsts & GINTSTS_RXFLVL) {
3810 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3811 * we need to retry dwc2_hsotg_handle_rx if this is still
3815 dwc2_hsotg_handle_rx(hsotg);
3818 if (gintsts & GINTSTS_ERLYSUSP) {
3819 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3820 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3824 * these next two seem to crop-up occasionally causing the core
3825 * to shutdown the USB transfer, so try clearing them and logging
3829 if (gintsts & GINTSTS_GOUTNAKEFF) {
3834 struct dwc2_hsotg_ep *hs_ep;
3836 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3837 daintmsk >>= DAINT_OUTEP_SHIFT;
3838 /* Mask this interrupt */
3839 gintmsk = dwc2_readl(hsotg, GINTMSK);
3840 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3841 dwc2_writel(hsotg, gintmsk, GINTMSK);
3843 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3844 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3845 hs_ep = hsotg->eps_out[idx];
3846 /* Proceed only unmasked ISOC EPs */
3847 if (BIT(idx) & ~daintmsk)
3850 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3853 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3854 epctrl |= DXEPCTL_SNAK;
3855 epctrl |= DXEPCTL_EPDIS;
3856 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3861 if (hs_ep->halted) {
3862 if (!(epctrl & DXEPCTL_EPENA))
3863 epctrl |= DXEPCTL_EPENA;
3864 epctrl |= DXEPCTL_EPDIS;
3865 epctrl |= DXEPCTL_STALL;
3866 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3870 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3873 if (gintsts & GINTSTS_GINNAKEFF) {
3874 dev_info(hsotg->dev, "GINNakEff triggered\n");
3876 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3878 dwc2_hsotg_dump(hsotg);
3881 if (gintsts & GINTSTS_INCOMPL_SOIN)
3882 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3884 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3885 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3888 * if we've had fifo events, we should try and go around the
3889 * loop again to see if there's any point in returning yet.
3892 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3895 /* Check WKUP_ALERT interrupt*/
3896 if (hsotg->params.service_interval)
3897 dwc2_gadget_wkup_alert_handler(hsotg);
3899 spin_unlock(&hsotg->lock);
3904 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3905 struct dwc2_hsotg_ep *hs_ep)
3910 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3911 DOEPCTL(hs_ep->index);
3912 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3913 DOEPINT(hs_ep->index);
3915 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3918 if (hs_ep->dir_in) {
3919 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3920 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3921 /* Wait for Nak effect */
3922 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3923 DXEPINT_INEPNAKEFF, 100))
3924 dev_warn(hsotg->dev,
3925 "%s: timeout DIEPINT.NAKEFF\n",
3928 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3929 /* Wait for Nak effect */
3930 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3931 GINTSTS_GINNAKEFF, 100))
3932 dev_warn(hsotg->dev,
3933 "%s: timeout GINTSTS.GINNAKEFF\n",
3937 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3938 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3940 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3941 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3943 if (!using_dma(hsotg)) {
3944 /* Wait for GINTSTS_RXFLVL interrupt */
3945 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3946 GINTSTS_RXFLVL, 100)) {
3947 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3951 * Pop GLOBAL OUT NAK status packet from RxFIFO
3952 * to assert GOUTNAKEFF interrupt
3954 dwc2_readl(hsotg, GRXSTSP);
3958 /* Wait for global nak to take effect */
3959 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3960 GINTSTS_GOUTNAKEFF, 100))
3961 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3966 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3968 /* Wait for ep to be disabled */
3969 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3970 dev_warn(hsotg->dev,
3971 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3973 /* Clear EPDISBLD interrupt */
3974 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3976 if (hs_ep->dir_in) {
3977 unsigned short fifo_index;
3979 if (hsotg->dedicated_fifos || hs_ep->periodic)
3980 fifo_index = hs_ep->fifo_index;
3985 dwc2_flush_tx_fifo(hsotg, fifo_index);
3987 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3988 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3989 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3992 /* Remove global NAKs */
3993 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
3998 * dwc2_hsotg_ep_enable - enable the given endpoint
3999 * @ep: The USB endpint to configure
4000 * @desc: The USB endpoint descriptor to configure with.
4002 * This is called from the USB gadget code's usb_ep_enable().
4004 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
4005 const struct usb_endpoint_descriptor *desc)
4007 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4008 struct dwc2_hsotg *hsotg = hs_ep->parent;
4009 unsigned long flags;
4010 unsigned int index = hs_ep->index;
4016 unsigned int dir_in;
4017 unsigned int i, val, size;
4019 unsigned char ep_type;
4023 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4024 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4025 desc->wMaxPacketSize, desc->bInterval);
4027 /* not to be called for EP0 */
4029 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4033 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4034 if (dir_in != hs_ep->dir_in) {
4035 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4039 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4040 mps = usb_endpoint_maxp(desc);
4041 mc = usb_endpoint_maxp_mult(desc);
4043 /* ISOC IN in DDMA supported bInterval up to 10 */
4044 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4045 dir_in && desc->bInterval > 10) {
4047 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4051 /* High bandwidth ISOC OUT in DDMA not supported */
4052 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4053 !dir_in && mc > 1) {
4055 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4059 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4061 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4062 epctrl = dwc2_readl(hsotg, epctrl_reg);
4064 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4065 __func__, epctrl, epctrl_reg);
4067 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4068 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4070 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4072 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4073 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4074 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4075 desc_num * sizeof(struct dwc2_dma_desc),
4076 &hs_ep->desc_list_dma, GFP_ATOMIC);
4077 if (!hs_ep->desc_list) {
4083 spin_lock_irqsave(&hsotg->lock, flags);
4085 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4086 epctrl |= DXEPCTL_MPS(mps);
4089 * mark the endpoint as active, otherwise the core may ignore
4090 * transactions entirely for this endpoint
4092 epctrl |= DXEPCTL_USBACTEP;
4094 /* update the endpoint state */
4095 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4097 /* default, set to non-periodic */
4098 hs_ep->isochronous = 0;
4099 hs_ep->periodic = 0;
4102 hs_ep->interval = desc->bInterval;
4105 case USB_ENDPOINT_XFER_ISOC:
4106 epctrl |= DXEPCTL_EPTYPE_ISO;
4107 epctrl |= DXEPCTL_SETEVENFR;
4108 hs_ep->isochronous = 1;
4109 hs_ep->interval = 1 << (desc->bInterval - 1);
4110 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4111 hs_ep->next_desc = 0;
4112 hs_ep->compl_desc = 0;
4114 hs_ep->periodic = 1;
4115 mask = dwc2_readl(hsotg, DIEPMSK);
4116 mask |= DIEPMSK_NAKMSK;
4117 dwc2_writel(hsotg, mask, DIEPMSK);
4119 epctrl |= DXEPCTL_SNAK;
4120 mask = dwc2_readl(hsotg, DOEPMSK);
4121 mask |= DOEPMSK_OUTTKNEPDISMSK;
4122 dwc2_writel(hsotg, mask, DOEPMSK);
4126 case USB_ENDPOINT_XFER_BULK:
4127 epctrl |= DXEPCTL_EPTYPE_BULK;
4130 case USB_ENDPOINT_XFER_INT:
4132 hs_ep->periodic = 1;
4134 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4135 hs_ep->interval = 1 << (desc->bInterval - 1);
4137 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4140 case USB_ENDPOINT_XFER_CONTROL:
4141 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4146 * if the hardware has dedicated fifos, we must give each IN EP
4147 * a unique tx-fifo even if it is non-periodic.
4149 if (dir_in && hsotg->dedicated_fifos) {
4150 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4152 u32 fifo_size = UINT_MAX;
4154 size = hs_ep->ep.maxpacket * hs_ep->mc;
4155 for (i = 1; i <= fifo_count; ++i) {
4156 if (hsotg->fifo_map & (1 << i))
4158 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4159 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4162 /* Search for smallest acceptable fifo */
4163 if (val < fifo_size) {
4170 "%s: No suitable fifo found\n", __func__);
4174 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4175 hsotg->fifo_map |= 1 << fifo_index;
4176 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4177 hs_ep->fifo_index = fifo_index;
4178 hs_ep->fifo_size = fifo_size;
4181 /* for non control endpoints, set PID to D0 */
4182 if (index && !hs_ep->isochronous)
4183 epctrl |= DXEPCTL_SETD0PID;
4185 /* WA for Full speed ISOC IN in DDMA mode.
4186 * By Clear NAK status of EP, core will send ZLP
4187 * to IN token and assert NAK interrupt relying
4188 * on TxFIFO status only
4191 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4192 hs_ep->isochronous && dir_in) {
4193 /* The WA applies only to core versions from 2.72a
4194 * to 4.00a (including both). Also for FS_IOT_1.00a
4197 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4199 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4200 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4201 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4202 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4203 epctrl |= DXEPCTL_CNAK;
4206 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4209 dwc2_writel(hsotg, epctrl, epctrl_reg);
4210 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4211 __func__, dwc2_readl(hsotg, epctrl_reg));
4213 /* enable the endpoint interrupt */
4214 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4217 spin_unlock_irqrestore(&hsotg->lock, flags);
4220 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4221 dmam_free_coherent(hsotg->dev, desc_num *
4222 sizeof(struct dwc2_dma_desc),
4223 hs_ep->desc_list, hs_ep->desc_list_dma);
4224 hs_ep->desc_list = NULL;
4231 * dwc2_hsotg_ep_disable - disable given endpoint
4232 * @ep: The endpoint to disable.
4234 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4236 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4237 struct dwc2_hsotg *hsotg = hs_ep->parent;
4238 int dir_in = hs_ep->dir_in;
4239 int index = hs_ep->index;
4243 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4245 if (ep == &hsotg->eps_out[0]->ep) {
4246 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4250 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4251 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4255 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4257 ctrl = dwc2_readl(hsotg, epctrl_reg);
4259 if (ctrl & DXEPCTL_EPENA)
4260 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4262 ctrl &= ~DXEPCTL_EPENA;
4263 ctrl &= ~DXEPCTL_USBACTEP;
4264 ctrl |= DXEPCTL_SNAK;
4266 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4267 dwc2_writel(hsotg, ctrl, epctrl_reg);
4269 /* disable endpoint interrupts */
4270 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4272 /* terminate all requests with shutdown */
4273 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4275 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4276 hs_ep->fifo_index = 0;
4277 hs_ep->fifo_size = 0;
4282 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4284 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4285 struct dwc2_hsotg *hsotg = hs_ep->parent;
4286 unsigned long flags;
4289 spin_lock_irqsave(&hsotg->lock, flags);
4290 ret = dwc2_hsotg_ep_disable(ep);
4291 spin_unlock_irqrestore(&hsotg->lock, flags);
4296 * on_list - check request is on the given endpoint
4297 * @ep: The endpoint to check.
4298 * @test: The request to test if it is on the endpoint.
4300 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4302 struct dwc2_hsotg_req *req, *treq;
4304 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4313 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4314 * @ep: The endpoint to dequeue.
4315 * @req: The request to be removed from a queue.
4317 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4319 struct dwc2_hsotg_req *hs_req = our_req(req);
4320 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4321 struct dwc2_hsotg *hs = hs_ep->parent;
4322 unsigned long flags;
4324 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4326 spin_lock_irqsave(&hs->lock, flags);
4328 if (!on_list(hs_ep, hs_req)) {
4329 spin_unlock_irqrestore(&hs->lock, flags);
4333 /* Dequeue already started request */
4334 if (req == &hs_ep->req->req)
4335 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4337 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4338 spin_unlock_irqrestore(&hs->lock, flags);
4344 * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
4345 * @ep: The endpoint to be wedged.
4348 static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
4350 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4351 struct dwc2_hsotg *hs = hs_ep->parent;
4353 unsigned long flags;
4356 spin_lock_irqsave(&hs->lock, flags);
4358 ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
4359 spin_unlock_irqrestore(&hs->lock, flags);
4365 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4366 * @ep: The endpoint to set halt.
4367 * @value: Set or unset the halt.
4368 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4369 * the endpoint is busy processing requests.
4371 * We need to stall the endpoint immediately if request comes from set_feature
4372 * protocol command handler.
4374 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4376 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4377 struct dwc2_hsotg *hs = hs_ep->parent;
4378 int index = hs_ep->index;
4383 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4387 dwc2_hsotg_stall_ep0(hs);
4390 "%s: can't clear halt on ep0\n", __func__);
4394 if (hs_ep->isochronous) {
4395 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4399 if (!now && value && !list_empty(&hs_ep->queue)) {
4400 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4405 if (hs_ep->dir_in) {
4406 epreg = DIEPCTL(index);
4407 epctl = dwc2_readl(hs, epreg);
4410 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4411 if (epctl & DXEPCTL_EPENA)
4412 epctl |= DXEPCTL_EPDIS;
4414 epctl &= ~DXEPCTL_STALL;
4416 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4417 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4418 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4419 epctl |= DXEPCTL_SETD0PID;
4421 dwc2_writel(hs, epctl, epreg);
4423 epreg = DOEPCTL(index);
4424 epctl = dwc2_readl(hs, epreg);
4427 /* Unmask GOUTNAKEFF interrupt */
4428 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4430 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4431 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4432 // STALL bit will be set in GOUTNAKEFF interrupt handler
4434 epctl &= ~DXEPCTL_STALL;
4436 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4437 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4438 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4439 epctl |= DXEPCTL_SETD0PID;
4440 dwc2_writel(hs, epctl, epreg);
4444 hs_ep->halted = value;
4449 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4450 * @ep: The endpoint to set halt.
4451 * @value: Set or unset the halt.
4453 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4455 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4456 struct dwc2_hsotg *hs = hs_ep->parent;
4457 unsigned long flags;
4460 spin_lock_irqsave(&hs->lock, flags);
4461 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4462 spin_unlock_irqrestore(&hs->lock, flags);
4467 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4468 .enable = dwc2_hsotg_ep_enable,
4469 .disable = dwc2_hsotg_ep_disable_lock,
4470 .alloc_request = dwc2_hsotg_ep_alloc_request,
4471 .free_request = dwc2_hsotg_ep_free_request,
4472 .queue = dwc2_hsotg_ep_queue_lock,
4473 .dequeue = dwc2_hsotg_ep_dequeue,
4474 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4475 .set_wedge = dwc2_gadget_ep_set_wedge,
4476 /* note, don't believe we have any call for the fifo routines */
4480 * dwc2_hsotg_init - initialize the usb core
4481 * @hsotg: The driver state
4483 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4485 /* unmask subset of endpoint interrupts */
4487 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4488 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4491 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4492 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4495 dwc2_writel(hsotg, 0, DAINTMSK);
4497 /* Be in disconnected state until gadget is registered */
4498 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4502 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4503 dwc2_readl(hsotg, GRXFSIZ),
4504 dwc2_readl(hsotg, GNPTXFSIZ));
4506 dwc2_hsotg_init_fifo(hsotg);
4508 if (using_dma(hsotg))
4509 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4513 * dwc2_hsotg_udc_start - prepare the udc for work
4514 * @gadget: The usb gadget state
4515 * @driver: The usb gadget driver
4517 * Perform initialization to prepare udc device and driver
4520 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4521 struct usb_gadget_driver *driver)
4523 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4524 unsigned long flags;
4528 pr_err("%s: called with no device\n", __func__);
4533 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4537 if (driver->max_speed < USB_SPEED_FULL)
4538 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4540 if (!driver->setup) {
4541 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4545 WARN_ON(hsotg->driver);
4547 hsotg->driver = driver;
4548 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4549 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4551 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4552 ret = dwc2_lowlevel_hw_enable(hsotg);
4557 if (!IS_ERR_OR_NULL(hsotg->uphy))
4558 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4560 spin_lock_irqsave(&hsotg->lock, flags);
4561 if (dwc2_hw_is_device(hsotg)) {
4562 dwc2_hsotg_init(hsotg);
4563 dwc2_hsotg_core_init_disconnected(hsotg, false);
4567 spin_unlock_irqrestore(&hsotg->lock, flags);
4569 gadget->sg_supported = using_desc_dma(hsotg);
4570 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4575 hsotg->driver = NULL;
4580 * dwc2_hsotg_udc_stop - stop the udc
4581 * @gadget: The usb gadget state
4583 * Stop udc hw block and stay tunned for future transmissions
4585 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4587 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4588 unsigned long flags;
4594 /* all endpoints should be shutdown */
4595 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4596 if (hsotg->eps_in[ep])
4597 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4598 if (hsotg->eps_out[ep])
4599 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4602 spin_lock_irqsave(&hsotg->lock, flags);
4604 hsotg->driver = NULL;
4605 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4608 spin_unlock_irqrestore(&hsotg->lock, flags);
4610 if (!IS_ERR_OR_NULL(hsotg->uphy))
4611 otg_set_peripheral(hsotg->uphy->otg, NULL);
4613 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4614 dwc2_lowlevel_hw_disable(hsotg);
4620 * dwc2_hsotg_gadget_getframe - read the frame number
4621 * @gadget: The usb gadget state
4623 * Read the {micro} frame number
4625 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4627 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4631 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4632 * @gadget: The usb gadget state
4633 * @is_selfpowered: Whether the device is self-powered
4635 * Set if the device is self or bus powered.
4637 static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4640 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4641 unsigned long flags;
4643 spin_lock_irqsave(&hsotg->lock, flags);
4644 gadget->is_selfpowered = !!is_selfpowered;
4645 spin_unlock_irqrestore(&hsotg->lock, flags);
4651 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4652 * @gadget: The usb gadget state
4653 * @is_on: Current state of the USB PHY
4655 * Connect/Disconnect the USB PHY pullup
4657 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4659 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4660 unsigned long flags;
4662 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4665 /* Don't modify pullup state while in host mode */
4666 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4667 hsotg->enabled = is_on;
4671 spin_lock_irqsave(&hsotg->lock, flags);
4674 dwc2_hsotg_core_init_disconnected(hsotg, false);
4675 /* Enable ACG feature in device mode,if supported */
4676 dwc2_enable_acg(hsotg);
4677 dwc2_hsotg_core_connect(hsotg);
4679 dwc2_hsotg_core_disconnect(hsotg);
4680 dwc2_hsotg_disconnect(hsotg);
4684 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4685 spin_unlock_irqrestore(&hsotg->lock, flags);
4690 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4692 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4693 unsigned long flags;
4695 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4696 spin_lock_irqsave(&hsotg->lock, flags);
4699 * If controller is in partial power down state, it must exit from
4700 * that state before being initialized / de-initialized
4702 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4704 * No need to check the return value as
4705 * registers are not being restored.
4707 dwc2_exit_partial_power_down(hsotg, 0, false);
4710 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4712 dwc2_hsotg_core_init_disconnected(hsotg, false);
4713 if (hsotg->enabled) {
4714 /* Enable ACG feature in device mode,if supported */
4715 dwc2_enable_acg(hsotg);
4716 dwc2_hsotg_core_connect(hsotg);
4719 dwc2_hsotg_core_disconnect(hsotg);
4720 dwc2_hsotg_disconnect(hsotg);
4723 spin_unlock_irqrestore(&hsotg->lock, flags);
4728 * dwc2_hsotg_vbus_draw - report bMaxPower field
4729 * @gadget: The usb gadget state
4730 * @mA: Amount of current
4732 * Report how much power the device may consume to the phy.
4734 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4736 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4738 if (IS_ERR_OR_NULL(hsotg->uphy))
4740 return usb_phy_set_power(hsotg->uphy, mA);
4743 static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
4745 struct dwc2_hsotg *hsotg = to_hsotg(g);
4746 unsigned long flags;
4748 spin_lock_irqsave(&hsotg->lock, flags);
4750 case USB_SPEED_HIGH:
4751 hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
4753 case USB_SPEED_FULL:
4754 hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
4757 hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
4760 dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
4762 spin_unlock_irqrestore(&hsotg->lock, flags);
4765 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4766 .get_frame = dwc2_hsotg_gadget_getframe,
4767 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4768 .udc_start = dwc2_hsotg_udc_start,
4769 .udc_stop = dwc2_hsotg_udc_stop,
4770 .pullup = dwc2_hsotg_pullup,
4771 .udc_set_speed = dwc2_gadget_set_speed,
4772 .vbus_session = dwc2_hsotg_vbus_session,
4773 .vbus_draw = dwc2_hsotg_vbus_draw,
4777 * dwc2_hsotg_initep - initialise a single endpoint
4778 * @hsotg: The device state.
4779 * @hs_ep: The endpoint to be initialised.
4780 * @epnum: The endpoint number
4781 * @dir_in: True if direction is in.
4783 * Initialise the given endpoint (as part of the probe and device state
4784 * creation) to give to the gadget driver. Setup the endpoint name, any
4785 * direction information and other state that may be required.
4787 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4788 struct dwc2_hsotg_ep *hs_ep,
4801 hs_ep->dir_in = dir_in;
4802 hs_ep->index = epnum;
4804 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4806 INIT_LIST_HEAD(&hs_ep->queue);
4807 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4809 /* add to the list of endpoints known by the gadget driver */
4811 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4813 hs_ep->parent = hsotg;
4814 hs_ep->ep.name = hs_ep->name;
4816 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4817 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4819 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4820 epnum ? 1024 : EP0_MPS_LIMIT);
4821 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4824 hs_ep->ep.caps.type_control = true;
4826 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4827 hs_ep->ep.caps.type_iso = true;
4828 hs_ep->ep.caps.type_bulk = true;
4830 hs_ep->ep.caps.type_int = true;
4834 hs_ep->ep.caps.dir_in = true;
4836 hs_ep->ep.caps.dir_out = true;
4839 * if we're using dma, we need to set the next-endpoint pointer
4840 * to be something valid.
4843 if (using_dma(hsotg)) {
4844 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4847 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4849 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4854 * dwc2_hsotg_hw_cfg - read HW configuration registers
4855 * @hsotg: Programming view of the DWC_otg controller
4857 * Read the USB core HW configuration registers
4859 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4865 /* check hardware configuration */
4867 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4870 hsotg->num_of_eps++;
4872 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4873 sizeof(struct dwc2_hsotg_ep),
4875 if (!hsotg->eps_in[0])
4877 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4878 hsotg->eps_out[0] = hsotg->eps_in[0];
4880 cfg = hsotg->hw_params.dev_ep_dirs;
4881 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4883 /* Direction in or both */
4884 if (!(ep_type & 2)) {
4885 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4886 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4887 if (!hsotg->eps_in[i])
4890 /* Direction out or both */
4891 if (!(ep_type & 1)) {
4892 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4893 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4894 if (!hsotg->eps_out[i])
4899 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4900 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4902 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4904 hsotg->dedicated_fifos ? "dedicated" : "shared",
4910 * dwc2_hsotg_dump - dump state of the udc
4911 * @hsotg: Programming view of the DWC_otg controller
4914 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4917 struct device *dev = hsotg->dev;
4921 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4922 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4923 dwc2_readl(hsotg, DIEPMSK));
4925 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4926 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4928 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4929 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4931 /* show periodic fifo settings */
4933 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4934 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4935 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4936 val >> FIFOSIZE_DEPTH_SHIFT,
4937 val & FIFOSIZE_STARTADDR_MASK);
4940 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4942 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4943 dwc2_readl(hsotg, DIEPCTL(idx)),
4944 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4945 dwc2_readl(hsotg, DIEPDMA(idx)));
4947 val = dwc2_readl(hsotg, DOEPCTL(idx));
4949 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4950 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4951 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4952 dwc2_readl(hsotg, DOEPDMA(idx)));
4955 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4956 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4961 * dwc2_gadget_init - init function for gadget
4962 * @hsotg: Programming view of the DWC_otg controller
4965 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4967 struct device *dev = hsotg->dev;
4971 /* Dump fifo information */
4972 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4973 hsotg->params.g_np_tx_fifo_size);
4974 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4976 switch (hsotg->params.speed) {
4977 case DWC2_SPEED_PARAM_LOW:
4978 hsotg->gadget.max_speed = USB_SPEED_LOW;
4980 case DWC2_SPEED_PARAM_FULL:
4981 hsotg->gadget.max_speed = USB_SPEED_FULL;
4984 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4988 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4989 hsotg->gadget.name = dev_name(dev);
4990 hsotg->gadget.otg_caps = &hsotg->params.otg_caps;
4991 hsotg->remote_wakeup_allowed = 0;
4993 if (hsotg->params.lpm)
4994 hsotg->gadget.lpm_capable = true;
4996 if (hsotg->dr_mode == USB_DR_MODE_OTG)
4997 hsotg->gadget.is_otg = 1;
4998 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4999 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
5001 ret = dwc2_hsotg_hw_cfg(hsotg);
5003 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
5007 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
5008 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5009 if (!hsotg->ctrl_buff)
5012 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
5013 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5014 if (!hsotg->ep0_buff)
5017 if (using_desc_dma(hsotg)) {
5018 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
5023 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
5024 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
5026 dev_err(dev, "cannot claim IRQ for gadget\n");
5030 /* hsotg->num_of_eps holds number of EPs other than ep0 */
5032 if (hsotg->num_of_eps == 0) {
5033 dev_err(dev, "wrong number of EPs (zero)\n");
5037 /* setup endpoint information */
5039 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
5040 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
5042 /* allocate EP0 request */
5044 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
5046 if (!hsotg->ctrl_req) {
5047 dev_err(dev, "failed to allocate ctrl req\n");
5051 /* initialise the endpoints now the core has been initialised */
5052 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
5053 if (hsotg->eps_in[epnum])
5054 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
5056 if (hsotg->eps_out[epnum])
5057 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5061 dwc2_hsotg_dump(hsotg);
5067 * dwc2_hsotg_remove - remove function for hsotg driver
5068 * @hsotg: Programming view of the DWC_otg controller
5071 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5073 usb_del_gadget_udc(&hsotg->gadget);
5074 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5079 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5081 unsigned long flags;
5083 if (hsotg->lx_state != DWC2_L0)
5086 if (hsotg->driver) {
5089 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5090 hsotg->driver->driver.name);
5092 spin_lock_irqsave(&hsotg->lock, flags);
5094 dwc2_hsotg_core_disconnect(hsotg);
5095 dwc2_hsotg_disconnect(hsotg);
5096 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5097 spin_unlock_irqrestore(&hsotg->lock, flags);
5099 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
5100 if (hsotg->eps_in[ep])
5101 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5102 if (hsotg->eps_out[ep])
5103 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5110 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5112 unsigned long flags;
5114 if (hsotg->lx_state == DWC2_L2)
5117 if (hsotg->driver) {
5118 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5119 hsotg->driver->driver.name);
5121 spin_lock_irqsave(&hsotg->lock, flags);
5122 dwc2_hsotg_core_init_disconnected(hsotg, false);
5123 if (hsotg->enabled) {
5124 /* Enable ACG feature in device mode,if supported */
5125 dwc2_enable_acg(hsotg);
5126 dwc2_hsotg_core_connect(hsotg);
5128 spin_unlock_irqrestore(&hsotg->lock, flags);
5135 * dwc2_backup_device_registers() - Backup controller device registers.
5136 * When suspending usb bus, registers needs to be backuped
5137 * if controller power is disabled once suspended.
5139 * @hsotg: Programming view of the DWC_otg controller
5141 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5143 struct dwc2_dregs_backup *dr;
5146 dev_dbg(hsotg->dev, "%s\n", __func__);
5148 /* Backup dev regs */
5149 dr = &hsotg->dr_backup;
5151 dr->dcfg = dwc2_readl(hsotg, DCFG);
5152 dr->dctl = dwc2_readl(hsotg, DCTL);
5153 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5154 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5155 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5157 for (i = 0; i < hsotg->num_of_eps; i++) {
5159 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5161 /* Ensure DATA PID is correctly configured */
5162 if (dr->diepctl[i] & DXEPCTL_DPID)
5163 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5165 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5167 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5168 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5170 /* Backup OUT EPs */
5171 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5173 /* Ensure DATA PID is correctly configured */
5174 if (dr->doepctl[i] & DXEPCTL_DPID)
5175 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5177 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5179 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5180 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5181 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5188 * dwc2_restore_device_registers() - Restore controller device registers.
5189 * When resuming usb bus, device registers needs to be restored
5190 * if controller power were disabled.
5192 * @hsotg: Programming view of the DWC_otg controller
5193 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5195 * Return: 0 if successful, negative error code otherwise
5197 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5199 struct dwc2_dregs_backup *dr;
5202 dev_dbg(hsotg->dev, "%s\n", __func__);
5204 /* Restore dev regs */
5205 dr = &hsotg->dr_backup;
5207 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5214 dwc2_writel(hsotg, dr->dctl, DCTL);
5216 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5217 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5218 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5220 for (i = 0; i < hsotg->num_of_eps; i++) {
5221 /* Restore IN EPs */
5222 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5223 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5224 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5225 /** WA for enabled EPx's IN in DDMA mode. On entering to
5226 * hibernation wrong value read and saved from DIEPDMAx,
5227 * as result BNA interrupt asserted on hibernation exit
5228 * by restoring from saved area.
5230 if (using_desc_dma(hsotg) &&
5231 (dr->diepctl[i] & DXEPCTL_EPENA))
5232 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5233 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5234 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5235 /* Restore OUT EPs */
5236 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5237 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5238 * hibernation wrong value read and saved from DOEPDMAx,
5239 * as result BNA interrupt asserted on hibernation exit
5240 * by restoring from saved area.
5242 if (using_desc_dma(hsotg) &&
5243 (dr->doepctl[i] & DXEPCTL_EPENA))
5244 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5245 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5246 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5253 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5255 * @hsotg: Programming view of DWC_otg controller
5258 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5262 if (!hsotg->params.lpm)
5265 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5266 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5267 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5268 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5269 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5270 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5271 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5272 dwc2_writel(hsotg, val, GLPMCFG);
5273 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5275 /* Unmask WKUP_ALERT Interrupt */
5276 if (hsotg->params.service_interval)
5277 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5281 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5283 * @hsotg: Programming view of DWC_otg controller
5286 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5290 val |= GREFCLK_REF_CLK_MODE;
5291 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5292 val |= hsotg->params.sof_cnt_wkup_alert <<
5293 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5295 dwc2_writel(hsotg, val, GREFCLK);
5296 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5300 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5302 * @hsotg: Programming view of the DWC_otg controller
5304 * Return non-zero if failed to enter to hibernation.
5306 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5311 /* Change to L2(suspend) state */
5312 hsotg->lx_state = DWC2_L2;
5313 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5314 ret = dwc2_backup_global_registers(hsotg);
5316 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5320 ret = dwc2_backup_device_registers(hsotg);
5322 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5327 gpwrdn = GPWRDN_PWRDNRSTN;
5328 gpwrdn |= GPWRDN_PMUACTV;
5329 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5332 /* Set flag to indicate that we are in hibernation */
5333 hsotg->hibernated = 1;
5335 /* Enable interrupts from wake up logic */
5336 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5337 gpwrdn |= GPWRDN_PMUINTSEL;
5338 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5341 /* Unmask device mode interrupts in GPWRDN */
5342 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5343 gpwrdn |= GPWRDN_RST_DET_MSK;
5344 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5345 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5346 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5349 /* Enable Power Down Clamp */
5350 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5351 gpwrdn |= GPWRDN_PWRDNCLMP;
5352 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5355 /* Switch off VDD */
5356 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5357 gpwrdn |= GPWRDN_PWRDNSWTCH;
5358 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5361 /* Save gpwrdn register for further usage if stschng interrupt */
5362 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5363 dev_dbg(hsotg->dev, "Hibernation completed\n");
5369 * dwc2_gadget_exit_hibernation()
5370 * This function is for exiting from Device mode hibernation by host initiated
5371 * resume/reset and device initiated remote-wakeup.
5373 * @hsotg: Programming view of the DWC_otg controller
5374 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5375 * @reset: indicates whether resume is initiated by Reset.
5377 * Return non-zero if failed to exit from hibernation.
5379 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5380 int rem_wakeup, int reset)
5386 struct dwc2_gregs_backup *gr;
5387 struct dwc2_dregs_backup *dr;
5389 gr = &hsotg->gr_backup;
5390 dr = &hsotg->dr_backup;
5392 if (!hsotg->hibernated) {
5393 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5397 "%s: called with rem_wakeup = %d reset = %d\n",
5398 __func__, rem_wakeup, reset);
5400 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5403 /* Clear all pending interupts */
5404 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5407 /* De-assert Restore */
5408 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5409 gpwrdn &= ~GPWRDN_RESTORE;
5410 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5414 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5415 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5416 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5419 /* Restore GUSBCFG, DCFG and DCTL */
5420 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5421 dwc2_writel(hsotg, dr->dcfg, DCFG);
5422 dwc2_writel(hsotg, dr->dctl, DCTL);
5424 /* On USB Reset, reset device address to zero */
5426 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5428 /* De-assert Wakeup Logic */
5429 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5430 gpwrdn &= ~GPWRDN_PMUACTV;
5431 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5435 /* Start Remote Wakeup Signaling */
5436 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5439 /* Set Device programming done bit */
5440 dctl = dwc2_readl(hsotg, DCTL);
5441 dctl |= DCTL_PWRONPRGDONE;
5442 dwc2_writel(hsotg, dctl, DCTL);
5444 /* Wait for interrupts which must be cleared */
5446 /* Clear all pending interupts */
5447 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5449 /* Restore global registers */
5450 ret = dwc2_restore_global_registers(hsotg);
5452 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5457 /* Restore device registers */
5458 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5460 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5467 dctl = dwc2_readl(hsotg, DCTL);
5468 dctl &= ~DCTL_RMTWKUPSIG;
5469 dwc2_writel(hsotg, dctl, DCTL);
5472 hsotg->hibernated = 0;
5473 hsotg->lx_state = DWC2_L0;
5474 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5480 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5483 * @hsotg: Programming view of the DWC_otg controller
5485 * Return: non-zero if failed to enter device partial power down.
5487 * This function is for entering device mode partial power down.
5489 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5494 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5496 /* Backup all registers */
5497 ret = dwc2_backup_global_registers(hsotg);
5499 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5504 ret = dwc2_backup_device_registers(hsotg);
5506 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5512 * Clear any pending interrupts since dwc2 will not be able to
5513 * clear them after entering partial_power_down.
5515 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5517 /* Put the controller in low power state */
5518 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5520 pcgcctl |= PCGCTL_PWRCLMP;
5521 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5524 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5525 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5528 pcgcctl |= PCGCTL_STOPPCLK;
5529 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5531 /* Set in_ppd flag to 1 as here core enters suspend. */
5533 hsotg->lx_state = DWC2_L2;
5535 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5541 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5544 * @hsotg: Programming view of the DWC_otg controller
5545 * @restore: indicates whether need to restore the registers or not.
5547 * Return: non-zero if failed to exit device partial power down.
5549 * This function is for exiting from device mode partial power down.
5551 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5556 struct dwc2_dregs_backup *dr;
5559 dr = &hsotg->dr_backup;
5561 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5563 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5564 pcgcctl &= ~PCGCTL_STOPPCLK;
5565 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5567 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5568 pcgcctl &= ~PCGCTL_PWRCLMP;
5569 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5571 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5572 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5573 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5577 ret = dwc2_restore_global_registers(hsotg);
5579 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5584 dwc2_writel(hsotg, dr->dcfg, DCFG);
5586 ret = dwc2_restore_device_registers(hsotg, 0);
5588 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5594 /* Set the Power-On Programming done bit */
5595 dctl = dwc2_readl(hsotg, DCTL);
5596 dctl |= DCTL_PWRONPRGDONE;
5597 dwc2_writel(hsotg, dctl, DCTL);
5599 /* Set in_ppd flag to 0 as here core exits from suspend. */
5601 hsotg->lx_state = DWC2_L0;
5603 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5608 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5610 * @hsotg: Programming view of the DWC_otg controller
5612 * Return: non-zero if failed to enter device partial power down.
5614 * This function is for entering device mode clock gating.
5616 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5620 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5622 /* Set the Phy Clock bit as suspend is received. */
5623 pcgctl = dwc2_readl(hsotg, PCGCTL);
5624 pcgctl |= PCGCTL_STOPPCLK;
5625 dwc2_writel(hsotg, pcgctl, PCGCTL);
5628 /* Set the Gate hclk as suspend is received. */
5629 pcgctl = dwc2_readl(hsotg, PCGCTL);
5630 pcgctl |= PCGCTL_GATEHCLK;
5631 dwc2_writel(hsotg, pcgctl, PCGCTL);
5634 hsotg->lx_state = DWC2_L2;
5635 hsotg->bus_suspended = true;
5639 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5641 * @hsotg: Programming view of the DWC_otg controller
5642 * @rem_wakeup: indicates whether remote wake up is enabled.
5644 * This function is for exiting from device mode clock gating.
5646 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5651 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5653 /* Clear the Gate hclk. */
5654 pcgctl = dwc2_readl(hsotg, PCGCTL);
5655 pcgctl &= ~PCGCTL_GATEHCLK;
5656 dwc2_writel(hsotg, pcgctl, PCGCTL);
5659 /* Phy Clock bit. */
5660 pcgctl = dwc2_readl(hsotg, PCGCTL);
5661 pcgctl &= ~PCGCTL_STOPPCLK;
5662 dwc2_writel(hsotg, pcgctl, PCGCTL);
5666 /* Set Remote Wakeup Signaling */
5667 dctl = dwc2_readl(hsotg, DCTL);
5668 dctl |= DCTL_RMTWKUPSIG;
5669 dwc2_writel(hsotg, dctl, DCTL);
5672 /* Change to L0 state */
5673 call_gadget(hsotg, resume);
5674 hsotg->lx_state = DWC2_L0;
5675 hsotg->bus_suspended = false;