1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
11 * S3C USB2.0 High-speed / OtG driver
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/mutex.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
24 #include <linux/slab.h>
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
28 #include <linux/usb/phy.h>
29 #include <linux/usb/composite.h>
35 /* conversion functions */
36 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
38 return container_of(req, struct dwc2_hsotg_req, req);
41 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
43 return container_of(ep, struct dwc2_hsotg_ep, ep);
46 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
48 return container_of(gadget, struct dwc2_hsotg, gadget);
51 static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
53 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset);
56 static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val)
58 dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset);
61 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
62 u32 ep_index, u32 dir_in)
65 return hsotg->eps_in[ep_index];
67 return hsotg->eps_out[ep_index];
70 /* forward declaration of functions */
71 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
74 * using_dma - return the DMA status of the driver.
75 * @hsotg: The driver state.
77 * Return true if we're using DMA.
79 * Currently, we have the DMA support code worked into everywhere
80 * that needs it, but the AMBA DMA implementation in the hardware can
81 * only DMA from 32bit aligned addresses. This means that gadgets such
82 * as the CDC Ethernet cannot work as they often pass packets which are
85 * Unfortunately the choice to use DMA or not is global to the controller
86 * and seems to be only settable when the controller is being put through
87 * a core reset. This means we either need to fix the gadgets to take
88 * account of DMA alignment, or add bounce buffers (yuerk).
90 * g_using_dma is set depending on dts flag.
92 static inline bool using_dma(struct dwc2_hsotg *hsotg)
94 return hsotg->params.g_dma;
98 * using_desc_dma - return the descriptor DMA status of the driver.
99 * @hsotg: The driver state.
101 * Return true if we're using descriptor DMA.
103 static inline bool using_desc_dma(struct dwc2_hsotg *hsotg)
105 return hsotg->params.g_dma_desc;
109 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
110 * @hs_ep: The endpoint
112 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
113 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
115 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
117 struct dwc2_hsotg *hsotg = hs_ep->parent;
118 u16 limit = DSTS_SOFFN_LIMIT;
120 if (hsotg->gadget.speed != USB_SPEED_HIGH)
123 hs_ep->target_frame += hs_ep->interval;
124 if (hs_ep->target_frame > limit) {
125 hs_ep->frame_overrun = true;
126 hs_ep->target_frame &= limit;
128 hs_ep->frame_overrun = false;
133 * dwc2_gadget_dec_frame_num_by_one - Decrements the targeted frame number
135 * @hs_ep: The endpoint.
137 * This function used in service interval based scheduling flow to calculate
138 * descriptor frame number filed value. For service interval mode frame
139 * number in descriptor should point to last (u)frame in the interval.
142 static inline void dwc2_gadget_dec_frame_num_by_one(struct dwc2_hsotg_ep *hs_ep)
144 struct dwc2_hsotg *hsotg = hs_ep->parent;
145 u16 limit = DSTS_SOFFN_LIMIT;
147 if (hsotg->gadget.speed != USB_SPEED_HIGH)
150 if (hs_ep->target_frame)
151 hs_ep->target_frame -= 1;
153 hs_ep->target_frame = limit;
157 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
158 * @hsotg: The device state
159 * @ints: A bitmask of the interrupts to enable
161 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
163 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
166 new_gsintmsk = gsintmsk | ints;
168 if (new_gsintmsk != gsintmsk) {
169 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
170 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
175 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
176 * @hsotg: The device state
177 * @ints: A bitmask of the interrupts to enable
179 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
181 u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
184 new_gsintmsk = gsintmsk & ~ints;
186 if (new_gsintmsk != gsintmsk)
187 dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
191 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
192 * @hsotg: The device state
193 * @ep: The endpoint index
194 * @dir_in: True if direction is in.
195 * @en: The enable value, true to enable
197 * Set or clear the mask for an individual endpoint's interrupt
200 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
201 unsigned int ep, unsigned int dir_in,
211 local_irq_save(flags);
212 daint = dwc2_readl(hsotg, DAINTMSK);
217 dwc2_writel(hsotg, daint, DAINTMSK);
218 local_irq_restore(flags);
222 * dwc2_hsotg_tx_fifo_count - return count of TX FIFOs in device mode
224 * @hsotg: Programming view of the DWC_otg controller
226 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
228 if (hsotg->hw_params.en_multiple_tx_fifo)
229 /* In dedicated FIFO mode we need count of IN EPs */
230 return hsotg->hw_params.num_dev_in_eps;
232 /* In shared FIFO mode we need count of Periodic IN EPs */
233 return hsotg->hw_params.num_dev_perio_in_ep;
237 * dwc2_hsotg_tx_fifo_total_depth - return total FIFO depth available for
238 * device mode TX FIFOs
240 * @hsotg: Programming view of the DWC_otg controller
242 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
248 np_tx_fifo_size = min_t(u32, hsotg->hw_params.dev_nperio_tx_fifo_size,
249 hsotg->params.g_np_tx_fifo_size);
251 /* Get Endpoint Info Control block size in DWORDs. */
252 tx_addr_max = hsotg->hw_params.total_fifo_size;
254 addr = hsotg->params.g_rx_fifo_size + np_tx_fifo_size;
255 if (tx_addr_max <= addr)
258 return tx_addr_max - addr;
262 * dwc2_gadget_wkup_alert_handler - Handler for WKUP_ALERT interrupt
264 * @hsotg: Programming view of the DWC_otg controller
267 static void dwc2_gadget_wkup_alert_handler(struct dwc2_hsotg *hsotg)
272 gintsts2 = dwc2_readl(hsotg, GINTSTS2);
273 gintmsk2 = dwc2_readl(hsotg, GINTMSK2);
274 gintsts2 &= gintmsk2;
276 if (gintsts2 & GINTSTS2_WKUP_ALERT_INT) {
277 dev_dbg(hsotg->dev, "%s: Wkup_Alert_Int\n", __func__);
278 dwc2_set_bit(hsotg, GINTSTS2, GINTSTS2_WKUP_ALERT_INT);
279 dwc2_set_bit(hsotg, DCTL, DCTL_RMTWKUPSIG);
284 * dwc2_hsotg_tx_fifo_average_depth - returns average depth of device mode
287 * @hsotg: Programming view of the DWC_otg controller
289 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
294 tx_fifo_depth = dwc2_hsotg_tx_fifo_total_depth(hsotg);
296 tx_fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
299 return tx_fifo_depth;
301 return tx_fifo_depth / tx_fifo_count;
305 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
306 * @hsotg: The device instance.
308 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
315 u32 *txfsz = hsotg->params.g_tx_fifo_size;
317 /* Reset fifo map if not correctly cleared during previous session */
318 WARN_ON(hsotg->fifo_map);
321 /* set RX/NPTX FIFO sizes */
322 dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
323 dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size <<
324 FIFOSIZE_STARTADDR_SHIFT) |
325 (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
329 * arange all the rest of the TX FIFOs, as some versions of this
330 * block have overlapping default addresses. This also ensures
331 * that if the settings have been changed, then they are set to
335 /* start at the end of the GNPTXFSIZ, rounded up */
336 addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
339 * Configure fifos sizes from provided configuration and assign
340 * them to endpoints dynamically according to maxpacket size value of
343 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
347 val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
348 WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
349 "insufficient fifo memory");
352 dwc2_writel(hsotg, val, DPTXFSIZN(ep));
353 val = dwc2_readl(hsotg, DPTXFSIZN(ep));
356 dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size |
357 addr << GDFIFOCFG_EPINFOBASE_SHIFT,
360 * according to p428 of the design guide, we need to ensure that
361 * all fifos are flushed before continuing
364 dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
365 GRSTCTL_RXFFLSH, GRSTCTL);
367 /* wait until the fifos are both flushed */
370 val = dwc2_readl(hsotg, GRSTCTL);
372 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
375 if (--timeout == 0) {
377 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
385 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
389 * dwc2_hsotg_ep_alloc_request - allocate USB rerequest structure
390 * @ep: USB endpoint to allocate request for.
391 * @flags: Allocation flags
393 * Allocate a new USB request structure appropriate for the specified endpoint
395 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
398 struct dwc2_hsotg_req *req;
400 req = kzalloc(sizeof(*req), flags);
404 INIT_LIST_HEAD(&req->queue);
410 * is_ep_periodic - return true if the endpoint is in periodic mode.
411 * @hs_ep: The endpoint to query.
413 * Returns true if the endpoint is in periodic mode, meaning it is being
414 * used for an Interrupt or ISO transfer.
416 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
418 return hs_ep->periodic;
422 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
423 * @hsotg: The device state.
424 * @hs_ep: The endpoint for the request
425 * @hs_req: The request being processed.
427 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
428 * of a request to ensure the buffer is ready for access by the caller.
430 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
431 struct dwc2_hsotg_ep *hs_ep,
432 struct dwc2_hsotg_req *hs_req)
434 struct usb_request *req = &hs_req->req;
436 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->map_dir);
440 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
441 * for Control endpoint
442 * @hsotg: The device state.
444 * This function will allocate 4 descriptor chains for EP 0: 2 for
445 * Setup stage, per one for IN and OUT data/status transactions.
447 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg *hsotg)
449 hsotg->setup_desc[0] =
450 dmam_alloc_coherent(hsotg->dev,
451 sizeof(struct dwc2_dma_desc),
452 &hsotg->setup_desc_dma[0],
454 if (!hsotg->setup_desc[0])
457 hsotg->setup_desc[1] =
458 dmam_alloc_coherent(hsotg->dev,
459 sizeof(struct dwc2_dma_desc),
460 &hsotg->setup_desc_dma[1],
462 if (!hsotg->setup_desc[1])
465 hsotg->ctrl_in_desc =
466 dmam_alloc_coherent(hsotg->dev,
467 sizeof(struct dwc2_dma_desc),
468 &hsotg->ctrl_in_desc_dma,
470 if (!hsotg->ctrl_in_desc)
473 hsotg->ctrl_out_desc =
474 dmam_alloc_coherent(hsotg->dev,
475 sizeof(struct dwc2_dma_desc),
476 &hsotg->ctrl_out_desc_dma,
478 if (!hsotg->ctrl_out_desc)
488 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
489 * @hsotg: The controller state.
490 * @hs_ep: The endpoint we're going to write for.
491 * @hs_req: The request to write data for.
493 * This is called when the TxFIFO has some space in it to hold a new
494 * transmission and we have something to give it. The actual setup of
495 * the data size is done elsewhere, so all we have to do is to actually
498 * The return value is zero if there is more space (or nothing was done)
499 * otherwise -ENOSPC is returned if the FIFO space was used up.
501 * This routine is only needed for PIO
503 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
504 struct dwc2_hsotg_ep *hs_ep,
505 struct dwc2_hsotg_req *hs_req)
507 bool periodic = is_ep_periodic(hs_ep);
508 u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS);
509 int buf_pos = hs_req->req.actual;
510 int to_write = hs_ep->size_loaded;
516 to_write -= (buf_pos - hs_ep->last_load);
518 /* if there's nothing to write, get out early */
522 if (periodic && !hsotg->dedicated_fifos) {
523 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
528 * work out how much data was loaded so we can calculate
529 * how much data is left in the fifo.
532 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
535 * if shared fifo, we cannot write anything until the
536 * previous data has been completely sent.
538 if (hs_ep->fifo_load != 0) {
539 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
543 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
545 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
547 /* how much of the data has moved */
548 size_done = hs_ep->size_loaded - size_left;
550 /* how much data is left in the fifo */
551 can_write = hs_ep->fifo_load - size_done;
552 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
553 __func__, can_write);
555 can_write = hs_ep->fifo_size - can_write;
556 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
557 __func__, can_write);
559 if (can_write <= 0) {
560 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
563 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
564 can_write = dwc2_readl(hsotg,
565 DTXFSTS(hs_ep->fifo_index));
570 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
572 "%s: no queue slots available (0x%08x)\n",
575 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
579 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
580 can_write *= 4; /* fifo size is in 32bit quantities. */
583 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
585 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
586 __func__, gnptxsts, can_write, to_write, max_transfer);
589 * limit to 512 bytes of data, it seems at least on the non-periodic
590 * FIFO, requests of >512 cause the endpoint to get stuck with a
591 * fragment of the end of the transfer in it.
593 if (can_write > 512 && !periodic)
597 * limit the write to one max-packet size worth of data, but allow
598 * the transfer to return that it did not run out of fifo space
601 if (to_write > max_transfer) {
602 to_write = max_transfer;
604 /* it's needed only when we do not use dedicated fifos */
605 if (!hsotg->dedicated_fifos)
606 dwc2_hsotg_en_gsint(hsotg,
607 periodic ? GINTSTS_PTXFEMP :
611 /* see if we can write data */
613 if (to_write > can_write) {
614 to_write = can_write;
615 pkt_round = to_write % max_transfer;
618 * Round the write down to an
619 * exact number of packets.
621 * Note, we do not currently check to see if we can ever
622 * write a full packet or not to the FIFO.
626 to_write -= pkt_round;
629 * enable correct FIFO interrupt to alert us when there
633 /* it's needed only when we do not use dedicated fifos */
634 if (!hsotg->dedicated_fifos)
635 dwc2_hsotg_en_gsint(hsotg,
636 periodic ? GINTSTS_PTXFEMP :
640 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
641 to_write, hs_req->req.length, can_write, buf_pos);
646 hs_req->req.actual = buf_pos + to_write;
647 hs_ep->total_data += to_write;
650 hs_ep->fifo_load += to_write;
652 to_write = DIV_ROUND_UP(to_write, 4);
653 data = hs_req->req.buf + buf_pos;
655 dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write);
657 return (to_write >= can_write) ? -ENOSPC : 0;
661 * get_ep_limit - get the maximum data legnth for this endpoint
662 * @hs_ep: The endpoint
664 * Return the maximum data that can be queued in one go on a given endpoint
665 * so that transfers that are too long can be split.
667 static unsigned int get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
669 int index = hs_ep->index;
670 unsigned int maxsize;
674 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
675 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
679 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
684 /* we made the constant loading easier above by using +1 */
689 * constrain by packet count if maxpkts*pktsize is greater
690 * than the length register size.
693 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
694 maxsize = maxpkt * hs_ep->ep.maxpacket;
700 * dwc2_hsotg_read_frameno - read current frame number
701 * @hsotg: The device instance
703 * Return the current frame number
705 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
709 dsts = dwc2_readl(hsotg, DSTS);
710 dsts &= DSTS_SOFFN_MASK;
711 dsts >>= DSTS_SOFFN_SHIFT;
717 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
718 * DMA descriptor chain prepared for specific endpoint
719 * @hs_ep: The endpoint
721 * Return the maximum data that can be queued in one go on a given endpoint
722 * depending on its descriptor chain capacity so that transfers that
723 * are too long can be split.
725 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep *hs_ep)
727 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
728 int is_isoc = hs_ep->isochronous;
729 unsigned int maxsize;
730 u32 mps = hs_ep->ep.maxpacket;
731 int dir_in = hs_ep->dir_in;
734 maxsize = (hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_LIMIT :
735 DEV_DMA_ISOC_RX_NBYTES_LIMIT) *
736 MAX_DMA_DESC_NUM_HS_ISOC;
738 maxsize = DEV_DMA_NBYTES_LIMIT * MAX_DMA_DESC_NUM_GENERIC;
740 /* Interrupt OUT EP with mps not multiple of 4 */
742 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
743 maxsize = mps * MAX_DMA_DESC_NUM_GENERIC;
749 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
750 * @hs_ep: The endpoint
751 * @mask: RX/TX bytes mask to be defined
753 * Returns maximum data payload for one descriptor after analyzing endpoint
755 * DMA descriptor transfer bytes limit depends on EP type:
757 * Isochronous - descriptor rx/tx bytes bitfield limit,
758 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
759 * have concatenations from various descriptors within one packet.
760 * Interrupt OUT - if mps not multiple of 4 then a single packet corresponds
761 * to a single descriptor.
763 * Selects corresponding mask for RX/TX bytes as well.
765 static u32 dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep *hs_ep, u32 *mask)
767 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
768 u32 mps = hs_ep->ep.maxpacket;
769 int dir_in = hs_ep->dir_in;
772 if (!hs_ep->index && !dir_in) {
774 *mask = DEV_DMA_NBYTES_MASK;
775 } else if (hs_ep->isochronous) {
777 desc_size = DEV_DMA_ISOC_TX_NBYTES_LIMIT;
778 *mask = DEV_DMA_ISOC_TX_NBYTES_MASK;
780 desc_size = DEV_DMA_ISOC_RX_NBYTES_LIMIT;
781 *mask = DEV_DMA_ISOC_RX_NBYTES_MASK;
784 desc_size = DEV_DMA_NBYTES_LIMIT;
785 *mask = DEV_DMA_NBYTES_MASK;
787 /* Round down desc_size to be mps multiple */
788 desc_size -= desc_size % mps;
791 /* Interrupt OUT EP with mps not multiple of 4 */
793 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4)) {
795 *mask = DEV_DMA_NBYTES_MASK;
801 static void dwc2_gadget_fill_nonisoc_xfer_ddma_one(struct dwc2_hsotg_ep *hs_ep,
802 struct dwc2_dma_desc **desc,
807 int dir_in = hs_ep->dir_in;
808 u32 mps = hs_ep->ep.maxpacket;
814 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
816 hs_ep->desc_count = (len / maxsize) +
817 ((len % maxsize) ? 1 : 0);
819 hs_ep->desc_count = 1;
821 for (i = 0; i < hs_ep->desc_count; ++i) {
823 (*desc)->status |= (DEV_DMA_BUFF_STS_HBUSY
824 << DEV_DMA_BUFF_STS_SHIFT);
827 if (!hs_ep->index && !dir_in)
828 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
831 maxsize << DEV_DMA_NBYTES_SHIFT & mask;
832 (*desc)->buf = dma_buff + offset;
838 (*desc)->status |= (DEV_DMA_L | DEV_DMA_IOC);
841 (*desc)->status |= (len % mps) ? DEV_DMA_SHORT :
842 ((hs_ep->send_zlp && true_last) ?
846 len << DEV_DMA_NBYTES_SHIFT & mask;
847 (*desc)->buf = dma_buff + offset;
850 (*desc)->status &= ~DEV_DMA_BUFF_STS_MASK;
851 (*desc)->status |= (DEV_DMA_BUFF_STS_HREADY
852 << DEV_DMA_BUFF_STS_SHIFT);
858 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
859 * @hs_ep: The endpoint
860 * @ureq: Request to transfer
861 * @offset: offset in bytes
862 * @len: Length of the transfer
864 * This function will iterate over descriptor chain and fill its entries
865 * with corresponding information based on transfer data.
867 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep *hs_ep,
871 struct usb_request *ureq = NULL;
872 struct dwc2_dma_desc *desc = hs_ep->desc_list;
873 struct scatterlist *sg;
878 ureq = &hs_ep->req->req;
880 /* non-DMA sg buffer */
881 if (!ureq || !ureq->num_sgs) {
882 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
883 dma_buff, len, true);
888 for_each_sg(ureq->sg, sg, ureq->num_sgs, i) {
889 dwc2_gadget_fill_nonisoc_xfer_ddma_one(hs_ep, &desc,
890 sg_dma_address(sg) + sg->offset, sg_dma_len(sg),
892 desc_count += hs_ep->desc_count;
895 hs_ep->desc_count = desc_count;
899 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
900 * @hs_ep: The isochronous endpoint.
901 * @dma_buff: usb requests dma buffer.
902 * @len: usb request transfer length.
904 * Fills next free descriptor with the data of the arrived usb request,
905 * frame info, sets Last and IOC bits increments next_desc. If filled
906 * descriptor is not the first one, removes L bit from the previous descriptor
909 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep *hs_ep,
910 dma_addr_t dma_buff, unsigned int len)
912 struct dwc2_dma_desc *desc;
913 struct dwc2_hsotg *hsotg = hs_ep->parent;
918 dwc2_gadget_get_desc_params(hs_ep, &mask);
920 index = hs_ep->next_desc;
921 desc = &hs_ep->desc_list[index];
923 /* Check if descriptor chain full */
924 if ((desc->status >> DEV_DMA_BUFF_STS_SHIFT) ==
925 DEV_DMA_BUFF_STS_HREADY) {
926 dev_dbg(hsotg->dev, "%s: desc chain full\n", __func__);
930 /* Clear L bit of previous desc if more than one entries in the chain */
931 if (hs_ep->next_desc)
932 hs_ep->desc_list[index - 1].status &= ~DEV_DMA_L;
934 dev_dbg(hsotg->dev, "%s: Filling ep %d, dir %s isoc desc # %d\n",
935 __func__, hs_ep->index, hs_ep->dir_in ? "in" : "out", index);
938 desc->status |= (DEV_DMA_BUFF_STS_HBUSY << DEV_DMA_BUFF_STS_SHIFT);
940 desc->buf = dma_buff;
941 desc->status |= (DEV_DMA_L | DEV_DMA_IOC |
942 ((len << DEV_DMA_NBYTES_SHIFT) & mask));
946 pid = DIV_ROUND_UP(len, hs_ep->ep.maxpacket);
949 desc->status |= ((pid << DEV_DMA_ISOC_PID_SHIFT) &
950 DEV_DMA_ISOC_PID_MASK) |
951 ((len % hs_ep->ep.maxpacket) ?
953 ((hs_ep->target_frame <<
954 DEV_DMA_ISOC_FRNUM_SHIFT) &
955 DEV_DMA_ISOC_FRNUM_MASK);
958 desc->status &= ~DEV_DMA_BUFF_STS_MASK;
959 desc->status |= (DEV_DMA_BUFF_STS_HREADY << DEV_DMA_BUFF_STS_SHIFT);
961 /* Increment frame number by interval for IN */
963 dwc2_gadget_incr_frame_num(hs_ep);
965 /* Update index of last configured entry in the chain */
967 if (hs_ep->next_desc >= MAX_DMA_DESC_NUM_HS_ISOC)
968 hs_ep->next_desc = 0;
974 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
975 * @hs_ep: The isochronous endpoint.
977 * Prepare descriptor chain for isochronous endpoints. Afterwards
978 * write DMA address to HW and enable the endpoint.
980 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep)
982 struct dwc2_hsotg *hsotg = hs_ep->parent;
983 struct dwc2_hsotg_req *hs_req, *treq;
984 int index = hs_ep->index;
990 struct dwc2_dma_desc *desc;
992 if (list_empty(&hs_ep->queue)) {
993 hs_ep->target_frame = TARGET_FRAME_INITIAL;
994 dev_dbg(hsotg->dev, "%s: No requests in queue\n", __func__);
998 /* Initialize descriptor chain by Host Busy status */
999 for (i = 0; i < MAX_DMA_DESC_NUM_HS_ISOC; i++) {
1000 desc = &hs_ep->desc_list[i];
1002 desc->status |= (DEV_DMA_BUFF_STS_HBUSY
1003 << DEV_DMA_BUFF_STS_SHIFT);
1006 hs_ep->next_desc = 0;
1007 list_for_each_entry_safe(hs_req, treq, &hs_ep->queue, queue) {
1008 dma_addr_t dma_addr = hs_req->req.dma;
1010 if (hs_req->req.num_sgs) {
1011 WARN_ON(hs_req->req.num_sgs > 1);
1012 dma_addr = sg_dma_address(hs_req->req.sg);
1014 ret = dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1015 hs_req->req.length);
1020 hs_ep->compl_desc = 0;
1021 depctl = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1022 dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index);
1024 /* write descriptor chain address to control register */
1025 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1027 ctrl = dwc2_readl(hsotg, depctl);
1028 ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK;
1029 dwc2_writel(hsotg, ctrl, depctl);
1032 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep);
1033 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1034 struct dwc2_hsotg_ep *hs_ep,
1035 struct dwc2_hsotg_req *hs_req,
1039 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
1040 * @hsotg: The controller state.
1041 * @hs_ep: The endpoint to process a request for
1042 * @hs_req: The request to start.
1043 * @continuing: True if we are doing more for the current request.
1045 * Start the given request running by setting the endpoint registers
1046 * appropriately, and writing any data to the FIFOs.
1048 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
1049 struct dwc2_hsotg_ep *hs_ep,
1050 struct dwc2_hsotg_req *hs_req,
1053 struct usb_request *ureq = &hs_req->req;
1054 int index = hs_ep->index;
1055 int dir_in = hs_ep->dir_in;
1060 unsigned int length;
1061 unsigned int packets;
1062 unsigned int maxreq;
1063 unsigned int dma_reg;
1066 if (hs_ep->req && !continuing) {
1067 dev_err(hsotg->dev, "%s: active request\n", __func__);
1070 } else if (hs_ep->req != hs_req && continuing) {
1072 "%s: continue different req\n", __func__);
1078 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
1079 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
1080 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1082 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
1083 __func__, dwc2_readl(hsotg, epctrl_reg), index,
1084 hs_ep->dir_in ? "in" : "out");
1086 /* If endpoint is stalled, we will restart request later */
1087 ctrl = dwc2_readl(hsotg, epctrl_reg);
1089 if (index && ctrl & DXEPCTL_STALL) {
1090 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
1094 length = ureq->length - ureq->actual;
1095 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
1096 ureq->length, ureq->actual);
1098 if (!using_desc_dma(hsotg))
1099 maxreq = get_ep_limit(hs_ep);
1101 maxreq = dwc2_gadget_get_chain_limit(hs_ep);
1103 if (length > maxreq) {
1104 int round = maxreq % hs_ep->ep.maxpacket;
1106 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
1107 __func__, length, maxreq, round);
1109 /* round down to multiple of packets */
1117 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
1119 packets = 1; /* send one packet if length is zero. */
1121 if (dir_in && index != 0)
1122 if (hs_ep->isochronous)
1123 epsize = DXEPTSIZ_MC(packets);
1125 epsize = DXEPTSIZ_MC(1);
1130 * zero length packet should be programmed on its own and should not
1131 * be counted in DIEPTSIZ.PktCnt with other packets.
1133 if (dir_in && ureq->zero && !continuing) {
1134 /* Test if zlp is actually required. */
1135 if ((ureq->length >= hs_ep->ep.maxpacket) &&
1136 !(ureq->length % hs_ep->ep.maxpacket))
1137 hs_ep->send_zlp = 1;
1140 epsize |= DXEPTSIZ_PKTCNT(packets);
1141 epsize |= DXEPTSIZ_XFERSIZE(length);
1143 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
1144 __func__, packets, length, ureq->length, epsize, epsize_reg);
1146 /* store the request as the current one we're doing */
1147 hs_ep->req = hs_req;
1149 if (using_desc_dma(hsotg)) {
1151 u32 mps = hs_ep->ep.maxpacket;
1153 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
1157 else if (length % mps)
1158 length += (mps - (length % mps));
1162 offset = ureq->actual;
1164 /* Fill DDMA chain entries */
1165 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, ureq->dma + offset,
1168 /* write descriptor chain address to control register */
1169 dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg);
1171 dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n",
1172 __func__, (u32)hs_ep->desc_list_dma, dma_reg);
1174 /* write size / packets */
1175 dwc2_writel(hsotg, epsize, epsize_reg);
1177 if (using_dma(hsotg) && !continuing && (length != 0)) {
1179 * write DMA address to control register, buffer
1180 * already synced by dwc2_hsotg_ep_queue().
1183 dwc2_writel(hsotg, ureq->dma, dma_reg);
1185 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
1186 __func__, &ureq->dma, dma_reg);
1190 if (hs_ep->isochronous) {
1191 if (!dwc2_gadget_target_frame_elapsed(hs_ep)) {
1192 if (hs_ep->interval == 1) {
1193 if (hs_ep->target_frame & 0x1)
1194 ctrl |= DXEPCTL_SETODDFR;
1196 ctrl |= DXEPCTL_SETEVENFR;
1198 ctrl |= DXEPCTL_CNAK;
1200 hs_req->req.frame_number = hs_ep->target_frame;
1201 hs_req->req.actual = 0;
1202 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
1207 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1209 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
1211 /* For Setup request do not clear NAK */
1212 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
1213 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1215 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
1216 dwc2_writel(hsotg, ctrl, epctrl_reg);
1219 * set these, it seems that DMA support increments past the end
1220 * of the packet buffer so we need to calculate the length from
1223 hs_ep->size_loaded = length;
1224 hs_ep->last_load = ureq->actual;
1226 if (dir_in && !using_dma(hsotg)) {
1227 /* set these anyway, we may need them for non-periodic in */
1228 hs_ep->fifo_load = 0;
1230 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1234 * Note, trying to clear the NAK here causes problems with transmit
1235 * on the S3C6400 ending up with the TXFIFO becoming full.
1238 /* check ep is enabled */
1239 if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA))
1241 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1242 index, dwc2_readl(hsotg, epctrl_reg));
1244 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
1245 __func__, dwc2_readl(hsotg, epctrl_reg));
1247 /* enable ep interrupts */
1248 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
1252 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1253 * @hsotg: The device state.
1254 * @hs_ep: The endpoint the request is on.
1255 * @req: The request being processed.
1257 * We've been asked to queue a request, so ensure that the memory buffer
1258 * is correctly setup for DMA. If we've been passed an extant DMA address
1259 * then ensure the buffer has been synced to memory. If our buffer has no
1260 * DMA memory, then we map the memory and mark our request to allow us to
1261 * cleanup on completion.
1263 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
1264 struct dwc2_hsotg_ep *hs_ep,
1265 struct usb_request *req)
1269 hs_ep->map_dir = hs_ep->dir_in;
1270 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
1277 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
1278 __func__, req->buf, req->length);
1283 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
1284 struct dwc2_hsotg_ep *hs_ep,
1285 struct dwc2_hsotg_req *hs_req)
1287 void *req_buf = hs_req->req.buf;
1289 /* If dma is not being used or buffer is aligned */
1290 if (!using_dma(hsotg) || !((long)req_buf & 3))
1293 WARN_ON(hs_req->saved_req_buf);
1295 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
1296 hs_ep->ep.name, req_buf, hs_req->req.length);
1298 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
1299 if (!hs_req->req.buf) {
1300 hs_req->req.buf = req_buf;
1302 "%s: unable to allocate memory for bounce buffer\n",
1307 /* Save actual buffer */
1308 hs_req->saved_req_buf = req_buf;
1311 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
1316 dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
1317 struct dwc2_hsotg_ep *hs_ep,
1318 struct dwc2_hsotg_req *hs_req)
1320 /* If dma is not being used or buffer was aligned */
1321 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
1324 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
1325 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
1327 /* Copy data from bounce buffer on successful out transfer */
1328 if (!hs_ep->dir_in && !hs_req->req.status)
1329 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
1330 hs_req->req.actual);
1332 /* Free bounce buffer */
1333 kfree(hs_req->req.buf);
1335 hs_req->req.buf = hs_req->saved_req_buf;
1336 hs_req->saved_req_buf = NULL;
1340 * dwc2_gadget_target_frame_elapsed - Checks target frame
1341 * @hs_ep: The driver endpoint to check
1343 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1344 * corresponding transfer.
1346 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep *hs_ep)
1348 struct dwc2_hsotg *hsotg = hs_ep->parent;
1349 u32 target_frame = hs_ep->target_frame;
1350 u32 current_frame = hsotg->frame_number;
1351 bool frame_overrun = hs_ep->frame_overrun;
1352 u16 limit = DSTS_SOFFN_LIMIT;
1354 if (hsotg->gadget.speed != USB_SPEED_HIGH)
1357 if (!frame_overrun && current_frame >= target_frame)
1360 if (frame_overrun && current_frame >= target_frame &&
1361 ((current_frame - target_frame) < limit / 2))
1368 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1369 * @hsotg: The driver state
1370 * @hs_ep: the ep descriptor chain is for
1372 * Called to update EP0 structure's pointers depend on stage of
1375 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg *hsotg,
1376 struct dwc2_hsotg_ep *hs_ep)
1378 switch (hsotg->ep0_state) {
1379 case DWC2_EP0_SETUP:
1380 case DWC2_EP0_STATUS_OUT:
1381 hs_ep->desc_list = hsotg->setup_desc[0];
1382 hs_ep->desc_list_dma = hsotg->setup_desc_dma[0];
1384 case DWC2_EP0_DATA_IN:
1385 case DWC2_EP0_STATUS_IN:
1386 hs_ep->desc_list = hsotg->ctrl_in_desc;
1387 hs_ep->desc_list_dma = hsotg->ctrl_in_desc_dma;
1389 case DWC2_EP0_DATA_OUT:
1390 hs_ep->desc_list = hsotg->ctrl_out_desc;
1391 hs_ep->desc_list_dma = hsotg->ctrl_out_desc_dma;
1394 dev_err(hsotg->dev, "invalid EP 0 state in queue %d\n",
1402 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
1405 struct dwc2_hsotg_req *hs_req = our_req(req);
1406 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1407 struct dwc2_hsotg *hs = hs_ep->parent;
1414 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1415 ep->name, req, req->length, req->buf, req->no_interrupt,
1416 req->zero, req->short_not_ok);
1418 if (hs->lx_state == DWC2_L1) {
1419 dwc2_wakeup_from_lpm_l1(hs, true);
1422 /* Prevent new request submission when controller is suspended */
1423 if (hs->lx_state != DWC2_L0) {
1424 dev_dbg(hs->dev, "%s: submit request only in active state\n",
1429 /* initialise status of the request */
1430 INIT_LIST_HEAD(&hs_req->queue);
1432 req->status = -EINPROGRESS;
1434 /* Don't queue ISOC request if length greater than mps*mc */
1435 if (hs_ep->isochronous &&
1436 req->length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
1437 dev_err(hs->dev, "req length > maxpacket*mc\n");
1441 /* In DDMA mode for ISOC's don't queue request if length greater
1442 * than descriptor limits.
1444 if (using_desc_dma(hs) && hs_ep->isochronous) {
1445 maxsize = dwc2_gadget_get_desc_params(hs_ep, &mask);
1446 if (hs_ep->dir_in && req->length > maxsize) {
1447 dev_err(hs->dev, "wrong length %d (maxsize=%d)\n",
1448 req->length, maxsize);
1452 if (!hs_ep->dir_in && req->length > hs_ep->ep.maxpacket) {
1453 dev_err(hs->dev, "ISOC OUT: wrong length %d (mps=%d)\n",
1454 req->length, hs_ep->ep.maxpacket);
1459 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
1463 /* if we're using DMA, sync the buffers as necessary */
1464 if (using_dma(hs)) {
1465 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
1469 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1470 if (using_desc_dma(hs) && !hs_ep->index) {
1471 ret = dwc2_gadget_set_ep0_desc_chain(hs, hs_ep);
1476 first = list_empty(&hs_ep->queue);
1477 list_add_tail(&hs_req->queue, &hs_ep->queue);
1480 * Handle DDMA isochronous transfers separately - just add new entry
1481 * to the descriptor chain.
1482 * Transfer will be started once SW gets either one of NAK or
1483 * OutTknEpDis interrupts.
1485 if (using_desc_dma(hs) && hs_ep->isochronous) {
1486 if (hs_ep->target_frame != TARGET_FRAME_INITIAL) {
1487 dma_addr_t dma_addr = hs_req->req.dma;
1489 if (hs_req->req.num_sgs) {
1490 WARN_ON(hs_req->req.num_sgs > 1);
1491 dma_addr = sg_dma_address(hs_req->req.sg);
1493 dwc2_gadget_fill_isoc_desc(hs_ep, dma_addr,
1494 hs_req->req.length);
1499 /* Change EP direction if status phase request is after data out */
1500 if (!hs_ep->index && !req->length && !hs_ep->dir_in &&
1501 hs->ep0_state == DWC2_EP0_DATA_OUT)
1505 if (!hs_ep->isochronous) {
1506 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1510 /* Update current frame number value. */
1511 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1512 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
1513 dwc2_gadget_incr_frame_num(hs_ep);
1514 /* Update current frame number value once more as it
1517 hs->frame_number = dwc2_hsotg_read_frameno(hs);
1520 if (hs_ep->target_frame != TARGET_FRAME_INITIAL)
1521 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
1526 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
1529 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1530 struct dwc2_hsotg *hs = hs_ep->parent;
1531 unsigned long flags;
1534 spin_lock_irqsave(&hs->lock, flags);
1535 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
1536 spin_unlock_irqrestore(&hs->lock, flags);
1541 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
1542 struct usb_request *req)
1544 struct dwc2_hsotg_req *hs_req = our_req(req);
1550 * dwc2_hsotg_complete_oursetup - setup completion callback
1551 * @ep: The endpoint the request was on.
1552 * @req: The request completed.
1554 * Called on completion of any requests the driver itself
1555 * submitted that need cleaning up.
1557 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
1558 struct usb_request *req)
1560 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1561 struct dwc2_hsotg *hsotg = hs_ep->parent;
1563 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
1565 dwc2_hsotg_ep_free_request(ep, req);
1569 * ep_from_windex - convert control wIndex value to endpoint
1570 * @hsotg: The driver state.
1571 * @windex: The control request wIndex field (in host order).
1573 * Convert the given wIndex into a pointer to an driver endpoint
1574 * structure, or return NULL if it is not a valid endpoint.
1576 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
1579 int dir = (windex & USB_DIR_IN) ? 1 : 0;
1580 int idx = windex & 0x7F;
1582 if (windex >= 0x100)
1585 if (idx > hsotg->num_of_eps)
1588 return index_to_ep(hsotg, idx, dir);
1592 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1593 * @hsotg: The driver state.
1594 * @testmode: requested usb test mode
1595 * Enable usb Test Mode requested by the Host.
1597 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
1599 int dctl = dwc2_readl(hsotg, DCTL);
1601 dctl &= ~DCTL_TSTCTL_MASK;
1605 case USB_TEST_SE0_NAK:
1606 case USB_TEST_PACKET:
1607 case USB_TEST_FORCE_ENABLE:
1608 dctl |= testmode << DCTL_TSTCTL_SHIFT;
1613 dwc2_writel(hsotg, dctl, DCTL);
1618 * dwc2_hsotg_send_reply - send reply to control request
1619 * @hsotg: The device state
1621 * @buff: Buffer for request
1622 * @length: Length of reply.
1624 * Create a request and queue it on the given endpoint. This is useful as
1625 * an internal method of sending replies to certain control requests, etc.
1627 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
1628 struct dwc2_hsotg_ep *ep,
1632 struct usb_request *req;
1635 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1637 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1638 hsotg->ep0_reply = req;
1640 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1644 req->buf = hsotg->ep0_buff;
1645 req->length = length;
1647 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1651 req->complete = dwc2_hsotg_complete_oursetup;
1654 memcpy(req->buf, buff, length);
1656 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1658 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1666 * dwc2_hsotg_process_req_status - process request GET_STATUS
1667 * @hsotg: The device state
1668 * @ctrl: USB control request
1670 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
1671 struct usb_ctrlrequest *ctrl)
1673 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1674 struct dwc2_hsotg_ep *ep;
1679 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1682 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1686 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1687 case USB_RECIP_DEVICE:
1688 status = hsotg->gadget.is_selfpowered <<
1689 USB_DEVICE_SELF_POWERED;
1690 status |= hsotg->remote_wakeup_allowed <<
1691 USB_DEVICE_REMOTE_WAKEUP;
1692 reply = cpu_to_le16(status);
1695 case USB_RECIP_INTERFACE:
1696 /* currently, the data result should be zero */
1697 reply = cpu_to_le16(0);
1700 case USB_RECIP_ENDPOINT:
1701 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1705 reply = cpu_to_le16(ep->halted ? 1 : 0);
1712 if (le16_to_cpu(ctrl->wLength) != 2)
1715 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1717 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1724 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1727 * get_ep_head - return the first request on the endpoint
1728 * @hs_ep: The controller endpoint to get
1730 * Get the first request on the endpoint.
1732 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1734 return list_first_entry_or_null(&hs_ep->queue, struct dwc2_hsotg_req,
1739 * dwc2_gadget_start_next_request - Starts next request from ep queue
1740 * @hs_ep: Endpoint structure
1742 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1743 * in its handler. Hence we need to unmask it here to be able to do
1744 * resynchronization.
1746 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1748 struct dwc2_hsotg *hsotg = hs_ep->parent;
1749 int dir_in = hs_ep->dir_in;
1750 struct dwc2_hsotg_req *hs_req;
1752 if (!list_empty(&hs_ep->queue)) {
1753 hs_req = get_ep_head(hs_ep);
1754 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1757 if (!hs_ep->isochronous)
1761 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1764 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1770 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1771 * @hsotg: The device state
1772 * @ctrl: USB control request
1774 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1775 struct usb_ctrlrequest *ctrl)
1777 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1778 struct dwc2_hsotg_req *hs_req;
1779 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1780 struct dwc2_hsotg_ep *ep;
1787 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1788 __func__, set ? "SET" : "CLEAR");
1790 wValue = le16_to_cpu(ctrl->wValue);
1791 wIndex = le16_to_cpu(ctrl->wIndex);
1792 recip = ctrl->bRequestType & USB_RECIP_MASK;
1795 case USB_RECIP_DEVICE:
1797 case USB_DEVICE_REMOTE_WAKEUP:
1799 hsotg->remote_wakeup_allowed = 1;
1801 hsotg->remote_wakeup_allowed = 0;
1804 case USB_DEVICE_TEST_MODE:
1805 if ((wIndex & 0xff) != 0)
1810 hsotg->test_mode = wIndex >> 8;
1816 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1819 "%s: failed to send reply\n", __func__);
1824 case USB_RECIP_ENDPOINT:
1825 ep = ep_from_windex(hsotg, wIndex);
1827 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1833 case USB_ENDPOINT_HALT:
1834 halted = ep->halted;
1837 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1839 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1842 "%s: failed to send reply\n", __func__);
1847 * we have to complete all requests for ep if it was
1848 * halted, and the halt was cleared by CLEAR_FEATURE
1851 if (!set && halted) {
1853 * If we have request in progress,
1859 list_del_init(&hs_req->queue);
1860 if (hs_req->req.complete) {
1861 spin_unlock(&hsotg->lock);
1862 usb_gadget_giveback_request(
1863 &ep->ep, &hs_req->req);
1864 spin_lock(&hsotg->lock);
1868 /* If we have pending request, then start it */
1870 dwc2_gadget_start_next_request(ep);
1885 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1888 * dwc2_hsotg_stall_ep0 - stall ep0
1889 * @hsotg: The device state
1891 * Set stall for ep0 as response for setup request.
1893 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1895 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1899 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1900 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1903 * DxEPCTL_Stall will be cleared by EP once it has
1904 * taken effect, so no need to clear later.
1907 ctrl = dwc2_readl(hsotg, reg);
1908 ctrl |= DXEPCTL_STALL;
1909 ctrl |= DXEPCTL_CNAK;
1910 dwc2_writel(hsotg, ctrl, reg);
1913 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1914 ctrl, reg, dwc2_readl(hsotg, reg));
1917 * complete won't be called, so we enqueue
1918 * setup request here
1920 dwc2_hsotg_enqueue_setup(hsotg);
1924 * dwc2_hsotg_process_control - process a control request
1925 * @hsotg: The device state
1926 * @ctrl: The control request received
1928 * The controller has received the SETUP phase of a control request, and
1929 * needs to work out what to do next (and whether to pass it on to the
1932 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1933 struct usb_ctrlrequest *ctrl)
1935 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1940 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1941 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1942 ctrl->wIndex, ctrl->wLength);
1944 if (ctrl->wLength == 0) {
1946 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1947 } else if (ctrl->bRequestType & USB_DIR_IN) {
1949 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1952 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1955 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1956 switch (ctrl->bRequest) {
1957 case USB_REQ_SET_ADDRESS:
1958 hsotg->connected = 1;
1959 dcfg = dwc2_readl(hsotg, DCFG);
1960 dcfg &= ~DCFG_DEVADDR_MASK;
1961 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1962 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1963 dwc2_writel(hsotg, dcfg, DCFG);
1965 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1967 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1970 case USB_REQ_GET_STATUS:
1971 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1974 case USB_REQ_CLEAR_FEATURE:
1975 case USB_REQ_SET_FEATURE:
1976 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1981 /* as a fallback, try delivering it to the driver to deal with */
1983 if (ret == 0 && hsotg->driver) {
1984 spin_unlock(&hsotg->lock);
1985 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1986 spin_lock(&hsotg->lock);
1988 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1991 hsotg->delayed_status = false;
1992 if (ret == USB_GADGET_DELAYED_STATUS)
1993 hsotg->delayed_status = true;
1996 * the request is either unhandlable, or is not formatted correctly
1997 * so respond with a STALL for the status stage to indicate failure.
2001 dwc2_hsotg_stall_ep0(hsotg);
2005 * dwc2_hsotg_complete_setup - completion of a setup transfer
2006 * @ep: The endpoint the request was on.
2007 * @req: The request completed.
2009 * Called on completion of any requests the driver itself submitted for
2012 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
2013 struct usb_request *req)
2015 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2016 struct dwc2_hsotg *hsotg = hs_ep->parent;
2018 if (req->status < 0) {
2019 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
2023 spin_lock(&hsotg->lock);
2024 if (req->actual == 0)
2025 dwc2_hsotg_enqueue_setup(hsotg);
2027 dwc2_hsotg_process_control(hsotg, req->buf);
2028 spin_unlock(&hsotg->lock);
2032 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
2033 * @hsotg: The device state.
2035 * Enqueue a request on EP0 if necessary to received any SETUP packets
2036 * received from the host.
2038 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
2040 struct usb_request *req = hsotg->ctrl_req;
2041 struct dwc2_hsotg_req *hs_req = our_req(req);
2044 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
2048 req->buf = hsotg->ctrl_buff;
2049 req->complete = dwc2_hsotg_complete_setup;
2051 if (!list_empty(&hs_req->queue)) {
2052 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
2056 hsotg->eps_out[0]->dir_in = 0;
2057 hsotg->eps_out[0]->send_zlp = 0;
2058 hsotg->ep0_state = DWC2_EP0_SETUP;
2060 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
2062 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
2064 * Don't think there's much we can do other than watch the
2070 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
2071 struct dwc2_hsotg_ep *hs_ep)
2074 u8 index = hs_ep->index;
2075 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
2076 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
2079 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
2082 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
2084 if (using_desc_dma(hsotg)) {
2085 /* Not specific buffer needed for ep0 ZLP */
2086 dma_addr_t dma = hs_ep->desc_list_dma;
2089 dwc2_gadget_set_ep0_desc_chain(hsotg, hs_ep);
2091 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0);
2093 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2094 DXEPTSIZ_XFERSIZE(0),
2098 ctrl = dwc2_readl(hsotg, epctl_reg);
2099 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
2100 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
2101 ctrl |= DXEPCTL_USBACTEP;
2102 dwc2_writel(hsotg, ctrl, epctl_reg);
2106 * dwc2_hsotg_complete_request - complete a request given to us
2107 * @hsotg: The device state.
2108 * @hs_ep: The endpoint the request was on.
2109 * @hs_req: The request to complete.
2110 * @result: The result code (0 => Ok, otherwise errno)
2112 * The given request has finished, so call the necessary completion
2113 * if it has one and then look to see if we can start a new request
2116 * Note, expects the ep to already be locked as appropriate.
2118 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
2119 struct dwc2_hsotg_ep *hs_ep,
2120 struct dwc2_hsotg_req *hs_req,
2124 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
2128 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
2129 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
2132 * only replace the status if we've not already set an error
2133 * from a previous transaction
2136 if (hs_req->req.status == -EINPROGRESS)
2137 hs_req->req.status = result;
2139 if (using_dma(hsotg))
2140 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
2142 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
2145 list_del_init(&hs_req->queue);
2148 * call the complete request with the locks off, just in case the
2149 * request tries to queue more work for this endpoint.
2152 if (hs_req->req.complete) {
2153 spin_unlock(&hsotg->lock);
2154 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
2155 spin_lock(&hsotg->lock);
2158 /* In DDMA don't need to proceed to starting of next ISOC request */
2159 if (using_desc_dma(hsotg) && hs_ep->isochronous)
2163 * Look to see if there is anything else to do. Note, the completion
2164 * of the previous request may have caused a new request to be started
2165 * so be careful when doing this.
2168 if (!hs_ep->req && result >= 0)
2169 dwc2_gadget_start_next_request(hs_ep);
2173 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
2174 * @hs_ep: The endpoint the request was on.
2176 * Get first request from the ep queue, determine descriptor on which complete
2177 * happened. SW discovers which descriptor currently in use by HW, adjusts
2178 * dma_address and calculates index of completed descriptor based on the value
2179 * of DEPDMA register. Update actual length of request, giveback to gadget.
2181 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep *hs_ep)
2183 struct dwc2_hsotg *hsotg = hs_ep->parent;
2184 struct dwc2_hsotg_req *hs_req;
2185 struct usb_request *ureq;
2189 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2191 /* Process only descriptors with buffer status set to DMA done */
2192 while ((desc_sts & DEV_DMA_BUFF_STS_MASK) >>
2193 DEV_DMA_BUFF_STS_SHIFT == DEV_DMA_BUFF_STS_DMADONE) {
2195 hs_req = get_ep_head(hs_ep);
2197 dev_warn(hsotg->dev, "%s: ISOC EP queue empty\n", __func__);
2200 ureq = &hs_req->req;
2202 /* Check completion status */
2203 if ((desc_sts & DEV_DMA_STS_MASK) >> DEV_DMA_STS_SHIFT ==
2205 mask = hs_ep->dir_in ? DEV_DMA_ISOC_TX_NBYTES_MASK :
2206 DEV_DMA_ISOC_RX_NBYTES_MASK;
2207 ureq->actual = ureq->length - ((desc_sts & mask) >>
2208 DEV_DMA_ISOC_NBYTES_SHIFT);
2210 /* Adjust actual len for ISOC Out if len is
2213 if (!hs_ep->dir_in && ureq->length & 0x3)
2214 ureq->actual += 4 - (ureq->length & 0x3);
2216 /* Set actual frame number for completed transfers */
2217 ureq->frame_number =
2218 (desc_sts & DEV_DMA_ISOC_FRNUM_MASK) >>
2219 DEV_DMA_ISOC_FRNUM_SHIFT;
2222 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2224 hs_ep->compl_desc++;
2225 if (hs_ep->compl_desc > (MAX_DMA_DESC_NUM_HS_ISOC - 1))
2226 hs_ep->compl_desc = 0;
2227 desc_sts = hs_ep->desc_list[hs_ep->compl_desc].status;
2232 * dwc2_gadget_handle_isoc_bna - handle BNA interrupt for ISOC.
2233 * @hs_ep: The isochronous endpoint.
2235 * If EP ISOC OUT then need to flush RX FIFO to remove source of BNA
2236 * interrupt. Reset target frame and next_desc to allow to start
2237 * ISOC's on NAK interrupt for IN direction or on OUTTKNEPDIS
2238 * interrupt for OUT direction.
2240 static void dwc2_gadget_handle_isoc_bna(struct dwc2_hsotg_ep *hs_ep)
2242 struct dwc2_hsotg *hsotg = hs_ep->parent;
2245 dwc2_flush_rx_fifo(hsotg);
2246 dwc2_hsotg_complete_request(hsotg, hs_ep, get_ep_head(hs_ep), 0);
2248 hs_ep->target_frame = TARGET_FRAME_INITIAL;
2249 hs_ep->next_desc = 0;
2250 hs_ep->compl_desc = 0;
2254 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2255 * @hsotg: The device state.
2256 * @ep_idx: The endpoint index for the data
2257 * @size: The size of data in the fifo, in bytes
2259 * The FIFO status shows there is data to read from the FIFO for a given
2260 * endpoint, so sort out whether we need to read the data into a request
2261 * that has been made for that endpoint.
2263 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
2265 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
2266 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2272 u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx));
2276 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2277 __func__, size, ep_idx, epctl);
2279 /* dump the data from the FIFO, we've nothing we can do */
2280 for (ptr = 0; ptr < size; ptr += 4)
2281 (void)dwc2_readl(hsotg, EPFIFO(ep_idx));
2287 read_ptr = hs_req->req.actual;
2288 max_req = hs_req->req.length - read_ptr;
2290 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
2291 __func__, to_read, max_req, read_ptr, hs_req->req.length);
2293 if (to_read > max_req) {
2295 * more data appeared than we where willing
2296 * to deal with in this request.
2299 /* currently we don't deal this */
2303 hs_ep->total_data += to_read;
2304 hs_req->req.actual += to_read;
2305 to_read = DIV_ROUND_UP(to_read, 4);
2308 * note, we might over-write the buffer end by 3 bytes depending on
2309 * alignment of the data.
2311 dwc2_readl_rep(hsotg, EPFIFO(ep_idx),
2312 hs_req->req.buf + read_ptr, to_read);
2316 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2317 * @hsotg: The device instance
2318 * @dir_in: If IN zlp
2320 * Generate a zero-length IN packet request for terminating a SETUP
2323 * Note, since we don't write any data to the TxFIFO, then it is
2324 * currently believed that we do not need to wait for any space in
2327 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
2329 /* eps_out[0] is used in both directions */
2330 hsotg->eps_out[0]->dir_in = dir_in;
2331 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
2333 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
2337 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2338 * @hs_ep - The endpoint on which transfer went
2340 * Iterate over endpoints descriptor chain and get info on bytes remained
2341 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2343 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep)
2345 const struct usb_endpoint_descriptor *ep_desc = hs_ep->ep.desc;
2346 struct dwc2_hsotg *hsotg = hs_ep->parent;
2347 unsigned int bytes_rem = 0;
2348 unsigned int bytes_rem_correction = 0;
2349 struct dwc2_dma_desc *desc = hs_ep->desc_list;
2352 u32 mps = hs_ep->ep.maxpacket;
2353 int dir_in = hs_ep->dir_in;
2358 /* Interrupt OUT EP with mps not multiple of 4 */
2360 if (usb_endpoint_xfer_int(ep_desc) && !dir_in && (mps % 4))
2361 bytes_rem_correction = 4 - (mps % 4);
2363 for (i = 0; i < hs_ep->desc_count; ++i) {
2364 status = desc->status;
2365 bytes_rem += status & DEV_DMA_NBYTES_MASK;
2366 bytes_rem -= bytes_rem_correction;
2368 if (status & DEV_DMA_STS_MASK)
2369 dev_err(hsotg->dev, "descriptor %d closed with %x\n",
2370 i, status & DEV_DMA_STS_MASK);
2372 if (status & DEV_DMA_L)
2382 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2383 * @hsotg: The device instance
2384 * @epnum: The endpoint received from
2386 * The RXFIFO has delivered an OutDone event, which means that the data
2387 * transfer for an OUT endpoint has been completed, either by a short
2388 * packet or by the finish of a transfer.
2390 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
2392 u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum));
2393 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
2394 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2395 struct usb_request *req = &hs_req->req;
2396 unsigned int size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2400 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
2404 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
2405 dev_dbg(hsotg->dev, "zlp packet received\n");
2406 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2407 dwc2_hsotg_enqueue_setup(hsotg);
2411 if (using_desc_dma(hsotg))
2412 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2414 if (using_dma(hsotg)) {
2415 unsigned int size_done;
2418 * Calculate the size of the transfer by checking how much
2419 * is left in the endpoint size register and then working it
2420 * out from the amount we loaded for the transfer.
2422 * We need to do this as DMA pointers are always 32bit aligned
2423 * so may overshoot/undershoot the transfer.
2426 size_done = hs_ep->size_loaded - size_left;
2427 size_done += hs_ep->last_load;
2429 req->actual = size_done;
2432 /* if there is more request to do, schedule new transfer */
2433 if (req->actual < req->length && size_left == 0) {
2434 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2438 if (req->actual < req->length && req->short_not_ok) {
2439 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
2440 __func__, req->actual, req->length);
2443 * todo - what should we return here? there's no one else
2444 * even bothering to check the status.
2448 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2449 if (!using_desc_dma(hsotg) && epnum == 0 &&
2450 hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
2451 /* Move to STATUS IN */
2452 if (!hsotg->delayed_status)
2453 dwc2_hsotg_ep0_zlp(hsotg, true);
2456 /* Set actual frame number for completed transfers */
2457 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2458 req->frame_number = hs_ep->target_frame;
2459 dwc2_gadget_incr_frame_num(hs_ep);
2462 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
2466 * dwc2_hsotg_handle_rx - RX FIFO has data
2467 * @hsotg: The device instance
2469 * The IRQ handler has detected that the RX FIFO has some data in it
2470 * that requires processing, so find out what is in there and do the
2473 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2474 * chunks, so if you have x packets received on an endpoint you'll get x
2475 * FIFO events delivered, each with a packet's worth of data in it.
2477 * When using DMA, we should not be processing events from the RXFIFO
2478 * as the actual data should be sent to the memory directly and we turn
2479 * on the completion interrupts to get notifications of transfer completion.
2481 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
2483 u32 grxstsr = dwc2_readl(hsotg, GRXSTSP);
2484 u32 epnum, status, size;
2486 WARN_ON(using_dma(hsotg));
2488 epnum = grxstsr & GRXSTS_EPNUM_MASK;
2489 status = grxstsr & GRXSTS_PKTSTS_MASK;
2491 size = grxstsr & GRXSTS_BYTECNT_MASK;
2492 size >>= GRXSTS_BYTECNT_SHIFT;
2494 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2495 __func__, grxstsr, size, epnum);
2497 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
2498 case GRXSTS_PKTSTS_GLOBALOUTNAK:
2499 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
2502 case GRXSTS_PKTSTS_OUTDONE:
2503 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
2504 dwc2_hsotg_read_frameno(hsotg));
2506 if (!using_dma(hsotg))
2507 dwc2_hsotg_handle_outdone(hsotg, epnum);
2510 case GRXSTS_PKTSTS_SETUPDONE:
2512 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2513 dwc2_hsotg_read_frameno(hsotg),
2514 dwc2_readl(hsotg, DOEPCTL(0)));
2516 * Call dwc2_hsotg_handle_outdone here if it was not called from
2517 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2518 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2520 if (hsotg->ep0_state == DWC2_EP0_SETUP)
2521 dwc2_hsotg_handle_outdone(hsotg, epnum);
2524 case GRXSTS_PKTSTS_OUTRX:
2525 dwc2_hsotg_rx_data(hsotg, epnum, size);
2528 case GRXSTS_PKTSTS_SETUPRX:
2530 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2531 dwc2_hsotg_read_frameno(hsotg),
2532 dwc2_readl(hsotg, DOEPCTL(0)));
2534 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
2536 dwc2_hsotg_rx_data(hsotg, epnum, size);
2540 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
2543 dwc2_hsotg_dump(hsotg);
2549 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2550 * @mps: The maximum packet size in bytes.
2552 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
2556 return D0EPCTL_MPS_64;
2558 return D0EPCTL_MPS_32;
2560 return D0EPCTL_MPS_16;
2562 return D0EPCTL_MPS_8;
2565 /* bad max packet size, warn and return invalid result */
2571 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2572 * @hsotg: The driver state.
2573 * @ep: The index number of the endpoint
2574 * @mps: The maximum packet size in bytes
2575 * @mc: The multicount value
2576 * @dir_in: True if direction is in.
2578 * Configure the maximum packet size for the given endpoint, updating
2579 * the hardware control registers to reflect this.
2581 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
2582 unsigned int ep, unsigned int mps,
2583 unsigned int mc, unsigned int dir_in)
2585 struct dwc2_hsotg_ep *hs_ep;
2588 hs_ep = index_to_ep(hsotg, ep, dir_in);
2593 u32 mps_bytes = mps;
2595 /* EP0 is a special case */
2596 mps = dwc2_hsotg_ep0_mps(mps_bytes);
2599 hs_ep->ep.maxpacket = mps_bytes;
2607 hs_ep->ep.maxpacket = mps;
2611 reg = dwc2_readl(hsotg, DIEPCTL(ep));
2612 reg &= ~DXEPCTL_MPS_MASK;
2614 dwc2_writel(hsotg, reg, DIEPCTL(ep));
2616 reg = dwc2_readl(hsotg, DOEPCTL(ep));
2617 reg &= ~DXEPCTL_MPS_MASK;
2619 dwc2_writel(hsotg, reg, DOEPCTL(ep));
2625 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
2629 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2630 * @hsotg: The driver state
2631 * @idx: The index for the endpoint (0..15)
2633 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
2635 dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
2638 /* wait until the fifo is flushed */
2639 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100))
2640 dev_warn(hsotg->dev, "%s: timeout flushing fifo GRSTCTL_TXFFLSH\n",
2645 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2646 * @hsotg: The driver state
2647 * @hs_ep: The driver endpoint to check.
2649 * Check to see if there is a request that has data to send, and if so
2650 * make an attempt to write data into the FIFO.
2652 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
2653 struct dwc2_hsotg_ep *hs_ep)
2655 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2657 if (!hs_ep->dir_in || !hs_req) {
2659 * if request is not enqueued, we disable interrupts
2660 * for endpoints, excepting ep0
2662 if (hs_ep->index != 0)
2663 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
2668 if (hs_req->req.actual < hs_req->req.length) {
2669 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
2671 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
2678 * dwc2_hsotg_complete_in - complete IN transfer
2679 * @hsotg: The device state.
2680 * @hs_ep: The endpoint that has just completed.
2682 * An IN transfer has been completed, update the transfer's state and then
2683 * call the relevant completion routines.
2685 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
2686 struct dwc2_hsotg_ep *hs_ep)
2688 struct dwc2_hsotg_req *hs_req = hs_ep->req;
2689 u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index));
2690 int size_left, size_done;
2693 dev_dbg(hsotg->dev, "XferCompl but no req\n");
2697 /* Finish ZLP handling for IN EP0 transactions */
2698 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
2699 dev_dbg(hsotg->dev, "zlp packet sent\n");
2702 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2703 * changed to IN. Change back to complete OUT transfer request
2707 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2708 if (hsotg->test_mode) {
2711 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
2713 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
2715 dwc2_hsotg_stall_ep0(hsotg);
2719 dwc2_hsotg_enqueue_setup(hsotg);
2724 * Calculate the size of the transfer by checking how much is left
2725 * in the endpoint size register and then working it out from
2726 * the amount we loaded for the transfer.
2728 * We do this even for DMA, as the transfer may have incremented
2729 * past the end of the buffer (DMA transfers are always 32bit
2732 if (using_desc_dma(hsotg)) {
2733 size_left = dwc2_gadget_get_xfersize_ddma(hs_ep);
2735 dev_err(hsotg->dev, "error parsing DDMA results %d\n",
2738 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
2741 size_done = hs_ep->size_loaded - size_left;
2742 size_done += hs_ep->last_load;
2744 if (hs_req->req.actual != size_done)
2745 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
2746 __func__, hs_req->req.actual, size_done);
2748 hs_req->req.actual = size_done;
2749 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
2750 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
2752 if (!size_left && hs_req->req.actual < hs_req->req.length) {
2753 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
2754 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
2758 /* Zlp for all endpoints in non DDMA, for ep0 only in DATA IN stage */
2759 if (hs_ep->send_zlp) {
2760 hs_ep->send_zlp = 0;
2761 if (!using_desc_dma(hsotg)) {
2762 dwc2_hsotg_program_zlp(hsotg, hs_ep);
2763 /* transfer will be completed on next complete interrupt */
2768 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
2769 /* Move to STATUS OUT */
2770 dwc2_hsotg_ep0_zlp(hsotg, false);
2774 /* Set actual frame number for completed transfers */
2775 if (!using_desc_dma(hsotg) && hs_ep->isochronous) {
2776 hs_req->req.frame_number = hs_ep->target_frame;
2777 dwc2_gadget_incr_frame_num(hs_ep);
2780 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
2784 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2785 * @hsotg: The device state.
2786 * @idx: Index of ep.
2787 * @dir_in: Endpoint direction 1-in 0-out.
2789 * Reads for endpoint with given index and direction, by masking
2790 * epint_reg with coresponding mask.
2792 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
2793 unsigned int idx, int dir_in)
2795 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
2796 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2801 mask = dwc2_readl(hsotg, epmsk_reg);
2802 diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK);
2803 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
2804 mask |= DXEPINT_SETUP_RCVD;
2806 ints = dwc2_readl(hsotg, epint_reg);
2812 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2813 * @hs_ep: The endpoint on which interrupt is asserted.
2815 * This interrupt indicates that the endpoint has been disabled per the
2816 * application's request.
2818 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2819 * in case of ISOC completes current request.
2821 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2822 * request starts it.
2824 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep)
2826 struct dwc2_hsotg *hsotg = hs_ep->parent;
2827 struct dwc2_hsotg_req *hs_req;
2828 unsigned char idx = hs_ep->index;
2829 int dir_in = hs_ep->dir_in;
2830 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2831 int dctl = dwc2_readl(hsotg, DCTL);
2833 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2836 int epctl = dwc2_readl(hsotg, epctl_reg);
2838 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2840 if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) {
2841 int dctl = dwc2_readl(hsotg, DCTL);
2843 dctl |= DCTL_CGNPINNAK;
2844 dwc2_writel(hsotg, dctl, DCTL);
2848 if (dctl & DCTL_GOUTNAKSTS) {
2849 dctl |= DCTL_CGOUTNAK;
2850 dwc2_writel(hsotg, dctl, DCTL);
2854 if (!hs_ep->isochronous)
2857 if (list_empty(&hs_ep->queue)) {
2858 dev_dbg(hsotg->dev, "%s: complete_ep 0x%p, ep->queue empty!\n",
2864 hs_req = get_ep_head(hs_ep);
2866 hs_req->req.frame_number = hs_ep->target_frame;
2867 hs_req->req.actual = 0;
2868 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req,
2871 dwc2_gadget_incr_frame_num(hs_ep);
2872 /* Update current frame number value. */
2873 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2874 } while (dwc2_gadget_target_frame_elapsed(hs_ep));
2878 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2879 * @ep: The endpoint on which interrupt is asserted.
2881 * This is starting point for ISOC-OUT transfer, synchronization done with
2882 * first out token received from host while corresponding EP is disabled.
2884 * Device does not know initial frame in which out token will come. For this
2885 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2886 * getting this interrupt SW starts calculation for next transfer frame.
2888 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2890 struct dwc2_hsotg *hsotg = ep->parent;
2891 struct dwc2_hsotg_req *hs_req;
2892 int dir_in = ep->dir_in;
2894 if (dir_in || !ep->isochronous)
2897 if (using_desc_dma(hsotg)) {
2898 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2899 /* Start first ISO Out */
2900 ep->target_frame = hsotg->frame_number;
2901 dwc2_gadget_start_isoc_ddma(ep);
2906 if (ep->target_frame == TARGET_FRAME_INITIAL) {
2909 ep->target_frame = hsotg->frame_number;
2910 if (ep->interval > 1) {
2911 ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index));
2912 if (ep->target_frame & 0x1)
2913 ctrl |= DXEPCTL_SETODDFR;
2915 ctrl |= DXEPCTL_SETEVENFR;
2917 dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index));
2921 while (dwc2_gadget_target_frame_elapsed(ep)) {
2922 hs_req = get_ep_head(ep);
2924 hs_req->req.frame_number = ep->target_frame;
2925 hs_req->req.actual = 0;
2926 dwc2_hsotg_complete_request(hsotg, ep, hs_req, -ENODATA);
2929 dwc2_gadget_incr_frame_num(ep);
2930 /* Update current frame number value. */
2931 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
2935 dwc2_gadget_start_next_request(ep);
2939 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
2940 struct dwc2_hsotg_ep *hs_ep);
2943 * dwc2_gadget_handle_nak - handle NAK interrupt
2944 * @hs_ep: The endpoint on which interrupt is asserted.
2946 * This is starting point for ISOC-IN transfer, synchronization done with
2947 * first IN token received from host while corresponding EP is disabled.
2949 * Device does not know when first one token will arrive from host. On first
2950 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2951 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2952 * sent in response to that as there was no data in FIFO. SW is basing on this
2953 * interrupt to obtain frame in which token has come and then based on the
2954 * interval calculates next frame for transfer.
2956 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2958 struct dwc2_hsotg *hsotg = hs_ep->parent;
2959 struct dwc2_hsotg_req *hs_req;
2960 int dir_in = hs_ep->dir_in;
2963 if (!dir_in || !hs_ep->isochronous)
2966 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2968 if (using_desc_dma(hsotg)) {
2969 hs_ep->target_frame = hsotg->frame_number;
2970 dwc2_gadget_incr_frame_num(hs_ep);
2972 /* In service interval mode target_frame must
2973 * be set to last (u)frame of the service interval.
2975 if (hsotg->params.service_interval) {
2976 /* Set target_frame to the first (u)frame of
2977 * the service interval
2979 hs_ep->target_frame &= ~hs_ep->interval + 1;
2981 /* Set target_frame to the last (u)frame of
2982 * the service interval
2984 dwc2_gadget_incr_frame_num(hs_ep);
2985 dwc2_gadget_dec_frame_num_by_one(hs_ep);
2988 dwc2_gadget_start_isoc_ddma(hs_ep);
2992 hs_ep->target_frame = hsotg->frame_number;
2993 if (hs_ep->interval > 1) {
2994 u32 ctrl = dwc2_readl(hsotg,
2995 DIEPCTL(hs_ep->index));
2996 if (hs_ep->target_frame & 0x1)
2997 ctrl |= DXEPCTL_SETODDFR;
2999 ctrl |= DXEPCTL_SETEVENFR;
3001 dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index));
3005 if (using_desc_dma(hsotg))
3008 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index));
3009 if (ctrl & DXEPCTL_EPENA)
3010 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
3012 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
3014 while (dwc2_gadget_target_frame_elapsed(hs_ep)) {
3015 hs_req = get_ep_head(hs_ep);
3017 hs_req->req.frame_number = hs_ep->target_frame;
3018 hs_req->req.actual = 0;
3019 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, -ENODATA);
3022 dwc2_gadget_incr_frame_num(hs_ep);
3023 /* Update current frame number value. */
3024 hsotg->frame_number = dwc2_hsotg_read_frameno(hsotg);
3028 dwc2_gadget_start_next_request(hs_ep);
3032 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
3033 * @hsotg: The driver state
3034 * @idx: The index for the endpoint (0..15)
3035 * @dir_in: Set if this is an IN endpoint
3037 * Process and clear any interrupt pending for an individual endpoint
3039 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
3042 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
3043 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
3044 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
3045 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
3048 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
3050 /* Clear endpoint interrupts */
3051 dwc2_writel(hsotg, ints, epint_reg);
3054 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
3055 __func__, idx, dir_in ? "in" : "out");
3059 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
3060 __func__, idx, dir_in ? "in" : "out", ints);
3062 /* Don't process XferCompl interrupt if it is a setup packet */
3063 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
3064 ints &= ~DXEPINT_XFERCOMPL;
3067 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
3068 * stage and xfercomplete was generated without SETUP phase done
3069 * interrupt. SW should parse received setup packet only after host's
3070 * exit from setup phase of control transfer.
3072 if (using_desc_dma(hsotg) && idx == 0 && !hs_ep->dir_in &&
3073 hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
3074 ints &= ~DXEPINT_XFERCOMPL;
3076 if (ints & DXEPINT_XFERCOMPL) {
3078 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
3079 __func__, dwc2_readl(hsotg, epctl_reg),
3080 dwc2_readl(hsotg, epsiz_reg));
3082 /* In DDMA handle isochronous requests separately */
3083 if (using_desc_dma(hsotg) && hs_ep->isochronous) {
3084 dwc2_gadget_complete_isoc_request_ddma(hs_ep);
3085 } else if (dir_in) {
3087 * We get OutDone from the FIFO, so we only
3088 * need to look at completing IN requests here
3089 * if operating slave mode
3091 if (!hs_ep->isochronous || !(ints & DXEPINT_NAKINTRPT))
3092 dwc2_hsotg_complete_in(hsotg, hs_ep);
3094 if (idx == 0 && !hs_ep->req)
3095 dwc2_hsotg_enqueue_setup(hsotg);
3096 } else if (using_dma(hsotg)) {
3098 * We're using DMA, we need to fire an OutDone here
3099 * as we ignore the RXFIFO.
3101 if (!hs_ep->isochronous || !(ints & DXEPINT_OUTTKNEPDIS))
3102 dwc2_hsotg_handle_outdone(hsotg, idx);
3106 if (ints & DXEPINT_EPDISBLD)
3107 dwc2_gadget_handle_ep_disabled(hs_ep);
3109 if (ints & DXEPINT_OUTTKNEPDIS)
3110 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
3112 if (ints & DXEPINT_NAKINTRPT)
3113 dwc2_gadget_handle_nak(hs_ep);
3115 if (ints & DXEPINT_AHBERR)
3116 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
3118 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
3119 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
3121 if (using_dma(hsotg) && idx == 0) {
3123 * this is the notification we've received a
3124 * setup packet. In non-DMA mode we'd get this
3125 * from the RXFIFO, instead we need to process
3132 dwc2_hsotg_handle_outdone(hsotg, 0);
3136 if (ints & DXEPINT_STSPHSERCVD) {
3137 dev_dbg(hsotg->dev, "%s: StsPhseRcvd\n", __func__);
3139 /* Safety check EP0 state when STSPHSERCVD asserted */
3140 if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
3141 /* Move to STATUS IN for DDMA */
3142 if (using_desc_dma(hsotg)) {
3143 if (!hsotg->delayed_status)
3144 dwc2_hsotg_ep0_zlp(hsotg, true);
3146 /* In case of 3 stage Control Write with delayed
3147 * status, when Status IN transfer started
3148 * before STSPHSERCVD asserted, NAKSTS bit not
3149 * cleared by CNAK in dwc2_hsotg_start_req()
3150 * function. Clear now NAKSTS to allow complete
3153 dwc2_set_bit(hsotg, DIEPCTL(0),
3160 if (ints & DXEPINT_BACK2BACKSETUP)
3161 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
3163 if (ints & DXEPINT_BNAINTR) {
3164 dev_dbg(hsotg->dev, "%s: BNA interrupt\n", __func__);
3165 if (hs_ep->isochronous)
3166 dwc2_gadget_handle_isoc_bna(hs_ep);
3169 if (dir_in && !hs_ep->isochronous) {
3170 /* not sure if this is important, but we'll clear it anyway */
3171 if (ints & DXEPINT_INTKNTXFEMP) {
3172 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
3176 /* this probably means something bad is happening */
3177 if (ints & DXEPINT_INTKNEPMIS) {
3178 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
3182 /* FIFO has space or is empty (see GAHBCFG) */
3183 if (hsotg->dedicated_fifos &&
3184 ints & DXEPINT_TXFEMP) {
3185 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
3187 if (!using_dma(hsotg))
3188 dwc2_hsotg_trytx(hsotg, hs_ep);
3194 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
3195 * @hsotg: The device state.
3197 * Handle updating the device settings after the enumeration phase has
3200 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
3202 u32 dsts = dwc2_readl(hsotg, DSTS);
3203 int ep0_mps = 0, ep_mps = 8;
3206 * This should signal the finish of the enumeration phase
3207 * of the USB handshaking, so we should now know what rate
3211 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
3214 * note, since we're limited by the size of transfer on EP0, and
3215 * it seems IN transfers must be a even number of packets we do
3216 * not advertise a 64byte MPS on EP0.
3219 /* catch both EnumSpd_FS and EnumSpd_FS48 */
3220 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
3221 case DSTS_ENUMSPD_FS:
3222 case DSTS_ENUMSPD_FS48:
3223 hsotg->gadget.speed = USB_SPEED_FULL;
3224 ep0_mps = EP0_MPS_LIMIT;
3228 case DSTS_ENUMSPD_HS:
3229 hsotg->gadget.speed = USB_SPEED_HIGH;
3230 ep0_mps = EP0_MPS_LIMIT;
3234 case DSTS_ENUMSPD_LS:
3235 hsotg->gadget.speed = USB_SPEED_LOW;
3239 * note, we don't actually support LS in this driver at the
3240 * moment, and the documentation seems to imply that it isn't
3241 * supported by the PHYs on some of the devices.
3245 dev_info(hsotg->dev, "new device is %s\n",
3246 usb_speed_string(hsotg->gadget.speed));
3249 * we should now know the maximum packet size for an
3250 * endpoint, so set the endpoints to a default value.
3255 /* Initialize ep0 for both in and out directions */
3256 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 1);
3257 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0, 0);
3258 for (i = 1; i < hsotg->num_of_eps; i++) {
3259 if (hsotg->eps_in[i])
3260 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3262 if (hsotg->eps_out[i])
3263 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps,
3268 /* ensure after enumeration our EP0 is active */
3270 dwc2_hsotg_enqueue_setup(hsotg);
3272 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3273 dwc2_readl(hsotg, DIEPCTL0),
3274 dwc2_readl(hsotg, DOEPCTL0));
3278 * kill_all_requests - remove all requests from the endpoint's queue
3279 * @hsotg: The device state.
3280 * @ep: The endpoint the requests may be on.
3281 * @result: The result code to use.
3283 * Go through the requests on the given endpoint and mark them
3284 * completed with the given result code.
3286 static void kill_all_requests(struct dwc2_hsotg *hsotg,
3287 struct dwc2_hsotg_ep *ep,
3294 while (!list_empty(&ep->queue)) {
3295 struct dwc2_hsotg_req *req = get_ep_head(ep);
3297 dwc2_hsotg_complete_request(hsotg, ep, req, result);
3300 if (!hsotg->dedicated_fifos)
3302 size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4;
3303 if (size < ep->fifo_size)
3304 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
3308 * dwc2_hsotg_disconnect - disconnect service
3309 * @hsotg: The device state.
3311 * The device has been disconnected. Remove all current
3312 * transactions and signal the gadget driver that this
3315 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
3319 if (!hsotg->connected)
3322 hsotg->connected = 0;
3323 hsotg->test_mode = 0;
3325 /* all endpoints should be shutdown */
3326 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3327 if (hsotg->eps_in[ep])
3328 kill_all_requests(hsotg, hsotg->eps_in[ep],
3330 if (hsotg->eps_out[ep])
3331 kill_all_requests(hsotg, hsotg->eps_out[ep],
3335 call_gadget(hsotg, disconnect);
3336 hsotg->lx_state = DWC2_L3;
3338 usb_gadget_set_state(&hsotg->gadget, USB_STATE_NOTATTACHED);
3342 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3343 * @hsotg: The device state:
3344 * @periodic: True if this is a periodic FIFO interrupt
3346 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
3348 struct dwc2_hsotg_ep *ep;
3351 /* look through for any more data to transmit */
3352 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
3353 ep = index_to_ep(hsotg, epno, 1);
3361 if ((periodic && !ep->periodic) ||
3362 (!periodic && ep->periodic))
3365 ret = dwc2_hsotg_trytx(hsotg, ep);
3371 /* IRQ flags which will trigger a retry around the IRQ loop */
3372 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3376 static int dwc2_hsotg_ep_disable(struct usb_ep *ep);
3378 * dwc2_hsotg_core_init_disconnected - issue softreset to the core
3379 * @hsotg: The device state
3380 * @is_usb_reset: Usb resetting flag
3382 * Issue a soft reset to the core, and await the core finishing it.
3384 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
3393 /* Kill any ep0 requests as controller will be reinitialized */
3394 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
3396 if (!is_usb_reset) {
3397 if (dwc2_core_reset(hsotg, true))
3400 /* all endpoints should be shutdown */
3401 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3402 if (hsotg->eps_in[ep])
3403 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3404 if (hsotg->eps_out[ep])
3405 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3410 * we must now enable ep0 ready for host detection and then
3411 * set configuration.
3414 /* keep other bits untouched (so e.g. forced modes are not lost) */
3415 usbcfg = dwc2_readl(hsotg, GUSBCFG);
3416 usbcfg &= ~GUSBCFG_TOUTCAL_MASK;
3417 usbcfg |= GUSBCFG_TOUTCAL(7);
3419 /* remove the HNP/SRP and set the PHY */
3420 usbcfg &= ~(GUSBCFG_SRPCAP | GUSBCFG_HNPCAP);
3421 dwc2_writel(hsotg, usbcfg, GUSBCFG);
3423 dwc2_phy_init(hsotg, true);
3425 dwc2_hsotg_init_fifo(hsotg);
3428 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3430 dcfg |= DCFG_EPMISCNT(1);
3432 switch (hsotg->params.speed) {
3433 case DWC2_SPEED_PARAM_LOW:
3434 dcfg |= DCFG_DEVSPD_LS;
3436 case DWC2_SPEED_PARAM_FULL:
3437 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS)
3438 dcfg |= DCFG_DEVSPD_FS48;
3440 dcfg |= DCFG_DEVSPD_FS;
3443 dcfg |= DCFG_DEVSPD_HS;
3446 if (hsotg->params.ipg_isoc_en)
3447 dcfg |= DCFG_IPG_ISOC_SUPPORDED;
3449 dwc2_writel(hsotg, dcfg, DCFG);
3451 /* Clear any pending OTG interrupts */
3452 dwc2_writel(hsotg, 0xffffffff, GOTGINT);
3454 /* Clear any pending interrupts */
3455 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
3456 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
3457 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
3458 GINTSTS_USBRST | GINTSTS_RESETDET |
3459 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
3460 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
3461 GINTSTS_LPMTRANRCVD;
3463 if (!using_desc_dma(hsotg))
3464 intmsk |= GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
3466 if (!hsotg->params.external_id_pin_ctl)
3467 intmsk |= GINTSTS_CONIDSTSCHNG;
3469 dwc2_writel(hsotg, intmsk, GINTMSK);
3471 if (using_dma(hsotg)) {
3472 dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
3473 hsotg->params.ahbcfg,
3476 /* Set DDMA mode support in the core if needed */
3477 if (using_desc_dma(hsotg))
3478 dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN);
3481 dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ?
3482 (GAHBCFG_NP_TXF_EMP_LVL |
3483 GAHBCFG_P_TXF_EMP_LVL) : 0) |
3484 GAHBCFG_GLBL_INTR_EN, GAHBCFG);
3488 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3489 * when we have no data to transfer. Otherwise we get being flooded by
3493 dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
3494 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
3495 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
3496 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK,
3500 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3501 * DMA mode we may need this and StsPhseRcvd.
3503 dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
3504 DOEPMSK_STSPHSERCVDMSK) : 0) |
3505 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
3509 /* Enable BNA interrupt for DDMA */
3510 if (using_desc_dma(hsotg)) {
3511 dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK);
3512 dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK);
3515 /* Enable Service Interval mode if supported */
3516 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3517 dwc2_set_bit(hsotg, DCTL, DCTL_SERVICE_INTERVAL_SUPPORTED);
3519 dwc2_writel(hsotg, 0, DAINTMSK);
3521 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3522 dwc2_readl(hsotg, DIEPCTL0),
3523 dwc2_readl(hsotg, DOEPCTL0));
3525 /* enable in and out endpoint interrupts */
3526 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
3529 * Enable the RXFIFO when in slave mode, as this is how we collect
3530 * the data. In DMA mode, we get events from the FIFO but also
3531 * things we cannot process, so do not use it.
3533 if (!using_dma(hsotg))
3534 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
3536 /* Enable interrupts for EP0 in and out */
3537 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
3538 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
3540 if (!is_usb_reset) {
3541 dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3542 udelay(10); /* see openiboot */
3543 dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE);
3546 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL));
3549 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3550 * writing to the EPCTL register..
3553 /* set to read 1 8byte packet */
3554 dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3555 DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0);
3557 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3558 DXEPCTL_CNAK | DXEPCTL_EPENA |
3562 /* enable, but don't activate EP0in */
3563 dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
3564 DXEPCTL_USBACTEP, DIEPCTL0);
3566 /* clear global NAKs */
3567 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
3569 val |= DCTL_SFTDISCON;
3570 dwc2_set_bit(hsotg, DCTL, val);
3572 /* configure the core to support LPM */
3573 dwc2_gadget_init_lpm(hsotg);
3575 /* program GREFCLK register if needed */
3576 if (using_desc_dma(hsotg) && hsotg->params.service_interval)
3577 dwc2_gadget_program_ref_clk(hsotg);
3579 /* must be at-least 3ms to allow bus to see disconnect */
3582 hsotg->lx_state = DWC2_L0;
3584 dwc2_hsotg_enqueue_setup(hsotg);
3586 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3587 dwc2_readl(hsotg, DIEPCTL0),
3588 dwc2_readl(hsotg, DOEPCTL0));
3591 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
3593 /* set the soft-disconnect bit */
3594 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
3597 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
3599 /* remove the soft-disconnect and let's go */
3600 if (!hsotg->role_sw || (dwc2_readl(hsotg, GOTGCTL) & GOTGCTL_BSESVLD))
3601 dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON);
3605 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3606 * @hsotg: The device state:
3608 * This interrupt indicates one of the following conditions occurred while
3609 * transmitting an ISOC transaction.
3610 * - Corrupted IN Token for ISOC EP.
3611 * - Packet not complete in FIFO.
3613 * The following actions will be taken:
3614 * - Determine the EP
3615 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3617 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg)
3619 struct dwc2_hsotg_ep *hs_ep;
3624 dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n");
3626 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3628 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3629 hs_ep = hsotg->eps_in[idx];
3630 /* Proceed only unmasked ISOC EPs */
3631 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3634 epctrl = dwc2_readl(hsotg, DIEPCTL(idx));
3635 if ((epctrl & DXEPCTL_EPENA) &&
3636 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3637 epctrl |= DXEPCTL_SNAK;
3638 epctrl |= DXEPCTL_EPDIS;
3639 dwc2_writel(hsotg, epctrl, DIEPCTL(idx));
3643 /* Clear interrupt */
3644 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS);
3648 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3649 * @hsotg: The device state:
3651 * This interrupt indicates one of the following conditions occurred while
3652 * transmitting an ISOC transaction.
3653 * - Corrupted OUT Token for ISOC EP.
3654 * - Packet not complete in FIFO.
3656 * The following actions will be taken:
3657 * - Determine the EP
3658 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3660 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg)
3666 struct dwc2_hsotg_ep *hs_ep;
3669 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
3671 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3672 daintmsk >>= DAINT_OUTEP_SHIFT;
3674 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3675 hs_ep = hsotg->eps_out[idx];
3676 /* Proceed only unmasked ISOC EPs */
3677 if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous)
3680 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3681 if ((epctrl & DXEPCTL_EPENA) &&
3682 dwc2_gadget_target_frame_elapsed(hs_ep)) {
3683 /* Unmask GOUTNAKEFF interrupt */
3684 gintmsk = dwc2_readl(hsotg, GINTMSK);
3685 gintmsk |= GINTSTS_GOUTNAKEFF;
3686 dwc2_writel(hsotg, gintmsk, GINTMSK);
3688 gintsts = dwc2_readl(hsotg, GINTSTS);
3689 if (!(gintsts & GINTSTS_GOUTNAKEFF)) {
3690 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3696 /* Clear interrupt */
3697 dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS);
3701 * dwc2_hsotg_irq - handle device interrupt
3702 * @irq: The IRQ number triggered
3703 * @pw: The pw value when registered the handler.
3705 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
3707 struct dwc2_hsotg *hsotg = pw;
3708 int retry_count = 8;
3712 if (!dwc2_is_device_mode(hsotg))
3715 spin_lock(&hsotg->lock);
3717 gintsts = dwc2_readl(hsotg, GINTSTS);
3718 gintmsk = dwc2_readl(hsotg, GINTMSK);
3720 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
3721 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
3725 if (gintsts & GINTSTS_RESETDET) {
3726 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
3728 dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS);
3730 /* This event must be used only if controller is suspended */
3731 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2)
3732 dwc2_exit_partial_power_down(hsotg, 0, true);
3734 /* Exit gadget mode clock gating. */
3735 if (hsotg->params.power_down ==
3736 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended &&
3737 !hsotg->params.no_clock_gating)
3738 dwc2_gadget_exit_clock_gating(hsotg, 0);
3740 hsotg->lx_state = DWC2_L0;
3743 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
3744 u32 usb_status = dwc2_readl(hsotg, GOTGCTL);
3745 u32 connected = hsotg->connected;
3747 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
3748 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
3749 dwc2_readl(hsotg, GNPTXSTS));
3751 dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS);
3753 /* Report disconnection if it is not already done. */
3754 dwc2_hsotg_disconnect(hsotg);
3756 /* Reset device address to zero */
3757 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
3759 if (usb_status & GOTGCTL_BSESVLD && connected)
3760 dwc2_hsotg_core_init_disconnected(hsotg, true);
3763 if (gintsts & GINTSTS_ENUMDONE) {
3764 dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS);
3766 dwc2_hsotg_irq_enumdone(hsotg);
3769 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
3770 u32 daint = dwc2_readl(hsotg, DAINT);
3771 u32 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3772 u32 daint_out, daint_in;
3776 daint_out = daint >> DAINT_OUTEP_SHIFT;
3777 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
3779 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
3781 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
3782 ep++, daint_out >>= 1) {
3784 dwc2_hsotg_epint(hsotg, ep, 0);
3787 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
3788 ep++, daint_in >>= 1) {
3790 dwc2_hsotg_epint(hsotg, ep, 1);
3794 /* check both FIFOs */
3796 if (gintsts & GINTSTS_NPTXFEMP) {
3797 dev_dbg(hsotg->dev, "NPTxFEmp\n");
3800 * Disable the interrupt to stop it happening again
3801 * unless one of these endpoint routines decides that
3802 * it needs re-enabling
3805 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
3806 dwc2_hsotg_irq_fifoempty(hsotg, false);
3809 if (gintsts & GINTSTS_PTXFEMP) {
3810 dev_dbg(hsotg->dev, "PTxFEmp\n");
3812 /* See note in GINTSTS_NPTxFEmp */
3814 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
3815 dwc2_hsotg_irq_fifoempty(hsotg, true);
3818 if (gintsts & GINTSTS_RXFLVL) {
3820 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3821 * we need to retry dwc2_hsotg_handle_rx if this is still
3825 dwc2_hsotg_handle_rx(hsotg);
3828 if (gintsts & GINTSTS_ERLYSUSP) {
3829 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
3830 dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS);
3834 * these next two seem to crop-up occasionally causing the core
3835 * to shutdown the USB transfer, so try clearing them and logging
3839 if (gintsts & GINTSTS_GOUTNAKEFF) {
3844 struct dwc2_hsotg_ep *hs_ep;
3846 daintmsk = dwc2_readl(hsotg, DAINTMSK);
3847 daintmsk >>= DAINT_OUTEP_SHIFT;
3848 /* Mask this interrupt */
3849 gintmsk = dwc2_readl(hsotg, GINTMSK);
3850 gintmsk &= ~GINTSTS_GOUTNAKEFF;
3851 dwc2_writel(hsotg, gintmsk, GINTMSK);
3853 dev_dbg(hsotg->dev, "GOUTNakEff triggered\n");
3854 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3855 hs_ep = hsotg->eps_out[idx];
3856 /* Proceed only unmasked ISOC EPs */
3857 if (BIT(idx) & ~daintmsk)
3860 epctrl = dwc2_readl(hsotg, DOEPCTL(idx));
3863 if ((epctrl & DXEPCTL_EPENA) && hs_ep->isochronous) {
3864 epctrl |= DXEPCTL_SNAK;
3865 epctrl |= DXEPCTL_EPDIS;
3866 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3871 if (hs_ep->halted) {
3872 if (!(epctrl & DXEPCTL_EPENA))
3873 epctrl |= DXEPCTL_EPENA;
3874 epctrl |= DXEPCTL_EPDIS;
3875 epctrl |= DXEPCTL_STALL;
3876 dwc2_writel(hsotg, epctrl, DOEPCTL(idx));
3880 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3883 if (gintsts & GINTSTS_GINNAKEFF) {
3884 dev_info(hsotg->dev, "GINNakEff triggered\n");
3886 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
3888 dwc2_hsotg_dump(hsotg);
3891 if (gintsts & GINTSTS_INCOMPL_SOIN)
3892 dwc2_gadget_handle_incomplete_isoc_in(hsotg);
3894 if (gintsts & GINTSTS_INCOMPL_SOOUT)
3895 dwc2_gadget_handle_incomplete_isoc_out(hsotg);
3898 * if we've had fifo events, we should try and go around the
3899 * loop again to see if there's any point in returning yet.
3902 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
3905 /* Check WKUP_ALERT interrupt*/
3906 if (hsotg->params.service_interval)
3907 dwc2_gadget_wkup_alert_handler(hsotg);
3909 spin_unlock(&hsotg->lock);
3914 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3915 struct dwc2_hsotg_ep *hs_ep)
3920 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3921 DOEPCTL(hs_ep->index);
3922 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3923 DOEPINT(hs_ep->index);
3925 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3928 if (hs_ep->dir_in) {
3929 if (hsotg->dedicated_fifos || hs_ep->periodic) {
3930 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK);
3931 /* Wait for Nak effect */
3932 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3933 DXEPINT_INEPNAKEFF, 100))
3934 dev_warn(hsotg->dev,
3935 "%s: timeout DIEPINT.NAKEFF\n",
3938 dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK);
3939 /* Wait for Nak effect */
3940 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3941 GINTSTS_GINNAKEFF, 100))
3942 dev_warn(hsotg->dev,
3943 "%s: timeout GINTSTS.GINNAKEFF\n",
3947 /* Mask GINTSTS_GOUTNAKEFF interrupt */
3948 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_GOUTNAKEFF);
3950 if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF))
3951 dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK);
3953 if (!using_dma(hsotg)) {
3954 /* Wait for GINTSTS_RXFLVL interrupt */
3955 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3956 GINTSTS_RXFLVL, 100)) {
3957 dev_warn(hsotg->dev, "%s: timeout GINTSTS.RXFLVL\n",
3961 * Pop GLOBAL OUT NAK status packet from RxFIFO
3962 * to assert GOUTNAKEFF interrupt
3964 dwc2_readl(hsotg, GRXSTSP);
3968 /* Wait for global nak to take effect */
3969 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3970 GINTSTS_GOUTNAKEFF, 100))
3971 dev_warn(hsotg->dev, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3976 dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3978 /* Wait for ep to be disabled */
3979 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3980 dev_warn(hsotg->dev,
3981 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3983 /* Clear EPDISBLD interrupt */
3984 dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD);
3986 if (hs_ep->dir_in) {
3987 unsigned short fifo_index;
3989 if (hsotg->dedicated_fifos || hs_ep->periodic)
3990 fifo_index = hs_ep->fifo_index;
3995 dwc2_flush_tx_fifo(hsotg, fifo_index);
3997 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3998 if (!hsotg->dedicated_fifos && !hs_ep->periodic)
3999 dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK);
4002 /* Remove global NAKs */
4003 dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK);
4008 * dwc2_hsotg_ep_enable - enable the given endpoint
4009 * @ep: The USB endpint to configure
4010 * @desc: The USB endpoint descriptor to configure with.
4012 * This is called from the USB gadget code's usb_ep_enable().
4014 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
4015 const struct usb_endpoint_descriptor *desc)
4017 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4018 struct dwc2_hsotg *hsotg = hs_ep->parent;
4019 unsigned long flags;
4020 unsigned int index = hs_ep->index;
4026 unsigned int dir_in;
4027 unsigned int i, val, size;
4029 unsigned char ep_type;
4033 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
4034 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
4035 desc->wMaxPacketSize, desc->bInterval);
4037 /* not to be called for EP0 */
4039 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
4043 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
4044 if (dir_in != hs_ep->dir_in) {
4045 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
4049 ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
4050 mps = usb_endpoint_maxp(desc);
4051 mc = usb_endpoint_maxp_mult(desc);
4053 /* ISOC IN in DDMA supported bInterval up to 10 */
4054 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4055 dir_in && desc->bInterval > 10) {
4057 "%s: ISOC IN, DDMA: bInterval>10 not supported!\n", __func__);
4061 /* High bandwidth ISOC OUT in DDMA not supported */
4062 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC &&
4063 !dir_in && mc > 1) {
4065 "%s: ISOC OUT, DDMA: HB not supported!\n", __func__);
4069 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
4071 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4072 epctrl = dwc2_readl(hsotg, epctrl_reg);
4074 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
4075 __func__, epctrl, epctrl_reg);
4077 if (using_desc_dma(hsotg) && ep_type == USB_ENDPOINT_XFER_ISOC)
4078 desc_num = MAX_DMA_DESC_NUM_HS_ISOC;
4080 desc_num = MAX_DMA_DESC_NUM_GENERIC;
4082 /* Allocate DMA descriptor chain for non-ctrl endpoints */
4083 if (using_desc_dma(hsotg) && !hs_ep->desc_list) {
4084 hs_ep->desc_list = dmam_alloc_coherent(hsotg->dev,
4085 desc_num * sizeof(struct dwc2_dma_desc),
4086 &hs_ep->desc_list_dma, GFP_ATOMIC);
4087 if (!hs_ep->desc_list) {
4093 spin_lock_irqsave(&hsotg->lock, flags);
4095 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
4096 epctrl |= DXEPCTL_MPS(mps);
4099 * mark the endpoint as active, otherwise the core may ignore
4100 * transactions entirely for this endpoint
4102 epctrl |= DXEPCTL_USBACTEP;
4104 /* update the endpoint state */
4105 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, mc, dir_in);
4107 /* default, set to non-periodic */
4108 hs_ep->isochronous = 0;
4109 hs_ep->periodic = 0;
4112 hs_ep->interval = desc->bInterval;
4115 case USB_ENDPOINT_XFER_ISOC:
4116 epctrl |= DXEPCTL_EPTYPE_ISO;
4117 epctrl |= DXEPCTL_SETEVENFR;
4118 hs_ep->isochronous = 1;
4119 hs_ep->interval = 1 << (desc->bInterval - 1);
4120 hs_ep->target_frame = TARGET_FRAME_INITIAL;
4121 hs_ep->next_desc = 0;
4122 hs_ep->compl_desc = 0;
4124 hs_ep->periodic = 1;
4125 mask = dwc2_readl(hsotg, DIEPMSK);
4126 mask |= DIEPMSK_NAKMSK;
4127 dwc2_writel(hsotg, mask, DIEPMSK);
4129 epctrl |= DXEPCTL_SNAK;
4130 mask = dwc2_readl(hsotg, DOEPMSK);
4131 mask |= DOEPMSK_OUTTKNEPDISMSK;
4132 dwc2_writel(hsotg, mask, DOEPMSK);
4136 case USB_ENDPOINT_XFER_BULK:
4137 epctrl |= DXEPCTL_EPTYPE_BULK;
4140 case USB_ENDPOINT_XFER_INT:
4142 hs_ep->periodic = 1;
4144 if (hsotg->gadget.speed == USB_SPEED_HIGH)
4145 hs_ep->interval = 1 << (desc->bInterval - 1);
4147 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
4150 case USB_ENDPOINT_XFER_CONTROL:
4151 epctrl |= DXEPCTL_EPTYPE_CONTROL;
4156 * if the hardware has dedicated fifos, we must give each IN EP
4157 * a unique tx-fifo even if it is non-periodic.
4159 if (dir_in && hsotg->dedicated_fifos) {
4160 unsigned fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
4162 u32 fifo_size = UINT_MAX;
4164 size = hs_ep->ep.maxpacket * hs_ep->mc;
4165 for (i = 1; i <= fifo_count; ++i) {
4166 if (hsotg->fifo_map & (1 << i))
4168 val = dwc2_readl(hsotg, DPTXFSIZN(i));
4169 val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4;
4172 /* Search for smallest acceptable fifo */
4173 if (val < fifo_size) {
4180 "%s: No suitable fifo found\n", __func__);
4184 epctrl &= ~(DXEPCTL_TXFNUM_LIMIT << DXEPCTL_TXFNUM_SHIFT);
4185 hsotg->fifo_map |= 1 << fifo_index;
4186 epctrl |= DXEPCTL_TXFNUM(fifo_index);
4187 hs_ep->fifo_index = fifo_index;
4188 hs_ep->fifo_size = fifo_size;
4191 /* for non control endpoints, set PID to D0 */
4192 if (index && !hs_ep->isochronous)
4193 epctrl |= DXEPCTL_SETD0PID;
4195 /* WA for Full speed ISOC IN in DDMA mode.
4196 * By Clear NAK status of EP, core will send ZLP
4197 * to IN token and assert NAK interrupt relying
4198 * on TxFIFO status only
4201 if (hsotg->gadget.speed == USB_SPEED_FULL &&
4202 hs_ep->isochronous && dir_in) {
4203 /* The WA applies only to core versions from 2.72a
4204 * to 4.00a (including both). Also for FS_IOT_1.00a
4207 u32 gsnpsid = dwc2_readl(hsotg, GSNPSID);
4209 if ((gsnpsid >= DWC2_CORE_REV_2_72a &&
4210 gsnpsid <= DWC2_CORE_REV_4_00a) ||
4211 gsnpsid == DWC2_FS_IOT_REV_1_00a ||
4212 gsnpsid == DWC2_HS_IOT_REV_1_00a)
4213 epctrl |= DXEPCTL_CNAK;
4216 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
4219 dwc2_writel(hsotg, epctrl, epctrl_reg);
4220 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
4221 __func__, dwc2_readl(hsotg, epctrl_reg));
4223 /* enable the endpoint interrupt */
4224 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
4227 spin_unlock_irqrestore(&hsotg->lock, flags);
4230 if (ret && using_desc_dma(hsotg) && hs_ep->desc_list) {
4231 dmam_free_coherent(hsotg->dev, desc_num *
4232 sizeof(struct dwc2_dma_desc),
4233 hs_ep->desc_list, hs_ep->desc_list_dma);
4234 hs_ep->desc_list = NULL;
4241 * dwc2_hsotg_ep_disable - disable given endpoint
4242 * @ep: The endpoint to disable.
4244 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
4246 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4247 struct dwc2_hsotg *hsotg = hs_ep->parent;
4248 int dir_in = hs_ep->dir_in;
4249 int index = hs_ep->index;
4253 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
4255 if (ep == &hsotg->eps_out[0]->ep) {
4256 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
4260 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4261 dev_err(hsotg->dev, "%s: called in host mode?\n", __func__);
4265 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
4267 ctrl = dwc2_readl(hsotg, epctrl_reg);
4269 if (ctrl & DXEPCTL_EPENA)
4270 dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep);
4272 ctrl &= ~DXEPCTL_EPENA;
4273 ctrl &= ~DXEPCTL_USBACTEP;
4274 ctrl |= DXEPCTL_SNAK;
4276 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
4277 dwc2_writel(hsotg, ctrl, epctrl_reg);
4279 /* disable endpoint interrupts */
4280 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
4282 /* terminate all requests with shutdown */
4283 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
4285 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
4286 hs_ep->fifo_index = 0;
4287 hs_ep->fifo_size = 0;
4292 static int dwc2_hsotg_ep_disable_lock(struct usb_ep *ep)
4294 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4295 struct dwc2_hsotg *hsotg = hs_ep->parent;
4296 unsigned long flags;
4299 spin_lock_irqsave(&hsotg->lock, flags);
4300 ret = dwc2_hsotg_ep_disable(ep);
4301 spin_unlock_irqrestore(&hsotg->lock, flags);
4306 * on_list - check request is on the given endpoint
4307 * @ep: The endpoint to check.
4308 * @test: The request to test if it is on the endpoint.
4310 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
4312 struct dwc2_hsotg_req *req, *treq;
4314 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
4323 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
4324 * @ep: The endpoint to dequeue.
4325 * @req: The request to be removed from a queue.
4327 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
4329 struct dwc2_hsotg_req *hs_req = our_req(req);
4330 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4331 struct dwc2_hsotg *hs = hs_ep->parent;
4332 unsigned long flags;
4334 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
4336 spin_lock_irqsave(&hs->lock, flags);
4338 if (!on_list(hs_ep, hs_req)) {
4339 spin_unlock_irqrestore(&hs->lock, flags);
4343 /* Dequeue already started request */
4344 if (req == &hs_ep->req->req)
4345 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
4347 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
4348 spin_unlock_irqrestore(&hs->lock, flags);
4354 * dwc2_gadget_ep_set_wedge - set wedge on a given endpoint
4355 * @ep: The endpoint to be wedged.
4358 static int dwc2_gadget_ep_set_wedge(struct usb_ep *ep)
4360 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4361 struct dwc2_hsotg *hs = hs_ep->parent;
4363 unsigned long flags;
4366 spin_lock_irqsave(&hs->lock, flags);
4368 ret = dwc2_hsotg_ep_sethalt(ep, 1, false);
4369 spin_unlock_irqrestore(&hs->lock, flags);
4375 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
4376 * @ep: The endpoint to set halt.
4377 * @value: Set or unset the halt.
4378 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
4379 * the endpoint is busy processing requests.
4381 * We need to stall the endpoint immediately if request comes from set_feature
4382 * protocol command handler.
4384 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
4386 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4387 struct dwc2_hsotg *hs = hs_ep->parent;
4388 int index = hs_ep->index;
4393 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
4397 dwc2_hsotg_stall_ep0(hs);
4400 "%s: can't clear halt on ep0\n", __func__);
4404 if (hs_ep->isochronous) {
4405 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
4409 if (!now && value && !list_empty(&hs_ep->queue)) {
4410 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
4415 if (hs_ep->dir_in) {
4416 epreg = DIEPCTL(index);
4417 epctl = dwc2_readl(hs, epreg);
4420 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
4421 if (epctl & DXEPCTL_EPENA)
4422 epctl |= DXEPCTL_EPDIS;
4424 epctl &= ~DXEPCTL_STALL;
4426 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4427 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4428 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4429 epctl |= DXEPCTL_SETD0PID;
4431 dwc2_writel(hs, epctl, epreg);
4433 epreg = DOEPCTL(index);
4434 epctl = dwc2_readl(hs, epreg);
4437 /* Unmask GOUTNAKEFF interrupt */
4438 dwc2_hsotg_en_gsint(hs, GINTSTS_GOUTNAKEFF);
4440 if (!(dwc2_readl(hs, GINTSTS) & GINTSTS_GOUTNAKEFF))
4441 dwc2_set_bit(hs, DCTL, DCTL_SGOUTNAK);
4442 // STALL bit will be set in GOUTNAKEFF interrupt handler
4444 epctl &= ~DXEPCTL_STALL;
4446 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
4447 if (xfertype == DXEPCTL_EPTYPE_BULK ||
4448 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
4449 epctl |= DXEPCTL_SETD0PID;
4450 dwc2_writel(hs, epctl, epreg);
4454 hs_ep->halted = value;
4459 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4460 * @ep: The endpoint to set halt.
4461 * @value: Set or unset the halt.
4463 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
4465 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
4466 struct dwc2_hsotg *hs = hs_ep->parent;
4467 unsigned long flags;
4470 spin_lock_irqsave(&hs->lock, flags);
4471 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
4472 spin_unlock_irqrestore(&hs->lock, flags);
4477 static const struct usb_ep_ops dwc2_hsotg_ep_ops = {
4478 .enable = dwc2_hsotg_ep_enable,
4479 .disable = dwc2_hsotg_ep_disable_lock,
4480 .alloc_request = dwc2_hsotg_ep_alloc_request,
4481 .free_request = dwc2_hsotg_ep_free_request,
4482 .queue = dwc2_hsotg_ep_queue_lock,
4483 .dequeue = dwc2_hsotg_ep_dequeue,
4484 .set_halt = dwc2_hsotg_ep_sethalt_lock,
4485 .set_wedge = dwc2_gadget_ep_set_wedge,
4486 /* note, don't believe we have any call for the fifo routines */
4490 * dwc2_hsotg_init - initialize the usb core
4491 * @hsotg: The driver state
4493 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
4495 /* unmask subset of endpoint interrupts */
4497 dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
4498 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
4501 dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
4502 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
4505 dwc2_writel(hsotg, 0, DAINTMSK);
4507 /* Be in disconnected state until gadget is registered */
4508 dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON);
4512 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4513 dwc2_readl(hsotg, GRXFSIZ),
4514 dwc2_readl(hsotg, GNPTXFSIZ));
4516 dwc2_hsotg_init_fifo(hsotg);
4518 if (using_dma(hsotg))
4519 dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN);
4523 * dwc2_hsotg_udc_start - prepare the udc for work
4524 * @gadget: The usb gadget state
4525 * @driver: The usb gadget driver
4527 * Perform initialization to prepare udc device and driver
4530 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
4531 struct usb_gadget_driver *driver)
4533 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4534 unsigned long flags;
4538 pr_err("%s: called with no device\n", __func__);
4543 dev_err(hsotg->dev, "%s: no driver\n", __func__);
4547 if (driver->max_speed < USB_SPEED_FULL)
4548 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
4550 if (!driver->setup) {
4551 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
4555 WARN_ON(hsotg->driver);
4557 hsotg->driver = driver;
4558 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
4559 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4561 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
4562 ret = dwc2_lowlevel_hw_enable(hsotg);
4567 if (!IS_ERR_OR_NULL(hsotg->uphy))
4568 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
4570 spin_lock_irqsave(&hsotg->lock, flags);
4571 if (dwc2_hw_is_device(hsotg)) {
4572 dwc2_hsotg_init(hsotg);
4573 dwc2_hsotg_core_init_disconnected(hsotg, false);
4577 spin_unlock_irqrestore(&hsotg->lock, flags);
4579 gadget->sg_supported = using_desc_dma(hsotg);
4580 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
4585 hsotg->driver = NULL;
4590 * dwc2_hsotg_udc_stop - stop the udc
4591 * @gadget: The usb gadget state
4593 * Stop udc hw block and stay tunned for future transmissions
4595 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
4597 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4598 unsigned long flags;
4604 /* all endpoints should be shutdown */
4605 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
4606 if (hsotg->eps_in[ep])
4607 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
4608 if (hsotg->eps_out[ep])
4609 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
4612 spin_lock_irqsave(&hsotg->lock, flags);
4614 hsotg->driver = NULL;
4615 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4618 spin_unlock_irqrestore(&hsotg->lock, flags);
4620 if (!IS_ERR_OR_NULL(hsotg->uphy))
4621 otg_set_peripheral(hsotg->uphy->otg, NULL);
4623 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
4624 dwc2_lowlevel_hw_disable(hsotg);
4630 * dwc2_hsotg_gadget_getframe - read the frame number
4631 * @gadget: The usb gadget state
4633 * Read the {micro} frame number
4635 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
4637 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
4641 * dwc2_hsotg_set_selfpowered - set if device is self/bus powered
4642 * @gadget: The usb gadget state
4643 * @is_selfpowered: Whether the device is self-powered
4645 * Set if the device is self or bus powered.
4647 static int dwc2_hsotg_set_selfpowered(struct usb_gadget *gadget,
4650 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4651 unsigned long flags;
4653 spin_lock_irqsave(&hsotg->lock, flags);
4654 gadget->is_selfpowered = !!is_selfpowered;
4655 spin_unlock_irqrestore(&hsotg->lock, flags);
4661 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4662 * @gadget: The usb gadget state
4663 * @is_on: Current state of the USB PHY
4665 * Connect/Disconnect the USB PHY pullup
4667 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
4669 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4670 unsigned long flags;
4672 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
4675 /* Don't modify pullup state while in host mode */
4676 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
4677 hsotg->enabled = is_on;
4681 spin_lock_irqsave(&hsotg->lock, flags);
4684 dwc2_hsotg_core_init_disconnected(hsotg, false);
4685 /* Enable ACG feature in device mode,if supported */
4686 dwc2_enable_acg(hsotg);
4687 dwc2_hsotg_core_connect(hsotg);
4689 dwc2_hsotg_core_disconnect(hsotg);
4690 dwc2_hsotg_disconnect(hsotg);
4694 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
4695 spin_unlock_irqrestore(&hsotg->lock, flags);
4700 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
4702 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4703 unsigned long flags;
4705 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
4706 spin_lock_irqsave(&hsotg->lock, flags);
4709 * If controller is in partial power down state, it must exit from
4710 * that state before being initialized / de-initialized
4712 if (hsotg->lx_state == DWC2_L2 && hsotg->in_ppd)
4714 * No need to check the return value as
4715 * registers are not being restored.
4717 dwc2_exit_partial_power_down(hsotg, 0, false);
4720 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
4722 dwc2_hsotg_core_init_disconnected(hsotg, false);
4723 if (hsotg->enabled) {
4724 /* Enable ACG feature in device mode,if supported */
4725 dwc2_enable_acg(hsotg);
4726 dwc2_hsotg_core_connect(hsotg);
4729 dwc2_hsotg_core_disconnect(hsotg);
4730 dwc2_hsotg_disconnect(hsotg);
4733 spin_unlock_irqrestore(&hsotg->lock, flags);
4738 * dwc2_hsotg_vbus_draw - report bMaxPower field
4739 * @gadget: The usb gadget state
4740 * @mA: Amount of current
4742 * Report how much power the device may consume to the phy.
4744 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
4746 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
4748 if (IS_ERR_OR_NULL(hsotg->uphy))
4750 return usb_phy_set_power(hsotg->uphy, mA);
4753 static void dwc2_gadget_set_speed(struct usb_gadget *g, enum usb_device_speed speed)
4755 struct dwc2_hsotg *hsotg = to_hsotg(g);
4756 unsigned long flags;
4758 spin_lock_irqsave(&hsotg->lock, flags);
4760 case USB_SPEED_HIGH:
4761 hsotg->params.speed = DWC2_SPEED_PARAM_HIGH;
4763 case USB_SPEED_FULL:
4764 hsotg->params.speed = DWC2_SPEED_PARAM_FULL;
4767 hsotg->params.speed = DWC2_SPEED_PARAM_LOW;
4770 dev_err(hsotg->dev, "invalid speed (%d)\n", speed);
4772 spin_unlock_irqrestore(&hsotg->lock, flags);
4775 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
4776 .get_frame = dwc2_hsotg_gadget_getframe,
4777 .set_selfpowered = dwc2_hsotg_set_selfpowered,
4778 .udc_start = dwc2_hsotg_udc_start,
4779 .udc_stop = dwc2_hsotg_udc_stop,
4780 .pullup = dwc2_hsotg_pullup,
4781 .udc_set_speed = dwc2_gadget_set_speed,
4782 .vbus_session = dwc2_hsotg_vbus_session,
4783 .vbus_draw = dwc2_hsotg_vbus_draw,
4787 * dwc2_hsotg_initep - initialise a single endpoint
4788 * @hsotg: The device state.
4789 * @hs_ep: The endpoint to be initialised.
4790 * @epnum: The endpoint number
4791 * @dir_in: True if direction is in.
4793 * Initialise the given endpoint (as part of the probe and device state
4794 * creation) to give to the gadget driver. Setup the endpoint name, any
4795 * direction information and other state that may be required.
4797 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
4798 struct dwc2_hsotg_ep *hs_ep,
4811 hs_ep->dir_in = dir_in;
4812 hs_ep->index = epnum;
4814 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
4816 INIT_LIST_HEAD(&hs_ep->queue);
4817 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
4819 /* add to the list of endpoints known by the gadget driver */
4821 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
4823 hs_ep->parent = hsotg;
4824 hs_ep->ep.name = hs_ep->name;
4826 if (hsotg->params.speed == DWC2_SPEED_PARAM_LOW)
4827 usb_ep_set_maxpacket_limit(&hs_ep->ep, 8);
4829 usb_ep_set_maxpacket_limit(&hs_ep->ep,
4830 epnum ? 1024 : EP0_MPS_LIMIT);
4831 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
4834 hs_ep->ep.caps.type_control = true;
4836 if (hsotg->params.speed != DWC2_SPEED_PARAM_LOW) {
4837 hs_ep->ep.caps.type_iso = true;
4838 hs_ep->ep.caps.type_bulk = true;
4840 hs_ep->ep.caps.type_int = true;
4844 hs_ep->ep.caps.dir_in = true;
4846 hs_ep->ep.caps.dir_out = true;
4849 * if we're using dma, we need to set the next-endpoint pointer
4850 * to be something valid.
4853 if (using_dma(hsotg)) {
4854 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
4857 dwc2_writel(hsotg, next, DIEPCTL(epnum));
4859 dwc2_writel(hsotg, next, DOEPCTL(epnum));
4864 * dwc2_hsotg_hw_cfg - read HW configuration registers
4865 * @hsotg: Programming view of the DWC_otg controller
4867 * Read the USB core HW configuration registers
4869 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
4875 /* check hardware configuration */
4877 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
4880 hsotg->num_of_eps++;
4882 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev,
4883 sizeof(struct dwc2_hsotg_ep),
4885 if (!hsotg->eps_in[0])
4887 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4888 hsotg->eps_out[0] = hsotg->eps_in[0];
4890 cfg = hsotg->hw_params.dev_ep_dirs;
4891 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
4893 /* Direction in or both */
4894 if (!(ep_type & 2)) {
4895 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
4896 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4897 if (!hsotg->eps_in[i])
4900 /* Direction out or both */
4901 if (!(ep_type & 1)) {
4902 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
4903 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
4904 if (!hsotg->eps_out[i])
4909 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
4910 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
4912 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4914 hsotg->dedicated_fifos ? "dedicated" : "shared",
4920 * dwc2_hsotg_dump - dump state of the udc
4921 * @hsotg: Programming view of the DWC_otg controller
4924 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
4927 struct device *dev = hsotg->dev;
4931 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4932 dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL),
4933 dwc2_readl(hsotg, DIEPMSK));
4935 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4936 dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1));
4938 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4939 dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ));
4941 /* show periodic fifo settings */
4943 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
4944 val = dwc2_readl(hsotg, DPTXFSIZN(idx));
4945 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
4946 val >> FIFOSIZE_DEPTH_SHIFT,
4947 val & FIFOSIZE_STARTADDR_MASK);
4950 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
4952 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
4953 dwc2_readl(hsotg, DIEPCTL(idx)),
4954 dwc2_readl(hsotg, DIEPTSIZ(idx)),
4955 dwc2_readl(hsotg, DIEPDMA(idx)));
4957 val = dwc2_readl(hsotg, DOEPCTL(idx));
4959 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4960 idx, dwc2_readl(hsotg, DOEPCTL(idx)),
4961 dwc2_readl(hsotg, DOEPTSIZ(idx)),
4962 dwc2_readl(hsotg, DOEPDMA(idx)));
4965 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4966 dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE));
4971 * dwc2_gadget_init - init function for gadget
4972 * @hsotg: Programming view of the DWC_otg controller
4975 int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
4977 struct device *dev = hsotg->dev;
4981 /* Dump fifo information */
4982 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
4983 hsotg->params.g_np_tx_fifo_size);
4984 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);
4986 switch (hsotg->params.speed) {
4987 case DWC2_SPEED_PARAM_LOW:
4988 hsotg->gadget.max_speed = USB_SPEED_LOW;
4990 case DWC2_SPEED_PARAM_FULL:
4991 hsotg->gadget.max_speed = USB_SPEED_FULL;
4994 hsotg->gadget.max_speed = USB_SPEED_HIGH;
4998 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
4999 hsotg->gadget.name = dev_name(dev);
5000 hsotg->gadget.otg_caps = &hsotg->params.otg_caps;
5001 hsotg->remote_wakeup_allowed = 0;
5003 if (hsotg->params.lpm)
5004 hsotg->gadget.lpm_capable = true;
5006 if (hsotg->dr_mode == USB_DR_MODE_OTG)
5007 hsotg->gadget.is_otg = 1;
5008 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
5009 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
5011 ret = dwc2_hsotg_hw_cfg(hsotg);
5013 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
5017 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
5018 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5019 if (!hsotg->ctrl_buff)
5022 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
5023 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
5024 if (!hsotg->ep0_buff)
5027 if (using_desc_dma(hsotg)) {
5028 ret = dwc2_gadget_alloc_ctrl_desc_chains(hsotg);
5033 ret = devm_request_irq(hsotg->dev, hsotg->irq, dwc2_hsotg_irq,
5034 IRQF_SHARED, dev_name(hsotg->dev), hsotg);
5036 dev_err(dev, "cannot claim IRQ for gadget\n");
5040 /* hsotg->num_of_eps holds number of EPs other than ep0 */
5042 if (hsotg->num_of_eps == 0) {
5043 dev_err(dev, "wrong number of EPs (zero)\n");
5047 /* setup endpoint information */
5049 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
5050 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
5052 /* allocate EP0 request */
5054 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
5056 if (!hsotg->ctrl_req) {
5057 dev_err(dev, "failed to allocate ctrl req\n");
5061 /* initialise the endpoints now the core has been initialised */
5062 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
5063 if (hsotg->eps_in[epnum])
5064 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
5066 if (hsotg->eps_out[epnum])
5067 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
5071 dwc2_hsotg_dump(hsotg);
5077 * dwc2_hsotg_remove - remove function for hsotg driver
5078 * @hsotg: Programming view of the DWC_otg controller
5081 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
5083 usb_del_gadget_udc(&hsotg->gadget);
5084 dwc2_hsotg_ep_free_request(&hsotg->eps_out[0]->ep, hsotg->ctrl_req);
5089 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
5091 unsigned long flags;
5093 if (hsotg->lx_state != DWC2_L0)
5096 if (hsotg->driver) {
5099 dev_info(hsotg->dev, "suspending usb gadget %s\n",
5100 hsotg->driver->driver.name);
5102 spin_lock_irqsave(&hsotg->lock, flags);
5104 dwc2_hsotg_core_disconnect(hsotg);
5105 dwc2_hsotg_disconnect(hsotg);
5106 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
5107 spin_unlock_irqrestore(&hsotg->lock, flags);
5109 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
5110 if (hsotg->eps_in[ep])
5111 dwc2_hsotg_ep_disable_lock(&hsotg->eps_in[ep]->ep);
5112 if (hsotg->eps_out[ep])
5113 dwc2_hsotg_ep_disable_lock(&hsotg->eps_out[ep]->ep);
5120 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
5122 unsigned long flags;
5124 if (hsotg->lx_state == DWC2_L2)
5127 if (hsotg->driver) {
5128 dev_info(hsotg->dev, "resuming usb gadget %s\n",
5129 hsotg->driver->driver.name);
5131 spin_lock_irqsave(&hsotg->lock, flags);
5132 dwc2_hsotg_core_init_disconnected(hsotg, false);
5133 if (hsotg->enabled) {
5134 /* Enable ACG feature in device mode,if supported */
5135 dwc2_enable_acg(hsotg);
5136 dwc2_hsotg_core_connect(hsotg);
5138 spin_unlock_irqrestore(&hsotg->lock, flags);
5145 * dwc2_backup_device_registers() - Backup controller device registers.
5146 * When suspending usb bus, registers needs to be backuped
5147 * if controller power is disabled once suspended.
5149 * @hsotg: Programming view of the DWC_otg controller
5151 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
5153 struct dwc2_dregs_backup *dr;
5156 dev_dbg(hsotg->dev, "%s\n", __func__);
5158 /* Backup dev regs */
5159 dr = &hsotg->dr_backup;
5161 dr->dcfg = dwc2_readl(hsotg, DCFG);
5162 dr->dctl = dwc2_readl(hsotg, DCTL);
5163 dr->daintmsk = dwc2_readl(hsotg, DAINTMSK);
5164 dr->diepmsk = dwc2_readl(hsotg, DIEPMSK);
5165 dr->doepmsk = dwc2_readl(hsotg, DOEPMSK);
5167 for (i = 0; i < hsotg->num_of_eps; i++) {
5169 dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i));
5171 /* Ensure DATA PID is correctly configured */
5172 if (dr->diepctl[i] & DXEPCTL_DPID)
5173 dr->diepctl[i] |= DXEPCTL_SETD1PID;
5175 dr->diepctl[i] |= DXEPCTL_SETD0PID;
5177 dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i));
5178 dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i));
5180 /* Backup OUT EPs */
5181 dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i));
5183 /* Ensure DATA PID is correctly configured */
5184 if (dr->doepctl[i] & DXEPCTL_DPID)
5185 dr->doepctl[i] |= DXEPCTL_SETD1PID;
5187 dr->doepctl[i] |= DXEPCTL_SETD0PID;
5189 dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i));
5190 dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i));
5191 dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i));
5198 * dwc2_restore_device_registers() - Restore controller device registers.
5199 * When resuming usb bus, device registers needs to be restored
5200 * if controller power were disabled.
5202 * @hsotg: Programming view of the DWC_otg controller
5203 * @remote_wakeup: Indicates whether resume is initiated by Device or Host.
5205 * Return: 0 if successful, negative error code otherwise
5207 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup)
5209 struct dwc2_dregs_backup *dr;
5212 dev_dbg(hsotg->dev, "%s\n", __func__);
5214 /* Restore dev regs */
5215 dr = &hsotg->dr_backup;
5217 dev_err(hsotg->dev, "%s: no device registers to restore\n",
5224 dwc2_writel(hsotg, dr->dctl, DCTL);
5226 dwc2_writel(hsotg, dr->daintmsk, DAINTMSK);
5227 dwc2_writel(hsotg, dr->diepmsk, DIEPMSK);
5228 dwc2_writel(hsotg, dr->doepmsk, DOEPMSK);
5230 for (i = 0; i < hsotg->num_of_eps; i++) {
5231 /* Restore IN EPs */
5232 dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i));
5233 dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i));
5234 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5235 /** WA for enabled EPx's IN in DDMA mode. On entering to
5236 * hibernation wrong value read and saved from DIEPDMAx,
5237 * as result BNA interrupt asserted on hibernation exit
5238 * by restoring from saved area.
5240 if (using_desc_dma(hsotg) &&
5241 (dr->diepctl[i] & DXEPCTL_EPENA))
5242 dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma;
5243 dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i));
5244 dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i));
5245 /* Restore OUT EPs */
5246 dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i));
5247 /* WA for enabled EPx's OUT in DDMA mode. On entering to
5248 * hibernation wrong value read and saved from DOEPDMAx,
5249 * as result BNA interrupt asserted on hibernation exit
5250 * by restoring from saved area.
5252 if (using_desc_dma(hsotg) &&
5253 (dr->doepctl[i] & DXEPCTL_EPENA))
5254 dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma;
5255 dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i));
5256 dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i));
5263 * dwc2_gadget_init_lpm - Configure the core to support LPM in device mode
5265 * @hsotg: Programming view of DWC_otg controller
5268 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
5272 if (!hsotg->params.lpm)
5275 val = GLPMCFG_LPMCAP | GLPMCFG_APPL1RES;
5276 val |= hsotg->params.hird_threshold_en ? GLPMCFG_HIRD_THRES_EN : 0;
5277 val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0;
5278 val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT;
5279 val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0;
5280 val |= GLPMCFG_LPM_REJECT_CTRL_CONTROL;
5281 val |= GLPMCFG_LPM_ACCEPT_CTRL_ISOC;
5282 dwc2_writel(hsotg, val, GLPMCFG);
5283 dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
5285 /* Unmask WKUP_ALERT Interrupt */
5286 if (hsotg->params.service_interval)
5287 dwc2_set_bit(hsotg, GINTMSK2, GINTMSK2_WKUP_ALERT_INT_MSK);
5291 * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
5293 * @hsotg: Programming view of DWC_otg controller
5296 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
5300 val |= GREFCLK_REF_CLK_MODE;
5301 val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
5302 val |= hsotg->params.sof_cnt_wkup_alert <<
5303 GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
5305 dwc2_writel(hsotg, val, GREFCLK);
5306 dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
5310 * dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
5312 * @hsotg: Programming view of the DWC_otg controller
5314 * Return non-zero if failed to enter to hibernation.
5316 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
5321 /* Change to L2(suspend) state */
5322 hsotg->lx_state = DWC2_L2;
5323 dev_dbg(hsotg->dev, "Start of hibernation completed\n");
5324 ret = dwc2_backup_global_registers(hsotg);
5326 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5330 ret = dwc2_backup_device_registers(hsotg);
5332 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5337 gpwrdn = GPWRDN_PWRDNRSTN;
5338 gpwrdn |= GPWRDN_PMUACTV;
5339 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5342 /* Set flag to indicate that we are in hibernation */
5343 hsotg->hibernated = 1;
5345 /* Enable interrupts from wake up logic */
5346 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5347 gpwrdn |= GPWRDN_PMUINTSEL;
5348 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5351 /* Unmask device mode interrupts in GPWRDN */
5352 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5353 gpwrdn |= GPWRDN_RST_DET_MSK;
5354 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5355 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5356 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5359 /* Enable Power Down Clamp */
5360 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5361 gpwrdn |= GPWRDN_PWRDNCLMP;
5362 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5365 /* Switch off VDD */
5366 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5367 gpwrdn |= GPWRDN_PWRDNSWTCH;
5368 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5371 /* Save gpwrdn register for further usage if stschng interrupt */
5372 hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN);
5373 dev_dbg(hsotg->dev, "Hibernation completed\n");
5379 * dwc2_gadget_exit_hibernation()
5380 * This function is for exiting from Device mode hibernation by host initiated
5381 * resume/reset and device initiated remote-wakeup.
5383 * @hsotg: Programming view of the DWC_otg controller
5384 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5385 * @reset: indicates whether resume is initiated by Reset.
5387 * Return non-zero if failed to exit from hibernation.
5389 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
5390 int rem_wakeup, int reset)
5396 struct dwc2_gregs_backup *gr;
5397 struct dwc2_dregs_backup *dr;
5399 gr = &hsotg->gr_backup;
5400 dr = &hsotg->dr_backup;
5402 if (!hsotg->hibernated) {
5403 dev_dbg(hsotg->dev, "Already exited from Hibernation\n");
5407 "%s: called with rem_wakeup = %d reset = %d\n",
5408 __func__, rem_wakeup, reset);
5410 dwc2_hib_restore_common(hsotg, rem_wakeup, 0);
5413 /* Clear all pending interupts */
5414 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5417 /* De-assert Restore */
5418 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5419 gpwrdn &= ~GPWRDN_RESTORE;
5420 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5424 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5425 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5426 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5429 /* Restore GUSBCFG, DCFG and DCTL */
5430 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5431 dwc2_writel(hsotg, dr->dcfg, DCFG);
5432 dwc2_writel(hsotg, dr->dctl, DCTL);
5434 /* On USB Reset, reset device address to zero */
5436 dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK);
5438 /* De-assert Wakeup Logic */
5439 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5440 gpwrdn &= ~GPWRDN_PMUACTV;
5441 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5445 /* Start Remote Wakeup Signaling */
5446 dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL);
5449 /* Set Device programming done bit */
5450 dctl = dwc2_readl(hsotg, DCTL);
5451 dctl |= DCTL_PWRONPRGDONE;
5452 dwc2_writel(hsotg, dctl, DCTL);
5454 /* Wait for interrupts which must be cleared */
5456 /* Clear all pending interupts */
5457 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5459 /* Restore global registers */
5460 ret = dwc2_restore_global_registers(hsotg);
5462 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5467 /* Restore device registers */
5468 ret = dwc2_restore_device_registers(hsotg, rem_wakeup);
5470 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5477 dctl = dwc2_readl(hsotg, DCTL);
5478 dctl &= ~DCTL_RMTWKUPSIG;
5479 dwc2_writel(hsotg, dctl, DCTL);
5482 hsotg->hibernated = 0;
5483 hsotg->lx_state = DWC2_L0;
5484 dev_dbg(hsotg->dev, "Hibernation recovery completes here\n");
5490 * dwc2_gadget_enter_partial_power_down() - Put controller in partial
5493 * @hsotg: Programming view of the DWC_otg controller
5495 * Return: non-zero if failed to enter device partial power down.
5497 * This function is for entering device mode partial power down.
5499 int dwc2_gadget_enter_partial_power_down(struct dwc2_hsotg *hsotg)
5504 dev_dbg(hsotg->dev, "Entering device partial power down started.\n");
5506 /* Backup all registers */
5507 ret = dwc2_backup_global_registers(hsotg);
5509 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5514 ret = dwc2_backup_device_registers(hsotg);
5516 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
5522 * Clear any pending interrupts since dwc2 will not be able to
5523 * clear them after entering partial_power_down.
5525 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5527 /* Put the controller in low power state */
5528 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5530 pcgcctl |= PCGCTL_PWRCLMP;
5531 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5534 pcgcctl |= PCGCTL_RSTPDWNMODULE;
5535 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5538 pcgcctl |= PCGCTL_STOPPCLK;
5539 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5541 /* Set in_ppd flag to 1 as here core enters suspend. */
5543 hsotg->lx_state = DWC2_L2;
5545 dev_dbg(hsotg->dev, "Entering device partial power down completed.\n");
5551 * dwc2_gadget_exit_partial_power_down() - Exit controller from device partial
5554 * @hsotg: Programming view of the DWC_otg controller
5555 * @restore: indicates whether need to restore the registers or not.
5557 * Return: non-zero if failed to exit device partial power down.
5559 * This function is for exiting from device mode partial power down.
5561 int dwc2_gadget_exit_partial_power_down(struct dwc2_hsotg *hsotg,
5566 struct dwc2_dregs_backup *dr;
5569 dr = &hsotg->dr_backup;
5571 dev_dbg(hsotg->dev, "Exiting device partial Power Down started.\n");
5573 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5574 pcgcctl &= ~PCGCTL_STOPPCLK;
5575 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5577 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5578 pcgcctl &= ~PCGCTL_PWRCLMP;
5579 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5581 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5582 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
5583 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5587 ret = dwc2_restore_global_registers(hsotg);
5589 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5594 dwc2_writel(hsotg, dr->dcfg, DCFG);
5596 ret = dwc2_restore_device_registers(hsotg, 0);
5598 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
5604 /* Set the Power-On Programming done bit */
5605 dctl = dwc2_readl(hsotg, DCTL);
5606 dctl |= DCTL_PWRONPRGDONE;
5607 dwc2_writel(hsotg, dctl, DCTL);
5609 /* Set in_ppd flag to 0 as here core exits from suspend. */
5611 hsotg->lx_state = DWC2_L0;
5613 dev_dbg(hsotg->dev, "Exiting device partial Power Down completed.\n");
5618 * dwc2_gadget_enter_clock_gating() - Put controller in clock gating.
5620 * @hsotg: Programming view of the DWC_otg controller
5622 * Return: non-zero if failed to enter device partial power down.
5624 * This function is for entering device mode clock gating.
5626 void dwc2_gadget_enter_clock_gating(struct dwc2_hsotg *hsotg)
5630 dev_dbg(hsotg->dev, "Entering device clock gating.\n");
5632 /* Set the Phy Clock bit as suspend is received. */
5633 pcgctl = dwc2_readl(hsotg, PCGCTL);
5634 pcgctl |= PCGCTL_STOPPCLK;
5635 dwc2_writel(hsotg, pcgctl, PCGCTL);
5638 /* Set the Gate hclk as suspend is received. */
5639 pcgctl = dwc2_readl(hsotg, PCGCTL);
5640 pcgctl |= PCGCTL_GATEHCLK;
5641 dwc2_writel(hsotg, pcgctl, PCGCTL);
5644 hsotg->lx_state = DWC2_L2;
5645 hsotg->bus_suspended = true;
5649 * dwc2_gadget_exit_clock_gating() - Exit controller from device clock gating.
5651 * @hsotg: Programming view of the DWC_otg controller
5652 * @rem_wakeup: indicates whether remote wake up is enabled.
5654 * This function is for exiting from device mode clock gating.
5656 void dwc2_gadget_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup)
5661 dev_dbg(hsotg->dev, "Exiting device clock gating.\n");
5663 /* Clear the Gate hclk. */
5664 pcgctl = dwc2_readl(hsotg, PCGCTL);
5665 pcgctl &= ~PCGCTL_GATEHCLK;
5666 dwc2_writel(hsotg, pcgctl, PCGCTL);
5669 /* Phy Clock bit. */
5670 pcgctl = dwc2_readl(hsotg, PCGCTL);
5671 pcgctl &= ~PCGCTL_STOPPCLK;
5672 dwc2_writel(hsotg, pcgctl, PCGCTL);
5676 /* Set Remote Wakeup Signaling */
5677 dctl = dwc2_readl(hsotg, DCTL);
5678 dctl |= DCTL_RMTWKUPSIG;
5679 dwc2_writel(hsotg, dctl, DCTL);
5682 /* Change to L0 state */
5683 call_gadget(hsotg, resume);
5684 hsotg->lx_state = DWC2_L0;
5685 hsotg->bus_suspended = false;