1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core_intr.c - DesignWare HS OTG Controller common interrupt handling
5 * Copyright (C) 2004-2013 Synopsys, Inc.
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8 * modification, are permitted provided that the following conditions
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20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * This file contains the common interrupt handlers
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/dma-mapping.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
57 static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
59 switch (hsotg->op_state) {
60 case OTG_STATE_A_HOST:
62 case OTG_STATE_A_SUSPEND:
64 case OTG_STATE_A_PERIPHERAL:
65 return "a_peripheral";
66 case OTG_STATE_B_PERIPHERAL:
67 return "b_peripheral";
68 case OTG_STATE_B_HOST:
76 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
77 * When the PRTINT interrupt fires, there are certain status bits in the Host
78 * Port that needs to get cleared.
80 * @hsotg: Programming view of DWC_otg controller
82 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
84 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
86 if (hprt0 & HPRT0_ENACHG) {
88 dwc2_writel(hsotg, hprt0, HPRT0);
93 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
95 * @hsotg: Programming view of DWC_otg controller
97 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
100 dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
102 dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
103 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
107 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
108 * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
110 * @hsotg: Programming view of DWC_otg controller
112 static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
118 gotgint = dwc2_readl(hsotg, GOTGINT);
119 gotgctl = dwc2_readl(hsotg, GOTGCTL);
120 dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
121 dwc2_op_state_str(hsotg));
123 if (gotgint & GOTGINT_SES_END_DET) {
125 " ++OTG Interrupt: Session End Detected++ (%s)\n",
126 dwc2_op_state_str(hsotg));
127 gotgctl = dwc2_readl(hsotg, GOTGCTL);
129 if (dwc2_is_device_mode(hsotg))
130 dwc2_hsotg_disconnect(hsotg);
132 if (hsotg->op_state == OTG_STATE_B_HOST) {
133 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
136 * If not B_HOST and Device HNP still set, HNP did
139 if (gotgctl & GOTGCTL_DEVHNPEN) {
140 dev_dbg(hsotg->dev, "Session End Detected\n");
142 "Device Not Connected/Responding!\n");
146 * If Session End Detected the B-Cable has been
149 /* Reset to a clean state */
150 hsotg->lx_state = DWC2_L0;
153 gotgctl = dwc2_readl(hsotg, GOTGCTL);
154 gotgctl &= ~GOTGCTL_DEVHNPEN;
155 dwc2_writel(hsotg, gotgctl, GOTGCTL);
158 if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
160 " ++OTG Interrupt: Session Request Success Status Change++\n");
161 gotgctl = dwc2_readl(hsotg, GOTGCTL);
162 if (gotgctl & GOTGCTL_SESREQSCS) {
163 if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
164 hsotg->params.i2c_enable) {
165 hsotg->srp_success = 1;
167 /* Clear Session Request */
168 gotgctl = dwc2_readl(hsotg, GOTGCTL);
169 gotgctl &= ~GOTGCTL_SESREQ;
170 dwc2_writel(hsotg, gotgctl, GOTGCTL);
175 if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
177 * Print statements during the HNP interrupt handling
178 * can cause it to fail
180 gotgctl = dwc2_readl(hsotg, GOTGCTL);
182 * WA for 3.00a- HW is not setting cur_mode, even sometimes
185 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
187 if (gotgctl & GOTGCTL_HSTNEGSCS) {
188 if (dwc2_is_host_mode(hsotg)) {
189 hsotg->op_state = OTG_STATE_B_HOST;
191 * Need to disable SOF interrupt immediately.
192 * When switching from device to host, the PCD
193 * interrupt handler won't handle the interrupt
194 * if host mode is already set. The HCD
195 * interrupt handler won't get called if the
196 * HCD state is HALT. This means that the
197 * interrupt does not get handled and Linux
200 gintmsk = dwc2_readl(hsotg, GINTMSK);
201 gintmsk &= ~GINTSTS_SOF;
202 dwc2_writel(hsotg, gintmsk, GINTMSK);
205 * Call callback function with spin lock
208 spin_unlock(&hsotg->lock);
210 /* Initialize the Core for Host mode */
211 dwc2_hcd_start(hsotg);
212 spin_lock(&hsotg->lock);
213 hsotg->op_state = OTG_STATE_B_HOST;
216 gotgctl = dwc2_readl(hsotg, GOTGCTL);
217 gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
218 dwc2_writel(hsotg, gotgctl, GOTGCTL);
219 dev_dbg(hsotg->dev, "HNP Failed\n");
221 "Device Not Connected/Responding\n");
225 if (gotgint & GOTGINT_HST_NEG_DET) {
227 * The disconnect interrupt is set at the same time as
228 * Host Negotiation Detected. During the mode switch all
229 * interrupts are cleared so the disconnect interrupt
230 * handler will not get executed.
233 " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
234 (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
235 if (dwc2_is_device_mode(hsotg)) {
236 dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
238 spin_unlock(&hsotg->lock);
239 dwc2_hcd_disconnect(hsotg, false);
240 spin_lock(&hsotg->lock);
241 hsotg->op_state = OTG_STATE_A_PERIPHERAL;
243 /* Need to disable SOF interrupt immediately */
244 gintmsk = dwc2_readl(hsotg, GINTMSK);
245 gintmsk &= ~GINTSTS_SOF;
246 dwc2_writel(hsotg, gintmsk, GINTMSK);
247 spin_unlock(&hsotg->lock);
248 dwc2_hcd_start(hsotg);
249 spin_lock(&hsotg->lock);
250 hsotg->op_state = OTG_STATE_A_HOST;
254 if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
256 " ++OTG Interrupt: A-Device Timeout Change++\n");
257 if (gotgint & GOTGINT_DBNCE_DONE)
258 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
261 dwc2_writel(hsotg, gotgint, GOTGINT);
265 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
268 * @hsotg: Programming view of DWC_otg controller
270 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
271 * Device to Host Mode transition or a Host to Device Mode transition. This only
272 * occurs when the cable is connected/removed from the PHY connector.
274 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
278 /* Clear interrupt */
279 dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
281 /* Need to disable SOF interrupt immediately */
282 gintmsk = dwc2_readl(hsotg, GINTMSK);
283 gintmsk &= ~GINTSTS_SOF;
284 dwc2_writel(hsotg, gintmsk, GINTMSK);
286 dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
287 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
290 * Need to schedule a work, as there are possible DELAY function calls.
293 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
297 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
298 * initiating the Session Request Protocol to request the host to turn on bus
299 * power so a new session can begin
301 * @hsotg: Programming view of DWC_otg controller
303 * This handler responds by turning on bus power. If the DWC_otg controller is
304 * in low power mode, this handler brings the controller out of low power mode
305 * before turning on bus power.
307 static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
312 /* Clear interrupt */
313 dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
315 dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
318 if (dwc2_is_device_mode(hsotg)) {
319 if (hsotg->lx_state == DWC2_L2) {
320 ret = dwc2_exit_partial_power_down(hsotg, true);
321 if (ret && (ret != -ENOTSUPP))
323 "exit power_down failed\n");
327 * Report disconnect if there is any previous session
330 dwc2_hsotg_disconnect(hsotg);
332 /* Turn on the port power bit. */
333 hprt0 = dwc2_read_hprt0(hsotg);
335 dwc2_writel(hsotg, hprt0, HPRT0);
336 /* Connect hcd after port power is set. */
337 dwc2_hcd_connect(hsotg);
342 * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state
344 * @hsotg: Programming view of DWC_otg controller
347 void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg, bool remotewakeup)
353 if (hsotg->lx_state != DWC2_L1) {
354 dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n");
358 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
359 if (dwc2_is_device_mode(hsotg)) {
360 dev_dbg(hsotg->dev, "Exit from L1 state, remotewakeup=%d\n", remotewakeup);
361 glpmcfg &= ~GLPMCFG_ENBLSLPM;
362 glpmcfg &= ~GLPMCFG_HIRD_THRES_MASK;
363 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
365 pcgctl = dwc2_readl(hsotg, PCGCTL);
366 pcgctl &= ~PCGCTL_ENBL_SLEEP_GATING;
367 dwc2_writel(hsotg, pcgctl, PCGCTL);
369 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
370 if (glpmcfg & GLPMCFG_ENBESL) {
371 glpmcfg |= GLPMCFG_RSTRSLPSTS;
372 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
376 if (dwc2_hsotg_wait_bit_set(hsotg, GLPMCFG, GLPMCFG_L1RESUMEOK, 1000)) {
377 dev_warn(hsotg->dev, "%s: timeout GLPMCFG_L1RESUMEOK\n", __func__);
382 dctl = dwc2_readl(hsotg, DCTL);
383 dctl |= DCTL_RMTWKUPSIG;
384 dwc2_writel(hsotg, dctl, DCTL);
386 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_WKUPINT, 1000)) {
387 dev_warn(hsotg->dev, "%s: timeout GINTSTS_WKUPINT\n", __func__);
393 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
394 if (glpmcfg & GLPMCFG_COREL1RES_MASK || glpmcfg & GLPMCFG_SLPSTS ||
395 glpmcfg & GLPMCFG_L1RESUMEOK) {
400 /* Inform gadget to exit from L1 */
401 call_gadget(hsotg, resume);
402 /* Change to L0 state */
403 hsotg->lx_state = DWC2_L0;
404 hsotg->bus_suspended = false;
405 fail: dwc2_gadget_init_lpm(hsotg);
408 dev_err(hsotg->dev, "Host side LPM is not supported.\n");
414 * This interrupt indicates that the DWC_otg controller has detected a
415 * resume or remote wakeup sequence. If the DWC_otg controller is in
416 * low power mode, the handler must brings the controller out of low
417 * power mode. The controller automatically begins resume signaling.
418 * The handler schedules a time to stop resume signaling.
420 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
424 /* Clear interrupt */
425 dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
427 dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
428 dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
430 if (hsotg->lx_state == DWC2_L1) {
431 dwc2_wakeup_from_lpm_l1(hsotg, false);
435 if (dwc2_is_device_mode(hsotg)) {
436 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
437 dwc2_readl(hsotg, DSTS));
438 if (hsotg->lx_state == DWC2_L2) {
439 u32 dctl = dwc2_readl(hsotg, DCTL);
441 /* Clear Remote Wakeup Signaling */
442 dctl &= ~DCTL_RMTWKUPSIG;
443 dwc2_writel(hsotg, dctl, DCTL);
444 ret = dwc2_exit_partial_power_down(hsotg, true);
445 if (ret && (ret != -ENOTSUPP))
446 dev_err(hsotg->dev, "exit power_down failed\n");
448 /* Change to L0 state */
449 hsotg->lx_state = DWC2_L0;
450 call_gadget(hsotg, resume);
452 /* Change to L0 state */
453 hsotg->lx_state = DWC2_L0;
456 if (hsotg->params.power_down)
459 if (hsotg->lx_state != DWC2_L1) {
460 u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
462 /* Restart the Phy Clock */
463 pcgcctl &= ~PCGCTL_STOPPCLK;
464 dwc2_writel(hsotg, pcgcctl, PCGCTL);
467 * If we've got this quirk then the PHY is stuck upon
468 * wakeup. Assert reset. This will propagate out and
469 * eventually we'll re-enumerate the device. Not great
470 * but the best we can do. We can't call phy_reset()
471 * at interrupt time but there's no hurry, so we'll
472 * schedule it for later.
474 if (hsotg->reset_phy_on_wake)
475 dwc2_host_schedule_phy_reset(hsotg);
477 mod_timer(&hsotg->wkp_timer,
478 jiffies + msecs_to_jiffies(71));
480 /* Change to L0 state */
481 hsotg->lx_state = DWC2_L0;
487 * This interrupt indicates that a device has been disconnected from the
490 static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
492 dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
494 dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
495 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
496 dwc2_op_state_str(hsotg));
498 if (hsotg->op_state == OTG_STATE_A_HOST)
499 dwc2_hcd_disconnect(hsotg, false);
503 * This interrupt indicates that SUSPEND state has been detected on the USB.
505 * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
508 * When power management is enabled the core will be put in low power mode.
510 static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
515 /* Clear interrupt */
516 dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
518 dev_dbg(hsotg->dev, "USB SUSPEND\n");
520 if (dwc2_is_device_mode(hsotg)) {
522 * Check the Device status register to determine if the Suspend
525 dsts = dwc2_readl(hsotg, DSTS);
526 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
528 "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
529 !!(dsts & DSTS_SUSPSTS),
530 hsotg->hw_params.power_optimized,
531 hsotg->hw_params.hibernation);
533 /* Ignore suspend request before enumeration */
534 if (!dwc2_is_device_connected(hsotg)) {
536 "ignore suspend request before enumeration\n");
539 if (dsts & DSTS_SUSPSTS) {
540 if (hsotg->hw_params.power_optimized) {
541 ret = dwc2_enter_partial_power_down(hsotg);
543 if (ret != -ENOTSUPP)
545 "%s: enter partial_power_down failed\n",
547 goto skip_power_saving;
552 /* Ask phy to be suspended */
553 if (!IS_ERR_OR_NULL(hsotg->uphy))
554 usb_phy_set_suspend(hsotg->uphy, true);
557 if (hsotg->hw_params.hibernation) {
558 ret = dwc2_enter_hibernation(hsotg, 0);
559 if (ret && ret != -ENOTSUPP)
561 "%s: enter hibernation failed\n",
566 * Change to L2 (suspend) state before releasing
569 hsotg->lx_state = DWC2_L2;
571 /* Call gadget suspend callback */
572 call_gadget(hsotg, suspend);
575 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
576 dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
578 /* Change to L2 (suspend) state */
579 hsotg->lx_state = DWC2_L2;
580 /* Clear the a_peripheral flag, back to a_host */
581 spin_unlock(&hsotg->lock);
582 dwc2_hcd_start(hsotg);
583 spin_lock(&hsotg->lock);
584 hsotg->op_state = OTG_STATE_A_HOST;
590 * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
592 * @hsotg: Programming view of DWC_otg controller
595 static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
604 /* Clear interrupt */
605 dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
607 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
609 if (!(glpmcfg & GLPMCFG_LPMCAP)) {
610 dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
614 hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT;
615 hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK &
616 ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT;
617 hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN;
618 enslpm = glpmcfg & GLPMCFG_ENBLSLPM;
620 if (dwc2_is_device_mode(hsotg)) {
621 dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en);
623 if (hird_thres_en && hird >= hird_thres) {
624 dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n");
626 dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
628 dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
630 pcgcctl = dwc2_readl(hsotg, PCGCTL);
631 pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
632 dwc2_writel(hsotg, pcgcctl, PCGCTL);
635 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
639 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
641 if (glpmcfg & GLPMCFG_SLPSTS) {
642 /* Save the current state */
643 hsotg->lx_state = DWC2_L1;
645 "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg);
647 /* Inform gadget that we are in L1 state */
648 call_gadget(hsotg, suspend);
653 #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
654 GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
655 GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
656 GINTSTS_USBSUSP | GINTSTS_PRTINT | \
660 * This function returns the Core Interrupt register
662 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
667 u32 gintmsk_common = GINTMSK_COMMON;
669 gintsts = dwc2_readl(hsotg, GINTSTS);
670 gintmsk = dwc2_readl(hsotg, GINTMSK);
671 gahbcfg = dwc2_readl(hsotg, GAHBCFG);
673 /* If any common interrupts set */
674 if (gintsts & gintmsk_common)
675 dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
678 if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
679 return gintsts & gintmsk & gintmsk_common;
685 * dwc_handle_gpwrdn_disc_det() - Handles the gpwrdn disconnect detect.
686 * Exits hibernation without restoring registers.
688 * @hsotg: Programming view of DWC_otg controller
689 * @gpwrdn: GPWRDN register
691 static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
696 /* Switch-on voltage to the core */
697 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
698 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
699 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
703 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
704 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
705 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
708 /* Disable Power Down Clamp */
709 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
710 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
711 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
714 /* Deassert reset core */
715 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
716 gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
717 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
720 /* Disable PMU interrupt */
721 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
722 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
723 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
725 /* De-assert Wakeup Logic */
726 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
727 gpwrdn_tmp &= ~GPWRDN_PMUACTV;
728 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
730 hsotg->hibernated = 0;
732 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
733 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
734 hsotg->bus_suspended = 0;
737 if (gpwrdn & GPWRDN_IDSTS) {
738 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
739 dwc2_core_init(hsotg, false);
740 dwc2_enable_global_interrupts(hsotg);
741 dwc2_hsotg_core_init_disconnected(hsotg, false);
742 dwc2_hsotg_core_connect(hsotg);
744 hsotg->op_state = OTG_STATE_A_HOST;
746 /* Initialize the Core for Host mode */
747 dwc2_core_init(hsotg, false);
748 dwc2_enable_global_interrupts(hsotg);
749 dwc2_hcd_start(hsotg);
754 * GPWRDN interrupt handler.
756 * The GPWRDN interrupts are those that occur in both Host and
757 * Device mode while core is in hibernated state.
759 static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
764 gpwrdn = dwc2_readl(hsotg, GPWRDN);
765 /* clear all interrupt */
766 dwc2_writel(hsotg, gpwrdn, GPWRDN);
767 linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
769 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
772 if ((gpwrdn & GPWRDN_DISCONN_DET) &&
773 (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
774 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
776 * Call disconnect detect function to exit from
779 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
780 } else if ((gpwrdn & GPWRDN_LNSTSCHG) &&
781 (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
782 dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
783 if (hsotg->hw_params.hibernation &&
785 if (gpwrdn & GPWRDN_IDSTS) {
786 dwc2_exit_hibernation(hsotg, 0, 0, 0);
787 call_gadget(hsotg, resume);
789 dwc2_exit_hibernation(hsotg, 1, 0, 1);
792 } else if ((gpwrdn & GPWRDN_RST_DET) &&
793 (gpwrdn & GPWRDN_RST_DET_MSK)) {
794 dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
795 if (!linestate && (gpwrdn & GPWRDN_BSESSVLD))
796 dwc2_exit_hibernation(hsotg, 0, 1, 0);
797 } else if ((gpwrdn & GPWRDN_STS_CHGINT) &&
798 (gpwrdn & GPWRDN_STS_CHGINT_MSK)) {
799 dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
801 * As GPWRDN_STS_CHGINT exit from hibernation flow is
802 * the same as in GPWRDN_DISCONN_DET flow. Call
803 * disconnect detect helper function to exit from
806 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
811 * Common interrupt handler
813 * The common interrupts are those that occur in both Host and Device mode.
814 * This handler handles the following interrupts:
815 * - Mode Mismatch Interrupt
817 * - Connector ID Status Change Interrupt
818 * - Disconnect Interrupt
819 * - Session Request Interrupt
820 * - Resume / Remote Wakeup Detected Interrupt
821 * - Suspend Interrupt
823 irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
825 struct dwc2_hsotg *hsotg = dev;
827 irqreturn_t retval = IRQ_NONE;
829 spin_lock(&hsotg->lock);
831 if (!dwc2_is_controller_alive(hsotg)) {
832 dev_warn(hsotg->dev, "Controller is dead\n");
836 /* Reading current frame number value in device or host modes. */
837 if (dwc2_is_device_mode(hsotg))
838 hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
839 & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
841 hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
842 & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
844 gintsts = dwc2_read_common_intr(hsotg);
845 if (gintsts & ~GINTSTS_PRTINT)
846 retval = IRQ_HANDLED;
848 /* In case of hibernated state gintsts must not work */
849 if (hsotg->hibernated) {
850 dwc2_handle_gpwrdn_intr(hsotg);
851 retval = IRQ_HANDLED;
855 if (gintsts & GINTSTS_MODEMIS)
856 dwc2_handle_mode_mismatch_intr(hsotg);
857 if (gintsts & GINTSTS_OTGINT)
858 dwc2_handle_otg_intr(hsotg);
859 if (gintsts & GINTSTS_CONIDSTSCHNG)
860 dwc2_handle_conn_id_status_change_intr(hsotg);
861 if (gintsts & GINTSTS_DISCONNINT)
862 dwc2_handle_disconnect_intr(hsotg);
863 if (gintsts & GINTSTS_SESSREQINT)
864 dwc2_handle_session_req_intr(hsotg);
865 if (gintsts & GINTSTS_WKUPINT)
866 dwc2_handle_wakeup_detected_intr(hsotg);
867 if (gintsts & GINTSTS_USBSUSP)
868 dwc2_handle_usb_suspend_intr(hsotg);
869 if (gintsts & GINTSTS_LPMTRANRCVD)
870 dwc2_handle_lpm_intr(hsotg);
872 if (gintsts & GINTSTS_PRTINT) {
874 * The port interrupt occurs while in device mode with HPRT0
875 * Port Enable/Disable
877 if (dwc2_is_device_mode(hsotg)) {
879 " --Port interrupt received in Device mode--\n");
880 dwc2_handle_usb_port_intr(hsotg);
881 retval = IRQ_HANDLED;
886 spin_unlock(&hsotg->lock);