1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * core.h - DesignWare HS OTG Controller common declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
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38 #ifndef __DWC2_CORE_H__
39 #define __DWC2_CORE_H__
41 #include <linux/phy/phy.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/usb/gadget.h>
44 #include <linux/usb/otg.h>
45 #include <linux/usb/phy.h>
49 * Suggested defines for tracers:
50 * - no_printk: Disable tracing
51 * - pr_info: Print this info to the console
52 * - trace_printk: Print this info to trace buffer (good for verbose logging)
55 #define DWC2_TRACE_SCHEDULER no_printk
56 #define DWC2_TRACE_SCHEDULER_VB no_printk
58 /* Detailed scheduler tracing, but won't overwhelm console */
59 #define dwc2_sch_dbg(hsotg, fmt, ...) \
60 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
61 dev_name(hsotg->dev), ##__VA_ARGS__)
63 /* Verbose scheduler tracing */
64 #define dwc2_sch_vdbg(hsotg, fmt, ...) \
65 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
66 dev_name(hsotg->dev), ##__VA_ARGS__)
68 /* Maximum number of Endpoints/HostChannels */
69 #define MAX_EPS_CHANNELS 16
71 /* dwc2-hsotg declarations */
72 static const char * const dwc2_hsotg_supply_names[] = {
73 "vusb_d", /* digital USB supply, 1.2V */
74 "vusb_a", /* analog USB supply, 1.1V */
77 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
82 * Unfortunately there seems to be a limit of the amount of data that can
83 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
84 * packets (which practically means 1 packet and 63 bytes of data) when the
87 * This means if we are wanting to move >127 bytes of data, we need to
88 * split the transactions up, but just doing one packet at a time does
89 * not work (this may be an implicit DATA0 PID on first packet of the
90 * transaction) and doing 2 packets is outside the controller's limits.
92 * If we try to lower the MPS size for EP0, then no transfers work properly
93 * for EP0, and the system will fail basic enumeration. As no cause for this
94 * has currently been found, we cannot support any large IN transfers for
97 #define EP0_MPS_LIMIT 64
100 struct dwc2_hsotg_req;
103 * struct dwc2_hsotg_ep - driver endpoint definition.
104 * @ep: The gadget layer representation of the endpoint.
105 * @name: The driver generated name for the endpoint.
106 * @queue: Queue of requests for this endpoint.
107 * @parent: Reference back to the parent device structure.
108 * @req: The current request that the endpoint is processing. This is
109 * used to indicate an request has been loaded onto the endpoint
110 * and has yet to be completed (maybe due to data move, or simply
111 * awaiting an ack from the core all the data has been completed).
112 * @debugfs: File entry for debugfs file for this endpoint.
113 * @dir_in: Set to true if this endpoint is of the IN direction, which
114 * means that it is sending data to the Host.
115 * @map_dir: Set to the value of dir_in when the DMA buffer is mapped.
116 * @index: The index for the endpoint registers.
117 * @mc: Multi Count - number of transactions per microframe
118 * @interval: Interval for periodic endpoints, in frames or microframes.
119 * @name: The name array passed to the USB core.
120 * @halted: Set if the endpoint has been halted.
121 * @periodic: Set if this is a periodic ep, such as Interrupt
122 * @isochronous: Set if this is a isochronous ep
123 * @send_zlp: Set if we need to send a zero-length packet.
124 * @desc_list_dma: The DMA address of descriptor chain currently in use.
125 * @desc_list: Pointer to descriptor DMA chain head currently in use.
126 * @desc_count: Count of entries within the DMA descriptor chain of EP.
127 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
128 * @compl_desc: index of next descriptor to be completed by xFerComplete
129 * @total_data: The total number of data bytes done.
130 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
131 * @fifo_index: For Dedicated FIFO operation, only FIFO0 can be used for EP0.
132 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
133 * @last_load: The offset of data for the last start of request.
134 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
135 * @target_frame: Targeted frame num to setup next ISOC transfer
136 * @frame_overrun: Indicates SOF number overrun in DSTS
138 * This is the driver's state for each registered endpoint, allowing it
139 * to keep track of transactions that need doing. Each endpoint has a
140 * lock to protect the state, to try and avoid using an overall lock
141 * for the host controller as much as possible.
143 * For periodic IN endpoints, we have fifo_size and fifo_load to try
144 * and keep track of the amount of data in the periodic FIFO for each
145 * of these as we don't have a status register that tells us how much
146 * is in each of them. (note, this may actually be useless information
147 * as in shared-fifo mode periodic in acts like a single-frame packet
148 * buffer than a fifo)
150 struct dwc2_hsotg_ep {
152 struct list_head queue;
153 struct dwc2_hsotg *parent;
154 struct dwc2_hsotg_req *req;
155 struct dentry *debugfs;
157 unsigned long total_data;
158 unsigned int size_loaded;
159 unsigned int last_load;
160 unsigned int fifo_load;
161 unsigned short fifo_size;
162 unsigned short fifo_index;
164 unsigned char dir_in;
165 unsigned char map_dir;
170 unsigned int halted:1;
171 unsigned int periodic:1;
172 unsigned int isochronous:1;
173 unsigned int send_zlp:1;
174 unsigned int target_frame;
175 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
178 dma_addr_t desc_list_dma;
179 struct dwc2_dma_desc *desc_list;
182 unsigned int next_desc;
183 unsigned int compl_desc;
189 * struct dwc2_hsotg_req - data transfer request
190 * @req: The USB gadget request
191 * @queue: The list of requests for the endpoint this is queued for.
192 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
194 struct dwc2_hsotg_req {
195 struct usb_request req;
196 struct list_head queue;
200 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
201 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
202 #define call_gadget(_hs, _entry) \
204 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
205 (_hs)->driver && (_hs)->driver->_entry) { \
206 spin_unlock(&_hs->lock); \
207 (_hs)->driver->_entry(&(_hs)->gadget); \
208 spin_lock(&_hs->lock); \
212 #define call_gadget(_hs, _entry) do {} while (0)
216 struct dwc2_host_chan;
220 DWC2_L0, /* On state */
221 DWC2_L1, /* LPM sleep state */
222 DWC2_L2, /* USB suspend state */
223 DWC2_L3, /* Off state */
226 /* Gadget ep0 states */
227 enum dwc2_ep0_state {
236 * struct dwc2_core_params - Parameters for configuring the core
238 * @otg_cap: Specifies the OTG capabilities.
239 * 0 - HNP and SRP capable
240 * 1 - SRP Only capable
241 * 2 - No HNP/SRP capable (always available)
242 * Defaults to best available option (0, 1, then 2)
243 * @host_dma: Specifies whether to use slave or DMA mode for accessing
244 * the data FIFOs. The driver will automatically detect the
245 * value for this parameter if none is specified.
246 * 0 - Slave (always available)
247 * 1 - DMA (default, if available)
248 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
249 * address DMA mode or descriptor DMA mode for accessing
250 * the data FIFOs. The driver will automatically detect the
251 * value for this if none is specified.
253 * 1 - Descriptor DMA (default, if available)
254 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
255 * address DMA mode or descriptor DMA mode for accessing
256 * the data FIFOs in Full Speed mode only. The driver
257 * will automatically detect the value for this if none is
260 * 1 - Descriptor DMA in FS (default, if available)
261 * @speed: Specifies the maximum speed of operation in host and
262 * device mode. The actual speed depends on the speed of
263 * the attached device and the value of phy_type.
265 * (default when phy_type is UTMI+ or ULPI)
267 * (default when phy_type is Full Speed)
268 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
269 * 1 - Allow dynamic FIFO sizing (default, if available)
270 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
271 * are enabled for non-periodic IN endpoints in device
273 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
274 * dynamic FIFO sizing is enabled
276 * Actual maximum value is autodetected and also
278 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
279 * in host mode when dynamic FIFO sizing is enabled
281 * Actual maximum value is autodetected and also
283 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
284 * host mode when dynamic FIFO sizing is enabled
286 * Actual maximum value is autodetected and also
288 * @max_transfer_size: The maximum transfer size supported, in bytes
290 * Actual maximum value is autodetected and also
292 * @max_packet_count: The maximum number of packets in a transfer
294 * Actual maximum value is autodetected and also
296 * @host_channels: The number of host channel registers to use
298 * Actual maximum value is autodetected and also
300 * @phy_type: Specifies the type of PHY interface to use. By default,
301 * the driver will automatically detect the phy_type.
305 * Defaults to best available option (2, 1, then 0)
306 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
307 * is applicable for a phy_type of UTMI+ or ULPI. (For a
308 * ULPI phy_type, this parameter indicates the data width
309 * between the MAC and the ULPI Wrapper.) Also, this
310 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
311 * parameter was set to "8 and 16 bits", meaning that the
312 * core has been configured to work at either data path
314 * 8 or 16 (default 16 if available)
315 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
316 * data rate. This parameter is only applicable if phy_type
318 * 0 - single data rate ULPI interface with 8 bit wide
320 * 1 - double data rate ULPI interface with 4 bit wide
322 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
323 * external supply to drive the VBus
324 * 0 - Internal supply (default)
325 * 1 - External supply
326 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
327 * speed PHY. This parameter is only applicable if phy_type
331 * @ipg_isoc_en: Indicates the IPG supports is enabled or disabled.
332 * 0 - Disable (default)
334 * @acg_enable: For enabling Active Clock Gating in the controller
337 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
340 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
341 * when attached to a Full Speed or Low Speed device in
343 * 0 - Don't support low power mode (default)
344 * 1 - Support low power mode
345 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
346 * when connected to a Low Speed device in host
347 * mode. This parameter is applicable only if
348 * host_support_fs_ls_low_power is enabled.
350 * (default when phy_type is UTMI+ or ULPI)
352 * (default when phy_type is Full Speed)
353 * @oc_disable: Flag to disable overcurrent condition.
354 * 0 - Allow overcurrent condition to get detected
355 * 1 - Disable overcurrent condtion to get detected
356 * @ts_dline: Enable Term Select Dline pulsing
359 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
360 * 0 - No (default for core < 2.92a)
361 * 1 - Yes (default for core >= 2.92a)
362 * @ahbcfg: This field allows the default value of the GAHBCFG
363 * register to be overridden
364 * -1 - GAHBCFG value will be set to 0x06
366 * all others - GAHBCFG value will be overridden with
368 * Not all bits can be controlled like this, the
369 * bits defined by GAHBCFG_CTRL_MASK are controlled
370 * by the driver and are ignored in this
371 * configuration value.
372 * @uframe_sched: True to enable the microframe scheduler
373 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
374 * Disable CONIDSTSCHNG controller interrupt in such
378 * @power_down: Specifies whether the controller support power_down.
379 * If power_down is enabled, the controller will enter
380 * power_down in both peripheral and host mode when
383 * 1 - Partial power down
385 * @lpm: Enable LPM support.
388 * @lpm_clock_gating: Enable core PHY clock gating.
391 * @besl: Enable LPM Errata support.
394 * @hird_threshold_en: HIRD or HIRD Threshold enable.
397 * @hird_threshold: Value of BESL or HIRD Threshold.
398 * @ref_clk_per: Indicates in terms of pico seconds the period
405 * 33333 - 30MHz (default)
407 * @sof_cnt_wkup_alert: Indicates in term of number of SOF's after which
408 * the controller should generate an interrupt if the
409 * device had been in L1 state until that period.
410 * This is used by SW to initiate Remote WakeUp in the
411 * controller so as to sync to the uF number from the host.
412 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
414 * 0 - Deactivate the transceiver (default)
415 * 1 - Activate the transceiver
416 * @activate_stm_id_vb_detection: Activate external ID pin and Vbus level
417 * detection using GGPIO register.
418 * 0 - Deactivate the external level detection (default)
419 * 1 - Activate the external level detection
420 * @g_dma: Enables gadget dma usage (default: autodetect).
421 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
422 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
423 * DWORDS from 16-32768 (default: 2048 if
424 * possible, otherwise autodetect).
425 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
426 * DWORDS from 16-32768 (default: 1024 if
427 * possible, otherwise autodetect).
428 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
429 * mode. Each value corresponds to one EP
430 * starting from EP1 (max 15 values). Sizes are
431 * in DWORDS with possible values from from
432 * 16-32768 (default: 256, 256, 256, 256, 768,
433 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
434 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
435 * while full&low speed device connect. And change speed
436 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
439 * @service_interval: Enable service interval based scheduling.
443 * The following parameters may be specified when starting the module. These
444 * parameters define how the DWC_otg controller should be configured. A
445 * value of -1 (or any other out of range value) for any parameter means
446 * to read the value from hardware (if possible) or use the builtin
447 * default described above.
449 struct dwc2_core_params {
451 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
452 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
453 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
456 #define DWC2_PHY_TYPE_PARAM_FS 0
457 #define DWC2_PHY_TYPE_PARAM_UTMI 1
458 #define DWC2_PHY_TYPE_PARAM_ULPI 2
461 #define DWC2_SPEED_PARAM_HIGH 0
462 #define DWC2_SPEED_PARAM_FULL 1
463 #define DWC2_SPEED_PARAM_LOW 2
467 bool phy_ulpi_ext_vbus;
468 bool enable_dynamic_fifo;
469 bool en_multiple_tx_fifo;
476 bool external_id_pin_ctl;
479 #define DWC2_POWER_DOWN_PARAM_NONE 0
480 #define DWC2_POWER_DOWN_PARAM_PARTIAL 1
481 #define DWC2_POWER_DOWN_PARAM_HIBERNATION 2
484 bool lpm_clock_gating;
486 bool hird_threshold_en;
487 bool service_interval;
489 bool activate_stm_fs_transceiver;
490 bool activate_stm_id_vb_detection;
492 u16 max_packet_count;
493 u32 max_transfer_size;
496 /* GREFCLK parameters */
498 u16 sof_cnt_wkup_alert;
500 /* Host parameters */
502 bool dma_desc_enable;
503 bool dma_desc_fs_enable;
504 bool host_support_fs_ls_low_power;
505 bool host_ls_low_power_phy_clk;
509 u16 host_rx_fifo_size;
510 u16 host_nperio_tx_fifo_size;
511 u16 host_perio_tx_fifo_size;
513 /* Gadget parameters */
517 u32 g_np_tx_fifo_size;
518 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
520 bool change_speed_quirk;
524 * struct dwc2_hw_params - Autodetected parameters.
526 * These parameters are the various parameters read from hardware
527 * registers during initialization. They typically contain the best
528 * supported or maximum value that can be configured in the
529 * corresponding dwc2_core_params value.
531 * The values that are not in dwc2_core_params are documented below.
533 * @op_mode: Mode of Operation
534 * 0 - HNP- and SRP-Capable OTG (Host & Device)
535 * 1 - SRP-Capable OTG (Host & Device)
536 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
537 * 3 - SRP-Capable Device
539 * 5 - SRP-Capable Host
541 * @arch: Architecture
545 * @ipg_isoc_en: This feature indicates that the controller supports
546 * the worst-case scenario of Rx followed by Rx
547 * Interpacket Gap (IPG) (32 bitTimes) as per the utmi
548 * specification for any token following ISOC OUT token.
551 * @power_optimized: Are power optimizations enabled?
552 * @num_dev_ep: Number of device endpoints available
553 * @num_dev_in_eps: Number of device IN endpoints available
554 * @num_dev_perio_in_ep: Number of device periodic IN endpoints
556 * @dev_token_q_depth: Device Mode IN Token Sequence Learning Queue
559 * @host_perio_tx_q_depth:
560 * Host Mode Periodic Request Queue Depth
562 * @nperio_tx_q_depth:
563 * Non-Periodic Request Queue Depth
565 * @hs_phy_type: High-speed PHY interface type
566 * 0 - High-speed interface not supported
570 * @fs_phy_type: Full-speed PHY interface type
571 * 0 - Full speed interface not supported
572 * 1 - Dedicated full speed interface
573 * 2 - FS pins shared with UTMI+ pins
574 * 3 - FS pins shared with ULPI pins
575 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
576 * @hibernation: Is hibernation enabled?
577 * @utmi_phy_data_width: UTMI+ PHY data width
581 * @snpsid: Value from SNPSID register
582 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
583 * @g_tx_fifo_size: Power-on values of TxFIFO sizes
584 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
585 * address DMA mode or descriptor DMA mode for accessing
586 * the data FIFOs. The driver will automatically detect the
587 * value for this if none is specified.
589 * 1 - Descriptor DMA (default, if available)
590 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
591 * 1 - Allow dynamic FIFO sizing (default, if available)
592 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
593 * are enabled for non-periodic IN endpoints in device
595 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
596 * in host mode when dynamic FIFO sizing is enabled
598 * Actual maximum value is autodetected and also
600 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
601 * host mode when dynamic FIFO sizing is enabled
603 * Actual maximum value is autodetected and also
605 * @max_transfer_size: The maximum transfer size supported, in bytes
607 * Actual maximum value is autodetected and also
609 * @max_packet_count: The maximum number of packets in a transfer
611 * Actual maximum value is autodetected and also
613 * @host_channels: The number of host channel registers to use
615 * Actual maximum value is autodetected and also
617 * @dev_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
618 * in device mode when dynamic FIFO sizing is enabled
620 * Actual maximum value is autodetected and also
622 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
623 * speed PHY. This parameter is only applicable if phy_type
627 * @acg_enable: For enabling Active Clock Gating in the controller
630 * @lpm_mode: For enabling Link Power Management in the controller
633 * @rx_fifo_size: Number of 4-byte words in the Rx FIFO when dynamic
634 * FIFO sizing is enabled 16 to 32768
635 * Actual maximum value is autodetected and also
637 * @service_interval_mode: For enabling service interval based scheduling in the
642 struct dwc2_hw_params {
645 unsigned dma_desc_enable:1;
646 unsigned enable_dynamic_fifo:1;
647 unsigned en_multiple_tx_fifo:1;
648 unsigned rx_fifo_size:16;
649 unsigned host_nperio_tx_fifo_size:16;
650 unsigned dev_nperio_tx_fifo_size:16;
651 unsigned host_perio_tx_fifo_size:16;
652 unsigned nperio_tx_q_depth:3;
653 unsigned host_perio_tx_q_depth:3;
654 unsigned dev_token_q_depth:5;
655 unsigned max_transfer_size:26;
656 unsigned max_packet_count:11;
657 unsigned host_channels:5;
658 unsigned hs_phy_type:2;
659 unsigned fs_phy_type:2;
660 unsigned i2c_enable:1;
661 unsigned acg_enable:1;
662 unsigned num_dev_ep:4;
663 unsigned num_dev_in_eps : 4;
664 unsigned num_dev_perio_in_ep:4;
665 unsigned total_fifo_size:16;
666 unsigned power_optimized:1;
667 unsigned hibernation:1;
668 unsigned utmi_phy_data_width:2;
670 unsigned ipg_isoc_en:1;
671 unsigned service_interval_mode:1;
674 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
677 /* Size of control and EP0 buffers */
678 #define DWC2_CTRL_BUFF_SIZE 8
681 * struct dwc2_gregs_backup - Holds global registers state before
682 * entering partial power down
683 * @gotgctl: Backup of GOTGCTL register
684 * @gintmsk: Backup of GINTMSK register
685 * @gahbcfg: Backup of GAHBCFG register
686 * @gusbcfg: Backup of GUSBCFG register
687 * @grxfsiz: Backup of GRXFSIZ register
688 * @gnptxfsiz: Backup of GNPTXFSIZ register
689 * @gi2cctl: Backup of GI2CCTL register
690 * @glpmcfg: Backup of GLPMCFG register
691 * @gdfifocfg: Backup of GDFIFOCFG register
692 * @pcgcctl: Backup of PCGCCTL register
693 * @pcgcctl1: Backup of PCGCCTL1 register
694 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
695 * @gpwrdn: Backup of GPWRDN register
696 * @valid: True if registers values backuped.
698 struct dwc2_gregs_backup {
715 * struct dwc2_dregs_backup - Holds device registers state before
716 * entering partial power down
717 * @dcfg: Backup of DCFG register
718 * @dctl: Backup of DCTL register
719 * @daintmsk: Backup of DAINTMSK register
720 * @diepmsk: Backup of DIEPMSK register
721 * @doepmsk: Backup of DOEPMSK register
722 * @diepctl: Backup of DIEPCTL register
723 * @dieptsiz: Backup of DIEPTSIZ register
724 * @diepdma: Backup of DIEPDMA register
725 * @doepctl: Backup of DOEPCTL register
726 * @doeptsiz: Backup of DOEPTSIZ register
727 * @doepdma: Backup of DOEPDMA register
728 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
729 * @valid: True if registers values backuped.
731 struct dwc2_dregs_backup {
737 u32 diepctl[MAX_EPS_CHANNELS];
738 u32 dieptsiz[MAX_EPS_CHANNELS];
739 u32 diepdma[MAX_EPS_CHANNELS];
740 u32 doepctl[MAX_EPS_CHANNELS];
741 u32 doeptsiz[MAX_EPS_CHANNELS];
742 u32 doepdma[MAX_EPS_CHANNELS];
743 u32 dtxfsiz[MAX_EPS_CHANNELS];
748 * struct dwc2_hregs_backup - Holds host registers state before
749 * entering partial power down
750 * @hcfg: Backup of HCFG register
751 * @hflbaddr: Backup of HFLBADDR register
752 * @haintmsk: Backup of HAINTMSK register
753 * @hcchar: Backup of HCCHAR register
754 * @hcsplt: Backup of HCSPLT register
755 * @hcintmsk: Backup of HCINTMSK register
756 * @hctsiz: Backup of HCTSIZ register
757 * @hdma: Backup of HCDMA register
758 * @hcdmab: Backup of HCDMAB register
759 * @hprt0: Backup of HPTR0 register
760 * @hfir: Backup of HFIR register
761 * @hptxfsiz: Backup of HPTXFSIZ register
762 * @valid: True if registers values backuped.
764 struct dwc2_hregs_backup {
768 u32 hcchar[MAX_EPS_CHANNELS];
769 u32 hcsplt[MAX_EPS_CHANNELS];
770 u32 hcintmsk[MAX_EPS_CHANNELS];
771 u32 hctsiz[MAX_EPS_CHANNELS];
772 u32 hcidma[MAX_EPS_CHANNELS];
773 u32 hcidmab[MAX_EPS_CHANNELS];
781 * Constants related to high speed periodic scheduling
783 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
784 * reservation point of view it's assumed that the schedule goes right back to
785 * the beginning after the end of the schedule.
787 * What does that mean for scheduling things with a long interval? It means
788 * we'll reserve time for them in every possible microframe that they could
789 * ever be scheduled in. ...but we'll still only actually schedule them as
790 * often as they were requested.
792 * We keep our schedule in a "bitmap" structure. This simplifies having
793 * to keep track of and merge intervals: we just let the bitmap code do most
794 * of the heavy lifting. In a way scheduling is much like memory allocation.
796 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
797 * supposed to schedule for periodic transfers). That's according to spec.
799 * Note that though we only schedule 80% of each microframe, the bitmap that we
800 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
801 * space for each uFrame).
804 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
805 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
806 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
807 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
809 #define DWC2_US_PER_UFRAME 125
810 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
812 #define DWC2_HS_SCHEDULE_UFRAMES 8
813 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
814 DWC2_HS_PERIODIC_US_PER_UFRAME)
817 * Constants related to low speed scheduling
819 * For high speed we schedule every 1us. For low speed that's a bit overkill,
820 * so we make up a unit called a "slice" that's worth 25us. There are 40
821 * slices in a full frame and we can schedule 36 of those (90%) for periodic
824 * Our low speed schedule can be as short as 1 frame or could be longer. When
825 * we only schedule 1 frame it means that we'll need to reserve a time every
826 * frame even for things that only transfer very rarely, so something that runs
827 * every 2048 frames will get time reserved in every frame. Our low speed
828 * schedule can be longer and we'll be able to handle more overlap, but that
829 * will come at increased memory cost and increased time to schedule.
831 * Note: one other advantage of a short low speed schedule is that if we mess
832 * up and miss scheduling we can jump in and use any of the slots that we
833 * happened to reserve.
835 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
836 * the schedule. There will be one schedule per TT.
839 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
841 #define DWC2_US_PER_SLICE 25
842 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
844 #define DWC2_ROUND_US_TO_SLICE(us) \
845 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
848 #define DWC2_LS_PERIODIC_US_PER_FRAME \
850 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
851 (DWC2_LS_PERIODIC_US_PER_FRAME / \
854 #define DWC2_LS_SCHEDULE_FRAMES 1
855 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
856 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
859 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
860 * and periodic schedules
862 * These are common for both host and peripheral modes:
864 * @dev: The struct device pointer
865 * @regs: Pointer to controller regs
866 * @hw_params: Parameters that were autodetected from the
868 * @params: Parameters that define how the core should be configured
869 * @op_state: The operational State, during transitions (a_host=>
870 * a_peripheral and b_device=>b_host) this may not match
871 * the core, but allows the software to determine
873 * @dr_mode: Requested mode of operation, one of following:
874 * - USB_DR_MODE_PERIPHERAL
877 * @role_sw: usb_role_switch handle
878 * @hcd_enabled: Host mode sub-driver initialization indicator.
879 * @gadget_enabled: Peripheral mode sub-driver initialization indicator.
880 * @ll_hw_enabled: Status of low-level hardware resources.
881 * @hibernated: True if core is hibernated
882 * @reset_phy_on_wake: Quirk saying that we should assert PHY reset on a
884 * @phy_off_for_suspend: Status of whether we turned the PHY off at suspend.
885 * @need_phy_for_wake: Quirk saying that we should keep the PHY on at
886 * suspend if we need USB to wake us up.
887 * @frame_number: Frame number read from the core. For both device
888 * and host modes. The value ranges are from 0
889 * to HFNUM_MAX_FRNUM.
890 * @phy: The otg phy transceiver structure for phy control.
891 * @uphy: The otg phy transceiver structure for old USB phy
893 * @plat: The platform specific configuration data. This can be
894 * removed once all SoCs support usb transceiver.
895 * @supplies: Definition of USB power supplies
896 * @vbus_supply: Regulator supplying vbus.
897 * @usb33d: Optional 3.3v regulator used on some stm32 devices to
898 * supply ID and VBUS detection hardware.
899 * @lock: Spinlock that protects all the driver data structures
900 * @priv: Stores a pointer to the struct usb_hcd
901 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
902 * transfer are in process of being queued
903 * @srp_success: Stores status of SRP request in the case of a FS PHY
904 * with an I2C interface
905 * @wq_otg: Workqueue object used for handling of some interrupts
906 * @wf_otg: Work object for handling Connector ID Status Change
908 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
909 * @lx_state: Lx state of connected device
910 * @gr_backup: Backup of global registers during suspend
911 * @dr_backup: Backup of device registers during suspend
912 * @hr_backup: Backup of host registers during suspend
913 * @needs_byte_swap: Specifies whether the opposite endianness.
915 * These are for host mode:
917 * @flags: Flags for handling root port state changes
918 * @flags.d32: Contain all root port flags
919 * @flags.b: Separate root port flags from each other
920 * @flags.b.port_connect_status_change: True if root port connect status
922 * @flags.b.port_connect_status: True if device connected to root port
923 * @flags.b.port_reset_change: True if root port reset status changed
924 * @flags.b.port_enable_change: True if root port enable status changed
925 * @flags.b.port_suspend_change: True if root port suspend status changed
926 * @flags.b.port_over_current_change: True if root port over current state
928 * @flags.b.port_l1_change: True if root port l1 status changed
929 * @flags.b.reserved: Reserved bits of root port register
930 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
931 * Transfers associated with these QHs are not currently
932 * assigned to a host channel.
933 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
934 * Transfers associated with these QHs are currently
935 * assigned to a host channel.
936 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
937 * non-periodic schedule
938 * @non_periodic_sched_waiting: Waiting QHs in the non-periodic schedule.
939 * Transfers associated with these QHs are not currently
940 * assigned to a host channel.
941 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
942 * list of QHs for periodic transfers that are _not_
943 * scheduled for the next frame. Each QH in the list has an
944 * interval counter that determines when it needs to be
945 * scheduled for execution. This scheduling mechanism
946 * allows only a simple calculation for periodic bandwidth
947 * used (i.e. must assume that all periodic transfers may
948 * need to execute in the same frame). However, it greatly
949 * simplifies scheduling and should be sufficient for the
950 * vast majority of OTG hosts, which need to connect to a
951 * small number of peripherals at one time. Items move from
952 * this list to periodic_sched_ready when the QH interval
953 * counter is 0 at SOF.
954 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
955 * the next frame, but have not yet been assigned to host
956 * channels. Items move from this list to
957 * periodic_sched_assigned as host channels become
958 * available during the current frame.
959 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
960 * frame that are assigned to host channels. Items move
961 * from this list to periodic_sched_queued as the
962 * transactions for the QH are queued to the DWC_otg
964 * @periodic_sched_queued: List of periodic QHs that have been queued for
965 * execution. Items move from this list to either
966 * periodic_sched_inactive or periodic_sched_ready when the
967 * channel associated with the transfer is released. If the
968 * interval for the QH is 1, the item moves to
969 * periodic_sched_ready because it must be rescheduled for
970 * the next frame. Otherwise, the item moves to
971 * periodic_sched_inactive.
972 * @split_order: List keeping track of channels doing splits, in order.
973 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
974 * This value is in microseconds per (micro)frame. The
975 * assumption is that all periodic transfers may occur in
976 * the same (micro)frame.
977 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
978 * host is in high speed mode; low speed schedules are
979 * stored elsewhere since we need one per TT.
980 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
981 * SOF enable/disable.
982 * @free_hc_list: Free host channels in the controller. This is a list of
983 * struct dwc2_host_chan items.
984 * @periodic_channels: Number of host channels assigned to periodic transfers.
985 * Currently assuming that there is a dedicated host
986 * channel for each periodic transaction and at least one
987 * host channel is available for non-periodic transactions.
988 * @non_periodic_channels: Number of host channels assigned to non-periodic
990 * @available_host_channels: Number of host channels available for the
991 * microframe scheduler to use
992 * @hc_ptr_array: Array of pointers to the host channel descriptors.
993 * Allows accessing a host channel descriptor given the
994 * host channel number. This is useful in interrupt
996 * @status_buf: Buffer used for data received during the status phase of
997 * a control transfer.
998 * @status_buf_dma: DMA address for status_buf
999 * @start_work: Delayed work for handling host A-cable connection
1000 * @reset_work: Delayed work for handling a port reset
1001 * @phy_reset_work: Work structure for doing a PHY reset
1002 * @otg_port: OTG port number
1003 * @frame_list: Frame list
1004 * @frame_list_dma: Frame list DMA address
1005 * @frame_list_sz: Frame list size
1006 * @desc_gen_cache: Kmem cache for generic descriptors
1007 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
1008 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
1010 * These are for peripheral mode:
1012 * @driver: USB gadget driver
1013 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
1014 * @num_of_eps: Number of available EPs (excluding EP0)
1015 * @debug_root: Root directrory for debugfs.
1016 * @ep0_reply: Request used for ep0 reply.
1017 * @ep0_buff: Buffer for EP0 reply data, if needed.
1018 * @ctrl_buff: Buffer for EP0 control requests.
1019 * @ctrl_req: Request for EP0 control packets.
1020 * @ep0_state: EP0 control transfers state
1021 * @delayed_status: true when gadget driver asks for delayed status
1022 * @test_mode: USB test mode requested by the host
1023 * @remote_wakeup_allowed: True if device is allowed to wake-up host by
1024 * remote-wakeup signalling
1025 * @setup_desc_dma: EP0 setup stage desc chain DMA address
1026 * @setup_desc: EP0 setup stage desc chain pointer
1027 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
1028 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
1029 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
1030 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
1031 * @irq: Interrupt request line number
1032 * @clk: Pointer to otg clock
1033 * @reset: Pointer to dwc2 reset controller
1034 * @reset_ecc: Pointer to dwc2 optional reset controller in Stratix10.
1035 * @regset: A pointer to a struct debugfs_regset32, which contains
1036 * a pointer to an array of register definitions, the
1037 * array size and the base address where the register bank
1039 * @bus_suspended: True if bus is suspended
1040 * @last_frame_num: Number of last frame. Range from 0 to 32768
1041 * @frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1042 * defined, for missed SOFs tracking. Array holds that
1043 * frame numbers, which not equal to last_frame_num +1
1044 * @last_frame_num_array: Used only if CONFIG_USB_DWC2_TRACK_MISSED_SOFS is
1045 * defined, for missed SOFs tracking.
1046 * If current_frame_number != last_frame_num+1
1047 * then last_frame_num added to this array
1048 * @frame_num_idx: Actual size of frame_num_array and last_frame_num_array
1049 * @dumped_frame_num_array: 1 - if missed SOFs frame numbers dumbed
1050 * 0 - if missed SOFs frame numbers not dumbed
1051 * @fifo_mem: Total internal RAM for FIFOs (bytes)
1052 * @fifo_map: Each bit intend for concrete fifo. If that bit is set,
1053 * then that fifo is used
1054 * @gadget: Represents a usb gadget device
1055 * @connected: Used in slave mode. True if device connected with host
1056 * @eps_in: The IN endpoints being supplied to the gadget framework
1057 * @eps_out: The OUT endpoints being supplied to the gadget framework
1058 * @new_connection: Used in host mode. True if there are new connected
1060 * @enabled: Indicates the enabling state of controller
1066 /** Params detected from hardware */
1067 struct dwc2_hw_params hw_params;
1068 /** Params to actually use */
1069 struct dwc2_core_params params;
1070 enum usb_otg_state op_state;
1071 enum usb_dr_mode dr_mode;
1072 struct usb_role_switch *role_sw;
1073 unsigned int hcd_enabled:1;
1074 unsigned int gadget_enabled:1;
1075 unsigned int ll_hw_enabled:1;
1076 unsigned int hibernated:1;
1077 unsigned int reset_phy_on_wake:1;
1078 unsigned int need_phy_for_wake:1;
1079 unsigned int phy_off_for_suspend:1;
1083 struct usb_phy *uphy;
1084 struct dwc2_hsotg_plat *plat;
1085 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
1086 struct regulator *vbus_supply;
1087 struct regulator *usb33d;
1093 struct reset_control *reset;
1094 struct reset_control *reset_ecc;
1096 unsigned int queuing_high_bandwidth:1;
1097 unsigned int srp_success:1;
1099 struct workqueue_struct *wq_otg;
1100 struct work_struct wf_otg;
1101 struct timer_list wkp_timer;
1102 enum dwc2_lx_state lx_state;
1103 struct dwc2_gregs_backup gr_backup;
1104 struct dwc2_dregs_backup dr_backup;
1105 struct dwc2_hregs_backup hr_backup;
1107 struct dentry *debug_root;
1108 struct debugfs_regset32 *regset;
1109 bool needs_byte_swap;
1111 /* DWC OTG HW Release versions */
1112 #define DWC2_CORE_REV_4_30a 0x4f54430a
1113 #define DWC2_CORE_REV_2_71a 0x4f54271a
1114 #define DWC2_CORE_REV_2_72a 0x4f54272a
1115 #define DWC2_CORE_REV_2_80a 0x4f54280a
1116 #define DWC2_CORE_REV_2_90a 0x4f54290a
1117 #define DWC2_CORE_REV_2_91a 0x4f54291a
1118 #define DWC2_CORE_REV_2_92a 0x4f54292a
1119 #define DWC2_CORE_REV_2_94a 0x4f54294a
1120 #define DWC2_CORE_REV_3_00a 0x4f54300a
1121 #define DWC2_CORE_REV_3_10a 0x4f54310a
1122 #define DWC2_CORE_REV_4_00a 0x4f54400a
1123 #define DWC2_CORE_REV_4_20a 0x4f54420a
1124 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
1125 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
1126 #define DWC2_CORE_REV_MASK 0x0000ffff
1128 /* DWC OTG HW Core ID */
1129 #define DWC2_OTG_ID 0x4f540000
1130 #define DWC2_FS_IOT_ID 0x55310000
1131 #define DWC2_HS_IOT_ID 0x55320000
1133 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1134 union dwc2_hcd_internal_flags {
1137 unsigned port_connect_status_change:1;
1138 unsigned port_connect_status:1;
1139 unsigned port_reset_change:1;
1140 unsigned port_enable_change:1;
1141 unsigned port_suspend_change:1;
1142 unsigned port_over_current_change:1;
1143 unsigned port_l1_change:1;
1144 unsigned reserved:25;
1148 struct list_head non_periodic_sched_inactive;
1149 struct list_head non_periodic_sched_waiting;
1150 struct list_head non_periodic_sched_active;
1151 struct list_head *non_periodic_qh_ptr;
1152 struct list_head periodic_sched_inactive;
1153 struct list_head periodic_sched_ready;
1154 struct list_head periodic_sched_assigned;
1155 struct list_head periodic_sched_queued;
1156 struct list_head split_order;
1158 unsigned long hs_periodic_bitmap[
1159 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
1160 u16 periodic_qh_count;
1162 bool new_connection;
1166 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
1167 #define FRAME_NUM_ARRAY_SIZE 1000
1168 u16 *frame_num_array;
1169 u16 *last_frame_num_array;
1171 int dumped_frame_num_array;
1174 struct list_head free_hc_list;
1175 int periodic_channels;
1176 int non_periodic_channels;
1177 int available_host_channels;
1178 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
1180 dma_addr_t status_buf_dma;
1181 #define DWC2_HCD_STATUS_BUF_SIZE 64
1183 struct delayed_work start_work;
1184 struct delayed_work reset_work;
1185 struct work_struct phy_reset_work;
1188 dma_addr_t frame_list_dma;
1190 struct kmem_cache *desc_gen_cache;
1191 struct kmem_cache *desc_hsisoc_cache;
1192 struct kmem_cache *unaligned_cache;
1193 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
1195 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1197 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1198 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1199 /* Gadget structures */
1200 struct usb_gadget_driver *driver;
1202 unsigned int dedicated_fifos:1;
1203 unsigned char num_of_eps;
1206 struct usb_request *ep0_reply;
1207 struct usb_request *ctrl_req;
1210 enum dwc2_ep0_state ep0_state;
1211 unsigned delayed_status : 1;
1214 dma_addr_t setup_desc_dma[2];
1215 struct dwc2_dma_desc *setup_desc[2];
1216 dma_addr_t ctrl_in_desc_dma;
1217 struct dwc2_dma_desc *ctrl_in_desc;
1218 dma_addr_t ctrl_out_desc_dma;
1219 struct dwc2_dma_desc *ctrl_out_desc;
1221 struct usb_gadget gadget;
1222 unsigned int enabled:1;
1223 unsigned int connected:1;
1224 unsigned int remote_wakeup_allowed:1;
1225 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1226 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1227 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1230 /* Normal architectures just use readl/write */
1231 static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset)
1235 val = readl(hsotg->regs + offset);
1236 if (hsotg->needs_byte_swap)
1242 static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset)
1244 if (hsotg->needs_byte_swap)
1245 writel(swab32(value), hsotg->regs + offset);
1247 writel(value, hsotg->regs + offset);
1249 #ifdef DWC2_LOG_WRITES
1250 pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset);
1254 static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset,
1255 void *buffer, unsigned int count)
1261 u32 x = dwc2_readl(hsotg, offset);
1267 static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset,
1268 const void *buffer, unsigned int count)
1271 const u32 *buf = buffer;
1274 dwc2_writel(hsotg, *buf++, offset);
1279 /* Reasons for halting a host channel */
1280 enum dwc2_halt_status {
1281 DWC2_HC_XFER_NO_HALT_STATUS,
1282 DWC2_HC_XFER_COMPLETE,
1283 DWC2_HC_XFER_URB_COMPLETE,
1288 DWC2_HC_XFER_XACT_ERR,
1289 DWC2_HC_XFER_FRAME_OVERRUN,
1290 DWC2_HC_XFER_BABBLE_ERR,
1291 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1292 DWC2_HC_XFER_AHB_ERR,
1293 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1294 DWC2_HC_XFER_URB_DEQUEUE,
1297 /* Core version information */
1298 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1300 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1303 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1305 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1308 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1310 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1314 * The following functions support initialization of the core driver component
1315 * and the DWC_otg controller
1317 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1318 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg);
1319 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore);
1320 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host);
1321 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
1322 int reset, int is_host);
1323 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg);
1324 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy);
1326 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host);
1327 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1329 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1331 int dwc2_check_core_version(struct dwc2_hsotg *hsotg);
1334 * Common core Functions.
1335 * The following functions support managing the DWC_otg controller in either
1336 * device or host mode.
1338 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1339 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1340 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1342 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1343 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1345 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
1347 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg);
1348 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg);
1350 void dwc2_enable_acg(struct dwc2_hsotg *hsotg);
1351 void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg, bool remotewakeup);
1353 /* This function should be called on every hardware interrupt. */
1354 irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1356 /* The device ID match table */
1357 extern const struct of_device_id dwc2_of_match_table[];
1359 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1360 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1362 /* Common polling functions */
1363 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1365 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hs_otg, u32 reg, u32 bit,
1368 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1369 int dwc2_init_params(struct dwc2_hsotg *hsotg);
1372 * The following functions check the controller's OTG operation mode
1373 * capability (GHWCFG2.OTG_MODE).
1375 * These functions can be used before the internal hsotg->hw_params
1376 * are read in and cached so they always read directly from the
1379 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1380 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1381 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1382 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1385 * Returns the mode of operation, host or device
1387 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1389 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1392 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1394 return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1397 int dwc2_drd_init(struct dwc2_hsotg *hsotg);
1398 void dwc2_drd_suspend(struct dwc2_hsotg *hsotg);
1399 void dwc2_drd_resume(struct dwc2_hsotg *hsotg);
1400 void dwc2_drd_exit(struct dwc2_hsotg *hsotg);
1403 * Dump core registers and SPRAM
1405 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1406 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1407 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1409 /* Gadget defines */
1410 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1411 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1412 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1413 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1414 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1415 int dwc2_gadget_init(struct dwc2_hsotg *hsotg);
1416 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1418 void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg);
1419 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1420 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1421 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1422 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1423 #define dwc2_is_device_enabled(hsotg) (hsotg->enabled)
1424 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1425 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup);
1426 int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg);
1427 int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1428 int rem_wakeup, int reset);
1429 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1430 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1431 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
1432 void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg);
1433 void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg);
1435 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1437 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1439 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1441 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg)
1443 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1445 static inline void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) {}
1446 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
1447 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
1448 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1451 #define dwc2_is_device_connected(hsotg) (0)
1452 #define dwc2_is_device_enabled(hsotg) (0)
1453 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1455 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg,
1458 static inline int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg)
1460 static inline int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg,
1461 int rem_wakeup, int reset)
1463 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1465 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1467 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1469 static inline void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) {}
1470 static inline void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg) {}
1473 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1474 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1475 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1476 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1477 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1478 void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1479 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup);
1480 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1481 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1482 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg);
1483 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1484 int rem_wakeup, int reset);
1485 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2);
1486 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg)
1487 { schedule_work(&hsotg->phy_reset_work); }
1489 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1491 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1494 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
1495 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
1496 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
1497 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
1498 static inline int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
1500 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1502 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1504 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1506 static inline int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
1508 static inline int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg,
1509 int rem_wakeup, int reset)
1511 static inline bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2)
1513 static inline void dwc2_host_schedule_phy_reset(struct dwc2_hsotg *hsotg) {}
1517 #endif /* __DWC2_CORE_H__ */