1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.c - DesignWare HS OTG Controller common routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
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12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
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18 * specific prior written permission.
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * The Core code provides basic services for accessing and managing the
40 * DWC_otg hardware. These services are used by both the Host Controller
41 * Driver and the Peripheral Controller Driver.
43 #include <linux/kernel.h>
44 #include <linux/module.h>
45 #include <linux/moduleparam.h>
46 #include <linux/spinlock.h>
47 #include <linux/interrupt.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/delay.h>
51 #include <linux/slab.h>
52 #include <linux/usb.h>
54 #include <linux/usb/hcd.h>
55 #include <linux/usb/ch11.h>
61 * dwc2_backup_global_registers() - Backup global controller registers.
62 * When suspending usb bus, registers needs to be backuped
63 * if controller power is disabled once suspended.
65 * @hsotg: Programming view of the DWC_otg controller
67 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
69 struct dwc2_gregs_backup *gr;
71 dev_dbg(hsotg->dev, "%s\n", __func__);
73 /* Backup global regs */
74 gr = &hsotg->gr_backup;
76 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
77 gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
78 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
79 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
80 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
81 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
82 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
83 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
84 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
85 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
86 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
93 * dwc2_restore_global_registers() - Restore controller global registers.
94 * When resuming usb bus, device registers needs to be restored
95 * if controller power were disabled.
97 * @hsotg: Programming view of the DWC_otg controller
99 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
101 struct dwc2_gregs_backup *gr;
103 dev_dbg(hsotg->dev, "%s\n", __func__);
105 /* Restore global regs */
106 gr = &hsotg->gr_backup;
108 dev_err(hsotg->dev, "%s: no global registers to restore\n",
114 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
115 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
116 dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
117 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
118 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
119 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
120 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
121 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
122 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
123 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
124 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
125 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
131 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
133 * @hsotg: Programming view of the DWC_otg controller
134 * @restore: Controller registers need to be restored
136 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore)
141 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
144 pcgcctl = dwc2_readl(hsotg, PCGCTL);
145 pcgcctl &= ~PCGCTL_STOPPCLK;
146 dwc2_writel(hsotg, pcgcctl, PCGCTL);
148 pcgcctl = dwc2_readl(hsotg, PCGCTL);
149 pcgcctl &= ~PCGCTL_PWRCLMP;
150 dwc2_writel(hsotg, pcgcctl, PCGCTL);
152 pcgcctl = dwc2_readl(hsotg, PCGCTL);
153 pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
154 dwc2_writel(hsotg, pcgcctl, PCGCTL);
158 ret = dwc2_restore_global_registers(hsotg);
160 dev_err(hsotg->dev, "%s: failed to restore registers\n",
164 if (dwc2_is_host_mode(hsotg)) {
165 ret = dwc2_restore_host_registers(hsotg);
167 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
172 ret = dwc2_restore_device_registers(hsotg, 0);
174 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
185 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
187 * @hsotg: Programming view of the DWC_otg controller
189 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
194 if (!hsotg->params.power_down)
197 /* Backup all registers */
198 ret = dwc2_backup_global_registers(hsotg);
200 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
205 if (dwc2_is_host_mode(hsotg)) {
206 ret = dwc2_backup_host_registers(hsotg);
208 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
213 ret = dwc2_backup_device_registers(hsotg);
215 dev_err(hsotg->dev, "%s: failed to backup device registers\n",
222 * Clear any pending interrupts since dwc2 will not be able to
223 * clear them after entering partial_power_down.
225 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
227 /* Put the controller in low power state */
228 pcgcctl = dwc2_readl(hsotg, PCGCTL);
230 pcgcctl |= PCGCTL_PWRCLMP;
231 dwc2_writel(hsotg, pcgcctl, PCGCTL);
234 pcgcctl |= PCGCTL_RSTPDWNMODULE;
235 dwc2_writel(hsotg, pcgcctl, PCGCTL);
238 pcgcctl |= PCGCTL_STOPPCLK;
239 dwc2_writel(hsotg, pcgcctl, PCGCTL);
245 * dwc2_restore_essential_regs() - Restore essiential regs of core.
247 * @hsotg: Programming view of the DWC_otg controller
248 * @rmode: Restore mode, enabled in case of remote-wakeup.
249 * @is_host: Host or device mode.
251 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
255 struct dwc2_gregs_backup *gr;
256 struct dwc2_dregs_backup *dr;
257 struct dwc2_hregs_backup *hr;
259 gr = &hsotg->gr_backup;
260 dr = &hsotg->dr_backup;
261 hr = &hsotg->hr_backup;
263 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
265 /* Load restore values for [31:14] bits */
266 pcgcctl = (gr->pcgcctl & 0xffffc000);
269 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
272 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
275 dwc2_writel(hsotg, pcgcctl, PCGCTL);
277 /* Umnask global Interrupt in GAHBCFG and restore it */
278 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
280 /* Clear all pending interupts */
281 dwc2_writel(hsotg, 0xffffffff, GINTSTS);
283 /* Unmask restore done interrupt */
284 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
286 /* Restore GUSBCFG and HCFG/DCFG */
287 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
290 dwc2_writel(hsotg, hr->hcfg, HCFG);
292 pcgcctl |= PCGCTL_RESTOREMODE;
293 dwc2_writel(hsotg, pcgcctl, PCGCTL);
296 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
297 dwc2_writel(hsotg, pcgcctl, PCGCTL);
300 dwc2_writel(hsotg, dr->dcfg, DCFG);
302 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
303 dwc2_writel(hsotg, pcgcctl, PCGCTL);
306 pcgcctl |= PCGCTL_ESS_REG_RESTORED;
307 dwc2_writel(hsotg, pcgcctl, PCGCTL);
313 * dwc2_hib_restore_common() - Common part of restore routine.
315 * @hsotg: Programming view of the DWC_otg controller
316 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
317 * @is_host: Host or device mode.
319 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
324 /* Switch-on voltage to the core */
325 gpwrdn = dwc2_readl(hsotg, GPWRDN);
326 gpwrdn &= ~GPWRDN_PWRDNSWTCH;
327 dwc2_writel(hsotg, gpwrdn, GPWRDN);
331 gpwrdn = dwc2_readl(hsotg, GPWRDN);
332 gpwrdn &= ~GPWRDN_PWRDNRSTN;
333 dwc2_writel(hsotg, gpwrdn, GPWRDN);
336 /* Enable restore from PMU */
337 gpwrdn = dwc2_readl(hsotg, GPWRDN);
338 gpwrdn |= GPWRDN_RESTORE;
339 dwc2_writel(hsotg, gpwrdn, GPWRDN);
342 /* Disable Power Down Clamp */
343 gpwrdn = dwc2_readl(hsotg, GPWRDN);
344 gpwrdn &= ~GPWRDN_PWRDNCLMP;
345 dwc2_writel(hsotg, gpwrdn, GPWRDN);
348 if (!is_host && rem_wakeup)
351 /* Deassert reset core */
352 gpwrdn = dwc2_readl(hsotg, GPWRDN);
353 gpwrdn |= GPWRDN_PWRDNRSTN;
354 dwc2_writel(hsotg, gpwrdn, GPWRDN);
357 /* Disable PMU interrupt */
358 gpwrdn = dwc2_readl(hsotg, GPWRDN);
359 gpwrdn &= ~GPWRDN_PMUINTSEL;
360 dwc2_writel(hsotg, gpwrdn, GPWRDN);
363 /* Set Restore Essential Regs bit in PCGCCTL register */
364 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
367 * Wait For Restore_done Interrupt. This mechanism of polling the
368 * interrupt is introduced to avoid any possible race conditions
370 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
373 "%s: Restore Done wan't generated here\n",
376 dev_dbg(hsotg->dev, "restore done generated here\n");
381 * dwc2_wait_for_mode() - Waits for the controller mode.
382 * @hsotg: Programming view of the DWC_otg controller.
383 * @host_mode: If true, waits for host mode, otherwise device mode.
385 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
390 unsigned int timeout = 110;
392 dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
393 host_mode ? "host" : "device");
400 if (dwc2_is_host_mode(hsotg) == host_mode) {
401 dev_vdbg(hsotg->dev, "%s mode set\n",
402 host_mode ? "Host" : "Device");
407 ms = ktime_to_ms(ktime_sub(end, start));
409 if (ms >= (s64)timeout) {
410 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
411 __func__, host_mode ? "host" : "device");
415 usleep_range(1000, 2000);
420 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
423 * @hsotg: Programming view of DWC_otg controller
425 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
430 if (!dwc2_hw_is_otg(hsotg))
433 /* Check if core configuration includes the IDDIG filter. */
434 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
435 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
439 * Check if the IDDIG debounce filter is bypassed. Available
440 * in core version >= 3.10a.
442 gsnpsid = dwc2_readl(hsotg, GSNPSID);
443 if (gsnpsid >= DWC2_CORE_REV_3_10a) {
444 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
446 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
454 * dwc2_enter_hibernation() - Common function to enter hibernation.
456 * @hsotg: Programming view of the DWC_otg controller
457 * @is_host: True if core is in host mode.
459 * Return: 0 if successful, negative error code otherwise
461 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
463 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_HIBERNATION)
467 return dwc2_host_enter_hibernation(hsotg);
469 return dwc2_gadget_enter_hibernation(hsotg);
473 * dwc2_exit_hibernation() - Common function to exit from hibernation.
475 * @hsotg: Programming view of the DWC_otg controller
476 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
477 * @reset: Enabled in case of restore with reset.
478 * @is_host: True if core is in host mode.
480 * Return: 0 if successful, negative error code otherwise
482 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
483 int reset, int is_host)
486 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
488 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
492 * Do core a soft reset of the core. Be careful with this because it
493 * resets all the internal state machines of the core.
495 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
498 bool wait_for_host_mode = false;
500 dev_vdbg(hsotg->dev, "%s()\n", __func__);
503 * If the current mode is host, either due to the force mode
504 * bit being set (which persists after core reset) or the
505 * connector id pin, a core soft reset will temporarily reset
506 * the mode to device. A delay from the IDDIG debounce filter
507 * will occur before going back to host mode.
509 * Determine whether we will go back into host mode after a
510 * reset and account for this delay after the reset.
512 if (dwc2_iddig_filter_enabled(hsotg)) {
513 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
514 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
516 if (!(gotgctl & GOTGCTL_CONID_B) ||
517 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
518 wait_for_host_mode = true;
522 /* Core Soft Reset */
523 greset = dwc2_readl(hsotg, GRSTCTL);
524 greset |= GRSTCTL_CSFTRST;
525 dwc2_writel(hsotg, greset, GRSTCTL);
527 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
528 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
529 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
530 GRSTCTL_CSFTRST, 10000)) {
531 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
536 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
537 GRSTCTL_CSFTRST_DONE, 10000)) {
538 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
542 greset = dwc2_readl(hsotg, GRSTCTL);
543 greset &= ~GRSTCTL_CSFTRST;
544 greset |= GRSTCTL_CSFTRST_DONE;
545 dwc2_writel(hsotg, greset, GRSTCTL);
548 /* Wait for AHB master IDLE state */
549 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
550 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
555 if (wait_for_host_mode && !skip_wait)
556 dwc2_wait_for_mode(hsotg, true);
562 * dwc2_force_mode() - Force the mode of the controller.
564 * Forcing the mode is needed for two cases:
566 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
567 * controller to stay in a particular mode regardless of ID pin
568 * changes. We do this once during probe.
570 * 2) During probe we want to read reset values of the hw
571 * configuration registers that are only available in either host or
572 * device mode. We may need to force the mode if the current mode does
573 * not allow us to access the register in the mode that we want.
575 * In either case it only makes sense to force the mode if the
576 * controller hardware is OTG capable.
578 * Checks are done in this function to determine whether doing a force
579 * would be valid or not.
581 * If a force is done, it requires a IDDIG debounce filter delay if
582 * the filter is configured and enabled. We poll the current mode of
583 * the controller to account for this delay.
585 * @hsotg: Programming view of DWC_otg controller
586 * @host: Host mode flag
588 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
594 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
597 * Force mode has no effect if the hardware is not OTG.
599 if (!dwc2_hw_is_otg(hsotg))
603 * If dr_mode is either peripheral or host only, there is no
604 * need to ever force the mode to the opposite mode.
606 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
609 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
612 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
614 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
615 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
619 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
621 dwc2_wait_for_mode(hsotg, host);
626 * dwc2_clear_force_mode() - Clears the force mode bits.
628 * After clearing the bits, wait up to 100 ms to account for any
629 * potential IDDIG filter delay. We can't know if we expect this delay
630 * or not because the value of the connector ID status is affected by
631 * the force mode. We only need to call this once during probe if
634 * @hsotg: Programming view of DWC_otg controller
636 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
640 if (!dwc2_hw_is_otg(hsotg))
643 dev_dbg(hsotg->dev, "Clearing force mode bits\n");
645 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
646 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
647 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
648 dwc2_writel(hsotg, gusbcfg, GUSBCFG);
650 if (dwc2_iddig_filter_enabled(hsotg))
655 * Sets or clears force mode based on the dr_mode parameter.
657 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
659 switch (hsotg->dr_mode) {
660 case USB_DR_MODE_HOST:
662 * NOTE: This is required for some rockchip soc based
663 * platforms on their host-only dwc2.
665 if (!dwc2_hw_is_otg(hsotg))
669 case USB_DR_MODE_PERIPHERAL:
670 dwc2_force_mode(hsotg, false);
672 case USB_DR_MODE_OTG:
673 dwc2_clear_force_mode(hsotg);
676 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
677 __func__, hsotg->dr_mode);
683 * dwc2_enable_acg - enable active clock gating feature
685 void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
687 if (hsotg->params.acg_enable) {
688 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
690 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
691 pcgcctl1 |= PCGCCTL1_GATEEN;
692 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
697 * dwc2_dump_host_registers() - Prints the host registers
699 * @hsotg: Programming view of DWC_otg controller
701 * NOTE: This function will be removed once the peripheral controller code
702 * is integrated and the driver is stable
704 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
710 dev_dbg(hsotg->dev, "Host Global Registers\n");
711 addr = hsotg->regs + HCFG;
712 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n",
713 (unsigned long)addr, dwc2_readl(hsotg, HCFG));
714 addr = hsotg->regs + HFIR;
715 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n",
716 (unsigned long)addr, dwc2_readl(hsotg, HFIR));
717 addr = hsotg->regs + HFNUM;
718 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n",
719 (unsigned long)addr, dwc2_readl(hsotg, HFNUM));
720 addr = hsotg->regs + HPTXSTS;
721 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n",
722 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
723 addr = hsotg->regs + HAINT;
724 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n",
725 (unsigned long)addr, dwc2_readl(hsotg, HAINT));
726 addr = hsotg->regs + HAINTMSK;
727 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n",
728 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
729 if (hsotg->params.dma_desc_enable) {
730 addr = hsotg->regs + HFLBADDR;
731 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
732 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
735 addr = hsotg->regs + HPRT0;
736 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n",
737 (unsigned long)addr, dwc2_readl(hsotg, HPRT0));
739 for (i = 0; i < hsotg->params.host_channels; i++) {
740 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
741 addr = hsotg->regs + HCCHAR(i);
742 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n",
743 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
744 addr = hsotg->regs + HCSPLT(i);
745 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n",
746 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
747 addr = hsotg->regs + HCINT(i);
748 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n",
749 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
750 addr = hsotg->regs + HCINTMSK(i);
751 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n",
752 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
753 addr = hsotg->regs + HCTSIZ(i);
754 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n",
755 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
756 addr = hsotg->regs + HCDMA(i);
757 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n",
758 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
759 if (hsotg->params.dma_desc_enable) {
760 addr = hsotg->regs + HCDMAB(i);
761 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n",
762 (unsigned long)addr, dwc2_readl(hsotg,
770 * dwc2_dump_global_registers() - Prints the core global registers
772 * @hsotg: Programming view of DWC_otg controller
774 * NOTE: This function will be removed once the peripheral controller code
775 * is integrated and the driver is stable
777 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
782 dev_dbg(hsotg->dev, "Core Global Registers\n");
783 addr = hsotg->regs + GOTGCTL;
784 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n",
785 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
786 addr = hsotg->regs + GOTGINT;
787 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n",
788 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
789 addr = hsotg->regs + GAHBCFG;
790 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n",
791 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
792 addr = hsotg->regs + GUSBCFG;
793 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n",
794 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
795 addr = hsotg->regs + GRSTCTL;
796 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n",
797 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
798 addr = hsotg->regs + GINTSTS;
799 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n",
800 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
801 addr = hsotg->regs + GINTMSK;
802 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n",
803 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
804 addr = hsotg->regs + GRXSTSR;
805 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n",
806 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
807 addr = hsotg->regs + GRXFSIZ;
808 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n",
809 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
810 addr = hsotg->regs + GNPTXFSIZ;
811 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n",
812 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
813 addr = hsotg->regs + GNPTXSTS;
814 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n",
815 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
816 addr = hsotg->regs + GI2CCTL;
817 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n",
818 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
819 addr = hsotg->regs + GPVNDCTL;
820 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n",
821 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
822 addr = hsotg->regs + GGPIO;
823 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n",
824 (unsigned long)addr, dwc2_readl(hsotg, GGPIO));
825 addr = hsotg->regs + GUID;
826 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n",
827 (unsigned long)addr, dwc2_readl(hsotg, GUID));
828 addr = hsotg->regs + GSNPSID;
829 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n",
830 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
831 addr = hsotg->regs + GHWCFG1;
832 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n",
833 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
834 addr = hsotg->regs + GHWCFG2;
835 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n",
836 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
837 addr = hsotg->regs + GHWCFG3;
838 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n",
839 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
840 addr = hsotg->regs + GHWCFG4;
841 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n",
842 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
843 addr = hsotg->regs + GLPMCFG;
844 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n",
845 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
846 addr = hsotg->regs + GPWRDN;
847 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n",
848 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
849 addr = hsotg->regs + GDFIFOCFG;
850 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n",
851 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
852 addr = hsotg->regs + HPTXFSIZ;
853 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n",
854 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
856 addr = hsotg->regs + PCGCTL;
857 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n",
858 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
863 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
865 * @hsotg: Programming view of DWC_otg controller
866 * @num: Tx FIFO to flush
868 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
872 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
874 /* Wait for AHB master IDLE state */
875 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
876 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
879 greset = GRSTCTL_TXFFLSH;
880 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
881 dwc2_writel(hsotg, greset, GRSTCTL);
883 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
884 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
887 /* Wait for at least 3 PHY Clocks */
892 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
894 * @hsotg: Programming view of DWC_otg controller
896 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
900 dev_vdbg(hsotg->dev, "%s()\n", __func__);
902 /* Wait for AHB master IDLE state */
903 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
904 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n",
907 greset = GRSTCTL_RXFFLSH;
908 dwc2_writel(hsotg, greset, GRSTCTL);
910 /* Wait for RxFIFO flush done */
911 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
912 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
915 /* Wait for at least 3 PHY Clocks */
919 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
921 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
928 * dwc2_enable_global_interrupts() - Enables the controller's Global
929 * Interrupt in the AHB Config register
931 * @hsotg: Programming view of DWC_otg controller
933 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
935 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
937 ahbcfg |= GAHBCFG_GLBL_INTR_EN;
938 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
942 * dwc2_disable_global_interrupts() - Disables the controller's Global
943 * Interrupt in the AHB Config register
945 * @hsotg: Programming view of DWC_otg controller
947 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
949 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
951 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
952 dwc2_writel(hsotg, ahbcfg, GAHBCFG);
955 /* Returns the controller's GHWCFG2.OTG_MODE. */
956 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
958 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
960 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
961 GHWCFG2_OP_MODE_SHIFT;
964 /* Returns true if the controller is capable of DRD. */
965 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
967 unsigned int op_mode = dwc2_op_mode(hsotg);
969 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
970 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
971 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
974 /* Returns true if the controller is host-only. */
975 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
977 unsigned int op_mode = dwc2_op_mode(hsotg);
979 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
980 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
983 /* Returns true if the controller is device-only. */
984 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
986 unsigned int op_mode = dwc2_op_mode(hsotg);
988 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
989 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
993 * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
994 * @hsotg: Programming view of DWC_otg controller.
995 * @offset: Register's offset where bit/bits must be set.
996 * @mask: Mask of the bit/bits which must be set.
997 * @timeout: Timeout to wait.
999 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
1001 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
1006 for (i = 0; i < timeout; i++) {
1007 if (dwc2_readl(hsotg, offset) & mask)
1016 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
1017 * @hsotg: Programming view of DWC_otg controller.
1018 * @offset: Register's offset where bit/bits must be set.
1019 * @mask: Mask of the bit/bits which must be set.
1020 * @timeout: Timeout to wait.
1022 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
1024 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
1029 for (i = 0; i < timeout; i++) {
1030 if (!(dwc2_readl(hsotg, offset) & mask))
1039 * Initializes the FSLSPClkSel field of the HCFG register depending on the
1042 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
1046 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1047 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1048 hsotg->params.ulpi_fs_ls) ||
1049 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1050 /* Full speed PHY */
1051 val = HCFG_FSLSPCLKSEL_48_MHZ;
1053 /* High speed PHY running at full speed or high speed */
1054 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
1057 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
1058 hcfg = dwc2_readl(hsotg, HCFG);
1059 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
1060 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
1061 dwc2_writel(hsotg, hcfg, HCFG);
1064 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1066 u32 usbcfg, ggpio, i2cctl;
1070 * core_init() is now called on every switch so only call the
1071 * following for the first time through
1074 dev_dbg(hsotg->dev, "FS PHY selected\n");
1076 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1077 if (!(usbcfg & GUSBCFG_PHYSEL)) {
1078 usbcfg |= GUSBCFG_PHYSEL;
1079 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1081 /* Reset after a PHY select */
1082 retval = dwc2_core_reset(hsotg, false);
1086 "%s: Reset failed, aborting", __func__);
1091 if (hsotg->params.activate_stm_fs_transceiver) {
1092 ggpio = dwc2_readl(hsotg, GGPIO);
1093 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1094 dev_dbg(hsotg->dev, "Activating transceiver\n");
1096 * STM32F4x9 uses the GGPIO register as general
1097 * core configuration register.
1099 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1100 dwc2_writel(hsotg, ggpio, GGPIO);
1106 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1107 * do this on HNP Dev/Host mode switches (done in dev_init and
1110 if (dwc2_is_host_mode(hsotg))
1111 dwc2_init_fs_ls_pclk_sel(hsotg);
1113 if (hsotg->params.i2c_enable) {
1114 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1116 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
1117 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1118 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1119 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1121 /* Program GI2CCTL.I2CEn */
1122 i2cctl = dwc2_readl(hsotg, GI2CCTL);
1123 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1124 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1125 i2cctl &= ~GI2CCTL_I2CEN;
1126 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1127 i2cctl |= GI2CCTL_I2CEN;
1128 dwc2_writel(hsotg, i2cctl, GI2CCTL);
1134 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1136 u32 usbcfg, usbcfg_old;
1142 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1143 usbcfg_old = usbcfg;
1146 * HS PHY parameters. These parameters are preserved during soft reset
1147 * so only program the first time. Do a soft reset immediately after
1150 switch (hsotg->params.phy_type) {
1151 case DWC2_PHY_TYPE_PARAM_ULPI:
1152 /* ULPI interface */
1153 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1154 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1155 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1156 if (hsotg->params.phy_ulpi_ddr)
1157 usbcfg |= GUSBCFG_DDRSEL;
1159 /* Set external VBUS indicator as needed. */
1160 if (hsotg->params.oc_disable)
1161 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1162 GUSBCFG_INDICATORPASSTHROUGH);
1164 case DWC2_PHY_TYPE_PARAM_UTMI:
1165 /* UTMI+ interface */
1166 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1167 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1168 if (hsotg->params.phy_utmi_width == 16)
1169 usbcfg |= GUSBCFG_PHYIF16;
1172 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1176 if (usbcfg != usbcfg_old) {
1177 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1179 /* Reset after setting the PHY parameters */
1180 retval = dwc2_core_reset(hsotg, false);
1183 "%s: Reset failed, aborting", __func__);
1191 static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1195 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1198 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1200 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1201 if (hsotg->params.phy_utmi_width == 16)
1202 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1204 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1206 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1209 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1214 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1215 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1216 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1217 /* If FS/LS mode with FS/LS PHY */
1218 retval = dwc2_fs_phy_init(hsotg, select_phy);
1222 /* High speed PHY */
1223 retval = dwc2_hs_phy_init(hsotg, select_phy);
1227 if (dwc2_is_device_mode(hsotg))
1228 dwc2_set_turnaround_time(hsotg);
1231 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1232 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1233 hsotg->params.ulpi_fs_ls) {
1234 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1235 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1236 usbcfg |= GUSBCFG_ULPI_FS_LS;
1237 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1238 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1240 usbcfg = dwc2_readl(hsotg, GUSBCFG);
1241 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1242 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1243 dwc2_writel(hsotg, usbcfg, GUSBCFG);
1249 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1250 MODULE_AUTHOR("Synopsys, Inc.");
1251 MODULE_LICENSE("Dual BSD/GPL");