1 // SPDX-License-Identifier: GPL-2.0
3 * host.c - ChipIdea USB host controller driver
5 * Copyright (c) 2012 Intel Corporation
7 * Author: Alexander Shishkin
10 #include <linux/kernel.h>
12 #include <linux/usb.h>
13 #include <linux/usb/hcd.h>
14 #include <linux/usb/chipidea.h>
15 #include <linux/regulator/consumer.h>
17 #include "../host/ehci.h"
23 static struct hc_driver __read_mostly ci_ehci_hc_driver;
24 static int (*orig_bus_suspend)(struct usb_hcd *hcd);
27 struct regulator *reg_vbus;
31 static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
33 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
34 struct ehci_ci_priv *priv = (struct ehci_ci_priv *)ehci->priv;
35 struct device *dev = hcd->self.controller;
36 struct ci_hdrc *ci = dev_get_drvdata(dev);
38 int port = HCS_N_PORTS(ehci->hcs_params);
40 if (priv->reg_vbus && enable != priv->enabled) {
43 "Not support multi-port regulator control\n");
47 ret = regulator_enable(priv->reg_vbus);
49 ret = regulator_disable(priv->reg_vbus);
52 "Failed to %s vbus regulator, ret=%d\n",
53 enable ? "enable" : "disable", ret);
56 priv->enabled = enable;
59 if (enable && (ci->platdata->phy_mode == USBPHY_INTERFACE_MODE_HSIC)) {
61 * Marvell 28nm HSIC PHY requires forcing the port to HS mode.
62 * As HSIC is always HS, this should be safe for others.
64 hw_port_test_set(ci, 5);
65 hw_port_test_set(ci, 0);
70 static int ehci_ci_reset(struct usb_hcd *hcd)
72 struct device *dev = hcd->self.controller;
73 struct ci_hdrc *ci = dev_get_drvdata(dev);
74 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
77 ret = ehci_setup(hcd);
81 ehci->need_io_watchdog = 0;
83 if (ci->platdata->notify_event) {
84 ret = ci->platdata->notify_event(ci,
85 CI_HDRC_CONTROLLER_RESET_EVENT);
90 ci_platform_configure(ci);
95 static const struct ehci_driver_overrides ehci_ci_overrides = {
96 .extra_priv_size = sizeof(struct ehci_ci_priv),
97 .port_power = ehci_ci_portpower,
98 .reset = ehci_ci_reset,
101 static irqreturn_t host_irq(struct ci_hdrc *ci)
103 return usb_hcd_irq(ci->irq, ci->hcd);
106 static int host_start(struct ci_hdrc *ci)
109 struct ehci_hcd *ehci;
110 struct ehci_ci_priv *priv;
116 hcd = __usb_create_hcd(&ci_ehci_hc_driver, ci->dev->parent,
117 ci->dev, dev_name(ci->dev), NULL);
121 dev_set_drvdata(ci->dev, ci);
122 hcd->rsrc_start = ci->hw_bank.phys;
123 hcd->rsrc_len = ci->hw_bank.size;
124 hcd->regs = ci->hw_bank.abs;
127 hcd->power_budget = ci->platdata->power_budget;
128 hcd->tpl_support = ci->platdata->tpl_support;
129 if (ci->phy || ci->usb_phy) {
130 hcd->skip_phy_initialization = 1;
132 hcd->usb_phy = ci->usb_phy;
135 ehci = hcd_to_ehci(hcd);
136 ehci->caps = ci->hw_bank.cap;
137 ehci->has_hostpc = ci->hw_bank.lpm;
138 ehci->has_tdi_phy_lpm = ci->hw_bank.lpm;
139 ehci->imx28_write_fix = ci->imx28_write_fix;
141 priv = (struct ehci_ci_priv *)ehci->priv;
142 priv->reg_vbus = NULL;
144 if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci)) {
145 if (ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON) {
146 ret = regulator_enable(ci->platdata->reg_vbus);
149 "Failed to enable vbus regulator, ret=%d\n",
154 priv->reg_vbus = ci->platdata->reg_vbus;
158 ret = usb_add_hcd(hcd, 0, 0);
162 struct usb_otg *otg = &ci->otg;
166 if (ci_otg_is_fsm_mode(ci)) {
167 otg->host = &hcd->self;
168 hcd->self.otg_port = 1;
175 if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci) &&
176 (ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON))
177 regulator_disable(ci->platdata->reg_vbus);
184 static void host_stop(struct ci_hdrc *ci)
186 struct usb_hcd *hcd = ci->hcd;
189 if (ci->platdata->notify_event)
190 ci->platdata->notify_event(ci,
191 CI_HDRC_CONTROLLER_STOPPED_EVENT);
193 ci->role = CI_ROLE_END;
194 synchronize_irq(ci->irq);
196 if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci) &&
197 (ci->platdata->flags & CI_HDRC_TURN_VBUS_EARLY_ON))
198 regulator_disable(ci->platdata->reg_vbus);
205 void ci_hdrc_host_destroy(struct ci_hdrc *ci)
207 if (ci->role == CI_ROLE_HOST && ci->hcd)
211 static int ci_ehci_bus_suspend(struct usb_hcd *hcd)
213 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
217 int ret = orig_bus_suspend(hcd);
222 port = HCS_N_PORTS(ehci->hcs_params);
224 u32 __iomem *reg = &ehci->regs->port_status[port];
225 u32 portsc = ehci_readl(ehci, reg);
227 if (portsc & PORT_CONNECT) {
229 * For chipidea, the resume signal will be ended
230 * automatically, so for remote wakeup case, the
231 * usbcmd.rs may not be set before the resume has
232 * ended if other resume paths consumes too much
233 * time (~24ms), in that case, the SOF will not
234 * send out within 3ms after resume ends, then the
235 * high speed device will enter full speed mode.
238 tmp = ehci_readl(ehci, &ehci->regs->command);
240 ehci_writel(ehci, tmp, &ehci->regs->command);
242 * It needs a short delay between set RS bit and PHCD.
244 usleep_range(150, 200);
252 int ci_hdrc_host_init(struct ci_hdrc *ci)
254 struct ci_role_driver *rdrv;
256 if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_HC))
259 rdrv = devm_kzalloc(ci->dev, sizeof(struct ci_role_driver), GFP_KERNEL);
263 rdrv->start = host_start;
264 rdrv->stop = host_stop;
265 rdrv->irq = host_irq;
267 ci->roles[CI_ROLE_HOST] = rdrv;
272 void ci_hdrc_host_driver_init(void)
274 ehci_init_driver(&ci_ehci_hc_driver, &ehci_ci_overrides);
275 orig_bus_suspend = ci_ehci_hc_driver.bus_suspend;
276 ci_ehci_hc_driver.bus_suspend = ci_ehci_bus_suspend;