1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - ChipIdea USB IP core family device controller
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
11 * Description: ChipIdea USB IP core family device controller
13 * This driver is composed of several blocks:
14 * - HW: hardware interface
15 * - DBG: debug facilities (optional)
17 * - ISR: interrupts handling
18 * - ENDPT: endpoint operations (Gadget API)
19 * - GADGET: gadget operations (Gadget API)
20 * - BUS: bus glue code, bus abstraction layer
23 * - STALL_IN: non-empty bulk-in pipes cannot be halted
24 * if defined mass storage compliance succeeds but with warnings
28 * if undefined usbtest 13 fails
29 * - TRACE: enable function tracing (depends on DEBUG)
32 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
33 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
34 * - Normal & LPM support
37 * - OK: 0-12, 13 (STALL_IN defined) & 14
38 * - Not Supported: 15 & 16 (ISO)
41 * - Suspend & Remote Wakeup
43 #include <linux/delay.h>
44 #include <linux/device.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/extcon.h>
47 #include <linux/phy/phy.h>
48 #include <linux/platform_device.h>
49 #include <linux/module.h>
50 #include <linux/idr.h>
51 #include <linux/interrupt.h>
53 #include <linux/kernel.h>
54 #include <linux/slab.h>
55 #include <linux/pm_runtime.h>
56 #include <linux/usb/ch9.h>
57 #include <linux/usb/gadget.h>
58 #include <linux/usb/otg.h>
59 #include <linux/usb/chipidea.h>
60 #include <linux/usb/of.h>
62 #include <linux/regulator/consumer.h>
63 #include <linux/usb/ehci_def.h>
72 /* Controller register map */
73 static const u8 ci_regs_nolpm[] = {
74 [CAP_CAPLENGTH] = 0x00U,
75 [CAP_HCCPARAMS] = 0x08U,
76 [CAP_DCCPARAMS] = 0x24U,
77 [CAP_TESTMODE] = 0x38U,
81 [OP_DEVICEADDR] = 0x14U,
82 [OP_ENDPTLISTADDR] = 0x18U,
84 [OP_BURSTSIZE] = 0x20U,
85 [OP_ULPI_VIEWPORT] = 0x30U,
90 [OP_ENDPTSETUPSTAT] = 0x6CU,
91 [OP_ENDPTPRIME] = 0x70U,
92 [OP_ENDPTFLUSH] = 0x74U,
93 [OP_ENDPTSTAT] = 0x78U,
94 [OP_ENDPTCOMPLETE] = 0x7CU,
95 [OP_ENDPTCTRL] = 0x80U,
98 static const u8 ci_regs_lpm[] = {
99 [CAP_CAPLENGTH] = 0x00U,
100 [CAP_HCCPARAMS] = 0x08U,
101 [CAP_DCCPARAMS] = 0x24U,
102 [CAP_TESTMODE] = 0xFCU,
105 [OP_USBINTR] = 0x08U,
106 [OP_DEVICEADDR] = 0x14U,
107 [OP_ENDPTLISTADDR] = 0x18U,
109 [OP_BURSTSIZE] = 0x20U,
110 [OP_ULPI_VIEWPORT] = 0x30U,
114 [OP_USBMODE] = 0xC8U,
115 [OP_ENDPTSETUPSTAT] = 0xD8U,
116 [OP_ENDPTPRIME] = 0xDCU,
117 [OP_ENDPTFLUSH] = 0xE0U,
118 [OP_ENDPTSTAT] = 0xE4U,
119 [OP_ENDPTCOMPLETE] = 0xE8U,
120 [OP_ENDPTCTRL] = 0xECU,
123 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
127 for (i = 0; i < OP_ENDPTCTRL; i++)
128 ci->hw_bank.regmap[i] =
129 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
130 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
132 for (; i <= OP_LAST; i++)
133 ci->hw_bank.regmap[i] = ci->hw_bank.op +
134 4 * (i - OP_ENDPTCTRL) +
136 ? ci_regs_lpm[OP_ENDPTCTRL]
137 : ci_regs_nolpm[OP_ENDPTCTRL]);
141 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
143 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
144 enum ci_revision rev = CI_REVISION_UNKNOWN;
147 rev = hw_read_id_reg(ci, ID_ID, REVISION)
149 rev += CI_REVISION_20;
150 } else if (ver == 0x0) {
151 rev = CI_REVISION_1X;
158 * hw_read_intr_enable: returns interrupt enable register
160 * @ci: the controller
162 * This function returns register data
164 u32 hw_read_intr_enable(struct ci_hdrc *ci)
166 return hw_read(ci, OP_USBINTR, ~0);
170 * hw_read_intr_status: returns interrupt status register
172 * @ci: the controller
174 * This function returns register data
176 u32 hw_read_intr_status(struct ci_hdrc *ci)
178 return hw_read(ci, OP_USBSTS, ~0);
182 * hw_port_test_set: writes port test mode (execute without interruption)
185 * This function returns an error code
187 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
189 const u8 TEST_MODE_MAX = 7;
191 if (mode > TEST_MODE_MAX)
194 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
199 * hw_port_test_get: reads port test mode value
201 * @ci: the controller
203 * This function returns port test mode value
205 u8 hw_port_test_get(struct ci_hdrc *ci)
207 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
210 static void hw_wait_phy_stable(void)
213 * The phy needs some delay to output the stable status from low
214 * power mode. And for OTGSC, the status inputs are debounced
215 * using a 1 ms time constant, so, delay 2ms for controller to get
216 * the stable status, like vbus and id when the phy leaves low power.
218 usleep_range(2000, 2500);
221 /* The PHY enters/leaves low power mode */
222 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
224 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
225 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
228 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
229 PORTSC_PHCD(ci->hw_bank.lpm));
230 else if (!enable && lpm)
231 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
235 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
239 /* bank is a module variable */
240 ci->hw_bank.abs = base;
242 ci->hw_bank.cap = ci->hw_bank.abs;
243 ci->hw_bank.cap += ci->platdata->capoffset;
244 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
246 hw_alloc_regmap(ci, false);
247 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
248 __ffs(HCCPARAMS_LEN);
249 ci->hw_bank.lpm = reg;
251 hw_alloc_regmap(ci, !!reg);
252 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
253 ci->hw_bank.size += OP_LAST;
254 ci->hw_bank.size /= sizeof(u32);
256 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
257 __ffs(DCCPARAMS_DEN);
258 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
260 if (ci->hw_ep_max > ENDPT_MAX)
263 ci_hdrc_enter_lpm(ci, false);
265 /* Disable all interrupts bits */
266 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
268 /* Clear all interrupts status bits*/
269 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
271 ci->rev = ci_get_revision(ci);
274 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
275 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
277 /* setup lock mode ? */
279 /* ENDPTSETUPSTAT is '0' by default */
281 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
286 void hw_phymode_configure(struct ci_hdrc *ci)
288 u32 portsc, lpm, sts = 0;
290 switch (ci->platdata->phy_mode) {
291 case USBPHY_INTERFACE_MODE_UTMI:
292 portsc = PORTSC_PTS(PTS_UTMI);
293 lpm = DEVLC_PTS(PTS_UTMI);
295 case USBPHY_INTERFACE_MODE_UTMIW:
296 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
297 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
299 case USBPHY_INTERFACE_MODE_ULPI:
300 portsc = PORTSC_PTS(PTS_ULPI);
301 lpm = DEVLC_PTS(PTS_ULPI);
303 case USBPHY_INTERFACE_MODE_SERIAL:
304 portsc = PORTSC_PTS(PTS_SERIAL);
305 lpm = DEVLC_PTS(PTS_SERIAL);
308 case USBPHY_INTERFACE_MODE_HSIC:
309 portsc = PORTSC_PTS(PTS_HSIC);
310 lpm = DEVLC_PTS(PTS_HSIC);
316 if (ci->hw_bank.lpm) {
317 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
319 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
321 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
323 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
326 EXPORT_SYMBOL_GPL(hw_phymode_configure);
329 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
331 * @ci: the controller
333 * This function returns an error code if the phy failed to init
335 static int _ci_usb_phy_init(struct ci_hdrc *ci)
340 ret = phy_init(ci->phy);
344 ret = phy_power_on(ci->phy);
350 ret = usb_phy_init(ci->usb_phy);
357 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
359 * @ci: the controller
361 static void ci_usb_phy_exit(struct ci_hdrc *ci)
363 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
367 phy_power_off(ci->phy);
370 usb_phy_shutdown(ci->usb_phy);
375 * ci_usb_phy_init: initialize phy according to different phy type
376 * @ci: the controller
378 * This function returns an error code if usb_phy_init has failed
380 static int ci_usb_phy_init(struct ci_hdrc *ci)
384 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
387 switch (ci->platdata->phy_mode) {
388 case USBPHY_INTERFACE_MODE_UTMI:
389 case USBPHY_INTERFACE_MODE_UTMIW:
390 case USBPHY_INTERFACE_MODE_HSIC:
391 ret = _ci_usb_phy_init(ci);
393 hw_wait_phy_stable();
396 hw_phymode_configure(ci);
398 case USBPHY_INTERFACE_MODE_ULPI:
399 case USBPHY_INTERFACE_MODE_SERIAL:
400 hw_phymode_configure(ci);
401 ret = _ci_usb_phy_init(ci);
406 ret = _ci_usb_phy_init(ci);
408 hw_wait_phy_stable();
416 * ci_platform_configure: do controller configure
417 * @ci: the controller
420 void ci_platform_configure(struct ci_hdrc *ci)
422 bool is_device_mode, is_host_mode;
424 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
425 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
427 if (is_device_mode) {
428 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
430 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
431 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
436 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
438 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
439 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
443 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
445 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
447 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
450 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
451 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
453 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
455 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
456 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
457 ci->platdata->ahb_burst_config);
459 /* override burst size, take effect only when ahb_burst_config is 0 */
460 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
461 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
462 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
463 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
465 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
466 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
467 ci->platdata->rx_burst_size);
472 * hw_controller_reset: do controller reset
473 * @ci: the controller
475 * This function returns an error code
477 static int hw_controller_reset(struct ci_hdrc *ci)
481 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
482 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
492 * hw_device_reset: resets chip (execute without interruption)
493 * @ci: the controller
495 * This function returns an error code
497 int hw_device_reset(struct ci_hdrc *ci)
501 /* should flush & stop before reset */
502 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
503 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
505 ret = hw_controller_reset(ci);
507 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
511 if (ci->platdata->notify_event) {
512 ret = ci->platdata->notify_event(ci,
513 CI_HDRC_CONTROLLER_RESET_EVENT);
518 /* USBMODE should be configured step by step */
519 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
520 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
522 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
524 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
525 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
526 pr_err("lpm = %i", ci->hw_bank.lpm);
530 ci_platform_configure(ci);
535 static irqreturn_t ci_irq_handler(int irq, void *data)
537 struct ci_hdrc *ci = data;
538 irqreturn_t ret = IRQ_NONE;
542 disable_irq_nosync(irq);
543 ci->wakeup_int = true;
544 pm_runtime_get(ci->dev);
549 otgsc = hw_read_otgsc(ci, ~0);
550 if (ci_otg_is_fsm_mode(ci)) {
551 ret = ci_otg_fsm_irq(ci);
552 if (ret == IRQ_HANDLED)
558 * Handle id change interrupt, it indicates device/host function
561 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
563 /* Clear ID change irq status */
564 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
565 ci_otg_queue_work(ci);
570 * Handle vbus change interrupt, it indicates device connection
571 * and disconnection events.
573 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
574 ci->b_sess_valid_event = true;
576 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
577 ci_otg_queue_work(ci);
581 /* Handle device/host interrupt */
582 if (ci->role != CI_ROLE_END)
583 ret = ci_role(ci)->irq(ci);
588 static void ci_irq(struct ci_hdrc *ci)
592 local_irq_save(flags);
593 ci_irq_handler(ci->irq, ci);
594 local_irq_restore(flags);
597 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
600 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
601 struct ci_hdrc *ci = cbl->ci;
603 cbl->connected = event;
610 static int ci_get_platdata(struct device *dev,
611 struct ci_hdrc_platform_data *platdata)
613 struct extcon_dev *ext_vbus, *ext_id;
614 struct ci_hdrc_cable *cable;
617 if (!platdata->phy_mode)
618 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
620 if (!platdata->dr_mode)
621 platdata->dr_mode = usb_get_dr_mode(dev);
623 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
624 platdata->dr_mode = USB_DR_MODE_OTG;
626 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
627 /* Get the vbus regulator */
628 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
629 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
630 return -EPROBE_DEFER;
631 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
632 /* no vbus regulator is needed */
633 platdata->reg_vbus = NULL;
634 } else if (IS_ERR(platdata->reg_vbus)) {
635 dev_err(dev, "Getting regulator error: %ld\n",
636 PTR_ERR(platdata->reg_vbus));
637 return PTR_ERR(platdata->reg_vbus);
639 /* Get TPL support */
640 if (!platdata->tpl_support)
641 platdata->tpl_support =
642 of_usb_host_tpl_support(dev->of_node);
645 if (platdata->dr_mode == USB_DR_MODE_OTG) {
646 /* We can support HNP and SRP of OTG 2.0 */
647 platdata->ci_otg_caps.otg_rev = 0x0200;
648 platdata->ci_otg_caps.hnp_support = true;
649 platdata->ci_otg_caps.srp_support = true;
651 /* Update otg capabilities by DT properties */
652 ret = of_usb_update_otg_caps(dev->of_node,
653 &platdata->ci_otg_caps);
658 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
659 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
661 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
662 &platdata->phy_clkgate_delay_us);
664 platdata->itc_setting = 1;
666 of_property_read_u32(dev->of_node, "itc-setting",
667 &platdata->itc_setting);
669 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
670 &platdata->ahb_burst_config);
672 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
673 } else if (ret != -EINVAL) {
674 dev_err(dev, "failed to get ahb-burst-config\n");
678 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
679 &platdata->tx_burst_size);
681 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
682 } else if (ret != -EINVAL) {
683 dev_err(dev, "failed to get tx-burst-size-dword\n");
687 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
688 &platdata->rx_burst_size);
690 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
691 } else if (ret != -EINVAL) {
692 dev_err(dev, "failed to get rx-burst-size-dword\n");
696 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
697 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
699 ext_id = ERR_PTR(-ENODEV);
700 ext_vbus = ERR_PTR(-ENODEV);
701 if (of_property_read_bool(dev->of_node, "extcon")) {
702 /* Each one of them is not mandatory */
703 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
704 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
705 return PTR_ERR(ext_vbus);
707 ext_id = extcon_get_edev_by_phandle(dev, 1);
708 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
709 return PTR_ERR(ext_id);
712 cable = &platdata->vbus_extcon;
713 cable->nb.notifier_call = ci_cable_notifier;
714 cable->edev = ext_vbus;
716 if (!IS_ERR(ext_vbus)) {
717 ret = extcon_get_state(cable->edev, EXTCON_USB);
719 cable->connected = true;
721 cable->connected = false;
724 cable = &platdata->id_extcon;
725 cable->nb.notifier_call = ci_cable_notifier;
726 cable->edev = ext_id;
728 if (!IS_ERR(ext_id)) {
729 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
731 cable->connected = true;
733 cable->connected = false;
738 static int ci_extcon_register(struct ci_hdrc *ci)
740 struct ci_hdrc_cable *id, *vbus;
743 id = &ci->platdata->id_extcon;
745 if (!IS_ERR_OR_NULL(id->edev)) {
746 ret = devm_extcon_register_notifier(ci->dev, id->edev,
747 EXTCON_USB_HOST, &id->nb);
749 dev_err(ci->dev, "register ID failed\n");
754 vbus = &ci->platdata->vbus_extcon;
756 if (!IS_ERR_OR_NULL(vbus->edev)) {
757 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
758 EXTCON_USB, &vbus->nb);
760 dev_err(ci->dev, "register VBUS failed\n");
768 static DEFINE_IDA(ci_ida);
770 struct platform_device *ci_hdrc_add_device(struct device *dev,
771 struct resource *res, int nres,
772 struct ci_hdrc_platform_data *platdata)
774 struct platform_device *pdev;
777 ret = ci_get_platdata(dev, platdata);
781 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
785 pdev = platform_device_alloc("ci_hdrc", id);
791 pdev->dev.parent = dev;
793 ret = platform_device_add_resources(pdev, res, nres);
797 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
801 ret = platform_device_add(pdev);
808 platform_device_put(pdev);
810 ida_simple_remove(&ci_ida, id);
813 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
815 void ci_hdrc_remove_device(struct platform_device *pdev)
818 platform_device_unregister(pdev);
819 ida_simple_remove(&ci_ida, id);
821 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
823 static inline void ci_role_destroy(struct ci_hdrc *ci)
825 ci_hdrc_gadget_destroy(ci);
826 ci_hdrc_host_destroy(ci);
827 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
828 ci_hdrc_otg_destroy(ci);
831 static void ci_get_otg_capable(struct ci_hdrc *ci)
833 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
836 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
837 DCCPARAMS_DC | DCCPARAMS_HC)
838 == (DCCPARAMS_DC | DCCPARAMS_HC));
840 dev_dbg(ci->dev, "It is OTG capable controller\n");
841 /* Disable and clear all OTG irq */
842 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
843 OTGSC_INT_STATUS_BITS);
847 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
850 struct ci_hdrc *ci = dev_get_drvdata(dev);
852 if (ci->role != CI_ROLE_END)
853 return sprintf(buf, "%s\n", ci_role(ci)->name);
858 static ssize_t role_store(struct device *dev,
859 struct device_attribute *attr, const char *buf, size_t n)
861 struct ci_hdrc *ci = dev_get_drvdata(dev);
865 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
866 dev_warn(dev, "Current configuration is not dual-role, quit\n");
870 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
871 if (!strncmp(buf, ci->roles[role]->name,
872 strlen(ci->roles[role]->name)))
875 if (role == CI_ROLE_END)
878 mutex_lock(&ci->mutex);
880 if (role == ci->role) {
881 mutex_unlock(&ci->mutex);
885 pm_runtime_get_sync(dev);
886 disable_irq(ci->irq);
888 ret = ci_role_start(ci, role);
889 if (!ret && ci->role == CI_ROLE_GADGET)
890 ci_handle_vbus_change(ci);
892 pm_runtime_put_sync(dev);
893 mutex_unlock(&ci->mutex);
895 return (ret == 0) ? n : ret;
897 static DEVICE_ATTR_RW(role);
899 static struct attribute *ci_attrs[] = {
904 static const struct attribute_group ci_attr_group = {
908 static int ci_hdrc_probe(struct platform_device *pdev)
910 struct device *dev = &pdev->dev;
912 struct resource *res;
915 enum usb_dr_mode dr_mode;
917 if (!dev_get_platdata(dev)) {
918 dev_err(dev, "platform data missing\n");
922 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
923 base = devm_ioremap_resource(dev, res);
925 return PTR_ERR(base);
927 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
931 spin_lock_init(&ci->lock);
932 mutex_init(&ci->mutex);
934 ci->platdata = dev_get_platdata(dev);
935 ci->imx28_write_fix = !!(ci->platdata->flags &
936 CI_HDRC_IMX28_WRITE_FIX);
937 ci->supports_runtime_pm = !!(ci->platdata->flags &
938 CI_HDRC_SUPPORTS_RUNTIME_PM);
939 platform_set_drvdata(pdev, ci);
941 ret = hw_device_init(ci, base);
943 dev_err(dev, "can't initialize hardware\n");
947 ret = ci_ulpi_init(ci);
951 if (ci->platdata->phy) {
952 ci->phy = ci->platdata->phy;
953 } else if (ci->platdata->usb_phy) {
954 ci->usb_phy = ci->platdata->usb_phy;
956 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent, "phys",
958 ci->phy = devm_phy_get(dev->parent, "usb-phy");
960 /* Fallback to grabbing any registered USB2 PHY */
961 if (IS_ERR(ci->usb_phy) &&
962 PTR_ERR(ci->usb_phy) != -EPROBE_DEFER)
963 ci->usb_phy = devm_usb_get_phy(dev->parent,
966 /* if both generic PHY and USB PHY layers aren't enabled */
967 if (PTR_ERR(ci->phy) == -ENOSYS &&
968 PTR_ERR(ci->usb_phy) == -ENXIO) {
973 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) {
980 else if (IS_ERR(ci->usb_phy))
984 ret = ci_usb_phy_init(ci);
986 dev_err(dev, "unable to init phy: %d\n", ret);
990 ci->hw_bank.phys = res->start;
992 ci->irq = platform_get_irq(pdev, 0);
994 dev_err(dev, "missing IRQ\n");
999 ci_get_otg_capable(ci);
1001 dr_mode = ci->platdata->dr_mode;
1002 /* initialize role(s) before the interrupt is requested */
1003 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1004 ret = ci_hdrc_host_init(ci);
1007 dev_info(dev, "doesn't support host\n");
1013 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1014 ret = ci_hdrc_gadget_init(ci);
1017 dev_info(dev, "doesn't support gadget\n");
1023 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1024 dev_err(dev, "no supported roles\n");
1029 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1030 ret = ci_hdrc_otg_init(ci);
1032 dev_err(dev, "init otg fails, ret = %d\n", ret);
1037 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1039 ci->role = ci_otg_role(ci);
1040 /* Enable ID change irq */
1041 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1044 * If the controller is not OTG capable, but support
1045 * role switch, the defalt role is gadget, and the
1046 * user can switch it through debugfs.
1048 ci->role = CI_ROLE_GADGET;
1051 ci->role = ci->roles[CI_ROLE_HOST]
1056 if (!ci_otg_is_fsm_mode(ci)) {
1057 /* only update vbus status for peripheral */
1058 if (ci->role == CI_ROLE_GADGET)
1059 ci_handle_vbus_change(ci);
1061 ret = ci_role_start(ci, ci->role);
1063 dev_err(dev, "can't start %s role\n",
1069 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
1070 ci->platdata->name, ci);
1074 ret = ci_extcon_register(ci);
1078 if (ci->supports_runtime_pm) {
1079 pm_runtime_set_active(&pdev->dev);
1080 pm_runtime_enable(&pdev->dev);
1081 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1082 pm_runtime_mark_last_busy(ci->dev);
1083 pm_runtime_use_autosuspend(&pdev->dev);
1086 if (ci_otg_is_fsm_mode(ci))
1087 ci_hdrc_otg_fsm_start(ci);
1089 device_set_wakeup_capable(&pdev->dev, true);
1090 dbg_create_files(ci);
1092 ret = sysfs_create_group(&dev->kobj, &ci_attr_group);
1099 dbg_remove_files(ci);
1101 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1102 ci_hdrc_otg_destroy(ci);
1104 ci_hdrc_gadget_destroy(ci);
1106 ci_hdrc_host_destroy(ci);
1108 ci_usb_phy_exit(ci);
1115 static int ci_hdrc_remove(struct platform_device *pdev)
1117 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1119 if (ci->supports_runtime_pm) {
1120 pm_runtime_get_sync(&pdev->dev);
1121 pm_runtime_disable(&pdev->dev);
1122 pm_runtime_put_noidle(&pdev->dev);
1125 dbg_remove_files(ci);
1126 sysfs_remove_group(&ci->dev->kobj, &ci_attr_group);
1127 ci_role_destroy(ci);
1128 ci_hdrc_enter_lpm(ci, true);
1129 ci_usb_phy_exit(ci);
1136 /* Prepare wakeup by SRP before suspend */
1137 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1139 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1140 !hw_read_otgsc(ci, OTGSC_ID)) {
1141 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1143 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1148 /* Handle SRP when wakeup by data pulse */
1149 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1151 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1152 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1153 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1154 ci->fsm.a_srp_det = 1;
1155 ci->fsm.a_bus_drop = 0;
1159 ci_otg_queue_work(ci);
1163 static void ci_controller_suspend(struct ci_hdrc *ci)
1165 disable_irq(ci->irq);
1166 ci_hdrc_enter_lpm(ci, true);
1167 if (ci->platdata->phy_clkgate_delay_us)
1168 usleep_range(ci->platdata->phy_clkgate_delay_us,
1169 ci->platdata->phy_clkgate_delay_us + 50);
1170 usb_phy_set_suspend(ci->usb_phy, 1);
1172 enable_irq(ci->irq);
1176 * Handle the wakeup interrupt triggered by extcon connector
1177 * We need to call ci_irq again for extcon since the first
1178 * interrupt (wakeup int) only let the controller be out of
1179 * low power mode, but not handle any interrupts.
1181 static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1183 struct ci_hdrc_cable *cable_id, *cable_vbus;
1184 u32 otgsc = hw_read_otgsc(ci, ~0);
1186 cable_id = &ci->platdata->id_extcon;
1187 cable_vbus = &ci->platdata->vbus_extcon;
1189 if (!IS_ERR(cable_id->edev) && ci->is_otg &&
1190 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1193 if (!IS_ERR(cable_vbus->edev) && ci->is_otg &&
1194 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1198 static int ci_controller_resume(struct device *dev)
1200 struct ci_hdrc *ci = dev_get_drvdata(dev);
1203 dev_dbg(dev, "at %s\n", __func__);
1210 ci_hdrc_enter_lpm(ci, false);
1212 ret = ci_ulpi_resume(ci);
1217 usb_phy_set_suspend(ci->usb_phy, 0);
1218 usb_phy_set_wakeup(ci->usb_phy, false);
1219 hw_wait_phy_stable();
1223 if (ci->wakeup_int) {
1224 ci->wakeup_int = false;
1225 pm_runtime_mark_last_busy(ci->dev);
1226 pm_runtime_put_autosuspend(ci->dev);
1227 enable_irq(ci->irq);
1228 if (ci_otg_is_fsm_mode(ci))
1229 ci_otg_fsm_wakeup_by_srp(ci);
1230 ci_extcon_wakeup_int(ci);
1236 #ifdef CONFIG_PM_SLEEP
1237 static int ci_suspend(struct device *dev)
1239 struct ci_hdrc *ci = dev_get_drvdata(dev);
1242 flush_workqueue(ci->wq);
1244 * Controller needs to be active during suspend, otherwise the core
1245 * may run resume when the parent is at suspend if other driver's
1246 * suspend fails, it occurs before parent's suspend has not started,
1247 * but the core suspend has finished.
1250 pm_runtime_resume(dev);
1257 if (device_may_wakeup(dev)) {
1258 if (ci_otg_is_fsm_mode(ci))
1259 ci_otg_fsm_suspend_for_srp(ci);
1261 usb_phy_set_wakeup(ci->usb_phy, true);
1262 enable_irq_wake(ci->irq);
1265 ci_controller_suspend(ci);
1270 static int ci_resume(struct device *dev)
1272 struct ci_hdrc *ci = dev_get_drvdata(dev);
1275 if (device_may_wakeup(dev))
1276 disable_irq_wake(ci->irq);
1278 ret = ci_controller_resume(dev);
1282 if (ci->supports_runtime_pm) {
1283 pm_runtime_disable(dev);
1284 pm_runtime_set_active(dev);
1285 pm_runtime_enable(dev);
1290 #endif /* CONFIG_PM_SLEEP */
1292 static int ci_runtime_suspend(struct device *dev)
1294 struct ci_hdrc *ci = dev_get_drvdata(dev);
1296 dev_dbg(dev, "at %s\n", __func__);
1303 if (ci_otg_is_fsm_mode(ci))
1304 ci_otg_fsm_suspend_for_srp(ci);
1306 usb_phy_set_wakeup(ci->usb_phy, true);
1307 ci_controller_suspend(ci);
1312 static int ci_runtime_resume(struct device *dev)
1314 return ci_controller_resume(dev);
1317 #endif /* CONFIG_PM */
1318 static const struct dev_pm_ops ci_pm_ops = {
1319 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1320 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1323 static struct platform_driver ci_hdrc_driver = {
1324 .probe = ci_hdrc_probe,
1325 .remove = ci_hdrc_remove,
1332 static int __init ci_hdrc_platform_register(void)
1334 ci_hdrc_host_driver_init();
1335 return platform_driver_register(&ci_hdrc_driver);
1337 module_init(ci_hdrc_platform_register);
1339 static void __exit ci_hdrc_platform_unregister(void)
1341 platform_driver_unregister(&ci_hdrc_driver);
1343 module_exit(ci_hdrc_platform_unregister);
1345 MODULE_ALIAS("platform:ci_hdrc");
1346 MODULE_LICENSE("GPL v2");
1347 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1348 MODULE_DESCRIPTION("ChipIdea HDRC Driver");