1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - ChipIdea USB IP core family device controller
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
6 * Copyright (C) 2020 NXP
9 * Peter Chen <peter.chen@nxp.com>
12 * - Four transfers are supported, usbtest is passed
13 * - USB Certification for gadget: CH9 and Mass Storage are passed
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/extcon.h>
21 #include <linux/phy/phy.h>
22 #include <linux/platform_device.h>
23 #include <linux/module.h>
24 #include <linux/idr.h>
25 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pinctrl/consumer.h>
31 #include <linux/usb/ch9.h>
32 #include <linux/usb/gadget.h>
33 #include <linux/usb/otg.h>
34 #include <linux/usb/chipidea.h>
35 #include <linux/usb/of.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/usb/ehci_def.h>
47 /* Controller register map */
48 static const u8 ci_regs_nolpm[] = {
49 [CAP_CAPLENGTH] = 0x00U,
50 [CAP_HCCPARAMS] = 0x08U,
51 [CAP_DCCPARAMS] = 0x24U,
52 [CAP_TESTMODE] = 0x38U,
56 [OP_DEVICEADDR] = 0x14U,
57 [OP_ENDPTLISTADDR] = 0x18U,
59 [OP_BURSTSIZE] = 0x20U,
60 [OP_ULPI_VIEWPORT] = 0x30U,
65 [OP_ENDPTSETUPSTAT] = 0x6CU,
66 [OP_ENDPTPRIME] = 0x70U,
67 [OP_ENDPTFLUSH] = 0x74U,
68 [OP_ENDPTSTAT] = 0x78U,
69 [OP_ENDPTCOMPLETE] = 0x7CU,
70 [OP_ENDPTCTRL] = 0x80U,
73 static const u8 ci_regs_lpm[] = {
74 [CAP_CAPLENGTH] = 0x00U,
75 [CAP_HCCPARAMS] = 0x08U,
76 [CAP_DCCPARAMS] = 0x24U,
77 [CAP_TESTMODE] = 0xFCU,
81 [OP_DEVICEADDR] = 0x14U,
82 [OP_ENDPTLISTADDR] = 0x18U,
84 [OP_BURSTSIZE] = 0x20U,
85 [OP_ULPI_VIEWPORT] = 0x30U,
90 [OP_ENDPTSETUPSTAT] = 0xD8U,
91 [OP_ENDPTPRIME] = 0xDCU,
92 [OP_ENDPTFLUSH] = 0xE0U,
93 [OP_ENDPTSTAT] = 0xE4U,
94 [OP_ENDPTCOMPLETE] = 0xE8U,
95 [OP_ENDPTCTRL] = 0xECU,
98 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
102 for (i = 0; i < OP_ENDPTCTRL; i++)
103 ci->hw_bank.regmap[i] =
104 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
105 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
107 for (; i <= OP_LAST; i++)
108 ci->hw_bank.regmap[i] = ci->hw_bank.op +
109 4 * (i - OP_ENDPTCTRL) +
111 ? ci_regs_lpm[OP_ENDPTCTRL]
112 : ci_regs_nolpm[OP_ENDPTCTRL]);
116 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
118 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
119 enum ci_revision rev = CI_REVISION_UNKNOWN;
122 rev = hw_read_id_reg(ci, ID_ID, REVISION)
124 rev += CI_REVISION_20;
125 } else if (ver == 0x0) {
126 rev = CI_REVISION_1X;
133 * hw_read_intr_enable: returns interrupt enable register
135 * @ci: the controller
137 * This function returns register data
139 u32 hw_read_intr_enable(struct ci_hdrc *ci)
141 return hw_read(ci, OP_USBINTR, ~0);
145 * hw_read_intr_status: returns interrupt status register
147 * @ci: the controller
149 * This function returns register data
151 u32 hw_read_intr_status(struct ci_hdrc *ci)
153 return hw_read(ci, OP_USBSTS, ~0);
157 * hw_port_test_set: writes port test mode (execute without interruption)
158 * @ci: the controller
161 * This function returns an error code
163 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
165 const u8 TEST_MODE_MAX = 7;
167 if (mode > TEST_MODE_MAX)
170 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
175 * hw_port_test_get: reads port test mode value
177 * @ci: the controller
179 * This function returns port test mode value
181 u8 hw_port_test_get(struct ci_hdrc *ci)
183 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
186 static void hw_wait_phy_stable(void)
189 * The phy needs some delay to output the stable status from low
190 * power mode. And for OTGSC, the status inputs are debounced
191 * using a 1 ms time constant, so, delay 2ms for controller to get
192 * the stable status, like vbus and id when the phy leaves low power.
194 usleep_range(2000, 2500);
197 /* The PHY enters/leaves low power mode */
198 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
200 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
201 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
204 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
205 PORTSC_PHCD(ci->hw_bank.lpm));
206 else if (!enable && lpm)
207 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
211 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
215 /* bank is a module variable */
216 ci->hw_bank.abs = base;
218 ci->hw_bank.cap = ci->hw_bank.abs;
219 ci->hw_bank.cap += ci->platdata->capoffset;
220 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
222 hw_alloc_regmap(ci, false);
223 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
224 __ffs(HCCPARAMS_LEN);
225 ci->hw_bank.lpm = reg;
227 hw_alloc_regmap(ci, !!reg);
228 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
229 ci->hw_bank.size += OP_LAST;
230 ci->hw_bank.size /= sizeof(u32);
232 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
233 __ffs(DCCPARAMS_DEN);
234 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
236 if (ci->hw_ep_max > ENDPT_MAX)
239 ci_hdrc_enter_lpm(ci, false);
241 /* Disable all interrupts bits */
242 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
244 /* Clear all interrupts status bits*/
245 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
247 ci->rev = ci_get_revision(ci);
250 "revision: %d, lpm: %d; cap: %px op: %px\n",
251 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
253 /* setup lock mode ? */
255 /* ENDPTSETUPSTAT is '0' by default */
257 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
262 void hw_phymode_configure(struct ci_hdrc *ci)
264 u32 portsc, lpm, sts = 0;
266 switch (ci->platdata->phy_mode) {
267 case USBPHY_INTERFACE_MODE_UTMI:
268 portsc = PORTSC_PTS(PTS_UTMI);
269 lpm = DEVLC_PTS(PTS_UTMI);
271 case USBPHY_INTERFACE_MODE_UTMIW:
272 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
273 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
275 case USBPHY_INTERFACE_MODE_ULPI:
276 portsc = PORTSC_PTS(PTS_ULPI);
277 lpm = DEVLC_PTS(PTS_ULPI);
279 case USBPHY_INTERFACE_MODE_SERIAL:
280 portsc = PORTSC_PTS(PTS_SERIAL);
281 lpm = DEVLC_PTS(PTS_SERIAL);
284 case USBPHY_INTERFACE_MODE_HSIC:
285 portsc = PORTSC_PTS(PTS_HSIC);
286 lpm = DEVLC_PTS(PTS_HSIC);
292 if (ci->hw_bank.lpm) {
293 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
295 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
297 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
299 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
302 EXPORT_SYMBOL_GPL(hw_phymode_configure);
305 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
307 * @ci: the controller
309 * This function returns an error code if the phy failed to init
311 static int _ci_usb_phy_init(struct ci_hdrc *ci)
316 ret = phy_init(ci->phy);
320 ret = phy_power_on(ci->phy);
326 ret = usb_phy_init(ci->usb_phy);
333 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
335 * @ci: the controller
337 static void ci_usb_phy_exit(struct ci_hdrc *ci)
339 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
343 phy_power_off(ci->phy);
346 usb_phy_shutdown(ci->usb_phy);
351 * ci_usb_phy_init: initialize phy according to different phy type
352 * @ci: the controller
354 * This function returns an error code if usb_phy_init has failed
356 static int ci_usb_phy_init(struct ci_hdrc *ci)
360 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
363 switch (ci->platdata->phy_mode) {
364 case USBPHY_INTERFACE_MODE_UTMI:
365 case USBPHY_INTERFACE_MODE_UTMIW:
366 case USBPHY_INTERFACE_MODE_HSIC:
367 ret = _ci_usb_phy_init(ci);
369 hw_wait_phy_stable();
372 hw_phymode_configure(ci);
374 case USBPHY_INTERFACE_MODE_ULPI:
375 case USBPHY_INTERFACE_MODE_SERIAL:
376 hw_phymode_configure(ci);
377 ret = _ci_usb_phy_init(ci);
382 ret = _ci_usb_phy_init(ci);
384 hw_wait_phy_stable();
392 * ci_platform_configure: do controller configure
393 * @ci: the controller
396 void ci_platform_configure(struct ci_hdrc *ci)
398 bool is_device_mode, is_host_mode;
400 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
401 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
403 if (is_device_mode) {
404 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
406 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
407 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
412 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
414 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
415 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
419 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
421 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
423 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
426 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
427 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
429 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
431 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
432 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
433 ci->platdata->ahb_burst_config);
435 /* override burst size, take effect only when ahb_burst_config is 0 */
436 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
437 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
438 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
439 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
441 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
442 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
443 ci->platdata->rx_burst_size);
448 * hw_controller_reset: do controller reset
449 * @ci: the controller
451 * This function returns an error code
453 static int hw_controller_reset(struct ci_hdrc *ci)
457 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
458 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
468 * hw_device_reset: resets chip (execute without interruption)
469 * @ci: the controller
471 * This function returns an error code
473 int hw_device_reset(struct ci_hdrc *ci)
477 /* should flush & stop before reset */
478 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
479 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
481 ret = hw_controller_reset(ci);
483 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
487 if (ci->platdata->notify_event) {
488 ret = ci->platdata->notify_event(ci,
489 CI_HDRC_CONTROLLER_RESET_EVENT);
494 /* USBMODE should be configured step by step */
495 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
496 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
498 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
500 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
501 dev_err(ci->dev, "cannot enter in %s device mode\n",
503 dev_err(ci->dev, "lpm = %i\n", ci->hw_bank.lpm);
507 ci_platform_configure(ci);
512 static irqreturn_t ci_irq_handler(int irq, void *data)
514 struct ci_hdrc *ci = data;
515 irqreturn_t ret = IRQ_NONE;
519 disable_irq_nosync(irq);
520 ci->wakeup_int = true;
521 pm_runtime_get(ci->dev);
526 otgsc = hw_read_otgsc(ci, ~0);
527 if (ci_otg_is_fsm_mode(ci)) {
528 ret = ci_otg_fsm_irq(ci);
529 if (ret == IRQ_HANDLED)
535 * Handle id change interrupt, it indicates device/host function
538 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
540 /* Clear ID change irq status */
541 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
542 ci_otg_queue_work(ci);
547 * Handle vbus change interrupt, it indicates device connection
548 * and disconnection events.
550 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
551 ci->b_sess_valid_event = true;
553 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
554 ci_otg_queue_work(ci);
558 /* Handle device/host interrupt */
559 if (ci->role != CI_ROLE_END)
560 ret = ci_role(ci)->irq(ci);
565 static void ci_irq(struct ci_hdrc *ci)
569 local_irq_save(flags);
570 ci_irq_handler(ci->irq, ci);
571 local_irq_restore(flags);
574 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
577 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
578 struct ci_hdrc *ci = cbl->ci;
580 cbl->connected = event;
587 static enum usb_role ci_usb_role_switch_get(struct usb_role_switch *sw)
589 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
593 spin_lock_irqsave(&ci->lock, flags);
594 role = ci_role_to_usb_role(ci);
595 spin_unlock_irqrestore(&ci->lock, flags);
600 static int ci_usb_role_switch_set(struct usb_role_switch *sw,
603 struct ci_hdrc *ci = usb_role_switch_get_drvdata(sw);
604 struct ci_hdrc_cable *cable = NULL;
605 enum usb_role current_role = ci_role_to_usb_role(ci);
606 enum ci_role ci_role = usb_role_to_ci_role(role);
609 if ((ci_role != CI_ROLE_END && !ci->roles[ci_role]) ||
610 (current_role == role))
613 pm_runtime_get_sync(ci->dev);
614 /* Stop current role */
615 spin_lock_irqsave(&ci->lock, flags);
616 if (current_role == USB_ROLE_DEVICE)
617 cable = &ci->platdata->vbus_extcon;
618 else if (current_role == USB_ROLE_HOST)
619 cable = &ci->platdata->id_extcon;
622 cable->changed = true;
623 cable->connected = false;
625 spin_unlock_irqrestore(&ci->lock, flags);
626 if (ci->wq && role != USB_ROLE_NONE)
627 flush_workqueue(ci->wq);
628 spin_lock_irqsave(&ci->lock, flags);
633 /* Start target role */
634 if (role == USB_ROLE_DEVICE)
635 cable = &ci->platdata->vbus_extcon;
636 else if (role == USB_ROLE_HOST)
637 cable = &ci->platdata->id_extcon;
640 cable->changed = true;
641 cable->connected = true;
644 spin_unlock_irqrestore(&ci->lock, flags);
645 pm_runtime_put_sync(ci->dev);
650 static struct usb_role_switch_desc ci_role_switch = {
651 .set = ci_usb_role_switch_set,
652 .get = ci_usb_role_switch_get,
653 .allow_userspace_control = true,
656 static int ci_get_platdata(struct device *dev,
657 struct ci_hdrc_platform_data *platdata)
659 struct extcon_dev *ext_vbus, *ext_id;
660 struct ci_hdrc_cable *cable;
663 if (!platdata->phy_mode)
664 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
666 if (!platdata->dr_mode)
667 platdata->dr_mode = usb_get_dr_mode(dev);
669 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
670 platdata->dr_mode = USB_DR_MODE_OTG;
672 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
673 /* Get the vbus regulator */
674 platdata->reg_vbus = devm_regulator_get_optional(dev, "vbus");
675 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
676 return -EPROBE_DEFER;
677 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
678 /* no vbus regulator is needed */
679 platdata->reg_vbus = NULL;
680 } else if (IS_ERR(platdata->reg_vbus)) {
681 dev_err(dev, "Getting regulator error: %ld\n",
682 PTR_ERR(platdata->reg_vbus));
683 return PTR_ERR(platdata->reg_vbus);
685 /* Get TPL support */
686 if (!platdata->tpl_support)
687 platdata->tpl_support =
688 of_usb_host_tpl_support(dev->of_node);
691 if (platdata->dr_mode == USB_DR_MODE_OTG) {
692 /* We can support HNP and SRP of OTG 2.0 */
693 platdata->ci_otg_caps.otg_rev = 0x0200;
694 platdata->ci_otg_caps.hnp_support = true;
695 platdata->ci_otg_caps.srp_support = true;
697 /* Update otg capabilities by DT properties */
698 ret = of_usb_update_otg_caps(dev->of_node,
699 &platdata->ci_otg_caps);
704 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
705 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
707 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
708 &platdata->phy_clkgate_delay_us);
710 platdata->itc_setting = 1;
712 of_property_read_u32(dev->of_node, "itc-setting",
713 &platdata->itc_setting);
715 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
716 &platdata->ahb_burst_config);
718 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
719 } else if (ret != -EINVAL) {
720 dev_err(dev, "failed to get ahb-burst-config\n");
724 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
725 &platdata->tx_burst_size);
727 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
728 } else if (ret != -EINVAL) {
729 dev_err(dev, "failed to get tx-burst-size-dword\n");
733 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
734 &platdata->rx_burst_size);
736 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
737 } else if (ret != -EINVAL) {
738 dev_err(dev, "failed to get rx-burst-size-dword\n");
742 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
743 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
745 ext_id = ERR_PTR(-ENODEV);
746 ext_vbus = ERR_PTR(-ENODEV);
747 if (of_property_read_bool(dev->of_node, "extcon")) {
748 /* Each one of them is not mandatory */
749 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
750 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
751 return PTR_ERR(ext_vbus);
753 ext_id = extcon_get_edev_by_phandle(dev, 1);
754 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
755 return PTR_ERR(ext_id);
758 cable = &platdata->vbus_extcon;
759 cable->nb.notifier_call = ci_cable_notifier;
760 cable->edev = ext_vbus;
762 if (!IS_ERR(ext_vbus)) {
763 ret = extcon_get_state(cable->edev, EXTCON_USB);
765 cable->connected = true;
767 cable->connected = false;
770 cable = &platdata->id_extcon;
771 cable->nb.notifier_call = ci_cable_notifier;
772 cable->edev = ext_id;
774 if (!IS_ERR(ext_id)) {
775 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
777 cable->connected = true;
779 cable->connected = false;
782 if (device_property_read_bool(dev, "usb-role-switch"))
783 ci_role_switch.fwnode = dev->fwnode;
785 platdata->pctl = devm_pinctrl_get(dev);
786 if (!IS_ERR(platdata->pctl)) {
787 struct pinctrl_state *p;
789 p = pinctrl_lookup_state(platdata->pctl, "default");
791 platdata->pins_default = p;
793 p = pinctrl_lookup_state(platdata->pctl, "host");
795 platdata->pins_host = p;
797 p = pinctrl_lookup_state(platdata->pctl, "device");
799 platdata->pins_device = p;
805 static int ci_extcon_register(struct ci_hdrc *ci)
807 struct ci_hdrc_cable *id, *vbus;
810 id = &ci->platdata->id_extcon;
812 if (!IS_ERR_OR_NULL(id->edev)) {
813 ret = devm_extcon_register_notifier(ci->dev, id->edev,
814 EXTCON_USB_HOST, &id->nb);
816 dev_err(ci->dev, "register ID failed\n");
821 vbus = &ci->platdata->vbus_extcon;
823 if (!IS_ERR_OR_NULL(vbus->edev)) {
824 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
825 EXTCON_USB, &vbus->nb);
827 dev_err(ci->dev, "register VBUS failed\n");
835 static DEFINE_IDA(ci_ida);
837 struct platform_device *ci_hdrc_add_device(struct device *dev,
838 struct resource *res, int nres,
839 struct ci_hdrc_platform_data *platdata)
841 struct platform_device *pdev;
844 ret = ci_get_platdata(dev, platdata);
848 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
852 pdev = platform_device_alloc("ci_hdrc", id);
858 pdev->dev.parent = dev;
860 ret = platform_device_add_resources(pdev, res, nres);
864 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
868 ret = platform_device_add(pdev);
875 platform_device_put(pdev);
877 ida_simple_remove(&ci_ida, id);
880 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
882 void ci_hdrc_remove_device(struct platform_device *pdev)
885 platform_device_unregister(pdev);
886 ida_simple_remove(&ci_ida, id);
888 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
891 * ci_hdrc_query_available_role: get runtime available operation mode
893 * The glue layer can get current operation mode (host/peripheral/otg)
894 * This function should be called after ci core device has created.
896 * @pdev: the platform device of ci core.
898 * Return runtime usb_dr_mode.
900 enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
902 struct ci_hdrc *ci = platform_get_drvdata(pdev);
905 return USB_DR_MODE_UNKNOWN;
906 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
907 return USB_DR_MODE_OTG;
908 else if (ci->roles[CI_ROLE_HOST])
909 return USB_DR_MODE_HOST;
910 else if (ci->roles[CI_ROLE_GADGET])
911 return USB_DR_MODE_PERIPHERAL;
913 return USB_DR_MODE_UNKNOWN;
915 EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
917 static inline void ci_role_destroy(struct ci_hdrc *ci)
919 ci_hdrc_gadget_destroy(ci);
920 ci_hdrc_host_destroy(ci);
921 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
922 ci_hdrc_otg_destroy(ci);
925 static void ci_get_otg_capable(struct ci_hdrc *ci)
927 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
930 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
931 DCCPARAMS_DC | DCCPARAMS_HC)
932 == (DCCPARAMS_DC | DCCPARAMS_HC));
934 dev_dbg(ci->dev, "It is OTG capable controller\n");
935 /* Disable and clear all OTG irq */
936 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
937 OTGSC_INT_STATUS_BITS);
941 static ssize_t role_show(struct device *dev, struct device_attribute *attr,
944 struct ci_hdrc *ci = dev_get_drvdata(dev);
946 if (ci->role != CI_ROLE_END)
947 return sprintf(buf, "%s\n", ci_role(ci)->name);
952 static ssize_t role_store(struct device *dev,
953 struct device_attribute *attr, const char *buf, size_t n)
955 struct ci_hdrc *ci = dev_get_drvdata(dev);
959 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
960 dev_warn(dev, "Current configuration is not dual-role, quit\n");
964 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
965 if (!strncmp(buf, ci->roles[role]->name,
966 strlen(ci->roles[role]->name)))
969 if (role == CI_ROLE_END || role == ci->role)
972 pm_runtime_get_sync(dev);
973 disable_irq(ci->irq);
975 ret = ci_role_start(ci, role);
976 if (!ret && ci->role == CI_ROLE_GADGET)
977 ci_handle_vbus_change(ci);
979 pm_runtime_put_sync(dev);
981 return (ret == 0) ? n : ret;
983 static DEVICE_ATTR_RW(role);
985 static struct attribute *ci_attrs[] = {
989 ATTRIBUTE_GROUPS(ci);
991 static int ci_hdrc_probe(struct platform_device *pdev)
993 struct device *dev = &pdev->dev;
995 struct resource *res;
998 enum usb_dr_mode dr_mode;
1000 if (!dev_get_platdata(dev)) {
1001 dev_err(dev, "platform data missing\n");
1005 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1006 base = devm_ioremap_resource(dev, res);
1008 return PTR_ERR(base);
1010 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
1014 spin_lock_init(&ci->lock);
1016 ci->platdata = dev_get_platdata(dev);
1017 ci->imx28_write_fix = !!(ci->platdata->flags &
1018 CI_HDRC_IMX28_WRITE_FIX);
1019 ci->supports_runtime_pm = !!(ci->platdata->flags &
1020 CI_HDRC_SUPPORTS_RUNTIME_PM);
1021 platform_set_drvdata(pdev, ci);
1023 ret = hw_device_init(ci, base);
1025 dev_err(dev, "can't initialize hardware\n");
1029 ret = ci_ulpi_init(ci);
1033 if (ci->platdata->phy) {
1034 ci->phy = ci->platdata->phy;
1035 } else if (ci->platdata->usb_phy) {
1036 ci->usb_phy = ci->platdata->usb_phy;
1038 /* Look for a generic PHY first */
1039 ci->phy = devm_phy_get(dev->parent, "usb-phy");
1041 if (PTR_ERR(ci->phy) == -EPROBE_DEFER) {
1042 ret = -EPROBE_DEFER;
1044 } else if (IS_ERR(ci->phy)) {
1048 /* Look for a legacy USB PHY from device-tree next */
1050 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent,
1053 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1054 ret = -EPROBE_DEFER;
1056 } else if (IS_ERR(ci->usb_phy)) {
1061 /* Look for any registered legacy USB PHY as last resort */
1062 if (!ci->phy && !ci->usb_phy) {
1063 ci->usb_phy = devm_usb_get_phy(dev->parent,
1066 if (PTR_ERR(ci->usb_phy) == -EPROBE_DEFER) {
1067 ret = -EPROBE_DEFER;
1069 } else if (IS_ERR(ci->usb_phy)) {
1074 /* No USB PHY was found in the end */
1075 if (!ci->phy && !ci->usb_phy) {
1081 ret = ci_usb_phy_init(ci);
1083 dev_err(dev, "unable to init phy: %d\n", ret);
1087 ci->hw_bank.phys = res->start;
1089 ci->irq = platform_get_irq(pdev, 0);
1095 ci_get_otg_capable(ci);
1097 dr_mode = ci->platdata->dr_mode;
1098 /* initialize role(s) before the interrupt is requested */
1099 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
1100 ret = ci_hdrc_host_init(ci);
1103 dev_info(dev, "doesn't support host\n");
1109 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1110 ret = ci_hdrc_gadget_init(ci);
1113 dev_info(dev, "doesn't support gadget\n");
1119 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1120 dev_err(dev, "no supported roles\n");
1125 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1126 ret = ci_hdrc_otg_init(ci);
1128 dev_err(dev, "init otg fails, ret = %d\n", ret);
1133 if (ci_role_switch.fwnode) {
1134 ci_role_switch.driver_data = ci;
1135 ci->role_switch = usb_role_switch_register(dev,
1137 if (IS_ERR(ci->role_switch)) {
1138 ret = PTR_ERR(ci->role_switch);
1143 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1145 ci->role = ci_otg_role(ci);
1146 /* Enable ID change irq */
1147 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1150 * If the controller is not OTG capable, but support
1151 * role switch, the defalt role is gadget, and the
1152 * user can switch it through debugfs.
1154 ci->role = CI_ROLE_GADGET;
1157 ci->role = ci->roles[CI_ROLE_HOST]
1162 if (!ci_otg_is_fsm_mode(ci)) {
1163 /* only update vbus status for peripheral */
1164 if (ci->role == CI_ROLE_GADGET) {
1165 /* Pull down DP for possible charger detection */
1166 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
1167 ci_handle_vbus_change(ci);
1170 ret = ci_role_start(ci, ci->role);
1172 dev_err(dev, "can't start %s role\n",
1178 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
1179 ci->platdata->name, ci);
1183 ret = ci_extcon_register(ci);
1187 if (ci->supports_runtime_pm) {
1188 pm_runtime_set_active(&pdev->dev);
1189 pm_runtime_enable(&pdev->dev);
1190 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1191 pm_runtime_mark_last_busy(ci->dev);
1192 pm_runtime_use_autosuspend(&pdev->dev);
1195 if (ci_otg_is_fsm_mode(ci))
1196 ci_hdrc_otg_fsm_start(ci);
1198 device_set_wakeup_capable(&pdev->dev, true);
1199 dbg_create_files(ci);
1204 if (ci->role_switch)
1205 usb_role_switch_unregister(ci->role_switch);
1207 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1208 ci_hdrc_otg_destroy(ci);
1210 ci_hdrc_gadget_destroy(ci);
1212 ci_hdrc_host_destroy(ci);
1214 ci_usb_phy_exit(ci);
1221 static int ci_hdrc_remove(struct platform_device *pdev)
1223 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1225 if (ci->role_switch)
1226 usb_role_switch_unregister(ci->role_switch);
1228 if (ci->supports_runtime_pm) {
1229 pm_runtime_get_sync(&pdev->dev);
1230 pm_runtime_disable(&pdev->dev);
1231 pm_runtime_put_noidle(&pdev->dev);
1234 dbg_remove_files(ci);
1235 ci_role_destroy(ci);
1236 ci_hdrc_enter_lpm(ci, true);
1237 ci_usb_phy_exit(ci);
1244 /* Prepare wakeup by SRP before suspend */
1245 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1247 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1248 !hw_read_otgsc(ci, OTGSC_ID)) {
1249 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1251 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1256 /* Handle SRP when wakeup by data pulse */
1257 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1259 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1260 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1261 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1262 ci->fsm.a_srp_det = 1;
1263 ci->fsm.a_bus_drop = 0;
1267 ci_otg_queue_work(ci);
1271 static void ci_controller_suspend(struct ci_hdrc *ci)
1273 disable_irq(ci->irq);
1274 ci_hdrc_enter_lpm(ci, true);
1275 if (ci->platdata->phy_clkgate_delay_us)
1276 usleep_range(ci->platdata->phy_clkgate_delay_us,
1277 ci->platdata->phy_clkgate_delay_us + 50);
1278 usb_phy_set_suspend(ci->usb_phy, 1);
1280 enable_irq(ci->irq);
1284 * Handle the wakeup interrupt triggered by extcon connector
1285 * We need to call ci_irq again for extcon since the first
1286 * interrupt (wakeup int) only let the controller be out of
1287 * low power mode, but not handle any interrupts.
1289 static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1291 struct ci_hdrc_cable *cable_id, *cable_vbus;
1292 u32 otgsc = hw_read_otgsc(ci, ~0);
1294 cable_id = &ci->platdata->id_extcon;
1295 cable_vbus = &ci->platdata->vbus_extcon;
1297 if (!IS_ERR(cable_id->edev) && ci->is_otg &&
1298 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1301 if (!IS_ERR(cable_vbus->edev) && ci->is_otg &&
1302 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1306 static int ci_controller_resume(struct device *dev)
1308 struct ci_hdrc *ci = dev_get_drvdata(dev);
1311 dev_dbg(dev, "at %s\n", __func__);
1318 ci_hdrc_enter_lpm(ci, false);
1320 ret = ci_ulpi_resume(ci);
1325 usb_phy_set_suspend(ci->usb_phy, 0);
1326 usb_phy_set_wakeup(ci->usb_phy, false);
1327 hw_wait_phy_stable();
1331 if (ci->wakeup_int) {
1332 ci->wakeup_int = false;
1333 pm_runtime_mark_last_busy(ci->dev);
1334 pm_runtime_put_autosuspend(ci->dev);
1335 enable_irq(ci->irq);
1336 if (ci_otg_is_fsm_mode(ci))
1337 ci_otg_fsm_wakeup_by_srp(ci);
1338 ci_extcon_wakeup_int(ci);
1344 #ifdef CONFIG_PM_SLEEP
1345 static int ci_suspend(struct device *dev)
1347 struct ci_hdrc *ci = dev_get_drvdata(dev);
1350 flush_workqueue(ci->wq);
1352 * Controller needs to be active during suspend, otherwise the core
1353 * may run resume when the parent is at suspend if other driver's
1354 * suspend fails, it occurs before parent's suspend has not started,
1355 * but the core suspend has finished.
1358 pm_runtime_resume(dev);
1365 if (device_may_wakeup(dev)) {
1366 if (ci_otg_is_fsm_mode(ci))
1367 ci_otg_fsm_suspend_for_srp(ci);
1369 usb_phy_set_wakeup(ci->usb_phy, true);
1370 enable_irq_wake(ci->irq);
1373 ci_controller_suspend(ci);
1378 static int ci_resume(struct device *dev)
1380 struct ci_hdrc *ci = dev_get_drvdata(dev);
1383 if (device_may_wakeup(dev))
1384 disable_irq_wake(ci->irq);
1386 ret = ci_controller_resume(dev);
1390 if (ci->supports_runtime_pm) {
1391 pm_runtime_disable(dev);
1392 pm_runtime_set_active(dev);
1393 pm_runtime_enable(dev);
1398 #endif /* CONFIG_PM_SLEEP */
1400 static int ci_runtime_suspend(struct device *dev)
1402 struct ci_hdrc *ci = dev_get_drvdata(dev);
1404 dev_dbg(dev, "at %s\n", __func__);
1411 if (ci_otg_is_fsm_mode(ci))
1412 ci_otg_fsm_suspend_for_srp(ci);
1414 usb_phy_set_wakeup(ci->usb_phy, true);
1415 ci_controller_suspend(ci);
1420 static int ci_runtime_resume(struct device *dev)
1422 return ci_controller_resume(dev);
1425 #endif /* CONFIG_PM */
1426 static const struct dev_pm_ops ci_pm_ops = {
1427 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1428 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1431 static struct platform_driver ci_hdrc_driver = {
1432 .probe = ci_hdrc_probe,
1433 .remove = ci_hdrc_remove,
1437 .dev_groups = ci_groups,
1441 static int __init ci_hdrc_platform_register(void)
1443 ci_hdrc_host_driver_init();
1444 return platform_driver_register(&ci_hdrc_driver);
1446 module_init(ci_hdrc_platform_register);
1448 static void __exit ci_hdrc_platform_unregister(void)
1450 platform_driver_unregister(&ci_hdrc_driver);
1452 module_exit(ci_hdrc_platform_unregister);
1454 MODULE_ALIAS("platform:ci_hdrc");
1455 MODULE_LICENSE("GPL v2");
1456 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1457 MODULE_DESCRIPTION("ChipIdea HDRC Driver");