1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Universal Flash Storage Host controller Platform bus based glue driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_opp.h>
15 #include <linux/pm_runtime.h>
18 #include <ufs/ufshcd.h>
19 #include "ufshcd-pltfrm.h"
20 #include <ufs/unipro.h>
22 #define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2
24 static int ufshcd_parse_clock_info(struct ufs_hba *hba)
29 struct device *dev = hba->dev;
30 struct device_node *np = dev->of_node;
33 struct ufs_clk_info *clki;
40 cnt = of_property_count_strings(np, "clock-names");
41 if (!cnt || (cnt == -EINVAL)) {
42 dev_info(dev, "%s: Unable to find clocks, assuming enabled\n",
45 dev_err(dev, "%s: count clock strings failed, err %d\n",
53 if (!of_get_property(np, "freq-table-hz", &len)) {
54 dev_info(dev, "freq-table-hz property not specified\n");
61 sz = len / sizeof(*clkfreq);
63 dev_err(dev, "%s len mismatch\n", "freq-table-hz");
68 clkfreq = devm_kcalloc(dev, sz, sizeof(*clkfreq),
75 ret = of_property_read_u32_array(np, "freq-table-hz",
77 if (ret && (ret != -EINVAL)) {
78 dev_err(dev, "%s: error reading array %d\n",
79 "freq-table-hz", ret);
83 for (i = 0; i < sz; i += 2) {
84 ret = of_property_read_string_index(np, "clock-names", i/2,
89 clki = devm_kzalloc(dev, sizeof(*clki), GFP_KERNEL);
95 clki->min_freq = clkfreq[i];
96 clki->max_freq = clkfreq[i+1];
97 clki->name = devm_kstrdup(dev, name, GFP_KERNEL);
103 if (!strcmp(name, "ref_clk"))
104 clki->keep_link_active = true;
105 dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",
106 clki->min_freq, clki->max_freq, clki->name);
107 list_add_tail(&clki->list, &hba->clk_list_head);
113 static bool phandle_exists(const struct device_node *np,
114 const char *phandle_name, int index)
116 struct device_node *parse_np = of_parse_phandle(np, phandle_name, index);
119 of_node_put(parse_np);
121 return parse_np != NULL;
124 #define MAX_PROP_SIZE 32
125 int ufshcd_populate_vreg(struct device *dev, const char *name,
126 struct ufs_vreg **out_vreg, bool skip_current)
128 char prop_name[MAX_PROP_SIZE];
129 struct ufs_vreg *vreg = NULL;
130 struct device_node *np = dev->of_node;
133 dev_err(dev, "%s: non DT initialization\n", __func__);
137 snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", name);
138 if (!phandle_exists(np, prop_name, 0)) {
139 dev_info(dev, "%s: Unable to find %s regulator, assuming enabled\n",
140 __func__, prop_name);
144 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
148 vreg->name = devm_kstrdup(dev, name, GFP_KERNEL);
157 snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name);
158 if (of_property_read_u32(np, prop_name, &vreg->max_uA)) {
159 dev_info(dev, "%s: unable to find %s\n", __func__, prop_name);
166 EXPORT_SYMBOL_GPL(ufshcd_populate_vreg);
169 * ufshcd_parse_regulator_info - get regulator info from device tree
170 * @hba: per adapter instance
172 * Get regulator info from device tree for vcc, vccq, vccq2 power supplies.
173 * If any of the supplies are not defined it is assumed that they are always-on
174 * and hence return zero. If the property is defined but parsing is failed
175 * then return corresponding error.
177 * Return: 0 upon success; < 0 upon failure.
179 static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
182 struct device *dev = hba->dev;
183 struct ufs_vreg_info *info = &hba->vreg_info;
185 err = ufshcd_populate_vreg(dev, "vdd-hba", &info->vdd_hba, true);
189 err = ufshcd_populate_vreg(dev, "vcc", &info->vcc, false);
193 err = ufshcd_populate_vreg(dev, "vccq", &info->vccq, false);
197 err = ufshcd_populate_vreg(dev, "vccq2", &info->vccq2, false);
202 static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
204 struct device *dev = hba->dev;
207 ret = of_property_read_u32(dev->of_node, "lanes-per-direction",
208 &hba->lanes_per_direction);
211 "%s: failed to read lanes-per-direction, ret=%d\n",
213 hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION;
218 * ufshcd_parse_clock_min_max_freq - Parse MIN and MAX clocks freq
219 * @hba: per adapter instance
221 * This function parses MIN and MAX frequencies of all clocks required
222 * by the host drivers.
224 * Returns 0 for success and non-zero for failure
226 static int ufshcd_parse_clock_min_max_freq(struct ufs_hba *hba)
228 struct list_head *head = &hba->clk_list_head;
229 struct ufs_clk_info *clki;
230 struct dev_pm_opp *opp;
234 list_for_each_entry(clki, head, list) {
238 clki->clk = devm_clk_get(hba->dev, clki->name);
239 if (IS_ERR(clki->clk))
244 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, &freq, idx);
246 dev_err(hba->dev, "Failed to find OPP for MAX frequency\n");
249 clki->max_freq = dev_pm_opp_get_freq_indexed(opp, idx);
254 opp = dev_pm_opp_find_freq_ceil_indexed(hba->dev, &freq, idx);
256 dev_err(hba->dev, "Failed to find OPP for MIN frequency\n");
259 clki->min_freq = dev_pm_opp_get_freq_indexed(opp, idx++);
266 static int ufshcd_parse_operating_points(struct ufs_hba *hba)
268 struct device *dev = hba->dev;
269 struct device_node *np = dev->of_node;
270 struct dev_pm_opp_config config = {};
271 struct ufs_clk_info *clki;
272 const char **clk_names;
275 if (!of_find_property(np, "operating-points-v2", NULL))
278 if (of_find_property(np, "freq-table-hz", NULL)) {
279 dev_err(dev, "%s: operating-points and freq-table-hz are incompatible\n",
284 cnt = of_property_count_strings(np, "clock-names");
286 dev_err(dev, "%s: Missing clock-names\n", __func__);
290 /* OPP expects clk_names to be NULL terminated */
291 clk_names = devm_kcalloc(dev, cnt + 1, sizeof(*clk_names), GFP_KERNEL);
296 * We still need to get reference to all clocks as the UFS core uses
299 for (i = 0; i < cnt; i++) {
300 ret = of_property_read_string_index(np, "clock-names", i,
305 clki = devm_kzalloc(dev, sizeof(*clki), GFP_KERNEL);
309 clki->name = devm_kstrdup(dev, clk_names[i], GFP_KERNEL);
313 if (!strcmp(clk_names[i], "ref_clk"))
314 clki->keep_link_active = true;
316 list_add_tail(&clki->list, &hba->clk_list_head);
319 config.clk_names = clk_names,
320 config.config_clks = ufshcd_opp_config_clks;
322 ret = devm_pm_opp_set_config(dev, &config);
326 ret = devm_pm_opp_of_add_table(dev);
328 dev_err(dev, "Failed to add OPP table: %d\n", ret);
332 ret = ufshcd_parse_clock_min_max_freq(hba);
336 hba->use_pm_opp = true;
342 * ufshcd_negotiate_pwr_params - find power mode settings that are supported by
343 * both the controller and the device
344 * @host_params: pointer to host parameters
345 * @dev_max: pointer to device attributes
346 * @agreed_pwr: returned agreed attributes
348 * Return: 0 on success, non-zero value on failure.
350 int ufshcd_negotiate_pwr_params(const struct ufs_host_params *host_params,
351 const struct ufs_pa_layer_attr *dev_max,
352 struct ufs_pa_layer_attr *agreed_pwr)
356 bool is_dev_sup_hs = false;
357 bool is_host_max_hs = false;
359 if (dev_max->pwr_rx == FAST_MODE)
360 is_dev_sup_hs = true;
362 if (host_params->desired_working_mode == UFS_HS_MODE) {
363 is_host_max_hs = true;
364 min_host_gear = min_t(u32, host_params->hs_rx_gear,
365 host_params->hs_tx_gear);
367 min_host_gear = min_t(u32, host_params->pwm_rx_gear,
368 host_params->pwm_tx_gear);
372 * device doesn't support HS but host_params->desired_working_mode is HS,
373 * thus device and host_params don't agree
375 if (!is_dev_sup_hs && is_host_max_hs) {
376 pr_info("%s: device doesn't support HS\n",
379 } else if (is_dev_sup_hs && is_host_max_hs) {
381 * since device supports HS, it supports FAST_MODE.
382 * since host_params->desired_working_mode is also HS
383 * then final decision (FAST/FASTAUTO) is done according
384 * to pltfrm_params as it is the restricting factor
386 agreed_pwr->pwr_rx = host_params->rx_pwr_hs;
387 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
390 * here host_params->desired_working_mode is PWM.
391 * it doesn't matter whether device supports HS or PWM,
392 * in both cases host_params->desired_working_mode will
395 agreed_pwr->pwr_rx = host_params->rx_pwr_pwm;
396 agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
400 * we would like tx to work in the minimum number of lanes
401 * between device capability and vendor preferences.
402 * the same decision will be made for rx
404 agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
405 host_params->tx_lanes);
406 agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
407 host_params->rx_lanes);
409 /* device maximum gear is the minimum between device rx and tx gears */
410 min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
413 * if both device capabilities and vendor pre-defined preferences are
414 * both HS or both PWM then set the minimum gear to be the chosen
416 * if one is PWM and one is HS then the one that is PWM get to decide
417 * what is the gear, as it is the one that also decided previously what
418 * pwr the device will be configured to.
420 if ((is_dev_sup_hs && is_host_max_hs) ||
421 (!is_dev_sup_hs && !is_host_max_hs)) {
422 agreed_pwr->gear_rx =
423 min_t(u32, min_dev_gear, min_host_gear);
424 } else if (!is_dev_sup_hs) {
425 agreed_pwr->gear_rx = min_dev_gear;
427 agreed_pwr->gear_rx = min_host_gear;
429 agreed_pwr->gear_tx = agreed_pwr->gear_rx;
431 agreed_pwr->hs_rate = host_params->hs_rate;
435 EXPORT_SYMBOL_GPL(ufshcd_negotiate_pwr_params);
437 void ufshcd_init_host_params(struct ufs_host_params *host_params)
439 *host_params = (struct ufs_host_params){
440 .tx_lanes = UFS_LANE_2,
441 .rx_lanes = UFS_LANE_2,
442 .hs_rx_gear = UFS_HS_G3,
443 .hs_tx_gear = UFS_HS_G3,
444 .pwm_rx_gear = UFS_PWM_G4,
445 .pwm_tx_gear = UFS_PWM_G4,
446 .rx_pwr_pwm = SLOW_MODE,
447 .tx_pwr_pwm = SLOW_MODE,
448 .rx_pwr_hs = FAST_MODE,
449 .tx_pwr_hs = FAST_MODE,
450 .hs_rate = PA_HS_MODE_B,
451 .desired_working_mode = UFS_HS_MODE,
454 EXPORT_SYMBOL_GPL(ufshcd_init_host_params);
457 * ufshcd_pltfrm_init - probe routine of the driver
458 * @pdev: pointer to Platform device handle
459 * @vops: pointer to variant ops
461 * Return: 0 on success, non-zero value on failure.
463 int ufshcd_pltfrm_init(struct platform_device *pdev,
464 const struct ufs_hba_variant_ops *vops)
467 void __iomem *mmio_base;
469 struct device *dev = &pdev->dev;
471 mmio_base = devm_platform_ioremap_resource(pdev, 0);
472 if (IS_ERR(mmio_base)) {
473 err = PTR_ERR(mmio_base);
477 irq = platform_get_irq(pdev, 0);
483 err = ufshcd_alloc_host(dev, &hba);
485 dev_err(dev, "Allocation failed\n");
491 err = ufshcd_parse_clock_info(hba);
493 dev_err(dev, "%s: clock parse failed %d\n",
497 err = ufshcd_parse_regulator_info(hba);
499 dev_err(dev, "%s: regulator init failed %d\n",
504 ufshcd_init_lanes_per_dir(hba);
506 err = ufshcd_parse_operating_points(hba);
508 dev_err(dev, "%s: OPP parse failed %d\n", __func__, err);
512 err = ufshcd_init(hba, mmio_base, irq);
514 dev_err_probe(dev, err, "Initialization failed with error %d\n",
519 pm_runtime_set_active(dev);
520 pm_runtime_enable(dev);
525 ufshcd_dealloc_host(hba);
529 EXPORT_SYMBOL_GPL(ufshcd_pltfrm_init);
531 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
532 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
533 MODULE_DESCRIPTION("UFS host controller Platform bus based glue driver");
534 MODULE_LICENSE("GPL");