1 // SPDX-License-Identifier: GPL-2.0-only
3 * Synopsys G210 Test Chip driver
5 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
7 * Authors: Joao Pinto <jpinto@synopsys.com>
10 #include <linux/module.h>
12 #include <ufs/ufshcd.h>
13 #include <ufs/unipro.h>
15 #include "ufshcd-dwc.h"
16 #include "ufshci-dwc.h"
17 #include "tc-dwc-g210.h"
20 * tc_dwc_g210_setup_40bit_rmmi() - configure 40-bit RMMI.
21 * @hba: Pointer to drivers structure
23 * Return: 0 on success or non-zero value on failure.
25 static int tc_dwc_g210_setup_40bit_rmmi(struct ufs_hba *hba)
27 static const struct ufshcd_dme_attr_val setup_attrs[] = {
28 { UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },
29 { UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },
30 { UIC_ARG_MIB(CDIRECTCTRL6), 0x80, DME_LOCAL },
31 { UIC_ARG_MIB(CBDIVFACTOR), 0x08, DME_LOCAL },
32 { UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },
33 { UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },
34 { UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },
35 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,
37 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,
39 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x14,
41 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
43 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,
45 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,
47 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 4,
49 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
51 { UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },
52 { UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },
53 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
55 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,
57 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,
59 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,
61 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,
63 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,
65 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,
67 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,
69 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,
71 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
73 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
75 { UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },
78 return ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
79 ARRAY_SIZE(setup_attrs));
83 * tc_dwc_g210_setup_20bit_rmmi_lane0() - configure 20-bit RMMI Lane 0.
84 * @hba: Pointer to drivers structure
86 * Return: 0 on success or non-zero value on failure.
88 static int tc_dwc_g210_setup_20bit_rmmi_lane0(struct ufs_hba *hba)
90 static const struct ufshcd_dme_attr_val setup_attrs[] = {
91 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN0_TX), 0x01,
93 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN0_TX), 0x19,
95 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN0_RX), 0x19,
97 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN0_TX), 0x12,
99 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
101 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN0_RX), 0x01,
103 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN0_RX), 2,
105 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN0_RX), 0x80,
107 { UIC_ARG_MIB(DIRECTCTRL10), 0x04, DME_LOCAL },
108 { UIC_ARG_MIB(DIRECTCTRL19), 0x02, DME_LOCAL },
109 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN0_RX), 0x03,
111 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN0_RX), 0x16,
113 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN0_RX), 0x42,
115 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN0_RX), 0xa4,
117 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN0_RX), 0x01,
119 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN0_RX), 0x01,
121 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN0_RX), 0x28,
123 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN0_RX), 0x1E,
125 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN0_RX), 0x2f,
127 { UIC_ARG_MIB(CBPRGPLL2), 0x00, DME_LOCAL },
130 return ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
131 ARRAY_SIZE(setup_attrs));
135 * tc_dwc_g210_setup_20bit_rmmi_lane1() - configure 20-bit RMMI Lane 1.
136 * @hba: Pointer to drivers structure
138 * Return: 0 on success or non-zero value on failure.
140 static int tc_dwc_g210_setup_20bit_rmmi_lane1(struct ufs_hba *hba)
142 int connected_rx_lanes = 0;
143 int connected_tx_lanes = 0;
146 static const struct ufshcd_dme_attr_val setup_tx_attrs[] = {
147 { UIC_ARG_MIB_SEL(TX_REFCLKFREQ, SELIND_LN1_TX), 0x0d,
149 { UIC_ARG_MIB_SEL(TX_CFGCLKFREQVAL, SELIND_LN1_TX), 0x19,
151 { UIC_ARG_MIB_SEL(CFGEXTRATTR, SELIND_LN1_TX), 0x12,
153 { UIC_ARG_MIB_SEL(DITHERCTRL2, SELIND_LN0_TX), 0xd6,
157 static const struct ufshcd_dme_attr_val setup_rx_attrs[] = {
158 { UIC_ARG_MIB_SEL(RX_REFCLKFREQ, SELIND_LN1_RX), 0x01,
160 { UIC_ARG_MIB_SEL(RX_CFGCLKFREQVAL, SELIND_LN1_RX), 0x19,
162 { UIC_ARG_MIB_SEL(CFGWIDEINLN, SELIND_LN1_RX), 2,
164 { UIC_ARG_MIB_SEL(CFGRXCDR8, SELIND_LN1_RX), 0x80,
166 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG4, SELIND_LN1_RX), 0x03,
168 { UIC_ARG_MIB_SEL(CFGRXOVR8, SELIND_LN1_RX), 0x16,
170 { UIC_ARG_MIB_SEL(RXDIRECTCTRL2, SELIND_LN1_RX), 0x42,
172 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG3, SELIND_LN1_RX), 0xa4,
174 { UIC_ARG_MIB_SEL(RXCALCTRL, SELIND_LN1_RX), 0x01,
176 { UIC_ARG_MIB_SEL(ENARXDIRECTCFG2, SELIND_LN1_RX), 0x01,
178 { UIC_ARG_MIB_SEL(CFGRXOVR4, SELIND_LN1_RX), 0x28,
180 { UIC_ARG_MIB_SEL(RXSQCTRL, SELIND_LN1_RX), 0x1E,
182 { UIC_ARG_MIB_SEL(CFGRXOVR6, SELIND_LN1_RX), 0x2f,
186 /* Get the available lane count */
187 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
188 &connected_rx_lanes);
189 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
190 &connected_tx_lanes);
192 if (connected_tx_lanes == 2) {
194 ret = ufshcd_dwc_dme_set_attrs(hba, setup_tx_attrs,
195 ARRAY_SIZE(setup_tx_attrs));
201 if (connected_rx_lanes == 2) {
202 ret = ufshcd_dwc_dme_set_attrs(hba, setup_rx_attrs,
203 ARRAY_SIZE(setup_rx_attrs));
211 * tc_dwc_g210_setup_20bit_rmmi() - configure 20-bit RMMI.
212 * @hba: Pointer to drivers structure
214 * Return: 0 on success or non-zero value on failure.
216 static int tc_dwc_g210_setup_20bit_rmmi(struct ufs_hba *hba)
220 static const struct ufshcd_dme_attr_val setup_attrs[] = {
221 { UIC_ARG_MIB(TX_GLOBALHIBERNATE), 0x00, DME_LOCAL },
222 { UIC_ARG_MIB(REFCLKMODE), 0x01, DME_LOCAL },
223 { UIC_ARG_MIB(CDIRECTCTRL6), 0xc0, DME_LOCAL },
224 { UIC_ARG_MIB(CBDIVFACTOR), 0x44, DME_LOCAL },
225 { UIC_ARG_MIB(CBDCOCTRL5), 0x64, DME_LOCAL },
226 { UIC_ARG_MIB(CBPRGTUNING), 0x09, DME_LOCAL },
227 { UIC_ARG_MIB(RTOBSERVESELECT), 0x00, DME_LOCAL },
230 ret = ufshcd_dwc_dme_set_attrs(hba, setup_attrs,
231 ARRAY_SIZE(setup_attrs));
235 /* Lane 0 configuration*/
236 ret = tc_dwc_g210_setup_20bit_rmmi_lane0(hba);
240 /* Lane 1 configuration*/
241 ret = tc_dwc_g210_setup_20bit_rmmi_lane1(hba);
250 * tc_dwc_g210_config_40_bit() - configure 40-bit TC specific attributes.
251 * @hba: Pointer to drivers structure
253 * Return: 0 on success non-zero value on failure.
255 int tc_dwc_g210_config_40_bit(struct ufs_hba *hba)
259 dev_info(hba->dev, "Configuring Test Chip 40-bit RMMI\n");
260 ret = tc_dwc_g210_setup_40bit_rmmi(hba);
262 dev_err(hba->dev, "Configuration failed\n");
266 /* To write Shadow register bank to effective configuration block */
267 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
271 /* To configure Debug OMC */
272 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);
277 EXPORT_SYMBOL(tc_dwc_g210_config_40_bit);
280 * tc_dwc_g210_config_20_bit() - configure 20-bit TC specific attributes.
281 * @hba: Pointer to drivers structure
283 * Return: 0 on success non-zero value on failure.
285 int tc_dwc_g210_config_20_bit(struct ufs_hba *hba)
289 dev_info(hba->dev, "Configuring Test Chip 20-bit RMMI\n");
290 ret = tc_dwc_g210_setup_20bit_rmmi(hba);
292 dev_err(hba->dev, "Configuration failed\n");
296 /* To write Shadow register bank to effective configuration block */
297 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x01);
301 /* To configure Debug OMC */
302 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(VS_DEBUGOMC), 0x01);
307 EXPORT_SYMBOL(tc_dwc_g210_config_20_bit);
309 MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
310 MODULE_DESCRIPTION("Synopsys G210 Test Chip driver");
311 MODULE_LICENSE("Dual BSD/GPL");