drivers/ufs/core/ufshcd.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Universal Flash Storage Host controller driver Core
   4  * Copyright (C) 2011-2013 Samsung India Software Operations
   5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   6  *
   7  * Authors:
   8  *      Santosh Yaraganavi <santosh.sy@samsung.com>
   9  *      Vinayak Holikatti <h.vinayak@samsung.com>
  10  */
  11
  12 #include <linux/async.h>
  13 #include <linux/devfreq.h>
  14 #include <linux/nls.h>
  15 #include <linux/of.h>
  16 #include <linux/bitfield.h>
  17 #include <linux/blk-pm.h>
  18 #include <linux/blkdev.h>
  19 #include <linux/clk.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/pm_opp.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/sched/clock.h>
  26 #include <linux/iopoll.h>
  27 #include <scsi/scsi_cmnd.h>
  28 #include <scsi/scsi_dbg.h>
  29 #include <scsi/scsi_driver.h>
  30 #include <scsi/scsi_eh.h>
  31 #include "ufshcd-priv.h"
  32 #include <ufs/ufs_quirks.h>
  33 #include <ufs/unipro.h>
  34 #include "ufs-sysfs.h"
  35 #include "ufs-debugfs.h"
  36 #include "ufs-fault-injection.h"
  37 #include "ufs_bsg.h"
  38 #include "ufshcd-crypto.h"
  39 #include <asm/unaligned.h>
  40
  41 #define CREATE_TRACE_POINTS
  42 #include <trace/events/ufs.h>
  43
  44 #define UFSHCD_ENABLE_INTRS     (UTP_TRANSFER_REQ_COMPL |\
  45                                  UTP_TASK_REQ_COMPL |\
  46                                  UFSHCD_ERROR_MASK)
  47
  48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\
  49                                  UFSHCD_ERROR_MASK |\
  50                                  MCQ_CQ_EVENT_STATUS)
  51
  52
  53 /* UIC command timeout, unit: ms */
  54 #define UIC_CMD_TIMEOUT 500
  55
  56 /* NOP OUT retries waiting for NOP IN response */
  57 #define NOP_OUT_RETRIES    10
  58 /* Timeout after 50 msecs if NOP OUT hangs without response */
  59 #define NOP_OUT_TIMEOUT    50 /* msecs */
  60
  61 /* Query request retries */
  62 #define QUERY_REQ_RETRIES 3
  63 /* Query request timeout */
  64 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
  65
  66 /* Advanced RPMB request timeout */
  67 #define ADVANCED_RPMB_REQ_TIMEOUT  3000 /* 3 seconds */
  68
  69 /* Task management command timeout */
  70 #define TM_CMD_TIMEOUT  100 /* msecs */
  71
  72 /* maximum number of retries for a general UIC command  */
  73 #define UFS_UIC_COMMAND_RETRIES 3
  74
  75 /* maximum number of link-startup retries */
  76 #define DME_LINKSTARTUP_RETRIES 3
  77
  78 /* maximum number of reset retries before giving up */
  79 #define MAX_HOST_RESET_RETRIES 5
  80
  81 /* Maximum number of error handler retries before giving up */
  82 #define MAX_ERR_HANDLER_RETRIES 5
  83
  84 /* Expose the flag value from utp_upiu_query.value */
  85 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  86
  87 /* Interrupt aggregation default timeout, unit: 40us */
  88 #define INT_AGGR_DEF_TO 0x02
  89
  90 /* default delay of autosuspend: 2000 ms */
  91 #define RPM_AUTOSUSPEND_DELAY_MS 2000
  92
  93 /* Default delay of RPM device flush delayed work */
  94 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
  95
  96 /* Default value of wait time before gating device ref clock */
  97 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
  98
  99 /* Polling time to wait for fDeviceInit */
 100 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
 101
 102 /* Default RTC update every 10 seconds */
 103 #define UFS_RTC_UPDATE_INTERVAL_MS (10 * MSEC_PER_SEC)
 104
 105 /* UFSHC 4.0 compliant HC support this mode. */
 106 static bool use_mcq_mode = true;
 107
 108 static bool is_mcq_supported(struct ufs_hba *hba)
 109 {
 110         return hba->mcq_sup && use_mcq_mode;
 111 }
 112
 113 module_param(use_mcq_mode, bool, 0644);
 114 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default");
 115
 116 #define ufshcd_toggle_vreg(_dev, _vreg, _on)                            \
 117         ({                                                              \
 118                 int _ret;                                               \
 119                 if (_on)                                                \
 120                         _ret = ufshcd_enable_vreg(_dev, _vreg);         \
 121                 else                                                    \
 122                         _ret = ufshcd_disable_vreg(_dev, _vreg);        \
 123                 _ret;                                                   \
 124         })
 125
 126 #define ufshcd_hex_dump(prefix_str, buf, len) do {                       \
 127         size_t __len = (len);                                            \
 128         print_hex_dump(KERN_ERR, prefix_str,                             \
 129                        __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
 130                        16, 4, buf, __len, false);                        \
 131 } while (0)
 132
 133 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
 134                      const char *prefix)
 135 {
 136         u32 *regs;
 137         size_t pos;
 138
 139         if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
 140                 return -EINVAL;
 141
 142         regs = kzalloc(len, GFP_ATOMIC);
 143         if (!regs)
 144                 return -ENOMEM;
 145
 146         for (pos = 0; pos < len; pos += 4) {
 147                 if (offset == 0 &&
 148                     pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER &&
 149                     pos <= REG_UIC_ERROR_CODE_DME)
 150                         continue;
 151                 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
 152         }
 153
 154         ufshcd_hex_dump(prefix, regs, len);
 155         kfree(regs);
 156
 157         return 0;
 158 }
 159 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
 160
 161 enum {
 162         UFSHCD_MAX_CHANNEL      = 0,
 163         UFSHCD_MAX_ID           = 1,
 164         UFSHCD_CMD_PER_LUN      = 32 - UFSHCD_NUM_RESERVED,
 165         UFSHCD_CAN_QUEUE        = 32 - UFSHCD_NUM_RESERVED,
 166 };
 167
 168 static const char *const ufshcd_state_name[] = {
 169         [UFSHCD_STATE_RESET]                    = "reset",
 170         [UFSHCD_STATE_OPERATIONAL]              = "operational",
 171         [UFSHCD_STATE_ERROR]                    = "error",
 172         [UFSHCD_STATE_EH_SCHEDULED_FATAL]       = "eh_fatal",
 173         [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL]   = "eh_non_fatal",
 174 };
 175
 176 /* UFSHCD error handling flags */
 177 enum {
 178         UFSHCD_EH_IN_PROGRESS = (1 << 0),
 179 };
 180
 181 /* UFSHCD UIC layer error flags */
 182 enum {
 183         UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
 184         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
 185         UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
 186         UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
 187         UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
 188         UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
 189         UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
 190 };
 191
 192 #define ufshcd_set_eh_in_progress(h) \
 193         ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
 194 #define ufshcd_eh_in_progress(h) \
 195         ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
 196 #define ufshcd_clear_eh_in_progress(h) \
 197         ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
 198
 199 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
 200         [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 201         [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 202         [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
 203         [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 204         [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
 205         [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
 206         /*
 207          * For DeepSleep, the link is first put in hibern8 and then off.
 208          * Leaving the link in hibern8 is not supported.
 209          */
 210         [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
 211 };
 212
 213 static inline enum ufs_dev_pwr_mode
 214 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
 215 {
 216         return ufs_pm_lvl_states[lvl].dev_state;
 217 }
 218
 219 static inline enum uic_link_state
 220 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
 221 {
 222         return ufs_pm_lvl_states[lvl].link_state;
 223 }
 224
 225 static inline enum ufs_pm_level
 226 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
 227                                         enum uic_link_state link_state)
 228 {
 229         enum ufs_pm_level lvl;
 230
 231         for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
 232                 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
 233                         (ufs_pm_lvl_states[lvl].link_state == link_state))
 234                         return lvl;
 235         }
 236
 237         /* if no match found, return the level 0 */
 238         return UFS_PM_LVL_0;
 239 }
 240
 241 static bool ufshcd_is_ufs_dev_busy(struct ufs_hba *hba)
 242 {
 243         return (hba->clk_gating.active_reqs || hba->outstanding_reqs || hba->outstanding_tasks ||
 244                 hba->active_uic_cmd || hba->uic_async_done);
 245 }
 246
 247 static const struct ufs_dev_quirk ufs_fixups[] = {
 248         /* UFS cards deviations table */
 249         { .wmanufacturerid = UFS_VENDOR_MICRON,
 250           .model = UFS_ANY_MODEL,
 251           .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
 252         { .wmanufacturerid = UFS_VENDOR_SAMSUNG,
 253           .model = UFS_ANY_MODEL,
 254           .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
 255                    UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
 256                    UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS },
 257         { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
 258           .model = UFS_ANY_MODEL,
 259           .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME },
 260         { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
 261           .model = "hB8aL1" /*H28U62301AMR*/,
 262           .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME },
 263         { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
 264           .model = UFS_ANY_MODEL,
 265           .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
 266         { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
 267           .model = "THGLF2G9C8KBADG",
 268           .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
 269         { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
 270           .model = "THGLF2G9D8KBADG",
 271           .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
 272         {}
 273 };
 274
 275 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
 276 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
 277 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
 278 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
 279 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
 280 static void ufshcd_hba_exit(struct ufs_hba *hba);
 281 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
 282 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
 283 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
 284 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
 285 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
 286 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
 287 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq,
 288                              bool scale_up);
 289 static irqreturn_t ufshcd_intr(int irq, void *__hba);
 290 static int ufshcd_change_power_mode(struct ufs_hba *hba,
 291                              struct ufs_pa_layer_attr *pwr_mode);
 292 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
 293 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
 294 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
 295                                          struct ufs_vreg *vreg);
 296 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
 297                                                  bool enable);
 298 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
 299 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
 300
 301 void ufshcd_enable_irq(struct ufs_hba *hba)
 302 {
 303         if (!hba->is_irq_enabled) {
 304                 enable_irq(hba->irq);
 305                 hba->is_irq_enabled = true;
 306         }
 307 }
 308 EXPORT_SYMBOL_GPL(ufshcd_enable_irq);
 309
 310 void ufshcd_disable_irq(struct ufs_hba *hba)
 311 {
 312         if (hba->is_irq_enabled) {
 313                 disable_irq(hba->irq);
 314                 hba->is_irq_enabled = false;
 315         }
 316 }
 317 EXPORT_SYMBOL_GPL(ufshcd_disable_irq);
 318
 319 static void ufshcd_configure_wb(struct ufs_hba *hba)
 320 {
 321         if (!ufshcd_is_wb_allowed(hba))
 322                 return;
 323
 324         ufshcd_wb_toggle(hba, true);
 325
 326         ufshcd_wb_toggle_buf_flush_during_h8(hba, true);
 327
 328         if (ufshcd_is_wb_buf_flush_allowed(hba))
 329                 ufshcd_wb_toggle_buf_flush(hba, true);
 330 }
 331
 332 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
 333 {
 334         if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
 335                 scsi_unblock_requests(hba->host);
 336 }
 337
 338 static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
 339 {
 340         if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
 341                 scsi_block_requests(hba->host);
 342 }
 343
 344 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 345                                       enum ufs_trace_str_t str_t)
 346 {
 347         struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
 348         struct utp_upiu_header *header;
 349
 350         if (!trace_ufshcd_upiu_enabled())
 351                 return;
 352
 353         if (str_t == UFS_CMD_SEND)
 354                 header = &rq->header;
 355         else
 356                 header = &hba->lrb[tag].ucd_rsp_ptr->header;
 357
 358         trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
 359                           UFS_TSF_CDB);
 360 }
 361
 362 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
 363                                         enum ufs_trace_str_t str_t,
 364                                         struct utp_upiu_req *rq_rsp)
 365 {
 366         if (!trace_ufshcd_upiu_enabled())
 367                 return;
 368
 369         trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
 370                           &rq_rsp->qr, UFS_TSF_OSF);
 371 }
 372
 373 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
 374                                      enum ufs_trace_str_t str_t)
 375 {
 376         struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
 377
 378         if (!trace_ufshcd_upiu_enabled())
 379                 return;
 380
 381         if (str_t == UFS_TM_SEND)
 382                 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
 383                                   &descp->upiu_req.req_header,
 384                                   &descp->upiu_req.input_param1,
 385                                   UFS_TSF_TM_INPUT);
 386         else
 387                 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
 388                                   &descp->upiu_rsp.rsp_header,
 389                                   &descp->upiu_rsp.output_param1,
 390                                   UFS_TSF_TM_OUTPUT);
 391 }
 392
 393 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
 394                                          const struct uic_command *ucmd,
 395                                          enum ufs_trace_str_t str_t)
 396 {
 397         u32 cmd;
 398
 399         if (!trace_ufshcd_uic_command_enabled())
 400                 return;
 401
 402         if (str_t == UFS_CMD_SEND)
 403                 cmd = ucmd->command;
 404         else
 405                 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
 406
 407         trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
 408                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
 409                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
 410                                  ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
 411 }
 412
 413 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
 414                                      enum ufs_trace_str_t str_t)
 415 {
 416         u64 lba = 0;
 417         u8 opcode = 0, group_id = 0;
 418         u32 doorbell = 0;
 419         u32 intr;
 420         int hwq_id = -1;
 421         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
 422         struct scsi_cmnd *cmd = lrbp->cmd;
 423         struct request *rq = scsi_cmd_to_rq(cmd);
 424         int transfer_len = -1;
 425
 426         if (!cmd)
 427                 return;
 428
 429         /* trace UPIU also */
 430         ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
 431         if (!trace_ufshcd_command_enabled())
 432                 return;
 433
 434         opcode = cmd->cmnd[0];
 435
 436         if (opcode == READ_10 || opcode == WRITE_10) {
 437                 /*
 438                  * Currently we only fully trace read(10) and write(10) commands
 439                  */
 440                 transfer_len =
 441                        be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
 442                 lba = scsi_get_lba(cmd);
 443                 if (opcode == WRITE_10)
 444                         group_id = lrbp->cmd->cmnd[6];
 445         } else if (opcode == UNMAP) {
 446                 /*
 447                  * The number of Bytes to be unmapped beginning with the lba.
 448                  */
 449                 transfer_len = blk_rq_bytes(rq);
 450                 lba = scsi_get_lba(cmd);
 451         }
 452
 453         intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
 454
 455         if (is_mcq_enabled(hba)) {
 456                 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq);
 457
 458                 hwq_id = hwq->id;
 459         } else {
 460                 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
 461         }
 462         trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id,
 463                              transfer_len, intr, lba, opcode, group_id);
 464 }
 465
 466 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
 467 {
 468         struct ufs_clk_info *clki;
 469         struct list_head *head = &hba->clk_list_head;
 470
 471         if (list_empty(head))
 472                 return;
 473
 474         list_for_each_entry(clki, head, list) {
 475                 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
 476                                 clki->max_freq)
 477                         dev_err(hba->dev, "clk: %s, rate: %u\n",
 478                                         clki->name, clki->curr_freq);
 479         }
 480 }
 481
 482 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
 483                              const char *err_name)
 484 {
 485         int i;
 486         bool found = false;
 487         const struct ufs_event_hist *e;
 488
 489         if (id >= UFS_EVT_CNT)
 490                 return;
 491
 492         e = &hba->ufs_stats.event[id];
 493
 494         for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
 495                 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
 496
 497                 if (e->tstamp[p] == 0)
 498                         continue;
 499                 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
 500                         e->val[p], div_u64(e->tstamp[p], 1000));
 501                 found = true;
 502         }
 503
 504         if (!found)
 505                 dev_err(hba->dev, "No record of %s\n", err_name);
 506         else
 507                 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
 508 }
 509
 510 static void ufshcd_print_evt_hist(struct ufs_hba *hba)
 511 {
 512         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
 513
 514         ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
 515         ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
 516         ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
 517         ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
 518         ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
 519         ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
 520                          "auto_hibern8_err");
 521         ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
 522         ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
 523                          "link_startup_fail");
 524         ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
 525         ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
 526                          "suspend_fail");
 527         ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail");
 528         ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR,
 529                          "wlun suspend_fail");
 530         ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
 531         ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
 532         ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
 533
 534         ufshcd_vops_dbg_register_dump(hba);
 535 }
 536
 537 static
 538 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt)
 539 {
 540         const struct ufshcd_lrb *lrbp;
 541         int prdt_length;
 542
 543         lrbp = &hba->lrb[tag];
 544
 545         dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
 546                         tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000));
 547         dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
 548                         tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000));
 549         dev_err(hba->dev,
 550                 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
 551                 tag, (u64)lrbp->utrd_dma_addr);
 552
 553         ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
 554                         sizeof(struct utp_transfer_req_desc));
 555         dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
 556                 (u64)lrbp->ucd_req_dma_addr);
 557         ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
 558                         sizeof(struct utp_upiu_req));
 559         dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
 560                 (u64)lrbp->ucd_rsp_dma_addr);
 561         ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
 562                         sizeof(struct utp_upiu_rsp));
 563
 564         prdt_length = le16_to_cpu(
 565                 lrbp->utr_descriptor_ptr->prd_table_length);
 566         if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
 567                 prdt_length /= ufshcd_sg_entry_size(hba);
 568
 569         dev_err(hba->dev,
 570                 "UPIU[%d] - PRDT - %d entries  phys@0x%llx\n",
 571                 tag, prdt_length,
 572                 (u64)lrbp->ucd_prdt_dma_addr);
 573
 574         if (pr_prdt)
 575                 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
 576                         ufshcd_sg_entry_size(hba) * prdt_length);
 577 }
 578
 579 static bool ufshcd_print_tr_iter(struct request *req, void *priv)
 580 {
 581         struct scsi_device *sdev = req->q->queuedata;
 582         struct Scsi_Host *shost = sdev->host;
 583         struct ufs_hba *hba = shost_priv(shost);
 584
 585         ufshcd_print_tr(hba, req->tag, *(bool *)priv);
 586
 587         return true;
 588 }
 589
 590 /**
 591  * ufshcd_print_trs_all - print trs for all started requests.
 592  * @hba: per-adapter instance.
 593  * @pr_prdt: need to print prdt or not.
 594  */
 595 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt)
 596 {
 597         blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt);
 598 }
 599
 600 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
 601 {
 602         int tag;
 603
 604         for_each_set_bit(tag, &bitmap, hba->nutmrs) {
 605                 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
 606
 607                 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
 608                 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
 609         }
 610 }
 611
 612 static void ufshcd_print_host_state(struct ufs_hba *hba)
 613 {
 614         const struct scsi_device *sdev_ufs = hba->ufs_device_wlun;
 615
 616         dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
 617         dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
 618                 hba->outstanding_reqs, hba->outstanding_tasks);
 619         dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
 620                 hba->saved_err, hba->saved_uic_err);
 621         dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
 622                 hba->curr_dev_pwr_mode, hba->uic_link_state);
 623         dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
 624                 hba->pm_op_in_progress, hba->is_sys_suspended);
 625         dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
 626                 hba->auto_bkops_enabled, hba->host->host_self_blocked);
 627         dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
 628         dev_err(hba->dev,
 629                 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
 630                 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000),
 631                 hba->ufs_stats.hibern8_exit_cnt);
 632         dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
 633                 div_u64(hba->ufs_stats.last_intr_ts, 1000),
 634                 hba->ufs_stats.last_intr_status);
 635         dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
 636                 hba->eh_flags, hba->req_abort_count);
 637         dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
 638                 hba->ufs_version, hba->capabilities, hba->caps);
 639         dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
 640                 hba->dev_quirks);
 641         if (sdev_ufs)
 642                 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
 643                         sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
 644
 645         ufshcd_print_clk_freqs(hba);
 646 }
 647
 648 /**
 649  * ufshcd_print_pwr_info - print power params as saved in hba
 650  * power info
 651  * @hba: per-adapter instance
 652  */
 653 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
 654 {
 655         static const char * const names[] = {
 656                 "INVALID MODE",
 657                 "FAST MODE",
 658                 "SLOW_MODE",
 659                 "INVALID MODE",
 660                 "FASTAUTO_MODE",
 661                 "SLOWAUTO_MODE",
 662                 "INVALID MODE",
 663         };
 664
 665         /*
 666          * Using dev_dbg to avoid messages during runtime PM to avoid
 667          * never-ending cycles of messages written back to storage by user space
 668          * causing runtime resume, causing more messages and so on.
 669          */
 670         dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
 671                  __func__,
 672                  hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
 673                  hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
 674                  names[hba->pwr_info.pwr_rx],
 675                  names[hba->pwr_info.pwr_tx],
 676                  hba->pwr_info.hs_rate);
 677 }
 678
 679 static void ufshcd_device_reset(struct ufs_hba *hba)
 680 {
 681         int err;
 682
 683         err = ufshcd_vops_device_reset(hba);
 684
 685         if (!err) {
 686                 ufshcd_set_ufs_dev_active(hba);
 687                 if (ufshcd_is_wb_allowed(hba)) {
 688                         hba->dev_info.wb_enabled = false;
 689                         hba->dev_info.wb_buf_flush_enabled = false;
 690                 }
 691                 if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE)
 692                         hba->dev_info.rtc_time_baseline = 0;
 693         }
 694         if (err != -EOPNOTSUPP)
 695                 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
 696 }
 697
 698 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
 699 {
 700         if (!us)
 701                 return;
 702
 703         if (us < 10)
 704                 udelay(us);
 705         else
 706                 usleep_range(us, us + tolerance);
 707 }
 708 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
 709
 710 /**
 711  * ufshcd_wait_for_register - wait for register value to change
 712  * @hba: per-adapter interface
 713  * @reg: mmio register offset
 714  * @mask: mask to apply to the read register value
 715  * @val: value to wait for
 716  * @interval_us: polling interval in microseconds
 717  * @timeout_ms: timeout in milliseconds
 718  *
 719  * Return: -ETIMEDOUT on error, zero on success.
 720  */
 721 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
 722                                 u32 val, unsigned long interval_us,
 723                                 unsigned long timeout_ms)
 724 {
 725         int err = 0;
 726         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
 727
 728         /* ignore bits that we don't intend to wait on */
 729         val = val & mask;
 730
 731         while ((ufshcd_readl(hba, reg) & mask) != val) {
 732                 usleep_range(interval_us, interval_us + 50);
 733                 if (time_after(jiffies, timeout)) {
 734                         if ((ufshcd_readl(hba, reg) & mask) != val)
 735                                 err = -ETIMEDOUT;
 736                         break;
 737                 }
 738         }
 739
 740         return err;
 741 }
 742
 743 /**
 744  * ufshcd_get_intr_mask - Get the interrupt bit mask
 745  * @hba: Pointer to adapter instance
 746  *
 747  * Return: interrupt bit mask per version
 748  */
 749 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
 750 {
 751         if (hba->ufs_version == ufshci_version(1, 0))
 752                 return INTERRUPT_MASK_ALL_VER_10;
 753         if (hba->ufs_version <= ufshci_version(2, 0))
 754                 return INTERRUPT_MASK_ALL_VER_11;
 755
 756         return INTERRUPT_MASK_ALL_VER_21;
 757 }
 758
 759 /**
 760  * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
 761  * @hba: Pointer to adapter instance
 762  *
 763  * Return: UFSHCI version supported by the controller
 764  */
 765 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
 766 {
 767         u32 ufshci_ver;
 768
 769         if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
 770                 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
 771         else
 772                 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
 773
 774         /*
 775          * UFSHCI v1.x uses a different version scheme, in order
 776          * to allow the use of comparisons with the ufshci_version
 777          * function, we convert it to the same scheme as ufs 2.0+.
 778          */
 779         if (ufshci_ver & 0x00010000)
 780                 return ufshci_version(1, ufshci_ver & 0x00000100);
 781
 782         return ufshci_ver;
 783 }
 784
 785 /**
 786  * ufshcd_is_device_present - Check if any device connected to
 787  *                            the host controller
 788  * @hba: pointer to adapter instance
 789  *
 790  * Return: true if device present, false if no device detected
 791  */
 792 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
 793 {
 794         return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
 795 }
 796
 797 /**
 798  * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
 799  * @lrbp: pointer to local command reference block
 800  * @cqe: pointer to the completion queue entry
 801  *
 802  * This function is used to get the OCS field from UTRD
 803  *
 804  * Return: the OCS field in the UTRD.
 805  */
 806 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp,
 807                                       struct cq_entry *cqe)
 808 {
 809         if (cqe)
 810                 return le32_to_cpu(cqe->status) & MASK_OCS;
 811
 812         return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS;
 813 }
 814
 815 /**
 816  * ufshcd_utrl_clear() - Clear requests from the controller request list.
 817  * @hba: per adapter instance
 818  * @mask: mask with one bit set for each request to be cleared
 819  */
 820 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask)
 821 {
 822         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 823                 mask = ~mask;
 824         /*
 825          * From the UFSHCI specification: "UTP Transfer Request List CLear
 826          * Register (UTRLCLR): This field is bit significant. Each bit
 827          * corresponds to a slot in the UTP Transfer Request List, where bit 0
 828          * corresponds to request slot 0. A bit in this field is set to ‘0’
 829          * by host software to indicate to the host controller that a transfer
 830          * request slot is cleared. The host controller
 831          * shall free up any resources associated to the request slot
 832          * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The
 833          * host software indicates no change to request slots by setting the
 834          * associated bits in this field to ‘1’. Bits in this field shall only
 835          * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’."
 836          */
 837         ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
 838 }
 839
 840 /**
 841  * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register
 842  * @hba: per adapter instance
 843  * @pos: position of the bit to be cleared
 844  */
 845 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
 846 {
 847         if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
 848                 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 849         else
 850                 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
 851 }
 852
 853 /**
 854  * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
 855  * @reg: Register value of host controller status
 856  *
 857  * Return: 0 on success; a positive value if failed.
 858  */
 859 static inline int ufshcd_get_lists_status(u32 reg)
 860 {
 861         return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
 862 }
 863
 864 /**
 865  * ufshcd_get_uic_cmd_result - Get the UIC command result
 866  * @hba: Pointer to adapter instance
 867  *
 868  * This function gets the result of UIC command completion
 869  *
 870  * Return: 0 on success; non-zero value on error.
 871  */
 872 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
 873 {
 874         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
 875                MASK_UIC_COMMAND_RESULT;
 876 }
 877
 878 /**
 879  * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
 880  * @hba: Pointer to adapter instance
 881  *
 882  * This function gets UIC command argument3
 883  *
 884  * Return: 0 on success; non-zero value on error.
 885  */
 886 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
 887 {
 888         return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
 889 }
 890
 891 /**
 892  * ufshcd_get_req_rsp - returns the TR response transaction type
 893  * @ucd_rsp_ptr: pointer to response UPIU
 894  *
 895  * Return: UPIU type.
 896  */
 897 static inline enum upiu_response_transaction
 898 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
 899 {
 900         return ucd_rsp_ptr->header.transaction_code;
 901 }
 902
 903 /**
 904  * ufshcd_is_exception_event - Check if the device raised an exception event
 905  * @ucd_rsp_ptr: pointer to response UPIU
 906  *
 907  * The function checks if the device raised an exception event indicated in
 908  * the Device Information field of response UPIU.
 909  *
 910  * Return: true if exception is raised, false otherwise.
 911  */
 912 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
 913 {
 914         return ucd_rsp_ptr->header.device_information & 1;
 915 }
 916
 917 /**
 918  * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
 919  * @hba: per adapter instance
 920  */
 921 static inline void
 922 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
 923 {
 924         ufshcd_writel(hba, INT_AGGR_ENABLE |
 925                       INT_AGGR_COUNTER_AND_TIMER_RESET,
 926                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 927 }
 928
 929 /**
 930  * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
 931  * @hba: per adapter instance
 932  * @cnt: Interrupt aggregation counter threshold
 933  * @tmout: Interrupt aggregation timeout value
 934  */
 935 static inline void
 936 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
 937 {
 938         ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
 939                       INT_AGGR_COUNTER_THLD_VAL(cnt) |
 940                       INT_AGGR_TIMEOUT_VAL(tmout),
 941                       REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 942 }
 943
 944 /**
 945  * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
 946  * @hba: per adapter instance
 947  */
 948 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
 949 {
 950         ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
 951 }
 952
 953 /**
 954  * ufshcd_enable_run_stop_reg - Enable run-stop registers,
 955  *                      When run-stop registers are set to 1, it indicates the
 956  *                      host controller that it can process the requests
 957  * @hba: per adapter instance
 958  */
 959 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
 960 {
 961         ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
 962                       REG_UTP_TASK_REQ_LIST_RUN_STOP);
 963         ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
 964                       REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
 965 }
 966
 967 /**
 968  * ufshcd_hba_start - Start controller initialization sequence
 969  * @hba: per adapter instance
 970  */
 971 static inline void ufshcd_hba_start(struct ufs_hba *hba)
 972 {
 973         u32 val = CONTROLLER_ENABLE;
 974
 975         if (ufshcd_crypto_enable(hba))
 976                 val |= CRYPTO_GENERAL_ENABLE;
 977
 978         ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
 979 }
 980
 981 /**
 982  * ufshcd_is_hba_active - Get controller state
 983  * @hba: per adapter instance
 984  *
 985  * Return: true if and only if the controller is active.
 986  */
 987 bool ufshcd_is_hba_active(struct ufs_hba *hba)
 988 {
 989         return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
 990 }
 991 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active);
 992
 993 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
 994 {
 995         /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
 996         if (hba->ufs_version <= ufshci_version(1, 1))
 997                 return UFS_UNIPRO_VER_1_41;
 998         else
 999                 return UFS_UNIPRO_VER_1_6;
1000 }
1001 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
1002
1003 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
1004 {
1005         /*
1006          * If both host and device support UniPro ver1.6 or later, PA layer
1007          * parameters tuning happens during link startup itself.
1008          *
1009          * We can manually tune PA layer parameters if either host or device
1010          * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
1011          * logic simple, we will only do manual tuning if local unipro version
1012          * doesn't support ver1.6 or later.
1013          */
1014         return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6;
1015 }
1016
1017 /**
1018  * ufshcd_pm_qos_init - initialize PM QoS request
1019  * @hba: per adapter instance
1020  */
1021 void ufshcd_pm_qos_init(struct ufs_hba *hba)
1022 {
1023
1024         if (hba->pm_qos_enabled)
1025                 return;
1026
1027         cpu_latency_qos_add_request(&hba->pm_qos_req, PM_QOS_DEFAULT_VALUE);
1028
1029         if (cpu_latency_qos_request_active(&hba->pm_qos_req))
1030                 hba->pm_qos_enabled = true;
1031 }
1032
1033 /**
1034  * ufshcd_pm_qos_exit - remove request from PM QoS
1035  * @hba: per adapter instance
1036  */
1037 void ufshcd_pm_qos_exit(struct ufs_hba *hba)
1038 {
1039         if (!hba->pm_qos_enabled)
1040                 return;
1041
1042         cpu_latency_qos_remove_request(&hba->pm_qos_req);
1043         hba->pm_qos_enabled = false;
1044 }
1045
1046 /**
1047  * ufshcd_pm_qos_update - update PM QoS request
1048  * @hba: per adapter instance
1049  * @on: If True, vote for perf PM QoS mode otherwise power save mode
1050  */
1051 static void ufshcd_pm_qos_update(struct ufs_hba *hba, bool on)
1052 {
1053         if (!hba->pm_qos_enabled)
1054                 return;
1055
1056         cpu_latency_qos_update_request(&hba->pm_qos_req, on ? 0 : PM_QOS_DEFAULT_VALUE);
1057 }
1058
1059 /**
1060  * ufshcd_set_clk_freq - set UFS controller clock frequencies
1061  * @hba: per adapter instance
1062  * @scale_up: If True, set max possible frequency othewise set low frequency
1063  *
1064  * Return: 0 if successful; < 0 upon failure.
1065  */
1066 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
1067 {
1068         int ret = 0;
1069         struct ufs_clk_info *clki;
1070         struct list_head *head = &hba->clk_list_head;
1071
1072         if (list_empty(head))
1073                 goto out;
1074
1075         list_for_each_entry(clki, head, list) {
1076                 if (!IS_ERR_OR_NULL(clki->clk)) {
1077                         if (scale_up && clki->max_freq) {
1078                                 if (clki->curr_freq == clki->max_freq)
1079                                         continue;
1080
1081                                 ret = clk_set_rate(clki->clk, clki->max_freq);
1082                                 if (ret) {
1083                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1084                                                 __func__, clki->name,
1085                                                 clki->max_freq, ret);
1086                                         break;
1087                                 }
1088                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1089                                                 "scaled up", clki->name,
1090                                                 clki->curr_freq,
1091                                                 clki->max_freq);
1092
1093                                 clki->curr_freq = clki->max_freq;
1094
1095                         } else if (!scale_up && clki->min_freq) {
1096                                 if (clki->curr_freq == clki->min_freq)
1097                                         continue;
1098
1099                                 ret = clk_set_rate(clki->clk, clki->min_freq);
1100                                 if (ret) {
1101                                         dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1102                                                 __func__, clki->name,
1103                                                 clki->min_freq, ret);
1104                                         break;
1105                                 }
1106                                 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1107                                                 "scaled down", clki->name,
1108                                                 clki->curr_freq,
1109                                                 clki->min_freq);
1110                                 clki->curr_freq = clki->min_freq;
1111                         }
1112                 }
1113                 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1114                                 clki->name, clk_get_rate(clki->clk));
1115         }
1116
1117 out:
1118         return ret;
1119 }
1120
1121 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
1122                            struct dev_pm_opp *opp, void *data,
1123                            bool scaling_down)
1124 {
1125         struct ufs_hba *hba = dev_get_drvdata(dev);
1126         struct list_head *head = &hba->clk_list_head;
1127         struct ufs_clk_info *clki;
1128         unsigned long freq;
1129         u8 idx = 0;
1130         int ret;
1131
1132         list_for_each_entry(clki, head, list) {
1133                 if (!IS_ERR_OR_NULL(clki->clk)) {
1134                         freq = dev_pm_opp_get_freq_indexed(opp, idx++);
1135
1136                         /* Do not set rate for clocks having frequency as 0 */
1137                         if (!freq)
1138                                 continue;
1139
1140                         ret = clk_set_rate(clki->clk, freq);
1141                         if (ret) {
1142                                 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n",
1143                                         __func__, clki->name, freq, ret);
1144                                 return ret;
1145                         }
1146
1147                         trace_ufshcd_clk_scaling(dev_name(dev),
1148                                 (scaling_down ? "scaled down" : "scaled up"),
1149                                 clki->name, hba->clk_scaling.target_freq, freq);
1150                 }
1151         }
1152
1153         return 0;
1154 }
1155 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks);
1156
1157 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq)
1158 {
1159         struct dev_pm_opp *opp;
1160         int ret;
1161
1162         opp = dev_pm_opp_find_freq_floor_indexed(hba->dev,
1163                                                  &freq, 0);
1164         if (IS_ERR(opp))
1165                 return PTR_ERR(opp);
1166
1167         ret = dev_pm_opp_set_opp(hba->dev, opp);
1168         dev_pm_opp_put(opp);
1169
1170         return ret;
1171 }
1172
1173 /**
1174  * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1175  * @hba: per adapter instance
1176  * @freq: frequency to scale
1177  * @scale_up: True if scaling up and false if scaling down
1178  *
1179  * Return: 0 if successful; < 0 upon failure.
1180  */
1181 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq,
1182                              bool scale_up)
1183 {
1184         int ret = 0;
1185         ktime_t start = ktime_get();
1186
1187         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1188         if (ret)
1189                 goto out;
1190
1191         if (hba->use_pm_opp)
1192                 ret = ufshcd_opp_set_rate(hba, freq);
1193         else
1194                 ret = ufshcd_set_clk_freq(hba, scale_up);
1195         if (ret)
1196                 goto out;
1197
1198         ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1199         if (ret) {
1200                 if (hba->use_pm_opp)
1201                         ufshcd_opp_set_rate(hba,
1202                                             hba->devfreq->previous_freq);
1203                 else
1204                         ufshcd_set_clk_freq(hba, !scale_up);
1205                 goto out;
1206         }
1207
1208         ufshcd_pm_qos_update(hba, scale_up);
1209
1210 out:
1211         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1212                         (scale_up ? "up" : "down"),
1213                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1214         return ret;
1215 }
1216
1217 /**
1218  * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1219  * @hba: per adapter instance
1220  * @freq: frequency to scale
1221  * @scale_up: True if scaling up and false if scaling down
1222  *
1223  * Return: true if scaling is required, false otherwise.
1224  */
1225 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1226                                                unsigned long freq, bool scale_up)
1227 {
1228         struct ufs_clk_info *clki;
1229         struct list_head *head = &hba->clk_list_head;
1230
1231         if (list_empty(head))
1232                 return false;
1233
1234         if (hba->use_pm_opp)
1235                 return freq != hba->clk_scaling.target_freq;
1236
1237         list_for_each_entry(clki, head, list) {
1238                 if (!IS_ERR_OR_NULL(clki->clk)) {
1239                         if (scale_up && clki->max_freq) {
1240                                 if (clki->curr_freq == clki->max_freq)
1241                                         continue;
1242                                 return true;
1243                         } else if (!scale_up && clki->min_freq) {
1244                                 if (clki->curr_freq == clki->min_freq)
1245                                         continue;
1246                                 return true;
1247                         }
1248                 }
1249         }
1250
1251         return false;
1252 }
1253
1254 /*
1255  * Determine the number of pending commands by counting the bits in the SCSI
1256  * device budget maps. This approach has been selected because a bit is set in
1257  * the budget map before scsi_host_queue_ready() checks the host_self_blocked
1258  * flag. The host_self_blocked flag can be modified by calling
1259  * scsi_block_requests() or scsi_unblock_requests().
1260  */
1261 static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1262 {
1263         const struct scsi_device *sdev;
1264         u32 pending = 0;
1265
1266         lockdep_assert_held(hba->host->host_lock);
1267         __shost_for_each_device(sdev, hba->host)
1268                 pending += sbitmap_weight(&sdev->budget_map);
1269
1270         return pending;
1271 }
1272
1273 /*
1274  * Wait until all pending SCSI commands and TMFs have finished or the timeout
1275  * has expired.
1276  *
1277  * Return: 0 upon success; -EBUSY upon timeout.
1278  */
1279 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1280                                         u64 wait_timeout_us)
1281 {
1282         unsigned long flags;
1283         int ret = 0;
1284         u32 tm_doorbell;
1285         u32 tr_pending;
1286         bool timeout = false, do_last_check = false;
1287         ktime_t start;
1288
1289         ufshcd_hold(hba);
1290         spin_lock_irqsave(hba->host->host_lock, flags);
1291         /*
1292          * Wait for all the outstanding tasks/transfer requests.
1293          * Verify by checking the doorbell registers are clear.
1294          */
1295         start = ktime_get();
1296         do {
1297                 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1298                         ret = -EBUSY;
1299                         goto out;
1300                 }
1301
1302                 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1303                 tr_pending = ufshcd_pending_cmds(hba);
1304                 if (!tm_doorbell && !tr_pending) {
1305                         timeout = false;
1306                         break;
1307                 } else if (do_last_check) {
1308                         break;
1309                 }
1310
1311                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1312                 io_schedule_timeout(msecs_to_jiffies(20));
1313                 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1314                     wait_timeout_us) {
1315                         timeout = true;
1316                         /*
1317                          * We might have scheduled out for long time so make
1318                          * sure to check if doorbells are cleared by this time
1319                          * or not.
1320                          */
1321                         do_last_check = true;
1322                 }
1323                 spin_lock_irqsave(hba->host->host_lock, flags);
1324         } while (tm_doorbell || tr_pending);
1325
1326         if (timeout) {
1327                 dev_err(hba->dev,
1328                         "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1329                         __func__, tm_doorbell, tr_pending);
1330                 ret = -EBUSY;
1331         }
1332 out:
1333         spin_unlock_irqrestore(hba->host->host_lock, flags);
1334         ufshcd_release(hba);
1335         return ret;
1336 }
1337
1338 /**
1339  * ufshcd_scale_gear - scale up/down UFS gear
1340  * @hba: per adapter instance
1341  * @scale_up: True for scaling up gear and false for scaling down
1342  *
1343  * Return: 0 for success; -EBUSY if scaling can't happen at this time;
1344  * non-zero for any other errors.
1345  */
1346 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1347 {
1348         int ret = 0;
1349         struct ufs_pa_layer_attr new_pwr_info;
1350
1351         if (scale_up) {
1352                 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info,
1353                        sizeof(struct ufs_pa_layer_attr));
1354         } else {
1355                 memcpy(&new_pwr_info, &hba->pwr_info,
1356                        sizeof(struct ufs_pa_layer_attr));
1357
1358                 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1359                     hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1360                         /* save the current power mode */
1361                         memcpy(&hba->clk_scaling.saved_pwr_info,
1362                                 &hba->pwr_info,
1363                                 sizeof(struct ufs_pa_layer_attr));
1364
1365                         /* scale down gear */
1366                         new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1367                         new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1368                 }
1369         }
1370
1371         /* check if the power mode needs to be changed or not? */
1372         ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1373         if (ret)
1374                 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1375                         __func__, ret,
1376                         hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1377                         new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1378
1379         return ret;
1380 }
1381
1382 /*
1383  * Wait until all pending SCSI commands and TMFs have finished or the timeout
1384  * has expired.
1385  *
1386  * Return: 0 upon success; -EBUSY upon timeout.
1387  */
1388 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us)
1389 {
1390         int ret = 0;
1391         /*
1392          * make sure that there are no outstanding requests when
1393          * clock scaling is in progress
1394          */
1395         ufshcd_scsi_block_requests(hba);
1396         mutex_lock(&hba->wb_mutex);
1397         down_write(&hba->clk_scaling_lock);
1398
1399         if (!hba->clk_scaling.is_allowed ||
1400             ufshcd_wait_for_doorbell_clr(hba, timeout_us)) {
1401                 ret = -EBUSY;
1402                 up_write(&hba->clk_scaling_lock);
1403                 mutex_unlock(&hba->wb_mutex);
1404                 ufshcd_scsi_unblock_requests(hba);
1405                 goto out;
1406         }
1407
1408         /* let's not get into low power until clock scaling is completed */
1409         ufshcd_hold(hba);
1410
1411 out:
1412         return ret;
1413 }
1414
1415 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up)
1416 {
1417         up_write(&hba->clk_scaling_lock);
1418
1419         /* Enable Write Booster if we have scaled up else disable it */
1420         if (ufshcd_enable_wb_if_scaling_up(hba) && !err)
1421                 ufshcd_wb_toggle(hba, scale_up);
1422
1423         mutex_unlock(&hba->wb_mutex);
1424
1425         ufshcd_scsi_unblock_requests(hba);
1426         ufshcd_release(hba);
1427 }
1428
1429 /**
1430  * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1431  * @hba: per adapter instance
1432  * @freq: frequency to scale
1433  * @scale_up: True for scaling up and false for scalin down
1434  *
1435  * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero
1436  * for any other errors.
1437  */
1438 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq,
1439                                 bool scale_up)
1440 {
1441         int ret = 0;
1442
1443         ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC);
1444         if (ret)
1445                 return ret;
1446
1447         /* scale down the gear before scaling down clocks */
1448         if (!scale_up) {
1449                 ret = ufshcd_scale_gear(hba, false);
1450                 if (ret)
1451                         goto out_unprepare;
1452         }
1453
1454         ret = ufshcd_scale_clks(hba, freq, scale_up);
1455         if (ret) {
1456                 if (!scale_up)
1457                         ufshcd_scale_gear(hba, true);
1458                 goto out_unprepare;
1459         }
1460
1461         /* scale up the gear after scaling up clocks */
1462         if (scale_up) {
1463                 ret = ufshcd_scale_gear(hba, true);
1464                 if (ret) {
1465                         ufshcd_scale_clks(hba, hba->devfreq->previous_freq,
1466                                           false);
1467                         goto out_unprepare;
1468                 }
1469         }
1470
1471 out_unprepare:
1472         ufshcd_clock_scaling_unprepare(hba, ret, scale_up);
1473         return ret;
1474 }
1475
1476 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1477 {
1478         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1479                                            clk_scaling.suspend_work);
1480         unsigned long irq_flags;
1481
1482         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1483         if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1484                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1485                 return;
1486         }
1487         hba->clk_scaling.is_suspended = true;
1488         hba->clk_scaling.window_start_t = 0;
1489         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1490
1491         devfreq_suspend_device(hba->devfreq);
1492 }
1493
1494 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1495 {
1496         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1497                                            clk_scaling.resume_work);
1498         unsigned long irq_flags;
1499
1500         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1501         if (!hba->clk_scaling.is_suspended) {
1502                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1503                 return;
1504         }
1505         hba->clk_scaling.is_suspended = false;
1506         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1507
1508         devfreq_resume_device(hba->devfreq);
1509 }
1510
1511 static int ufshcd_devfreq_target(struct device *dev,
1512                                 unsigned long *freq, u32 flags)
1513 {
1514         int ret = 0;
1515         struct ufs_hba *hba = dev_get_drvdata(dev);
1516         ktime_t start;
1517         bool scale_up = false, sched_clk_scaling_suspend_work = false;
1518         struct list_head *clk_list = &hba->clk_list_head;
1519         struct ufs_clk_info *clki;
1520         unsigned long irq_flags;
1521
1522         if (!ufshcd_is_clkscaling_supported(hba))
1523                 return -EINVAL;
1524
1525         if (hba->use_pm_opp) {
1526                 struct dev_pm_opp *opp;
1527
1528                 /* Get the recommended frequency from OPP framework */
1529                 opp = devfreq_recommended_opp(dev, freq, flags);
1530                 if (IS_ERR(opp))
1531                         return PTR_ERR(opp);
1532
1533                 dev_pm_opp_put(opp);
1534         } else {
1535                 /* Override with the closest supported frequency */
1536                 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info,
1537                                         list);
1538                 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1539         }
1540
1541         spin_lock_irqsave(hba->host->host_lock, irq_flags);
1542         if (ufshcd_eh_in_progress(hba)) {
1543                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1544                 return 0;
1545         }
1546
1547         /* Skip scaling clock when clock scaling is suspended */
1548         if (hba->clk_scaling.is_suspended) {
1549                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1550                 dev_warn(hba->dev, "clock scaling is suspended, skip");
1551                 return 0;
1552         }
1553
1554         if (!hba->clk_scaling.active_reqs)
1555                 sched_clk_scaling_suspend_work = true;
1556
1557         if (list_empty(clk_list)) {
1558                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1559                 goto out;
1560         }
1561
1562         /* Decide based on the target or rounded-off frequency and update */
1563         if (hba->use_pm_opp)
1564                 scale_up = *freq > hba->clk_scaling.target_freq;
1565         else
1566                 scale_up = *freq == clki->max_freq;
1567
1568         if (!hba->use_pm_opp && !scale_up)
1569                 *freq = clki->min_freq;
1570
1571         /* Update the frequency */
1572         if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) {
1573                 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1574                 ret = 0;
1575                 goto out; /* no state change required */
1576         }
1577         spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1578
1579         start = ktime_get();
1580         ret = ufshcd_devfreq_scale(hba, *freq, scale_up);
1581         if (!ret)
1582                 hba->clk_scaling.target_freq = *freq;
1583
1584         trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1585                 (scale_up ? "up" : "down"),
1586                 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1587
1588 out:
1589         if (sched_clk_scaling_suspend_work && !scale_up)
1590                 queue_work(hba->clk_scaling.workq,
1591                            &hba->clk_scaling.suspend_work);
1592
1593         return ret;
1594 }
1595
1596 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1597                 struct devfreq_dev_status *stat)
1598 {
1599         struct ufs_hba *hba = dev_get_drvdata(dev);
1600         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1601         unsigned long flags;
1602         ktime_t curr_t;
1603
1604         if (!ufshcd_is_clkscaling_supported(hba))
1605                 return -EINVAL;
1606
1607         memset(stat, 0, sizeof(*stat));
1608
1609         spin_lock_irqsave(hba->host->host_lock, flags);
1610         curr_t = ktime_get();
1611         if (!scaling->window_start_t)
1612                 goto start_window;
1613
1614         /*
1615          * If current frequency is 0, then the ondemand governor considers
1616          * there's no initial frequency set. And it always requests to set
1617          * to max. frequency.
1618          */
1619         if (hba->use_pm_opp) {
1620                 stat->current_frequency = hba->clk_scaling.target_freq;
1621         } else {
1622                 struct list_head *clk_list = &hba->clk_list_head;
1623                 struct ufs_clk_info *clki;
1624
1625                 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1626                 stat->current_frequency = clki->curr_freq;
1627         }
1628
1629         if (scaling->is_busy_started)
1630                 scaling->tot_busy_t += ktime_us_delta(curr_t,
1631                                 scaling->busy_start_t);
1632         stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1633         stat->busy_time = scaling->tot_busy_t;
1634 start_window:
1635         scaling->window_start_t = curr_t;
1636         scaling->tot_busy_t = 0;
1637
1638         if (scaling->active_reqs) {
1639                 scaling->busy_start_t = curr_t;
1640                 scaling->is_busy_started = true;
1641         } else {
1642                 scaling->busy_start_t = 0;
1643                 scaling->is_busy_started = false;
1644         }
1645         spin_unlock_irqrestore(hba->host->host_lock, flags);
1646         return 0;
1647 }
1648
1649 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1650 {
1651         struct list_head *clk_list = &hba->clk_list_head;
1652         struct ufs_clk_info *clki;
1653         struct devfreq *devfreq;
1654         int ret;
1655
1656         /* Skip devfreq if we don't have any clocks in the list */
1657         if (list_empty(clk_list))
1658                 return 0;
1659
1660         if (!hba->use_pm_opp) {
1661                 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1662                 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1663                 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1664         }
1665
1666         ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1667                                          &hba->vps->ondemand_data);
1668         devfreq = devfreq_add_device(hba->dev,
1669                         &hba->vps->devfreq_profile,
1670                         DEVFREQ_GOV_SIMPLE_ONDEMAND,
1671                         &hba->vps->ondemand_data);
1672         if (IS_ERR(devfreq)) {
1673                 ret = PTR_ERR(devfreq);
1674                 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1675
1676                 if (!hba->use_pm_opp) {
1677                         dev_pm_opp_remove(hba->dev, clki->min_freq);
1678                         dev_pm_opp_remove(hba->dev, clki->max_freq);
1679                 }
1680                 return ret;
1681         }
1682
1683         hba->devfreq = devfreq;
1684
1685         return 0;
1686 }
1687
1688 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1689 {
1690         struct list_head *clk_list = &hba->clk_list_head;
1691
1692         if (!hba->devfreq)
1693                 return;
1694
1695         devfreq_remove_device(hba->devfreq);
1696         hba->devfreq = NULL;
1697
1698         if (!hba->use_pm_opp) {
1699                 struct ufs_clk_info *clki;
1700
1701                 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1702                 dev_pm_opp_remove(hba->dev, clki->min_freq);
1703                 dev_pm_opp_remove(hba->dev, clki->max_freq);
1704         }
1705 }
1706
1707 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1708 {
1709         unsigned long flags;
1710         bool suspend = false;
1711
1712         cancel_work_sync(&hba->clk_scaling.suspend_work);
1713         cancel_work_sync(&hba->clk_scaling.resume_work);
1714
1715         spin_lock_irqsave(hba->host->host_lock, flags);
1716         if (!hba->clk_scaling.is_suspended) {
1717                 suspend = true;
1718                 hba->clk_scaling.is_suspended = true;
1719                 hba->clk_scaling.window_start_t = 0;
1720         }
1721         spin_unlock_irqrestore(hba->host->host_lock, flags);
1722
1723         if (suspend)
1724                 devfreq_suspend_device(hba->devfreq);
1725 }
1726
1727 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1728 {
1729         unsigned long flags;
1730         bool resume = false;
1731
1732         spin_lock_irqsave(hba->host->host_lock, flags);
1733         if (hba->clk_scaling.is_suspended) {
1734                 resume = true;
1735                 hba->clk_scaling.is_suspended = false;
1736         }
1737         spin_unlock_irqrestore(hba->host->host_lock, flags);
1738
1739         if (resume)
1740                 devfreq_resume_device(hba->devfreq);
1741 }
1742
1743 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1744                 struct device_attribute *attr, char *buf)
1745 {
1746         struct ufs_hba *hba = dev_get_drvdata(dev);
1747
1748         return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1749 }
1750
1751 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1752                 struct device_attribute *attr, const char *buf, size_t count)
1753 {
1754         struct ufs_hba *hba = dev_get_drvdata(dev);
1755         u32 value;
1756         int err = 0;
1757
1758         if (kstrtou32(buf, 0, &value))
1759                 return -EINVAL;
1760
1761         down(&hba->host_sem);
1762         if (!ufshcd_is_user_access_allowed(hba)) {
1763                 err = -EBUSY;
1764                 goto out;
1765         }
1766
1767         value = !!value;
1768         if (value == hba->clk_scaling.is_enabled)
1769                 goto out;
1770
1771         ufshcd_rpm_get_sync(hba);
1772         ufshcd_hold(hba);
1773
1774         hba->clk_scaling.is_enabled = value;
1775
1776         if (value) {
1777                 ufshcd_resume_clkscaling(hba);
1778         } else {
1779                 ufshcd_suspend_clkscaling(hba);
1780                 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true);
1781                 if (err)
1782                         dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1783                                         __func__, err);
1784         }
1785
1786         ufshcd_release(hba);
1787         ufshcd_rpm_put_sync(hba);
1788 out:
1789         up(&hba->host_sem);
1790         return err ? err : count;
1791 }
1792
1793 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1794 {
1795         hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1796         hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1797         sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1798         hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1799         hba->clk_scaling.enable_attr.attr.mode = 0644;
1800         if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1801                 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1802 }
1803
1804 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1805 {
1806         if (hba->clk_scaling.enable_attr.attr.name)
1807                 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1808 }
1809
1810 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1811 {
1812         char wq_name[sizeof("ufs_clkscaling_00")];
1813
1814         if (!ufshcd_is_clkscaling_supported(hba))
1815                 return;
1816
1817         if (!hba->clk_scaling.min_gear)
1818                 hba->clk_scaling.min_gear = UFS_HS_G1;
1819
1820         INIT_WORK(&hba->clk_scaling.suspend_work,
1821                   ufshcd_clk_scaling_suspend_work);
1822         INIT_WORK(&hba->clk_scaling.resume_work,
1823                   ufshcd_clk_scaling_resume_work);
1824
1825         snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1826                  hba->host->host_no);
1827         hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1828
1829         hba->clk_scaling.is_initialized = true;
1830 }
1831
1832 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1833 {
1834         if (!hba->clk_scaling.is_initialized)
1835                 return;
1836
1837         ufshcd_remove_clk_scaling_sysfs(hba);
1838         destroy_workqueue(hba->clk_scaling.workq);
1839         ufshcd_devfreq_remove(hba);
1840         hba->clk_scaling.is_initialized = false;
1841 }
1842
1843 static void ufshcd_ungate_work(struct work_struct *work)
1844 {
1845         int ret;
1846         unsigned long flags;
1847         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1848                         clk_gating.ungate_work);
1849
1850         cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1851
1852         spin_lock_irqsave(hba->host->host_lock, flags);
1853         if (hba->clk_gating.state == CLKS_ON) {
1854                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1855                 return;
1856         }
1857
1858         spin_unlock_irqrestore(hba->host->host_lock, flags);
1859         ufshcd_hba_vreg_set_hpm(hba);
1860         ufshcd_setup_clocks(hba, true);
1861
1862         ufshcd_enable_irq(hba);
1863
1864         /* Exit from hibern8 */
1865         if (ufshcd_can_hibern8_during_gating(hba)) {
1866                 /* Prevent gating in this path */
1867                 hba->clk_gating.is_suspended = true;
1868                 if (ufshcd_is_link_hibern8(hba)) {
1869                         ret = ufshcd_uic_hibern8_exit(hba);
1870                         if (ret)
1871                                 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1872                                         __func__, ret);
1873                         else
1874                                 ufshcd_set_link_active(hba);
1875                 }
1876                 hba->clk_gating.is_suspended = false;
1877         }
1878 }
1879
1880 /**
1881  * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1882  * Also, exit from hibern8 mode and set the link as active.
1883  * @hba: per adapter instance
1884  */
1885 void ufshcd_hold(struct ufs_hba *hba)
1886 {
1887         bool flush_result;
1888         unsigned long flags;
1889
1890         if (!ufshcd_is_clkgating_allowed(hba) ||
1891             !hba->clk_gating.is_initialized)
1892                 return;
1893         spin_lock_irqsave(hba->host->host_lock, flags);
1894         hba->clk_gating.active_reqs++;
1895
1896 start:
1897         switch (hba->clk_gating.state) {
1898         case CLKS_ON:
1899                 /*
1900                  * Wait for the ungate work to complete if in progress.
1901                  * Though the clocks may be in ON state, the link could
1902                  * still be in hibner8 state if hibern8 is allowed
1903                  * during clock gating.
1904                  * Make sure we exit hibern8 state also in addition to
1905                  * clocks being ON.
1906                  */
1907                 if (ufshcd_can_hibern8_during_gating(hba) &&
1908                     ufshcd_is_link_hibern8(hba)) {
1909                         spin_unlock_irqrestore(hba->host->host_lock, flags);
1910                         flush_result = flush_work(&hba->clk_gating.ungate_work);
1911                         if (hba->clk_gating.is_suspended && !flush_result)
1912                                 return;
1913                         spin_lock_irqsave(hba->host->host_lock, flags);
1914                         goto start;
1915                 }
1916                 break;
1917         case REQ_CLKS_OFF:
1918                 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1919                         hba->clk_gating.state = CLKS_ON;
1920                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1921                                                 hba->clk_gating.state);
1922                         break;
1923                 }
1924                 /*
1925                  * If we are here, it means gating work is either done or
1926                  * currently running. Hence, fall through to cancel gating
1927                  * work and to enable clocks.
1928                  */
1929                 fallthrough;
1930         case CLKS_OFF:
1931                 hba->clk_gating.state = REQ_CLKS_ON;
1932                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1933                                         hba->clk_gating.state);
1934                 queue_work(hba->clk_gating.clk_gating_workq,
1935                            &hba->clk_gating.ungate_work);
1936                 /*
1937                  * fall through to check if we should wait for this
1938                  * work to be done or not.
1939                  */
1940                 fallthrough;
1941         case REQ_CLKS_ON:
1942                 spin_unlock_irqrestore(hba->host->host_lock, flags);
1943                 flush_work(&hba->clk_gating.ungate_work);
1944                 /* Make sure state is CLKS_ON before returning */
1945                 spin_lock_irqsave(hba->host->host_lock, flags);
1946                 goto start;
1947         default:
1948                 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1949                                 __func__, hba->clk_gating.state);
1950                 break;
1951         }
1952         spin_unlock_irqrestore(hba->host->host_lock, flags);
1953 }
1954 EXPORT_SYMBOL_GPL(ufshcd_hold);
1955
1956 static void ufshcd_gate_work(struct work_struct *work)
1957 {
1958         struct ufs_hba *hba = container_of(work, struct ufs_hba,
1959                         clk_gating.gate_work.work);
1960         unsigned long flags;
1961         int ret;
1962
1963         spin_lock_irqsave(hba->host->host_lock, flags);
1964         /*
1965          * In case you are here to cancel this work the gating state
1966          * would be marked as REQ_CLKS_ON. In this case save time by
1967          * skipping the gating work and exit after changing the clock
1968          * state to CLKS_ON.
1969          */
1970         if (hba->clk_gating.is_suspended ||
1971                 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1972                 hba->clk_gating.state = CLKS_ON;
1973                 trace_ufshcd_clk_gating(dev_name(hba->dev),
1974                                         hba->clk_gating.state);
1975                 goto rel_lock;
1976         }
1977
1978         if (ufshcd_is_ufs_dev_busy(hba) || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL)
1979                 goto rel_lock;
1980
1981         spin_unlock_irqrestore(hba->host->host_lock, flags);
1982
1983         /* put the link into hibern8 mode before turning off clocks */
1984         if (ufshcd_can_hibern8_during_gating(hba)) {
1985                 ret = ufshcd_uic_hibern8_enter(hba);
1986                 if (ret) {
1987                         hba->clk_gating.state = CLKS_ON;
1988                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1989                                         __func__, ret);
1990                         trace_ufshcd_clk_gating(dev_name(hba->dev),
1991                                                 hba->clk_gating.state);
1992                         goto out;
1993                 }
1994                 ufshcd_set_link_hibern8(hba);
1995         }
1996
1997         ufshcd_disable_irq(hba);
1998
1999         ufshcd_setup_clocks(hba, false);
2000
2001         /* Put the host controller in low power mode if possible */
2002         ufshcd_hba_vreg_set_lpm(hba);
2003         /*
2004          * In case you are here to cancel this work the gating state
2005          * would be marked as REQ_CLKS_ON. In this case keep the state
2006          * as REQ_CLKS_ON which would anyway imply that clocks are off
2007          * and a request to turn them on is pending. By doing this way,
2008          * we keep the state machine in tact and this would ultimately
2009          * prevent from doing cancel work multiple times when there are
2010          * new requests arriving before the current cancel work is done.
2011          */
2012         spin_lock_irqsave(hba->host->host_lock, flags);
2013         if (hba->clk_gating.state == REQ_CLKS_OFF) {
2014                 hba->clk_gating.state = CLKS_OFF;
2015                 trace_ufshcd_clk_gating(dev_name(hba->dev),
2016                                         hba->clk_gating.state);
2017         }
2018 rel_lock:
2019         spin_unlock_irqrestore(hba->host->host_lock, flags);
2020 out:
2021         return;
2022 }
2023
2024 /* host lock must be held before calling this variant */
2025 static void __ufshcd_release(struct ufs_hba *hba)
2026 {
2027         if (!ufshcd_is_clkgating_allowed(hba))
2028                 return;
2029
2030         hba->clk_gating.active_reqs--;
2031
2032         if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
2033             hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
2034             hba->outstanding_tasks || !hba->clk_gating.is_initialized ||
2035             hba->active_uic_cmd || hba->uic_async_done ||
2036             hba->clk_gating.state == CLKS_OFF)
2037                 return;
2038
2039         hba->clk_gating.state = REQ_CLKS_OFF;
2040         trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
2041         queue_delayed_work(hba->clk_gating.clk_gating_workq,
2042                            &hba->clk_gating.gate_work,
2043                            msecs_to_jiffies(hba->clk_gating.delay_ms));
2044 }
2045
2046 void ufshcd_release(struct ufs_hba *hba)
2047 {
2048         unsigned long flags;
2049
2050         spin_lock_irqsave(hba->host->host_lock, flags);
2051         __ufshcd_release(hba);
2052         spin_unlock_irqrestore(hba->host->host_lock, flags);
2053 }
2054 EXPORT_SYMBOL_GPL(ufshcd_release);
2055
2056 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
2057                 struct device_attribute *attr, char *buf)
2058 {
2059         struct ufs_hba *hba = dev_get_drvdata(dev);
2060
2061         return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
2062 }
2063
2064 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value)
2065 {
2066         struct ufs_hba *hba = dev_get_drvdata(dev);
2067         unsigned long flags;
2068
2069         spin_lock_irqsave(hba->host->host_lock, flags);
2070         hba->clk_gating.delay_ms = value;
2071         spin_unlock_irqrestore(hba->host->host_lock, flags);
2072 }
2073 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set);
2074
2075 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
2076                 struct device_attribute *attr, const char *buf, size_t count)
2077 {
2078         unsigned long value;
2079
2080         if (kstrtoul(buf, 0, &value))
2081                 return -EINVAL;
2082
2083         ufshcd_clkgate_delay_set(dev, value);
2084         return count;
2085 }
2086
2087 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
2088                 struct device_attribute *attr, char *buf)
2089 {
2090         struct ufs_hba *hba = dev_get_drvdata(dev);
2091
2092         return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
2093 }
2094
2095 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
2096                 struct device_attribute *attr, const char *buf, size_t count)
2097 {
2098         struct ufs_hba *hba = dev_get_drvdata(dev);
2099         unsigned long flags;
2100         u32 value;
2101
2102         if (kstrtou32(buf, 0, &value))
2103                 return -EINVAL;
2104
2105         value = !!value;
2106
2107         spin_lock_irqsave(hba->host->host_lock, flags);
2108         if (value == hba->clk_gating.is_enabled)
2109                 goto out;
2110
2111         if (value)
2112                 __ufshcd_release(hba);
2113         else
2114                 hba->clk_gating.active_reqs++;
2115
2116         hba->clk_gating.is_enabled = value;
2117 out:
2118         spin_unlock_irqrestore(hba->host->host_lock, flags);
2119         return count;
2120 }
2121
2122 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
2123 {
2124         hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
2125         hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
2126         sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
2127         hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
2128         hba->clk_gating.delay_attr.attr.mode = 0644;
2129         if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
2130                 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
2131
2132         hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
2133         hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
2134         sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
2135         hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
2136         hba->clk_gating.enable_attr.attr.mode = 0644;
2137         if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
2138                 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
2139 }
2140
2141 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
2142 {
2143         if (hba->clk_gating.delay_attr.attr.name)
2144                 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
2145         if (hba->clk_gating.enable_attr.attr.name)
2146                 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
2147 }
2148
2149 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
2150 {
2151         char wq_name[sizeof("ufs_clk_gating_00")];
2152
2153         if (!ufshcd_is_clkgating_allowed(hba))
2154                 return;
2155
2156         hba->clk_gating.state = CLKS_ON;
2157
2158         hba->clk_gating.delay_ms = 150;
2159         INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
2160         INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
2161
2162         snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
2163                  hba->host->host_no);
2164         hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
2165                                         WQ_MEM_RECLAIM | WQ_HIGHPRI);
2166
2167         ufshcd_init_clk_gating_sysfs(hba);
2168
2169         hba->clk_gating.is_enabled = true;
2170         hba->clk_gating.is_initialized = true;
2171 }
2172
2173 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
2174 {
2175         if (!hba->clk_gating.is_initialized)
2176                 return;
2177
2178         ufshcd_remove_clk_gating_sysfs(hba);
2179
2180         /* Ungate the clock if necessary. */
2181         ufshcd_hold(hba);
2182         hba->clk_gating.is_initialized = false;
2183         ufshcd_release(hba);
2184
2185         destroy_workqueue(hba->clk_gating.clk_gating_workq);
2186 }
2187
2188 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2189 {
2190         bool queue_resume_work = false;
2191         ktime_t curr_t = ktime_get();
2192         unsigned long flags;
2193
2194         if (!ufshcd_is_clkscaling_supported(hba))
2195                 return;
2196
2197         spin_lock_irqsave(hba->host->host_lock, flags);
2198         if (!hba->clk_scaling.active_reqs++)
2199                 queue_resume_work = true;
2200
2201         if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
2202                 spin_unlock_irqrestore(hba->host->host_lock, flags);
2203                 return;
2204         }
2205
2206         if (queue_resume_work)
2207                 queue_work(hba->clk_scaling.workq,
2208                            &hba->clk_scaling.resume_work);
2209
2210         if (!hba->clk_scaling.window_start_t) {
2211                 hba->clk_scaling.window_start_t = curr_t;
2212                 hba->clk_scaling.tot_busy_t = 0;
2213                 hba->clk_scaling.is_busy_started = false;
2214         }
2215
2216         if (!hba->clk_scaling.is_busy_started) {
2217                 hba->clk_scaling.busy_start_t = curr_t;
2218                 hba->clk_scaling.is_busy_started = true;
2219         }
2220         spin_unlock_irqrestore(hba->host->host_lock, flags);
2221 }
2222
2223 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2224 {
2225         struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2226         unsigned long flags;
2227
2228         if (!ufshcd_is_clkscaling_supported(hba))
2229                 return;
2230
2231         spin_lock_irqsave(hba->host->host_lock, flags);
2232         hba->clk_scaling.active_reqs--;
2233         if (!scaling->active_reqs && scaling->is_busy_started) {
2234                 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2235                                         scaling->busy_start_t));
2236                 scaling->busy_start_t = 0;
2237                 scaling->is_busy_started = false;
2238         }
2239         spin_unlock_irqrestore(hba->host->host_lock, flags);
2240 }
2241
2242 static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2243 {
2244         if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2245                 return READ;
2246         else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2247                 return WRITE;
2248         else
2249                 return -EINVAL;
2250 }
2251
2252 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2253                                                 struct ufshcd_lrb *lrbp)
2254 {
2255         const struct ufs_hba_monitor *m = &hba->monitor;
2256
2257         return (m->enabled && lrbp && lrbp->cmd &&
2258                 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2259                 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2260 }
2261
2262 static void ufshcd_start_monitor(struct ufs_hba *hba,
2263                                  const struct ufshcd_lrb *lrbp)
2264 {
2265         int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2266         unsigned long flags;
2267
2268         spin_lock_irqsave(hba->host->host_lock, flags);
2269         if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2270                 hba->monitor.busy_start_ts[dir] = ktime_get();
2271         spin_unlock_irqrestore(hba->host->host_lock, flags);
2272 }
2273
2274 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp)
2275 {
2276         int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2277         unsigned long flags;
2278
2279         spin_lock_irqsave(hba->host->host_lock, flags);
2280         if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2281                 const struct request *req = scsi_cmd_to_rq(lrbp->cmd);
2282                 struct ufs_hba_monitor *m = &hba->monitor;
2283                 ktime_t now, inc, lat;
2284
2285                 now = lrbp->compl_time_stamp;
2286                 inc = ktime_sub(now, m->busy_start_ts[dir]);
2287                 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2288                 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2289
2290                 /* Update latencies */
2291                 m->nr_req[dir]++;
2292                 lat = ktime_sub(now, lrbp->issue_time_stamp);
2293                 m->lat_sum[dir] += lat;
2294                 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2295                         m->lat_max[dir] = lat;
2296                 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2297                         m->lat_min[dir] = lat;
2298
2299                 m->nr_queued[dir]--;
2300                 /* Push forward the busy start of monitor */
2301                 m->busy_start_ts[dir] = now;
2302         }
2303         spin_unlock_irqrestore(hba->host->host_lock, flags);
2304 }
2305
2306 /**
2307  * ufshcd_send_command - Send SCSI or device management commands
2308  * @hba: per adapter instance
2309  * @task_tag: Task tag of the command
2310  * @hwq: pointer to hardware queue instance
2311  */
2312 static inline
2313 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag,
2314                          struct ufs_hw_queue *hwq)
2315 {
2316         struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2317         unsigned long flags;
2318
2319         lrbp->issue_time_stamp = ktime_get();
2320         lrbp->issue_time_stamp_local_clock = local_clock();
2321         lrbp->compl_time_stamp = ktime_set(0, 0);
2322         lrbp->compl_time_stamp_local_clock = 0;
2323         ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2324         if (lrbp->cmd)
2325                 ufshcd_clk_scaling_start_busy(hba);
2326         if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2327                 ufshcd_start_monitor(hba, lrbp);
2328
2329         if (is_mcq_enabled(hba)) {
2330                 int utrd_size = sizeof(struct utp_transfer_req_desc);
2331                 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr;
2332                 struct utp_transfer_req_desc *dest;
2333
2334                 spin_lock(&hwq->sq_lock);
2335                 dest = hwq->sqe_base_addr + hwq->sq_tail_slot;
2336                 memcpy(dest, src, utrd_size);
2337                 ufshcd_inc_sq_tail(hwq);
2338                 spin_unlock(&hwq->sq_lock);
2339         } else {
2340                 spin_lock_irqsave(&hba->outstanding_lock, flags);
2341                 if (hba->vops && hba->vops->setup_xfer_req)
2342                         hba->vops->setup_xfer_req(hba, lrbp->task_tag,
2343                                                   !!lrbp->cmd);
2344                 __set_bit(lrbp->task_tag, &hba->outstanding_reqs);
2345                 ufshcd_writel(hba, 1 << lrbp->task_tag,
2346                               REG_UTP_TRANSFER_REQ_DOOR_BELL);
2347                 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2348         }
2349 }
2350
2351 /**
2352  * ufshcd_copy_sense_data - Copy sense data in case of check condition
2353  * @lrbp: pointer to local reference block
2354  */
2355 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2356 {
2357         u8 *const sense_buffer = lrbp->cmd->sense_buffer;
2358         u16 resp_len;
2359         int len;
2360
2361         resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length);
2362         if (sense_buffer && resp_len) {
2363                 int len_to_copy;
2364
2365                 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2366                 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2367
2368                 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2369                        len_to_copy);
2370         }
2371 }
2372
2373 /**
2374  * ufshcd_copy_query_response() - Copy the Query Response and the data
2375  * descriptor
2376  * @hba: per adapter instance
2377  * @lrbp: pointer to local reference block
2378  *
2379  * Return: 0 upon success; < 0 upon failure.
2380  */
2381 static
2382 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2383 {
2384         struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2385
2386         memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2387
2388         /* Get the descriptor */
2389         if (hba->dev_cmd.query.descriptor &&
2390             lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2391                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2392                                 GENERAL_UPIU_REQUEST_SIZE;
2393                 u16 resp_len;
2394                 u16 buf_len;
2395
2396                 /* data segment length */
2397                 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
2398                                        .data_segment_length);
2399                 buf_len = be16_to_cpu(
2400                                 hba->dev_cmd.query.request.upiu_req.length);
2401                 if (likely(buf_len >= resp_len)) {
2402                         memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2403                 } else {
2404                         dev_warn(hba->dev,
2405                                  "%s: rsp size %d is bigger than buffer size %d",
2406                                  __func__, resp_len, buf_len);
2407                         return -EINVAL;
2408                 }
2409         }
2410
2411         return 0;
2412 }
2413
2414 /**
2415  * ufshcd_hba_capabilities - Read controller capabilities
2416  * @hba: per adapter instance
2417  *
2418  * Return: 0 on success, negative on error.
2419  */
2420 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2421 {
2422         int err;
2423
2424         hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2425         if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
2426                 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
2427
2428         /* nutrs and nutmrs are 0 based values */
2429         hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2430         hba->nutmrs =
2431         ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2432         hba->reserved_slot = hba->nutrs - 1;
2433
2434         /* Read crypto capabilities */
2435         err = ufshcd_hba_init_crypto_capabilities(hba);
2436         if (err) {
2437                 dev_err(hba->dev, "crypto setup failed\n");
2438                 return err;
2439         }
2440
2441         hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities);
2442         if (!hba->mcq_sup)
2443                 return 0;
2444
2445         hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP);
2446         hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT,
2447                                      hba->mcq_capabilities);
2448
2449         return 0;
2450 }
2451
2452 /**
2453  * ufshcd_ready_for_uic_cmd - Check if controller is ready
2454  *                            to accept UIC commands
2455  * @hba: per adapter instance
2456  *
2457  * Return: true on success, else false.
2458  */
2459 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2460 {
2461         u32 val;
2462         int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY,
2463                                     500, UIC_CMD_TIMEOUT * 1000, false, hba,
2464                                     REG_CONTROLLER_STATUS);
2465         return ret == 0;
2466 }
2467
2468 /**
2469  * ufshcd_get_upmcrs - Get the power mode change request status
2470  * @hba: Pointer to adapter instance
2471  *
2472  * This function gets the UPMCRS field of HCS register
2473  *
2474  * Return: value of UPMCRS field.
2475  */
2476 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2477 {
2478         return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2479 }
2480
2481 /**
2482  * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
2483  * @hba: per adapter instance
2484  * @uic_cmd: UIC command
2485  */
2486 static inline void
2487 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2488 {
2489         lockdep_assert_held(&hba->uic_cmd_mutex);
2490
2491         WARN_ON(hba->active_uic_cmd);
2492
2493         hba->active_uic_cmd = uic_cmd;
2494
2495         /* Write Args */
2496         ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2497         ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2498         ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2499
2500         ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2501
2502         /* Write UIC Cmd */
2503         ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2504                       REG_UIC_COMMAND);
2505 }
2506
2507 /**
2508  * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
2509  * @hba: per adapter instance
2510  * @uic_cmd: UIC command
2511  *
2512  * Return: 0 only if success.
2513  */
2514 static int
2515 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2516 {
2517         int ret;
2518         unsigned long flags;
2519
2520         lockdep_assert_held(&hba->uic_cmd_mutex);
2521
2522         if (wait_for_completion_timeout(&uic_cmd->done,
2523                                         msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2524                 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2525         } else {
2526                 ret = -ETIMEDOUT;
2527                 dev_err(hba->dev,
2528                         "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2529                         uic_cmd->command, uic_cmd->argument3);
2530
2531                 if (!uic_cmd->cmd_active) {
2532                         dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2533                                 __func__);
2534                         ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2535                 }
2536         }
2537
2538         spin_lock_irqsave(hba->host->host_lock, flags);
2539         hba->active_uic_cmd = NULL;
2540         spin_unlock_irqrestore(hba->host->host_lock, flags);
2541
2542         return ret;
2543 }
2544
2545 /**
2546  * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2547  * @hba: per adapter instance
2548  * @uic_cmd: UIC command
2549  * @completion: initialize the completion only if this is set to true
2550  *
2551  * Return: 0 only if success.
2552  */
2553 static int
2554 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2555                       bool completion)
2556 {
2557         lockdep_assert_held(&hba->uic_cmd_mutex);
2558
2559         if (!ufshcd_ready_for_uic_cmd(hba)) {
2560                 dev_err(hba->dev,
2561                         "Controller not ready to accept UIC commands\n");
2562                 return -EIO;
2563         }
2564
2565         if (completion)
2566                 init_completion(&uic_cmd->done);
2567
2568         uic_cmd->cmd_active = 1;
2569         ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2570
2571         return 0;
2572 }
2573
2574 /**
2575  * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2576  * @hba: per adapter instance
2577  * @uic_cmd: UIC command
2578  *
2579  * Return: 0 only if success.
2580  */
2581 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2582 {
2583         int ret;
2584
2585         if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2586                 return 0;
2587
2588         ufshcd_hold(hba);
2589         mutex_lock(&hba->uic_cmd_mutex);
2590         ufshcd_add_delay_before_dme_cmd(hba);
2591
2592         ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2593         if (!ret)
2594                 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2595
2596         mutex_unlock(&hba->uic_cmd_mutex);
2597
2598         ufshcd_release(hba);
2599         return ret;
2600 }
2601
2602 /**
2603  * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format)
2604  * @hba:        per-adapter instance
2605  * @lrbp:       pointer to local reference block
2606  * @sg_entries: The number of sg lists actually used
2607  * @sg_list:    Pointer to SG list
2608  */
2609 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries,
2610                                struct scatterlist *sg_list)
2611 {
2612         struct ufshcd_sg_entry *prd;
2613         struct scatterlist *sg;
2614         int i;
2615
2616         if (sg_entries) {
2617
2618                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2619                         lrbp->utr_descriptor_ptr->prd_table_length =
2620                                 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba));
2621                 else
2622                         lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries);
2623
2624                 prd = lrbp->ucd_prdt_ptr;
2625
2626                 for_each_sg(sg_list, sg, sg_entries, i) {
2627                         const unsigned int len = sg_dma_len(sg);
2628
2629                         /*
2630                          * From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2631                          * based value that indicates the length, in bytes, of
2632                          * the data block. A maximum of length of 256KB may
2633                          * exist for any entry. Bits 1:0 of this field shall be
2634                          * 11b to indicate Dword granularity. A value of '3'
2635                          * indicates 4 bytes, '7' indicates 8 bytes, etc."
2636                          */
2637                         WARN_ONCE(len > SZ_256K, "len = %#x\n", len);
2638                         prd->size = cpu_to_le32(len - 1);
2639                         prd->addr = cpu_to_le64(sg->dma_address);
2640                         prd->reserved = 0;
2641                         prd = (void *)prd + ufshcd_sg_entry_size(hba);
2642                 }
2643         } else {
2644                 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2645         }
2646 }
2647
2648 /**
2649  * ufshcd_map_sg - Map scatter-gather list to prdt
2650  * @hba: per adapter instance
2651  * @lrbp: pointer to local reference block
2652  *
2653  * Return: 0 in case of success, non-zero value in case of failure.
2654  */
2655 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2656 {
2657         struct scsi_cmnd *cmd = lrbp->cmd;
2658         int sg_segments = scsi_dma_map(cmd);
2659
2660         if (sg_segments < 0)
2661                 return sg_segments;
2662
2663         ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd));
2664
2665         return 0;
2666 }
2667
2668 /**
2669  * ufshcd_enable_intr - enable interrupts
2670  * @hba: per adapter instance
2671  * @intrs: interrupt bits
2672  */
2673 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2674 {
2675         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2676
2677         if (hba->ufs_version == ufshci_version(1, 0)) {
2678                 u32 rw;
2679                 rw = set & INTERRUPT_MASK_RW_VER_10;
2680                 set = rw | ((set ^ intrs) & intrs);
2681         } else {
2682                 set |= intrs;
2683         }
2684
2685         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2686 }
2687
2688 /**
2689  * ufshcd_disable_intr - disable interrupts
2690  * @hba: per adapter instance
2691  * @intrs: interrupt bits
2692  */
2693 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2694 {
2695         u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2696
2697         if (hba->ufs_version == ufshci_version(1, 0)) {
2698                 u32 rw;
2699                 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2700                         ~(intrs & INTERRUPT_MASK_RW_VER_10);
2701                 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2702
2703         } else {
2704                 set &= ~intrs;
2705         }
2706
2707         ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2708 }
2709
2710 /**
2711  * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request
2712  * descriptor according to request
2713  * @lrbp: pointer to local reference block
2714  * @upiu_flags: flags required in the header
2715  * @cmd_dir: requests data direction
2716  * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments)
2717  */
2718 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags,
2719                                         enum dma_data_direction cmd_dir, int ehs_length)
2720 {
2721         struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2722         struct request_desc_header *h = &req_desc->header;
2723         enum utp_data_direction data_direction;
2724
2725         *h = (typeof(*h)){ };
2726
2727         if (cmd_dir == DMA_FROM_DEVICE) {
2728                 data_direction = UTP_DEVICE_TO_HOST;
2729                 *upiu_flags = UPIU_CMD_FLAGS_READ;
2730         } else if (cmd_dir == DMA_TO_DEVICE) {
2731                 data_direction = UTP_HOST_TO_DEVICE;
2732                 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2733         } else {
2734                 data_direction = UTP_NO_DATA_TRANSFER;
2735                 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2736         }
2737
2738         h->command_type = lrbp->command_type;
2739         h->data_direction = data_direction;
2740         h->ehs_length = ehs_length;
2741
2742         if (lrbp->intr_cmd)
2743                 h->interrupt = 1;
2744
2745         /* Prepare crypto related dwords */
2746         ufshcd_prepare_req_desc_hdr_crypto(lrbp, h);
2747
2748         /*
2749          * assigning invalid value for command status. Controller
2750          * updates OCS on command completion, with the command
2751          * status
2752          */
2753         h->ocs = OCS_INVALID_COMMAND_STATUS;
2754
2755         req_desc->prd_table_length = 0;
2756 }
2757
2758 /**
2759  * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2760  * for scsi commands
2761  * @lrbp: local reference block pointer
2762  * @upiu_flags: flags
2763  */
2764 static
2765 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2766 {
2767         struct scsi_cmnd *cmd = lrbp->cmd;
2768         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2769         unsigned short cdb_len;
2770
2771         ucd_req_ptr->header = (struct utp_upiu_header){
2772                 .transaction_code = UPIU_TRANSACTION_COMMAND,
2773                 .flags = upiu_flags,
2774                 .lun = lrbp->lun,
2775                 .task_tag = lrbp->task_tag,
2776                 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI,
2777         };
2778
2779         WARN_ON_ONCE(ucd_req_ptr->header.task_tag != lrbp->task_tag);
2780
2781         ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2782
2783         cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2784         memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2785         memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2786
2787         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2788 }
2789
2790 /**
2791  * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request
2792  * @hba: UFS hba
2793  * @lrbp: local reference block pointer
2794  * @upiu_flags: flags
2795  */
2796 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2797                                 struct ufshcd_lrb *lrbp, u8 upiu_flags)
2798 {
2799         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2800         struct ufs_query *query = &hba->dev_cmd.query;
2801         u16 len = be16_to_cpu(query->request.upiu_req.length);
2802
2803         /* Query request header */
2804         ucd_req_ptr->header = (struct utp_upiu_header){
2805                 .transaction_code = UPIU_TRANSACTION_QUERY_REQ,
2806                 .flags = upiu_flags,
2807                 .lun = lrbp->lun,
2808                 .task_tag = lrbp->task_tag,
2809                 .query_function = query->request.query_func,
2810                 /* Data segment length only need for WRITE_DESC */
2811                 .data_segment_length =
2812                         query->request.upiu_req.opcode ==
2813                                         UPIU_QUERY_OPCODE_WRITE_DESC ?
2814                                 cpu_to_be16(len) :
2815                                 0,
2816         };
2817
2818         /* Copy the Query Request buffer as is */
2819         memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2820                         QUERY_OSF_SIZE);
2821
2822         /* Copy the Descriptor */
2823         if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2824                 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2825
2826         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2827 }
2828
2829 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2830 {
2831         struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2832
2833         memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2834
2835         ucd_req_ptr->header = (struct utp_upiu_header){
2836                 .transaction_code = UPIU_TRANSACTION_NOP_OUT,
2837                 .task_tag = lrbp->task_tag,
2838         };
2839
2840         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2841 }
2842
2843 /**
2844  * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2845  *                           for Device Management Purposes
2846  * @hba: per adapter instance
2847  * @lrbp: pointer to local reference block
2848  *
2849  * Return: 0 upon success; < 0 upon failure.
2850  */
2851 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2852                                       struct ufshcd_lrb *lrbp)
2853 {
2854         u8 upiu_flags;
2855         int ret = 0;
2856
2857         if (hba->ufs_version <= ufshci_version(1, 1))
2858                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2859         else
2860                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2861
2862         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
2863         if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2864                 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2865         else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2866                 ufshcd_prepare_utp_nop_upiu(lrbp);
2867         else
2868                 ret = -EINVAL;
2869
2870         return ret;
2871 }
2872
2873 /**
2874  * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2875  *                         for SCSI Purposes
2876  * @hba: per adapter instance
2877  * @lrbp: pointer to local reference block
2878  */
2879 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2880 {
2881         struct request *rq = scsi_cmd_to_rq(lrbp->cmd);
2882         unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq));
2883         u8 upiu_flags;
2884
2885         if (hba->ufs_version <= ufshci_version(1, 1))
2886                 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2887         else
2888                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2889
2890         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2891                                     lrbp->cmd->sc_data_direction, 0);
2892         if (ioprio_class == IOPRIO_CLASS_RT)
2893                 upiu_flags |= UPIU_CMD_FLAGS_CP;
2894         ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2895 }
2896
2897 /**
2898  * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2899  * @upiu_wlun_id: UPIU W-LUN id
2900  *
2901  * Return: SCSI W-LUN id.
2902  */
2903 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2904 {
2905         return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2906 }
2907
2908 static inline bool is_device_wlun(struct scsi_device *sdev)
2909 {
2910         return sdev->lun ==
2911                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2912 }
2913
2914 /*
2915  * Associate the UFS controller queue with the default and poll HCTX types.
2916  * Initialize the mq_map[] arrays.
2917  */
2918 static void ufshcd_map_queues(struct Scsi_Host *shost)
2919 {
2920         struct ufs_hba *hba = shost_priv(shost);
2921         int i, queue_offset = 0;
2922
2923         if (!is_mcq_supported(hba)) {
2924                 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1;
2925                 hba->nr_queues[HCTX_TYPE_READ] = 0;
2926                 hba->nr_queues[HCTX_TYPE_POLL] = 1;
2927                 hba->nr_hw_queues = 1;
2928         }
2929
2930         for (i = 0; i < shost->nr_maps; i++) {
2931                 struct blk_mq_queue_map *map = &shost->tag_set.map[i];
2932
2933                 map->nr_queues = hba->nr_queues[i];
2934                 if (!map->nr_queues)
2935                         continue;
2936                 map->queue_offset = queue_offset;
2937                 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba))
2938                         map->queue_offset = 0;
2939
2940                 blk_mq_map_queues(map);
2941                 queue_offset += map->nr_queues;
2942         }
2943 }
2944
2945 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2946 {
2947         struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr +
2948                 i * ufshcd_get_ucd_size(hba);
2949         struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2950         dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2951                 i * ufshcd_get_ucd_size(hba);
2952         u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2953                                        response_upiu);
2954         u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2955
2956         lrb->utr_descriptor_ptr = utrdlp + i;
2957         lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2958                 i * sizeof(struct utp_transfer_req_desc);
2959         lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu;
2960         lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2961         lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu;
2962         lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2963         lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table;
2964         lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2965 }
2966
2967 /**
2968  * ufshcd_queuecommand - main entry point for SCSI requests
2969  * @host: SCSI host pointer
2970  * @cmd: command from SCSI Midlayer
2971  *
2972  * Return: 0 for success, non-zero in case of failure.
2973  */
2974 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2975 {
2976         struct ufs_hba *hba = shost_priv(host);
2977         int tag = scsi_cmd_to_rq(cmd)->tag;
2978         struct ufshcd_lrb *lrbp;
2979         int err = 0;
2980         struct ufs_hw_queue *hwq = NULL;
2981
2982         switch (hba->ufshcd_state) {
2983         case UFSHCD_STATE_OPERATIONAL:
2984                 break;
2985         case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2986                 /*
2987                  * SCSI error handler can call ->queuecommand() while UFS error
2988                  * handler is in progress. Error interrupts could change the
2989                  * state from UFSHCD_STATE_RESET to
2990                  * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
2991                  * being issued in that case.
2992                  */
2993                 if (ufshcd_eh_in_progress(hba)) {
2994                         err = SCSI_MLQUEUE_HOST_BUSY;
2995                         goto out;
2996                 }
2997                 break;
2998         case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2999                 /*
3000                  * pm_runtime_get_sync() is used at error handling preparation
3001                  * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
3002                  * PM ops, it can never be finished if we let SCSI layer keep
3003                  * retrying it, which gets err handler stuck forever. Neither
3004                  * can we let the scsi cmd pass through, because UFS is in bad
3005                  * state, the scsi cmd may eventually time out, which will get
3006                  * err handler blocked for too long. So, just fail the scsi cmd
3007                  * sent from PM ops, err handler can recover PM error anyways.
3008                  */
3009                 if (hba->pm_op_in_progress) {
3010                         hba->force_reset = true;
3011                         set_host_byte(cmd, DID_BAD_TARGET);
3012                         scsi_done(cmd);
3013                         goto out;
3014                 }
3015                 fallthrough;
3016         case UFSHCD_STATE_RESET:
3017                 err = SCSI_MLQUEUE_HOST_BUSY;
3018                 goto out;
3019         case UFSHCD_STATE_ERROR:
3020                 set_host_byte(cmd, DID_ERROR);
3021                 scsi_done(cmd);
3022                 goto out;
3023         }
3024
3025         hba->req_abort_count = 0;
3026
3027         ufshcd_hold(hba);
3028
3029         lrbp = &hba->lrb[tag];
3030         lrbp->cmd = cmd;
3031         lrbp->task_tag = tag;
3032         lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
3033         lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
3034
3035         ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
3036
3037         lrbp->req_abort_skip = false;
3038
3039         ufshcd_comp_scsi_upiu(hba, lrbp);
3040
3041         err = ufshcd_map_sg(hba, lrbp);
3042         if (err) {
3043                 ufshcd_release(hba);
3044                 goto out;
3045         }
3046
3047         if (is_mcq_enabled(hba))
3048                 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd));
3049
3050         ufshcd_send_command(hba, tag, hwq);
3051
3052 out:
3053         if (ufs_trigger_eh(hba)) {
3054                 unsigned long flags;
3055
3056                 spin_lock_irqsave(hba->host->host_lock, flags);
3057                 ufshcd_schedule_eh_work(hba);
3058                 spin_unlock_irqrestore(hba->host->host_lock, flags);
3059         }
3060
3061         return err;
3062 }
3063
3064 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
3065                 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
3066 {
3067         lrbp->cmd = NULL;
3068         lrbp->task_tag = tag;
3069         lrbp->lun = 0; /* device management cmd is not specific to any LUN */
3070         lrbp->intr_cmd = true; /* No interrupt aggregation */
3071         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
3072         hba->dev_cmd.type = cmd_type;
3073
3074         return ufshcd_compose_devman_upiu(hba, lrbp);
3075 }
3076
3077 /*
3078  * Check with the block layer if the command is inflight
3079  * @cmd: command to check.
3080  *
3081  * Return: true if command is inflight; false if not.
3082  */
3083 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd)
3084 {
3085         struct request *rq;
3086
3087         if (!cmd)
3088                 return false;
3089
3090         rq = scsi_cmd_to_rq(cmd);
3091         if (!blk_mq_request_started(rq))
3092                 return false;
3093
3094         return true;
3095 }
3096
3097 /*
3098  * Clear the pending command in the controller and wait until
3099  * the controller confirms that the command has been cleared.
3100  * @hba: per adapter instance
3101  * @task_tag: The tag number of the command to be cleared.
3102  */
3103 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag)
3104 {
3105         u32 mask;
3106         unsigned long flags;
3107         int err;
3108
3109         if (is_mcq_enabled(hba)) {
3110                 /*
3111                  * MCQ mode. Clean up the MCQ resources similar to
3112                  * what the ufshcd_utrl_clear() does for SDB mode.
3113                  */
3114                 err = ufshcd_mcq_sq_cleanup(hba, task_tag);
3115                 if (err) {
3116                         dev_err(hba->dev, "%s: failed tag=%d. err=%d\n",
3117                                 __func__, task_tag, err);
3118                         return err;
3119                 }
3120                 return 0;
3121         }
3122
3123         mask = 1U << task_tag;
3124
3125         /* clear outstanding transaction before retry */
3126         spin_lock_irqsave(hba->host->host_lock, flags);
3127         ufshcd_utrl_clear(hba, mask);
3128         spin_unlock_irqrestore(hba->host->host_lock, flags);
3129
3130         /*
3131          * wait for h/w to clear corresponding bit in door-bell.
3132          * max. wait is 1 sec.
3133          */
3134         return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL,
3135                                         mask, ~mask, 1000, 1000);
3136 }
3137
3138 /**
3139  * ufshcd_dev_cmd_completion() - handles device management command responses
3140  * @hba: per adapter instance
3141  * @lrbp: pointer to local reference block
3142  *
3143  * Return: 0 upon success; < 0 upon failure.
3144  */
3145 static int
3146 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
3147 {
3148         enum upiu_response_transaction resp;
3149         int err = 0;
3150
3151         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
3152         resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
3153
3154         switch (resp) {
3155         case UPIU_TRANSACTION_NOP_IN:
3156                 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
3157                         err = -EINVAL;
3158                         dev_err(hba->dev, "%s: unexpected response %x\n",
3159                                         __func__, resp);
3160                 }
3161                 break;
3162         case UPIU_TRANSACTION_QUERY_RSP: {
3163                 u8 response = lrbp->ucd_rsp_ptr->header.response;
3164
3165                 if (response == 0)
3166                         err = ufshcd_copy_query_response(hba, lrbp);
3167                 break;
3168         }
3169         case UPIU_TRANSACTION_REJECT_UPIU:
3170                 /* TODO: handle Reject UPIU Response */
3171                 err = -EPERM;
3172                 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
3173                                 __func__);
3174                 break;
3175         case UPIU_TRANSACTION_RESPONSE:
3176                 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) {
3177                         err = -EINVAL;
3178                         dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp);
3179                 }
3180                 break;
3181         default:
3182                 err = -EINVAL;
3183                 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
3184                                 __func__, resp);
3185                 break;
3186         }
3187
3188         return err;
3189 }
3190
3191 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
3192                 struct ufshcd_lrb *lrbp, int max_timeout)
3193 {
3194         unsigned long time_left = msecs_to_jiffies(max_timeout);
3195         unsigned long flags;
3196         bool pending;
3197         int err;
3198
3199 retry:
3200         time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
3201                                                 time_left);
3202
3203         if (likely(time_left)) {
3204                 /*
3205                  * The completion handler called complete() and the caller of
3206                  * this function still owns the @lrbp tag so the code below does
3207                  * not trigger any race conditions.
3208                  */
3209                 hba->dev_cmd.complete = NULL;
3210                 err = ufshcd_get_tr_ocs(lrbp, NULL);
3211                 if (!err)
3212                         err = ufshcd_dev_cmd_completion(hba, lrbp);
3213         } else {
3214                 err = -ETIMEDOUT;
3215                 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
3216                         __func__, lrbp->task_tag);
3217
3218                 /* MCQ mode */
3219                 if (is_mcq_enabled(hba)) {
3220                         /* successfully cleared the command, retry if needed */
3221                         if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0)
3222                                 err = -EAGAIN;
3223                         hba->dev_cmd.complete = NULL;
3224                         return err;
3225                 }
3226
3227                 /* SDB mode */
3228                 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) {
3229                         /* successfully cleared the command, retry if needed */
3230                         err = -EAGAIN;
3231                         /*
3232                          * Since clearing the command succeeded we also need to
3233                          * clear the task tag bit from the outstanding_reqs
3234                          * variable.
3235                          */
3236                         spin_lock_irqsave(&hba->outstanding_lock, flags);
3237                         pending = test_bit(lrbp->task_tag,
3238                                            &hba->outstanding_reqs);
3239                         if (pending) {
3240                                 hba->dev_cmd.complete = NULL;
3241                                 __clear_bit(lrbp->task_tag,
3242                                             &hba->outstanding_reqs);
3243                         }
3244                         spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3245
3246                         if (!pending) {
3247                                 /*
3248                                  * The completion handler ran while we tried to
3249                                  * clear the command.
3250                                  */
3251                                 time_left = 1;
3252                                 goto retry;
3253                         }
3254                 } else {
3255                         dev_err(hba->dev, "%s: failed to clear tag %d\n",
3256                                 __func__, lrbp->task_tag);
3257
3258                         spin_lock_irqsave(&hba->outstanding_lock, flags);
3259                         pending = test_bit(lrbp->task_tag,
3260                                            &hba->outstanding_reqs);
3261                         if (pending)
3262                                 hba->dev_cmd.complete = NULL;
3263                         spin_unlock_irqrestore(&hba->outstanding_lock, flags);
3264
3265                         if (!pending) {
3266                                 /*
3267                                  * The completion handler ran while we tried to
3268                                  * clear the command.
3269                                  */
3270                                 time_left = 1;
3271                                 goto retry;
3272                         }
3273                 }
3274         }
3275
3276         return err;
3277 }
3278
3279 /**
3280  * ufshcd_exec_dev_cmd - API for sending device management requests
3281  * @hba: UFS hba
3282  * @cmd_type: specifies the type (NOP, Query...)
3283  * @timeout: timeout in milliseconds
3284  *
3285  * Return: 0 upon success; < 0 upon failure.
3286  *
3287  * NOTE: Since there is only one available tag for device management commands,
3288  * it is expected you hold the hba->dev_cmd.lock mutex.
3289  */
3290 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
3291                 enum dev_cmd_type cmd_type, int timeout)
3292 {
3293         DECLARE_COMPLETION_ONSTACK(wait);
3294         const u32 tag = hba->reserved_slot;
3295         struct ufshcd_lrb *lrbp;
3296         int err;
3297
3298         /* Protects use of hba->reserved_slot. */
3299         lockdep_assert_held(&hba->dev_cmd.lock);
3300
3301         down_read(&hba->clk_scaling_lock);
3302
3303         lrbp = &hba->lrb[tag];
3304         lrbp->cmd = NULL;
3305         err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
3306         if (unlikely(err))
3307                 goto out;
3308
3309         hba->dev_cmd.complete = &wait;
3310
3311         ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
3312
3313         ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
3314         err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
3315         ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
3316                                     (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
3317
3318 out:
3319         up_read(&hba->clk_scaling_lock);
3320         return err;
3321 }
3322
3323 /**
3324  * ufshcd_init_query() - init the query response and request parameters
3325  * @hba: per-adapter instance
3326  * @request: address of the request pointer to be initialized
3327  * @response: address of the response pointer to be initialized
3328  * @opcode: operation to perform
3329  * @idn: flag idn to access
3330  * @index: LU number to access
3331  * @selector: query/flag/descriptor further identification
3332  */
3333 static inline void ufshcd_init_query(struct ufs_hba *hba,
3334                 struct ufs_query_req **request, struct ufs_query_res **response,
3335                 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3336 {
3337         *request = &hba->dev_cmd.query.request;
3338         *response = &hba->dev_cmd.query.response;
3339         memset(*request, 0, sizeof(struct ufs_query_req));
3340         memset(*response, 0, sizeof(struct ufs_query_res));
3341         (*request)->upiu_req.opcode = opcode;
3342         (*request)->upiu_req.idn = idn;
3343         (*request)->upiu_req.index = index;
3344         (*request)->upiu_req.selector = selector;
3345 }
3346
3347 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
3348         enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
3349 {
3350         int ret;
3351         int retries;
3352
3353         for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
3354                 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
3355                 if (ret)
3356                         dev_dbg(hba->dev,
3357                                 "%s: failed with error %d, retries %d\n",
3358                                 __func__, ret, retries);
3359                 else
3360                         break;
3361         }
3362
3363         if (ret)
3364                 dev_err(hba->dev,
3365                         "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n",
3366                         __func__, opcode, idn, ret, retries);
3367         return ret;
3368 }
3369
3370 /**
3371  * ufshcd_query_flag() - API function for sending flag query requests
3372  * @hba: per-adapter instance
3373  * @opcode: flag query to perform
3374  * @idn: flag idn to access
3375  * @index: flag index to access
3376  * @flag_res: the flag value after the query request completes
3377  *
3378  * Return: 0 for success, non-zero in case of failure.
3379  */
3380 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3381                         enum flag_idn idn, u8 index, bool *flag_res)
3382 {
3383         struct ufs_query_req *request = NULL;
3384         struct ufs_query_res *response = NULL;
3385         int err, selector = 0;
3386         int timeout = QUERY_REQ_TIMEOUT;
3387
3388         BUG_ON(!hba);
3389
3390         ufshcd_hold(hba);
3391         mutex_lock(&hba->dev_cmd.lock);
3392         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3393                         selector);
3394
3395         switch (opcode) {
3396         case UPIU_QUERY_OPCODE_SET_FLAG:
3397         case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3398         case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3399                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3400                 break;
3401         case UPIU_QUERY_OPCODE_READ_FLAG:
3402                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3403                 if (!flag_res) {
3404                         /* No dummy reads */
3405                         dev_err(hba->dev, "%s: Invalid argument for read request\n",
3406                                         __func__);
3407                         err = -EINVAL;
3408                         goto out_unlock;
3409                 }
3410                 break;
3411         default:
3412                 dev_err(hba->dev,
3413                         "%s: Expected query flag opcode but got = %d\n",
3414                         __func__, opcode);
3415                 err = -EINVAL;
3416                 goto out_unlock;
3417         }
3418
3419         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3420
3421         if (err) {
3422                 dev_err(hba->dev,
3423                         "%s: Sending flag query for idn %d failed, err = %d\n",
3424                         __func__, idn, err);
3425                 goto out_unlock;
3426         }
3427
3428         if (flag_res)
3429                 *flag_res = (be32_to_cpu(response->upiu_res.value) &
3430                                 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3431
3432 out_unlock:
3433         mutex_unlock(&hba->dev_cmd.lock);
3434         ufshcd_release(hba);
3435         return err;
3436 }
3437
3438 /**
3439  * ufshcd_query_attr - API function for sending attribute requests
3440  * @hba: per-adapter instance
3441  * @opcode: attribute opcode
3442  * @idn: attribute idn to access
3443  * @index: index field
3444  * @selector: selector field
3445  * @attr_val: the attribute value after the query request completes
3446  *
3447  * Return: 0 for success, non-zero in case of failure.
3448 */
3449 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3450                       enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3451 {
3452         struct ufs_query_req *request = NULL;
3453         struct ufs_query_res *response = NULL;
3454         int err;
3455
3456         BUG_ON(!hba);
3457
3458         if (!attr_val) {
3459                 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3460                                 __func__, opcode);
3461                 return -EINVAL;
3462         }
3463
3464         ufshcd_hold(hba);
3465
3466         mutex_lock(&hba->dev_cmd.lock);
3467         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3468                         selector);
3469
3470         switch (opcode) {
3471         case UPIU_QUERY_OPCODE_WRITE_ATTR:
3472                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3473                 request->upiu_req.value = cpu_to_be32(*attr_val);
3474                 break;
3475         case UPIU_QUERY_OPCODE_READ_ATTR:
3476                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3477                 break;
3478         default:
3479                 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3480                                 __func__, opcode);
3481                 err = -EINVAL;
3482                 goto out_unlock;
3483         }
3484
3485         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3486
3487         if (err) {
3488                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3489                                 __func__, opcode, idn, index, err);
3490                 goto out_unlock;
3491         }
3492
3493         *attr_val = be32_to_cpu(response->upiu_res.value);
3494
3495 out_unlock:
3496         mutex_unlock(&hba->dev_cmd.lock);
3497         ufshcd_release(hba);
3498         return err;
3499 }
3500
3501 /**
3502  * ufshcd_query_attr_retry() - API function for sending query
3503  * attribute with retries
3504  * @hba: per-adapter instance
3505  * @opcode: attribute opcode
3506  * @idn: attribute idn to access
3507  * @index: index field
3508  * @selector: selector field
3509  * @attr_val: the attribute value after the query request
3510  * completes
3511  *
3512  * Return: 0 for success, non-zero in case of failure.
3513 */
3514 int ufshcd_query_attr_retry(struct ufs_hba *hba,
3515         enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3516         u32 *attr_val)
3517 {
3518         int ret = 0;
3519         u32 retries;
3520
3521         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3522                 ret = ufshcd_query_attr(hba, opcode, idn, index,
3523                                                 selector, attr_val);
3524                 if (ret)
3525                         dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3526                                 __func__, ret, retries);
3527                 else
3528                         break;
3529         }
3530
3531         if (ret)
3532                 dev_err(hba->dev,
3533                         "%s: query attribute, idn %d, failed with error %d after %d retries\n",
3534                         __func__, idn, ret, QUERY_REQ_RETRIES);
3535         return ret;
3536 }
3537
3538 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3539                         enum query_opcode opcode, enum desc_idn idn, u8 index,
3540                         u8 selector, u8 *desc_buf, int *buf_len)
3541 {
3542         struct ufs_query_req *request = NULL;
3543         struct ufs_query_res *response = NULL;
3544         int err;
3545
3546         BUG_ON(!hba);
3547
3548         if (!desc_buf) {
3549                 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3550                                 __func__, opcode);
3551                 return -EINVAL;
3552         }
3553
3554         if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3555                 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3556                                 __func__, *buf_len);
3557                 return -EINVAL;
3558         }
3559
3560         ufshcd_hold(hba);
3561
3562         mutex_lock(&hba->dev_cmd.lock);
3563         ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3564                         selector);
3565         hba->dev_cmd.query.descriptor = desc_buf;
3566         request->upiu_req.length = cpu_to_be16(*buf_len);
3567
3568         switch (opcode) {
3569         case UPIU_QUERY_OPCODE_WRITE_DESC:
3570                 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3571                 break;
3572         case UPIU_QUERY_OPCODE_READ_DESC:
3573                 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3574                 break;
3575         default:
3576                 dev_err(hba->dev,
3577                                 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3578                                 __func__, opcode);
3579                 err = -EINVAL;
3580                 goto out_unlock;
3581         }
3582
3583         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3584
3585         if (err) {
3586                 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3587                                 __func__, opcode, idn, index, err);
3588                 goto out_unlock;
3589         }
3590
3591         *buf_len = be16_to_cpu(response->upiu_res.length);
3592
3593 out_unlock:
3594         hba->dev_cmd.query.descriptor = NULL;
3595         mutex_unlock(&hba->dev_cmd.lock);
3596         ufshcd_release(hba);
3597         return err;
3598 }
3599
3600 /**
3601  * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3602  * @hba: per-adapter instance
3603  * @opcode: attribute opcode
3604  * @idn: attribute idn to access
3605  * @index: index field
3606  * @selector: selector field
3607  * @desc_buf: the buffer that contains the descriptor
3608  * @buf_len: length parameter passed to the device
3609  *
3610  * The buf_len parameter will contain, on return, the length parameter
3611  * received on the response.
3612  *
3613  * Return: 0 for success, non-zero in case of failure.
3614  */
3615 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3616                                   enum query_opcode opcode,
3617                                   enum desc_idn idn, u8 index,
3618                                   u8 selector,
3619                                   u8 *desc_buf, int *buf_len)
3620 {
3621         int err;
3622         int retries;
3623
3624         for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3625                 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3626                                                 selector, desc_buf, buf_len);
3627                 if (!err || err == -EINVAL)
3628                         break;
3629         }
3630
3631         return err;
3632 }
3633
3634 /**
3635  * ufshcd_read_desc_param - read the specified descriptor parameter
3636  * @hba: Pointer to adapter instance
3637  * @desc_id: descriptor idn value
3638  * @desc_index: descriptor index
3639  * @param_offset: offset of the parameter to read
3640  * @param_read_buf: pointer to buffer where parameter would be read
3641  * @param_size: sizeof(param_read_buf)
3642  *
3643  * Return: 0 in case of success, non-zero otherwise.
3644  */
3645 int ufshcd_read_desc_param(struct ufs_hba *hba,
3646                            enum desc_idn desc_id,
3647                            int desc_index,
3648                            u8 param_offset,
3649                            u8 *param_read_buf,
3650                            u8 param_size)
3651 {
3652         int ret;
3653         u8 *desc_buf;
3654         int buff_len = QUERY_DESC_MAX_SIZE;
3655         bool is_kmalloc = true;
3656
3657         /* Safety check */
3658         if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3659                 return -EINVAL;
3660
3661         /* Check whether we need temp memory */
3662         if (param_offset != 0 || param_size < buff_len) {
3663                 desc_buf = kzalloc(buff_len, GFP_KERNEL);
3664                 if (!desc_buf)
3665                         return -ENOMEM;
3666         } else {
3667                 desc_buf = param_read_buf;
3668                 is_kmalloc = false;
3669         }
3670
3671         /* Request for full descriptor */
3672         ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3673                                             desc_id, desc_index, 0,
3674                                             desc_buf, &buff_len);
3675         if (ret) {
3676                 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3677                         __func__, desc_id, desc_index, param_offset, ret);
3678                 goto out;
3679         }
3680
3681         /* Update descriptor length */
3682         buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3683
3684         if (param_offset >= buff_len) {
3685                 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3686                         __func__, param_offset, desc_id, buff_len);
3687                 ret = -EINVAL;
3688                 goto out;
3689         }
3690
3691         /* Sanity check */
3692         if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3693                 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3694                         __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3695                 ret = -EINVAL;
3696                 goto out;
3697         }
3698
3699         if (is_kmalloc) {
3700                 /* Make sure we don't copy more data than available */
3701                 if (param_offset >= buff_len)
3702                         ret = -EINVAL;
3703                 else
3704                         memcpy(param_read_buf, &desc_buf[param_offset],
3705                                min_t(u32, param_size, buff_len - param_offset));
3706         }
3707 out:
3708         if (is_kmalloc)
3709                 kfree(desc_buf);
3710         return ret;
3711 }
3712
3713 /**
3714  * struct uc_string_id - unicode string
3715  *
3716  * @len: size of this descriptor inclusive
3717  * @type: descriptor type
3718  * @uc: unicode string character
3719  */
3720 struct uc_string_id {
3721         u8 len;
3722         u8 type;
3723         wchar_t uc[];
3724 } __packed;
3725
3726 /* replace non-printable or non-ASCII characters with spaces */
3727 static inline char ufshcd_remove_non_printable(u8 ch)
3728 {
3729         return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3730 }
3731
3732 /**
3733  * ufshcd_read_string_desc - read string descriptor
3734  * @hba: pointer to adapter instance
3735  * @desc_index: descriptor index
3736  * @buf: pointer to buffer where descriptor would be read,
3737  *       the caller should free the memory.
3738  * @ascii: if true convert from unicode to ascii characters
3739  *         null terminated string.
3740  *
3741  * Return:
3742  * *      string size on success.
3743  * *      -ENOMEM: on allocation failure
3744  * *      -EINVAL: on a wrong parameter
3745  */
3746 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3747                             u8 **buf, bool ascii)
3748 {
3749         struct uc_string_id *uc_str;
3750         u8 *str;
3751         int ret;
3752
3753         if (!buf)
3754                 return -EINVAL;
3755
3756         uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3757         if (!uc_str)
3758                 return -ENOMEM;
3759
3760         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3761                                      (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3762         if (ret < 0) {
3763                 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3764                         QUERY_REQ_RETRIES, ret);
3765                 str = NULL;
3766                 goto out;
3767         }
3768
3769         if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3770                 dev_dbg(hba->dev, "String Desc is of zero length\n");
3771                 str = NULL;
3772                 ret = 0;
3773                 goto out;
3774         }
3775
3776         if (ascii) {
3777                 ssize_t ascii_len;
3778                 int i;
3779                 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3780                 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3781                 str = kzalloc(ascii_len, GFP_KERNEL);
3782                 if (!str) {
3783                         ret = -ENOMEM;
3784                         goto out;
3785                 }
3786
3787                 /*
3788                  * the descriptor contains string in UTF16 format
3789                  * we need to convert to utf-8 so it can be displayed
3790                  */
3791                 ret = utf16s_to_utf8s(uc_str->uc,
3792                                       uc_str->len - QUERY_DESC_HDR_SIZE,
3793                                       UTF16_BIG_ENDIAN, str, ascii_len - 1);
3794
3795                 /* replace non-printable or non-ASCII characters with spaces */
3796                 for (i = 0; i < ret; i++)
3797                         str[i] = ufshcd_remove_non_printable(str[i]);
3798
3799                 str[ret++] = '\0';
3800
3801         } else {
3802                 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3803                 if (!str) {
3804                         ret = -ENOMEM;
3805                         goto out;
3806                 }
3807                 ret = uc_str->len;
3808         }
3809 out:
3810         *buf = str;
3811         kfree(uc_str);
3812         return ret;
3813 }
3814
3815 /**
3816  * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3817  * @hba: Pointer to adapter instance
3818  * @lun: lun id
3819  * @param_offset: offset of the parameter to read
3820  * @param_read_buf: pointer to buffer where parameter would be read
3821  * @param_size: sizeof(param_read_buf)
3822  *
3823  * Return: 0 in case of success, non-zero otherwise.
3824  */
3825 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3826                                               int lun,
3827                                               enum unit_desc_param param_offset,
3828                                               u8 *param_read_buf,
3829                                               u32 param_size)
3830 {
3831         /*
3832          * Unit descriptors are only available for general purpose LUs (LUN id
3833          * from 0 to 7) and RPMB Well known LU.
3834          */
3835         if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun))
3836                 return -EOPNOTSUPP;
3837
3838         return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3839                                       param_offset, param_read_buf, param_size);
3840 }
3841
3842 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3843 {
3844         int err = 0;
3845         u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3846
3847         if (hba->dev_info.wspecversion >= 0x300) {
3848                 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3849                                 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3850                                 &gating_wait);
3851                 if (err)
3852                         dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3853                                          err, gating_wait);
3854
3855                 if (gating_wait == 0) {
3856                         gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3857                         dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3858                                          gating_wait);
3859                 }
3860
3861                 hba->dev_info.clk_gating_wait_us = gating_wait;
3862         }
3863
3864         return err;
3865 }
3866
3867 /**
3868  * ufshcd_memory_alloc - allocate memory for host memory space data structures
3869  * @hba: per adapter instance
3870  *
3871  * 1. Allocate DMA memory for Command Descriptor array
3872  *      Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3873  * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3874  * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3875  *      (UTMRDL)
3876  * 4. Allocate memory for local reference block(lrb).
3877  *
3878  * Return: 0 for success, non-zero in case of failure.
3879  */
3880 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3881 {
3882         size_t utmrdl_size, utrdl_size, ucdl_size;
3883
3884         /* Allocate memory for UTP command descriptors */
3885         ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs;
3886         hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3887                                                   ucdl_size,
3888                                                   &hba->ucdl_dma_addr,
3889                                                   GFP_KERNEL);
3890
3891         /*
3892          * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3893          */
3894         if (!hba->ucdl_base_addr ||
3895             WARN_ON(hba->ucdl_dma_addr & (128 - 1))) {
3896                 dev_err(hba->dev,
3897                         "Command Descriptor Memory allocation failed\n");
3898                 goto out;
3899         }
3900
3901         /*
3902          * Allocate memory for UTP Transfer descriptors
3903          * UFSHCI requires 1KB alignment of UTRD
3904          */
3905         utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3906         hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3907                                                    utrdl_size,
3908                                                    &hba->utrdl_dma_addr,
3909                                                    GFP_KERNEL);
3910         if (!hba->utrdl_base_addr ||
3911             WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) {
3912                 dev_err(hba->dev,
3913                         "Transfer Descriptor Memory allocation failed\n");
3914                 goto out;
3915         }
3916
3917         /*
3918          * Skip utmrdl allocation; it may have been
3919          * allocated during first pass and not released during
3920          * MCQ memory allocation.
3921          * See ufshcd_release_sdb_queue() and ufshcd_config_mcq()
3922          */
3923         if (hba->utmrdl_base_addr)
3924                 goto skip_utmrdl;
3925         /*
3926          * Allocate memory for UTP Task Management descriptors
3927          * UFSHCI requires 1KB alignment of UTMRD
3928          */
3929         utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3930         hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3931                                                     utmrdl_size,
3932                                                     &hba->utmrdl_dma_addr,
3933                                                     GFP_KERNEL);
3934         if (!hba->utmrdl_base_addr ||
3935             WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) {
3936                 dev_err(hba->dev,
3937                 "Task Management Descriptor Memory allocation failed\n");
3938                 goto out;
3939         }
3940
3941 skip_utmrdl:
3942         /* Allocate memory for local reference block */
3943         hba->lrb = devm_kcalloc(hba->dev,
3944                                 hba->nutrs, sizeof(struct ufshcd_lrb),
3945                                 GFP_KERNEL);
3946         if (!hba->lrb) {
3947                 dev_err(hba->dev, "LRB Memory allocation failed\n");
3948                 goto out;
3949         }
3950         return 0;
3951 out:
3952         return -ENOMEM;
3953 }
3954
3955 /**
3956  * ufshcd_host_memory_configure - configure local reference block with
3957  *                              memory offsets
3958  * @hba: per adapter instance
3959  *
3960  * Configure Host memory space
3961  * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3962  * address.
3963  * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3964  * and PRDT offset.
3965  * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3966  * into local reference block.
3967  */
3968 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3969 {
3970         struct utp_transfer_req_desc *utrdlp;
3971         dma_addr_t cmd_desc_dma_addr;
3972         dma_addr_t cmd_desc_element_addr;
3973         u16 response_offset;
3974         u16 prdt_offset;
3975         int cmd_desc_size;
3976         int i;
3977
3978         utrdlp = hba->utrdl_base_addr;
3979
3980         response_offset =
3981                 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3982         prdt_offset =
3983                 offsetof(struct utp_transfer_cmd_desc, prd_table);
3984
3985         cmd_desc_size = ufshcd_get_ucd_size(hba);
3986         cmd_desc_dma_addr = hba->ucdl_dma_addr;
3987
3988         for (i = 0; i < hba->nutrs; i++) {
3989                 /* Configure UTRD with command descriptor base address */
3990                 cmd_desc_element_addr =
3991                                 (cmd_desc_dma_addr + (cmd_desc_size * i));
3992                 utrdlp[i].command_desc_base_addr =
3993                                 cpu_to_le64(cmd_desc_element_addr);
3994
3995                 /* Response upiu and prdt offset should be in double words */
3996                 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3997                         utrdlp[i].response_upiu_offset =
3998                                 cpu_to_le16(response_offset);
3999                         utrdlp[i].prd_table_offset =
4000                                 cpu_to_le16(prdt_offset);
4001                         utrdlp[i].response_upiu_length =
4002                                 cpu_to_le16(ALIGNED_UPIU_SIZE);
4003                 } else {
4004                         utrdlp[i].response_upiu_offset =
4005                                 cpu_to_le16(response_offset >> 2);
4006                         utrdlp[i].prd_table_offset =
4007                                 cpu_to_le16(prdt_offset >> 2);
4008                         utrdlp[i].response_upiu_length =
4009                                 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
4010                 }
4011
4012                 ufshcd_init_lrb(hba, &hba->lrb[i], i);
4013         }
4014 }
4015
4016 /**
4017  * ufshcd_dme_link_startup - Notify Unipro to perform link startup
4018  * @hba: per adapter instance
4019  *
4020  * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
4021  * in order to initialize the Unipro link startup procedure.
4022  * Once the Unipro links are up, the device connected to the controller
4023  * is detected.
4024  *
4025  * Return: 0 on success, non-zero value on failure.
4026  */
4027 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
4028 {
4029         struct uic_command uic_cmd = {0};
4030         int ret;
4031
4032         uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
4033
4034         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4035         if (ret)
4036                 dev_dbg(hba->dev,
4037                         "dme-link-startup: error code %d\n", ret);
4038         return ret;
4039 }
4040 /**
4041  * ufshcd_dme_reset - UIC command for DME_RESET
4042  * @hba: per adapter instance
4043  *
4044  * DME_RESET command is issued in order to reset UniPro stack.
4045  * This function now deals with cold reset.
4046  *
4047  * Return: 0 on success, non-zero value on failure.
4048  */
4049 static int ufshcd_dme_reset(struct ufs_hba *hba)
4050 {
4051         struct uic_command uic_cmd = {0};
4052         int ret;
4053
4054         uic_cmd.command = UIC_CMD_DME_RESET;
4055
4056         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4057         if (ret)
4058                 dev_err(hba->dev,
4059                         "dme-reset: error code %d\n", ret);
4060
4061         return ret;
4062 }
4063
4064 int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
4065                                int agreed_gear,
4066                                int adapt_val)
4067 {
4068         int ret;
4069
4070         if (agreed_gear < UFS_HS_G4)
4071                 adapt_val = PA_NO_ADAPT;
4072
4073         ret = ufshcd_dme_set(hba,
4074                              UIC_ARG_MIB(PA_TXHSADAPTTYPE),
4075                              adapt_val);
4076         return ret;
4077 }
4078 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
4079
4080 /**
4081  * ufshcd_dme_enable - UIC command for DME_ENABLE
4082  * @hba: per adapter instance
4083  *
4084  * DME_ENABLE command is issued in order to enable UniPro stack.
4085  *
4086  * Return: 0 on success, non-zero value on failure.
4087  */
4088 static int ufshcd_dme_enable(struct ufs_hba *hba)
4089 {
4090         struct uic_command uic_cmd = {0};
4091         int ret;
4092
4093         uic_cmd.command = UIC_CMD_DME_ENABLE;
4094
4095         ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4096         if (ret)
4097                 dev_err(hba->dev,
4098                         "dme-enable: error code %d\n", ret);
4099
4100         return ret;
4101 }
4102
4103 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
4104 {
4105         #define MIN_DELAY_BEFORE_DME_CMDS_US    1000
4106         unsigned long min_sleep_time_us;
4107
4108         if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
4109                 return;
4110
4111         /*
4112          * last_dme_cmd_tstamp will be 0 only for 1st call to
4113          * this function
4114          */
4115         if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
4116                 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
4117         } else {
4118                 unsigned long delta =
4119                         (unsigned long) ktime_to_us(
4120                                 ktime_sub(ktime_get(),
4121                                 hba->last_dme_cmd_tstamp));
4122
4123                 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
4124                         min_sleep_time_us =
4125                                 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
4126                 else
4127                         return; /* no more delay required */
4128         }
4129
4130         /* allow sleep for extra 50us if needed */
4131         usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
4132 }
4133
4134 /**
4135  * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
4136  * @hba: per adapter instance
4137  * @attr_sel: uic command argument1
4138  * @attr_set: attribute set type as uic command argument2
4139  * @mib_val: setting value as uic command argument3
4140  * @peer: indicate whether peer or local
4141  *
4142  * Return: 0 on success, non-zero value on failure.
4143  */
4144 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
4145                         u8 attr_set, u32 mib_val, u8 peer)
4146 {
4147         struct uic_command uic_cmd = {0};
4148         static const char *const action[] = {
4149                 "dme-set",
4150                 "dme-peer-set"
4151         };
4152         const char *set = action[!!peer];
4153         int ret;
4154         int retries = UFS_UIC_COMMAND_RETRIES;
4155
4156         uic_cmd.command = peer ?
4157                 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
4158         uic_cmd.argument1 = attr_sel;
4159         uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
4160         uic_cmd.argument3 = mib_val;
4161
4162         do {
4163                 /* for peer attributes we retry upon failure */
4164                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4165                 if (ret)
4166                         dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
4167                                 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
4168         } while (ret && peer && --retries);
4169
4170         if (ret)
4171                 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
4172                         set, UIC_GET_ATTR_ID(attr_sel), mib_val,
4173                         UFS_UIC_COMMAND_RETRIES - retries);
4174
4175         return ret;
4176 }
4177 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
4178
4179 /**
4180  * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
4181  * @hba: per adapter instance
4182  * @attr_sel: uic command argument1
4183  * @mib_val: the value of the attribute as returned by the UIC command
4184  * @peer: indicate whether peer or local
4185  *
4186  * Return: 0 on success, non-zero value on failure.
4187  */
4188 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
4189                         u32 *mib_val, u8 peer)
4190 {
4191         struct uic_command uic_cmd = {0};
4192         static const char *const action[] = {
4193                 "dme-get",
4194                 "dme-peer-get"
4195         };
4196         const char *get = action[!!peer];
4197         int ret;
4198         int retries = UFS_UIC_COMMAND_RETRIES;
4199         struct ufs_pa_layer_attr orig_pwr_info;
4200         struct ufs_pa_layer_attr temp_pwr_info;
4201         bool pwr_mode_change = false;
4202
4203         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
4204                 orig_pwr_info = hba->pwr_info;
4205                 temp_pwr_info = orig_pwr_info;
4206
4207                 if (orig_pwr_info.pwr_tx == FAST_MODE ||
4208                     orig_pwr_info.pwr_rx == FAST_MODE) {
4209                         temp_pwr_info.pwr_tx = FASTAUTO_MODE;
4210                         temp_pwr_info.pwr_rx = FASTAUTO_MODE;
4211                         pwr_mode_change = true;
4212                 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
4213                     orig_pwr_info.pwr_rx == SLOW_MODE) {
4214                         temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
4215                         temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
4216                         pwr_mode_change = true;
4217                 }
4218                 if (pwr_mode_change) {
4219                         ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
4220                         if (ret)
4221                                 goto out;
4222                 }
4223         }
4224
4225         uic_cmd.command = peer ?
4226                 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
4227         uic_cmd.argument1 = attr_sel;
4228
4229         do {
4230                 /* for peer attributes we retry upon failure */
4231                 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4232                 if (ret)
4233                         dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
4234                                 get, UIC_GET_ATTR_ID(attr_sel), ret);
4235         } while (ret && peer && --retries);
4236
4237         if (ret)
4238                 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
4239                         get, UIC_GET_ATTR_ID(attr_sel),
4240                         UFS_UIC_COMMAND_RETRIES - retries);
4241
4242         if (mib_val && !ret)
4243                 *mib_val = uic_cmd.argument3;
4244
4245         if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
4246             && pwr_mode_change)
4247                 ufshcd_change_power_mode(hba, &orig_pwr_info);
4248 out:
4249         return ret;
4250 }
4251 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
4252
4253 /**
4254  * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
4255  * state) and waits for it to take effect.
4256  *
4257  * @hba: per adapter instance
4258  * @cmd: UIC command to execute
4259  *
4260  * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
4261  * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
4262  * and device UniPro link and hence it's final completion would be indicated by
4263  * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
4264  * addition to normal UIC command completion Status (UCCS). This function only
4265  * returns after the relevant status bits indicate the completion.
4266  *
4267  * Return: 0 on success, non-zero value on failure.
4268  */
4269 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
4270 {
4271         DECLARE_COMPLETION_ONSTACK(uic_async_done);
4272         unsigned long flags;
4273         u8 status;
4274         int ret;
4275         bool reenable_intr = false;
4276
4277         mutex_lock(&hba->uic_cmd_mutex);
4278         ufshcd_add_delay_before_dme_cmd(hba);
4279
4280         spin_lock_irqsave(hba->host->host_lock, flags);
4281         if (ufshcd_is_link_broken(hba)) {
4282                 ret = -ENOLINK;
4283                 goto out_unlock;
4284         }
4285         hba->uic_async_done = &uic_async_done;
4286         if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
4287                 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4288                 /*
4289                  * Make sure UIC command completion interrupt is disabled before
4290                  * issuing UIC command.
4291                  */
4292                 wmb();
4293                 reenable_intr = true;
4294         }
4295         spin_unlock_irqrestore(hba->host->host_lock, flags);
4296         ret = __ufshcd_send_uic_cmd(hba, cmd, false);
4297         if (ret) {
4298                 dev_err(hba->dev,
4299                         "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4300                         cmd->command, cmd->argument3, ret);
4301                 goto out;
4302         }
4303
4304         if (!wait_for_completion_timeout(hba->uic_async_done,
4305                                          msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4306                 dev_err(hba->dev,
4307                         "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4308                         cmd->command, cmd->argument3);
4309
4310                 if (!cmd->cmd_active) {
4311                         dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4312                                 __func__);
4313                         goto check_upmcrs;
4314                 }
4315
4316                 ret = -ETIMEDOUT;
4317                 goto out;
4318         }
4319
4320 check_upmcrs:
4321         status = ufshcd_get_upmcrs(hba);
4322         if (status != PWR_LOCAL) {
4323                 dev_err(hba->dev,
4324                         "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
4325                         cmd->command, status);
4326                 ret = (status != PWR_OK) ? status : -1;
4327         }
4328 out:
4329         if (ret) {
4330                 ufshcd_print_host_state(hba);
4331                 ufshcd_print_pwr_info(hba);
4332                 ufshcd_print_evt_hist(hba);
4333         }
4334
4335         spin_lock_irqsave(hba->host->host_lock, flags);
4336         hba->active_uic_cmd = NULL;
4337         hba->uic_async_done = NULL;
4338         if (reenable_intr)
4339                 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4340         if (ret) {
4341                 ufshcd_set_link_broken(hba);
4342                 ufshcd_schedule_eh_work(hba);
4343         }
4344 out_unlock:
4345         spin_unlock_irqrestore(hba->host->host_lock, flags);
4346         mutex_unlock(&hba->uic_cmd_mutex);
4347
4348         return ret;
4349 }
4350
4351 /**
4352  * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4353  *                              using DME_SET primitives.
4354  * @hba: per adapter instance
4355  * @mode: powr mode value
4356  *
4357  * Return: 0 on success, non-zero value on failure.
4358  */
4359 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4360 {
4361         struct uic_command uic_cmd = {0};
4362         int ret;
4363
4364         if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4365                 ret = ufshcd_dme_set(hba,
4366                                 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4367                 if (ret) {
4368                         dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4369                                                 __func__, ret);
4370                         goto out;
4371                 }
4372         }
4373
4374         uic_cmd.command = UIC_CMD_DME_SET;
4375         uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4376         uic_cmd.argument3 = mode;
4377         ufshcd_hold(hba);
4378         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4379         ufshcd_release(hba);
4380
4381 out:
4382         return ret;
4383 }
4384 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode);
4385
4386 int ufshcd_link_recovery(struct ufs_hba *hba)
4387 {
4388         int ret;
4389         unsigned long flags;
4390
4391         spin_lock_irqsave(hba->host->host_lock, flags);
4392         hba->ufshcd_state = UFSHCD_STATE_RESET;
4393         ufshcd_set_eh_in_progress(hba);
4394         spin_unlock_irqrestore(hba->host->host_lock, flags);
4395
4396         /* Reset the attached device */
4397         ufshcd_device_reset(hba);
4398
4399         ret = ufshcd_host_reset_and_restore(hba);
4400
4401         spin_lock_irqsave(hba->host->host_lock, flags);
4402         if (ret)
4403                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4404         ufshcd_clear_eh_in_progress(hba);
4405         spin_unlock_irqrestore(hba->host->host_lock, flags);
4406
4407         if (ret)
4408                 dev_err(hba->dev, "%s: link recovery failed, err %d",
4409                         __func__, ret);
4410
4411         return ret;
4412 }
4413 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4414
4415 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4416 {
4417         int ret;
4418         struct uic_command uic_cmd = {0};
4419         ktime_t start = ktime_get();
4420
4421         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4422
4423         uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
4424         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4425         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4426                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4427
4428         if (ret)
4429                 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4430                         __func__, ret);
4431         else
4432                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4433                                                                 POST_CHANGE);
4434
4435         return ret;
4436 }
4437 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
4438
4439 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4440 {
4441         struct uic_command uic_cmd = {0};
4442         int ret;
4443         ktime_t start = ktime_get();
4444
4445         ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4446
4447         uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4448         ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4449         trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4450                              ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4451
4452         if (ret) {
4453                 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4454                         __func__, ret);
4455         } else {
4456                 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4457                                                                 POST_CHANGE);
4458                 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock();
4459                 hba->ufs_stats.hibern8_exit_cnt++;
4460         }
4461
4462         return ret;
4463 }
4464 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4465
4466 static void ufshcd_configure_auto_hibern8(struct ufs_hba *hba)
4467 {
4468         if (!ufshcd_is_auto_hibern8_supported(hba))
4469                 return;
4470
4471         ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4472 }
4473
4474 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4475 {
4476         const u32 cur_ahit = READ_ONCE(hba->ahit);
4477
4478         if (!ufshcd_is_auto_hibern8_supported(hba) || cur_ahit == ahit)
4479                 return;
4480
4481         WRITE_ONCE(hba->ahit, ahit);
4482         if (!pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) {
4483                 ufshcd_rpm_get_sync(hba);
4484                 ufshcd_hold(hba);
4485                 ufshcd_configure_auto_hibern8(hba);
4486                 ufshcd_release(hba);
4487                 ufshcd_rpm_put_sync(hba);
4488         }
4489 }
4490 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4491
4492  /**
4493  * ufshcd_init_pwr_info - setting the POR (power on reset)
4494  * values in hba power info
4495  * @hba: per-adapter instance
4496  */
4497 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4498 {
4499         hba->pwr_info.gear_rx = UFS_PWM_G1;
4500         hba->pwr_info.gear_tx = UFS_PWM_G1;
4501         hba->pwr_info.lane_rx = UFS_LANE_1;
4502         hba->pwr_info.lane_tx = UFS_LANE_1;
4503         hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4504         hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4505         hba->pwr_info.hs_rate = 0;
4506 }
4507
4508 /**
4509  * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4510  * @hba: per-adapter instance
4511  *
4512  * Return: 0 upon success; < 0 upon failure.
4513  */
4514 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4515 {
4516         struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4517
4518         if (hba->max_pwr_info.is_valid)
4519                 return 0;
4520
4521         if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) {
4522                 pwr_info->pwr_tx = FASTAUTO_MODE;
4523                 pwr_info->pwr_rx = FASTAUTO_MODE;
4524         } else {
4525                 pwr_info->pwr_tx = FAST_MODE;
4526                 pwr_info->pwr_rx = FAST_MODE;
4527         }
4528         pwr_info->hs_rate = PA_HS_MODE_B;
4529
4530         /* Get the connected lane count */
4531         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4532                         &pwr_info->lane_rx);
4533         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4534                         &pwr_info->lane_tx);
4535
4536         if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4537                 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4538                                 __func__,
4539                                 pwr_info->lane_rx,
4540                                 pwr_info->lane_tx);
4541                 return -EINVAL;
4542         }
4543
4544         /*
4545          * First, get the maximum gears of HS speed.
4546          * If a zero value, it means there is no HSGEAR capability.
4547          * Then, get the maximum gears of PWM speed.
4548          */
4549         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4550         if (!pwr_info->gear_rx) {
4551                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4552                                 &pwr_info->gear_rx);
4553                 if (!pwr_info->gear_rx) {
4554                         dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4555                                 __func__, pwr_info->gear_rx);
4556                         return -EINVAL;
4557                 }
4558                 pwr_info->pwr_rx = SLOW_MODE;
4559         }
4560
4561         ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4562                         &pwr_info->gear_tx);
4563         if (!pwr_info->gear_tx) {
4564                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4565                                 &pwr_info->gear_tx);
4566                 if (!pwr_info->gear_tx) {
4567                         dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4568                                 __func__, pwr_info->gear_tx);
4569                         return -EINVAL;
4570                 }
4571                 pwr_info->pwr_tx = SLOW_MODE;
4572         }
4573
4574         hba->max_pwr_info.is_valid = true;
4575         return 0;
4576 }
4577
4578 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4579                              struct ufs_pa_layer_attr *pwr_mode)
4580 {
4581         int ret;
4582
4583         /* if already configured to the requested pwr_mode */
4584         if (!hba->force_pmc &&
4585             pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4586             pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4587             pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4588             pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4589             pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4590             pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4591             pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4592                 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4593                 return 0;
4594         }
4595
4596         /*
4597          * Configure attributes for power mode change with below.
4598          * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4599          * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4600          * - PA_HSSERIES
4601          */
4602         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4603         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4604                         pwr_mode->lane_rx);
4605         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4606                         pwr_mode->pwr_rx == FAST_MODE)
4607                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
4608         else
4609                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false);
4610
4611         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4612         ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4613                         pwr_mode->lane_tx);
4614         if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4615                         pwr_mode->pwr_tx == FAST_MODE)
4616                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
4617         else
4618                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false);
4619
4620         if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4621             pwr_mode->pwr_tx == FASTAUTO_MODE ||
4622             pwr_mode->pwr_rx == FAST_MODE ||
4623             pwr_mode->pwr_tx == FAST_MODE)
4624                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4625                                                 pwr_mode->hs_rate);
4626
4627         if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4628                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4629                                 DL_FC0ProtectionTimeOutVal_Default);
4630                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4631                                 DL_TC0ReplayTimeOutVal_Default);
4632                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4633                                 DL_AFC0ReqTimeOutVal_Default);
4634                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4635                                 DL_FC1ProtectionTimeOutVal_Default);
4636                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4637                                 DL_TC1ReplayTimeOutVal_Default);
4638                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4639                                 DL_AFC1ReqTimeOutVal_Default);
4640
4641                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4642                                 DL_FC0ProtectionTimeOutVal_Default);
4643                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4644                                 DL_TC0ReplayTimeOutVal_Default);
4645                 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4646                                 DL_AFC0ReqTimeOutVal_Default);
4647         }
4648
4649         ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4650                         | pwr_mode->pwr_tx);
4651
4652         if (ret) {
4653                 dev_err(hba->dev,
4654                         "%s: power mode change failed %d\n", __func__, ret);
4655         } else {
4656                 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4657                                                                 pwr_mode);
4658
4659                 memcpy(&hba->pwr_info, pwr_mode,
4660                         sizeof(struct ufs_pa_layer_attr));
4661         }
4662
4663         return ret;
4664 }
4665
4666 /**
4667  * ufshcd_config_pwr_mode - configure a new power mode
4668  * @hba: per-adapter instance
4669  * @desired_pwr_mode: desired power configuration
4670  *
4671  * Return: 0 upon success; < 0 upon failure.
4672  */
4673 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4674                 struct ufs_pa_layer_attr *desired_pwr_mode)
4675 {
4676         struct ufs_pa_layer_attr final_params = { 0 };
4677         int ret;
4678
4679         ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4680                                         desired_pwr_mode, &final_params);
4681
4682         if (ret)
4683                 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4684
4685         ret = ufshcd_change_power_mode(hba, &final_params);
4686
4687         return ret;
4688 }
4689 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4690
4691 /**
4692  * ufshcd_complete_dev_init() - checks device readiness
4693  * @hba: per-adapter instance
4694  *
4695  * Set fDeviceInit flag and poll until device toggles it.
4696  *
4697  * Return: 0 upon success; < 0 upon failure.
4698  */
4699 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4700 {
4701         int err;
4702         bool flag_res = true;
4703         ktime_t timeout;
4704
4705         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4706                 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4707         if (err) {
4708                 dev_err(hba->dev,
4709                         "%s: setting fDeviceInit flag failed with error %d\n",
4710                         __func__, err);
4711                 goto out;
4712         }
4713
4714         /* Poll fDeviceInit flag to be cleared */
4715         timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4716         do {
4717                 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4718                                         QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4719                 if (!flag_res)
4720                         break;
4721                 usleep_range(500, 1000);
4722         } while (ktime_before(ktime_get(), timeout));
4723
4724         if (err) {
4725                 dev_err(hba->dev,
4726                                 "%s: reading fDeviceInit flag failed with error %d\n",
4727                                 __func__, err);
4728         } else if (flag_res) {
4729                 dev_err(hba->dev,
4730                                 "%s: fDeviceInit was not cleared by the device\n",
4731                                 __func__);
4732                 err = -EBUSY;
4733         }
4734 out:
4735         return err;
4736 }
4737
4738 /**
4739  * ufshcd_make_hba_operational - Make UFS controller operational
4740  * @hba: per adapter instance
4741  *
4742  * To bring UFS host controller to operational state,
4743  * 1. Enable required interrupts
4744  * 2. Configure interrupt aggregation
4745  * 3. Program UTRL and UTMRL base address
4746  * 4. Configure run-stop-registers
4747  *
4748  * Return: 0 on success, non-zero value on failure.
4749  */
4750 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4751 {
4752         int err = 0;
4753         u32 reg;
4754
4755         /* Enable required interrupts */
4756         ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4757
4758         /* Configure interrupt aggregation */
4759         if (ufshcd_is_intr_aggr_allowed(hba))
4760                 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4761         else
4762                 ufshcd_disable_intr_aggr(hba);
4763
4764         /* Configure UTRL and UTMRL base address registers */
4765         ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4766                         REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4767         ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4768                         REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4769         ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4770                         REG_UTP_TASK_REQ_LIST_BASE_L);
4771         ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4772                         REG_UTP_TASK_REQ_LIST_BASE_H);
4773
4774         /*
4775          * Make sure base address and interrupt setup are updated before
4776          * enabling the run/stop registers below.
4777          */
4778         wmb();
4779
4780         /*
4781          * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4782          */
4783         reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4784         if (!(ufshcd_get_lists_status(reg))) {
4785                 ufshcd_enable_run_stop_reg(hba);
4786         } else {
4787                 dev_err(hba->dev,
4788                         "Host controller not ready to process requests");
4789                 err = -EIO;
4790         }
4791
4792         return err;
4793 }
4794 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4795
4796 /**
4797  * ufshcd_hba_stop - Send controller to reset state
4798  * @hba: per adapter instance
4799  */
4800 void ufshcd_hba_stop(struct ufs_hba *hba)
4801 {
4802         unsigned long flags;
4803         int err;
4804
4805         /*
4806          * Obtain the host lock to prevent that the controller is disabled
4807          * while the UFS interrupt handler is active on another CPU.
4808          */
4809         spin_lock_irqsave(hba->host->host_lock, flags);
4810         ufshcd_writel(hba, CONTROLLER_DISABLE,  REG_CONTROLLER_ENABLE);
4811         spin_unlock_irqrestore(hba->host->host_lock, flags);
4812
4813         err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4814                                         CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4815                                         10, 1);
4816         if (err)
4817                 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4818 }
4819 EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4820
4821 /**
4822  * ufshcd_hba_execute_hce - initialize the controller
4823  * @hba: per adapter instance
4824  *
4825  * The controller resets itself and controller firmware initialization
4826  * sequence kicks off. When controller is ready it will set
4827  * the Host Controller Enable bit to 1.
4828  *
4829  * Return: 0 on success, non-zero value on failure.
4830  */
4831 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4832 {
4833         int retry_outer = 3;
4834         int retry_inner;
4835
4836 start:
4837         if (ufshcd_is_hba_active(hba))
4838                 /* change controller state to "reset state" */
4839                 ufshcd_hba_stop(hba);
4840
4841         /* UniPro link is disabled at this point */
4842         ufshcd_set_link_off(hba);
4843
4844         ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4845
4846         /* start controller initialization sequence */
4847         ufshcd_hba_start(hba);
4848
4849         /*
4850          * To initialize a UFS host controller HCE bit must be set to 1.
4851          * During initialization the HCE bit value changes from 1->0->1.
4852          * When the host controller completes initialization sequence
4853          * it sets the value of HCE bit to 1. The same HCE bit is read back
4854          * to check if the controller has completed initialization sequence.
4855          * So without this delay the value HCE = 1, set in the previous
4856          * instruction might be read back.
4857          * This delay can be changed based on the controller.
4858          */
4859         ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4860
4861         /* wait for the host controller to complete initialization */
4862         retry_inner = 50;
4863         while (!ufshcd_is_hba_active(hba)) {
4864                 if (retry_inner) {
4865                         retry_inner--;
4866                 } else {
4867                         dev_err(hba->dev,
4868                                 "Controller enable failed\n");
4869                         if (retry_outer) {
4870                                 retry_outer--;
4871                                 goto start;
4872                         }
4873                         return -EIO;
4874                 }
4875                 usleep_range(1000, 1100);
4876         }
4877
4878         /* enable UIC related interrupts */
4879         ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4880
4881         ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4882
4883         return 0;
4884 }
4885
4886 int ufshcd_hba_enable(struct ufs_hba *hba)
4887 {
4888         int ret;
4889
4890         if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4891                 ufshcd_set_link_off(hba);
4892                 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4893
4894                 /* enable UIC related interrupts */
4895                 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4896                 ret = ufshcd_dme_reset(hba);
4897                 if (ret) {
4898                         dev_err(hba->dev, "DME_RESET failed\n");
4899                         return ret;
4900                 }
4901
4902                 ret = ufshcd_dme_enable(hba);
4903                 if (ret) {
4904                         dev_err(hba->dev, "Enabling DME failed\n");
4905                         return ret;
4906                 }
4907
4908                 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4909         } else {
4910                 ret = ufshcd_hba_execute_hce(hba);
4911         }
4912
4913         return ret;
4914 }
4915 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4916
4917 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4918 {
4919         int tx_lanes = 0, i, err = 0;
4920
4921         if (!peer)
4922                 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4923                                &tx_lanes);
4924         else
4925                 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4926                                     &tx_lanes);
4927         for (i = 0; i < tx_lanes; i++) {
4928                 if (!peer)
4929                         err = ufshcd_dme_set(hba,
4930                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4931                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4932                                         0);
4933                 else
4934                         err = ufshcd_dme_peer_set(hba,
4935                                 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4936                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4937                                         0);
4938                 if (err) {
4939                         dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4940                                 __func__, peer, i, err);
4941                         break;
4942                 }
4943         }
4944
4945         return err;
4946 }
4947
4948 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4949 {
4950         return ufshcd_disable_tx_lcc(hba, true);
4951 }
4952
4953 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4954 {
4955         struct ufs_event_hist *e;
4956
4957         if (id >= UFS_EVT_CNT)
4958                 return;
4959
4960         e = &hba->ufs_stats.event[id];
4961         e->val[e->pos] = val;
4962         e->tstamp[e->pos] = local_clock();
4963         e->cnt += 1;
4964         e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4965
4966         ufshcd_vops_event_notify(hba, id, &val);
4967 }
4968 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4969
4970 /**
4971  * ufshcd_link_startup - Initialize unipro link startup
4972  * @hba: per adapter instance
4973  *
4974  * Return: 0 for success, non-zero in case of failure.
4975  */
4976 static int ufshcd_link_startup(struct ufs_hba *hba)
4977 {
4978         int ret;
4979         int retries = DME_LINKSTARTUP_RETRIES;
4980         bool link_startup_again = false;
4981
4982         /*
4983          * If UFS device isn't active then we will have to issue link startup
4984          * 2 times to make sure the device state move to active.
4985          */
4986         if (!ufshcd_is_ufs_dev_active(hba))
4987                 link_startup_again = true;
4988
4989 link_startup:
4990         do {
4991                 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4992
4993                 ret = ufshcd_dme_link_startup(hba);
4994
4995                 /* check if device is detected by inter-connect layer */
4996                 if (!ret && !ufshcd_is_device_present(hba)) {
4997                         ufshcd_update_evt_hist(hba,
4998                                                UFS_EVT_LINK_STARTUP_FAIL,
4999                                                0);
5000                         dev_err(hba->dev, "%s: Device not present\n", __func__);
5001                         ret = -ENXIO;
5002                         goto out;
5003                 }
5004
5005                 /*
5006                  * DME link lost indication is only received when link is up,
5007                  * but we can't be sure if the link is up until link startup
5008                  * succeeds. So reset the local Uni-Pro and try again.
5009                  */
5010                 if (ret && retries && ufshcd_hba_enable(hba)) {
5011                         ufshcd_update_evt_hist(hba,
5012                                                UFS_EVT_LINK_STARTUP_FAIL,
5013                                                (u32)ret);
5014                         goto out;
5015                 }
5016         } while (ret && retries--);
5017
5018         if (ret) {
5019                 /* failed to get the link up... retire */
5020                 ufshcd_update_evt_hist(hba,
5021                                        UFS_EVT_LINK_STARTUP_FAIL,
5022                                        (u32)ret);
5023                 goto out;
5024         }
5025
5026         if (link_startup_again) {
5027                 link_startup_again = false;
5028                 retries = DME_LINKSTARTUP_RETRIES;
5029                 goto link_startup;
5030         }
5031
5032         /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
5033         ufshcd_init_pwr_info(hba);
5034         ufshcd_print_pwr_info(hba);
5035
5036         if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
5037                 ret = ufshcd_disable_device_tx_lcc(hba);
5038                 if (ret)
5039                         goto out;
5040         }
5041
5042         /* Include any host controller configuration via UIC commands */
5043         ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
5044         if (ret)
5045                 goto out;
5046
5047         /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
5048         ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
5049         ret = ufshcd_make_hba_operational(hba);
5050 out:
5051         if (ret) {
5052                 dev_err(hba->dev, "link startup failed %d\n", ret);
5053                 ufshcd_print_host_state(hba);
5054                 ufshcd_print_pwr_info(hba);
5055                 ufshcd_print_evt_hist(hba);
5056         }
5057         return ret;
5058 }
5059
5060 /**
5061  * ufshcd_verify_dev_init() - Verify device initialization
5062  * @hba: per-adapter instance
5063  *
5064  * Send NOP OUT UPIU and wait for NOP IN response to check whether the
5065  * device Transport Protocol (UTP) layer is ready after a reset.
5066  * If the UTP layer at the device side is not initialized, it may
5067  * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
5068  * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
5069  *
5070  * Return: 0 upon success; < 0 upon failure.
5071  */
5072 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
5073 {
5074         int err = 0;
5075         int retries;
5076
5077         ufshcd_hold(hba);
5078         mutex_lock(&hba->dev_cmd.lock);
5079         for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
5080                 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
5081                                           hba->nop_out_timeout);
5082
5083                 if (!err || err == -ETIMEDOUT)
5084                         break;
5085
5086                 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
5087         }
5088         mutex_unlock(&hba->dev_cmd.lock);
5089         ufshcd_release(hba);
5090
5091         if (err)
5092                 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
5093         return err;
5094 }
5095
5096 /**
5097  * ufshcd_setup_links - associate link b/w device wlun and other luns
5098  * @sdev: pointer to SCSI device
5099  * @hba: pointer to ufs hba
5100  */
5101 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
5102 {
5103         struct device_link *link;
5104
5105         /*
5106          * Device wlun is the supplier & rest of the luns are consumers.
5107          * This ensures that device wlun suspends after all other luns.
5108          */
5109         if (hba->ufs_device_wlun) {
5110                 link = device_link_add(&sdev->sdev_gendev,
5111                                        &hba->ufs_device_wlun->sdev_gendev,
5112                                        DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
5113                 if (!link) {
5114                         dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
5115                                 dev_name(&hba->ufs_device_wlun->sdev_gendev));
5116                         return;
5117                 }
5118                 hba->luns_avail--;
5119                 /* Ignore REPORT_LUN wlun probing */
5120                 if (hba->luns_avail == 1) {
5121                         ufshcd_rpm_put(hba);
5122                         return;
5123                 }
5124         } else {
5125                 /*
5126                  * Device wlun is probed. The assumption is that WLUNs are
5127                  * scanned before other LUNs.
5128                  */
5129                 hba->luns_avail--;
5130         }
5131 }
5132
5133 /**
5134  * ufshcd_lu_init - Initialize the relevant parameters of the LU
5135  * @hba: per-adapter instance
5136  * @sdev: pointer to SCSI device
5137  */
5138 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev)
5139 {
5140         int len = QUERY_DESC_MAX_SIZE;
5141         u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun);
5142         u8 lun_qdepth = hba->nutrs;
5143         u8 *desc_buf;
5144         int ret;
5145
5146         desc_buf = kzalloc(len, GFP_KERNEL);
5147         if (!desc_buf)
5148                 goto set_qdepth;
5149
5150         ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len);
5151         if (ret < 0) {
5152                 if (ret == -EOPNOTSUPP)
5153                         /* If LU doesn't support unit descriptor, its queue depth is set to 1 */
5154                         lun_qdepth = 1;
5155                 kfree(desc_buf);
5156                 goto set_qdepth;
5157         }
5158
5159         if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) {
5160                 /*
5161                  * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will
5162                  * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth
5163                  */
5164                 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs);
5165         }
5166         /*
5167          * According to UFS device specification, the write protection mode is only supported by
5168          * normal LU, not supported by WLUN.
5169          */
5170         if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported &&
5171             !hba->dev_info.is_lu_power_on_wp &&
5172             desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP)
5173                 hba->dev_info.is_lu_power_on_wp = true;
5174
5175         /* In case of RPMB LU, check if advanced RPMB mode is enabled */
5176         if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN &&
5177             desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4))
5178                 hba->dev_info.b_advanced_rpmb_en = true;
5179
5180
5181         kfree(desc_buf);
5182 set_qdepth:
5183         /*
5184          * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose
5185          * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue.
5186          */
5187         dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth);
5188         scsi_change_queue_depth(sdev, lun_qdepth);
5189 }
5190
5191 /**
5192  * ufshcd_slave_alloc - handle initial SCSI device configurations
5193  * @sdev: pointer to SCSI device
5194  *
5195  * Return: success.
5196  */
5197 static int ufshcd_slave_alloc(struct scsi_device *sdev)
5198 {
5199         struct ufs_hba *hba;
5200
5201         hba = shost_priv(sdev->host);
5202
5203         /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
5204         sdev->use_10_for_ms = 1;
5205
5206         /* DBD field should be set to 1 in mode sense(10) */
5207         sdev->set_dbd_for_ms = 1;
5208
5209         /* allow SCSI layer to restart the device in case of errors */
5210         sdev->allow_restart = 1;
5211
5212         /* REPORT SUPPORTED OPERATION CODES is not supported */
5213         sdev->no_report_opcodes = 1;
5214
5215         /* WRITE_SAME command is not supported */
5216         sdev->no_write_same = 1;
5217
5218         ufshcd_lu_init(hba, sdev);
5219
5220         ufshcd_setup_links(hba, sdev);
5221
5222         return 0;
5223 }
5224
5225 /**
5226  * ufshcd_change_queue_depth - change queue depth
5227  * @sdev: pointer to SCSI device
5228  * @depth: required depth to set
5229  *
5230  * Change queue depth and make sure the max. limits are not crossed.
5231  *
5232  * Return: new queue depth.
5233  */
5234 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
5235 {
5236         return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
5237 }
5238
5239 /**
5240  * ufshcd_slave_configure - adjust SCSI device configurations
5241  * @sdev: pointer to SCSI device
5242  *
5243  * Return: 0 (success).
5244  */
5245 static int ufshcd_slave_configure(struct scsi_device *sdev)
5246 {
5247         struct ufs_hba *hba = shost_priv(sdev->host);
5248         struct request_queue *q = sdev->request_queue;
5249
5250         blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
5251
5252         /*
5253          * Block runtime-pm until all consumers are added.
5254          * Refer ufshcd_setup_links().
5255          */
5256         if (is_device_wlun(sdev))
5257                 pm_runtime_get_noresume(&sdev->sdev_gendev);
5258         else if (ufshcd_is_rpm_autosuspend_allowed(hba))
5259                 sdev->rpm_autosuspend = 1;
5260         /*
5261          * Do not print messages during runtime PM to avoid never-ending cycles
5262          * of messages written back to storage by user space causing runtime
5263          * resume, causing more messages and so on.
5264          */
5265         sdev->silence_suspend = 1;
5266
5267         if (hba->vops && hba->vops->config_scsi_dev)
5268                 hba->vops->config_scsi_dev(sdev);
5269
5270         ufshcd_crypto_register(hba, q);
5271
5272         return 0;
5273 }
5274
5275 /**
5276  * ufshcd_slave_destroy - remove SCSI device configurations
5277  * @sdev: pointer to SCSI device
5278  */
5279 static void ufshcd_slave_destroy(struct scsi_device *sdev)
5280 {
5281         struct ufs_hba *hba;
5282         unsigned long flags;
5283
5284         hba = shost_priv(sdev->host);
5285
5286         /* Drop the reference as it won't be needed anymore */
5287         if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5288                 spin_lock_irqsave(hba->host->host_lock, flags);
5289                 hba->ufs_device_wlun = NULL;
5290                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5291         } else if (hba->ufs_device_wlun) {
5292                 struct device *supplier = NULL;
5293
5294                 /* Ensure UFS Device WLUN exists and does not disappear */
5295                 spin_lock_irqsave(hba->host->host_lock, flags);
5296                 if (hba->ufs_device_wlun) {
5297                         supplier = &hba->ufs_device_wlun->sdev_gendev;
5298                         get_device(supplier);
5299                 }
5300                 spin_unlock_irqrestore(hba->host->host_lock, flags);
5301
5302                 if (supplier) {
5303                         /*
5304                          * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5305                          * device will not have been registered but can still
5306                          * have a device link holding a reference to the device.
5307                          */
5308                         device_link_remove(&sdev->sdev_gendev, supplier);
5309                         put_device(supplier);
5310                 }
5311         }
5312 }
5313
5314 /**
5315  * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5316  * @lrbp: pointer to local reference block of completed command
5317  * @scsi_status: SCSI command status
5318  *
5319  * Return: value base on SCSI command status.
5320  */
5321 static inline int
5322 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5323 {
5324         int result = 0;
5325
5326         switch (scsi_status) {
5327         case SAM_STAT_CHECK_CONDITION:
5328                 ufshcd_copy_sense_data(lrbp);
5329                 fallthrough;
5330         case SAM_STAT_GOOD:
5331                 result |= DID_OK << 16 | scsi_status;
5332                 break;
5333         case SAM_STAT_TASK_SET_FULL:
5334         case SAM_STAT_BUSY:
5335         case SAM_STAT_TASK_ABORTED:
5336                 ufshcd_copy_sense_data(lrbp);
5337                 result |= scsi_status;
5338                 break;
5339         default:
5340                 result |= DID_ERROR << 16;
5341                 break;
5342         } /* end of switch */
5343
5344         return result;
5345 }
5346
5347 /**
5348  * ufshcd_transfer_rsp_status - Get overall status of the response
5349  * @hba: per adapter instance
5350  * @lrbp: pointer to local reference block of completed command
5351  * @cqe: pointer to the completion queue entry
5352  *
5353  * Return: result of the command to notify SCSI midlayer.
5354  */
5355 static inline int
5356 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp,
5357                            struct cq_entry *cqe)
5358 {
5359         int result = 0;
5360         int scsi_status;
5361         enum utp_ocs ocs;
5362         u8 upiu_flags;
5363         u32 resid;
5364
5365         upiu_flags = lrbp->ucd_rsp_ptr->header.flags;
5366         resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count);
5367         /*
5368          * Test !overflow instead of underflow to support UFS devices that do
5369          * not set either flag.
5370          */
5371         if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW))
5372                 scsi_set_resid(lrbp->cmd, resid);
5373
5374         /* overall command status of utrd */
5375         ocs = ufshcd_get_tr_ocs(lrbp, cqe);
5376
5377         if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5378                 if (lrbp->ucd_rsp_ptr->header.response ||
5379                     lrbp->ucd_rsp_ptr->header.status)
5380                         ocs = OCS_SUCCESS;
5381         }
5382
5383         switch (ocs) {
5384         case OCS_SUCCESS:
5385                 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5386                 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) {
5387                 case UPIU_TRANSACTION_RESPONSE:
5388                         /*
5389                          * get the result based on SCSI status response
5390                          * to notify the SCSI midlayer of the command status
5391                          */
5392                         scsi_status = lrbp->ucd_rsp_ptr->header.status;
5393                         result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5394
5395                         /*
5396                          * Currently we are only supporting BKOPs exception
5397                          * events hence we can ignore BKOPs exception event
5398                          * during power management callbacks. BKOPs exception
5399                          * event is not expected to be raised in runtime suspend
5400                          * callback as it allows the urgent bkops.
5401                          * During system suspend, we are anyway forcefully
5402                          * disabling the bkops and if urgent bkops is needed
5403                          * it will be enabled on system resume. Long term
5404                          * solution could be to abort the system suspend if
5405                          * UFS device needs urgent BKOPs.
5406                          */
5407                         if (!hba->pm_op_in_progress &&
5408                             !ufshcd_eh_in_progress(hba) &&
5409                             ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5410                                 /* Flushed in suspend */
5411                                 schedule_work(&hba->eeh_work);
5412                         break;
5413                 case UPIU_TRANSACTION_REJECT_UPIU:
5414                         /* TODO: handle Reject UPIU Response */
5415                         result = DID_ERROR << 16;
5416                         dev_err(hba->dev,
5417                                 "Reject UPIU not fully implemented\n");
5418                         break;
5419                 default:
5420                         dev_err(hba->dev,
5421                                 "Unexpected request response code = %x\n",
5422                                 result);
5423                         result = DID_ERROR << 16;
5424                         break;
5425                 }
5426                 break;
5427         case OCS_ABORTED:
5428                 result |= DID_ABORT << 16;
5429                 break;
5430         case OCS_INVALID_COMMAND_STATUS:
5431                 result |= DID_REQUEUE << 16;
5432                 break;
5433         case OCS_INVALID_CMD_TABLE_ATTR:
5434         case OCS_INVALID_PRDT_ATTR:
5435         case OCS_MISMATCH_DATA_BUF_SIZE:
5436         case OCS_MISMATCH_RESP_UPIU_SIZE:
5437         case OCS_PEER_COMM_FAILURE:
5438         case OCS_FATAL_ERROR:
5439         case OCS_DEVICE_FATAL_ERROR:
5440         case OCS_INVALID_CRYPTO_CONFIG:
5441         case OCS_GENERAL_CRYPTO_ERROR:
5442         default:
5443                 result |= DID_ERROR << 16;
5444                 dev_err(hba->dev,
5445                                 "OCS error from controller = %x for tag %d\n",
5446                                 ocs, lrbp->task_tag);
5447                 ufshcd_print_evt_hist(hba);
5448                 ufshcd_print_host_state(hba);
5449                 break;
5450         } /* end of switch */
5451
5452         if ((host_byte(result) != DID_OK) &&
5453             (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5454                 ufshcd_print_tr(hba, lrbp->task_tag, true);
5455         return result;
5456 }
5457
5458 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5459                                          u32 intr_mask)
5460 {
5461         if (!ufshcd_is_auto_hibern8_supported(hba) ||
5462             !ufshcd_is_auto_hibern8_enabled(hba))
5463                 return false;
5464
5465         if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5466                 return false;
5467
5468         if (hba->active_uic_cmd &&
5469             (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5470             hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5471                 return false;
5472
5473         return true;
5474 }
5475
5476 /**
5477  * ufshcd_uic_cmd_compl - handle completion of uic command
5478  * @hba: per adapter instance
5479  * @intr_status: interrupt status generated by the controller
5480  *
5481  * Return:
5482  *  IRQ_HANDLED - If interrupt is valid
5483  *  IRQ_NONE    - If invalid interrupt
5484  */
5485 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5486 {
5487         irqreturn_t retval = IRQ_NONE;
5488
5489         spin_lock(hba->host->host_lock);
5490         if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5491                 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5492
5493         if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
5494                 hba->active_uic_cmd->argument2 |=
5495                         ufshcd_get_uic_cmd_result(hba);
5496                 hba->active_uic_cmd->argument3 =
5497                         ufshcd_get_dme_attr_val(hba);
5498                 if (!hba->uic_async_done)
5499                         hba->active_uic_cmd->cmd_active = 0;
5500                 complete(&hba->active_uic_cmd->done);
5501                 retval = IRQ_HANDLED;
5502         }
5503
5504         if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
5505                 hba->active_uic_cmd->cmd_active = 0;
5506                 complete(hba->uic_async_done);
5507                 retval = IRQ_HANDLED;
5508         }
5509
5510         if (retval == IRQ_HANDLED)
5511                 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
5512                                              UFS_CMD_COMP);
5513         spin_unlock(hba->host->host_lock);
5514         return retval;
5515 }
5516
5517 /* Release the resources allocated for processing a SCSI command. */
5518 void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
5519                              struct ufshcd_lrb *lrbp)
5520 {
5521         struct scsi_cmnd *cmd = lrbp->cmd;
5522
5523         scsi_dma_unmap(cmd);
5524         ufshcd_release(hba);
5525         ufshcd_clk_scaling_update_busy(hba);
5526 }
5527
5528 /**
5529  * ufshcd_compl_one_cqe - handle a completion queue entry
5530  * @hba: per adapter instance
5531  * @task_tag: the task tag of the request to be completed
5532  * @cqe: pointer to the completion queue entry
5533  */
5534 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag,
5535                           struct cq_entry *cqe)
5536 {
5537         struct ufshcd_lrb *lrbp;
5538         struct scsi_cmnd *cmd;
5539         enum utp_ocs ocs;
5540
5541         lrbp = &hba->lrb[task_tag];
5542         lrbp->compl_time_stamp = ktime_get();
5543         cmd = lrbp->cmd;
5544         if (cmd) {
5545                 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5546                         ufshcd_update_monitor(hba, lrbp);
5547                 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP);
5548                 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe);
5549                 ufshcd_release_scsi_cmd(hba, lrbp);
5550                 /* Do not touch lrbp after scsi done */
5551                 scsi_done(cmd);
5552         } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5553                    lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5554                 if (hba->dev_cmd.complete) {
5555                         if (cqe) {
5556                                 ocs = le32_to_cpu(cqe->status) & MASK_OCS;
5557                                 lrbp->utr_descriptor_ptr->header.ocs = ocs;
5558                         }
5559                         complete(hba->dev_cmd.complete);
5560                 }
5561         }
5562 }
5563
5564 /**
5565  * __ufshcd_transfer_req_compl - handle SCSI and query command completion
5566  * @hba: per adapter instance
5567  * @completed_reqs: bitmask that indicates which requests to complete
5568  */
5569 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5570                                         unsigned long completed_reqs)
5571 {
5572         int tag;
5573
5574         for_each_set_bit(tag, &completed_reqs, hba->nutrs)
5575                 ufshcd_compl_one_cqe(hba, tag, NULL);
5576 }
5577
5578 /* Any value that is not an existing queue number is fine for this constant. */
5579 enum {
5580         UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1
5581 };
5582
5583 static void ufshcd_clear_polled(struct ufs_hba *hba,
5584                                 unsigned long *completed_reqs)
5585 {
5586         int tag;
5587
5588         for_each_set_bit(tag, completed_reqs, hba->nutrs) {
5589                 struct scsi_cmnd *cmd = hba->lrb[tag].cmd;
5590
5591                 if (!cmd)
5592                         continue;
5593                 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED)
5594                         __clear_bit(tag, completed_reqs);
5595         }
5596 }
5597
5598 /*
5599  * Return: > 0 if one or more commands have been completed or 0 if no
5600  * requests have been completed.
5601  */
5602 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5603 {
5604         struct ufs_hba *hba = shost_priv(shost);
5605         unsigned long completed_reqs, flags;
5606         u32 tr_doorbell;
5607         struct ufs_hw_queue *hwq;
5608
5609         if (is_mcq_enabled(hba)) {
5610                 hwq = &hba->uhq[queue_num];
5611
5612                 return ufshcd_mcq_poll_cqe_lock(hba, hwq);
5613         }
5614
5615         spin_lock_irqsave(&hba->outstanding_lock, flags);
5616         tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5617         completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5618         WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5619                   "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5620                   hba->outstanding_reqs);
5621         if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) {
5622                 /* Do not complete polled requests from interrupt context. */
5623                 ufshcd_clear_polled(hba, &completed_reqs);
5624         }
5625         hba->outstanding_reqs &= ~completed_reqs;
5626         spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5627
5628         if (completed_reqs)
5629                 __ufshcd_transfer_req_compl(hba, completed_reqs);
5630
5631         return completed_reqs != 0;
5632 }
5633
5634 /**
5635  * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is
5636  * invoked from the error handler context or ufshcd_host_reset_and_restore()
5637  * to complete the pending transfers and free the resources associated with
5638  * the scsi command.
5639  *
5640  * @hba: per adapter instance
5641  * @force_compl: This flag is set to true when invoked
5642  * from ufshcd_host_reset_and_restore() in which case it requires special
5643  * handling because the host controller has been reset by ufshcd_hba_stop().
5644  */
5645 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba,
5646                                               bool force_compl)
5647 {
5648         struct ufs_hw_queue *hwq;
5649         struct ufshcd_lrb *lrbp;
5650         struct scsi_cmnd *cmd;
5651         unsigned long flags;
5652         int tag;
5653
5654         for (tag = 0; tag < hba->nutrs; tag++) {
5655                 lrbp = &hba->lrb[tag];
5656                 cmd = lrbp->cmd;
5657                 if (!ufshcd_cmd_inflight(cmd) ||
5658                     test_bit(SCMD_STATE_COMPLETE, &cmd->state))
5659                         continue;
5660
5661                 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd));
5662
5663                 if (force_compl) {
5664                         ufshcd_mcq_compl_all_cqes_lock(hba, hwq);
5665                         /*
5666                          * For those cmds of which the cqes are not present
5667                          * in the cq, complete them explicitly.
5668                          */
5669                         spin_lock_irqsave(&hwq->cq_lock, flags);
5670                         if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) {
5671                                 set_host_byte(cmd, DID_REQUEUE);
5672                                 ufshcd_release_scsi_cmd(hba, lrbp);
5673                                 scsi_done(cmd);
5674                         }
5675                         spin_unlock_irqrestore(&hwq->cq_lock, flags);
5676                 } else {
5677                         ufshcd_mcq_poll_cqe_lock(hba, hwq);
5678                 }
5679         }
5680 }
5681
5682 /**
5683  * ufshcd_transfer_req_compl - handle SCSI and query command completion
5684  * @hba: per adapter instance
5685  *
5686  * Return:
5687  *  IRQ_HANDLED - If interrupt is valid
5688  *  IRQ_NONE    - If invalid interrupt
5689  */
5690 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5691 {
5692         /* Resetting interrupt aggregation counters first and reading the
5693          * DOOR_BELL afterward allows us to handle all the completed requests.
5694          * In order to prevent other interrupts starvation the DB is read once
5695          * after reset. The down side of this solution is the possibility of
5696          * false interrupt if device completes another request after resetting
5697          * aggregation and before reading the DB.
5698          */
5699         if (ufshcd_is_intr_aggr_allowed(hba) &&
5700             !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5701                 ufshcd_reset_intr_aggr(hba);
5702
5703         if (ufs_fail_completion(hba))
5704                 return IRQ_HANDLED;
5705
5706         /*
5707          * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5708          * do not want polling to trigger spurious interrupt complaints.
5709          */
5710         ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT);
5711
5712         return IRQ_HANDLED;
5713 }
5714
5715 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5716 {
5717         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5718                                        QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5719                                        &ee_ctrl_mask);
5720 }
5721
5722 int ufshcd_write_ee_control(struct ufs_hba *hba)
5723 {
5724         int err;
5725
5726         mutex_lock(&hba->ee_ctrl_mutex);
5727         err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5728         mutex_unlock(&hba->ee_ctrl_mutex);
5729         if (err)
5730                 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5731                         __func__, err);
5732         return err;
5733 }
5734
5735 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
5736                              const u16 *other_mask, u16 set, u16 clr)
5737 {
5738         u16 new_mask, ee_ctrl_mask;
5739         int err = 0;
5740
5741         mutex_lock(&hba->ee_ctrl_mutex);
5742         new_mask = (*mask & ~clr) | set;
5743         ee_ctrl_mask = new_mask | *other_mask;
5744         if (ee_ctrl_mask != hba->ee_ctrl_mask)
5745                 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5746         /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5747         if (!err) {
5748                 hba->ee_ctrl_mask = ee_ctrl_mask;
5749                 *mask = new_mask;
5750         }
5751         mutex_unlock(&hba->ee_ctrl_mutex);
5752         return err;
5753 }
5754
5755 /**
5756  * ufshcd_disable_ee - disable exception event
5757  * @hba: per-adapter instance
5758  * @mask: exception event to disable
5759  *
5760  * Disables exception event in the device so that the EVENT_ALERT
5761  * bit is not set.
5762  *
5763  * Return: zero on success, non-zero error value on failure.
5764  */
5765 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5766 {
5767         return ufshcd_update_ee_drv_mask(hba, 0, mask);
5768 }
5769
5770 /**
5771  * ufshcd_enable_ee - enable exception event
5772  * @hba: per-adapter instance
5773  * @mask: exception event to enable
5774  *
5775  * Enable corresponding exception event in the device to allow
5776  * device to alert host in critical scenarios.
5777  *
5778  * Return: zero on success, non-zero error value on failure.
5779  */
5780 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5781 {
5782         return ufshcd_update_ee_drv_mask(hba, mask, 0);
5783 }
5784
5785 /**
5786  * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5787  * @hba: per-adapter instance
5788  *
5789  * Allow device to manage background operations on its own. Enabling
5790  * this might lead to inconsistent latencies during normal data transfers
5791  * as the device is allowed to manage its own way of handling background
5792  * operations.
5793  *
5794  * Return: zero on success, non-zero on failure.
5795  */
5796 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5797 {
5798         int err = 0;
5799
5800         if (hba->auto_bkops_enabled)
5801                 goto out;
5802
5803         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5804                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5805         if (err) {
5806                 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5807                                 __func__, err);
5808                 goto out;
5809         }
5810
5811         hba->auto_bkops_enabled = true;
5812         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5813
5814         /* No need of URGENT_BKOPS exception from the device */
5815         err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5816         if (err)
5817                 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5818                                 __func__, err);
5819 out:
5820         return err;
5821 }
5822
5823 /**
5824  * ufshcd_disable_auto_bkops - block device in doing background operations
5825  * @hba: per-adapter instance
5826  *
5827  * Disabling background operations improves command response latency but
5828  * has drawback of device moving into critical state where the device is
5829  * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5830  * host is idle so that BKOPS are managed effectively without any negative
5831  * impacts.
5832  *
5833  * Return: zero on success, non-zero on failure.
5834  */
5835 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5836 {
5837         int err = 0;
5838
5839         if (!hba->auto_bkops_enabled)
5840                 goto out;
5841
5842         /*
5843          * If host assisted BKOPs is to be enabled, make sure
5844          * urgent bkops exception is allowed.
5845          */
5846         err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5847         if (err) {
5848                 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5849                                 __func__, err);
5850                 goto out;
5851         }
5852
5853         err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5854                         QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5855         if (err) {
5856                 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5857                                 __func__, err);
5858                 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5859                 goto out;
5860         }
5861
5862         hba->auto_bkops_enabled = false;
5863         trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5864         hba->is_urgent_bkops_lvl_checked = false;
5865 out:
5866         return err;
5867 }
5868
5869 /**
5870  * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5871  * @hba: per adapter instance
5872  *
5873  * After a device reset the device may toggle the BKOPS_EN flag
5874  * to default value. The s/w tracking variables should be updated
5875  * as well. This function would change the auto-bkops state based on
5876  * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5877  */
5878 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5879 {
5880         if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5881                 hba->auto_bkops_enabled = false;
5882                 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5883                 ufshcd_enable_auto_bkops(hba);
5884         } else {
5885                 hba->auto_bkops_enabled = true;
5886                 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5887                 ufshcd_disable_auto_bkops(hba);
5888         }
5889         hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5890         hba->is_urgent_bkops_lvl_checked = false;
5891 }
5892
5893 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5894 {
5895         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5896                         QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5897 }
5898
5899 /**
5900  * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5901  * @hba: per-adapter instance
5902  * @status: bkops_status value
5903  *
5904  * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5905  * flag in the device to permit background operations if the device
5906  * bkops_status is greater than or equal to "status" argument passed to
5907  * this function, disable otherwise.
5908  *
5909  * Return: 0 for success, non-zero in case of failure.
5910  *
5911  * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5912  * to know whether auto bkops is enabled or disabled after this function
5913  * returns control to it.
5914  */
5915 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5916                              enum bkops_status status)
5917 {
5918         int err;
5919         u32 curr_status = 0;
5920
5921         err = ufshcd_get_bkops_status(hba, &curr_status);
5922         if (err) {
5923                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5924                                 __func__, err);
5925                 goto out;
5926         } else if (curr_status > BKOPS_STATUS_MAX) {
5927                 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5928                                 __func__, curr_status);
5929                 err = -EINVAL;
5930                 goto out;
5931         }
5932
5933         if (curr_status >= status)
5934                 err = ufshcd_enable_auto_bkops(hba);
5935         else
5936                 err = ufshcd_disable_auto_bkops(hba);
5937 out:
5938         return err;
5939 }
5940
5941 /**
5942  * ufshcd_urgent_bkops - handle urgent bkops exception event
5943  * @hba: per-adapter instance
5944  *
5945  * Enable fBackgroundOpsEn flag in the device to permit background
5946  * operations.
5947  *
5948  * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5949  * and negative error value for any other failure.
5950  *
5951  * Return: 0 upon success; < 0 upon failure.
5952  */
5953 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5954 {
5955         return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5956 }
5957
5958 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5959 {
5960         return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5961                         QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5962 }
5963
5964 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5965 {
5966         int err;
5967         u32 curr_status = 0;
5968
5969         if (hba->is_urgent_bkops_lvl_checked)
5970                 goto enable_auto_bkops;
5971
5972         err = ufshcd_get_bkops_status(hba, &curr_status);
5973         if (err) {
5974                 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5975                                 __func__, err);
5976                 goto out;
5977         }
5978
5979         /*
5980          * We are seeing that some devices are raising the urgent bkops
5981          * exception events even when BKOPS status doesn't indicate performace
5982          * impacted or critical. Handle these device by determining their urgent
5983          * bkops status at runtime.
5984          */
5985         if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5986                 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5987                                 __func__, curr_status);
5988                 /* update the current status as the urgent bkops level */
5989                 hba->urgent_bkops_lvl = curr_status;
5990                 hba->is_urgent_bkops_lvl_checked = true;
5991         }
5992
5993 enable_auto_bkops:
5994         err = ufshcd_enable_auto_bkops(hba);
5995 out:
5996         if (err < 0)
5997                 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5998                                 __func__, err);
5999 }
6000
6001 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status)
6002 {
6003         u32 value;
6004
6005         if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6006                                 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value))
6007                 return;
6008
6009         dev_info(hba->dev, "exception Tcase %d\n", value - 80);
6010
6011         ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP);
6012
6013         /*
6014          * A placeholder for the platform vendors to add whatever additional
6015          * steps required
6016          */
6017 }
6018
6019 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
6020 {
6021         u8 index;
6022         enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
6023                                    UPIU_QUERY_OPCODE_CLEAR_FLAG;
6024
6025         index = ufshcd_wb_get_query_index(hba);
6026         return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
6027 }
6028
6029 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
6030 {
6031         int ret;
6032
6033         if (!ufshcd_is_wb_allowed(hba) ||
6034             hba->dev_info.wb_enabled == enable)
6035                 return 0;
6036
6037         ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
6038         if (ret) {
6039                 dev_err(hba->dev, "%s: Write Booster %s failed %d\n",
6040                         __func__, enable ? "enabling" : "disabling", ret);
6041                 return ret;
6042         }
6043
6044         hba->dev_info.wb_enabled = enable;
6045         dev_dbg(hba->dev, "%s: Write Booster %s\n",
6046                         __func__, enable ? "enabled" : "disabled");
6047
6048         return ret;
6049 }
6050
6051 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba,
6052                                                  bool enable)
6053 {
6054         int ret;
6055
6056         ret = __ufshcd_wb_toggle(hba, enable,
6057                         QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
6058         if (ret) {
6059                 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n",
6060                         __func__, enable ? "enabling" : "disabling", ret);
6061                 return;
6062         }
6063         dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n",
6064                         __func__, enable ? "enabled" : "disabled");
6065 }
6066
6067 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable)
6068 {
6069         int ret;
6070
6071         if (!ufshcd_is_wb_allowed(hba) ||
6072             hba->dev_info.wb_buf_flush_enabled == enable)
6073                 return 0;
6074
6075         ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
6076         if (ret) {
6077                 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n",
6078                         __func__, enable ? "enabling" : "disabling", ret);
6079                 return ret;
6080         }
6081
6082         hba->dev_info.wb_buf_flush_enabled = enable;
6083         dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n",
6084                         __func__, enable ? "enabled" : "disabled");
6085
6086         return ret;
6087 }
6088
6089 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
6090                                                 u32 avail_buf)
6091 {
6092         u32 cur_buf;
6093         int ret;
6094         u8 index;
6095
6096         index = ufshcd_wb_get_query_index(hba);
6097         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6098                                               QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
6099                                               index, 0, &cur_buf);
6100         if (ret) {
6101                 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n",
6102                         __func__, ret);
6103                 return false;
6104         }
6105
6106         if (!cur_buf) {
6107                 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
6108                          cur_buf);
6109                 return false;
6110         }
6111         /* Let it continue to flush when available buffer exceeds threshold */
6112         return avail_buf < hba->vps->wb_flush_threshold;
6113 }
6114
6115 static void ufshcd_wb_force_disable(struct ufs_hba *hba)
6116 {
6117         if (ufshcd_is_wb_buf_flush_allowed(hba))
6118                 ufshcd_wb_toggle_buf_flush(hba, false);
6119
6120         ufshcd_wb_toggle_buf_flush_during_h8(hba, false);
6121         ufshcd_wb_toggle(hba, false);
6122         hba->caps &= ~UFSHCD_CAP_WB_EN;
6123
6124         dev_info(hba->dev, "%s: WB force disabled\n", __func__);
6125 }
6126
6127 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
6128 {
6129         u32 lifetime;
6130         int ret;
6131         u8 index;
6132
6133         index = ufshcd_wb_get_query_index(hba);
6134         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6135                                       QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
6136                                       index, 0, &lifetime);
6137         if (ret) {
6138                 dev_err(hba->dev,
6139                         "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
6140                         __func__, ret);
6141                 return false;
6142         }
6143
6144         if (lifetime == UFS_WB_EXCEED_LIFETIME) {
6145                 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
6146                         __func__, lifetime);
6147                 return false;
6148         }
6149
6150         dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
6151                 __func__, lifetime);
6152
6153         return true;
6154 }
6155
6156 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
6157 {
6158         int ret;
6159         u32 avail_buf;
6160         u8 index;
6161
6162         if (!ufshcd_is_wb_allowed(hba))
6163                 return false;
6164
6165         if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
6166                 ufshcd_wb_force_disable(hba);
6167                 return false;
6168         }
6169
6170         /*
6171          * The ufs device needs the vcc to be ON to flush.
6172          * With user-space reduction enabled, it's enough to enable flush
6173          * by checking only the available buffer. The threshold
6174          * defined here is > 90% full.
6175          * With user-space preserved enabled, the current-buffer
6176          * should be checked too because the wb buffer size can reduce
6177          * when disk tends to be full. This info is provided by current
6178          * buffer (dCurrentWriteBoosterBufferSize). There's no point in
6179          * keeping vcc on when current buffer is empty.
6180          */
6181         index = ufshcd_wb_get_query_index(hba);
6182         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
6183                                       QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
6184                                       index, 0, &avail_buf);
6185         if (ret) {
6186                 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n",
6187                          __func__, ret);
6188                 return false;
6189         }
6190
6191         if (!hba->dev_info.b_presrv_uspc_en)
6192                 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10);
6193
6194         return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
6195 }
6196
6197 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
6198 {
6199         struct ufs_hba *hba = container_of(to_delayed_work(work),
6200                                            struct ufs_hba,
6201                                            rpm_dev_flush_recheck_work);
6202         /*
6203          * To prevent unnecessary VCC power drain after device finishes
6204          * WriteBooster buffer flush or Auto BKOPs, force runtime resume
6205          * after a certain delay to recheck the threshold by next runtime
6206          * suspend.
6207          */
6208         ufshcd_rpm_get_sync(hba);
6209         ufshcd_rpm_put_sync(hba);
6210 }
6211
6212 /**
6213  * ufshcd_exception_event_handler - handle exceptions raised by device
6214  * @work: pointer to work data
6215  *
6216  * Read bExceptionEventStatus attribute from the device and handle the
6217  * exception event accordingly.
6218  */
6219 static void ufshcd_exception_event_handler(struct work_struct *work)
6220 {
6221         struct ufs_hba *hba;
6222         int err;
6223         u32 status = 0;
6224         hba = container_of(work, struct ufs_hba, eeh_work);
6225
6226         ufshcd_scsi_block_requests(hba);
6227         err = ufshcd_get_ee_status(hba, &status);
6228         if (err) {
6229                 dev_err(hba->dev, "%s: failed to get exception status %d\n",
6230                                 __func__, err);
6231                 goto out;
6232         }
6233
6234         trace_ufshcd_exception_event(dev_name(hba->dev), status);
6235
6236         if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
6237                 ufshcd_bkops_exception_event_handler(hba);
6238
6239         if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
6240                 ufshcd_temp_exception_event_handler(hba, status);
6241
6242         ufs_debugfs_exception_event(hba, status);
6243 out:
6244         ufshcd_scsi_unblock_requests(hba);
6245 }
6246
6247 /* Complete requests that have door-bell cleared */
6248 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl)
6249 {
6250         if (is_mcq_enabled(hba))
6251                 ufshcd_mcq_compl_pending_transfer(hba, force_compl);
6252         else
6253                 ufshcd_transfer_req_compl(hba);
6254
6255         ufshcd_tmc_handler(hba);
6256 }
6257
6258 /**
6259  * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
6260  *                              to recover from the DL NAC errors or not.
6261  * @hba: per-adapter instance
6262  *
6263  * Return: true if error handling is required, false otherwise.
6264  */
6265 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
6266 {
6267         unsigned long flags;
6268         bool err_handling = true;
6269
6270         spin_lock_irqsave(hba->host->host_lock, flags);
6271         /*
6272          * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
6273          * device fatal error and/or DL NAC & REPLAY timeout errors.
6274          */
6275         if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
6276                 goto out;
6277
6278         if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
6279             ((hba->saved_err & UIC_ERROR) &&
6280              (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
6281                 goto out;
6282
6283         if ((hba->saved_err & UIC_ERROR) &&
6284             (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
6285                 int err;
6286                 /*
6287                  * wait for 50ms to see if we can get any other errors or not.
6288                  */
6289                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6290                 msleep(50);
6291                 spin_lock_irqsave(hba->host->host_lock, flags);
6292
6293                 /*
6294                  * now check if we have got any other severe errors other than
6295                  * DL NAC error?
6296                  */
6297                 if ((hba->saved_err & INT_FATAL_ERRORS) ||
6298                     ((hba->saved_err & UIC_ERROR) &&
6299                     (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
6300                         goto out;
6301
6302                 /*
6303                  * As DL NAC is the only error received so far, send out NOP
6304                  * command to confirm if link is still active or not.
6305                  *   - If we don't get any response then do error recovery.
6306                  *   - If we get response then clear the DL NAC error bit.
6307                  */
6308
6309                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6310                 err = ufshcd_verify_dev_init(hba);
6311                 spin_lock_irqsave(hba->host->host_lock, flags);
6312
6313                 if (err)
6314                         goto out;
6315
6316                 /* Link seems to be alive hence ignore the DL NAC errors */
6317                 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
6318                         hba->saved_err &= ~UIC_ERROR;
6319                 /* clear NAC error */
6320                 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6321                 if (!hba->saved_uic_err)
6322                         err_handling = false;
6323         }
6324 out:
6325         spin_unlock_irqrestore(hba->host->host_lock, flags);
6326         return err_handling;
6327 }
6328
6329 /* host lock must be held before calling this func */
6330 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6331 {
6332         return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6333                (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6334 }
6335
6336 void ufshcd_schedule_eh_work(struct ufs_hba *hba)
6337 {
6338         lockdep_assert_held(hba->host->host_lock);
6339
6340         /* handle fatal errors only when link is not in error state */
6341         if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6342                 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6343                     ufshcd_is_saved_err_fatal(hba))
6344                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6345                 else
6346                         hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6347                 queue_work(hba->eh_wq, &hba->eh_work);
6348         }
6349 }
6350
6351 static void ufshcd_force_error_recovery(struct ufs_hba *hba)
6352 {
6353         spin_lock_irq(hba->host->host_lock);
6354         hba->force_reset = true;
6355         ufshcd_schedule_eh_work(hba);
6356         spin_unlock_irq(hba->host->host_lock);
6357 }
6358
6359 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6360 {
6361         mutex_lock(&hba->wb_mutex);
6362         down_write(&hba->clk_scaling_lock);
6363         hba->clk_scaling.is_allowed = allow;
6364         up_write(&hba->clk_scaling_lock);
6365         mutex_unlock(&hba->wb_mutex);
6366 }
6367
6368 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6369 {
6370         if (suspend) {
6371                 if (hba->clk_scaling.is_enabled)
6372                         ufshcd_suspend_clkscaling(hba);
6373                 ufshcd_clk_scaling_allow(hba, false);
6374         } else {
6375                 ufshcd_clk_scaling_allow(hba, true);
6376                 if (hba->clk_scaling.is_enabled)
6377                         ufshcd_resume_clkscaling(hba);
6378         }
6379 }
6380
6381 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6382 {
6383         ufshcd_rpm_get_sync(hba);
6384         if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) ||
6385             hba->is_sys_suspended) {
6386                 enum ufs_pm_op pm_op;
6387
6388                 /*
6389                  * Don't assume anything of resume, if
6390                  * resume fails, irq and clocks can be OFF, and powers
6391                  * can be OFF or in LPM.
6392                  */
6393                 ufshcd_setup_hba_vreg(hba, true);
6394                 ufshcd_enable_irq(hba);
6395                 ufshcd_setup_vreg(hba, true);
6396                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6397                 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6398                 ufshcd_hold(hba);
6399                 if (!ufshcd_is_clkgating_allowed(hba))
6400                         ufshcd_setup_clocks(hba, true);
6401                 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6402                 ufshcd_vops_resume(hba, pm_op);
6403         } else {
6404                 ufshcd_hold(hba);
6405                 if (ufshcd_is_clkscaling_supported(hba) &&
6406                     hba->clk_scaling.is_enabled)
6407                         ufshcd_suspend_clkscaling(hba);
6408                 ufshcd_clk_scaling_allow(hba, false);
6409         }
6410         ufshcd_scsi_block_requests(hba);
6411         /* Wait for ongoing ufshcd_queuecommand() calls to finish. */
6412         blk_mq_wait_quiesce_done(&hba->host->tag_set);
6413         cancel_work_sync(&hba->eeh_work);
6414 }
6415
6416 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6417 {
6418         ufshcd_scsi_unblock_requests(hba);
6419         ufshcd_release(hba);
6420         if (ufshcd_is_clkscaling_supported(hba))
6421                 ufshcd_clk_scaling_suspend(hba, false);
6422         ufshcd_rpm_put(hba);
6423 }
6424
6425 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6426 {
6427         return (!hba->is_powered || hba->shutting_down ||
6428                 !hba->ufs_device_wlun ||
6429                 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
6430                 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
6431                    ufshcd_is_link_broken(hba))));
6432 }
6433
6434 #ifdef CONFIG_PM
6435 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6436 {
6437         struct Scsi_Host *shost = hba->host;
6438         struct scsi_device *sdev;
6439         struct request_queue *q;
6440         int ret;
6441
6442         hba->is_sys_suspended = false;
6443         /*
6444          * Set RPM status of wlun device to RPM_ACTIVE,
6445          * this also clears its runtime error.
6446          */
6447         ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev);
6448
6449         /* hba device might have a runtime error otherwise */
6450         if (ret)
6451                 ret = pm_runtime_set_active(hba->dev);
6452         /*
6453          * If wlun device had runtime error, we also need to resume those
6454          * consumer scsi devices in case any of them has failed to be
6455          * resumed due to supplier runtime resume failure. This is to unblock
6456          * blk_queue_enter in case there are bios waiting inside it.
6457          */
6458         if (!ret) {
6459                 shost_for_each_device(sdev, shost) {
6460                         q = sdev->request_queue;
6461                         if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6462                                        q->rpm_status == RPM_SUSPENDING))
6463                                 pm_request_resume(q->dev);
6464                 }
6465         }
6466 }
6467 #else
6468 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6469 {
6470 }
6471 #endif
6472
6473 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6474 {
6475         struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6476         u32 mode;
6477
6478         ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6479
6480         if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6481                 return true;
6482
6483         if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6484                 return true;
6485
6486         return false;
6487 }
6488
6489 static bool ufshcd_abort_one(struct request *rq, void *priv)
6490 {
6491         int *ret = priv;
6492         u32 tag = rq->tag;
6493         struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq);
6494         struct scsi_device *sdev = cmd->device;
6495         struct Scsi_Host *shost = sdev->host;
6496         struct ufs_hba *hba = shost_priv(shost);
6497         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
6498         struct ufs_hw_queue *hwq;
6499         unsigned long flags;
6500
6501         *ret = ufshcd_try_to_abort_task(hba, tag);
6502         dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag,
6503                 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1,
6504                 *ret ? "failed" : "succeeded");
6505
6506         /* Release cmd in MCQ mode if abort succeeds */
6507         if (is_mcq_enabled(hba) && (*ret == 0)) {
6508                 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd));
6509                 spin_lock_irqsave(&hwq->cq_lock, flags);
6510                 if (ufshcd_cmd_inflight(lrbp->cmd))
6511                         ufshcd_release_scsi_cmd(hba, lrbp);
6512                 spin_unlock_irqrestore(&hwq->cq_lock, flags);
6513         }
6514
6515         return *ret == 0;
6516 }
6517
6518 /**
6519  * ufshcd_abort_all - Abort all pending commands.
6520  * @hba: Host bus adapter pointer.
6521  *
6522  * Return: true if and only if the host controller needs to be reset.
6523  */
6524 static bool ufshcd_abort_all(struct ufs_hba *hba)
6525 {
6526         int tag, ret = 0;
6527
6528         blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret);
6529         if (ret)
6530                 goto out;
6531
6532         /* Clear pending task management requests */
6533         for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6534                 ret = ufshcd_clear_tm_cmd(hba, tag);
6535                 if (ret)
6536                         goto out;
6537         }
6538
6539 out:
6540         /* Complete the requests that are cleared by s/w */
6541         ufshcd_complete_requests(hba, false);
6542
6543         return ret != 0;
6544 }
6545
6546 /**
6547  * ufshcd_err_handler - handle UFS errors that require s/w attention
6548  * @work: pointer to work structure
6549  */
6550 static void ufshcd_err_handler(struct work_struct *work)
6551 {
6552         int retries = MAX_ERR_HANDLER_RETRIES;
6553         struct ufs_hba *hba;
6554         unsigned long flags;
6555         bool needs_restore;
6556         bool needs_reset;
6557         int pmc_err;
6558
6559         hba = container_of(work, struct ufs_hba, eh_work);
6560
6561         dev_info(hba->dev,
6562                  "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n",
6563                  __func__, ufshcd_state_name[hba->ufshcd_state],
6564                  hba->is_powered, hba->shutting_down, hba->saved_err,
6565                  hba->saved_uic_err, hba->force_reset,
6566                  ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6567
6568         down(&hba->host_sem);
6569         spin_lock_irqsave(hba->host->host_lock, flags);
6570         if (ufshcd_err_handling_should_stop(hba)) {
6571                 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6572                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6573                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6574                 up(&hba->host_sem);
6575                 return;
6576         }
6577         ufshcd_set_eh_in_progress(hba);
6578         spin_unlock_irqrestore(hba->host->host_lock, flags);
6579         ufshcd_err_handling_prepare(hba);
6580         /* Complete requests that have door-bell cleared by h/w */
6581         ufshcd_complete_requests(hba, false);
6582         spin_lock_irqsave(hba->host->host_lock, flags);
6583 again:
6584         needs_restore = false;
6585         needs_reset = false;
6586
6587         if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6588                 hba->ufshcd_state = UFSHCD_STATE_RESET;
6589         /*
6590          * A full reset and restore might have happened after preparation
6591          * is finished, double check whether we should stop.
6592          */
6593         if (ufshcd_err_handling_should_stop(hba))
6594                 goto skip_err_handling;
6595
6596         if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6597                 bool ret;
6598
6599                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6600                 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6601                 ret = ufshcd_quirk_dl_nac_errors(hba);
6602                 spin_lock_irqsave(hba->host->host_lock, flags);
6603                 if (!ret && ufshcd_err_handling_should_stop(hba))
6604                         goto skip_err_handling;
6605         }
6606
6607         if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6608             (hba->saved_uic_err &&
6609              (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6610                 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6611
6612                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6613                 ufshcd_print_host_state(hba);
6614                 ufshcd_print_pwr_info(hba);
6615                 ufshcd_print_evt_hist(hba);
6616                 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6617                 ufshcd_print_trs_all(hba, pr_prdt);
6618                 spin_lock_irqsave(hba->host->host_lock, flags);
6619         }
6620
6621         /*
6622          * if host reset is required then skip clearing the pending
6623          * transfers forcefully because they will get cleared during
6624          * host reset and restore
6625          */
6626         if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6627             ufshcd_is_saved_err_fatal(hba) ||
6628             ((hba->saved_err & UIC_ERROR) &&
6629              (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6630                                     UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6631                 needs_reset = true;
6632                 goto do_reset;
6633         }
6634
6635         /*
6636          * If LINERESET was caught, UFS might have been put to PWM mode,
6637          * check if power mode restore is needed.
6638          */
6639         if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6640                 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6641                 if (!hba->saved_uic_err)
6642                         hba->saved_err &= ~UIC_ERROR;
6643                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6644                 if (ufshcd_is_pwr_mode_restore_needed(hba))
6645                         needs_restore = true;
6646                 spin_lock_irqsave(hba->host->host_lock, flags);
6647                 if (!hba->saved_err && !needs_restore)
6648                         goto skip_err_handling;
6649         }
6650
6651         hba->silence_err_logs = true;
6652         /* release lock as clear command might sleep */
6653         spin_unlock_irqrestore(hba->host->host_lock, flags);
6654
6655         needs_reset = ufshcd_abort_all(hba);
6656
6657         spin_lock_irqsave(hba->host->host_lock, flags);
6658         hba->silence_err_logs = false;
6659         if (needs_reset)
6660                 goto do_reset;
6661
6662         /*
6663          * After all reqs and tasks are cleared from doorbell,
6664          * now it is safe to retore power mode.
6665          */
6666         if (needs_restore) {
6667                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6668                 /*
6669                  * Hold the scaling lock just in case dev cmds
6670                  * are sent via bsg and/or sysfs.
6671                  */
6672                 down_write(&hba->clk_scaling_lock);
6673                 hba->force_pmc = true;
6674                 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6675                 if (pmc_err) {
6676                         needs_reset = true;
6677                         dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6678                                         __func__, pmc_err);
6679                 }
6680                 hba->force_pmc = false;
6681                 ufshcd_print_pwr_info(hba);
6682                 up_write(&hba->clk_scaling_lock);
6683                 spin_lock_irqsave(hba->host->host_lock, flags);
6684         }
6685
6686 do_reset:
6687         /* Fatal errors need reset */
6688         if (needs_reset) {
6689                 int err;
6690
6691                 hba->force_reset = false;
6692                 spin_unlock_irqrestore(hba->host->host_lock, flags);
6693                 err = ufshcd_reset_and_restore(hba);
6694                 if (err)
6695                         dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6696                                         __func__, err);
6697                 else
6698                         ufshcd_recover_pm_error(hba);
6699                 spin_lock_irqsave(hba->host->host_lock, flags);
6700         }
6701
6702 skip_err_handling:
6703         if (!needs_reset) {
6704                 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6705                         hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6706                 if (hba->saved_err || hba->saved_uic_err)
6707                         dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6708                             __func__, hba->saved_err, hba->saved_uic_err);
6709         }
6710         /* Exit in an operational state or dead */
6711         if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6712             hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6713                 if (--retries)
6714                         goto again;
6715                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6716         }
6717         ufshcd_clear_eh_in_progress(hba);
6718         spin_unlock_irqrestore(hba->host->host_lock, flags);
6719         ufshcd_err_handling_unprepare(hba);
6720         up(&hba->host_sem);
6721
6722         dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6723                  ufshcd_state_name[hba->ufshcd_state]);
6724 }
6725
6726 /**
6727  * ufshcd_update_uic_error - check and set fatal UIC error flags.
6728  * @hba: per-adapter instance
6729  *
6730  * Return:
6731  *  IRQ_HANDLED - If interrupt is valid
6732  *  IRQ_NONE    - If invalid interrupt
6733  */
6734 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6735 {
6736         u32 reg;
6737         irqreturn_t retval = IRQ_NONE;
6738
6739         /* PHY layer error */
6740         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6741         if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6742             (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6743                 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6744                 /*
6745                  * To know whether this error is fatal or not, DB timeout
6746                  * must be checked but this error is handled separately.
6747                  */
6748                 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6749                         dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6750                                         __func__);
6751
6752                 /* Got a LINERESET indication. */
6753                 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6754                         struct uic_command *cmd = NULL;
6755
6756                         hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6757                         if (hba->uic_async_done && hba->active_uic_cmd)
6758                                 cmd = hba->active_uic_cmd;
6759                         /*
6760                          * Ignore the LINERESET during power mode change
6761                          * operation via DME_SET command.
6762                          */
6763                         if (cmd && (cmd->command == UIC_CMD_DME_SET))
6764                                 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6765                 }
6766                 retval |= IRQ_HANDLED;
6767         }
6768
6769         /* PA_INIT_ERROR is fatal and needs UIC reset */
6770         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6771         if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6772             (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6773                 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6774
6775                 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6776                         hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6777                 else if (hba->dev_quirks &
6778                                 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6779                         if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6780                                 hba->uic_error |=
6781                                         UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6782                         else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6783                                 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6784                 }
6785                 retval |= IRQ_HANDLED;
6786         }
6787
6788         /* UIC NL/TL/DME errors needs software retry */
6789         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6790         if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6791             (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6792                 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6793                 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6794                 retval |= IRQ_HANDLED;
6795         }
6796
6797         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6798         if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6799             (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6800                 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6801                 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6802                 retval |= IRQ_HANDLED;
6803         }
6804
6805         reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6806         if ((reg & UIC_DME_ERROR) &&
6807             (reg & UIC_DME_ERROR_CODE_MASK)) {
6808                 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6809                 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6810                 retval |= IRQ_HANDLED;
6811         }
6812
6813         dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6814                         __func__, hba->uic_error);
6815         return retval;
6816 }
6817
6818 /**
6819  * ufshcd_check_errors - Check for errors that need s/w attention
6820  * @hba: per-adapter instance
6821  * @intr_status: interrupt status generated by the controller
6822  *
6823  * Return:
6824  *  IRQ_HANDLED - If interrupt is valid
6825  *  IRQ_NONE    - If invalid interrupt
6826  */
6827 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6828 {
6829         bool queue_eh_work = false;
6830         irqreturn_t retval = IRQ_NONE;
6831
6832         spin_lock(hba->host->host_lock);
6833         hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6834
6835         if (hba->errors & INT_FATAL_ERRORS) {
6836                 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6837                                        hba->errors);
6838                 queue_eh_work = true;
6839         }
6840
6841         if (hba->errors & UIC_ERROR) {
6842                 hba->uic_error = 0;
6843                 retval = ufshcd_update_uic_error(hba);
6844                 if (hba->uic_error)
6845                         queue_eh_work = true;
6846         }
6847
6848         if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6849                 dev_err(hba->dev,
6850                         "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6851                         __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6852                         "Enter" : "Exit",
6853                         hba->errors, ufshcd_get_upmcrs(hba));
6854                 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6855                                        hba->errors);
6856                 ufshcd_set_link_broken(hba);
6857                 queue_eh_work = true;
6858         }
6859
6860         if (queue_eh_work) {
6861                 /*
6862                  * update the transfer error masks to sticky bits, let's do this
6863                  * irrespective of current ufshcd_state.
6864                  */
6865                 hba->saved_err |= hba->errors;
6866                 hba->saved_uic_err |= hba->uic_error;
6867
6868                 /* dump controller state before resetting */
6869                 if ((hba->saved_err &
6870                      (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6871                     (hba->saved_uic_err &&
6872                      (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6873                         dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6874                                         __func__, hba->saved_err,
6875                                         hba->saved_uic_err);
6876                         ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6877                                          "host_regs: ");
6878                         ufshcd_print_pwr_info(hba);
6879                 }
6880                 ufshcd_schedule_eh_work(hba);
6881                 retval |= IRQ_HANDLED;
6882         }
6883         /*
6884          * if (!queue_eh_work) -
6885          * Other errors are either non-fatal where host recovers
6886          * itself without s/w intervention or errors that will be
6887          * handled by the SCSI core layer.
6888          */
6889         hba->errors = 0;
6890         hba->uic_error = 0;
6891         spin_unlock(hba->host->host_lock);
6892         return retval;
6893 }
6894
6895 /**
6896  * ufshcd_tmc_handler - handle task management function completion
6897  * @hba: per adapter instance
6898  *
6899  * Return:
6900  *  IRQ_HANDLED - If interrupt is valid
6901  *  IRQ_NONE    - If invalid interrupt
6902  */
6903 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6904 {
6905         unsigned long flags, pending, issued;
6906         irqreturn_t ret = IRQ_NONE;
6907         int tag;
6908
6909         spin_lock_irqsave(hba->host->host_lock, flags);
6910         pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
6911         issued = hba->outstanding_tasks & ~pending;
6912         for_each_set_bit(tag, &issued, hba->nutmrs) {
6913                 struct request *req = hba->tmf_rqs[tag];
6914                 struct completion *c = req->end_io_data;
6915
6916                 complete(c);
6917                 ret = IRQ_HANDLED;
6918         }
6919         spin_unlock_irqrestore(hba->host->host_lock, flags);
6920
6921         return ret;
6922 }
6923
6924 /**
6925  * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events
6926  * @hba: per adapter instance
6927  *
6928  * Return: IRQ_HANDLED if interrupt is handled.
6929  */
6930 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba)
6931 {
6932         struct ufs_hw_queue *hwq;
6933         unsigned long outstanding_cqs;
6934         unsigned int nr_queues;
6935         int i, ret;
6936         u32 events;
6937
6938         ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs);
6939         if (ret)
6940                 outstanding_cqs = (1U << hba->nr_hw_queues) - 1;
6941
6942         /* Exclude the poll queues */
6943         nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL];
6944         for_each_set_bit(i, &outstanding_cqs, nr_queues) {
6945                 hwq = &hba->uhq[i];
6946
6947                 events = ufshcd_mcq_read_cqis(hba, i);
6948                 if (events)
6949                         ufshcd_mcq_write_cqis(hba, events, i);
6950
6951                 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS)
6952                         ufshcd_mcq_poll_cqe_lock(hba, hwq);
6953         }
6954
6955         return IRQ_HANDLED;
6956 }
6957
6958 /**
6959  * ufshcd_sl_intr - Interrupt service routine
6960  * @hba: per adapter instance
6961  * @intr_status: contains interrupts generated by the controller
6962  *
6963  * Return:
6964  *  IRQ_HANDLED - If interrupt is valid
6965  *  IRQ_NONE    - If invalid interrupt
6966  */
6967 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6968 {
6969         irqreturn_t retval = IRQ_NONE;
6970
6971         if (intr_status & UFSHCD_UIC_MASK)
6972                 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6973
6974         if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6975                 retval |= ufshcd_check_errors(hba, intr_status);
6976
6977         if (intr_status & UTP_TASK_REQ_COMPL)
6978                 retval |= ufshcd_tmc_handler(hba);
6979
6980         if (intr_status & UTP_TRANSFER_REQ_COMPL)
6981                 retval |= ufshcd_transfer_req_compl(hba);
6982
6983         if (intr_status & MCQ_CQ_EVENT_STATUS)
6984                 retval |= ufshcd_handle_mcq_cq_events(hba);
6985
6986         return retval;
6987 }
6988
6989 /**
6990  * ufshcd_intr - Main interrupt service routine
6991  * @irq: irq number
6992  * @__hba: pointer to adapter instance
6993  *
6994  * Return:
6995  *  IRQ_HANDLED - If interrupt is valid
6996  *  IRQ_NONE    - If invalid interrupt
6997  */
6998 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6999 {
7000         u32 intr_status, enabled_intr_status = 0;
7001         irqreturn_t retval = IRQ_NONE;
7002         struct ufs_hba *hba = __hba;
7003         int retries = hba->nutrs;
7004
7005         intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7006         hba->ufs_stats.last_intr_status = intr_status;
7007         hba->ufs_stats.last_intr_ts = local_clock();
7008
7009         /*
7010          * There could be max of hba->nutrs reqs in flight and in worst case
7011          * if the reqs get finished 1 by 1 after the interrupt status is
7012          * read, make sure we handle them by checking the interrupt status
7013          * again in a loop until we process all of the reqs before returning.
7014          */
7015         while (intr_status && retries--) {
7016                 enabled_intr_status =
7017                         intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
7018                 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
7019                 if (enabled_intr_status)
7020                         retval |= ufshcd_sl_intr(hba, enabled_intr_status);
7021
7022                 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
7023         }
7024
7025         if (enabled_intr_status && retval == IRQ_NONE &&
7026             (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
7027              hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
7028                 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
7029                                         __func__,
7030                                         intr_status,
7031                                         hba->ufs_stats.last_intr_status,
7032                                         enabled_intr_status);
7033                 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
7034         }
7035
7036         return retval;
7037 }
7038
7039 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
7040 {
7041         int err = 0;
7042         u32 mask = 1 << tag;
7043         unsigned long flags;
7044
7045         if (!test_bit(tag, &hba->outstanding_tasks))
7046                 goto out;
7047
7048         spin_lock_irqsave(hba->host->host_lock, flags);
7049         ufshcd_utmrl_clear(hba, tag);
7050         spin_unlock_irqrestore(hba->host->host_lock, flags);
7051
7052         /* poll for max. 1 sec to clear door bell register by h/w */
7053         err = ufshcd_wait_for_register(hba,
7054                         REG_UTP_TASK_REQ_DOOR_BELL,
7055                         mask, 0, 1000, 1000);
7056
7057         dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
7058                 tag, err < 0 ? "failed" : "succeeded");
7059
7060 out:
7061         return err;
7062 }
7063
7064 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
7065                 struct utp_task_req_desc *treq, u8 tm_function)
7066 {
7067         struct request_queue *q = hba->tmf_queue;
7068         struct Scsi_Host *host = hba->host;
7069         DECLARE_COMPLETION_ONSTACK(wait);
7070         struct request *req;
7071         unsigned long flags;
7072         int task_tag, err;
7073
7074         /*
7075          * blk_mq_alloc_request() is used here only to get a free tag.
7076          */
7077         req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
7078         if (IS_ERR(req))
7079                 return PTR_ERR(req);
7080
7081         req->end_io_data = &wait;
7082         ufshcd_hold(hba);
7083
7084         spin_lock_irqsave(host->host_lock, flags);
7085
7086         task_tag = req->tag;
7087         hba->tmf_rqs[req->tag] = req;
7088         treq->upiu_req.req_header.task_tag = task_tag;
7089
7090         memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
7091         ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
7092
7093         /* send command to the controller */
7094         __set_bit(task_tag, &hba->outstanding_tasks);
7095
7096         ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
7097         /* Make sure that doorbell is committed immediately */
7098         wmb();
7099
7100         spin_unlock_irqrestore(host->host_lock, flags);
7101
7102         ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
7103
7104         /* wait until the task management command is completed */
7105         err = wait_for_completion_io_timeout(&wait,
7106                         msecs_to_jiffies(TM_CMD_TIMEOUT));
7107         if (!err) {
7108                 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
7109                 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
7110                                 __func__, tm_function);
7111                 if (ufshcd_clear_tm_cmd(hba, task_tag))
7112                         dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
7113                                         __func__, task_tag);
7114                 err = -ETIMEDOUT;
7115         } else {
7116                 err = 0;
7117                 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
7118
7119                 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
7120         }
7121
7122         spin_lock_irqsave(hba->host->host_lock, flags);
7123         hba->tmf_rqs[req->tag] = NULL;
7124         __clear_bit(task_tag, &hba->outstanding_tasks);
7125         spin_unlock_irqrestore(hba->host->host_lock, flags);
7126
7127         ufshcd_release(hba);
7128         blk_mq_free_request(req);
7129
7130         return err;
7131 }
7132
7133 /**
7134  * ufshcd_issue_tm_cmd - issues task management commands to controller
7135  * @hba: per adapter instance
7136  * @lun_id: LUN ID to which TM command is sent
7137  * @task_id: task ID to which the TM command is applicable
7138  * @tm_function: task management function opcode
7139  * @tm_response: task management service response return value
7140  *
7141  * Return: non-zero value on error, zero on success.
7142  */
7143 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
7144                 u8 tm_function, u8 *tm_response)
7145 {
7146         struct utp_task_req_desc treq = { };
7147         enum utp_ocs ocs_value;
7148         int err;
7149
7150         /* Configure task request descriptor */
7151         treq.header.interrupt = 1;
7152         treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7153
7154         /* Configure task request UPIU */
7155         treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ;
7156         treq.upiu_req.req_header.lun = lun_id;
7157         treq.upiu_req.req_header.tm_function = tm_function;
7158
7159         /*
7160          * The host shall provide the same value for LUN field in the basic
7161          * header and for Input Parameter.
7162          */
7163         treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
7164         treq.upiu_req.input_param2 = cpu_to_be32(task_id);
7165
7166         err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
7167         if (err == -ETIMEDOUT)
7168                 return err;
7169
7170         ocs_value = treq.header.ocs & MASK_OCS;
7171         if (ocs_value != OCS_SUCCESS)
7172                 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
7173                                 __func__, ocs_value);
7174         else if (tm_response)
7175                 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
7176                                 MASK_TM_SERVICE_RESP;
7177         return err;
7178 }
7179
7180 /**
7181  * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
7182  * @hba:        per-adapter instance
7183  * @req_upiu:   upiu request
7184  * @rsp_upiu:   upiu reply
7185  * @desc_buff:  pointer to descriptor buffer, NULL if NA
7186  * @buff_len:   descriptor size, 0 if NA
7187  * @cmd_type:   specifies the type (NOP, Query...)
7188  * @desc_op:    descriptor operation
7189  *
7190  * Those type of requests uses UTP Transfer Request Descriptor - utrd.
7191  * Therefore, it "rides" the device management infrastructure: uses its tag and
7192  * tasks work queues.
7193  *
7194  * Since there is only one available tag for device management commands,
7195  * the caller is expected to hold the hba->dev_cmd.lock mutex.
7196  *
7197  * Return: 0 upon success; < 0 upon failure.
7198  */
7199 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
7200                                         struct utp_upiu_req *req_upiu,
7201                                         struct utp_upiu_req *rsp_upiu,
7202                                         u8 *desc_buff, int *buff_len,
7203                                         enum dev_cmd_type cmd_type,
7204                                         enum query_opcode desc_op)
7205 {
7206         DECLARE_COMPLETION_ONSTACK(wait);
7207         const u32 tag = hba->reserved_slot;
7208         struct ufshcd_lrb *lrbp;
7209         int err = 0;
7210         u8 upiu_flags;
7211
7212         /* Protects use of hba->reserved_slot. */
7213         lockdep_assert_held(&hba->dev_cmd.lock);
7214
7215         down_read(&hba->clk_scaling_lock);
7216
7217         lrbp = &hba->lrb[tag];
7218         lrbp->cmd = NULL;
7219         lrbp->task_tag = tag;
7220         lrbp->lun = 0;
7221         lrbp->intr_cmd = true;
7222         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
7223         hba->dev_cmd.type = cmd_type;
7224
7225         if (hba->ufs_version <= ufshci_version(1, 1))
7226                 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
7227         else
7228                 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
7229
7230         /* update the task tag in the request upiu */
7231         req_upiu->header.task_tag = tag;
7232
7233         ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0);
7234
7235         /* just copy the upiu request as it is */
7236         memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7237         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
7238                 /* The Data Segment Area is optional depending upon the query
7239                  * function value. for WRITE DESCRIPTOR, the data segment
7240                  * follows right after the tsf.
7241                  */
7242                 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
7243                 *buff_len = 0;
7244         }
7245
7246         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7247
7248         hba->dev_cmd.complete = &wait;
7249
7250         ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
7251
7252         ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
7253         /*
7254          * ignore the returning value here - ufshcd_check_query_response is
7255          * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
7256          * read the response directly ignoring all errors.
7257          */
7258         ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
7259
7260         /* just copy the upiu response as it is */
7261         memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7262         if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
7263                 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
7264                 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header
7265                                            .data_segment_length);
7266
7267                 if (*buff_len >= resp_len) {
7268                         memcpy(desc_buff, descp, resp_len);
7269                         *buff_len = resp_len;
7270                 } else {
7271                         dev_warn(hba->dev,
7272                                  "%s: rsp size %d is bigger than buffer size %d",
7273                                  __func__, resp_len, *buff_len);
7274                         *buff_len = 0;
7275                         err = -EINVAL;
7276                 }
7277         }
7278         ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
7279                                     (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
7280
7281         up_read(&hba->clk_scaling_lock);
7282         return err;
7283 }
7284
7285 /**
7286  * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
7287  * @hba:        per-adapter instance
7288  * @req_upiu:   upiu request
7289  * @rsp_upiu:   upiu reply - only 8 DW as we do not support scsi commands
7290  * @msgcode:    message code, one of UPIU Transaction Codes Initiator to Target
7291  * @desc_buff:  pointer to descriptor buffer, NULL if NA
7292  * @buff_len:   descriptor size, 0 if NA
7293  * @desc_op:    descriptor operation
7294  *
7295  * Supports UTP Transfer requests (nop and query), and UTP Task
7296  * Management requests.
7297  * It is up to the caller to fill the upiu conent properly, as it will
7298  * be copied without any further input validations.
7299  *
7300  * Return: 0 upon success; < 0 upon failure.
7301  */
7302 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
7303                              struct utp_upiu_req *req_upiu,
7304                              struct utp_upiu_req *rsp_upiu,
7305                              enum upiu_request_transaction msgcode,
7306                              u8 *desc_buff, int *buff_len,
7307                              enum query_opcode desc_op)
7308 {
7309         int err;
7310         enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
7311         struct utp_task_req_desc treq = { };
7312         enum utp_ocs ocs_value;
7313         u8 tm_f = req_upiu->header.tm_function;
7314
7315         switch (msgcode) {
7316         case UPIU_TRANSACTION_NOP_OUT:
7317                 cmd_type = DEV_CMD_TYPE_NOP;
7318                 fallthrough;
7319         case UPIU_TRANSACTION_QUERY_REQ:
7320                 ufshcd_hold(hba);
7321                 mutex_lock(&hba->dev_cmd.lock);
7322                 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
7323                                                    desc_buff, buff_len,
7324                                                    cmd_type, desc_op);
7325                 mutex_unlock(&hba->dev_cmd.lock);
7326                 ufshcd_release(hba);
7327
7328                 break;
7329         case UPIU_TRANSACTION_TASK_REQ:
7330                 treq.header.interrupt = 1;
7331                 treq.header.ocs = OCS_INVALID_COMMAND_STATUS;
7332
7333                 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
7334
7335                 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
7336                 if (err == -ETIMEDOUT)
7337                         break;
7338
7339                 ocs_value = treq.header.ocs & MASK_OCS;
7340                 if (ocs_value != OCS_SUCCESS) {
7341                         dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
7342                                 ocs_value);
7343                         break;
7344                 }
7345
7346                 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
7347
7348                 break;
7349         default:
7350                 err = -EINVAL;
7351
7352                 break;
7353         }
7354
7355         return err;
7356 }
7357
7358 /**
7359  * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request
7360  * @hba:        per adapter instance
7361  * @req_upiu:   upiu request
7362  * @rsp_upiu:   upiu reply
7363  * @req_ehs:    EHS field which contains Advanced RPMB Request Message
7364  * @rsp_ehs:    EHS field which returns Advanced RPMB Response Message
7365  * @sg_cnt:     The number of sg lists actually used
7366  * @sg_list:    Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation
7367  * @dir:        DMA direction
7368  *
7369  * Return: zero on success, non-zero on failure.
7370  */
7371 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
7372                          struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs,
7373                          struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list,
7374                          enum dma_data_direction dir)
7375 {
7376         DECLARE_COMPLETION_ONSTACK(wait);
7377         const u32 tag = hba->reserved_slot;
7378         struct ufshcd_lrb *lrbp;
7379         int err = 0;
7380         int result;
7381         u8 upiu_flags;
7382         u8 *ehs_data;
7383         u16 ehs_len;
7384
7385         /* Protects use of hba->reserved_slot. */
7386         ufshcd_hold(hba);
7387         mutex_lock(&hba->dev_cmd.lock);
7388         down_read(&hba->clk_scaling_lock);
7389
7390         lrbp = &hba->lrb[tag];
7391         lrbp->cmd = NULL;
7392         lrbp->task_tag = tag;
7393         lrbp->lun = UFS_UPIU_RPMB_WLUN;
7394
7395         lrbp->intr_cmd = true;
7396         ufshcd_prepare_lrbp_crypto(NULL, lrbp);
7397         hba->dev_cmd.type = DEV_CMD_TYPE_RPMB;
7398
7399         /* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */
7400         lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
7401
7402         /*
7403          * According to UFSHCI 4.0 specification page 24, if EHSLUTRDS is 0, host controller takes
7404          * EHS length from CMD UPIU, and SW driver use EHS Length field in CMD UPIU. if it is 1,
7405          * HW controller takes EHS length from UTRD.
7406          */
7407         if (hba->capabilities & MASK_EHSLUTRD_SUPPORTED)
7408                 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2);
7409         else
7410                 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 0);
7411
7412         /* update the task tag */
7413         req_upiu->header.task_tag = tag;
7414
7415         /* copy the UPIU(contains CDB) request as it is */
7416         memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
7417         /* Copy EHS, starting with byte32, immediately after the CDB package */
7418         memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs));
7419
7420         if (dir != DMA_NONE && sg_list)
7421                 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list);
7422
7423         memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
7424
7425         hba->dev_cmd.complete = &wait;
7426
7427         ufshcd_send_command(hba, tag, hba->dev_cmd_queue);
7428
7429         err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT);
7430
7431         if (!err) {
7432                 /* Just copy the upiu response as it is */
7433                 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
7434                 /* Get the response UPIU result */
7435                 result = (lrbp->ucd_rsp_ptr->header.response << 8) |
7436                         lrbp->ucd_rsp_ptr->header.status;
7437
7438                 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length;
7439                 /*
7440                  * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data
7441                  * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB
7442                  * Message is 02h
7443                  */
7444                 if (ehs_len == 2 && rsp_ehs) {
7445                         /*
7446                          * ucd_rsp_ptr points to a buffer with a length of 512 bytes
7447                          * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32
7448                          */
7449                         ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE;
7450                         memcpy(rsp_ehs, ehs_data, ehs_len * 32);
7451                 }
7452         }
7453
7454         up_read(&hba->clk_scaling_lock);
7455         mutex_unlock(&hba->dev_cmd.lock);
7456         ufshcd_release(hba);
7457         return err ? : result;
7458 }
7459
7460 /**
7461  * ufshcd_eh_device_reset_handler() - Reset a single logical unit.
7462  * @cmd: SCSI command pointer
7463  *
7464  * Return: SUCCESS or FAILED.
7465  */
7466 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7467 {
7468         unsigned long flags, pending_reqs = 0, not_cleared = 0;
7469         struct Scsi_Host *host;
7470         struct ufs_hba *hba;
7471         struct ufs_hw_queue *hwq;
7472         struct ufshcd_lrb *lrbp;
7473         u32 pos, not_cleared_mask = 0;
7474         int err;
7475         u8 resp = 0xF, lun;
7476
7477         host = cmd->device->host;
7478         hba = shost_priv(host);
7479
7480         lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
7481         err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
7482         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7483                 if (!err)
7484                         err = resp;
7485                 goto out;
7486         }
7487
7488         if (is_mcq_enabled(hba)) {
7489                 for (pos = 0; pos < hba->nutrs; pos++) {
7490                         lrbp = &hba->lrb[pos];
7491                         if (ufshcd_cmd_inflight(lrbp->cmd) &&
7492                             lrbp->lun == lun) {
7493                                 ufshcd_clear_cmd(hba, pos);
7494                                 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd));
7495                                 ufshcd_mcq_poll_cqe_lock(hba, hwq);
7496                         }
7497                 }
7498                 err = 0;
7499                 goto out;
7500         }
7501
7502         /* clear the commands that were pending for corresponding LUN */
7503         spin_lock_irqsave(&hba->outstanding_lock, flags);
7504         for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs)
7505                 if (hba->lrb[pos].lun == lun)
7506                         __set_bit(pos, &pending_reqs);
7507         hba->outstanding_reqs &= ~pending_reqs;
7508         spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7509
7510         for_each_set_bit(pos, &pending_reqs, hba->nutrs) {
7511                 if (ufshcd_clear_cmd(hba, pos) < 0) {
7512                         spin_lock_irqsave(&hba->outstanding_lock, flags);
7513                         not_cleared = 1U << pos &
7514                                 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7515                         hba->outstanding_reqs |= not_cleared;
7516                         not_cleared_mask |= not_cleared;
7517                         spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7518
7519                         dev_err(hba->dev, "%s: failed to clear request %d\n",
7520                                 __func__, pos);
7521                 }
7522         }
7523         __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask);
7524
7525 out:
7526         hba->req_abort_count = 0;
7527         ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
7528         if (!err) {
7529                 err = SUCCESS;
7530         } else {
7531                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7532                 err = FAILED;
7533         }
7534         return err;
7535 }
7536
7537 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7538 {
7539         struct ufshcd_lrb *lrbp;
7540         int tag;
7541
7542         for_each_set_bit(tag, &bitmap, hba->nutrs) {
7543                 lrbp = &hba->lrb[tag];
7544                 lrbp->req_abort_skip = true;
7545         }
7546 }
7547
7548 /**
7549  * ufshcd_try_to_abort_task - abort a specific task
7550  * @hba: Pointer to adapter instance
7551  * @tag: Task tag/index to be aborted
7552  *
7553  * Abort the pending command in device by sending UFS_ABORT_TASK task management
7554  * command, and in host controller by clearing the door-bell register. There can
7555  * be race between controller sending the command to the device while abort is
7556  * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7557  * really issued and then try to abort it.
7558  *
7559  * Return: zero on success, non-zero on failure.
7560  */
7561 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7562 {
7563         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7564         int err = 0;
7565         int poll_cnt;
7566         u8 resp = 0xF;
7567         u32 reg;
7568
7569         for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7570                 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7571                                 UFS_QUERY_TASK, &resp);
7572                 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7573                         /* cmd pending in the device */
7574                         dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7575                                 __func__, tag);
7576                         break;
7577                 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7578                         /*
7579                          * cmd not pending in the device, check if it is
7580                          * in transition.
7581                          */
7582                         dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
7583                                 __func__, tag);
7584                         if (is_mcq_enabled(hba)) {
7585                                 /* MCQ mode */
7586                                 if (ufshcd_cmd_inflight(lrbp->cmd)) {
7587                                         /* sleep for max. 200us same delay as in SDB mode */
7588                                         usleep_range(100, 200);
7589                                         continue;
7590                                 }
7591                                 /* command completed already */
7592                                 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n",
7593                                         __func__, tag);
7594                                 goto out;
7595                         }
7596
7597                         /* Single Doorbell Mode */
7598                         reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7599                         if (reg & (1 << tag)) {
7600                                 /* sleep for max. 200us to stabilize */
7601                                 usleep_range(100, 200);
7602                                 continue;
7603                         }
7604                         /* command completed already */
7605                         dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
7606                                 __func__, tag);
7607                         goto out;
7608                 } else {
7609                         dev_err(hba->dev,
7610                                 "%s: no response from device. tag = %d, err %d\n",
7611                                 __func__, tag, err);
7612                         if (!err)
7613                                 err = resp; /* service response error */
7614                         goto out;
7615                 }
7616         }
7617
7618         if (!poll_cnt) {
7619                 err = -EBUSY;
7620                 goto out;
7621         }
7622
7623         err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7624                         UFS_ABORT_TASK, &resp);
7625         if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7626                 if (!err) {
7627                         err = resp; /* service response error */
7628                         dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7629                                 __func__, tag, err);
7630                 }
7631                 goto out;
7632         }
7633
7634         err = ufshcd_clear_cmd(hba, tag);
7635         if (err)
7636                 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7637                         __func__, tag, err);
7638
7639 out:
7640         return err;
7641 }
7642
7643 /**
7644  * ufshcd_abort - scsi host template eh_abort_handler callback
7645  * @cmd: SCSI command pointer
7646  *
7647  * Return: SUCCESS or FAILED.
7648  */
7649 static int ufshcd_abort(struct scsi_cmnd *cmd)
7650 {
7651         struct Scsi_Host *host = cmd->device->host;
7652         struct ufs_hba *hba = shost_priv(host);
7653         int tag = scsi_cmd_to_rq(cmd)->tag;
7654         struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7655         unsigned long flags;
7656         int err = FAILED;
7657         bool outstanding;
7658         u32 reg;
7659
7660         ufshcd_hold(hba);
7661
7662         if (!is_mcq_enabled(hba)) {
7663                 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7664                 if (!test_bit(tag, &hba->outstanding_reqs)) {
7665                         /* If command is already aborted/completed, return FAILED. */
7666                         dev_err(hba->dev,
7667                                 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7668                                 __func__, tag, hba->outstanding_reqs, reg);
7669                         goto release;
7670                 }
7671         }
7672
7673         /* Print Transfer Request of aborted task */
7674         dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
7675
7676         /*
7677          * Print detailed info about aborted request.
7678          * As more than one request might get aborted at the same time,
7679          * print full information only for the first aborted request in order
7680          * to reduce repeated printouts. For other aborted requests only print
7681          * basic details.
7682          */
7683         scsi_print_command(cmd);
7684         if (!hba->req_abort_count) {
7685                 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7686                 ufshcd_print_evt_hist(hba);
7687                 ufshcd_print_host_state(hba);
7688                 ufshcd_print_pwr_info(hba);
7689                 ufshcd_print_tr(hba, tag, true);
7690         } else {
7691                 ufshcd_print_tr(hba, tag, false);
7692         }
7693         hba->req_abort_count++;
7694
7695         if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) {
7696                 /* only execute this code in single doorbell mode */
7697                 dev_err(hba->dev,
7698                 "%s: cmd was completed, but without a notifying intr, tag = %d",
7699                 __func__, tag);
7700                 __ufshcd_transfer_req_compl(hba, 1UL << tag);
7701                 goto release;
7702         }
7703
7704         /*
7705          * Task abort to the device W-LUN is illegal. When this command
7706          * will fail, due to spec violation, scsi err handling next step
7707          * will be to send LU reset which, again, is a spec violation.
7708          * To avoid these unnecessary/illegal steps, first we clean up
7709          * the lrb taken by this cmd and re-set it in outstanding_reqs,
7710          * then queue the eh_work and bail.
7711          */
7712         if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7713                 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7714
7715                 spin_lock_irqsave(host->host_lock, flags);
7716                 hba->force_reset = true;
7717                 ufshcd_schedule_eh_work(hba);
7718                 spin_unlock_irqrestore(host->host_lock, flags);
7719                 goto release;
7720         }
7721
7722         if (is_mcq_enabled(hba)) {
7723                 /* MCQ mode. Branch off to handle abort for mcq mode */
7724                 err = ufshcd_mcq_abort(cmd);
7725                 goto release;
7726         }
7727
7728         /* Skip task abort in case previous aborts failed and report failure */
7729         if (lrbp->req_abort_skip) {
7730                 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7731                 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7732                 goto release;
7733         }
7734
7735         err = ufshcd_try_to_abort_task(hba, tag);
7736         if (err) {
7737                 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7738                 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7739                 err = FAILED;
7740                 goto release;
7741         }
7742
7743         /*
7744          * Clear the corresponding bit from outstanding_reqs since the command
7745          * has been aborted successfully.
7746          */
7747         spin_lock_irqsave(&hba->outstanding_lock, flags);
7748         outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7749         spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7750
7751         if (outstanding)
7752                 ufshcd_release_scsi_cmd(hba, lrbp);
7753
7754         err = SUCCESS;
7755
7756 release:
7757         /* Matches the ufshcd_hold() call at the start of this function. */
7758         ufshcd_release(hba);
7759         return err;
7760 }
7761
7762 /**
7763  * ufshcd_host_reset_and_restore - reset and restore host controller
7764  * @hba: per-adapter instance
7765  *
7766  * Note that host controller reset may issue DME_RESET to
7767  * local and remote (device) Uni-Pro stack and the attributes
7768  * are reset to default state.
7769  *
7770  * Return: zero on success, non-zero on failure.
7771  */
7772 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7773 {
7774         int err;
7775
7776         /*
7777          * Stop the host controller and complete the requests
7778          * cleared by h/w
7779          */
7780         ufshcd_hba_stop(hba);
7781         hba->silence_err_logs = true;
7782         ufshcd_complete_requests(hba, true);
7783         hba->silence_err_logs = false;
7784
7785         /* scale up clocks to max frequency before full reinitialization */
7786         ufshcd_scale_clks(hba, ULONG_MAX, true);
7787
7788         err = ufshcd_hba_enable(hba);
7789
7790         /* Establish the link again and restore the device */
7791         if (!err)
7792                 err = ufshcd_probe_hba(hba, false);
7793
7794         if (err)
7795                 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7796         ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7797         return err;
7798 }
7799
7800 /**
7801  * ufshcd_reset_and_restore - reset and re-initialize host/device
7802  * @hba: per-adapter instance
7803  *
7804  * Reset and recover device, host and re-establish link. This
7805  * is helpful to recover the communication in fatal error conditions.
7806  *
7807  * Return: zero on success, non-zero on failure.
7808  */
7809 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7810 {
7811         u32 saved_err = 0;
7812         u32 saved_uic_err = 0;
7813         int err = 0;
7814         unsigned long flags;
7815         int retries = MAX_HOST_RESET_RETRIES;
7816
7817         spin_lock_irqsave(hba->host->host_lock, flags);
7818         do {
7819                 /*
7820                  * This is a fresh start, cache and clear saved error first,
7821                  * in case new error generated during reset and restore.
7822                  */
7823                 saved_err |= hba->saved_err;
7824                 saved_uic_err |= hba->saved_uic_err;
7825                 hba->saved_err = 0;
7826                 hba->saved_uic_err = 0;
7827                 hba->force_reset = false;
7828                 hba->ufshcd_state = UFSHCD_STATE_RESET;
7829                 spin_unlock_irqrestore(hba->host->host_lock, flags);
7830
7831                 /* Reset the attached device */
7832                 ufshcd_device_reset(hba);
7833
7834                 err = ufshcd_host_reset_and_restore(hba);
7835
7836                 spin_lock_irqsave(hba->host->host_lock, flags);
7837                 if (err)
7838                         continue;
7839                 /* Do not exit unless operational or dead */
7840                 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
7841                     hba->ufshcd_state != UFSHCD_STATE_ERROR &&
7842                     hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
7843                         err = -EAGAIN;
7844         } while (err && --retries);
7845
7846         /*
7847          * Inform scsi mid-layer that we did reset and allow to handle
7848          * Unit Attention properly.
7849          */
7850         scsi_report_bus_reset(hba->host, 0);
7851         if (err) {
7852                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
7853                 hba->saved_err |= saved_err;
7854                 hba->saved_uic_err |= saved_uic_err;
7855         }
7856         spin_unlock_irqrestore(hba->host->host_lock, flags);
7857
7858         return err;
7859 }
7860
7861 /**
7862  * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
7863  * @cmd: SCSI command pointer
7864  *
7865  * Return: SUCCESS or FAILED.
7866  */
7867 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7868 {
7869         int err = SUCCESS;
7870         unsigned long flags;
7871         struct ufs_hba *hba;
7872
7873         hba = shost_priv(cmd->device->host);
7874
7875         /*
7876          * If runtime PM sent SSU and got a timeout, scsi_error_handler is
7877          * stuck in this function waiting for flush_work(&hba->eh_work). And
7878          * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do
7879          * ufshcd_link_recovery instead of eh_work to prevent deadlock.
7880          */
7881         if (hba->pm_op_in_progress) {
7882                 if (ufshcd_link_recovery(hba))
7883                         err = FAILED;
7884
7885                 return err;
7886         }
7887
7888         spin_lock_irqsave(hba->host->host_lock, flags);
7889         hba->force_reset = true;
7890         ufshcd_schedule_eh_work(hba);
7891         dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7892         spin_unlock_irqrestore(hba->host->host_lock, flags);
7893
7894         flush_work(&hba->eh_work);
7895
7896         spin_lock_irqsave(hba->host->host_lock, flags);
7897         if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7898                 err = FAILED;
7899         spin_unlock_irqrestore(hba->host->host_lock, flags);
7900
7901         return err;
7902 }
7903
7904 /**
7905  * ufshcd_get_max_icc_level - calculate the ICC level
7906  * @sup_curr_uA: max. current supported by the regulator
7907  * @start_scan: row at the desc table to start scan from
7908  * @buff: power descriptor buffer
7909  *
7910  * Return: calculated max ICC level for specific regulator.
7911  */
7912 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan,
7913                                     const char *buff)
7914 {
7915         int i;
7916         int curr_uA;
7917         u16 data;
7918         u16 unit;
7919
7920         for (i = start_scan; i >= 0; i--) {
7921                 data = get_unaligned_be16(&buff[2 * i]);
7922                 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7923                                                 ATTR_ICC_LVL_UNIT_OFFSET;
7924                 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7925                 switch (unit) {
7926                 case UFSHCD_NANO_AMP:
7927                         curr_uA = curr_uA / 1000;
7928                         break;
7929                 case UFSHCD_MILI_AMP:
7930                         curr_uA = curr_uA * 1000;
7931                         break;
7932                 case UFSHCD_AMP:
7933                         curr_uA = curr_uA * 1000 * 1000;
7934                         break;
7935                 case UFSHCD_MICRO_AMP:
7936                 default:
7937                         break;
7938                 }
7939                 if (sup_curr_uA >= curr_uA)
7940                         break;
7941         }
7942         if (i < 0) {
7943                 i = 0;
7944                 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7945         }
7946
7947         return (u32)i;
7948 }
7949
7950 /**
7951  * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
7952  * In case regulators are not initialized we'll return 0
7953  * @hba: per-adapter instance
7954  * @desc_buf: power descriptor buffer to extract ICC levels from.
7955  *
7956  * Return: calculated ICC level.
7957  */
7958 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7959                                                 const u8 *desc_buf)
7960 {
7961         u32 icc_level = 0;
7962
7963         if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7964                                                 !hba->vreg_info.vccq2) {
7965                 /*
7966                  * Using dev_dbg to avoid messages during runtime PM to avoid
7967                  * never-ending cycles of messages written back to storage by
7968                  * user space causing runtime resume, causing more messages and
7969                  * so on.
7970                  */
7971                 dev_dbg(hba->dev,
7972                         "%s: Regulator capability was not set, actvIccLevel=%d",
7973                                                         __func__, icc_level);
7974                 goto out;
7975         }
7976
7977         if (hba->vreg_info.vcc->max_uA)
7978                 icc_level = ufshcd_get_max_icc_level(
7979                                 hba->vreg_info.vcc->max_uA,
7980                                 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7981                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7982
7983         if (hba->vreg_info.vccq->max_uA)
7984                 icc_level = ufshcd_get_max_icc_level(
7985                                 hba->vreg_info.vccq->max_uA,
7986                                 icc_level,
7987                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7988
7989         if (hba->vreg_info.vccq2->max_uA)
7990                 icc_level = ufshcd_get_max_icc_level(
7991                                 hba->vreg_info.vccq2->max_uA,
7992                                 icc_level,
7993                                 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7994 out:
7995         return icc_level;
7996 }
7997
7998 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7999 {
8000         int ret;
8001         u8 *desc_buf;
8002         u32 icc_level;
8003
8004         desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8005         if (!desc_buf)
8006                 return;
8007
8008         ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
8009                                      desc_buf, QUERY_DESC_MAX_SIZE);
8010         if (ret) {
8011                 dev_err(hba->dev,
8012                         "%s: Failed reading power descriptor ret = %d",
8013                         __func__, ret);
8014                 goto out;
8015         }
8016
8017         icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf);
8018         dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
8019
8020         ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8021                 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
8022
8023         if (ret)
8024                 dev_err(hba->dev,
8025                         "%s: Failed configuring bActiveICCLevel = %d ret = %d",
8026                         __func__, icc_level, ret);
8027
8028 out:
8029         kfree(desc_buf);
8030 }
8031
8032 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
8033 {
8034         struct Scsi_Host *shost = sdev->host;
8035
8036         scsi_autopm_get_device(sdev);
8037         blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
8038         if (sdev->rpm_autosuspend)
8039                 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
8040                                                  shost->rpm_autosuspend_delay);
8041         scsi_autopm_put_device(sdev);
8042 }
8043
8044 /**
8045  * ufshcd_scsi_add_wlus - Adds required W-LUs
8046  * @hba: per-adapter instance
8047  *
8048  * UFS device specification requires the UFS devices to support 4 well known
8049  * logical units:
8050  *      "REPORT_LUNS" (address: 01h)
8051  *      "UFS Device" (address: 50h)
8052  *      "RPMB" (address: 44h)
8053  *      "BOOT" (address: 30h)
8054  * UFS device's power management needs to be controlled by "POWER CONDITION"
8055  * field of SSU (START STOP UNIT) command. But this "power condition" field
8056  * will take effect only when its sent to "UFS device" well known logical unit
8057  * hence we require the scsi_device instance to represent this logical unit in
8058  * order for the UFS host driver to send the SSU command for power management.
8059  *
8060  * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
8061  * Block) LU so user space process can control this LU. User space may also
8062  * want to have access to BOOT LU.
8063  *
8064  * This function adds scsi device instances for each of all well known LUs
8065  * (except "REPORT LUNS" LU).
8066  *
8067  * Return: zero on success (all required W-LUs are added successfully),
8068  * non-zero error value on failure (if failed to add any of the required W-LU).
8069  */
8070 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
8071 {
8072         int ret = 0;
8073         struct scsi_device *sdev_boot, *sdev_rpmb;
8074
8075         hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0,
8076                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
8077         if (IS_ERR(hba->ufs_device_wlun)) {
8078                 ret = PTR_ERR(hba->ufs_device_wlun);
8079                 hba->ufs_device_wlun = NULL;
8080                 goto out;
8081         }
8082         scsi_device_put(hba->ufs_device_wlun);
8083
8084         sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
8085                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
8086         if (IS_ERR(sdev_rpmb)) {
8087                 ret = PTR_ERR(sdev_rpmb);
8088                 goto remove_ufs_device_wlun;
8089         }
8090         ufshcd_blk_pm_runtime_init(sdev_rpmb);
8091         scsi_device_put(sdev_rpmb);
8092
8093         sdev_boot = __scsi_add_device(hba->host, 0, 0,
8094                 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
8095         if (IS_ERR(sdev_boot)) {
8096                 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
8097         } else {
8098                 ufshcd_blk_pm_runtime_init(sdev_boot);
8099                 scsi_device_put(sdev_boot);
8100         }
8101         goto out;
8102
8103 remove_ufs_device_wlun:
8104         scsi_remove_device(hba->ufs_device_wlun);
8105 out:
8106         return ret;
8107 }
8108
8109 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf)
8110 {
8111         struct ufs_dev_info *dev_info = &hba->dev_info;
8112         u8 lun;
8113         u32 d_lu_wb_buf_alloc;
8114         u32 ext_ufs_feature;
8115
8116         if (!ufshcd_is_wb_allowed(hba))
8117                 return;
8118
8119         /*
8120          * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
8121          * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
8122          * enabled
8123          */
8124         if (!(dev_info->wspecversion >= 0x310 ||
8125               dev_info->wspecversion == 0x220 ||
8126              (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
8127                 goto wb_disabled;
8128
8129         ext_ufs_feature = get_unaligned_be32(desc_buf +
8130                                         DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8131
8132         if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
8133                 goto wb_disabled;
8134
8135         /*
8136          * WB may be supported but not configured while provisioning. The spec
8137          * says, in dedicated wb buffer mode, a max of 1 lun would have wb
8138          * buffer configured.
8139          */
8140         dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
8141
8142         dev_info->b_presrv_uspc_en =
8143                 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
8144
8145         if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
8146                 if (!get_unaligned_be32(desc_buf +
8147                                    DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
8148                         goto wb_disabled;
8149         } else {
8150                 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
8151                         d_lu_wb_buf_alloc = 0;
8152                         ufshcd_read_unit_desc_param(hba,
8153                                         lun,
8154                                         UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
8155                                         (u8 *)&d_lu_wb_buf_alloc,
8156                                         sizeof(d_lu_wb_buf_alloc));
8157                         if (d_lu_wb_buf_alloc) {
8158                                 dev_info->wb_dedicated_lu = lun;
8159                                 break;
8160                         }
8161                 }
8162
8163                 if (!d_lu_wb_buf_alloc)
8164                         goto wb_disabled;
8165         }
8166
8167         if (!ufshcd_is_wb_buf_lifetime_available(hba))
8168                 goto wb_disabled;
8169
8170         return;
8171
8172 wb_disabled:
8173         hba->caps &= ~UFSHCD_CAP_WB_EN;
8174 }
8175
8176 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf)
8177 {
8178         struct ufs_dev_info *dev_info = &hba->dev_info;
8179         u32 ext_ufs_feature;
8180         u8 mask = 0;
8181
8182         if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
8183                 return;
8184
8185         ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8186
8187         if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
8188                 mask |= MASK_EE_TOO_LOW_TEMP;
8189
8190         if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
8191                 mask |= MASK_EE_TOO_HIGH_TEMP;
8192
8193         if (mask) {
8194                 ufshcd_enable_ee(hba, mask);
8195                 ufs_hwmon_probe(hba, mask);
8196         }
8197 }
8198
8199 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf)
8200 {
8201         struct ufs_dev_info *dev_info = &hba->dev_info;
8202         u32 ext_ufs_feature;
8203         u32 ext_iid_en = 0;
8204         int err;
8205
8206         /* Only UFS-4.0 and above may support EXT_IID */
8207         if (dev_info->wspecversion < 0x400)
8208                 goto out;
8209
8210         ext_ufs_feature = get_unaligned_be32(desc_buf +
8211                                      DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
8212         if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP))
8213                 goto out;
8214
8215         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8216                                       QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en);
8217         if (err)
8218                 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err);
8219
8220 out:
8221         dev_info->b_ext_iid_en = ext_iid_en;
8222 }
8223
8224 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
8225                              const struct ufs_dev_quirk *fixups)
8226 {
8227         const struct ufs_dev_quirk *f;
8228         struct ufs_dev_info *dev_info = &hba->dev_info;
8229
8230         if (!fixups)
8231                 return;
8232
8233         for (f = fixups; f->quirk; f++) {
8234                 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
8235                      f->wmanufacturerid == UFS_ANY_VENDOR) &&
8236                      ((dev_info->model &&
8237                        STR_PRFX_EQUAL(f->model, dev_info->model)) ||
8238                       !strcmp(f->model, UFS_ANY_MODEL)))
8239                         hba->dev_quirks |= f->quirk;
8240         }
8241 }
8242 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
8243
8244 static void ufs_fixup_device_setup(struct ufs_hba *hba)
8245 {
8246         /* fix by general quirk table */
8247         ufshcd_fixup_dev_quirks(hba, ufs_fixups);
8248
8249         /* allow vendors to fix quirks */
8250         ufshcd_vops_fixup_dev_quirks(hba);
8251 }
8252
8253 static void ufshcd_update_rtc(struct ufs_hba *hba)
8254 {
8255         struct timespec64 ts64;
8256         int err;
8257         u32 val;
8258
8259         ktime_get_real_ts64(&ts64);
8260
8261         if (ts64.tv_sec < hba->dev_info.rtc_time_baseline) {
8262                 dev_warn_once(hba->dev, "%s: Current time precedes previous setting!\n", __func__);
8263                 return;
8264         }
8265
8266         /*
8267          * The Absolute RTC mode has a 136-year limit, spanning from 2010 to 2146. If a time beyond
8268          * 2146 is required, it is recommended to choose the relative RTC mode.
8269          */
8270         val = ts64.tv_sec - hba->dev_info.rtc_time_baseline;
8271
8272         ufshcd_rpm_get_sync(hba);
8273         err = ufshcd_query_attr(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, QUERY_ATTR_IDN_SECONDS_PASSED,
8274                                 0, 0, &val);
8275         ufshcd_rpm_put_sync(hba);
8276
8277         if (err)
8278                 dev_err(hba->dev, "%s: Failed to update rtc %d\n", __func__, err);
8279         else if (hba->dev_info.rtc_type == UFS_RTC_RELATIVE)
8280                 hba->dev_info.rtc_time_baseline = ts64.tv_sec;
8281 }
8282
8283 static void ufshcd_rtc_work(struct work_struct *work)
8284 {
8285         struct ufs_hba *hba;
8286
8287         hba = container_of(to_delayed_work(work), struct ufs_hba, ufs_rtc_update_work);
8288
8289          /* Update RTC only when there are no requests in progress and UFSHCI is operational */
8290         if (!ufshcd_is_ufs_dev_busy(hba) && hba->ufshcd_state == UFSHCD_STATE_OPERATIONAL)
8291                 ufshcd_update_rtc(hba);
8292
8293         if (ufshcd_is_ufs_dev_active(hba) && hba->dev_info.rtc_update_period)
8294                 schedule_delayed_work(&hba->ufs_rtc_update_work,
8295                                       msecs_to_jiffies(hba->dev_info.rtc_update_period));
8296 }
8297
8298 static void ufs_init_rtc(struct ufs_hba *hba, u8 *desc_buf)
8299 {
8300         u16 periodic_rtc_update = get_unaligned_be16(&desc_buf[DEVICE_DESC_PARAM_FRQ_RTC]);
8301         struct ufs_dev_info *dev_info = &hba->dev_info;
8302
8303         if (periodic_rtc_update & UFS_RTC_TIME_BASELINE) {
8304                 dev_info->rtc_type = UFS_RTC_ABSOLUTE;
8305
8306                 /*
8307                  * The concept of measuring time in Linux as the number of seconds elapsed since
8308                  * 00:00:00 UTC on January 1, 1970, and UFS ABS RTC is elapsed from January 1st
8309                  * 2010 00:00, here we need to adjust ABS baseline.
8310                  */
8311                 dev_info->rtc_time_baseline = mktime64(2010, 1, 1, 0, 0, 0) -
8312                                                         mktime64(1970, 1, 1, 0, 0, 0);
8313         } else {
8314                 dev_info->rtc_type = UFS_RTC_RELATIVE;
8315                 dev_info->rtc_time_baseline = 0;
8316         }
8317
8318         /*
8319          * We ignore TIME_PERIOD defined in wPeriodicRTCUpdate because Spec does not clearly state
8320          * how to calculate the specific update period for each time unit. And we disable periodic
8321          * RTC update work, let user configure by sysfs node according to specific circumstance.
8322          */
8323         dev_info->rtc_update_period = 0;
8324 }
8325
8326 static int ufs_get_device_desc(struct ufs_hba *hba)
8327 {
8328         int err;
8329         u8 model_index;
8330         u8 *desc_buf;
8331         struct ufs_dev_info *dev_info = &hba->dev_info;
8332
8333         desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8334         if (!desc_buf) {
8335                 err = -ENOMEM;
8336                 goto out;
8337         }
8338
8339         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
8340                                      QUERY_DESC_MAX_SIZE);
8341         if (err) {
8342                 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
8343                         __func__, err);
8344                 goto out;
8345         }
8346
8347         /*
8348          * getting vendor (manufacturerID) and Bank Index in big endian
8349          * format
8350          */
8351         dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
8352                                      desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
8353
8354         /* getting Specification Version in big endian format */
8355         dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
8356                                       desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
8357         dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH];
8358
8359         model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
8360
8361         err = ufshcd_read_string_desc(hba, model_index,
8362                                       &dev_info->model, SD_ASCII_STD);
8363         if (err < 0) {
8364                 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
8365                         __func__, err);
8366                 goto out;
8367         }
8368
8369         hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
8370                 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
8371
8372         ufs_fixup_device_setup(hba);
8373
8374         ufshcd_wb_probe(hba, desc_buf);
8375
8376         ufshcd_temp_notif_probe(hba, desc_buf);
8377
8378         ufs_init_rtc(hba, desc_buf);
8379
8380         if (hba->ext_iid_sup)
8381                 ufshcd_ext_iid_probe(hba, desc_buf);
8382
8383         /*
8384          * ufshcd_read_string_desc returns size of the string
8385          * reset the error value
8386          */
8387         err = 0;
8388
8389 out:
8390         kfree(desc_buf);
8391         return err;
8392 }
8393
8394 static void ufs_put_device_desc(struct ufs_hba *hba)
8395 {
8396         struct ufs_dev_info *dev_info = &hba->dev_info;
8397
8398         kfree(dev_info->model);
8399         dev_info->model = NULL;
8400 }
8401
8402 /**
8403  * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
8404  * @hba: per-adapter instance
8405  *
8406  * PA_TActivate parameter can be tuned manually if UniPro version is less than
8407  * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
8408  * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
8409  * the hibern8 exit latency.
8410  *
8411  * Return: zero on success, non-zero error value on failure.
8412  */
8413 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
8414 {
8415         int ret = 0;
8416         u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
8417
8418         ret = ufshcd_dme_peer_get(hba,
8419                                   UIC_ARG_MIB_SEL(
8420                                         RX_MIN_ACTIVATETIME_CAPABILITY,
8421                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
8422                                   &peer_rx_min_activatetime);
8423         if (ret)
8424                 goto out;
8425
8426         /* make sure proper unit conversion is applied */
8427         tuned_pa_tactivate =
8428                 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
8429                  / PA_TACTIVATE_TIME_UNIT_US);
8430         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8431                              tuned_pa_tactivate);
8432
8433 out:
8434         return ret;
8435 }
8436
8437 /**
8438  * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
8439  * @hba: per-adapter instance
8440  *
8441  * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
8442  * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
8443  * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
8444  * This optimal value can help reduce the hibern8 exit latency.
8445  *
8446  * Return: zero on success, non-zero error value on failure.
8447  */
8448 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
8449 {
8450         int ret = 0;
8451         u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
8452         u32 max_hibern8_time, tuned_pa_hibern8time;
8453
8454         ret = ufshcd_dme_get(hba,
8455                              UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
8456                                         UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
8457                                   &local_tx_hibern8_time_cap);
8458         if (ret)
8459                 goto out;
8460
8461         ret = ufshcd_dme_peer_get(hba,
8462                                   UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
8463                                         UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
8464                                   &peer_rx_hibern8_time_cap);
8465         if (ret)
8466                 goto out;
8467
8468         max_hibern8_time = max(local_tx_hibern8_time_cap,
8469                                peer_rx_hibern8_time_cap);
8470         /* make sure proper unit conversion is applied */
8471         tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
8472                                 / PA_HIBERN8_TIME_UNIT_US);
8473         ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
8474                              tuned_pa_hibern8time);
8475 out:
8476         return ret;
8477 }
8478
8479 /**
8480  * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
8481  * less than device PA_TACTIVATE time.
8482  * @hba: per-adapter instance
8483  *
8484  * Some UFS devices require host PA_TACTIVATE to be lower than device
8485  * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
8486  * for such devices.
8487  *
8488  * Return: zero on success, non-zero error value on failure.
8489  */
8490 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
8491 {
8492         int ret = 0;
8493         u32 granularity, peer_granularity;
8494         u32 pa_tactivate, peer_pa_tactivate;
8495         u32 pa_tactivate_us, peer_pa_tactivate_us;
8496         static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
8497
8498         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8499                                   &granularity);
8500         if (ret)
8501                 goto out;
8502
8503         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
8504                                   &peer_granularity);
8505         if (ret)
8506                 goto out;
8507
8508         if ((granularity < PA_GRANULARITY_MIN_VAL) ||
8509             (granularity > PA_GRANULARITY_MAX_VAL)) {
8510                 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
8511                         __func__, granularity);
8512                 return -EINVAL;
8513         }
8514
8515         if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
8516             (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
8517                 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
8518                         __func__, peer_granularity);
8519                 return -EINVAL;
8520         }
8521
8522         ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
8523         if (ret)
8524                 goto out;
8525
8526         ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
8527                                   &peer_pa_tactivate);
8528         if (ret)
8529                 goto out;
8530
8531         pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
8532         peer_pa_tactivate_us = peer_pa_tactivate *
8533                              gran_to_us_table[peer_granularity - 1];
8534
8535         if (pa_tactivate_us >= peer_pa_tactivate_us) {
8536                 u32 new_peer_pa_tactivate;
8537
8538                 new_peer_pa_tactivate = pa_tactivate_us /
8539                                       gran_to_us_table[peer_granularity - 1];
8540                 new_peer_pa_tactivate++;
8541                 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
8542                                           new_peer_pa_tactivate);
8543         }
8544
8545 out:
8546         return ret;
8547 }
8548
8549 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
8550 {
8551         if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
8552                 ufshcd_tune_pa_tactivate(hba);
8553                 ufshcd_tune_pa_hibern8time(hba);
8554         }
8555
8556         ufshcd_vops_apply_dev_quirks(hba);
8557
8558         if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
8559                 /* set 1ms timeout for PA_TACTIVATE */
8560                 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
8561
8562         if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
8563                 ufshcd_quirk_tune_host_pa_tactivate(hba);
8564 }
8565
8566 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
8567 {
8568         hba->ufs_stats.hibern8_exit_cnt = 0;
8569         hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
8570         hba->req_abort_count = 0;
8571 }
8572
8573 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
8574 {
8575         int err;
8576         u8 *desc_buf;
8577
8578         desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
8579         if (!desc_buf) {
8580                 err = -ENOMEM;
8581                 goto out;
8582         }
8583
8584         err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
8585                                      desc_buf, QUERY_DESC_MAX_SIZE);
8586         if (err) {
8587                 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
8588                                 __func__, err);
8589                 goto out;
8590         }
8591
8592         if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
8593                 hba->dev_info.max_lu_supported = 32;
8594         else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
8595                 hba->dev_info.max_lu_supported = 8;
8596
8597 out:
8598         kfree(desc_buf);
8599         return err;
8600 }
8601
8602 struct ufs_ref_clk {
8603         unsigned long freq_hz;
8604         enum ufs_ref_clk_freq val;
8605 };
8606
8607 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = {
8608         {19200000, REF_CLK_FREQ_19_2_MHZ},
8609         {26000000, REF_CLK_FREQ_26_MHZ},
8610         {38400000, REF_CLK_FREQ_38_4_MHZ},
8611         {52000000, REF_CLK_FREQ_52_MHZ},
8612         {0, REF_CLK_FREQ_INVAL},
8613 };
8614
8615 static enum ufs_ref_clk_freq
8616 ufs_get_bref_clk_from_hz(unsigned long freq)
8617 {
8618         int i;
8619
8620         for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
8621                 if (ufs_ref_clk_freqs[i].freq_hz == freq)
8622                         return ufs_ref_clk_freqs[i].val;
8623
8624         return REF_CLK_FREQ_INVAL;
8625 }
8626
8627 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
8628 {
8629         unsigned long freq;
8630
8631         freq = clk_get_rate(refclk);
8632
8633         hba->dev_ref_clk_freq =
8634                 ufs_get_bref_clk_from_hz(freq);
8635
8636         if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
8637                 dev_err(hba->dev,
8638                 "invalid ref_clk setting = %ld\n", freq);
8639 }
8640
8641 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
8642 {
8643         int err;
8644         u32 ref_clk;
8645         u32 freq = hba->dev_ref_clk_freq;
8646
8647         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8648                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
8649
8650         if (err) {
8651                 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8652                         err);
8653                 goto out;
8654         }
8655
8656         if (ref_clk == freq)
8657                 goto out; /* nothing to update */
8658
8659         err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8660                         QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
8661
8662         if (err) {
8663                 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8664                         ufs_ref_clk_freqs[freq].freq_hz);
8665                 goto out;
8666         }
8667
8668         dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8669                         ufs_ref_clk_freqs[freq].freq_hz);
8670
8671 out:
8672         return err;
8673 }
8674
8675 static int ufshcd_device_params_init(struct ufs_hba *hba)
8676 {
8677         bool flag;
8678         int ret;
8679
8680         /* Init UFS geometry descriptor related parameters */
8681         ret = ufshcd_device_geo_params_init(hba);
8682         if (ret)
8683                 goto out;
8684
8685         /* Check and apply UFS device quirks */
8686         ret = ufs_get_device_desc(hba);
8687         if (ret) {
8688                 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8689                         __func__, ret);
8690                 goto out;
8691         }
8692
8693         ufshcd_get_ref_clk_gating_wait(hba);
8694
8695         if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
8696                         QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
8697                 hba->dev_info.f_power_on_wp_en = flag;
8698
8699         /* Probe maximum power mode co-supported by both UFS host and device */
8700         if (ufshcd_get_max_pwr_mode(hba))
8701                 dev_err(hba->dev,
8702                         "%s: Failed getting max supported power mode\n",
8703                         __func__);
8704 out:
8705         return ret;
8706 }
8707
8708 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba)
8709 {
8710         int err;
8711         struct ufs_query_req *request = NULL;
8712         struct ufs_query_res *response = NULL;
8713         struct ufs_dev_info *dev_info = &hba->dev_info;
8714         struct utp_upiu_query_v4_0 *upiu_data;
8715
8716         if (dev_info->wspecversion < 0x400)
8717                 return;
8718
8719         ufshcd_hold(hba);
8720
8721         mutex_lock(&hba->dev_cmd.lock);
8722
8723         ufshcd_init_query(hba, &request, &response,
8724                           UPIU_QUERY_OPCODE_WRITE_ATTR,
8725                           QUERY_ATTR_IDN_TIMESTAMP, 0, 0);
8726
8727         request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
8728
8729         upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req;
8730
8731         put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3);
8732
8733         err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
8734
8735         if (err)
8736                 dev_err(hba->dev, "%s: failed to set timestamp %d\n",
8737                         __func__, err);
8738
8739         mutex_unlock(&hba->dev_cmd.lock);
8740         ufshcd_release(hba);
8741 }
8742
8743 /**
8744  * ufshcd_add_lus - probe and add UFS logical units
8745  * @hba: per-adapter instance
8746  *
8747  * Return: 0 upon success; < 0 upon failure.
8748  */
8749 static int ufshcd_add_lus(struct ufs_hba *hba)
8750 {
8751         int ret;
8752
8753         /* Add required well known logical units to scsi mid layer */
8754         ret = ufshcd_scsi_add_wlus(hba);
8755         if (ret)
8756                 goto out;
8757
8758         /* Initialize devfreq after UFS device is detected */
8759         if (ufshcd_is_clkscaling_supported(hba)) {
8760                 memcpy(&hba->clk_scaling.saved_pwr_info,
8761                         &hba->pwr_info,
8762                         sizeof(struct ufs_pa_layer_attr));
8763                 hba->clk_scaling.is_allowed = true;
8764
8765                 ret = ufshcd_devfreq_init(hba);
8766                 if (ret)
8767                         goto out;
8768
8769                 hba->clk_scaling.is_enabled = true;
8770                 ufshcd_init_clk_scaling_sysfs(hba);
8771         }
8772
8773         ufs_bsg_probe(hba);
8774         scsi_scan_host(hba->host);
8775
8776 out:
8777         return ret;
8778 }
8779
8780 /* SDB - Single Doorbell */
8781 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs)
8782 {
8783         size_t ucdl_size, utrdl_size;
8784
8785         ucdl_size = ufshcd_get_ucd_size(hba) * nutrs;
8786         dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr,
8787                            hba->ucdl_dma_addr);
8788
8789         utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs;
8790         dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr,
8791                            hba->utrdl_dma_addr);
8792
8793         devm_kfree(hba->dev, hba->lrb);
8794 }
8795
8796 static int ufshcd_alloc_mcq(struct ufs_hba *hba)
8797 {
8798         int ret;
8799         int old_nutrs = hba->nutrs;
8800
8801         ret = ufshcd_mcq_decide_queue_depth(hba);
8802         if (ret < 0)
8803                 return ret;
8804
8805         hba->nutrs = ret;
8806         ret = ufshcd_mcq_init(hba);
8807         if (ret)
8808                 goto err;
8809
8810         /*
8811          * Previously allocated memory for nutrs may not be enough in MCQ mode.
8812          * Number of supported tags in MCQ mode may be larger than SDB mode.
8813          */
8814         if (hba->nutrs != old_nutrs) {
8815                 ufshcd_release_sdb_queue(hba, old_nutrs);
8816                 ret = ufshcd_memory_alloc(hba);
8817                 if (ret)
8818                         goto err;
8819                 ufshcd_host_memory_configure(hba);
8820         }
8821
8822         ret = ufshcd_mcq_memory_alloc(hba);
8823         if (ret)
8824                 goto err;
8825
8826         return 0;
8827 err:
8828         hba->nutrs = old_nutrs;
8829         return ret;
8830 }
8831
8832 static void ufshcd_config_mcq(struct ufs_hba *hba)
8833 {
8834         int ret;
8835         u32 intrs;
8836
8837         ret = ufshcd_mcq_vops_config_esi(hba);
8838         dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : "");
8839
8840         intrs = UFSHCD_ENABLE_MCQ_INTRS;
8841         if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR)
8842                 intrs &= ~MCQ_CQ_EVENT_STATUS;
8843         ufshcd_enable_intr(hba, intrs);
8844         ufshcd_mcq_make_queues_operational(hba);
8845         ufshcd_mcq_config_mac(hba, hba->nutrs);
8846
8847         hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
8848         hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED;
8849
8850         ufshcd_mcq_enable(hba);
8851         hba->mcq_enabled = true;
8852
8853         dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n",
8854                  hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT],
8855                  hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL],
8856                  hba->nutrs);
8857 }
8858
8859 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params)
8860 {
8861         int ret;
8862         struct Scsi_Host *host = hba->host;
8863
8864         hba->ufshcd_state = UFSHCD_STATE_RESET;
8865
8866         ret = ufshcd_link_startup(hba);
8867         if (ret)
8868                 return ret;
8869
8870         if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
8871                 return ret;
8872
8873         /* Debug counters initialization */
8874         ufshcd_clear_dbg_ufs_stats(hba);
8875
8876         /* UniPro link is active now */
8877         ufshcd_set_link_active(hba);
8878
8879         /* Reconfigure MCQ upon reset */
8880         if (is_mcq_enabled(hba) && !init_dev_params)
8881                 ufshcd_config_mcq(hba);
8882
8883         /* Verify device initialization by sending NOP OUT UPIU */
8884         ret = ufshcd_verify_dev_init(hba);
8885         if (ret)
8886                 return ret;
8887
8888         /* Initiate UFS initialization, and waiting until completion */
8889         ret = ufshcd_complete_dev_init(hba);
8890         if (ret)
8891                 return ret;
8892
8893         /*
8894          * Initialize UFS device parameters used by driver, these
8895          * parameters are associated with UFS descriptors.
8896          */
8897         if (init_dev_params) {
8898                 ret = ufshcd_device_params_init(hba);
8899                 if (ret)
8900                         return ret;
8901                 if (is_mcq_supported(hba) && !hba->scsi_host_added) {
8902                         ret = ufshcd_alloc_mcq(hba);
8903                         if (!ret) {
8904                                 ufshcd_config_mcq(hba);
8905                         } else {
8906                                 /* Continue with SDB mode */
8907                                 use_mcq_mode = false;
8908                                 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n",
8909                                          ret);
8910                         }
8911                         ret = scsi_add_host(host, hba->dev);
8912                         if (ret) {
8913                                 dev_err(hba->dev, "scsi_add_host failed\n");
8914                                 return ret;
8915                         }
8916                         hba->scsi_host_added = true;
8917                 } else if (is_mcq_supported(hba)) {
8918                         /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */
8919                         ufshcd_config_mcq(hba);
8920                 }
8921         }
8922
8923         ufshcd_tune_unipro_params(hba);
8924
8925         /* UFS device is also active now */
8926         ufshcd_set_ufs_dev_active(hba);
8927         ufshcd_force_reset_auto_bkops(hba);
8928
8929         ufshcd_set_timestamp_attr(hba);
8930         schedule_delayed_work(&hba->ufs_rtc_update_work,
8931                               msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS));
8932
8933         /* Gear up to HS gear if supported */
8934         if (hba->max_pwr_info.is_valid) {
8935                 /*
8936                  * Set the right value to bRefClkFreq before attempting to
8937                  * switch to HS gears.
8938                  */
8939                 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8940                         ufshcd_set_dev_ref_clk(hba);
8941                 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8942                 if (ret) {
8943                         dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8944                                         __func__, ret);
8945                         return ret;
8946                 }
8947         }
8948
8949         return 0;
8950 }
8951
8952 /**
8953  * ufshcd_probe_hba - probe hba to detect device and initialize it
8954  * @hba: per-adapter instance
8955  * @init_dev_params: whether or not to call ufshcd_device_params_init().
8956  *
8957  * Execute link-startup and verify device initialization
8958  *
8959  * Return: 0 upon success; < 0 upon failure.
8960  */
8961 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
8962 {
8963         ktime_t start = ktime_get();
8964         unsigned long flags;
8965         int ret;
8966
8967         ret = ufshcd_device_init(hba, init_dev_params);
8968         if (ret)
8969                 goto out;
8970
8971         if (!hba->pm_op_in_progress &&
8972             (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) {
8973                 /* Reset the device and controller before doing reinit */
8974                 ufshcd_device_reset(hba);
8975                 ufshcd_hba_stop(hba);
8976                 ufshcd_vops_reinit_notify(hba);
8977                 ret = ufshcd_hba_enable(hba);
8978                 if (ret) {
8979                         dev_err(hba->dev, "Host controller enable failed\n");
8980                         ufshcd_print_evt_hist(hba);
8981                         ufshcd_print_host_state(hba);
8982                         goto out;
8983                 }
8984
8985                 /* Reinit the device */
8986                 ret = ufshcd_device_init(hba, init_dev_params);
8987                 if (ret)
8988                         goto out;
8989         }
8990
8991         ufshcd_print_pwr_info(hba);
8992
8993         /*
8994          * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8995          * and for removable UFS card as well, hence always set the parameter.
8996          * Note: Error handler may issue the device reset hence resetting
8997          * bActiveICCLevel as well so it is always safe to set this here.
8998          */
8999         ufshcd_set_active_icc_lvl(hba);
9000
9001         /* Enable UFS Write Booster if supported */
9002         ufshcd_configure_wb(hba);
9003
9004         if (hba->ee_usr_mask)
9005                 ufshcd_write_ee_control(hba);
9006         ufshcd_configure_auto_hibern8(hba);
9007
9008 out:
9009         spin_lock_irqsave(hba->host->host_lock, flags);
9010         if (ret)
9011                 hba->ufshcd_state = UFSHCD_STATE_ERROR;
9012         else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
9013                 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
9014         spin_unlock_irqrestore(hba->host->host_lock, flags);
9015
9016         trace_ufshcd_init(dev_name(hba->dev), ret,
9017                 ktime_to_us(ktime_sub(ktime_get(), start)),
9018                 hba->curr_dev_pwr_mode, hba->uic_link_state);
9019         return ret;
9020 }
9021
9022 /**
9023  * ufshcd_async_scan - asynchronous execution for probing hba
9024  * @data: data pointer to pass to this function
9025  * @cookie: cookie data
9026  */
9027 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
9028 {
9029         struct ufs_hba *hba = (struct ufs_hba *)data;
9030         int ret;
9031
9032         down(&hba->host_sem);
9033         /* Initialize hba, detect and initialize UFS device */
9034         ret = ufshcd_probe_hba(hba, true);
9035         up(&hba->host_sem);
9036         if (ret)
9037                 goto out;
9038
9039         /* Probe and add UFS logical units  */
9040         ret = ufshcd_add_lus(hba);
9041
9042 out:
9043         pm_runtime_put_sync(hba->dev);
9044
9045         if (ret)
9046                 dev_err(hba->dev, "%s failed: %d\n", __func__, ret);
9047 }
9048
9049 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd)
9050 {
9051         struct ufs_hba *hba = shost_priv(scmd->device->host);
9052
9053         if (!hba->system_suspending) {
9054                 /* Activate the error handler in the SCSI core. */
9055                 return SCSI_EH_NOT_HANDLED;
9056         }
9057
9058         /*
9059          * If we get here we know that no TMFs are outstanding and also that
9060          * the only pending command is a START STOP UNIT command. Handle the
9061          * timeout of that command directly to prevent a deadlock between
9062          * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler().
9063          */
9064         ufshcd_link_recovery(hba);
9065         dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n",
9066                  __func__, hba->outstanding_tasks);
9067
9068         return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE;
9069 }
9070
9071 static const struct attribute_group *ufshcd_driver_groups[] = {
9072         &ufs_sysfs_unit_descriptor_group,
9073         &ufs_sysfs_lun_attributes_group,
9074         NULL,
9075 };
9076
9077 static struct ufs_hba_variant_params ufs_hba_vps = {
9078         .hba_enable_delay_us            = 1000,
9079         .wb_flush_threshold             = UFS_WB_BUF_REMAIN_PERCENT(40),
9080         .devfreq_profile.polling_ms     = 100,
9081         .devfreq_profile.target         = ufshcd_devfreq_target,
9082         .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
9083         .ondemand_data.upthreshold      = 70,
9084         .ondemand_data.downdifferential = 5,
9085 };
9086
9087 static const struct scsi_host_template ufshcd_driver_template = {
9088         .module                 = THIS_MODULE,
9089         .name                   = UFSHCD,
9090         .proc_name              = UFSHCD,
9091         .map_queues             = ufshcd_map_queues,
9092         .queuecommand           = ufshcd_queuecommand,
9093         .mq_poll                = ufshcd_poll,
9094         .slave_alloc            = ufshcd_slave_alloc,
9095         .slave_configure        = ufshcd_slave_configure,
9096         .slave_destroy          = ufshcd_slave_destroy,
9097         .change_queue_depth     = ufshcd_change_queue_depth,
9098         .eh_abort_handler       = ufshcd_abort,
9099         .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
9100         .eh_host_reset_handler   = ufshcd_eh_host_reset_handler,
9101         .eh_timed_out           = ufshcd_eh_timed_out,
9102         .this_id                = -1,
9103         .sg_tablesize           = SG_ALL,
9104         .cmd_per_lun            = UFSHCD_CMD_PER_LUN,
9105         .can_queue              = UFSHCD_CAN_QUEUE,
9106         .max_segment_size       = PRDT_DATA_BYTE_COUNT_MAX,
9107         .max_sectors            = SZ_1M / SECTOR_SIZE,
9108         .max_host_blocked       = 1,
9109         .track_queue_depth      = 1,
9110         .skip_settle_delay      = 1,
9111         .sdev_groups            = ufshcd_driver_groups,
9112 };
9113
9114 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
9115                                    int ua)
9116 {
9117         int ret;
9118
9119         if (!vreg)
9120                 return 0;
9121
9122         /*
9123          * "set_load" operation shall be required on those regulators
9124          * which specifically configured current limitation. Otherwise
9125          * zero max_uA may cause unexpected behavior when regulator is
9126          * enabled or set as high power mode.
9127          */
9128         if (!vreg->max_uA)
9129                 return 0;
9130
9131         ret = regulator_set_load(vreg->reg, ua);
9132         if (ret < 0) {
9133                 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
9134                                 __func__, vreg->name, ua, ret);
9135         }
9136
9137         return ret;
9138 }
9139
9140 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
9141                                          struct ufs_vreg *vreg)
9142 {
9143         return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
9144 }
9145
9146 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
9147                                          struct ufs_vreg *vreg)
9148 {
9149         if (!vreg)
9150                 return 0;
9151
9152         return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
9153 }
9154
9155 static int ufshcd_config_vreg(struct device *dev,
9156                 struct ufs_vreg *vreg, bool on)
9157 {
9158         if (regulator_count_voltages(vreg->reg) <= 0)
9159                 return 0;
9160
9161         return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0);
9162 }
9163
9164 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
9165 {
9166         int ret = 0;
9167
9168         if (!vreg || vreg->enabled)
9169                 goto out;
9170
9171         ret = ufshcd_config_vreg(dev, vreg, true);
9172         if (!ret)
9173                 ret = regulator_enable(vreg->reg);
9174
9175         if (!ret)
9176                 vreg->enabled = true;
9177         else
9178                 dev_err(dev, "%s: %s enable failed, err=%d\n",
9179                                 __func__, vreg->name, ret);
9180 out:
9181         return ret;
9182 }
9183
9184 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
9185 {
9186         int ret = 0;
9187
9188         if (!vreg || !vreg->enabled || vreg->always_on)
9189                 goto out;
9190
9191         ret = regulator_disable(vreg->reg);
9192
9193         if (!ret) {
9194                 /* ignore errors on applying disable config */
9195                 ufshcd_config_vreg(dev, vreg, false);
9196                 vreg->enabled = false;
9197         } else {
9198                 dev_err(dev, "%s: %s disable failed, err=%d\n",
9199                                 __func__, vreg->name, ret);
9200         }
9201 out:
9202         return ret;
9203 }
9204
9205 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
9206 {
9207         int ret = 0;
9208         struct device *dev = hba->dev;
9209         struct ufs_vreg_info *info = &hba->vreg_info;
9210
9211         ret = ufshcd_toggle_vreg(dev, info->vcc, on);
9212         if (ret)
9213                 goto out;
9214
9215         ret = ufshcd_toggle_vreg(dev, info->vccq, on);
9216         if (ret)
9217                 goto out;
9218
9219         ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
9220
9221 out:
9222         if (ret) {
9223                 ufshcd_toggle_vreg(dev, info->vccq2, false);
9224                 ufshcd_toggle_vreg(dev, info->vccq, false);
9225                 ufshcd_toggle_vreg(dev, info->vcc, false);
9226         }
9227         return ret;
9228 }
9229
9230 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
9231 {
9232         struct ufs_vreg_info *info = &hba->vreg_info;
9233
9234         return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
9235 }
9236
9237 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
9238 {
9239         int ret = 0;
9240
9241         if (!vreg)
9242                 goto out;
9243
9244         vreg->reg = devm_regulator_get(dev, vreg->name);
9245         if (IS_ERR(vreg->reg)) {
9246                 ret = PTR_ERR(vreg->reg);
9247                 dev_err(dev, "%s: %s get failed, err=%d\n",
9248                                 __func__, vreg->name, ret);
9249         }
9250 out:
9251         return ret;
9252 }
9253 EXPORT_SYMBOL_GPL(ufshcd_get_vreg);
9254
9255 static int ufshcd_init_vreg(struct ufs_hba *hba)
9256 {
9257         int ret = 0;
9258         struct device *dev = hba->dev;
9259         struct ufs_vreg_info *info = &hba->vreg_info;
9260
9261         ret = ufshcd_get_vreg(dev, info->vcc);
9262         if (ret)
9263                 goto out;
9264
9265         ret = ufshcd_get_vreg(dev, info->vccq);
9266         if (!ret)
9267                 ret = ufshcd_get_vreg(dev, info->vccq2);
9268 out:
9269         return ret;
9270 }
9271
9272 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
9273 {
9274         struct ufs_vreg_info *info = &hba->vreg_info;
9275
9276         return ufshcd_get_vreg(hba->dev, info->vdd_hba);
9277 }
9278
9279 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
9280 {
9281         int ret = 0;
9282         struct ufs_clk_info *clki;
9283         struct list_head *head = &hba->clk_list_head;
9284         unsigned long flags;
9285         ktime_t start = ktime_get();
9286         bool clk_state_changed = false;
9287
9288         if (list_empty(head))
9289                 goto out;
9290
9291         ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
9292         if (ret)
9293                 return ret;
9294
9295         list_for_each_entry(clki, head, list) {
9296                 if (!IS_ERR_OR_NULL(clki->clk)) {
9297                         /*
9298                          * Don't disable clocks which are needed
9299                          * to keep the link active.
9300                          */
9301                         if (ufshcd_is_link_active(hba) &&
9302                             clki->keep_link_active)
9303                                 continue;
9304
9305                         clk_state_changed = on ^ clki->enabled;
9306                         if (on && !clki->enabled) {
9307                                 ret = clk_prepare_enable(clki->clk);
9308                                 if (ret) {
9309                                         dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
9310                                                 __func__, clki->name, ret);
9311                                         goto out;
9312                                 }
9313                         } else if (!on && clki->enabled) {
9314                                 clk_disable_unprepare(clki->clk);
9315                         }
9316                         clki->enabled = on;
9317                         dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
9318                                         clki->name, on ? "en" : "dis");
9319                 }
9320         }
9321
9322         ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
9323         if (ret)
9324                 return ret;
9325
9326         if (!ufshcd_is_clkscaling_supported(hba))
9327                 ufshcd_pm_qos_update(hba, on);
9328 out:
9329         if (ret) {
9330                 list_for_each_entry(clki, head, list) {
9331                         if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
9332                                 clk_disable_unprepare(clki->clk);
9333                 }
9334         } else if (!ret && on) {
9335                 spin_lock_irqsave(hba->host->host_lock, flags);
9336                 hba->clk_gating.state = CLKS_ON;
9337                 trace_ufshcd_clk_gating(dev_name(hba->dev),
9338                                         hba->clk_gating.state);
9339                 spin_unlock_irqrestore(hba->host->host_lock, flags);
9340         }
9341
9342         if (clk_state_changed)
9343                 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
9344                         (on ? "on" : "off"),
9345                         ktime_to_us(ktime_sub(ktime_get(), start)), ret);
9346         return ret;
9347 }
9348
9349 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba)
9350 {
9351         u32 freq;
9352         int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq);
9353
9354         if (ret) {
9355                 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret);
9356                 return REF_CLK_FREQ_INVAL;
9357         }
9358
9359         return ufs_get_bref_clk_from_hz(freq);
9360 }
9361
9362 static int ufshcd_init_clocks(struct ufs_hba *hba)
9363 {
9364         int ret = 0;
9365         struct ufs_clk_info *clki;
9366         struct device *dev = hba->dev;
9367         struct list_head *head = &hba->clk_list_head;
9368
9369         if (list_empty(head))
9370                 goto out;
9371
9372         list_for_each_entry(clki, head, list) {
9373                 if (!clki->name)
9374                         continue;
9375
9376                 clki->clk = devm_clk_get(dev, clki->name);
9377                 if (IS_ERR(clki->clk)) {
9378                         ret = PTR_ERR(clki->clk);
9379                         dev_err(dev, "%s: %s clk get failed, %d\n",
9380                                         __func__, clki->name, ret);
9381                         goto out;
9382                 }
9383
9384                 /*
9385                  * Parse device ref clk freq as per device tree "ref_clk".
9386                  * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
9387                  * in ufshcd_alloc_host().
9388                  */
9389                 if (!strcmp(clki->name, "ref_clk"))
9390                         ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
9391
9392                 if (clki->max_freq) {
9393                         ret = clk_set_rate(clki->clk, clki->max_freq);
9394                         if (ret) {
9395                                 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
9396                                         __func__, clki->name,
9397                                         clki->max_freq, ret);
9398                                 goto out;
9399                         }
9400                         clki->curr_freq = clki->max_freq;
9401                 }
9402                 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
9403                                 clki->name, clk_get_rate(clki->clk));
9404         }
9405
9406         /* Set Max. frequency for all clocks */
9407         if (hba->use_pm_opp) {
9408                 ret = ufshcd_opp_set_rate(hba, ULONG_MAX);
9409                 if (ret) {
9410                         dev_err(hba->dev, "%s: failed to set OPP: %d", __func__,
9411                                 ret);
9412                         goto out;
9413                 }
9414         }
9415
9416 out:
9417         return ret;
9418 }
9419
9420 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
9421 {
9422         int err = 0;
9423
9424         if (!hba->vops)
9425                 goto out;
9426
9427         err = ufshcd_vops_init(hba);
9428         if (err)
9429                 dev_err_probe(hba->dev, err,
9430                               "%s: variant %s init failed with err %d\n",
9431                               __func__, ufshcd_get_var_name(hba), err);
9432 out:
9433         return err;
9434 }
9435
9436 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
9437 {
9438         if (!hba->vops)
9439                 return;
9440
9441         ufshcd_vops_exit(hba);
9442 }
9443
9444 static int ufshcd_hba_init(struct ufs_hba *hba)
9445 {
9446         int err;
9447
9448         /*
9449          * Handle host controller power separately from the UFS device power
9450          * rails as it will help controlling the UFS host controller power
9451          * collapse easily which is different than UFS device power collapse.
9452          * Also, enable the host controller power before we go ahead with rest
9453          * of the initialization here.
9454          */
9455         err = ufshcd_init_hba_vreg(hba);
9456         if (err)
9457                 goto out;
9458
9459         err = ufshcd_setup_hba_vreg(hba, true);
9460         if (err)
9461                 goto out;
9462
9463         err = ufshcd_init_clocks(hba);
9464         if (err)
9465                 goto out_disable_hba_vreg;
9466
9467         if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
9468                 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba);
9469
9470         err = ufshcd_setup_clocks(hba, true);
9471         if (err)
9472                 goto out_disable_hba_vreg;
9473
9474         err = ufshcd_init_vreg(hba);
9475         if (err)
9476                 goto out_disable_clks;
9477
9478         err = ufshcd_setup_vreg(hba, true);
9479         if (err)
9480                 goto out_disable_clks;
9481
9482         err = ufshcd_variant_hba_init(hba);
9483         if (err)
9484                 goto out_disable_vreg;
9485
9486         ufs_debugfs_hba_init(hba);
9487         ufs_fault_inject_hba_init(hba);
9488
9489         hba->is_powered = true;
9490         goto out;
9491
9492 out_disable_vreg:
9493         ufshcd_setup_vreg(hba, false);
9494 out_disable_clks:
9495         ufshcd_setup_clocks(hba, false);
9496 out_disable_hba_vreg:
9497         ufshcd_setup_hba_vreg(hba, false);
9498 out:
9499         return err;
9500 }
9501
9502 static void ufshcd_hba_exit(struct ufs_hba *hba)
9503 {
9504         if (hba->is_powered) {
9505                 ufshcd_pm_qos_exit(hba);
9506                 ufshcd_exit_clk_scaling(hba);
9507                 ufshcd_exit_clk_gating(hba);
9508                 if (hba->eh_wq)
9509                         destroy_workqueue(hba->eh_wq);
9510                 ufs_debugfs_hba_exit(hba);
9511                 ufshcd_variant_hba_exit(hba);
9512                 ufshcd_setup_vreg(hba, false);
9513                 ufshcd_setup_clocks(hba, false);
9514                 ufshcd_setup_hba_vreg(hba, false);
9515                 hba->is_powered = false;
9516                 ufs_put_device_desc(hba);
9517         }
9518 }
9519
9520 static int ufshcd_execute_start_stop(struct scsi_device *sdev,
9521                                      enum ufs_dev_pwr_mode pwr_mode,
9522                                      struct scsi_sense_hdr *sshdr)
9523 {
9524         const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 };
9525         struct scsi_failure failure_defs[] = {
9526                 {
9527                         .allowed = 2,
9528                         .result = SCMD_FAILURE_RESULT_ANY,
9529                 },
9530         };
9531         struct scsi_failures failures = {
9532                 .failure_definitions = failure_defs,
9533         };
9534         const struct scsi_exec_args args = {
9535                 .failures = &failures,
9536                 .sshdr = sshdr,
9537                 .req_flags = BLK_MQ_REQ_PM,
9538                 .scmd_flags = SCMD_FAIL_IF_RECOVERING,
9539         };
9540
9541         return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL,
9542                         /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0,
9543                         &args);
9544 }
9545
9546 /**
9547  * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
9548  *                           power mode
9549  * @hba: per adapter instance
9550  * @pwr_mode: device power mode to set
9551  *
9552  * Return: 0 if requested power mode is set successfully;
9553  *         < 0 if failed to set the requested power mode.
9554  */
9555 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
9556                                      enum ufs_dev_pwr_mode pwr_mode)
9557 {
9558         struct scsi_sense_hdr sshdr;
9559         struct scsi_device *sdp;
9560         unsigned long flags;
9561         int ret;
9562
9563         spin_lock_irqsave(hba->host->host_lock, flags);
9564         sdp = hba->ufs_device_wlun;
9565         if (sdp && scsi_device_online(sdp))
9566                 ret = scsi_device_get(sdp);
9567         else
9568                 ret = -ENODEV;
9569         spin_unlock_irqrestore(hba->host->host_lock, flags);
9570
9571         if (ret)
9572                 return ret;
9573
9574         /*
9575          * If scsi commands fail, the scsi mid-layer schedules scsi error-
9576          * handling, which would wait for host to be resumed. Since we know
9577          * we are functional while we are here, skip host resume in error
9578          * handling context.
9579          */
9580         hba->host->eh_noresume = 1;
9581
9582         /*
9583          * Current function would be generally called from the power management
9584          * callbacks hence set the RQF_PM flag so that it doesn't resume the
9585          * already suspended childs.
9586          */
9587         ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr);
9588         if (ret) {
9589                 sdev_printk(KERN_WARNING, sdp,
9590                             "START_STOP failed for power mode: %d, result %x\n",
9591                             pwr_mode, ret);
9592                 if (ret > 0) {
9593                         if (scsi_sense_valid(&sshdr))
9594                                 scsi_print_sense_hdr(sdp, NULL, &sshdr);
9595                         ret = -EIO;
9596                 }
9597         } else {
9598                 hba->curr_dev_pwr_mode = pwr_mode;
9599         }
9600
9601         scsi_device_put(sdp);
9602         hba->host->eh_noresume = 0;
9603         return ret;
9604 }
9605
9606 static int ufshcd_link_state_transition(struct ufs_hba *hba,
9607                                         enum uic_link_state req_link_state,
9608                                         bool check_for_bkops)
9609 {
9610         int ret = 0;
9611
9612         if (req_link_state == hba->uic_link_state)
9613                 return 0;
9614
9615         if (req_link_state == UIC_LINK_HIBERN8_STATE) {
9616                 ret = ufshcd_uic_hibern8_enter(hba);
9617                 if (!ret) {
9618                         ufshcd_set_link_hibern8(hba);
9619                 } else {
9620                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9621                                         __func__, ret);
9622                         goto out;
9623                 }
9624         }
9625         /*
9626          * If autobkops is enabled, link can't be turned off because
9627          * turning off the link would also turn off the device, except in the
9628          * case of DeepSleep where the device is expected to remain powered.
9629          */
9630         else if ((req_link_state == UIC_LINK_OFF_STATE) &&
9631                  (!check_for_bkops || !hba->auto_bkops_enabled)) {
9632                 /*
9633                  * Let's make sure that link is in low power mode, we are doing
9634                  * this currently by putting the link in Hibern8. Otherway to
9635                  * put the link in low power mode is to send the DME end point
9636                  * to device and then send the DME reset command to local
9637                  * unipro. But putting the link in hibern8 is much faster.
9638                  *
9639                  * Note also that putting the link in Hibern8 is a requirement
9640                  * for entering DeepSleep.
9641                  */
9642                 ret = ufshcd_uic_hibern8_enter(hba);
9643                 if (ret) {
9644                         dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
9645                                         __func__, ret);
9646                         goto out;
9647                 }
9648                 /*
9649                  * Change controller state to "reset state" which
9650                  * should also put the link in off/reset state
9651                  */
9652                 ufshcd_hba_stop(hba);
9653                 /*
9654                  * TODO: Check if we need any delay to make sure that
9655                  * controller is reset
9656                  */
9657                 ufshcd_set_link_off(hba);
9658         }
9659
9660 out:
9661         return ret;
9662 }
9663
9664 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
9665 {
9666         bool vcc_off = false;
9667
9668         /*
9669          * It seems some UFS devices may keep drawing more than sleep current
9670          * (atleast for 500us) from UFS rails (especially from VCCQ rail).
9671          * To avoid this situation, add 2ms delay before putting these UFS
9672          * rails in LPM mode.
9673          */
9674         if (!ufshcd_is_link_active(hba) &&
9675             hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
9676                 usleep_range(2000, 2100);
9677
9678         /*
9679          * If UFS device is either in UFS_Sleep turn off VCC rail to save some
9680          * power.
9681          *
9682          * If UFS device and link is in OFF state, all power supplies (VCC,
9683          * VCCQ, VCCQ2) can be turned off if power on write protect is not
9684          * required. If UFS link is inactive (Hibern8 or OFF state) and device
9685          * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
9686          *
9687          * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
9688          * in low power state which would save some power.
9689          *
9690          * If Write Booster is enabled and the device needs to flush the WB
9691          * buffer OR if bkops status is urgent for WB, keep Vcc on.
9692          */
9693         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9694             !hba->dev_info.is_lu_power_on_wp) {
9695                 ufshcd_setup_vreg(hba, false);
9696                 vcc_off = true;
9697         } else if (!ufshcd_is_ufs_dev_active(hba)) {
9698                 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9699                 vcc_off = true;
9700                 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
9701                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9702                         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
9703                 }
9704         }
9705
9706         /*
9707          * Some UFS devices require delay after VCC power rail is turned-off.
9708          */
9709         if (vcc_off && hba->vreg_info.vcc &&
9710                 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
9711                 usleep_range(5000, 5100);
9712 }
9713
9714 #ifdef CONFIG_PM
9715 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
9716 {
9717         int ret = 0;
9718
9719         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
9720             !hba->dev_info.is_lu_power_on_wp) {
9721                 ret = ufshcd_setup_vreg(hba, true);
9722         } else if (!ufshcd_is_ufs_dev_active(hba)) {
9723                 if (!ufshcd_is_link_active(hba)) {
9724                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
9725                         if (ret)
9726                                 goto vcc_disable;
9727                         ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
9728                         if (ret)
9729                                 goto vccq_lpm;
9730                 }
9731                 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
9732         }
9733         goto out;
9734
9735 vccq_lpm:
9736         ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
9737 vcc_disable:
9738         ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
9739 out:
9740         return ret;
9741 }
9742 #endif /* CONFIG_PM */
9743
9744 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
9745 {
9746         if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9747                 ufshcd_setup_hba_vreg(hba, false);
9748 }
9749
9750 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
9751 {
9752         if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
9753                 ufshcd_setup_hba_vreg(hba, true);
9754 }
9755
9756 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9757 {
9758         int ret = 0;
9759         bool check_for_bkops;
9760         enum ufs_pm_level pm_lvl;
9761         enum ufs_dev_pwr_mode req_dev_pwr_mode;
9762         enum uic_link_state req_link_state;
9763
9764         hba->pm_op_in_progress = true;
9765         if (pm_op != UFS_SHUTDOWN_PM) {
9766                 pm_lvl = pm_op == UFS_RUNTIME_PM ?
9767                          hba->rpm_lvl : hba->spm_lvl;
9768                 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
9769                 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
9770         } else {
9771                 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
9772                 req_link_state = UIC_LINK_OFF_STATE;
9773         }
9774
9775         /*
9776          * If we can't transition into any of the low power modes
9777          * just gate the clocks.
9778          */
9779         ufshcd_hold(hba);
9780         hba->clk_gating.is_suspended = true;
9781
9782         if (ufshcd_is_clkscaling_supported(hba))
9783                 ufshcd_clk_scaling_suspend(hba, true);
9784
9785         if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
9786                         req_link_state == UIC_LINK_ACTIVE_STATE) {
9787                 goto vops_suspend;
9788         }
9789
9790         if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
9791             (req_link_state == hba->uic_link_state))
9792                 goto enable_scaling;
9793
9794         /* UFS device & link must be active before we enter in this function */
9795         if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
9796                 /*  Wait err handler finish or trigger err recovery */
9797                 if (!ufshcd_eh_in_progress(hba))
9798                         ufshcd_force_error_recovery(hba);
9799                 ret = -EBUSY;
9800                 goto enable_scaling;
9801         }
9802
9803         if (pm_op == UFS_RUNTIME_PM) {
9804                 if (ufshcd_can_autobkops_during_suspend(hba)) {
9805                         /*
9806                          * The device is idle with no requests in the queue,
9807                          * allow background operations if bkops status shows
9808                          * that performance might be impacted.
9809                          */
9810                         ret = ufshcd_urgent_bkops(hba);
9811                         if (ret) {
9812                                 /*
9813                                  * If return err in suspend flow, IO will hang.
9814                                  * Trigger error handler and break suspend for
9815                                  * error recovery.
9816                                  */
9817                                 ufshcd_force_error_recovery(hba);
9818                                 ret = -EBUSY;
9819                                 goto enable_scaling;
9820                         }
9821                 } else {
9822                         /* make sure that auto bkops is disabled */
9823                         ufshcd_disable_auto_bkops(hba);
9824                 }
9825                 /*
9826                  * If device needs to do BKOP or WB buffer flush during
9827                  * Hibern8, keep device power mode as "active power mode"
9828                  * and VCC supply.
9829                  */
9830                 hba->dev_info.b_rpm_dev_flush_capable =
9831                         hba->auto_bkops_enabled ||
9832                         (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
9833                         ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
9834                         ufshcd_is_auto_hibern8_enabled(hba))) &&
9835                         ufshcd_wb_need_flush(hba));
9836         }
9837
9838         flush_work(&hba->eeh_work);
9839
9840         ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9841         if (ret)
9842                 goto enable_scaling;
9843
9844         if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
9845                 if (pm_op != UFS_RUNTIME_PM)
9846                         /* ensure that bkops is disabled */
9847                         ufshcd_disable_auto_bkops(hba);
9848
9849                 if (!hba->dev_info.b_rpm_dev_flush_capable) {
9850                         ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
9851                         if (ret && pm_op != UFS_SHUTDOWN_PM) {
9852                                 /*
9853                                  * If return err in suspend flow, IO will hang.
9854                                  * Trigger error handler and break suspend for
9855                                  * error recovery.
9856                                  */
9857                                 ufshcd_force_error_recovery(hba);
9858                                 ret = -EBUSY;
9859                         }
9860                         if (ret)
9861                                 goto enable_scaling;
9862                 }
9863         }
9864
9865         /*
9866          * In the case of DeepSleep, the device is expected to remain powered
9867          * with the link off, so do not check for bkops.
9868          */
9869         check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
9870         ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
9871         if (ret && pm_op != UFS_SHUTDOWN_PM) {
9872                 /*
9873                  * If return err in suspend flow, IO will hang.
9874                  * Trigger error handler and break suspend for
9875                  * error recovery.
9876                  */
9877                 ufshcd_force_error_recovery(hba);
9878                 ret = -EBUSY;
9879         }
9880         if (ret)
9881                 goto set_dev_active;
9882
9883 vops_suspend:
9884         /*
9885          * Call vendor specific suspend callback. As these callbacks may access
9886          * vendor specific host controller register space call them before the
9887          * host clocks are ON.
9888          */
9889         ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9890         if (ret)
9891                 goto set_link_active;
9892
9893         cancel_delayed_work_sync(&hba->ufs_rtc_update_work);
9894         goto out;
9895
9896 set_link_active:
9897         /*
9898          * Device hardware reset is required to exit DeepSleep. Also, for
9899          * DeepSleep, the link is off so host reset and restore will be done
9900          * further below.
9901          */
9902         if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9903                 ufshcd_device_reset(hba);
9904                 WARN_ON(!ufshcd_is_link_off(hba));
9905         }
9906         if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
9907                 ufshcd_set_link_active(hba);
9908         else if (ufshcd_is_link_off(hba))
9909                 ufshcd_host_reset_and_restore(hba);
9910 set_dev_active:
9911         /* Can also get here needing to exit DeepSleep */
9912         if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9913                 ufshcd_device_reset(hba);
9914                 ufshcd_host_reset_and_restore(hba);
9915         }
9916         if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
9917                 ufshcd_disable_auto_bkops(hba);
9918 enable_scaling:
9919         if (ufshcd_is_clkscaling_supported(hba))
9920                 ufshcd_clk_scaling_suspend(hba, false);
9921
9922         hba->dev_info.b_rpm_dev_flush_capable = false;
9923 out:
9924         if (hba->dev_info.b_rpm_dev_flush_capable) {
9925                 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
9926                         msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
9927         }
9928
9929         if (ret) {
9930                 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9931                 hba->clk_gating.is_suspended = false;
9932                 ufshcd_release(hba);
9933         }
9934         hba->pm_op_in_progress = false;
9935         return ret;
9936 }
9937
9938 #ifdef CONFIG_PM
9939 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9940 {
9941         int ret;
9942         enum uic_link_state old_link_state = hba->uic_link_state;
9943
9944         hba->pm_op_in_progress = true;
9945
9946         /*
9947          * Call vendor specific resume callback. As these callbacks may access
9948          * vendor specific host controller register space call them when the
9949          * host clocks are ON.
9950          */
9951         ret = ufshcd_vops_resume(hba, pm_op);
9952         if (ret)
9953                 goto out;
9954
9955         /* For DeepSleep, the only supported option is to have the link off */
9956         WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9957
9958         if (ufshcd_is_link_hibern8(hba)) {
9959                 ret = ufshcd_uic_hibern8_exit(hba);
9960                 if (!ret) {
9961                         ufshcd_set_link_active(hba);
9962                 } else {
9963                         dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9964                                         __func__, ret);
9965                         goto vendor_suspend;
9966                 }
9967         } else if (ufshcd_is_link_off(hba)) {
9968                 /*
9969                  * A full initialization of the host and the device is
9970                  * required since the link was put to off during suspend.
9971                  * Note, in the case of DeepSleep, the device will exit
9972                  * DeepSleep due to device reset.
9973                  */
9974                 ret = ufshcd_reset_and_restore(hba);
9975                 /*
9976                  * ufshcd_reset_and_restore() should have already
9977                  * set the link state as active
9978                  */
9979                 if (ret || !ufshcd_is_link_active(hba))
9980                         goto vendor_suspend;
9981         }
9982
9983         if (!ufshcd_is_ufs_dev_active(hba)) {
9984                 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9985                 if (ret)
9986                         goto set_old_link_state;
9987                 ufshcd_set_timestamp_attr(hba);
9988                 schedule_delayed_work(&hba->ufs_rtc_update_work,
9989                                       msecs_to_jiffies(UFS_RTC_UPDATE_INTERVAL_MS));
9990         }
9991
9992         if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9993                 ufshcd_enable_auto_bkops(hba);
9994         else
9995                 /*
9996                  * If BKOPs operations are urgently needed at this moment then
9997                  * keep auto-bkops enabled or else disable it.
9998                  */
9999                 ufshcd_urgent_bkops(hba);
10000
10001         if (hba->ee_usr_mask)
10002                 ufshcd_write_ee_control(hba);
10003
10004         if (ufshcd_is_clkscaling_supported(hba))
10005                 ufshcd_clk_scaling_suspend(hba, false);
10006
10007         if (hba->dev_info.b_rpm_dev_flush_capable) {
10008                 hba->dev_info.b_rpm_dev_flush_capable = false;
10009                 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
10010         }
10011
10012         ufshcd_configure_auto_hibern8(hba);
10013
10014         goto out;
10015
10016 set_old_link_state:
10017         ufshcd_link_state_transition(hba, old_link_state, 0);
10018 vendor_suspend:
10019         ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
10020         ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
10021 out:
10022         if (ret)
10023                 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
10024         hba->clk_gating.is_suspended = false;
10025         ufshcd_release(hba);
10026         hba->pm_op_in_progress = false;
10027         return ret;
10028 }
10029
10030 static int ufshcd_wl_runtime_suspend(struct device *dev)
10031 {
10032         struct scsi_device *sdev = to_scsi_device(dev);
10033         struct ufs_hba *hba;
10034         int ret;
10035         ktime_t start = ktime_get();
10036
10037         hba = shost_priv(sdev->host);
10038
10039         ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
10040         if (ret)
10041                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
10042
10043         trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
10044                 ktime_to_us(ktime_sub(ktime_get(), start)),
10045                 hba->curr_dev_pwr_mode, hba->uic_link_state);
10046
10047         return ret;
10048 }
10049
10050 static int ufshcd_wl_runtime_resume(struct device *dev)
10051 {
10052         struct scsi_device *sdev = to_scsi_device(dev);
10053         struct ufs_hba *hba;
10054         int ret = 0;
10055         ktime_t start = ktime_get();
10056
10057         hba = shost_priv(sdev->host);
10058
10059         ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
10060         if (ret)
10061                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
10062
10063         trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
10064                 ktime_to_us(ktime_sub(ktime_get(), start)),
10065                 hba->curr_dev_pwr_mode, hba->uic_link_state);
10066
10067         return ret;
10068 }
10069 #endif
10070
10071 #ifdef CONFIG_PM_SLEEP
10072 static int ufshcd_wl_suspend(struct device *dev)
10073 {
10074         struct scsi_device *sdev = to_scsi_device(dev);
10075         struct ufs_hba *hba;
10076         int ret = 0;
10077         ktime_t start = ktime_get();
10078
10079         hba = shost_priv(sdev->host);
10080         down(&hba->host_sem);
10081         hba->system_suspending = true;
10082
10083         if (pm_runtime_suspended(dev))
10084                 goto out;
10085
10086         ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
10087         if (ret) {
10088                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__,  ret);
10089                 up(&hba->host_sem);
10090         }
10091
10092 out:
10093         if (!ret)
10094                 hba->is_sys_suspended = true;
10095         trace_ufshcd_wl_suspend(dev_name(dev), ret,
10096                 ktime_to_us(ktime_sub(ktime_get(), start)),
10097                 hba->curr_dev_pwr_mode, hba->uic_link_state);
10098
10099         return ret;
10100 }
10101
10102 static int ufshcd_wl_resume(struct device *dev)
10103 {
10104         struct scsi_device *sdev = to_scsi_device(dev);
10105         struct ufs_hba *hba;
10106         int ret = 0;
10107         ktime_t start = ktime_get();
10108
10109         hba = shost_priv(sdev->host);
10110
10111         if (pm_runtime_suspended(dev))
10112                 goto out;
10113
10114         ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
10115         if (ret)
10116                 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
10117 out:
10118         trace_ufshcd_wl_resume(dev_name(dev), ret,
10119                 ktime_to_us(ktime_sub(ktime_get(), start)),
10120                 hba->curr_dev_pwr_mode, hba->uic_link_state);
10121         if (!ret)
10122                 hba->is_sys_suspended = false;
10123         hba->system_suspending = false;
10124         up(&hba->host_sem);
10125         return ret;
10126 }
10127 #endif
10128
10129 /**
10130  * ufshcd_suspend - helper function for suspend operations
10131  * @hba: per adapter instance
10132  *
10133  * This function will put disable irqs, turn off clocks
10134  * and set vreg and hba-vreg in lpm mode.
10135  *
10136  * Return: 0 upon success; < 0 upon failure.
10137  */
10138 static int ufshcd_suspend(struct ufs_hba *hba)
10139 {
10140         int ret;
10141
10142         if (!hba->is_powered)
10143                 return 0;
10144         /*
10145          * Disable the host irq as host controller as there won't be any
10146          * host controller transaction expected till resume.
10147          */
10148         ufshcd_disable_irq(hba);
10149         ret = ufshcd_setup_clocks(hba, false);
10150         if (ret) {
10151                 ufshcd_enable_irq(hba);
10152                 return ret;
10153         }
10154         if (ufshcd_is_clkgating_allowed(hba)) {
10155                 hba->clk_gating.state = CLKS_OFF;
10156                 trace_ufshcd_clk_gating(dev_name(hba->dev),
10157                                         hba->clk_gating.state);
10158         }
10159
10160         ufshcd_vreg_set_lpm(hba);
10161         /* Put the host controller in low power mode if possible */
10162         ufshcd_hba_vreg_set_lpm(hba);
10163         ufshcd_pm_qos_update(hba, false);
10164         return ret;
10165 }
10166
10167 #ifdef CONFIG_PM
10168 /**
10169  * ufshcd_resume - helper function for resume operations
10170  * @hba: per adapter instance
10171  *
10172  * This function basically turns on the regulators, clocks and
10173  * irqs of the hba.
10174  *
10175  * Return: 0 for success and non-zero for failure.
10176  */
10177 static int ufshcd_resume(struct ufs_hba *hba)
10178 {
10179         int ret;
10180
10181         if (!hba->is_powered)
10182                 return 0;
10183
10184         ufshcd_hba_vreg_set_hpm(hba);
10185         ret = ufshcd_vreg_set_hpm(hba);
10186         if (ret)
10187                 goto out;
10188
10189         /* Make sure clocks are enabled before accessing controller */
10190         ret = ufshcd_setup_clocks(hba, true);
10191         if (ret)
10192                 goto disable_vreg;
10193
10194         /* enable the host irq as host controller would be active soon */
10195         ufshcd_enable_irq(hba);
10196
10197         goto out;
10198
10199 disable_vreg:
10200         ufshcd_vreg_set_lpm(hba);
10201 out:
10202         if (ret)
10203                 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
10204         return ret;
10205 }
10206 #endif /* CONFIG_PM */
10207
10208 #ifdef CONFIG_PM_SLEEP
10209 /**
10210  * ufshcd_system_suspend - system suspend callback
10211  * @dev: Device associated with the UFS controller.
10212  *
10213  * Executed before putting the system into a sleep state in which the contents
10214  * of main memory are preserved.
10215  *
10216  * Return: 0 for success and non-zero for failure.
10217  */
10218 int ufshcd_system_suspend(struct device *dev)
10219 {
10220         struct ufs_hba *hba = dev_get_drvdata(dev);
10221         int ret = 0;
10222         ktime_t start = ktime_get();
10223
10224         if (pm_runtime_suspended(hba->dev))
10225                 goto out;
10226
10227         ret = ufshcd_suspend(hba);
10228 out:
10229         trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
10230                 ktime_to_us(ktime_sub(ktime_get(), start)),
10231                 hba->curr_dev_pwr_mode, hba->uic_link_state);
10232         return ret;
10233 }
10234 EXPORT_SYMBOL(ufshcd_system_suspend);
10235
10236 /**
10237  * ufshcd_system_resume - system resume callback
10238  * @dev: Device associated with the UFS controller.
10239  *
10240  * Executed after waking the system up from a sleep state in which the contents
10241  * of main memory were preserved.
10242  *
10243  * Return: 0 for success and non-zero for failure.
10244  */
10245 int ufshcd_system_resume(struct device *dev)
10246 {
10247         struct ufs_hba *hba = dev_get_drvdata(dev);
10248         ktime_t start = ktime_get();
10249         int ret = 0;
10250
10251         if (pm_runtime_suspended(hba->dev))
10252                 goto out;
10253
10254         ret = ufshcd_resume(hba);
10255
10256 out:
10257         trace_ufshcd_system_resume(dev_name(hba->dev), ret,
10258                 ktime_to_us(ktime_sub(ktime_get(), start)),
10259                 hba->curr_dev_pwr_mode, hba->uic_link_state);
10260
10261         return ret;
10262 }
10263 EXPORT_SYMBOL(ufshcd_system_resume);
10264 #endif /* CONFIG_PM_SLEEP */
10265
10266 #ifdef CONFIG_PM
10267 /**
10268  * ufshcd_runtime_suspend - runtime suspend callback
10269  * @dev: Device associated with the UFS controller.
10270  *
10271  * Check the description of ufshcd_suspend() function for more details.
10272  *
10273  * Return: 0 for success and non-zero for failure.
10274  */
10275 int ufshcd_runtime_suspend(struct device *dev)
10276 {
10277         struct ufs_hba *hba = dev_get_drvdata(dev);
10278         int ret;
10279         ktime_t start = ktime_get();
10280
10281         ret = ufshcd_suspend(hba);
10282
10283         trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
10284                 ktime_to_us(ktime_sub(ktime_get(), start)),
10285                 hba->curr_dev_pwr_mode, hba->uic_link_state);
10286         return ret;
10287 }
10288 EXPORT_SYMBOL(ufshcd_runtime_suspend);
10289
10290 /**
10291  * ufshcd_runtime_resume - runtime resume routine
10292  * @dev: Device associated with the UFS controller.
10293  *
10294  * This function basically brings controller
10295  * to active state. Following operations are done in this function:
10296  *
10297  * 1. Turn on all the controller related clocks
10298  * 2. Turn ON VCC rail
10299  *
10300  * Return: 0 upon success; < 0 upon failure.
10301  */
10302 int ufshcd_runtime_resume(struct device *dev)
10303 {
10304         struct ufs_hba *hba = dev_get_drvdata(dev);
10305         int ret;
10306         ktime_t start = ktime_get();
10307
10308         ret = ufshcd_resume(hba);
10309
10310         trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
10311                 ktime_to_us(ktime_sub(ktime_get(), start)),
10312                 hba->curr_dev_pwr_mode, hba->uic_link_state);
10313         return ret;
10314 }
10315 EXPORT_SYMBOL(ufshcd_runtime_resume);
10316 #endif /* CONFIG_PM */
10317
10318 static void ufshcd_wl_shutdown(struct device *dev)
10319 {
10320         struct scsi_device *sdev = to_scsi_device(dev);
10321         struct ufs_hba *hba = shost_priv(sdev->host);
10322
10323         down(&hba->host_sem);
10324         hba->shutting_down = true;
10325         up(&hba->host_sem);
10326
10327         /* Turn on everything while shutting down */
10328         ufshcd_rpm_get_sync(hba);
10329         scsi_device_quiesce(sdev);
10330         shost_for_each_device(sdev, hba->host) {
10331                 if (sdev == hba->ufs_device_wlun)
10332                         continue;
10333                 scsi_device_quiesce(sdev);
10334         }
10335         __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10336
10337         /*
10338          * Next, turn off the UFS controller and the UFS regulators. Disable
10339          * clocks.
10340          */
10341         if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
10342                 ufshcd_suspend(hba);
10343
10344         hba->is_powered = false;
10345 }
10346
10347 /**
10348  * ufshcd_remove - de-allocate SCSI host and host memory space
10349  *              data structure memory
10350  * @hba: per adapter instance
10351  */
10352 void ufshcd_remove(struct ufs_hba *hba)
10353 {
10354         if (hba->ufs_device_wlun)
10355                 ufshcd_rpm_get_sync(hba);
10356         ufs_hwmon_remove(hba);
10357         ufs_bsg_remove(hba);
10358         ufs_sysfs_remove_nodes(hba->dev);
10359         blk_mq_destroy_queue(hba->tmf_queue);
10360         blk_put_queue(hba->tmf_queue);
10361         blk_mq_free_tag_set(&hba->tmf_tag_set);
10362         scsi_remove_host(hba->host);
10363         /* disable interrupts */
10364         ufshcd_disable_intr(hba, hba->intr_mask);
10365         ufshcd_hba_stop(hba);
10366         ufshcd_hba_exit(hba);
10367 }
10368 EXPORT_SYMBOL_GPL(ufshcd_remove);
10369
10370 #ifdef CONFIG_PM_SLEEP
10371 int ufshcd_system_freeze(struct device *dev)
10372 {
10373
10374         return ufshcd_system_suspend(dev);
10375
10376 }
10377 EXPORT_SYMBOL_GPL(ufshcd_system_freeze);
10378
10379 int ufshcd_system_restore(struct device *dev)
10380 {
10381
10382         struct ufs_hba *hba = dev_get_drvdata(dev);
10383         int ret;
10384
10385         ret = ufshcd_system_resume(dev);
10386         if (ret)
10387                 return ret;
10388
10389         /* Configure UTRL and UTMRL base address registers */
10390         ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
10391                         REG_UTP_TRANSFER_REQ_LIST_BASE_L);
10392         ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
10393                         REG_UTP_TRANSFER_REQ_LIST_BASE_H);
10394         ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
10395                         REG_UTP_TASK_REQ_LIST_BASE_L);
10396         ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
10397                         REG_UTP_TASK_REQ_LIST_BASE_H);
10398         /*
10399          * Make sure that UTRL and UTMRL base address registers
10400          * are updated with the latest queue addresses. Only after
10401          * updating these addresses, we can queue the new commands.
10402          */
10403         mb();
10404
10405         /* Resuming from hibernate, assume that link was OFF */
10406         ufshcd_set_link_off(hba);
10407
10408         return 0;
10409
10410 }
10411 EXPORT_SYMBOL_GPL(ufshcd_system_restore);
10412
10413 int ufshcd_system_thaw(struct device *dev)
10414 {
10415         return ufshcd_system_resume(dev);
10416 }
10417 EXPORT_SYMBOL_GPL(ufshcd_system_thaw);
10418 #endif /* CONFIG_PM_SLEEP  */
10419
10420 /**
10421  * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
10422  * @hba: pointer to Host Bus Adapter (HBA)
10423  */
10424 void ufshcd_dealloc_host(struct ufs_hba *hba)
10425 {
10426         scsi_host_put(hba->host);
10427 }
10428 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
10429
10430 /**
10431  * ufshcd_set_dma_mask - Set dma mask based on the controller
10432  *                       addressing capability
10433  * @hba: per adapter instance
10434  *
10435  * Return: 0 for success, non-zero for failure.
10436  */
10437 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
10438 {
10439         if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
10440                 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
10441                         return 0;
10442         }
10443         return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
10444 }
10445
10446 /**
10447  * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
10448  * @dev: pointer to device handle
10449  * @hba_handle: driver private handle
10450  *
10451  * Return: 0 on success, non-zero value on failure.
10452  */
10453 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
10454 {
10455         struct Scsi_Host *host;
10456         struct ufs_hba *hba;
10457         int err = 0;
10458
10459         if (!dev) {
10460                 dev_err(dev,
10461                 "Invalid memory reference for dev is NULL\n");
10462                 err = -ENODEV;
10463                 goto out_error;
10464         }
10465
10466         host = scsi_host_alloc(&ufshcd_driver_template,
10467                                 sizeof(struct ufs_hba));
10468         if (!host) {
10469                 dev_err(dev, "scsi_host_alloc failed\n");
10470                 err = -ENOMEM;
10471                 goto out_error;
10472         }
10473         host->nr_maps = HCTX_TYPE_POLL + 1;
10474         hba = shost_priv(host);
10475         hba->host = host;
10476         hba->dev = dev;
10477         hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
10478         hba->nop_out_timeout = NOP_OUT_TIMEOUT;
10479         ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry));
10480         INIT_LIST_HEAD(&hba->clk_list_head);
10481         spin_lock_init(&hba->outstanding_lock);
10482
10483         *hba_handle = hba;
10484
10485 out_error:
10486         return err;
10487 }
10488 EXPORT_SYMBOL(ufshcd_alloc_host);
10489
10490 /* This function exists because blk_mq_alloc_tag_set() requires this. */
10491 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
10492                                      const struct blk_mq_queue_data *qd)
10493 {
10494         WARN_ON_ONCE(true);
10495         return BLK_STS_NOTSUPP;
10496 }
10497
10498 static const struct blk_mq_ops ufshcd_tmf_ops = {
10499         .queue_rq = ufshcd_queue_tmf,
10500 };
10501
10502 /**
10503  * ufshcd_init - Driver initialization routine
10504  * @hba: per-adapter instance
10505  * @mmio_base: base register address
10506  * @irq: Interrupt line of device
10507  *
10508  * Return: 0 on success, non-zero value on failure.
10509  */
10510 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
10511 {
10512         int err;
10513         struct Scsi_Host *host = hba->host;
10514         struct device *dev = hba->dev;
10515         char eh_wq_name[sizeof("ufs_eh_wq_00")];
10516
10517         /*
10518          * dev_set_drvdata() must be called before any callbacks are registered
10519          * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
10520          * sysfs).
10521          */
10522         dev_set_drvdata(dev, hba);
10523
10524         if (!mmio_base) {
10525                 dev_err(hba->dev,
10526                 "Invalid memory reference for mmio_base is NULL\n");
10527                 err = -ENODEV;
10528                 goto out_error;
10529         }
10530
10531         hba->mmio_base = mmio_base;
10532         hba->irq = irq;
10533         hba->vps = &ufs_hba_vps;
10534
10535         err = ufshcd_hba_init(hba);
10536         if (err)
10537                 goto out_error;
10538
10539         /* Read capabilities registers */
10540         err = ufshcd_hba_capabilities(hba);
10541         if (err)
10542                 goto out_disable;
10543
10544         /* Get UFS version supported by the controller */
10545         hba->ufs_version = ufshcd_get_ufs_version(hba);
10546
10547         /* Get Interrupt bit mask per version */
10548         hba->intr_mask = ufshcd_get_intr_mask(hba);
10549
10550         err = ufshcd_set_dma_mask(hba);
10551         if (err) {
10552                 dev_err(hba->dev, "set dma mask failed\n");
10553                 goto out_disable;
10554         }
10555
10556         /* Allocate memory for host memory space */
10557         err = ufshcd_memory_alloc(hba);
10558         if (err) {
10559                 dev_err(hba->dev, "Memory allocation failed\n");
10560                 goto out_disable;
10561         }
10562
10563         /* Configure LRB */
10564         ufshcd_host_memory_configure(hba);
10565
10566         host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
10567         host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
10568         host->max_id = UFSHCD_MAX_ID;
10569         host->max_lun = UFS_MAX_LUNS;
10570         host->max_channel = UFSHCD_MAX_CHANNEL;
10571         host->unique_id = host->host_no;
10572         host->max_cmd_len = UFS_CDB_SIZE;
10573         host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING);
10574
10575         /* Use default RPM delay if host not set */
10576         if (host->rpm_autosuspend_delay == 0)
10577                 host->rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS;
10578
10579         hba->max_pwr_info.is_valid = false;
10580
10581         /* Initialize work queues */
10582         snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
10583                  hba->host->host_no);
10584         hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
10585         if (!hba->eh_wq) {
10586                 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
10587                         __func__);
10588                 err = -ENOMEM;
10589                 goto out_disable;
10590         }
10591         INIT_WORK(&hba->eh_work, ufshcd_err_handler);
10592         INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
10593
10594         sema_init(&hba->host_sem, 1);
10595
10596         /* Initialize UIC command mutex */
10597         mutex_init(&hba->uic_cmd_mutex);
10598
10599         /* Initialize mutex for device management commands */
10600         mutex_init(&hba->dev_cmd.lock);
10601
10602         /* Initialize mutex for exception event control */
10603         mutex_init(&hba->ee_ctrl_mutex);
10604
10605         mutex_init(&hba->wb_mutex);
10606         init_rwsem(&hba->clk_scaling_lock);
10607
10608         ufshcd_init_clk_gating(hba);
10609
10610         ufshcd_init_clk_scaling(hba);
10611
10612         /*
10613          * In order to avoid any spurious interrupt immediately after
10614          * registering UFS controller interrupt handler, clear any pending UFS
10615          * interrupt status and disable all the UFS interrupts.
10616          */
10617         ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
10618                       REG_INTERRUPT_STATUS);
10619         ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
10620         /*
10621          * Make sure that UFS interrupts are disabled and any pending interrupt
10622          * status is cleared before registering UFS interrupt handler.
10623          */
10624         mb();
10625
10626         /* IRQ registration */
10627         err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
10628         if (err) {
10629                 dev_err(hba->dev, "request irq failed\n");
10630                 goto out_disable;
10631         } else {
10632                 hba->is_irq_enabled = true;
10633         }
10634
10635         if (!is_mcq_supported(hba)) {
10636                 err = scsi_add_host(host, hba->dev);
10637                 if (err) {
10638                         dev_err(hba->dev, "scsi_add_host failed\n");
10639                         goto out_disable;
10640                 }
10641         }
10642
10643         hba->tmf_tag_set = (struct blk_mq_tag_set) {
10644                 .nr_hw_queues   = 1,
10645                 .queue_depth    = hba->nutmrs,
10646                 .ops            = &ufshcd_tmf_ops,
10647                 .flags          = BLK_MQ_F_NO_SCHED,
10648         };
10649         err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
10650         if (err < 0)
10651                 goto out_remove_scsi_host;
10652         hba->tmf_queue = blk_mq_alloc_queue(&hba->tmf_tag_set, NULL, NULL);
10653         if (IS_ERR(hba->tmf_queue)) {
10654                 err = PTR_ERR(hba->tmf_queue);
10655                 goto free_tmf_tag_set;
10656         }
10657         hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
10658                                     sizeof(*hba->tmf_rqs), GFP_KERNEL);
10659         if (!hba->tmf_rqs) {
10660                 err = -ENOMEM;
10661                 goto free_tmf_queue;
10662         }
10663
10664         /* Reset the attached device */
10665         ufshcd_device_reset(hba);
10666
10667         ufshcd_init_crypto(hba);
10668
10669         /* Host controller enable */
10670         err = ufshcd_hba_enable(hba);
10671         if (err) {
10672                 dev_err(hba->dev, "Host controller enable failed\n");
10673                 ufshcd_print_evt_hist(hba);
10674                 ufshcd_print_host_state(hba);
10675                 goto free_tmf_queue;
10676         }
10677
10678         /*
10679          * Set the default power management level for runtime and system PM.
10680          * Default power saving mode is to keep UFS link in Hibern8 state
10681          * and UFS device in sleep state.
10682          */
10683         hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10684                                                 UFS_SLEEP_PWR_MODE,
10685                                                 UIC_LINK_HIBERN8_STATE);
10686         hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
10687                                                 UFS_SLEEP_PWR_MODE,
10688                                                 UIC_LINK_HIBERN8_STATE);
10689
10690         INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, ufshcd_rpm_dev_flush_recheck_work);
10691         INIT_DELAYED_WORK(&hba->ufs_rtc_update_work, ufshcd_rtc_work);
10692
10693         /* Set the default auto-hiberate idle timer value to 150 ms */
10694         if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
10695                 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
10696                             FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
10697         }
10698
10699         /* Hold auto suspend until async scan completes */
10700         pm_runtime_get_sync(dev);
10701         atomic_set(&hba->scsi_block_reqs_cnt, 0);
10702         /*
10703          * We are assuming that device wasn't put in sleep/power-down
10704          * state exclusively during the boot stage before kernel.
10705          * This assumption helps avoid doing link startup twice during
10706          * ufshcd_probe_hba().
10707          */
10708         ufshcd_set_ufs_dev_active(hba);
10709
10710         async_schedule(ufshcd_async_scan, hba);
10711         ufs_sysfs_add_nodes(hba->dev);
10712
10713         device_enable_async_suspend(dev);
10714         ufshcd_pm_qos_init(hba);
10715         return 0;
10716
10717 free_tmf_queue:
10718         blk_mq_destroy_queue(hba->tmf_queue);
10719         blk_put_queue(hba->tmf_queue);
10720 free_tmf_tag_set:
10721         blk_mq_free_tag_set(&hba->tmf_tag_set);
10722 out_remove_scsi_host:
10723         scsi_remove_host(hba->host);
10724 out_disable:
10725         hba->is_irq_enabled = false;
10726         ufshcd_hba_exit(hba);
10727 out_error:
10728         return err;
10729 }
10730 EXPORT_SYMBOL_GPL(ufshcd_init);
10731
10732 void ufshcd_resume_complete(struct device *dev)
10733 {
10734         struct ufs_hba *hba = dev_get_drvdata(dev);
10735
10736         if (hba->complete_put) {
10737                 ufshcd_rpm_put(hba);
10738                 hba->complete_put = false;
10739         }
10740 }
10741 EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
10742
10743 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
10744 {
10745         struct device *dev = &hba->ufs_device_wlun->sdev_gendev;
10746         enum ufs_dev_pwr_mode dev_pwr_mode;
10747         enum uic_link_state link_state;
10748         unsigned long flags;
10749         bool res;
10750
10751         spin_lock_irqsave(&dev->power.lock, flags);
10752         dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
10753         link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
10754         res = pm_runtime_suspended(dev) &&
10755               hba->curr_dev_pwr_mode == dev_pwr_mode &&
10756               hba->uic_link_state == link_state &&
10757               !hba->dev_info.b_rpm_dev_flush_capable;
10758         spin_unlock_irqrestore(&dev->power.lock, flags);
10759
10760         return res;
10761 }
10762
10763 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
10764 {
10765         struct ufs_hba *hba = dev_get_drvdata(dev);
10766         int ret;
10767
10768         /*
10769          * SCSI assumes that runtime-pm and system-pm for scsi drivers
10770          * are same. And it doesn't wake up the device for system-suspend
10771          * if it's runtime suspended. But ufs doesn't follow that.
10772          * Refer ufshcd_resume_complete()
10773          */
10774         if (hba->ufs_device_wlun) {
10775                 /* Prevent runtime suspend */
10776                 ufshcd_rpm_get_noresume(hba);
10777                 /*
10778                  * Check if already runtime suspended in same state as system
10779                  * suspend would be.
10780                  */
10781                 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
10782                         /* RPM state is not ok for SPM, so runtime resume */
10783                         ret = ufshcd_rpm_resume(hba);
10784                         if (ret < 0 && ret != -EACCES) {
10785                                 ufshcd_rpm_put(hba);
10786                                 return ret;
10787                         }
10788                 }
10789                 hba->complete_put = true;
10790         }
10791         return 0;
10792 }
10793 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
10794
10795 int ufshcd_suspend_prepare(struct device *dev)
10796 {
10797         return __ufshcd_suspend_prepare(dev, true);
10798 }
10799 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
10800
10801 #ifdef CONFIG_PM_SLEEP
10802 static int ufshcd_wl_poweroff(struct device *dev)
10803 {
10804         struct scsi_device *sdev = to_scsi_device(dev);
10805         struct ufs_hba *hba = shost_priv(sdev->host);
10806
10807         __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
10808         return 0;
10809 }
10810 #endif
10811
10812 static int ufshcd_wl_probe(struct device *dev)
10813 {
10814         struct scsi_device *sdev = to_scsi_device(dev);
10815
10816         if (!is_device_wlun(sdev))
10817                 return -ENODEV;
10818
10819         blk_pm_runtime_init(sdev->request_queue, dev);
10820         pm_runtime_set_autosuspend_delay(dev, 0);
10821         pm_runtime_allow(dev);
10822
10823         return  0;
10824 }
10825
10826 static int ufshcd_wl_remove(struct device *dev)
10827 {
10828         pm_runtime_forbid(dev);
10829         return 0;
10830 }
10831
10832 static const struct dev_pm_ops ufshcd_wl_pm_ops = {
10833 #ifdef CONFIG_PM_SLEEP
10834         .suspend = ufshcd_wl_suspend,
10835         .resume = ufshcd_wl_resume,
10836         .freeze = ufshcd_wl_suspend,
10837         .thaw = ufshcd_wl_resume,
10838         .poweroff = ufshcd_wl_poweroff,
10839         .restore = ufshcd_wl_resume,
10840 #endif
10841         SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
10842 };
10843
10844 static void ufshcd_check_header_layout(void)
10845 {
10846         /*
10847          * gcc compilers before version 10 cannot do constant-folding for
10848          * sub-byte bitfields. Hence skip the layout checks for gcc 9 and
10849          * before.
10850          */
10851         if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000)
10852                 return;
10853
10854         BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10855                                 .cci = 3})[0] != 3);
10856
10857         BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10858                                 .ehs_length = 2})[1] != 2);
10859
10860         BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10861                                 .enable_crypto = 1})[2]
10862                      != 0x80);
10863
10864         BUILD_BUG_ON((((u8 *)&(struct request_desc_header){
10865                                         .command_type = 5,
10866                                         .data_direction = 3,
10867                                         .interrupt = 1,
10868                                 })[3]) != ((5 << 4) | (3 << 1) | 1));
10869
10870         BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
10871                                 .dunl = cpu_to_le32(0xdeadbeef)})[1] !=
10872                 cpu_to_le32(0xdeadbeef));
10873
10874         BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10875                                 .ocs = 4})[8] != 4);
10876
10877         BUILD_BUG_ON(((u8 *)&(struct request_desc_header){
10878                                 .cds = 5})[9] != 5);
10879
10880         BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){
10881                                 .dunu = cpu_to_le32(0xbadcafe)})[3] !=
10882                 cpu_to_le32(0xbadcafe));
10883
10884         BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
10885                              .iid = 0xf })[4] != 0xf0);
10886
10887         BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){
10888                              .command_set_type = 0xf })[4] != 0xf);
10889 }
10890
10891 /*
10892  * ufs_dev_wlun_template - describes ufs device wlun
10893  * ufs-device wlun - used to send pm commands
10894  * All luns are consumers of ufs-device wlun.
10895  *
10896  * Currently, no sd driver is present for wluns.
10897  * Hence the no specific pm operations are performed.
10898  * With ufs design, SSU should be sent to ufs-device wlun.
10899  * Hence register a scsi driver for ufs wluns only.
10900  */
10901 static struct scsi_driver ufs_dev_wlun_template = {
10902         .gendrv = {
10903                 .name = "ufs_device_wlun",
10904                 .owner = THIS_MODULE,
10905                 .probe = ufshcd_wl_probe,
10906                 .remove = ufshcd_wl_remove,
10907                 .pm = &ufshcd_wl_pm_ops,
10908                 .shutdown = ufshcd_wl_shutdown,
10909         },
10910 };
10911
10912 static int __init ufshcd_core_init(void)
10913 {
10914         int ret;
10915
10916         ufshcd_check_header_layout();
10917
10918         ufs_debugfs_init();
10919
10920         ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
10921         if (ret)
10922                 ufs_debugfs_exit();
10923         return ret;
10924 }
10925
10926 static void __exit ufshcd_core_exit(void)
10927 {
10928         ufs_debugfs_exit();
10929         scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
10930 }
10931
10932 module_init(ufshcd_core_init);
10933 module_exit(ufshcd_core_exit);
10934
10935 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
10936 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
10937 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
10938 MODULE_SOFTDEP("pre: governor_simpleondemand");
10939 MODULE_LICENSE("GPL");