drivers/ufs/core/ufshcd-crypto.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2019 Google LLC
   4  */
   5
   6 #include <ufs/ufshcd.h>
   7 #include "ufshcd-crypto.h"
   8
   9 /* Blk-crypto modes supported by UFS crypto */
  10 static const struct ufs_crypto_alg_entry {
  11         enum ufs_crypto_alg ufs_alg;
  12         enum ufs_crypto_key_size ufs_key_size;
  13 } ufs_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
  14         [BLK_ENCRYPTION_MODE_AES_256_XTS] = {
  15                 .ufs_alg = UFS_CRYPTO_ALG_AES_XTS,
  16                 .ufs_key_size = UFS_CRYPTO_KEY_SIZE_256,
  17         },
  18 };
  19
  20 static int ufshcd_program_key(struct ufs_hba *hba,
  21                               const union ufs_crypto_cfg_entry *cfg, int slot)
  22 {
  23         int i;
  24         u32 slot_offset = hba->crypto_cfg_register + slot * sizeof(*cfg);
  25         int err = 0;
  26
  27         ufshcd_hold(hba);
  28
  29         if (hba->vops && hba->vops->program_key) {
  30                 err = hba->vops->program_key(hba, cfg, slot);
  31                 goto out;
  32         }
  33
  34         /* Ensure that CFGE is cleared before programming the key */
  35         ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
  36         for (i = 0; i < 16; i++) {
  37                 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]),
  38                               slot_offset + i * sizeof(cfg->reg_val[0]));
  39         }
  40         /* Write dword 17 */
  41         ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[17]),
  42                       slot_offset + 17 * sizeof(cfg->reg_val[0]));
  43         /* Dword 16 must be written last */
  44         ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[16]),
  45                       slot_offset + 16 * sizeof(cfg->reg_val[0]));
  46 out:
  47         ufshcd_release(hba);
  48         return err;
  49 }
  50
  51 static int ufshcd_crypto_keyslot_program(struct blk_crypto_profile *profile,
  52                                          const struct blk_crypto_key *key,
  53                                          unsigned int slot)
  54 {
  55         struct ufs_hba *hba =
  56                 container_of(profile, struct ufs_hba, crypto_profile);
  57         const union ufs_crypto_cap_entry *ccap_array = hba->crypto_cap_array;
  58         const struct ufs_crypto_alg_entry *alg =
  59                         &ufs_crypto_algs[key->crypto_cfg.crypto_mode];
  60         u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
  61         int i;
  62         int cap_idx = -1;
  63         union ufs_crypto_cfg_entry cfg = {};
  64         int err;
  65
  66         BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
  67         for (i = 0; i < hba->crypto_capabilities.num_crypto_cap; i++) {
  68                 if (ccap_array[i].algorithm_id == alg->ufs_alg &&
  69                     ccap_array[i].key_size == alg->ufs_key_size &&
  70                     (ccap_array[i].sdus_mask & data_unit_mask)) {
  71                         cap_idx = i;
  72                         break;
  73                 }
  74         }
  75
  76         if (WARN_ON(cap_idx < 0))
  77                 return -EOPNOTSUPP;
  78
  79         cfg.data_unit_size = data_unit_mask;
  80         cfg.crypto_cap_idx = cap_idx;
  81         cfg.config_enable = UFS_CRYPTO_CONFIGURATION_ENABLE;
  82
  83         if (ccap_array[cap_idx].algorithm_id == UFS_CRYPTO_ALG_AES_XTS) {
  84                 /* In XTS mode, the blk_crypto_key's size is already doubled */
  85                 memcpy(cfg.crypto_key, key->raw, key->size/2);
  86                 memcpy(cfg.crypto_key + UFS_CRYPTO_KEY_MAX_SIZE/2,
  87                        key->raw + key->size/2, key->size/2);
  88         } else {
  89                 memcpy(cfg.crypto_key, key->raw, key->size);
  90         }
  91
  92         err = ufshcd_program_key(hba, &cfg, slot);
  93
  94         memzero_explicit(&cfg, sizeof(cfg));
  95         return err;
  96 }
  97
  98 static int ufshcd_clear_keyslot(struct ufs_hba *hba, int slot)
  99 {
 100         /*
 101          * Clear the crypto cfg on the device. Clearing CFGE
 102          * might not be sufficient, so just clear the entire cfg.
 103          */
 104         union ufs_crypto_cfg_entry cfg = {};
 105
 106         return ufshcd_program_key(hba, &cfg, slot);
 107 }
 108
 109 static int ufshcd_crypto_keyslot_evict(struct blk_crypto_profile *profile,
 110                                        const struct blk_crypto_key *key,
 111                                        unsigned int slot)
 112 {
 113         struct ufs_hba *hba =
 114                 container_of(profile, struct ufs_hba, crypto_profile);
 115
 116         return ufshcd_clear_keyslot(hba, slot);
 117 }
 118
 119 bool ufshcd_crypto_enable(struct ufs_hba *hba)
 120 {
 121         if (!(hba->caps & UFSHCD_CAP_CRYPTO))
 122                 return false;
 123
 124         /* Reset might clear all keys, so reprogram all the keys. */
 125         blk_crypto_reprogram_all_keys(&hba->crypto_profile);
 126         return true;
 127 }
 128
 129 static const struct blk_crypto_ll_ops ufshcd_crypto_ops = {
 130         .keyslot_program        = ufshcd_crypto_keyslot_program,
 131         .keyslot_evict          = ufshcd_crypto_keyslot_evict,
 132 };
 133
 134 static enum blk_crypto_mode_num
 135 ufshcd_find_blk_crypto_mode(union ufs_crypto_cap_entry cap)
 136 {
 137         int i;
 138
 139         for (i = 0; i < ARRAY_SIZE(ufs_crypto_algs); i++) {
 140                 BUILD_BUG_ON(UFS_CRYPTO_KEY_SIZE_INVALID != 0);
 141                 if (ufs_crypto_algs[i].ufs_alg == cap.algorithm_id &&
 142                     ufs_crypto_algs[i].ufs_key_size == cap.key_size) {
 143                         return i;
 144                 }
 145         }
 146         return BLK_ENCRYPTION_MODE_INVALID;
 147 }
 148
 149 /**
 150  * ufshcd_hba_init_crypto_capabilities - Read crypto capabilities, init crypto
 151  *                                       fields in hba
 152  * @hba: Per adapter instance
 153  *
 154  * Return: 0 if crypto was initialized or is not supported, else a -errno value.
 155  */
 156 int ufshcd_hba_init_crypto_capabilities(struct ufs_hba *hba)
 157 {
 158         int cap_idx;
 159         int err = 0;
 160         enum blk_crypto_mode_num blk_mode_num;
 161
 162         /*
 163          * Don't use crypto if either the hardware doesn't advertise the
 164          * standard crypto capability bit *or* if the vendor specific driver
 165          * hasn't advertised that crypto is supported.
 166          */
 167         if (!(hba->capabilities & MASK_CRYPTO_SUPPORT) ||
 168             !(hba->caps & UFSHCD_CAP_CRYPTO))
 169                 goto out;
 170
 171         hba->crypto_capabilities.reg_val =
 172                         cpu_to_le32(ufshcd_readl(hba, REG_UFS_CCAP));
 173         hba->crypto_cfg_register =
 174                 (u32)hba->crypto_capabilities.config_array_ptr * 0x100;
 175         hba->crypto_cap_array =
 176                 devm_kcalloc(hba->dev, hba->crypto_capabilities.num_crypto_cap,
 177                              sizeof(hba->crypto_cap_array[0]), GFP_KERNEL);
 178         if (!hba->crypto_cap_array) {
 179                 err = -ENOMEM;
 180                 goto out;
 181         }
 182
 183         /* The actual number of configurations supported is (CFGC+1) */
 184         err = devm_blk_crypto_profile_init(
 185                         hba->dev, &hba->crypto_profile,
 186                         hba->crypto_capabilities.config_count + 1);
 187         if (err)
 188                 goto out;
 189
 190         hba->crypto_profile.ll_ops = ufshcd_crypto_ops;
 191         /* UFS only supports 8 bytes for any DUN */
 192         hba->crypto_profile.max_dun_bytes_supported = 8;
 193         hba->crypto_profile.dev = hba->dev;
 194
 195         /*
 196          * Cache all the UFS crypto capabilities and advertise the supported
 197          * crypto modes and data unit sizes to the block layer.
 198          */
 199         for (cap_idx = 0; cap_idx < hba->crypto_capabilities.num_crypto_cap;
 200              cap_idx++) {
 201                 hba->crypto_cap_array[cap_idx].reg_val =
 202                         cpu_to_le32(ufshcd_readl(hba,
 203                                                  REG_UFS_CRYPTOCAP +
 204                                                  cap_idx * sizeof(__le32)));
 205                 blk_mode_num = ufshcd_find_blk_crypto_mode(
 206                                                 hba->crypto_cap_array[cap_idx]);
 207                 if (blk_mode_num != BLK_ENCRYPTION_MODE_INVALID)
 208                         hba->crypto_profile.modes_supported[blk_mode_num] |=
 209                                 hba->crypto_cap_array[cap_idx].sdus_mask * 512;
 210         }
 211
 212         return 0;
 213
 214 out:
 215         /* Indicate that init failed by clearing UFSHCD_CAP_CRYPTO */
 216         hba->caps &= ~UFSHCD_CAP_CRYPTO;
 217         return err;
 218 }
 219
 220 /**
 221  * ufshcd_init_crypto - Initialize crypto hardware
 222  * @hba: Per adapter instance
 223  */
 224 void ufshcd_init_crypto(struct ufs_hba *hba)
 225 {
 226         int slot;
 227
 228         if (!(hba->caps & UFSHCD_CAP_CRYPTO))
 229                 return;
 230
 231         /* Clear all keyslots - the number of keyslots is (CFGC + 1) */
 232         for (slot = 0; slot < hba->crypto_capabilities.config_count + 1; slot++)
 233                 ufshcd_clear_keyslot(hba, slot);
 234 }
 235
 236 void ufshcd_crypto_register(struct ufs_hba *hba, struct request_queue *q)
 237 {
 238         if (hba->caps & UFSHCD_CAP_CRYPTO)
 239                 blk_crypto_register(&hba->crypto_profile, q);
 240 }