drivers/tty/synclink_gt.c

   1 // SPDX-License-Identifier: GPL-1.0+
   2 /*
   3  * Device driver for Microgate SyncLink GT serial adapters.
   4  *
   5  * written by Paul Fulghum for Microgate Corporation
   6  * paulkf@microgate.com
   7  *
   8  * Microgate and SyncLink are trademarks of Microgate Corporation
   9  *
  10  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  11  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  12  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  13  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  14  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  15  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  16  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  17  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  18  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  19  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  20  * OF THE POSSIBILITY OF SUCH DAMAGE.
  21  */
  22
  23 /*
  24  * DEBUG OUTPUT DEFINITIONS
  25  *
  26  * uncomment lines below to enable specific types of debug output
  27  *
  28  * DBGINFO   information - most verbose output
  29  * DBGERR    serious errors
  30  * DBGBH     bottom half service routine debugging
  31  * DBGISR    interrupt service routine debugging
  32  * DBGDATA   output receive and transmit data
  33  * DBGTBUF   output transmit DMA buffers and registers
  34  * DBGRBUF   output receive DMA buffers and registers
  35  */
  36
  37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  42 /*#define DBGTBUF(info) dump_tbufs(info)*/
  43 /*#define DBGRBUF(info) dump_rbufs(info)*/
  44
  45
  46 #include <linux/module.h>
  47 #include <linux/errno.h>
  48 #include <linux/signal.h>
  49 #include <linux/sched.h>
  50 #include <linux/timer.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/pci.h>
  53 #include <linux/tty.h>
  54 #include <linux/tty_flip.h>
  55 #include <linux/serial.h>
  56 #include <linux/major.h>
  57 #include <linux/string.h>
  58 #include <linux/fcntl.h>
  59 #include <linux/ptrace.h>
  60 #include <linux/ioport.h>
  61 #include <linux/mm.h>
  62 #include <linux/seq_file.h>
  63 #include <linux/slab.h>
  64 #include <linux/netdevice.h>
  65 #include <linux/vmalloc.h>
  66 #include <linux/init.h>
  67 #include <linux/delay.h>
  68 #include <linux/ioctl.h>
  69 #include <linux/termios.h>
  70 #include <linux/bitops.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/hdlc.h>
  73 #include <linux/synclink.h>
  74
  75 #include <asm/io.h>
  76 #include <asm/irq.h>
  77 #include <asm/dma.h>
  78 #include <asm/types.h>
  79 #include <linux/uaccess.h>
  80
  81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  82 #define SYNCLINK_GENERIC_HDLC 1
  83 #else
  84 #define SYNCLINK_GENERIC_HDLC 0
  85 #endif
  86
  87 /*
  88  * module identification
  89  */
  90 static char *driver_name     = "SyncLink GT";
  91 static char *slgt_driver_name = "synclink_gt";
  92 static char *tty_dev_prefix  = "ttySLG";
  93 MODULE_LICENSE("GPL");
  94 #define MGSL_MAGIC 0x5401
  95 #define MAX_DEVICES 32
  96
  97 static const struct pci_device_id pci_table[] = {
  98         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {0,}, /* terminate list */
 103 };
 104 MODULE_DEVICE_TABLE(pci, pci_table);
 105
 106 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 107 static void remove_one(struct pci_dev *dev);
 108 static struct pci_driver pci_driver = {
 109         .name           = "synclink_gt",
 110         .id_table       = pci_table,
 111         .probe          = init_one,
 112         .remove         = remove_one,
 113 };
 114
 115 static bool pci_registered;
 116
 117 /*
 118  * module configuration and status
 119  */
 120 static struct slgt_info *slgt_device_list;
 121 static int slgt_device_count;
 122
 123 static int ttymajor;
 124 static int debug_level;
 125 static int maxframe[MAX_DEVICES];
 126
 127 module_param(ttymajor, int, 0);
 128 module_param(debug_level, int, 0);
 129 module_param_array(maxframe, int, NULL, 0);
 130
 131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 134
 135 /*
 136  * tty support and callbacks
 137  */
 138 static struct tty_driver *serial_driver;
 139
 140 static void wait_until_sent(struct tty_struct *tty, int timeout);
 141 static void flush_buffer(struct tty_struct *tty);
 142 static void tx_release(struct tty_struct *tty);
 143
 144 /*
 145  * generic HDLC support
 146  */
 147 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 148
 149
 150 /*
 151  * device specific structures, macros and functions
 152  */
 153
 154 #define SLGT_MAX_PORTS 4
 155 #define SLGT_REG_SIZE  256
 156
 157 /*
 158  * conditional wait facility
 159  */
 160 struct cond_wait {
 161         struct cond_wait *next;
 162         wait_queue_head_t q;
 163         wait_queue_entry_t wait;
 164         unsigned int data;
 165 };
 166 static void flush_cond_wait(struct cond_wait **head);
 167
 168 /*
 169  * DMA buffer descriptor and access macros
 170  */
 171 struct slgt_desc
 172 {
 173         __le16 count;
 174         __le16 status;
 175         __le32 pbuf;  /* physical address of data buffer */
 176         __le32 next;  /* physical address of next descriptor */
 177
 178         /* driver book keeping */
 179         char *buf;          /* virtual  address of data buffer */
 180         unsigned int pdesc; /* physical address of this descriptor */
 181         dma_addr_t buf_dma_addr;
 182         unsigned short buf_count;
 183 };
 184
 185 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 186 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 187 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 188 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 189 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 190 #define desc_count(a)      (le16_to_cpu((a).count))
 191 #define desc_status(a)     (le16_to_cpu((a).status))
 192 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 193 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 194 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 195 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 196 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 197
 198 struct _input_signal_events {
 199         int ri_up;
 200         int ri_down;
 201         int dsr_up;
 202         int dsr_down;
 203         int dcd_up;
 204         int dcd_down;
 205         int cts_up;
 206         int cts_down;
 207 };
 208
 209 /*
 210  * device instance data structure
 211  */
 212 struct slgt_info {
 213         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 214         struct tty_port port;
 215
 216         struct slgt_info *next_device;  /* device list link */
 217
 218         int magic;
 219
 220         char device_name[25];
 221         struct pci_dev *pdev;
 222
 223         int port_count;  /* count of ports on adapter */
 224         int adapter_num; /* adapter instance number */
 225         int port_num;    /* port instance number */
 226
 227         /* array of pointers to port contexts on this adapter */
 228         struct slgt_info *port_array[SLGT_MAX_PORTS];
 229
 230         int                     line;           /* tty line instance number */
 231
 232         struct mgsl_icount      icount;
 233
 234         int                     timeout;
 235         int                     x_char;         /* xon/xoff character */
 236         unsigned int            read_status_mask;
 237         unsigned int            ignore_status_mask;
 238
 239         wait_queue_head_t       status_event_wait_q;
 240         wait_queue_head_t       event_wait_q;
 241         struct timer_list       tx_timer;
 242         struct timer_list       rx_timer;
 243
 244         unsigned int            gpio_present;
 245         struct cond_wait        *gpio_wait_q;
 246
 247         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 248
 249         struct work_struct task;
 250         u32 pending_bh;
 251         bool bh_requested;
 252         bool bh_running;
 253
 254         int isr_overflow;
 255         bool irq_requested;     /* true if IRQ requested */
 256         bool irq_occurred;      /* for diagnostics use */
 257
 258         /* device configuration */
 259
 260         unsigned int bus_type;
 261         unsigned int irq_level;
 262         unsigned long irq_flags;
 263
 264         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 265         u32 phys_reg_addr;
 266         bool reg_addr_requested;
 267
 268         MGSL_PARAMS params;       /* communications parameters */
 269         u32 idle_mode;
 270         u32 max_frame_size;       /* as set by device config */
 271
 272         unsigned int rbuf_fill_level;
 273         unsigned int rx_pio;
 274         unsigned int if_mode;
 275         unsigned int base_clock;
 276         unsigned int xsync;
 277         unsigned int xctrl;
 278
 279         /* device status */
 280
 281         bool rx_enabled;
 282         bool rx_restart;
 283
 284         bool tx_enabled;
 285         bool tx_active;
 286
 287         unsigned char signals;    /* serial signal states */
 288         int init_error;  /* initialization error */
 289
 290         unsigned char *tx_buf;
 291         int tx_count;
 292
 293         char *flag_buf;
 294         bool drop_rts_on_tx_done;
 295         struct  _input_signal_events    input_signal_events;
 296
 297         int dcd_chkcount;       /* check counts to prevent */
 298         int cts_chkcount;       /* too many IRQs if a signal */
 299         int dsr_chkcount;       /* is floating */
 300         int ri_chkcount;
 301
 302         char *bufs;             /* virtual address of DMA buffer lists */
 303         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 304
 305         unsigned int rbuf_count;
 306         struct slgt_desc *rbufs;
 307         unsigned int rbuf_current;
 308         unsigned int rbuf_index;
 309         unsigned int rbuf_fill_index;
 310         unsigned short rbuf_fill_count;
 311
 312         unsigned int tbuf_count;
 313         struct slgt_desc *tbufs;
 314         unsigned int tbuf_current;
 315         unsigned int tbuf_start;
 316
 317         unsigned char *tmp_rbuf;
 318         unsigned int tmp_rbuf_count;
 319
 320         /* SPPP/Cisco HDLC device parts */
 321
 322         int netcount;
 323         spinlock_t netlock;
 324 #if SYNCLINK_GENERIC_HDLC
 325         struct net_device *netdev;
 326 #endif
 327
 328 };
 329
 330 static MGSL_PARAMS default_params = {
 331         .mode            = MGSL_MODE_HDLC,
 332         .loopback        = 0,
 333         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 334         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 335         .clock_speed     = 0,
 336         .addr_filter     = 0xff,
 337         .crc_type        = HDLC_CRC_16_CCITT,
 338         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 339         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 340         .data_rate       = 9600,
 341         .data_bits       = 8,
 342         .stop_bits       = 1,
 343         .parity          = ASYNC_PARITY_NONE
 344 };
 345
 346
 347 #define BH_RECEIVE  1
 348 #define BH_TRANSMIT 2
 349 #define BH_STATUS   4
 350 #define IO_PIN_SHUTDOWN_LIMIT 100
 351
 352 #define DMABUFSIZE 256
 353 #define DESC_LIST_SIZE 4096
 354
 355 #define MASK_PARITY  BIT1
 356 #define MASK_FRAMING BIT0
 357 #define MASK_BREAK   BIT14
 358 #define MASK_OVERRUN BIT4
 359
 360 #define GSR   0x00 /* global status */
 361 #define JCR   0x04 /* JTAG control */
 362 #define IODR  0x08 /* GPIO direction */
 363 #define IOER  0x0c /* GPIO interrupt enable */
 364 #define IOVR  0x10 /* GPIO value */
 365 #define IOSR  0x14 /* GPIO interrupt status */
 366 #define TDR   0x80 /* tx data */
 367 #define RDR   0x80 /* rx data */
 368 #define TCR   0x82 /* tx control */
 369 #define TIR   0x84 /* tx idle */
 370 #define TPR   0x85 /* tx preamble */
 371 #define RCR   0x86 /* rx control */
 372 #define VCR   0x88 /* V.24 control */
 373 #define CCR   0x89 /* clock control */
 374 #define BDR   0x8a /* baud divisor */
 375 #define SCR   0x8c /* serial control */
 376 #define SSR   0x8e /* serial status */
 377 #define RDCSR 0x90 /* rx DMA control/status */
 378 #define TDCSR 0x94 /* tx DMA control/status */
 379 #define RDDAR 0x98 /* rx DMA descriptor address */
 380 #define TDDAR 0x9c /* tx DMA descriptor address */
 381 #define XSR   0x40 /* extended sync pattern */
 382 #define XCR   0x44 /* extended control */
 383
 384 #define RXIDLE      BIT14
 385 #define RXBREAK     BIT14
 386 #define IRQ_TXDATA  BIT13
 387 #define IRQ_TXIDLE  BIT12
 388 #define IRQ_TXUNDER BIT11 /* HDLC */
 389 #define IRQ_RXDATA  BIT10
 390 #define IRQ_RXIDLE  BIT9  /* HDLC */
 391 #define IRQ_RXBREAK BIT9  /* async */
 392 #define IRQ_RXOVER  BIT8
 393 #define IRQ_DSR     BIT7
 394 #define IRQ_CTS     BIT6
 395 #define IRQ_DCD     BIT5
 396 #define IRQ_RI      BIT4
 397 #define IRQ_ALL     0x3ff0
 398 #define IRQ_MASTER  BIT0
 399
 400 #define slgt_irq_on(info, mask) \
 401         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 402 #define slgt_irq_off(info, mask) \
 403         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 404
 405 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 406 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 407 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 408 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 409 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 410 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 411
 412 static void  msc_set_vcr(struct slgt_info *info);
 413
 414 static int  startup(struct slgt_info *info);
 415 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 416 static void shutdown(struct slgt_info *info);
 417 static void program_hw(struct slgt_info *info);
 418 static void change_params(struct slgt_info *info);
 419
 420 static int  adapter_test(struct slgt_info *info);
 421
 422 static void reset_port(struct slgt_info *info);
 423 static void async_mode(struct slgt_info *info);
 424 static void sync_mode(struct slgt_info *info);
 425
 426 static void rx_stop(struct slgt_info *info);
 427 static void rx_start(struct slgt_info *info);
 428 static void reset_rbufs(struct slgt_info *info);
 429 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 430 static bool rx_get_frame(struct slgt_info *info);
 431 static bool rx_get_buf(struct slgt_info *info);
 432
 433 static void tx_start(struct slgt_info *info);
 434 static void tx_stop(struct slgt_info *info);
 435 static void tx_set_idle(struct slgt_info *info);
 436 static unsigned int tbuf_bytes(struct slgt_info *info);
 437 static void reset_tbufs(struct slgt_info *info);
 438 static void tdma_reset(struct slgt_info *info);
 439 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 440
 441 static void get_gtsignals(struct slgt_info *info);
 442 static void set_gtsignals(struct slgt_info *info);
 443 static void set_rate(struct slgt_info *info, u32 data_rate);
 444
 445 static void bh_transmit(struct slgt_info *info);
 446 static void isr_txeom(struct slgt_info *info, unsigned short status);
 447
 448 static void tx_timeout(struct timer_list *t);
 449 static void rx_timeout(struct timer_list *t);
 450
 451 /*
 452  * ioctl handlers
 453  */
 454 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 455 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 456 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 457 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 458 static int  set_txidle(struct slgt_info *info, int idle_mode);
 459 static int  tx_enable(struct slgt_info *info, int enable);
 460 static int  tx_abort(struct slgt_info *info);
 461 static int  rx_enable(struct slgt_info *info, int enable);
 462 static int  modem_input_wait(struct slgt_info *info,int arg);
 463 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 464 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 465 static int  set_interface(struct slgt_info *info, int if_mode);
 466 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 467 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 468 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 469 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 470 static int  set_xsync(struct slgt_info *info, int if_mode);
 471 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 472 static int  set_xctrl(struct slgt_info *info, int if_mode);
 473
 474 /*
 475  * driver functions
 476  */
 477 static void release_resources(struct slgt_info *info);
 478
 479 /*
 480  * DEBUG OUTPUT CODE
 481  */
 482 #ifndef DBGINFO
 483 #define DBGINFO(fmt)
 484 #endif
 485 #ifndef DBGERR
 486 #define DBGERR(fmt)
 487 #endif
 488 #ifndef DBGBH
 489 #define DBGBH(fmt)
 490 #endif
 491 #ifndef DBGISR
 492 #define DBGISR(fmt)
 493 #endif
 494
 495 #ifdef DBGDATA
 496 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 497 {
 498         int i;
 499         int linecount;
 500         printk("%s %s data:\n",info->device_name, label);
 501         while(count) {
 502                 linecount = (count > 16) ? 16 : count;
 503                 for(i=0; i < linecount; i++)
 504                         printk("%02X ",(unsigned char)data[i]);
 505                 for(;i<17;i++)
 506                         printk("   ");
 507                 for(i=0;i<linecount;i++) {
 508                         if (data[i]>=040 && data[i]<=0176)
 509                                 printk("%c",data[i]);
 510                         else
 511                                 printk(".");
 512                 }
 513                 printk("\n");
 514                 data  += linecount;
 515                 count -= linecount;
 516         }
 517 }
 518 #else
 519 #define DBGDATA(info, buf, size, label)
 520 #endif
 521
 522 #ifdef DBGTBUF
 523 static void dump_tbufs(struct slgt_info *info)
 524 {
 525         int i;
 526         printk("tbuf_current=%d\n", info->tbuf_current);
 527         for (i=0 ; i < info->tbuf_count ; i++) {
 528                 printk("%d: count=%04X status=%04X\n",
 529                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 530         }
 531 }
 532 #else
 533 #define DBGTBUF(info)
 534 #endif
 535
 536 #ifdef DBGRBUF
 537 static void dump_rbufs(struct slgt_info *info)
 538 {
 539         int i;
 540         printk("rbuf_current=%d\n", info->rbuf_current);
 541         for (i=0 ; i < info->rbuf_count ; i++) {
 542                 printk("%d: count=%04X status=%04X\n",
 543                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 544         }
 545 }
 546 #else
 547 #define DBGRBUF(info)
 548 #endif
 549
 550 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 551 {
 552 #ifdef SANITY_CHECK
 553         if (!info) {
 554                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 555                 return 1;
 556         }
 557         if (info->magic != MGSL_MAGIC) {
 558                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 559                 return 1;
 560         }
 561 #else
 562         if (!info)
 563                 return 1;
 564 #endif
 565         return 0;
 566 }
 567
 568 /**
 569  * line discipline callback wrappers
 570  *
 571  * The wrappers maintain line discipline references
 572  * while calling into the line discipline.
 573  *
 574  * ldisc_receive_buf  - pass receive data to line discipline
 575  */
 576 static void ldisc_receive_buf(struct tty_struct *tty,
 577                               const __u8 *data, char *flags, int count)
 578 {
 579         struct tty_ldisc *ld;
 580         if (!tty)
 581                 return;
 582         ld = tty_ldisc_ref(tty);
 583         if (ld) {
 584                 if (ld->ops->receive_buf)
 585                         ld->ops->receive_buf(tty, data, flags, count);
 586                 tty_ldisc_deref(ld);
 587         }
 588 }
 589
 590 /* tty callbacks */
 591
 592 static int open(struct tty_struct *tty, struct file *filp)
 593 {
 594         struct slgt_info *info;
 595         int retval, line;
 596         unsigned long flags;
 597
 598         line = tty->index;
 599         if (line >= slgt_device_count) {
 600                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 601                 return -ENODEV;
 602         }
 603
 604         info = slgt_device_list;
 605         while(info && info->line != line)
 606                 info = info->next_device;
 607         if (sanity_check(info, tty->name, "open"))
 608                 return -ENODEV;
 609         if (info->init_error) {
 610                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 611                 return -ENODEV;
 612         }
 613
 614         tty->driver_data = info;
 615         info->port.tty = tty;
 616
 617         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 618
 619         mutex_lock(&info->port.mutex);
 620         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 621
 622         spin_lock_irqsave(&info->netlock, flags);
 623         if (info->netcount) {
 624                 retval = -EBUSY;
 625                 spin_unlock_irqrestore(&info->netlock, flags);
 626                 mutex_unlock(&info->port.mutex);
 627                 goto cleanup;
 628         }
 629         info->port.count++;
 630         spin_unlock_irqrestore(&info->netlock, flags);
 631
 632         if (info->port.count == 1) {
 633                 /* 1st open on this device, init hardware */
 634                 retval = startup(info);
 635                 if (retval < 0) {
 636                         mutex_unlock(&info->port.mutex);
 637                         goto cleanup;
 638                 }
 639         }
 640         mutex_unlock(&info->port.mutex);
 641         retval = block_til_ready(tty, filp, info);
 642         if (retval) {
 643                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 644                 goto cleanup;
 645         }
 646
 647         retval = 0;
 648
 649 cleanup:
 650         if (retval) {
 651                 if (tty->count == 1)
 652                         info->port.tty = NULL; /* tty layer will release tty struct */
 653                 if(info->port.count)
 654                         info->port.count--;
 655         }
 656
 657         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 658         return retval;
 659 }
 660
 661 static void close(struct tty_struct *tty, struct file *filp)
 662 {
 663         struct slgt_info *info = tty->driver_data;
 664
 665         if (sanity_check(info, tty->name, "close"))
 666                 return;
 667         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 668
 669         if (tty_port_close_start(&info->port, tty, filp) == 0)
 670                 goto cleanup;
 671
 672         mutex_lock(&info->port.mutex);
 673         if (tty_port_initialized(&info->port))
 674                 wait_until_sent(tty, info->timeout);
 675         flush_buffer(tty);
 676         tty_ldisc_flush(tty);
 677
 678         shutdown(info);
 679         mutex_unlock(&info->port.mutex);
 680
 681         tty_port_close_end(&info->port, tty);
 682         info->port.tty = NULL;
 683 cleanup:
 684         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 685 }
 686
 687 static void hangup(struct tty_struct *tty)
 688 {
 689         struct slgt_info *info = tty->driver_data;
 690         unsigned long flags;
 691
 692         if (sanity_check(info, tty->name, "hangup"))
 693                 return;
 694         DBGINFO(("%s hangup\n", info->device_name));
 695
 696         flush_buffer(tty);
 697
 698         mutex_lock(&info->port.mutex);
 699         shutdown(info);
 700
 701         spin_lock_irqsave(&info->port.lock, flags);
 702         info->port.count = 0;
 703         info->port.tty = NULL;
 704         spin_unlock_irqrestore(&info->port.lock, flags);
 705         tty_port_set_active(&info->port, 0);
 706         mutex_unlock(&info->port.mutex);
 707
 708         wake_up_interruptible(&info->port.open_wait);
 709 }
 710
 711 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 712 {
 713         struct slgt_info *info = tty->driver_data;
 714         unsigned long flags;
 715
 716         DBGINFO(("%s set_termios\n", tty->driver->name));
 717
 718         change_params(info);
 719
 720         /* Handle transition to B0 status */
 721         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 722                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 723                 spin_lock_irqsave(&info->lock,flags);
 724                 set_gtsignals(info);
 725                 spin_unlock_irqrestore(&info->lock,flags);
 726         }
 727
 728         /* Handle transition away from B0 status */
 729         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 730                 info->signals |= SerialSignal_DTR;
 731                 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 732                         info->signals |= SerialSignal_RTS;
 733                 spin_lock_irqsave(&info->lock,flags);
 734                 set_gtsignals(info);
 735                 spin_unlock_irqrestore(&info->lock,flags);
 736         }
 737
 738         /* Handle turning off CRTSCTS */
 739         if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
 740                 tty->hw_stopped = 0;
 741                 tx_release(tty);
 742         }
 743 }
 744
 745 static void update_tx_timer(struct slgt_info *info)
 746 {
 747         /*
 748          * use worst case speed of 1200bps to calculate transmit timeout
 749          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 750          */
 751         if (info->params.mode == MGSL_MODE_HDLC) {
 752                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 753                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 754         }
 755 }
 756
 757 static int write(struct tty_struct *tty,
 758                  const unsigned char *buf, int count)
 759 {
 760         int ret = 0;
 761         struct slgt_info *info = tty->driver_data;
 762         unsigned long flags;
 763
 764         if (sanity_check(info, tty->name, "write"))
 765                 return -EIO;
 766
 767         DBGINFO(("%s write count=%d\n", info->device_name, count));
 768
 769         if (!info->tx_buf || (count > info->max_frame_size))
 770                 return -EIO;
 771
 772         if (!count || tty->stopped || tty->hw_stopped)
 773                 return 0;
 774
 775         spin_lock_irqsave(&info->lock, flags);
 776
 777         if (info->tx_count) {
 778                 /* send accumulated data from send_char() */
 779                 if (!tx_load(info, info->tx_buf, info->tx_count))
 780                         goto cleanup;
 781                 info->tx_count = 0;
 782         }
 783
 784         if (tx_load(info, buf, count))
 785                 ret = count;
 786
 787 cleanup:
 788         spin_unlock_irqrestore(&info->lock, flags);
 789         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 790         return ret;
 791 }
 792
 793 static int put_char(struct tty_struct *tty, unsigned char ch)
 794 {
 795         struct slgt_info *info = tty->driver_data;
 796         unsigned long flags;
 797         int ret = 0;
 798
 799         if (sanity_check(info, tty->name, "put_char"))
 800                 return 0;
 801         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 802         if (!info->tx_buf)
 803                 return 0;
 804         spin_lock_irqsave(&info->lock,flags);
 805         if (info->tx_count < info->max_frame_size) {
 806                 info->tx_buf[info->tx_count++] = ch;
 807                 ret = 1;
 808         }
 809         spin_unlock_irqrestore(&info->lock,flags);
 810         return ret;
 811 }
 812
 813 static void send_xchar(struct tty_struct *tty, char ch)
 814 {
 815         struct slgt_info *info = tty->driver_data;
 816         unsigned long flags;
 817
 818         if (sanity_check(info, tty->name, "send_xchar"))
 819                 return;
 820         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 821         info->x_char = ch;
 822         if (ch) {
 823                 spin_lock_irqsave(&info->lock,flags);
 824                 if (!info->tx_enabled)
 825                         tx_start(info);
 826                 spin_unlock_irqrestore(&info->lock,flags);
 827         }
 828 }
 829
 830 static void wait_until_sent(struct tty_struct *tty, int timeout)
 831 {
 832         struct slgt_info *info = tty->driver_data;
 833         unsigned long orig_jiffies, char_time;
 834
 835         if (!info )
 836                 return;
 837         if (sanity_check(info, tty->name, "wait_until_sent"))
 838                 return;
 839         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 840         if (!tty_port_initialized(&info->port))
 841                 goto exit;
 842
 843         orig_jiffies = jiffies;
 844
 845         /* Set check interval to 1/5 of estimated time to
 846          * send a character, and make it at least 1. The check
 847          * interval should also be less than the timeout.
 848          * Note: use tight timings here to satisfy the NIST-PCTS.
 849          */
 850
 851         if (info->params.data_rate) {
 852                 char_time = info->timeout/(32 * 5);
 853                 if (!char_time)
 854                         char_time++;
 855         } else
 856                 char_time = 1;
 857
 858         if (timeout)
 859                 char_time = min_t(unsigned long, char_time, timeout);
 860
 861         while (info->tx_active) {
 862                 msleep_interruptible(jiffies_to_msecs(char_time));
 863                 if (signal_pending(current))
 864                         break;
 865                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 866                         break;
 867         }
 868 exit:
 869         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 870 }
 871
 872 static int write_room(struct tty_struct *tty)
 873 {
 874         struct slgt_info *info = tty->driver_data;
 875         int ret;
 876
 877         if (sanity_check(info, tty->name, "write_room"))
 878                 return 0;
 879         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 880         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 881         return ret;
 882 }
 883
 884 static void flush_chars(struct tty_struct *tty)
 885 {
 886         struct slgt_info *info = tty->driver_data;
 887         unsigned long flags;
 888
 889         if (sanity_check(info, tty->name, "flush_chars"))
 890                 return;
 891         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 892
 893         if (info->tx_count <= 0 || tty->stopped ||
 894             tty->hw_stopped || !info->tx_buf)
 895                 return;
 896
 897         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 898
 899         spin_lock_irqsave(&info->lock,flags);
 900         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 901                 info->tx_count = 0;
 902         spin_unlock_irqrestore(&info->lock,flags);
 903 }
 904
 905 static void flush_buffer(struct tty_struct *tty)
 906 {
 907         struct slgt_info *info = tty->driver_data;
 908         unsigned long flags;
 909
 910         if (sanity_check(info, tty->name, "flush_buffer"))
 911                 return;
 912         DBGINFO(("%s flush_buffer\n", info->device_name));
 913
 914         spin_lock_irqsave(&info->lock, flags);
 915         info->tx_count = 0;
 916         spin_unlock_irqrestore(&info->lock, flags);
 917
 918         tty_wakeup(tty);
 919 }
 920
 921 /*
 922  * throttle (stop) transmitter
 923  */
 924 static void tx_hold(struct tty_struct *tty)
 925 {
 926         struct slgt_info *info = tty->driver_data;
 927         unsigned long flags;
 928
 929         if (sanity_check(info, tty->name, "tx_hold"))
 930                 return;
 931         DBGINFO(("%s tx_hold\n", info->device_name));
 932         spin_lock_irqsave(&info->lock,flags);
 933         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 934                 tx_stop(info);
 935         spin_unlock_irqrestore(&info->lock,flags);
 936 }
 937
 938 /*
 939  * release (start) transmitter
 940  */
 941 static void tx_release(struct tty_struct *tty)
 942 {
 943         struct slgt_info *info = tty->driver_data;
 944         unsigned long flags;
 945
 946         if (sanity_check(info, tty->name, "tx_release"))
 947                 return;
 948         DBGINFO(("%s tx_release\n", info->device_name));
 949         spin_lock_irqsave(&info->lock, flags);
 950         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 951                 info->tx_count = 0;
 952         spin_unlock_irqrestore(&info->lock, flags);
 953 }
 954
 955 /*
 956  * Service an IOCTL request
 957  *
 958  * Arguments
 959  *
 960  *      tty     pointer to tty instance data
 961  *      cmd     IOCTL command code
 962  *      arg     command argument/context
 963  *
 964  * Return 0 if success, otherwise error code
 965  */
 966 static int ioctl(struct tty_struct *tty,
 967                  unsigned int cmd, unsigned long arg)
 968 {
 969         struct slgt_info *info = tty->driver_data;
 970         void __user *argp = (void __user *)arg;
 971         int ret;
 972
 973         if (sanity_check(info, tty->name, "ioctl"))
 974                 return -ENODEV;
 975         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
 976
 977         if (cmd != TIOCMIWAIT) {
 978                 if (tty_io_error(tty))
 979                     return -EIO;
 980         }
 981
 982         switch (cmd) {
 983         case MGSL_IOCWAITEVENT:
 984                 return wait_mgsl_event(info, argp);
 985         case TIOCMIWAIT:
 986                 return modem_input_wait(info,(int)arg);
 987         case MGSL_IOCSGPIO:
 988                 return set_gpio(info, argp);
 989         case MGSL_IOCGGPIO:
 990                 return get_gpio(info, argp);
 991         case MGSL_IOCWAITGPIO:
 992                 return wait_gpio(info, argp);
 993         case MGSL_IOCGXSYNC:
 994                 return get_xsync(info, argp);
 995         case MGSL_IOCSXSYNC:
 996                 return set_xsync(info, (int)arg);
 997         case MGSL_IOCGXCTRL:
 998                 return get_xctrl(info, argp);
 999         case MGSL_IOCSXCTRL:
1000                 return set_xctrl(info, (int)arg);
1001         }
1002         mutex_lock(&info->port.mutex);
1003         switch (cmd) {
1004         case MGSL_IOCGPARAMS:
1005                 ret = get_params(info, argp);
1006                 break;
1007         case MGSL_IOCSPARAMS:
1008                 ret = set_params(info, argp);
1009                 break;
1010         case MGSL_IOCGTXIDLE:
1011                 ret = get_txidle(info, argp);
1012                 break;
1013         case MGSL_IOCSTXIDLE:
1014                 ret = set_txidle(info, (int)arg);
1015                 break;
1016         case MGSL_IOCTXENABLE:
1017                 ret = tx_enable(info, (int)arg);
1018                 break;
1019         case MGSL_IOCRXENABLE:
1020                 ret = rx_enable(info, (int)arg);
1021                 break;
1022         case MGSL_IOCTXABORT:
1023                 ret = tx_abort(info);
1024                 break;
1025         case MGSL_IOCGSTATS:
1026                 ret = get_stats(info, argp);
1027                 break;
1028         case MGSL_IOCGIF:
1029                 ret = get_interface(info, argp);
1030                 break;
1031         case MGSL_IOCSIF:
1032                 ret = set_interface(info,(int)arg);
1033                 break;
1034         default:
1035                 ret = -ENOIOCTLCMD;
1036         }
1037         mutex_unlock(&info->port.mutex);
1038         return ret;
1039 }
1040
1041 static int get_icount(struct tty_struct *tty,
1042                                 struct serial_icounter_struct *icount)
1043
1044 {
1045         struct slgt_info *info = tty->driver_data;
1046         struct mgsl_icount cnow;        /* kernel counter temps */
1047         unsigned long flags;
1048
1049         spin_lock_irqsave(&info->lock,flags);
1050         cnow = info->icount;
1051         spin_unlock_irqrestore(&info->lock,flags);
1052
1053         icount->cts = cnow.cts;
1054         icount->dsr = cnow.dsr;
1055         icount->rng = cnow.rng;
1056         icount->dcd = cnow.dcd;
1057         icount->rx = cnow.rx;
1058         icount->tx = cnow.tx;
1059         icount->frame = cnow.frame;
1060         icount->overrun = cnow.overrun;
1061         icount->parity = cnow.parity;
1062         icount->brk = cnow.brk;
1063         icount->buf_overrun = cnow.buf_overrun;
1064
1065         return 0;
1066 }
1067
1068 /*
1069  * support for 32 bit ioctl calls on 64 bit systems
1070  */
1071 #ifdef CONFIG_COMPAT
1072 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1073 {
1074         struct MGSL_PARAMS32 tmp_params;
1075
1076         DBGINFO(("%s get_params32\n", info->device_name));
1077         memset(&tmp_params, 0, sizeof(tmp_params));
1078         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1079         tmp_params.loopback        = info->params.loopback;
1080         tmp_params.flags           = info->params.flags;
1081         tmp_params.encoding        = info->params.encoding;
1082         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1083         tmp_params.addr_filter     = info->params.addr_filter;
1084         tmp_params.crc_type        = info->params.crc_type;
1085         tmp_params.preamble_length = info->params.preamble_length;
1086         tmp_params.preamble        = info->params.preamble;
1087         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1088         tmp_params.data_bits       = info->params.data_bits;
1089         tmp_params.stop_bits       = info->params.stop_bits;
1090         tmp_params.parity          = info->params.parity;
1091         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1092                 return -EFAULT;
1093         return 0;
1094 }
1095
1096 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1097 {
1098         struct MGSL_PARAMS32 tmp_params;
1099
1100         DBGINFO(("%s set_params32\n", info->device_name));
1101         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1102                 return -EFAULT;
1103
1104         spin_lock(&info->lock);
1105         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1106                 info->base_clock = tmp_params.clock_speed;
1107         } else {
1108                 info->params.mode            = tmp_params.mode;
1109                 info->params.loopback        = tmp_params.loopback;
1110                 info->params.flags           = tmp_params.flags;
1111                 info->params.encoding        = tmp_params.encoding;
1112                 info->params.clock_speed     = tmp_params.clock_speed;
1113                 info->params.addr_filter     = tmp_params.addr_filter;
1114                 info->params.crc_type        = tmp_params.crc_type;
1115                 info->params.preamble_length = tmp_params.preamble_length;
1116                 info->params.preamble        = tmp_params.preamble;
1117                 info->params.data_rate       = tmp_params.data_rate;
1118                 info->params.data_bits       = tmp_params.data_bits;
1119                 info->params.stop_bits       = tmp_params.stop_bits;
1120                 info->params.parity          = tmp_params.parity;
1121         }
1122         spin_unlock(&info->lock);
1123
1124         program_hw(info);
1125
1126         return 0;
1127 }
1128
1129 static long slgt_compat_ioctl(struct tty_struct *tty,
1130                          unsigned int cmd, unsigned long arg)
1131 {
1132         struct slgt_info *info = tty->driver_data;
1133         int rc;
1134
1135         if (sanity_check(info, tty->name, "compat_ioctl"))
1136                 return -ENODEV;
1137         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1138
1139         switch (cmd) {
1140         case MGSL_IOCSPARAMS32:
1141                 rc = set_params32(info, compat_ptr(arg));
1142                 break;
1143
1144         case MGSL_IOCGPARAMS32:
1145                 rc = get_params32(info, compat_ptr(arg));
1146                 break;
1147
1148         case MGSL_IOCGPARAMS:
1149         case MGSL_IOCSPARAMS:
1150         case MGSL_IOCGTXIDLE:
1151         case MGSL_IOCGSTATS:
1152         case MGSL_IOCWAITEVENT:
1153         case MGSL_IOCGIF:
1154         case MGSL_IOCSGPIO:
1155         case MGSL_IOCGGPIO:
1156         case MGSL_IOCWAITGPIO:
1157         case MGSL_IOCGXSYNC:
1158         case MGSL_IOCGXCTRL:
1159                 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1160                 break;
1161         default:
1162                 rc = ioctl(tty, cmd, arg);
1163         }
1164         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1165         return rc;
1166 }
1167 #else
1168 #define slgt_compat_ioctl NULL
1169 #endif /* ifdef CONFIG_COMPAT */
1170
1171 /*
1172  * proc fs support
1173  */
1174 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1175 {
1176         char stat_buf[30];
1177         unsigned long flags;
1178
1179         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1180                       info->device_name, info->phys_reg_addr,
1181                       info->irq_level, info->max_frame_size);
1182
1183         /* output current serial signal states */
1184         spin_lock_irqsave(&info->lock,flags);
1185         get_gtsignals(info);
1186         spin_unlock_irqrestore(&info->lock,flags);
1187
1188         stat_buf[0] = 0;
1189         stat_buf[1] = 0;
1190         if (info->signals & SerialSignal_RTS)
1191                 strcat(stat_buf, "|RTS");
1192         if (info->signals & SerialSignal_CTS)
1193                 strcat(stat_buf, "|CTS");
1194         if (info->signals & SerialSignal_DTR)
1195                 strcat(stat_buf, "|DTR");
1196         if (info->signals & SerialSignal_DSR)
1197                 strcat(stat_buf, "|DSR");
1198         if (info->signals & SerialSignal_DCD)
1199                 strcat(stat_buf, "|CD");
1200         if (info->signals & SerialSignal_RI)
1201                 strcat(stat_buf, "|RI");
1202
1203         if (info->params.mode != MGSL_MODE_ASYNC) {
1204                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1205                                info->icount.txok, info->icount.rxok);
1206                 if (info->icount.txunder)
1207                         seq_printf(m, " txunder:%d", info->icount.txunder);
1208                 if (info->icount.txabort)
1209                         seq_printf(m, " txabort:%d", info->icount.txabort);
1210                 if (info->icount.rxshort)
1211                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1212                 if (info->icount.rxlong)
1213                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1214                 if (info->icount.rxover)
1215                         seq_printf(m, " rxover:%d", info->icount.rxover);
1216                 if (info->icount.rxcrc)
1217                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1218         } else {
1219                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1220                                info->icount.tx, info->icount.rx);
1221                 if (info->icount.frame)
1222                         seq_printf(m, " fe:%d", info->icount.frame);
1223                 if (info->icount.parity)
1224                         seq_printf(m, " pe:%d", info->icount.parity);
1225                 if (info->icount.brk)
1226                         seq_printf(m, " brk:%d", info->icount.brk);
1227                 if (info->icount.overrun)
1228                         seq_printf(m, " oe:%d", info->icount.overrun);
1229         }
1230
1231         /* Append serial signal status to end */
1232         seq_printf(m, " %s\n", stat_buf+1);
1233
1234         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1235                        info->tx_active,info->bh_requested,info->bh_running,
1236                        info->pending_bh);
1237 }
1238
1239 /* Called to print information about devices
1240  */
1241 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1242 {
1243         struct slgt_info *info;
1244
1245         seq_puts(m, "synclink_gt driver\n");
1246
1247         info = slgt_device_list;
1248         while( info ) {
1249                 line_info(m, info);
1250                 info = info->next_device;
1251         }
1252         return 0;
1253 }
1254
1255 /*
1256  * return count of bytes in transmit buffer
1257  */
1258 static int chars_in_buffer(struct tty_struct *tty)
1259 {
1260         struct slgt_info *info = tty->driver_data;
1261         int count;
1262         if (sanity_check(info, tty->name, "chars_in_buffer"))
1263                 return 0;
1264         count = tbuf_bytes(info);
1265         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1266         return count;
1267 }
1268
1269 /*
1270  * signal remote device to throttle send data (our receive data)
1271  */
1272 static void throttle(struct tty_struct * tty)
1273 {
1274         struct slgt_info *info = tty->driver_data;
1275         unsigned long flags;
1276
1277         if (sanity_check(info, tty->name, "throttle"))
1278                 return;
1279         DBGINFO(("%s throttle\n", info->device_name));
1280         if (I_IXOFF(tty))
1281                 send_xchar(tty, STOP_CHAR(tty));
1282         if (C_CRTSCTS(tty)) {
1283                 spin_lock_irqsave(&info->lock,flags);
1284                 info->signals &= ~SerialSignal_RTS;
1285                 set_gtsignals(info);
1286                 spin_unlock_irqrestore(&info->lock,flags);
1287         }
1288 }
1289
1290 /*
1291  * signal remote device to stop throttling send data (our receive data)
1292  */
1293 static void unthrottle(struct tty_struct * tty)
1294 {
1295         struct slgt_info *info = tty->driver_data;
1296         unsigned long flags;
1297
1298         if (sanity_check(info, tty->name, "unthrottle"))
1299                 return;
1300         DBGINFO(("%s unthrottle\n", info->device_name));
1301         if (I_IXOFF(tty)) {
1302                 if (info->x_char)
1303                         info->x_char = 0;
1304                 else
1305                         send_xchar(tty, START_CHAR(tty));
1306         }
1307         if (C_CRTSCTS(tty)) {
1308                 spin_lock_irqsave(&info->lock,flags);
1309                 info->signals |= SerialSignal_RTS;
1310                 set_gtsignals(info);
1311                 spin_unlock_irqrestore(&info->lock,flags);
1312         }
1313 }
1314
1315 /*
1316  * set or clear transmit break condition
1317  * break_state  -1=set break condition, 0=clear
1318  */
1319 static int set_break(struct tty_struct *tty, int break_state)
1320 {
1321         struct slgt_info *info = tty->driver_data;
1322         unsigned short value;
1323         unsigned long flags;
1324
1325         if (sanity_check(info, tty->name, "set_break"))
1326                 return -EINVAL;
1327         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1328
1329         spin_lock_irqsave(&info->lock,flags);
1330         value = rd_reg16(info, TCR);
1331         if (break_state == -1)
1332                 value |= BIT6;
1333         else
1334                 value &= ~BIT6;
1335         wr_reg16(info, TCR, value);
1336         spin_unlock_irqrestore(&info->lock,flags);
1337         return 0;
1338 }
1339
1340 #if SYNCLINK_GENERIC_HDLC
1341
1342 /**
1343  * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1344  * @dev:      pointer to network device structure
1345  * @encoding: serial encoding setting
1346  * @parity:   FCS setting
1347  *
1348  * Set encoding and frame check sequence (FCS) options.
1349  *
1350  * Return: 0 if success, otherwise error code
1351  */
1352 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1353                           unsigned short parity)
1354 {
1355         struct slgt_info *info = dev_to_port(dev);
1356         unsigned char  new_encoding;
1357         unsigned short new_crctype;
1358
1359         /* return error if TTY interface open */
1360         if (info->port.count)
1361                 return -EBUSY;
1362
1363         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1364
1365         switch (encoding)
1366         {
1367         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1368         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1369         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1370         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1371         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1372         default: return -EINVAL;
1373         }
1374
1375         switch (parity)
1376         {
1377         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1378         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1379         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1380         default: return -EINVAL;
1381         }
1382
1383         info->params.encoding = new_encoding;
1384         info->params.crc_type = new_crctype;
1385
1386         /* if network interface up, reprogram hardware */
1387         if (info->netcount)
1388                 program_hw(info);
1389
1390         return 0;
1391 }
1392
1393 /**
1394  * hdlcdev_xmit - called by generic HDLC layer to send a frame
1395  * @skb: socket buffer containing HDLC frame
1396  * @dev: pointer to network device structure
1397  */
1398 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1399                                       struct net_device *dev)
1400 {
1401         struct slgt_info *info = dev_to_port(dev);
1402         unsigned long flags;
1403
1404         DBGINFO(("%s hdlc_xmit\n", dev->name));
1405
1406         if (!skb->len)
1407                 return NETDEV_TX_OK;
1408
1409         /* stop sending until this frame completes */
1410         netif_stop_queue(dev);
1411
1412         /* update network statistics */
1413         dev->stats.tx_packets++;
1414         dev->stats.tx_bytes += skb->len;
1415
1416         /* save start time for transmit timeout detection */
1417         netif_trans_update(dev);
1418
1419         spin_lock_irqsave(&info->lock, flags);
1420         tx_load(info, skb->data, skb->len);
1421         spin_unlock_irqrestore(&info->lock, flags);
1422
1423         /* done with socket buffer, so free it */
1424         dev_kfree_skb(skb);
1425
1426         return NETDEV_TX_OK;
1427 }
1428
1429 /**
1430  * hdlcdev_open - called by network layer when interface enabled
1431  * @dev: pointer to network device structure
1432  *
1433  * Claim resources and initialize hardware.
1434  *
1435  * Return: 0 if success, otherwise error code
1436  */
1437 static int hdlcdev_open(struct net_device *dev)
1438 {
1439         struct slgt_info *info = dev_to_port(dev);
1440         int rc;
1441         unsigned long flags;
1442
1443         if (!try_module_get(THIS_MODULE))
1444                 return -EBUSY;
1445
1446         DBGINFO(("%s hdlcdev_open\n", dev->name));
1447
1448         /* generic HDLC layer open processing */
1449         rc = hdlc_open(dev);
1450         if (rc)
1451                 return rc;
1452
1453         /* arbitrate between network and tty opens */
1454         spin_lock_irqsave(&info->netlock, flags);
1455         if (info->port.count != 0 || info->netcount != 0) {
1456                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1457                 spin_unlock_irqrestore(&info->netlock, flags);
1458                 return -EBUSY;
1459         }
1460         info->netcount=1;
1461         spin_unlock_irqrestore(&info->netlock, flags);
1462
1463         /* claim resources and init adapter */
1464         if ((rc = startup(info)) != 0) {
1465                 spin_lock_irqsave(&info->netlock, flags);
1466                 info->netcount=0;
1467                 spin_unlock_irqrestore(&info->netlock, flags);
1468                 return rc;
1469         }
1470
1471         /* assert RTS and DTR, apply hardware settings */
1472         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1473         program_hw(info);
1474
1475         /* enable network layer transmit */
1476         netif_trans_update(dev);
1477         netif_start_queue(dev);
1478
1479         /* inform generic HDLC layer of current DCD status */
1480         spin_lock_irqsave(&info->lock, flags);
1481         get_gtsignals(info);
1482         spin_unlock_irqrestore(&info->lock, flags);
1483         if (info->signals & SerialSignal_DCD)
1484                 netif_carrier_on(dev);
1485         else
1486                 netif_carrier_off(dev);
1487         return 0;
1488 }
1489
1490 /**
1491  * hdlcdev_close - called by network layer when interface is disabled
1492  * @dev:  pointer to network device structure
1493  *
1494  * Shutdown hardware and release resources.
1495  *
1496  * Return: 0 if success, otherwise error code
1497  */
1498 static int hdlcdev_close(struct net_device *dev)
1499 {
1500         struct slgt_info *info = dev_to_port(dev);
1501         unsigned long flags;
1502
1503         DBGINFO(("%s hdlcdev_close\n", dev->name));
1504
1505         netif_stop_queue(dev);
1506
1507         /* shutdown adapter and release resources */
1508         shutdown(info);
1509
1510         hdlc_close(dev);
1511
1512         spin_lock_irqsave(&info->netlock, flags);
1513         info->netcount=0;
1514         spin_unlock_irqrestore(&info->netlock, flags);
1515
1516         module_put(THIS_MODULE);
1517         return 0;
1518 }
1519
1520 /**
1521  * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1522  * @dev: pointer to network device structure
1523  * @ifr: pointer to network interface request structure
1524  * @cmd: IOCTL command code
1525  *
1526  * Return: 0 if success, otherwise error code
1527  */
1528 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1529 {
1530         const size_t size = sizeof(sync_serial_settings);
1531         sync_serial_settings new_line;
1532         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1533         struct slgt_info *info = dev_to_port(dev);
1534         unsigned int flags;
1535
1536         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1537
1538         /* return error if TTY interface open */
1539         if (info->port.count)
1540                 return -EBUSY;
1541
1542         if (cmd != SIOCWANDEV)
1543                 return hdlc_ioctl(dev, ifr, cmd);
1544
1545         memset(&new_line, 0, sizeof(new_line));
1546
1547         switch(ifr->ifr_settings.type) {
1548         case IF_GET_IFACE: /* return current sync_serial_settings */
1549
1550                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1551                 if (ifr->ifr_settings.size < size) {
1552                         ifr->ifr_settings.size = size; /* data size wanted */
1553                         return -ENOBUFS;
1554                 }
1555
1556                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1557                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1558                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1559                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1560
1561                 switch (flags){
1562                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1563                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1564                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1565                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1566                 default: new_line.clock_type = CLOCK_DEFAULT;
1567                 }
1568
1569                 new_line.clock_rate = info->params.clock_speed;
1570                 new_line.loopback   = info->params.loopback ? 1:0;
1571
1572                 if (copy_to_user(line, &new_line, size))
1573                         return -EFAULT;
1574                 return 0;
1575
1576         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1577
1578                 if(!capable(CAP_NET_ADMIN))
1579                         return -EPERM;
1580                 if (copy_from_user(&new_line, line, size))
1581                         return -EFAULT;
1582
1583                 switch (new_line.clock_type)
1584                 {
1585                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1586                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1587                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1588                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1589                 case CLOCK_DEFAULT:  flags = info->params.flags &
1590                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1591                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1592                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1593                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1594                 default: return -EINVAL;
1595                 }
1596
1597                 if (new_line.loopback != 0 && new_line.loopback != 1)
1598                         return -EINVAL;
1599
1600                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1601                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1602                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1603                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1604                 info->params.flags |= flags;
1605
1606                 info->params.loopback = new_line.loopback;
1607
1608                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1609                         info->params.clock_speed = new_line.clock_rate;
1610                 else
1611                         info->params.clock_speed = 0;
1612
1613                 /* if network interface up, reprogram hardware */
1614                 if (info->netcount)
1615                         program_hw(info);
1616                 return 0;
1617
1618         default:
1619                 return hdlc_ioctl(dev, ifr, cmd);
1620         }
1621 }
1622
1623 /**
1624  * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1625  * @dev: pointer to network device structure
1626  */
1627 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1628 {
1629         struct slgt_info *info = dev_to_port(dev);
1630         unsigned long flags;
1631
1632         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1633
1634         dev->stats.tx_errors++;
1635         dev->stats.tx_aborted_errors++;
1636
1637         spin_lock_irqsave(&info->lock,flags);
1638         tx_stop(info);
1639         spin_unlock_irqrestore(&info->lock,flags);
1640
1641         netif_wake_queue(dev);
1642 }
1643
1644 /**
1645  * hdlcdev_tx_done - called by device driver when transmit completes
1646  * @info: pointer to device instance information
1647  *
1648  * Reenable network layer transmit if stopped.
1649  */
1650 static void hdlcdev_tx_done(struct slgt_info *info)
1651 {
1652         if (netif_queue_stopped(info->netdev))
1653                 netif_wake_queue(info->netdev);
1654 }
1655
1656 /**
1657  * hdlcdev_rx - called by device driver when frame received
1658  * @info: pointer to device instance information
1659  * @buf:  pointer to buffer contianing frame data
1660  * @size: count of data bytes in buf
1661  *
1662  * Pass frame to network layer.
1663  */
1664 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1665 {
1666         struct sk_buff *skb = dev_alloc_skb(size);
1667         struct net_device *dev = info->netdev;
1668
1669         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1670
1671         if (skb == NULL) {
1672                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1673                 dev->stats.rx_dropped++;
1674                 return;
1675         }
1676
1677         skb_put_data(skb, buf, size);
1678
1679         skb->protocol = hdlc_type_trans(skb, dev);
1680
1681         dev->stats.rx_packets++;
1682         dev->stats.rx_bytes += size;
1683
1684         netif_rx(skb);
1685 }
1686
1687 static const struct net_device_ops hdlcdev_ops = {
1688         .ndo_open       = hdlcdev_open,
1689         .ndo_stop       = hdlcdev_close,
1690         .ndo_start_xmit = hdlc_start_xmit,
1691         .ndo_do_ioctl   = hdlcdev_ioctl,
1692         .ndo_tx_timeout = hdlcdev_tx_timeout,
1693 };
1694
1695 /**
1696  * hdlcdev_init - called by device driver when adding device instance
1697  * @info: pointer to device instance information
1698  *
1699  * Do generic HDLC initialization.
1700  *
1701  * Return: 0 if success, otherwise error code
1702  */
1703 static int hdlcdev_init(struct slgt_info *info)
1704 {
1705         int rc;
1706         struct net_device *dev;
1707         hdlc_device *hdlc;
1708
1709         /* allocate and initialize network and HDLC layer objects */
1710
1711         dev = alloc_hdlcdev(info);
1712         if (!dev) {
1713                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1714                 return -ENOMEM;
1715         }
1716
1717         /* for network layer reporting purposes only */
1718         dev->mem_start = info->phys_reg_addr;
1719         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1720         dev->irq       = info->irq_level;
1721
1722         /* network layer callbacks and settings */
1723         dev->netdev_ops     = &hdlcdev_ops;
1724         dev->watchdog_timeo = 10 * HZ;
1725         dev->tx_queue_len   = 50;
1726
1727         /* generic HDLC layer callbacks and settings */
1728         hdlc         = dev_to_hdlc(dev);
1729         hdlc->attach = hdlcdev_attach;
1730         hdlc->xmit   = hdlcdev_xmit;
1731
1732         /* register objects with HDLC layer */
1733         rc = register_hdlc_device(dev);
1734         if (rc) {
1735                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1736                 free_netdev(dev);
1737                 return rc;
1738         }
1739
1740         info->netdev = dev;
1741         return 0;
1742 }
1743
1744 /**
1745  * hdlcdev_exit - called by device driver when removing device instance
1746  * @info: pointer to device instance information
1747  *
1748  * Do generic HDLC cleanup.
1749  */
1750 static void hdlcdev_exit(struct slgt_info *info)
1751 {
1752         if (!info->netdev)
1753                 return;
1754         unregister_hdlc_device(info->netdev);
1755         free_netdev(info->netdev);
1756         info->netdev = NULL;
1757 }
1758
1759 #endif /* ifdef CONFIG_HDLC */
1760
1761 /*
1762  * get async data from rx DMA buffers
1763  */
1764 static void rx_async(struct slgt_info *info)
1765 {
1766         struct mgsl_icount *icount = &info->icount;
1767         unsigned int start, end;
1768         unsigned char *p;
1769         unsigned char status;
1770         struct slgt_desc *bufs = info->rbufs;
1771         int i, count;
1772         int chars = 0;
1773         int stat;
1774         unsigned char ch;
1775
1776         start = end = info->rbuf_current;
1777
1778         while(desc_complete(bufs[end])) {
1779                 count = desc_count(bufs[end]) - info->rbuf_index;
1780                 p     = bufs[end].buf + info->rbuf_index;
1781
1782                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1783                 DBGDATA(info, p, count, "rx");
1784
1785                 for(i=0 ; i < count; i+=2, p+=2) {
1786                         ch = *p;
1787                         icount->rx++;
1788
1789                         stat = 0;
1790
1791                         status = *(p + 1) & (BIT1 + BIT0);
1792                         if (status) {
1793                                 if (status & BIT1)
1794                                         icount->parity++;
1795                                 else if (status & BIT0)
1796                                         icount->frame++;
1797                                 /* discard char if tty control flags say so */
1798                                 if (status & info->ignore_status_mask)
1799                                         continue;
1800                                 if (status & BIT1)
1801                                         stat = TTY_PARITY;
1802                                 else if (status & BIT0)
1803                                         stat = TTY_FRAME;
1804                         }
1805                         tty_insert_flip_char(&info->port, ch, stat);
1806                         chars++;
1807                 }
1808
1809                 if (i < count) {
1810                         /* receive buffer not completed */
1811                         info->rbuf_index += i;
1812                         mod_timer(&info->rx_timer, jiffies + 1);
1813                         break;
1814                 }
1815
1816                 info->rbuf_index = 0;
1817                 free_rbufs(info, end, end);
1818
1819                 if (++end == info->rbuf_count)
1820                         end = 0;
1821
1822                 /* if entire list searched then no frame available */
1823                 if (end == start)
1824                         break;
1825         }
1826
1827         if (chars)
1828                 tty_flip_buffer_push(&info->port);
1829 }
1830
1831 /*
1832  * return next bottom half action to perform
1833  */
1834 static int bh_action(struct slgt_info *info)
1835 {
1836         unsigned long flags;
1837         int rc;
1838
1839         spin_lock_irqsave(&info->lock,flags);
1840
1841         if (info->pending_bh & BH_RECEIVE) {
1842                 info->pending_bh &= ~BH_RECEIVE;
1843                 rc = BH_RECEIVE;
1844         } else if (info->pending_bh & BH_TRANSMIT) {
1845                 info->pending_bh &= ~BH_TRANSMIT;
1846                 rc = BH_TRANSMIT;
1847         } else if (info->pending_bh & BH_STATUS) {
1848                 info->pending_bh &= ~BH_STATUS;
1849                 rc = BH_STATUS;
1850         } else {
1851                 /* Mark BH routine as complete */
1852                 info->bh_running = false;
1853                 info->bh_requested = false;
1854                 rc = 0;
1855         }
1856
1857         spin_unlock_irqrestore(&info->lock,flags);
1858
1859         return rc;
1860 }
1861
1862 /*
1863  * perform bottom half processing
1864  */
1865 static void bh_handler(struct work_struct *work)
1866 {
1867         struct slgt_info *info = container_of(work, struct slgt_info, task);
1868         int action;
1869
1870         info->bh_running = true;
1871
1872         while((action = bh_action(info))) {
1873                 switch (action) {
1874                 case BH_RECEIVE:
1875                         DBGBH(("%s bh receive\n", info->device_name));
1876                         switch(info->params.mode) {
1877                         case MGSL_MODE_ASYNC:
1878                                 rx_async(info);
1879                                 break;
1880                         case MGSL_MODE_HDLC:
1881                                 while(rx_get_frame(info));
1882                                 break;
1883                         case MGSL_MODE_RAW:
1884                         case MGSL_MODE_MONOSYNC:
1885                         case MGSL_MODE_BISYNC:
1886                         case MGSL_MODE_XSYNC:
1887                                 while(rx_get_buf(info));
1888                                 break;
1889                         }
1890                         /* restart receiver if rx DMA buffers exhausted */
1891                         if (info->rx_restart)
1892                                 rx_start(info);
1893                         break;
1894                 case BH_TRANSMIT:
1895                         bh_transmit(info);
1896                         break;
1897                 case BH_STATUS:
1898                         DBGBH(("%s bh status\n", info->device_name));
1899                         info->ri_chkcount = 0;
1900                         info->dsr_chkcount = 0;
1901                         info->dcd_chkcount = 0;
1902                         info->cts_chkcount = 0;
1903                         break;
1904                 default:
1905                         DBGBH(("%s unknown action\n", info->device_name));
1906                         break;
1907                 }
1908         }
1909         DBGBH(("%s bh_handler exit\n", info->device_name));
1910 }
1911
1912 static void bh_transmit(struct slgt_info *info)
1913 {
1914         struct tty_struct *tty = info->port.tty;
1915
1916         DBGBH(("%s bh_transmit\n", info->device_name));
1917         if (tty)
1918                 tty_wakeup(tty);
1919 }
1920
1921 static void dsr_change(struct slgt_info *info, unsigned short status)
1922 {
1923         if (status & BIT3) {
1924                 info->signals |= SerialSignal_DSR;
1925                 info->input_signal_events.dsr_up++;
1926         } else {
1927                 info->signals &= ~SerialSignal_DSR;
1928                 info->input_signal_events.dsr_down++;
1929         }
1930         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1931         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1932                 slgt_irq_off(info, IRQ_DSR);
1933                 return;
1934         }
1935         info->icount.dsr++;
1936         wake_up_interruptible(&info->status_event_wait_q);
1937         wake_up_interruptible(&info->event_wait_q);
1938         info->pending_bh |= BH_STATUS;
1939 }
1940
1941 static void cts_change(struct slgt_info *info, unsigned short status)
1942 {
1943         if (status & BIT2) {
1944                 info->signals |= SerialSignal_CTS;
1945                 info->input_signal_events.cts_up++;
1946         } else {
1947                 info->signals &= ~SerialSignal_CTS;
1948                 info->input_signal_events.cts_down++;
1949         }
1950         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1951         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1952                 slgt_irq_off(info, IRQ_CTS);
1953                 return;
1954         }
1955         info->icount.cts++;
1956         wake_up_interruptible(&info->status_event_wait_q);
1957         wake_up_interruptible(&info->event_wait_q);
1958         info->pending_bh |= BH_STATUS;
1959
1960         if (tty_port_cts_enabled(&info->port)) {
1961                 if (info->port.tty) {
1962                         if (info->port.tty->hw_stopped) {
1963                                 if (info->signals & SerialSignal_CTS) {
1964                                         info->port.tty->hw_stopped = 0;
1965                                         info->pending_bh |= BH_TRANSMIT;
1966                                         return;
1967                                 }
1968                         } else {
1969                                 if (!(info->signals & SerialSignal_CTS))
1970                                         info->port.tty->hw_stopped = 1;
1971                         }
1972                 }
1973         }
1974 }
1975
1976 static void dcd_change(struct slgt_info *info, unsigned short status)
1977 {
1978         if (status & BIT1) {
1979                 info->signals |= SerialSignal_DCD;
1980                 info->input_signal_events.dcd_up++;
1981         } else {
1982                 info->signals &= ~SerialSignal_DCD;
1983                 info->input_signal_events.dcd_down++;
1984         }
1985         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1986         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1987                 slgt_irq_off(info, IRQ_DCD);
1988                 return;
1989         }
1990         info->icount.dcd++;
1991 #if SYNCLINK_GENERIC_HDLC
1992         if (info->netcount) {
1993                 if (info->signals & SerialSignal_DCD)
1994                         netif_carrier_on(info->netdev);
1995                 else
1996                         netif_carrier_off(info->netdev);
1997         }
1998 #endif
1999         wake_up_interruptible(&info->status_event_wait_q);
2000         wake_up_interruptible(&info->event_wait_q);
2001         info->pending_bh |= BH_STATUS;
2002
2003         if (tty_port_check_carrier(&info->port)) {
2004                 if (info->signals & SerialSignal_DCD)
2005                         wake_up_interruptible(&info->port.open_wait);
2006                 else {
2007                         if (info->port.tty)
2008                                 tty_hangup(info->port.tty);
2009                 }
2010         }
2011 }
2012
2013 static void ri_change(struct slgt_info *info, unsigned short status)
2014 {
2015         if (status & BIT0) {
2016                 info->signals |= SerialSignal_RI;
2017                 info->input_signal_events.ri_up++;
2018         } else {
2019                 info->signals &= ~SerialSignal_RI;
2020                 info->input_signal_events.ri_down++;
2021         }
2022         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2023         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2024                 slgt_irq_off(info, IRQ_RI);
2025                 return;
2026         }
2027         info->icount.rng++;
2028         wake_up_interruptible(&info->status_event_wait_q);
2029         wake_up_interruptible(&info->event_wait_q);
2030         info->pending_bh |= BH_STATUS;
2031 }
2032
2033 static void isr_rxdata(struct slgt_info *info)
2034 {
2035         unsigned int count = info->rbuf_fill_count;
2036         unsigned int i = info->rbuf_fill_index;
2037         unsigned short reg;
2038
2039         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2040                 reg = rd_reg16(info, RDR);
2041                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2042                 if (desc_complete(info->rbufs[i])) {
2043                         /* all buffers full */
2044                         rx_stop(info);
2045                         info->rx_restart = true;
2046                         continue;
2047                 }
2048                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2049                 /* async mode saves status byte to buffer for each data byte */
2050                 if (info->params.mode == MGSL_MODE_ASYNC)
2051                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2052                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2053                         /* buffer full or end of frame */
2054                         set_desc_count(info->rbufs[i], count);
2055                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2056                         info->rbuf_fill_count = count = 0;
2057                         if (++i == info->rbuf_count)
2058                                 i = 0;
2059                         info->pending_bh |= BH_RECEIVE;
2060                 }
2061         }
2062
2063         info->rbuf_fill_index = i;
2064         info->rbuf_fill_count = count;
2065 }
2066
2067 static void isr_serial(struct slgt_info *info)
2068 {
2069         unsigned short status = rd_reg16(info, SSR);
2070
2071         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2072
2073         wr_reg16(info, SSR, status); /* clear pending */
2074
2075         info->irq_occurred = true;
2076
2077         if (info->params.mode == MGSL_MODE_ASYNC) {
2078                 if (status & IRQ_TXIDLE) {
2079                         if (info->tx_active)
2080                                 isr_txeom(info, status);
2081                 }
2082                 if (info->rx_pio && (status & IRQ_RXDATA))
2083                         isr_rxdata(info);
2084                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2085                         info->icount.brk++;
2086                         /* process break detection if tty control allows */
2087                         if (info->port.tty) {
2088                                 if (!(status & info->ignore_status_mask)) {
2089                                         if (info->read_status_mask & MASK_BREAK) {
2090                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2091                                                 if (info->port.flags & ASYNC_SAK)
2092                                                         do_SAK(info->port.tty);
2093                                         }
2094                                 }
2095                         }
2096                 }
2097         } else {
2098                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2099                         isr_txeom(info, status);
2100                 if (info->rx_pio && (status & IRQ_RXDATA))
2101                         isr_rxdata(info);
2102                 if (status & IRQ_RXIDLE) {
2103                         if (status & RXIDLE)
2104                                 info->icount.rxidle++;
2105                         else
2106                                 info->icount.exithunt++;
2107                         wake_up_interruptible(&info->event_wait_q);
2108                 }
2109
2110                 if (status & IRQ_RXOVER)
2111                         rx_start(info);
2112         }
2113
2114         if (status & IRQ_DSR)
2115                 dsr_change(info, status);
2116         if (status & IRQ_CTS)
2117                 cts_change(info, status);
2118         if (status & IRQ_DCD)
2119                 dcd_change(info, status);
2120         if (status & IRQ_RI)
2121                 ri_change(info, status);
2122 }
2123
2124 static void isr_rdma(struct slgt_info *info)
2125 {
2126         unsigned int status = rd_reg32(info, RDCSR);
2127
2128         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2129
2130         /* RDCSR (rx DMA control/status)
2131          *
2132          * 31..07  reserved
2133          * 06      save status byte to DMA buffer
2134          * 05      error
2135          * 04      eol (end of list)
2136          * 03      eob (end of buffer)
2137          * 02      IRQ enable
2138          * 01      reset
2139          * 00      enable
2140          */
2141         wr_reg32(info, RDCSR, status);  /* clear pending */
2142
2143         if (status & (BIT5 + BIT4)) {
2144                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2145                 info->rx_restart = true;
2146         }
2147         info->pending_bh |= BH_RECEIVE;
2148 }
2149
2150 static void isr_tdma(struct slgt_info *info)
2151 {
2152         unsigned int status = rd_reg32(info, TDCSR);
2153
2154         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2155
2156         /* TDCSR (tx DMA control/status)
2157          *
2158          * 31..06  reserved
2159          * 05      error
2160          * 04      eol (end of list)
2161          * 03      eob (end of buffer)
2162          * 02      IRQ enable
2163          * 01      reset
2164          * 00      enable
2165          */
2166         wr_reg32(info, TDCSR, status);  /* clear pending */
2167
2168         if (status & (BIT5 + BIT4 + BIT3)) {
2169                 // another transmit buffer has completed
2170                 // run bottom half to get more send data from user
2171                 info->pending_bh |= BH_TRANSMIT;
2172         }
2173 }
2174
2175 /*
2176  * return true if there are unsent tx DMA buffers, otherwise false
2177  *
2178  * if there are unsent buffers then info->tbuf_start
2179  * is set to index of first unsent buffer
2180  */
2181 static bool unsent_tbufs(struct slgt_info *info)
2182 {
2183         unsigned int i = info->tbuf_current;
2184         bool rc = false;
2185
2186         /*
2187          * search backwards from last loaded buffer (precedes tbuf_current)
2188          * for first unsent buffer (desc_count > 0)
2189          */
2190
2191         do {
2192                 if (i)
2193                         i--;
2194                 else
2195                         i = info->tbuf_count - 1;
2196                 if (!desc_count(info->tbufs[i]))
2197                         break;
2198                 info->tbuf_start = i;
2199                 rc = true;
2200         } while (i != info->tbuf_current);
2201
2202         return rc;
2203 }
2204
2205 static void isr_txeom(struct slgt_info *info, unsigned short status)
2206 {
2207         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2208
2209         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2210         tdma_reset(info);
2211         if (status & IRQ_TXUNDER) {
2212                 unsigned short val = rd_reg16(info, TCR);
2213                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2214                 wr_reg16(info, TCR, val); /* clear reset bit */
2215         }
2216
2217         if (info->tx_active) {
2218                 if (info->params.mode != MGSL_MODE_ASYNC) {
2219                         if (status & IRQ_TXUNDER)
2220                                 info->icount.txunder++;
2221                         else if (status & IRQ_TXIDLE)
2222                                 info->icount.txok++;
2223                 }
2224
2225                 if (unsent_tbufs(info)) {
2226                         tx_start(info);
2227                         update_tx_timer(info);
2228                         return;
2229                 }
2230                 info->tx_active = false;
2231
2232                 del_timer(&info->tx_timer);
2233
2234                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2235                         info->signals &= ~SerialSignal_RTS;
2236                         info->drop_rts_on_tx_done = false;
2237                         set_gtsignals(info);
2238                 }
2239
2240 #if SYNCLINK_GENERIC_HDLC
2241                 if (info->netcount)
2242                         hdlcdev_tx_done(info);
2243                 else
2244 #endif
2245                 {
2246                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2247                                 tx_stop(info);
2248                                 return;
2249                         }
2250                         info->pending_bh |= BH_TRANSMIT;
2251                 }
2252         }
2253 }
2254
2255 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2256 {
2257         struct cond_wait *w, *prev;
2258
2259         /* wake processes waiting for specific transitions */
2260         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2261                 if (w->data & changed) {
2262                         w->data = state;
2263                         wake_up_interruptible(&w->q);
2264                         if (prev != NULL)
2265                                 prev->next = w->next;
2266                         else
2267                                 info->gpio_wait_q = w->next;
2268                 } else
2269                         prev = w;
2270         }
2271 }
2272
2273 /* interrupt service routine
2274  *
2275  *      irq     interrupt number
2276  *      dev_id  device ID supplied during interrupt registration
2277  */
2278 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2279 {
2280         struct slgt_info *info = dev_id;
2281         unsigned int gsr;
2282         unsigned int i;
2283
2284         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2285
2286         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2287                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2288                 info->irq_occurred = true;
2289                 for(i=0; i < info->port_count ; i++) {
2290                         if (info->port_array[i] == NULL)
2291                                 continue;
2292                         spin_lock(&info->port_array[i]->lock);
2293                         if (gsr & (BIT8 << i))
2294                                 isr_serial(info->port_array[i]);
2295                         if (gsr & (BIT16 << (i*2)))
2296                                 isr_rdma(info->port_array[i]);
2297                         if (gsr & (BIT17 << (i*2)))
2298                                 isr_tdma(info->port_array[i]);
2299                         spin_unlock(&info->port_array[i]->lock);
2300                 }
2301         }
2302
2303         if (info->gpio_present) {
2304                 unsigned int state;
2305                 unsigned int changed;
2306                 spin_lock(&info->lock);
2307                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2308                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2309                         /* read latched state of GPIO signals */
2310                         state = rd_reg32(info, IOVR);
2311                         /* clear pending GPIO interrupt bits */
2312                         wr_reg32(info, IOSR, changed);
2313                         for (i=0 ; i < info->port_count ; i++) {
2314                                 if (info->port_array[i] != NULL)
2315                                         isr_gpio(info->port_array[i], changed, state);
2316                         }
2317                 }
2318                 spin_unlock(&info->lock);
2319         }
2320
2321         for(i=0; i < info->port_count ; i++) {
2322                 struct slgt_info *port = info->port_array[i];
2323                 if (port == NULL)
2324                         continue;
2325                 spin_lock(&port->lock);
2326                 if ((port->port.count || port->netcount) &&
2327                     port->pending_bh && !port->bh_running &&
2328                     !port->bh_requested) {
2329                         DBGISR(("%s bh queued\n", port->device_name));
2330                         schedule_work(&port->task);
2331                         port->bh_requested = true;
2332                 }
2333                 spin_unlock(&port->lock);
2334         }
2335
2336         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2337         return IRQ_HANDLED;
2338 }
2339
2340 static int startup(struct slgt_info *info)
2341 {
2342         DBGINFO(("%s startup\n", info->device_name));
2343
2344         if (tty_port_initialized(&info->port))
2345                 return 0;
2346
2347         if (!info->tx_buf) {
2348                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2349                 if (!info->tx_buf) {
2350                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2351                         return -ENOMEM;
2352                 }
2353         }
2354
2355         info->pending_bh = 0;
2356
2357         memset(&info->icount, 0, sizeof(info->icount));
2358
2359         /* program hardware for current parameters */
2360         change_params(info);
2361
2362         if (info->port.tty)
2363                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2364
2365         tty_port_set_initialized(&info->port, 1);
2366
2367         return 0;
2368 }
2369
2370 /*
2371  *  called by close() and hangup() to shutdown hardware
2372  */
2373 static void shutdown(struct slgt_info *info)
2374 {
2375         unsigned long flags;
2376
2377         if (!tty_port_initialized(&info->port))
2378                 return;
2379
2380         DBGINFO(("%s shutdown\n", info->device_name));
2381
2382         /* clear status wait queue because status changes */
2383         /* can't happen after shutting down the hardware */
2384         wake_up_interruptible(&info->status_event_wait_q);
2385         wake_up_interruptible(&info->event_wait_q);
2386
2387         del_timer_sync(&info->tx_timer);
2388         del_timer_sync(&info->rx_timer);
2389
2390         kfree(info->tx_buf);
2391         info->tx_buf = NULL;
2392
2393         spin_lock_irqsave(&info->lock,flags);
2394
2395         tx_stop(info);
2396         rx_stop(info);
2397
2398         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2399
2400         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2401                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2402                 set_gtsignals(info);
2403         }
2404
2405         flush_cond_wait(&info->gpio_wait_q);
2406
2407         spin_unlock_irqrestore(&info->lock,flags);
2408
2409         if (info->port.tty)
2410                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2411
2412         tty_port_set_initialized(&info->port, 0);
2413 }
2414
2415 static void program_hw(struct slgt_info *info)
2416 {
2417         unsigned long flags;
2418
2419         spin_lock_irqsave(&info->lock,flags);
2420
2421         rx_stop(info);
2422         tx_stop(info);
2423
2424         if (info->params.mode != MGSL_MODE_ASYNC ||
2425             info->netcount)
2426                 sync_mode(info);
2427         else
2428                 async_mode(info);
2429
2430         set_gtsignals(info);
2431
2432         info->dcd_chkcount = 0;
2433         info->cts_chkcount = 0;
2434         info->ri_chkcount = 0;
2435         info->dsr_chkcount = 0;
2436
2437         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2438         get_gtsignals(info);
2439
2440         if (info->netcount ||
2441             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2442                 rx_start(info);
2443
2444         spin_unlock_irqrestore(&info->lock,flags);
2445 }
2446
2447 /*
2448  * reconfigure adapter based on new parameters
2449  */
2450 static void change_params(struct slgt_info *info)
2451 {
2452         unsigned cflag;
2453         int bits_per_char;
2454
2455         if (!info->port.tty)
2456                 return;
2457         DBGINFO(("%s change_params\n", info->device_name));
2458
2459         cflag = info->port.tty->termios.c_cflag;
2460
2461         /* if B0 rate (hangup) specified then negate RTS and DTR */
2462         /* otherwise assert RTS and DTR */
2463         if (cflag & CBAUD)
2464                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2465         else
2466                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2467
2468         /* byte size and parity */
2469
2470         switch (cflag & CSIZE) {
2471         case CS5: info->params.data_bits = 5; break;
2472         case CS6: info->params.data_bits = 6; break;
2473         case CS7: info->params.data_bits = 7; break;
2474         case CS8: info->params.data_bits = 8; break;
2475         default:  info->params.data_bits = 7; break;
2476         }
2477
2478         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2479
2480         if (cflag & PARENB)
2481                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2482         else
2483                 info->params.parity = ASYNC_PARITY_NONE;
2484
2485         /* calculate number of jiffies to transmit a full
2486          * FIFO (32 bytes) at specified data rate
2487          */
2488         bits_per_char = info->params.data_bits +
2489                         info->params.stop_bits + 1;
2490
2491         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2492
2493         if (info->params.data_rate) {
2494                 info->timeout = (32*HZ*bits_per_char) /
2495                                 info->params.data_rate;
2496         }
2497         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2498
2499         tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2500         tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2501
2502         /* process tty input control flags */
2503
2504         info->read_status_mask = IRQ_RXOVER;
2505         if (I_INPCK(info->port.tty))
2506                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2507         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2508                 info->read_status_mask |= MASK_BREAK;
2509         if (I_IGNPAR(info->port.tty))
2510                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2511         if (I_IGNBRK(info->port.tty)) {
2512                 info->ignore_status_mask |= MASK_BREAK;
2513                 /* If ignoring parity and break indicators, ignore
2514                  * overruns too.  (For real raw support).
2515                  */
2516                 if (I_IGNPAR(info->port.tty))
2517                         info->ignore_status_mask |= MASK_OVERRUN;
2518         }
2519
2520         program_hw(info);
2521 }
2522
2523 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2524 {
2525         DBGINFO(("%s get_stats\n",  info->device_name));
2526         if (!user_icount) {
2527                 memset(&info->icount, 0, sizeof(info->icount));
2528         } else {
2529                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2530                         return -EFAULT;
2531         }
2532         return 0;
2533 }
2534
2535 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2536 {
2537         DBGINFO(("%s get_params\n", info->device_name));
2538         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2539                 return -EFAULT;
2540         return 0;
2541 }
2542
2543 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2544 {
2545         unsigned long flags;
2546         MGSL_PARAMS tmp_params;
2547
2548         DBGINFO(("%s set_params\n", info->device_name));
2549         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2550                 return -EFAULT;
2551
2552         spin_lock_irqsave(&info->lock, flags);
2553         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2554                 info->base_clock = tmp_params.clock_speed;
2555         else
2556                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2557         spin_unlock_irqrestore(&info->lock, flags);
2558
2559         program_hw(info);
2560
2561         return 0;
2562 }
2563
2564 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2565 {
2566         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2567         if (put_user(info->idle_mode, idle_mode))
2568                 return -EFAULT;
2569         return 0;
2570 }
2571
2572 static int set_txidle(struct slgt_info *info, int idle_mode)
2573 {
2574         unsigned long flags;
2575         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2576         spin_lock_irqsave(&info->lock,flags);
2577         info->idle_mode = idle_mode;
2578         if (info->params.mode != MGSL_MODE_ASYNC)
2579                 tx_set_idle(info);
2580         spin_unlock_irqrestore(&info->lock,flags);
2581         return 0;
2582 }
2583
2584 static int tx_enable(struct slgt_info *info, int enable)
2585 {
2586         unsigned long flags;
2587         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2588         spin_lock_irqsave(&info->lock,flags);
2589         if (enable) {
2590                 if (!info->tx_enabled)
2591                         tx_start(info);
2592         } else {
2593                 if (info->tx_enabled)
2594                         tx_stop(info);
2595         }
2596         spin_unlock_irqrestore(&info->lock,flags);
2597         return 0;
2598 }
2599
2600 /*
2601  * abort transmit HDLC frame
2602  */
2603 static int tx_abort(struct slgt_info *info)
2604 {
2605         unsigned long flags;
2606         DBGINFO(("%s tx_abort\n", info->device_name));
2607         spin_lock_irqsave(&info->lock,flags);
2608         tdma_reset(info);
2609         spin_unlock_irqrestore(&info->lock,flags);
2610         return 0;
2611 }
2612
2613 static int rx_enable(struct slgt_info *info, int enable)
2614 {
2615         unsigned long flags;
2616         unsigned int rbuf_fill_level;
2617         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2618         spin_lock_irqsave(&info->lock,flags);
2619         /*
2620          * enable[31..16] = receive DMA buffer fill level
2621          * 0 = noop (leave fill level unchanged)
2622          * fill level must be multiple of 4 and <= buffer size
2623          */
2624         rbuf_fill_level = ((unsigned int)enable) >> 16;
2625         if (rbuf_fill_level) {
2626                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2627                         spin_unlock_irqrestore(&info->lock, flags);
2628                         return -EINVAL;
2629                 }
2630                 info->rbuf_fill_level = rbuf_fill_level;
2631                 if (rbuf_fill_level < 128)
2632                         info->rx_pio = 1; /* PIO mode */
2633                 else
2634                         info->rx_pio = 0; /* DMA mode */
2635                 rx_stop(info); /* restart receiver to use new fill level */
2636         }
2637
2638         /*
2639          * enable[1..0] = receiver enable command
2640          * 0 = disable
2641          * 1 = enable
2642          * 2 = enable or force hunt mode if already enabled
2643          */
2644         enable &= 3;
2645         if (enable) {
2646                 if (!info->rx_enabled)
2647                         rx_start(info);
2648                 else if (enable == 2) {
2649                         /* force hunt mode (write 1 to RCR[3]) */
2650                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2651                 }
2652         } else {
2653                 if (info->rx_enabled)
2654                         rx_stop(info);
2655         }
2656         spin_unlock_irqrestore(&info->lock,flags);
2657         return 0;
2658 }
2659
2660 /*
2661  *  wait for specified event to occur
2662  */
2663 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2664 {
2665         unsigned long flags;
2666         int s;
2667         int rc=0;
2668         struct mgsl_icount cprev, cnow;
2669         int events;
2670         int mask;
2671         struct  _input_signal_events oldsigs, newsigs;
2672         DECLARE_WAITQUEUE(wait, current);
2673
2674         if (get_user(mask, mask_ptr))
2675                 return -EFAULT;
2676
2677         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2678
2679         spin_lock_irqsave(&info->lock,flags);
2680
2681         /* return immediately if state matches requested events */
2682         get_gtsignals(info);
2683         s = info->signals;
2684
2685         events = mask &
2686                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2687                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2688                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2689                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2690         if (events) {
2691                 spin_unlock_irqrestore(&info->lock,flags);
2692                 goto exit;
2693         }
2694
2695         /* save current irq counts */
2696         cprev = info->icount;
2697         oldsigs = info->input_signal_events;
2698
2699         /* enable hunt and idle irqs if needed */
2700         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2701                 unsigned short val = rd_reg16(info, SCR);
2702                 if (!(val & IRQ_RXIDLE))
2703                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2704         }
2705
2706         set_current_state(TASK_INTERRUPTIBLE);
2707         add_wait_queue(&info->event_wait_q, &wait);
2708
2709         spin_unlock_irqrestore(&info->lock,flags);
2710
2711         for(;;) {
2712                 schedule();
2713                 if (signal_pending(current)) {
2714                         rc = -ERESTARTSYS;
2715                         break;
2716                 }
2717
2718                 /* get current irq counts */
2719                 spin_lock_irqsave(&info->lock,flags);
2720                 cnow = info->icount;
2721                 newsigs = info->input_signal_events;
2722                 set_current_state(TASK_INTERRUPTIBLE);
2723                 spin_unlock_irqrestore(&info->lock,flags);
2724
2725                 /* if no change, wait aborted for some reason */
2726                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2727                     newsigs.dsr_down == oldsigs.dsr_down &&
2728                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2729                     newsigs.dcd_down == oldsigs.dcd_down &&
2730                     newsigs.cts_up   == oldsigs.cts_up   &&
2731                     newsigs.cts_down == oldsigs.cts_down &&
2732                     newsigs.ri_up    == oldsigs.ri_up    &&
2733                     newsigs.ri_down  == oldsigs.ri_down  &&
2734                     cnow.exithunt    == cprev.exithunt   &&
2735                     cnow.rxidle      == cprev.rxidle) {
2736                         rc = -EIO;
2737                         break;
2738                 }
2739
2740                 events = mask &
2741                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2742                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2743                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2744                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2745                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2746                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2747                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2748                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2749                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2750                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2751                 if (events)
2752                         break;
2753
2754                 cprev = cnow;
2755                 oldsigs = newsigs;
2756         }
2757
2758         remove_wait_queue(&info->event_wait_q, &wait);
2759         set_current_state(TASK_RUNNING);
2760
2761
2762         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2763                 spin_lock_irqsave(&info->lock,flags);
2764                 if (!waitqueue_active(&info->event_wait_q)) {
2765                         /* disable enable exit hunt mode/idle rcvd IRQs */
2766                         wr_reg16(info, SCR,
2767                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2768                 }
2769                 spin_unlock_irqrestore(&info->lock,flags);
2770         }
2771 exit:
2772         if (rc == 0)
2773                 rc = put_user(events, mask_ptr);
2774         return rc;
2775 }
2776
2777 static int get_interface(struct slgt_info *info, int __user *if_mode)
2778 {
2779         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2780         if (put_user(info->if_mode, if_mode))
2781                 return -EFAULT;
2782         return 0;
2783 }
2784
2785 static int set_interface(struct slgt_info *info, int if_mode)
2786 {
2787         unsigned long flags;
2788         unsigned short val;
2789
2790         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2791         spin_lock_irqsave(&info->lock,flags);
2792         info->if_mode = if_mode;
2793
2794         msc_set_vcr(info);
2795
2796         /* TCR (tx control) 07  1=RTS driver control */
2797         val = rd_reg16(info, TCR);
2798         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2799                 val |= BIT7;
2800         else
2801                 val &= ~BIT7;
2802         wr_reg16(info, TCR, val);
2803
2804         spin_unlock_irqrestore(&info->lock,flags);
2805         return 0;
2806 }
2807
2808 static int get_xsync(struct slgt_info *info, int __user *xsync)
2809 {
2810         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2811         if (put_user(info->xsync, xsync))
2812                 return -EFAULT;
2813         return 0;
2814 }
2815
2816 /*
2817  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2818  *
2819  * sync pattern is contained in least significant bytes of value
2820  * most significant byte of sync pattern is oldest (1st sent/detected)
2821  */
2822 static int set_xsync(struct slgt_info *info, int xsync)
2823 {
2824         unsigned long flags;
2825
2826         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2827         spin_lock_irqsave(&info->lock, flags);
2828         info->xsync = xsync;
2829         wr_reg32(info, XSR, xsync);
2830         spin_unlock_irqrestore(&info->lock, flags);
2831         return 0;
2832 }
2833
2834 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2835 {
2836         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2837         if (put_user(info->xctrl, xctrl))
2838                 return -EFAULT;
2839         return 0;
2840 }
2841
2842 /*
2843  * set extended control options
2844  *
2845  * xctrl[31:19] reserved, must be zero
2846  * xctrl[18:17] extended sync pattern length in bytes
2847  *              00 = 1 byte  in xsr[7:0]
2848  *              01 = 2 bytes in xsr[15:0]
2849  *              10 = 3 bytes in xsr[23:0]
2850  *              11 = 4 bytes in xsr[31:0]
2851  * xctrl[16]    1 = enable terminal count, 0=disabled
2852  * xctrl[15:0]  receive terminal count for fixed length packets
2853  *              value is count minus one (0 = 1 byte packet)
2854  *              when terminal count is reached, receiver
2855  *              automatically returns to hunt mode and receive
2856  *              FIFO contents are flushed to DMA buffers with
2857  *              end of frame (EOF) status
2858  */
2859 static int set_xctrl(struct slgt_info *info, int xctrl)
2860 {
2861         unsigned long flags;
2862
2863         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2864         spin_lock_irqsave(&info->lock, flags);
2865         info->xctrl = xctrl;
2866         wr_reg32(info, XCR, xctrl);
2867         spin_unlock_irqrestore(&info->lock, flags);
2868         return 0;
2869 }
2870
2871 /*
2872  * set general purpose IO pin state and direction
2873  *
2874  * user_gpio fields:
2875  * state   each bit indicates a pin state
2876  * smask   set bit indicates pin state to set
2877  * dir     each bit indicates a pin direction (0=input, 1=output)
2878  * dmask   set bit indicates pin direction to set
2879  */
2880 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2881 {
2882         unsigned long flags;
2883         struct gpio_desc gpio;
2884         __u32 data;
2885
2886         if (!info->gpio_present)
2887                 return -EINVAL;
2888         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2889                 return -EFAULT;
2890         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2891                  info->device_name, gpio.state, gpio.smask,
2892                  gpio.dir, gpio.dmask));
2893
2894         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2895         if (gpio.dmask) {
2896                 data = rd_reg32(info, IODR);
2897                 data |= gpio.dmask & gpio.dir;
2898                 data &= ~(gpio.dmask & ~gpio.dir);
2899                 wr_reg32(info, IODR, data);
2900         }
2901         if (gpio.smask) {
2902                 data = rd_reg32(info, IOVR);
2903                 data |= gpio.smask & gpio.state;
2904                 data &= ~(gpio.smask & ~gpio.state);
2905                 wr_reg32(info, IOVR, data);
2906         }
2907         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2908
2909         return 0;
2910 }
2911
2912 /*
2913  * get general purpose IO pin state and direction
2914  */
2915 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2916 {
2917         struct gpio_desc gpio;
2918         if (!info->gpio_present)
2919                 return -EINVAL;
2920         gpio.state = rd_reg32(info, IOVR);
2921         gpio.smask = 0xffffffff;
2922         gpio.dir   = rd_reg32(info, IODR);
2923         gpio.dmask = 0xffffffff;
2924         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2925                 return -EFAULT;
2926         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2927                  info->device_name, gpio.state, gpio.dir));
2928         return 0;
2929 }
2930
2931 /*
2932  * conditional wait facility
2933  */
2934 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2935 {
2936         init_waitqueue_head(&w->q);
2937         init_waitqueue_entry(&w->wait, current);
2938         w->data = data;
2939 }
2940
2941 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2942 {
2943         set_current_state(TASK_INTERRUPTIBLE);
2944         add_wait_queue(&w->q, &w->wait);
2945         w->next = *head;
2946         *head = w;
2947 }
2948
2949 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2950 {
2951         struct cond_wait *w, *prev;
2952         remove_wait_queue(&cw->q, &cw->wait);
2953         set_current_state(TASK_RUNNING);
2954         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2955                 if (w == cw) {
2956                         if (prev != NULL)
2957                                 prev->next = w->next;
2958                         else
2959                                 *head = w->next;
2960                         break;
2961                 }
2962         }
2963 }
2964
2965 static void flush_cond_wait(struct cond_wait **head)
2966 {
2967         while (*head != NULL) {
2968                 wake_up_interruptible(&(*head)->q);
2969                 *head = (*head)->next;
2970         }
2971 }
2972
2973 /*
2974  * wait for general purpose I/O pin(s) to enter specified state
2975  *
2976  * user_gpio fields:
2977  * state - bit indicates target pin state
2978  * smask - set bit indicates watched pin
2979  *
2980  * The wait ends when at least one watched pin enters the specified
2981  * state. When 0 (no error) is returned, user_gpio->state is set to the
2982  * state of all GPIO pins when the wait ends.
2983  *
2984  * Note: Each pin may be a dedicated input, dedicated output, or
2985  * configurable input/output. The number and configuration of pins
2986  * varies with the specific adapter model. Only input pins (dedicated
2987  * or configured) can be monitored with this function.
2988  */
2989 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2990 {
2991         unsigned long flags;
2992         int rc = 0;
2993         struct gpio_desc gpio;
2994         struct cond_wait wait;
2995         u32 state;
2996
2997         if (!info->gpio_present)
2998                 return -EINVAL;
2999         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3000                 return -EFAULT;
3001         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3002                  info->device_name, gpio.state, gpio.smask));
3003         /* ignore output pins identified by set IODR bit */
3004         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3005                 return -EINVAL;
3006         init_cond_wait(&wait, gpio.smask);
3007
3008         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3009         /* enable interrupts for watched pins */
3010         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3011         /* get current pin states */
3012         state = rd_reg32(info, IOVR);
3013
3014         if (gpio.smask & ~(state ^ gpio.state)) {
3015                 /* already in target state */
3016                 gpio.state = state;
3017         } else {
3018                 /* wait for target state */
3019                 add_cond_wait(&info->gpio_wait_q, &wait);
3020                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3021                 schedule();
3022                 if (signal_pending(current))
3023                         rc = -ERESTARTSYS;
3024                 else
3025                         gpio.state = wait.data;
3026                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3027                 remove_cond_wait(&info->gpio_wait_q, &wait);
3028         }
3029
3030         /* disable all GPIO interrupts if no waiting processes */
3031         if (info->gpio_wait_q == NULL)
3032                 wr_reg32(info, IOER, 0);
3033         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3034
3035         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3036                 rc = -EFAULT;
3037         return rc;
3038 }
3039
3040 static int modem_input_wait(struct slgt_info *info,int arg)
3041 {
3042         unsigned long flags;
3043         int rc;
3044         struct mgsl_icount cprev, cnow;
3045         DECLARE_WAITQUEUE(wait, current);
3046
3047         /* save current irq counts */
3048         spin_lock_irqsave(&info->lock,flags);
3049         cprev = info->icount;
3050         add_wait_queue(&info->status_event_wait_q, &wait);
3051         set_current_state(TASK_INTERRUPTIBLE);
3052         spin_unlock_irqrestore(&info->lock,flags);
3053
3054         for(;;) {
3055                 schedule();
3056                 if (signal_pending(current)) {
3057                         rc = -ERESTARTSYS;
3058                         break;
3059                 }
3060
3061                 /* get new irq counts */
3062                 spin_lock_irqsave(&info->lock,flags);
3063                 cnow = info->icount;
3064                 set_current_state(TASK_INTERRUPTIBLE);
3065                 spin_unlock_irqrestore(&info->lock,flags);
3066
3067                 /* if no change, wait aborted for some reason */
3068                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3069                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3070                         rc = -EIO;
3071                         break;
3072                 }
3073
3074                 /* check for change in caller specified modem input */
3075                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3076                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3077                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3078                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3079                         rc = 0;
3080                         break;
3081                 }
3082
3083                 cprev = cnow;
3084         }
3085         remove_wait_queue(&info->status_event_wait_q, &wait);
3086         set_current_state(TASK_RUNNING);
3087         return rc;
3088 }
3089
3090 /*
3091  *  return state of serial control and status signals
3092  */
3093 static int tiocmget(struct tty_struct *tty)
3094 {
3095         struct slgt_info *info = tty->driver_data;
3096         unsigned int result;
3097         unsigned long flags;
3098
3099         spin_lock_irqsave(&info->lock,flags);
3100         get_gtsignals(info);
3101         spin_unlock_irqrestore(&info->lock,flags);
3102
3103         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3104                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3105                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3106                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3107                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3108                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3109
3110         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3111         return result;
3112 }
3113
3114 /*
3115  * set modem control signals (DTR/RTS)
3116  *
3117  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3118  *              TIOCMSET = set/clear signal values
3119  *      value   bit mask for command
3120  */
3121 static int tiocmset(struct tty_struct *tty,
3122                     unsigned int set, unsigned int clear)
3123 {
3124         struct slgt_info *info = tty->driver_data;
3125         unsigned long flags;
3126
3127         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3128
3129         if (set & TIOCM_RTS)
3130                 info->signals |= SerialSignal_RTS;
3131         if (set & TIOCM_DTR)
3132                 info->signals |= SerialSignal_DTR;
3133         if (clear & TIOCM_RTS)
3134                 info->signals &= ~SerialSignal_RTS;
3135         if (clear & TIOCM_DTR)
3136                 info->signals &= ~SerialSignal_DTR;
3137
3138         spin_lock_irqsave(&info->lock,flags);
3139         set_gtsignals(info);
3140         spin_unlock_irqrestore(&info->lock,flags);
3141         return 0;
3142 }
3143
3144 static int carrier_raised(struct tty_port *port)
3145 {
3146         unsigned long flags;
3147         struct slgt_info *info = container_of(port, struct slgt_info, port);
3148
3149         spin_lock_irqsave(&info->lock,flags);
3150         get_gtsignals(info);
3151         spin_unlock_irqrestore(&info->lock,flags);
3152         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3153 }
3154
3155 static void dtr_rts(struct tty_port *port, int on)
3156 {
3157         unsigned long flags;
3158         struct slgt_info *info = container_of(port, struct slgt_info, port);
3159
3160         spin_lock_irqsave(&info->lock,flags);
3161         if (on)
3162                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3163         else
3164                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3165         set_gtsignals(info);
3166         spin_unlock_irqrestore(&info->lock,flags);
3167 }
3168
3169
3170 /*
3171  *  block current process until the device is ready to open
3172  */
3173 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3174                            struct slgt_info *info)
3175 {
3176         DECLARE_WAITQUEUE(wait, current);
3177         int             retval;
3178         bool            do_clocal = false;
3179         unsigned long   flags;
3180         int             cd;
3181         struct tty_port *port = &info->port;
3182
3183         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3184
3185         if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3186                 /* nonblock mode is set or port is not enabled */
3187                 tty_port_set_active(port, 1);
3188                 return 0;
3189         }
3190
3191         if (C_CLOCAL(tty))
3192                 do_clocal = true;
3193
3194         /* Wait for carrier detect and the line to become
3195          * free (i.e., not in use by the callout).  While we are in
3196          * this loop, port->count is dropped by one, so that
3197          * close() knows when to free things.  We restore it upon
3198          * exit, either normal or abnormal.
3199          */
3200
3201         retval = 0;
3202         add_wait_queue(&port->open_wait, &wait);
3203
3204         spin_lock_irqsave(&info->lock, flags);
3205         port->count--;
3206         spin_unlock_irqrestore(&info->lock, flags);
3207         port->blocked_open++;
3208
3209         while (1) {
3210                 if (C_BAUD(tty) && tty_port_initialized(port))
3211                         tty_port_raise_dtr_rts(port);
3212
3213                 set_current_state(TASK_INTERRUPTIBLE);
3214
3215                 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3216                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3217                                         -EAGAIN : -ERESTARTSYS;
3218                         break;
3219                 }
3220
3221                 cd = tty_port_carrier_raised(port);
3222                 if (do_clocal || cd)
3223                         break;
3224
3225                 if (signal_pending(current)) {
3226                         retval = -ERESTARTSYS;
3227                         break;
3228                 }
3229
3230                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3231                 tty_unlock(tty);
3232                 schedule();
3233                 tty_lock(tty);
3234         }
3235
3236         set_current_state(TASK_RUNNING);
3237         remove_wait_queue(&port->open_wait, &wait);
3238
3239         if (!tty_hung_up_p(filp))
3240                 port->count++;
3241         port->blocked_open--;
3242
3243         if (!retval)
3244                 tty_port_set_active(port, 1);
3245
3246         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3247         return retval;
3248 }
3249
3250 /*
3251  * allocate buffers used for calling line discipline receive_buf
3252  * directly in synchronous mode
3253  * note: add 5 bytes to max frame size to allow appending
3254  * 32-bit CRC and status byte when configured to do so
3255  */
3256 static int alloc_tmp_rbuf(struct slgt_info *info)
3257 {
3258         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3259         if (info->tmp_rbuf == NULL)
3260                 return -ENOMEM;
3261         /* unused flag buffer to satisfy receive_buf calling interface */
3262         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3263         if (!info->flag_buf) {
3264                 kfree(info->tmp_rbuf);
3265                 info->tmp_rbuf = NULL;
3266                 return -ENOMEM;
3267         }
3268         return 0;
3269 }
3270
3271 static void free_tmp_rbuf(struct slgt_info *info)
3272 {
3273         kfree(info->tmp_rbuf);
3274         info->tmp_rbuf = NULL;
3275         kfree(info->flag_buf);
3276         info->flag_buf = NULL;
3277 }
3278
3279 /*
3280  * allocate DMA descriptor lists.
3281  */
3282 static int alloc_desc(struct slgt_info *info)
3283 {
3284         unsigned int i;
3285         unsigned int pbufs;
3286
3287         /* allocate memory to hold descriptor lists */
3288         info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3289                                         &info->bufs_dma_addr, GFP_KERNEL);
3290         if (info->bufs == NULL)
3291                 return -ENOMEM;
3292
3293         info->rbufs = (struct slgt_desc*)info->bufs;
3294         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3295
3296         pbufs = (unsigned int)info->bufs_dma_addr;
3297
3298         /*
3299          * Build circular lists of descriptors
3300          */
3301
3302         for (i=0; i < info->rbuf_count; i++) {
3303                 /* physical address of this descriptor */
3304                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3305
3306                 /* physical address of next descriptor */
3307                 if (i == info->rbuf_count - 1)
3308                         info->rbufs[i].next = cpu_to_le32(pbufs);
3309                 else
3310                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3311                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3312         }
3313
3314         for (i=0; i < info->tbuf_count; i++) {
3315                 /* physical address of this descriptor */
3316                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3317
3318                 /* physical address of next descriptor */
3319                 if (i == info->tbuf_count - 1)
3320                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3321                 else
3322                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3323         }
3324
3325         return 0;
3326 }
3327
3328 static void free_desc(struct slgt_info *info)
3329 {
3330         if (info->bufs != NULL) {
3331                 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3332                                   info->bufs, info->bufs_dma_addr);
3333                 info->bufs  = NULL;
3334                 info->rbufs = NULL;
3335                 info->tbufs = NULL;
3336         }
3337 }
3338
3339 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3340 {
3341         int i;
3342         for (i=0; i < count; i++) {
3343                 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3344                                                  &bufs[i].buf_dma_addr, GFP_KERNEL);
3345                 if (!bufs[i].buf)
3346                         return -ENOMEM;
3347                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3348         }
3349         return 0;
3350 }
3351
3352 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3353 {
3354         int i;
3355         for (i=0; i < count; i++) {
3356                 if (bufs[i].buf == NULL)
3357                         continue;
3358                 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3359                                   bufs[i].buf_dma_addr);
3360                 bufs[i].buf = NULL;
3361         }
3362 }
3363
3364 static int alloc_dma_bufs(struct slgt_info *info)
3365 {
3366         info->rbuf_count = 32;
3367         info->tbuf_count = 32;
3368
3369         if (alloc_desc(info) < 0 ||
3370             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3371             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3372             alloc_tmp_rbuf(info) < 0) {
3373                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3374                 return -ENOMEM;
3375         }
3376         reset_rbufs(info);
3377         return 0;
3378 }
3379
3380 static void free_dma_bufs(struct slgt_info *info)
3381 {
3382         if (info->bufs) {
3383                 free_bufs(info, info->rbufs, info->rbuf_count);
3384                 free_bufs(info, info->tbufs, info->tbuf_count);
3385                 free_desc(info);
3386         }
3387         free_tmp_rbuf(info);
3388 }
3389
3390 static int claim_resources(struct slgt_info *info)
3391 {
3392         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3393                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3394                         info->device_name, info->phys_reg_addr));
3395                 info->init_error = DiagStatus_AddressConflict;
3396                 goto errout;
3397         }
3398         else
3399                 info->reg_addr_requested = true;
3400
3401         info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3402         if (!info->reg_addr) {
3403                 DBGERR(("%s can't map device registers, addr=%08X\n",
3404                         info->device_name, info->phys_reg_addr));
3405                 info->init_error = DiagStatus_CantAssignPciResources;
3406                 goto errout;
3407         }
3408         return 0;
3409
3410 errout:
3411         release_resources(info);
3412         return -ENODEV;
3413 }
3414
3415 static void release_resources(struct slgt_info *info)
3416 {
3417         if (info->irq_requested) {
3418                 free_irq(info->irq_level, info);
3419                 info->irq_requested = false;
3420         }
3421
3422         if (info->reg_addr_requested) {
3423                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3424                 info->reg_addr_requested = false;
3425         }
3426
3427         if (info->reg_addr) {
3428                 iounmap(info->reg_addr);
3429                 info->reg_addr = NULL;
3430         }
3431 }
3432
3433 /* Add the specified device instance data structure to the
3434  * global linked list of devices and increment the device count.
3435  */
3436 static void add_device(struct slgt_info *info)
3437 {
3438         char *devstr;
3439
3440         info->next_device = NULL;
3441         info->line = slgt_device_count;
3442         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3443
3444         if (info->line < MAX_DEVICES) {
3445                 if (maxframe[info->line])
3446                         info->max_frame_size = maxframe[info->line];
3447         }
3448
3449         slgt_device_count++;
3450
3451         if (!slgt_device_list)
3452                 slgt_device_list = info;
3453         else {
3454                 struct slgt_info *current_dev = slgt_device_list;
3455                 while(current_dev->next_device)
3456                         current_dev = current_dev->next_device;
3457                 current_dev->next_device = info;
3458         }
3459
3460         if (info->max_frame_size < 4096)
3461                 info->max_frame_size = 4096;
3462         else if (info->max_frame_size > 65535)
3463                 info->max_frame_size = 65535;
3464
3465         switch(info->pdev->device) {
3466         case SYNCLINK_GT_DEVICE_ID:
3467                 devstr = "GT";
3468                 break;
3469         case SYNCLINK_GT2_DEVICE_ID:
3470                 devstr = "GT2";
3471                 break;
3472         case SYNCLINK_GT4_DEVICE_ID:
3473                 devstr = "GT4";
3474                 break;
3475         case SYNCLINK_AC_DEVICE_ID:
3476                 devstr = "AC";
3477                 info->params.mode = MGSL_MODE_ASYNC;
3478                 break;
3479         default:
3480                 devstr = "(unknown model)";
3481         }
3482         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3483                 devstr, info->device_name, info->phys_reg_addr,
3484                 info->irq_level, info->max_frame_size);
3485
3486 #if SYNCLINK_GENERIC_HDLC
3487         hdlcdev_init(info);
3488 #endif
3489 }
3490
3491 static const struct tty_port_operations slgt_port_ops = {
3492         .carrier_raised = carrier_raised,
3493         .dtr_rts = dtr_rts,
3494 };
3495
3496 /*
3497  *  allocate device instance structure, return NULL on failure
3498  */
3499 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3500 {
3501         struct slgt_info *info;
3502
3503         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3504
3505         if (!info) {
3506                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3507                         driver_name, adapter_num, port_num));
3508         } else {
3509                 tty_port_init(&info->port);
3510                 info->port.ops = &slgt_port_ops;
3511                 info->magic = MGSL_MAGIC;
3512                 INIT_WORK(&info->task, bh_handler);
3513                 info->max_frame_size = 4096;
3514                 info->base_clock = 14745600;
3515                 info->rbuf_fill_level = DMABUFSIZE;
3516                 info->port.close_delay = 5*HZ/10;
3517                 info->port.closing_wait = 30*HZ;
3518                 init_waitqueue_head(&info->status_event_wait_q);
3519                 init_waitqueue_head(&info->event_wait_q);
3520                 spin_lock_init(&info->netlock);
3521                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3522                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3523                 info->adapter_num = adapter_num;
3524                 info->port_num = port_num;
3525
3526                 timer_setup(&info->tx_timer, tx_timeout, 0);
3527                 timer_setup(&info->rx_timer, rx_timeout, 0);
3528
3529                 /* Copy configuration info to device instance data */
3530                 info->pdev = pdev;
3531                 info->irq_level = pdev->irq;
3532                 info->phys_reg_addr = pci_resource_start(pdev,0);
3533
3534                 info->bus_type = MGSL_BUS_TYPE_PCI;
3535                 info->irq_flags = IRQF_SHARED;
3536
3537                 info->init_error = -1; /* assume error, set to 0 on successful init */
3538         }
3539
3540         return info;
3541 }
3542
3543 static void device_init(int adapter_num, struct pci_dev *pdev)
3544 {
3545         struct slgt_info *port_array[SLGT_MAX_PORTS];
3546         int i;
3547         int port_count = 1;
3548
3549         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3550                 port_count = 2;
3551         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3552                 port_count = 4;
3553
3554         /* allocate device instances for all ports */
3555         for (i=0; i < port_count; ++i) {
3556                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3557                 if (port_array[i] == NULL) {
3558                         for (--i; i >= 0; --i) {
3559                                 tty_port_destroy(&port_array[i]->port);
3560                                 kfree(port_array[i]);
3561                         }
3562                         return;
3563                 }
3564         }
3565
3566         /* give copy of port_array to all ports and add to device list  */
3567         for (i=0; i < port_count; ++i) {
3568                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3569                 add_device(port_array[i]);
3570                 port_array[i]->port_count = port_count;
3571                 spin_lock_init(&port_array[i]->lock);
3572         }
3573
3574         /* Allocate and claim adapter resources */
3575         if (!claim_resources(port_array[0])) {
3576
3577                 alloc_dma_bufs(port_array[0]);
3578
3579                 /* copy resource information from first port to others */
3580                 for (i = 1; i < port_count; ++i) {
3581                         port_array[i]->irq_level = port_array[0]->irq_level;
3582                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3583                         alloc_dma_bufs(port_array[i]);
3584                 }
3585
3586                 if (request_irq(port_array[0]->irq_level,
3587                                         slgt_interrupt,
3588                                         port_array[0]->irq_flags,
3589                                         port_array[0]->device_name,
3590                                         port_array[0]) < 0) {
3591                         DBGERR(("%s request_irq failed IRQ=%d\n",
3592                                 port_array[0]->device_name,
3593                                 port_array[0]->irq_level));
3594                 } else {
3595                         port_array[0]->irq_requested = true;
3596                         adapter_test(port_array[0]);
3597                         for (i=1 ; i < port_count ; i++) {
3598                                 port_array[i]->init_error = port_array[0]->init_error;
3599                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3600                         }
3601                 }
3602         }
3603
3604         for (i = 0; i < port_count; ++i) {
3605                 struct slgt_info *info = port_array[i];
3606                 tty_port_register_device(&info->port, serial_driver, info->line,
3607                                 &info->pdev->dev);
3608         }
3609 }
3610
3611 static int init_one(struct pci_dev *dev,
3612                               const struct pci_device_id *ent)
3613 {
3614         if (pci_enable_device(dev)) {
3615                 printk("error enabling pci device %p\n", dev);
3616                 return -EIO;
3617         }
3618         pci_set_master(dev);
3619         device_init(slgt_device_count, dev);
3620         return 0;
3621 }
3622
3623 static void remove_one(struct pci_dev *dev)
3624 {
3625 }
3626
3627 static const struct tty_operations ops = {
3628         .open = open,
3629         .close = close,
3630         .write = write,
3631         .put_char = put_char,
3632         .flush_chars = flush_chars,
3633         .write_room = write_room,
3634         .chars_in_buffer = chars_in_buffer,
3635         .flush_buffer = flush_buffer,
3636         .ioctl = ioctl,
3637         .compat_ioctl = slgt_compat_ioctl,
3638         .throttle = throttle,
3639         .unthrottle = unthrottle,
3640         .send_xchar = send_xchar,
3641         .break_ctl = set_break,
3642         .wait_until_sent = wait_until_sent,
3643         .set_termios = set_termios,
3644         .stop = tx_hold,
3645         .start = tx_release,
3646         .hangup = hangup,
3647         .tiocmget = tiocmget,
3648         .tiocmset = tiocmset,
3649         .get_icount = get_icount,
3650         .proc_show = synclink_gt_proc_show,
3651 };
3652
3653 static void slgt_cleanup(void)
3654 {
3655         int rc;
3656         struct slgt_info *info;
3657         struct slgt_info *tmp;
3658
3659         printk(KERN_INFO "unload %s\n", driver_name);
3660
3661         if (serial_driver) {
3662                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3663                         tty_unregister_device(serial_driver, info->line);
3664                 rc = tty_unregister_driver(serial_driver);
3665                 if (rc)
3666                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3667                 put_tty_driver(serial_driver);
3668         }
3669
3670         /* reset devices */
3671         info = slgt_device_list;
3672         while(info) {
3673                 reset_port(info);
3674                 info = info->next_device;
3675         }
3676
3677         /* release devices */
3678         info = slgt_device_list;
3679         while(info) {
3680 #if SYNCLINK_GENERIC_HDLC
3681                 hdlcdev_exit(info);
3682 #endif
3683                 free_dma_bufs(info);
3684                 free_tmp_rbuf(info);
3685                 if (info->port_num == 0)
3686                         release_resources(info);
3687                 tmp = info;
3688                 info = info->next_device;
3689                 tty_port_destroy(&tmp->port);
3690                 kfree(tmp);
3691         }
3692
3693         if (pci_registered)
3694                 pci_unregister_driver(&pci_driver);
3695 }
3696
3697 /*
3698  *  Driver initialization entry point.
3699  */
3700 static int __init slgt_init(void)
3701 {
3702         int rc;
3703
3704         printk(KERN_INFO "%s\n", driver_name);
3705
3706         serial_driver = alloc_tty_driver(MAX_DEVICES);
3707         if (!serial_driver) {
3708                 printk("%s can't allocate tty driver\n", driver_name);
3709                 return -ENOMEM;
3710         }
3711
3712         /* Initialize the tty_driver structure */
3713
3714         serial_driver->driver_name = slgt_driver_name;
3715         serial_driver->name = tty_dev_prefix;
3716         serial_driver->major = ttymajor;
3717         serial_driver->minor_start = 64;
3718         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3719         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3720         serial_driver->init_termios = tty_std_termios;
3721         serial_driver->init_termios.c_cflag =
3722                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3723         serial_driver->init_termios.c_ispeed = 9600;
3724         serial_driver->init_termios.c_ospeed = 9600;
3725         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3726         tty_set_operations(serial_driver, &ops);
3727         if ((rc = tty_register_driver(serial_driver)) < 0) {
3728                 DBGERR(("%s can't register serial driver\n", driver_name));
3729                 put_tty_driver(serial_driver);
3730                 serial_driver = NULL;
3731                 goto error;
3732         }
3733
3734         printk(KERN_INFO "%s, tty major#%d\n",
3735                driver_name, serial_driver->major);
3736
3737         slgt_device_count = 0;
3738         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3739                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3740                 goto error;
3741         }
3742         pci_registered = true;
3743
3744         if (!slgt_device_list)
3745                 printk("%s no devices found\n",driver_name);
3746
3747         return 0;
3748
3749 error:
3750         slgt_cleanup();
3751         return rc;
3752 }
3753
3754 static void __exit slgt_exit(void)
3755 {
3756         slgt_cleanup();
3757 }
3758
3759 module_init(slgt_init);
3760 module_exit(slgt_exit);
3761
3762 /*
3763  * register access routines
3764  */
3765
3766 #define CALC_REGADDR() \
3767         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3768         if (addr >= 0x80) \
3769                 reg_addr += (info->port_num) * 32; \
3770         else if (addr >= 0x40)  \
3771                 reg_addr += (info->port_num) * 16;
3772
3773 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3774 {
3775         CALC_REGADDR();
3776         return readb((void __iomem *)reg_addr);
3777 }
3778
3779 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3780 {
3781         CALC_REGADDR();
3782         writeb(value, (void __iomem *)reg_addr);
3783 }
3784
3785 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3786 {
3787         CALC_REGADDR();
3788         return readw((void __iomem *)reg_addr);
3789 }
3790
3791 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3792 {
3793         CALC_REGADDR();
3794         writew(value, (void __iomem *)reg_addr);
3795 }
3796
3797 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3798 {
3799         CALC_REGADDR();
3800         return readl((void __iomem *)reg_addr);
3801 }
3802
3803 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3804 {
3805         CALC_REGADDR();
3806         writel(value, (void __iomem *)reg_addr);
3807 }
3808
3809 static void rdma_reset(struct slgt_info *info)
3810 {
3811         unsigned int i;
3812
3813         /* set reset bit */
3814         wr_reg32(info, RDCSR, BIT1);
3815
3816         /* wait for enable bit cleared */
3817         for(i=0 ; i < 1000 ; i++)
3818                 if (!(rd_reg32(info, RDCSR) & BIT0))
3819                         break;
3820 }
3821
3822 static void tdma_reset(struct slgt_info *info)
3823 {
3824         unsigned int i;
3825
3826         /* set reset bit */
3827         wr_reg32(info, TDCSR, BIT1);
3828
3829         /* wait for enable bit cleared */
3830         for(i=0 ; i < 1000 ; i++)
3831                 if (!(rd_reg32(info, TDCSR) & BIT0))
3832                         break;
3833 }
3834
3835 /*
3836  * enable internal loopback
3837  * TxCLK and RxCLK are generated from BRG
3838  * and TxD is looped back to RxD internally.
3839  */
3840 static void enable_loopback(struct slgt_info *info)
3841 {
3842         /* SCR (serial control) BIT2=loopback enable */
3843         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3844
3845         if (info->params.mode != MGSL_MODE_ASYNC) {
3846                 /* CCR (clock control)
3847                  * 07..05  tx clock source (010 = BRG)
3848                  * 04..02  rx clock source (010 = BRG)
3849                  * 01      auxclk enable   (0 = disable)
3850                  * 00      BRG enable      (1 = enable)
3851                  *
3852                  * 0100 1001
3853                  */
3854                 wr_reg8(info, CCR, 0x49);
3855
3856                 /* set speed if available, otherwise use default */
3857                 if (info->params.clock_speed)
3858                         set_rate(info, info->params.clock_speed);
3859                 else
3860                         set_rate(info, 3686400);
3861         }
3862 }
3863
3864 /*
3865  *  set baud rate generator to specified rate
3866  */
3867 static void set_rate(struct slgt_info *info, u32 rate)
3868 {
3869         unsigned int div;
3870         unsigned int osc = info->base_clock;
3871
3872         /* div = osc/rate - 1
3873          *
3874          * Round div up if osc/rate is not integer to
3875          * force to next slowest rate.
3876          */
3877
3878         if (rate) {
3879                 div = osc/rate;
3880                 if (!(osc % rate) && div)
3881                         div--;
3882                 wr_reg16(info, BDR, (unsigned short)div);
3883         }
3884 }
3885
3886 static void rx_stop(struct slgt_info *info)
3887 {
3888         unsigned short val;
3889
3890         /* disable and reset receiver */
3891         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3892         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3893         wr_reg16(info, RCR, val);                  /* clear reset bit */
3894
3895         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3896
3897         /* clear pending rx interrupts */
3898         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3899
3900         rdma_reset(info);
3901
3902         info->rx_enabled = false;
3903         info->rx_restart = false;
3904 }
3905
3906 static void rx_start(struct slgt_info *info)
3907 {
3908         unsigned short val;
3909
3910         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3911
3912         /* clear pending rx overrun IRQ */
3913         wr_reg16(info, SSR, IRQ_RXOVER);
3914
3915         /* reset and disable receiver */
3916         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3917         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3918         wr_reg16(info, RCR, val);                  /* clear reset bit */
3919
3920         rdma_reset(info);
3921         reset_rbufs(info);
3922
3923         if (info->rx_pio) {
3924                 /* rx request when rx FIFO not empty */
3925                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3926                 slgt_irq_on(info, IRQ_RXDATA);
3927                 if (info->params.mode == MGSL_MODE_ASYNC) {
3928                         /* enable saving of rx status */
3929                         wr_reg32(info, RDCSR, BIT6);
3930                 }
3931         } else {
3932                 /* rx request when rx FIFO half full */
3933                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3934                 /* set 1st descriptor address */
3935                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3936
3937                 if (info->params.mode != MGSL_MODE_ASYNC) {
3938                         /* enable rx DMA and DMA interrupt */
3939                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
3940                 } else {
3941                         /* enable saving of rx status, rx DMA and DMA interrupt */
3942                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3943                 }
3944         }
3945
3946         slgt_irq_on(info, IRQ_RXOVER);
3947
3948         /* enable receiver */
3949         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3950
3951         info->rx_restart = false;
3952         info->rx_enabled = true;
3953 }
3954
3955 static void tx_start(struct slgt_info *info)
3956 {
3957         if (!info->tx_enabled) {
3958                 wr_reg16(info, TCR,
3959                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3960                 info->tx_enabled = true;
3961         }
3962
3963         if (desc_count(info->tbufs[info->tbuf_start])) {
3964                 info->drop_rts_on_tx_done = false;
3965
3966                 if (info->params.mode != MGSL_MODE_ASYNC) {
3967                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3968                                 get_gtsignals(info);
3969                                 if (!(info->signals & SerialSignal_RTS)) {
3970                                         info->signals |= SerialSignal_RTS;
3971                                         set_gtsignals(info);
3972                                         info->drop_rts_on_tx_done = true;
3973                                 }
3974                         }
3975
3976                         slgt_irq_off(info, IRQ_TXDATA);
3977                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3978                         /* clear tx idle and underrun status bits */
3979                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3980                 } else {
3981                         slgt_irq_off(info, IRQ_TXDATA);
3982                         slgt_irq_on(info, IRQ_TXIDLE);
3983                         /* clear tx idle status bit */
3984                         wr_reg16(info, SSR, IRQ_TXIDLE);
3985                 }
3986                 /* set 1st descriptor address and start DMA */
3987                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3988                 wr_reg32(info, TDCSR, BIT2 + BIT0);
3989                 info->tx_active = true;
3990         }
3991 }
3992
3993 static void tx_stop(struct slgt_info *info)
3994 {
3995         unsigned short val;
3996
3997         del_timer(&info->tx_timer);
3998
3999         tdma_reset(info);
4000
4001         /* reset and disable transmitter */
4002         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4003         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4004
4005         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4006
4007         /* clear tx idle and underrun status bit */
4008         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4009
4010         reset_tbufs(info);
4011
4012         info->tx_enabled = false;
4013         info->tx_active = false;
4014 }
4015
4016 static void reset_port(struct slgt_info *info)
4017 {
4018         if (!info->reg_addr)
4019                 return;
4020
4021         tx_stop(info);
4022         rx_stop(info);
4023
4024         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4025         set_gtsignals(info);
4026
4027         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4028 }
4029
4030 static void reset_adapter(struct slgt_info *info)
4031 {
4032         int i;
4033         for (i=0; i < info->port_count; ++i) {
4034                 if (info->port_array[i])
4035                         reset_port(info->port_array[i]);
4036         }
4037 }
4038
4039 static void async_mode(struct slgt_info *info)
4040 {
4041         unsigned short val;
4042
4043         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4044         tx_stop(info);
4045         rx_stop(info);
4046
4047         /* TCR (tx control)
4048          *
4049          * 15..13  mode, 010=async
4050          * 12..10  encoding, 000=NRZ
4051          * 09      parity enable
4052          * 08      1=odd parity, 0=even parity
4053          * 07      1=RTS driver control
4054          * 06      1=break enable
4055          * 05..04  character length
4056          *         00=5 bits
4057          *         01=6 bits
4058          *         10=7 bits
4059          *         11=8 bits
4060          * 03      0=1 stop bit, 1=2 stop bits
4061          * 02      reset
4062          * 01      enable
4063          * 00      auto-CTS enable
4064          */
4065         val = 0x4000;
4066
4067         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4068                 val |= BIT7;
4069
4070         if (info->params.parity != ASYNC_PARITY_NONE) {
4071                 val |= BIT9;
4072                 if (info->params.parity == ASYNC_PARITY_ODD)
4073                         val |= BIT8;
4074         }
4075
4076         switch (info->params.data_bits)
4077         {
4078         case 6: val |= BIT4; break;
4079         case 7: val |= BIT5; break;
4080         case 8: val |= BIT5 + BIT4; break;
4081         }
4082
4083         if (info->params.stop_bits != 1)
4084                 val |= BIT3;
4085
4086         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4087                 val |= BIT0;
4088
4089         wr_reg16(info, TCR, val);
4090
4091         /* RCR (rx control)
4092          *
4093          * 15..13  mode, 010=async
4094          * 12..10  encoding, 000=NRZ
4095          * 09      parity enable
4096          * 08      1=odd parity, 0=even parity
4097          * 07..06  reserved, must be 0
4098          * 05..04  character length
4099          *         00=5 bits
4100          *         01=6 bits
4101          *         10=7 bits
4102          *         11=8 bits
4103          * 03      reserved, must be zero
4104          * 02      reset
4105          * 01      enable
4106          * 00      auto-DCD enable
4107          */
4108         val = 0x4000;
4109
4110         if (info->params.parity != ASYNC_PARITY_NONE) {
4111                 val |= BIT9;
4112                 if (info->params.parity == ASYNC_PARITY_ODD)
4113                         val |= BIT8;
4114         }
4115
4116         switch (info->params.data_bits)
4117         {
4118         case 6: val |= BIT4; break;
4119         case 7: val |= BIT5; break;
4120         case 8: val |= BIT5 + BIT4; break;
4121         }
4122
4123         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4124                 val |= BIT0;
4125
4126         wr_reg16(info, RCR, val);
4127
4128         /* CCR (clock control)
4129          *
4130          * 07..05  011 = tx clock source is BRG/16
4131          * 04..02  010 = rx clock source is BRG
4132          * 01      0 = auxclk disabled
4133          * 00      1 = BRG enabled
4134          *
4135          * 0110 1001
4136          */
4137         wr_reg8(info, CCR, 0x69);
4138
4139         msc_set_vcr(info);
4140
4141         /* SCR (serial control)
4142          *
4143          * 15  1=tx req on FIFO half empty
4144          * 14  1=rx req on FIFO half full
4145          * 13  tx data  IRQ enable
4146          * 12  tx idle  IRQ enable
4147          * 11  rx break on IRQ enable
4148          * 10  rx data  IRQ enable
4149          * 09  rx break off IRQ enable
4150          * 08  overrun  IRQ enable
4151          * 07  DSR      IRQ enable
4152          * 06  CTS      IRQ enable
4153          * 05  DCD      IRQ enable
4154          * 04  RI       IRQ enable
4155          * 03  0=16x sampling, 1=8x sampling
4156          * 02  1=txd->rxd internal loopback enable
4157          * 01  reserved, must be zero
4158          * 00  1=master IRQ enable
4159          */
4160         val = BIT15 + BIT14 + BIT0;
4161         /* JCR[8] : 1 = x8 async mode feature available */
4162         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4163             ((info->base_clock < (info->params.data_rate * 16)) ||
4164              (info->base_clock % (info->params.data_rate * 16)))) {
4165                 /* use 8x sampling */
4166                 val |= BIT3;
4167                 set_rate(info, info->params.data_rate * 8);
4168         } else {
4169                 /* use 16x sampling */
4170                 set_rate(info, info->params.data_rate * 16);
4171         }
4172         wr_reg16(info, SCR, val);
4173
4174         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4175
4176         if (info->params.loopback)
4177                 enable_loopback(info);
4178 }
4179
4180 static void sync_mode(struct slgt_info *info)
4181 {
4182         unsigned short val;
4183
4184         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4185         tx_stop(info);
4186         rx_stop(info);
4187
4188         /* TCR (tx control)
4189          *
4190          * 15..13  mode
4191          *         000=HDLC/SDLC
4192          *         001=raw bit synchronous
4193          *         010=asynchronous/isochronous
4194          *         011=monosync byte synchronous
4195          *         100=bisync byte synchronous
4196          *         101=xsync byte synchronous
4197          * 12..10  encoding
4198          * 09      CRC enable
4199          * 08      CRC32
4200          * 07      1=RTS driver control
4201          * 06      preamble enable
4202          * 05..04  preamble length
4203          * 03      share open/close flag
4204          * 02      reset
4205          * 01      enable
4206          * 00      auto-CTS enable
4207          */
4208         val = BIT2;
4209
4210         switch(info->params.mode) {
4211         case MGSL_MODE_XSYNC:
4212                 val |= BIT15 + BIT13;
4213                 break;
4214         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4215         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4216         case MGSL_MODE_RAW:      val |= BIT13; break;
4217         }
4218         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4219                 val |= BIT7;
4220
4221         switch(info->params.encoding)
4222         {
4223         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4224         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4225         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4226         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4227         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4228         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4229         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4230         }
4231
4232         switch (info->params.crc_type & HDLC_CRC_MASK)
4233         {
4234         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4235         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4236         }
4237
4238         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4239                 val |= BIT6;
4240
4241         switch (info->params.preamble_length)
4242         {
4243         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4244         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4245         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4246         }
4247
4248         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4249                 val |= BIT0;
4250
4251         wr_reg16(info, TCR, val);
4252
4253         /* TPR (transmit preamble) */
4254
4255         switch (info->params.preamble)
4256         {
4257         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4258         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4259         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4260         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4261         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4262         default:                          val = 0x7e; break;
4263         }
4264         wr_reg8(info, TPR, (unsigned char)val);
4265
4266         /* RCR (rx control)
4267          *
4268          * 15..13  mode
4269          *         000=HDLC/SDLC
4270          *         001=raw bit synchronous
4271          *         010=asynchronous/isochronous
4272          *         011=monosync byte synchronous
4273          *         100=bisync byte synchronous
4274          *         101=xsync byte synchronous
4275          * 12..10  encoding
4276          * 09      CRC enable
4277          * 08      CRC32
4278          * 07..03  reserved, must be 0
4279          * 02      reset
4280          * 01      enable
4281          * 00      auto-DCD enable
4282          */
4283         val = 0;
4284
4285         switch(info->params.mode) {
4286         case MGSL_MODE_XSYNC:
4287                 val |= BIT15 + BIT13;
4288                 break;
4289         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4290         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4291         case MGSL_MODE_RAW:      val |= BIT13; break;
4292         }
4293
4294         switch(info->params.encoding)
4295         {
4296         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4297         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4298         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4299         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4300         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4301         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4302         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4303         }
4304
4305         switch (info->params.crc_type & HDLC_CRC_MASK)
4306         {
4307         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4308         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4309         }
4310
4311         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4312                 val |= BIT0;
4313
4314         wr_reg16(info, RCR, val);
4315
4316         /* CCR (clock control)
4317          *
4318          * 07..05  tx clock source
4319          * 04..02  rx clock source
4320          * 01      auxclk enable
4321          * 00      BRG enable
4322          */
4323         val = 0;
4324
4325         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4326         {
4327                 // when RxC source is DPLL, BRG generates 16X DPLL
4328                 // reference clock, so take TxC from BRG/16 to get
4329                 // transmit clock at actual data rate
4330                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4331                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4332                 else
4333                         val |= BIT6;    /* 010, txclk = BRG */
4334         }
4335         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4336                 val |= BIT7;    /* 100, txclk = DPLL Input */
4337         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4338                 val |= BIT5;    /* 001, txclk = RXC Input */
4339
4340         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4341                 val |= BIT3;    /* 010, rxclk = BRG */
4342         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4343                 val |= BIT4;    /* 100, rxclk = DPLL */
4344         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4345                 val |= BIT2;    /* 001, rxclk = TXC Input */
4346
4347         if (info->params.clock_speed)
4348                 val |= BIT1 + BIT0;
4349
4350         wr_reg8(info, CCR, (unsigned char)val);
4351
4352         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4353         {
4354                 // program DPLL mode
4355                 switch(info->params.encoding)
4356                 {
4357                 case HDLC_ENCODING_BIPHASE_MARK:
4358                 case HDLC_ENCODING_BIPHASE_SPACE:
4359                         val = BIT7; break;
4360                 case HDLC_ENCODING_BIPHASE_LEVEL:
4361                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4362                         val = BIT7 + BIT6; break;
4363                 default: val = BIT6;    // NRZ encodings
4364                 }
4365                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4366
4367                 // DPLL requires a 16X reference clock from BRG
4368                 set_rate(info, info->params.clock_speed * 16);
4369         }
4370         else
4371                 set_rate(info, info->params.clock_speed);
4372
4373         tx_set_idle(info);
4374
4375         msc_set_vcr(info);
4376
4377         /* SCR (serial control)
4378          *
4379          * 15  1=tx req on FIFO half empty
4380          * 14  1=rx req on FIFO half full
4381          * 13  tx data  IRQ enable
4382          * 12  tx idle  IRQ enable
4383          * 11  underrun IRQ enable
4384          * 10  rx data  IRQ enable
4385          * 09  rx idle  IRQ enable
4386          * 08  overrun  IRQ enable
4387          * 07  DSR      IRQ enable
4388          * 06  CTS      IRQ enable
4389          * 05  DCD      IRQ enable
4390          * 04  RI       IRQ enable
4391          * 03  reserved, must be zero
4392          * 02  1=txd->rxd internal loopback enable
4393          * 01  reserved, must be zero
4394          * 00  1=master IRQ enable
4395          */
4396         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4397
4398         if (info->params.loopback)
4399                 enable_loopback(info);
4400 }
4401
4402 /*
4403  *  set transmit idle mode
4404  */
4405 static void tx_set_idle(struct slgt_info *info)
4406 {
4407         unsigned char val;
4408         unsigned short tcr;
4409
4410         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4411          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4412          */
4413         tcr = rd_reg16(info, TCR);
4414         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4415                 /* disable preamble, set idle size to 16 bits */
4416                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4417                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4418                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4419         } else if (!(tcr & BIT6)) {
4420                 /* preamble is disabled, set idle size to 8 bits */
4421                 tcr &= ~(BIT5 + BIT4);
4422         }
4423         wr_reg16(info, TCR, tcr);
4424
4425         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4426                 /* LSB of custom tx idle specified in tx idle register */
4427                 val = (unsigned char)(info->idle_mode & 0xff);
4428         } else {
4429                 /* standard 8 bit idle patterns */
4430                 switch(info->idle_mode)
4431                 {
4432                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4433                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4434                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4435                 case HDLC_TXIDLE_ZEROS:
4436                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4437                 default:                         val = 0xff;
4438                 }
4439         }
4440
4441         wr_reg8(info, TIR, val);
4442 }
4443
4444 /*
4445  * get state of V24 status (input) signals
4446  */
4447 static void get_gtsignals(struct slgt_info *info)
4448 {
4449         unsigned short status = rd_reg16(info, SSR);
4450
4451         /* clear all serial signals except RTS and DTR */
4452         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4453
4454         if (status & BIT3)
4455                 info->signals |= SerialSignal_DSR;
4456         if (status & BIT2)
4457                 info->signals |= SerialSignal_CTS;
4458         if (status & BIT1)
4459                 info->signals |= SerialSignal_DCD;
4460         if (status & BIT0)
4461                 info->signals |= SerialSignal_RI;
4462 }
4463
4464 /*
4465  * set V.24 Control Register based on current configuration
4466  */
4467 static void msc_set_vcr(struct slgt_info *info)
4468 {
4469         unsigned char val = 0;
4470
4471         /* VCR (V.24 control)
4472          *
4473          * 07..04  serial IF select
4474          * 03      DTR
4475          * 02      RTS
4476          * 01      LL
4477          * 00      RL
4478          */
4479
4480         switch(info->if_mode & MGSL_INTERFACE_MASK)
4481         {
4482         case MGSL_INTERFACE_RS232:
4483                 val |= BIT5; /* 0010 */
4484                 break;
4485         case MGSL_INTERFACE_V35:
4486                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4487                 break;
4488         case MGSL_INTERFACE_RS422:
4489                 val |= BIT6; /* 0100 */
4490                 break;
4491         }
4492
4493         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4494                 val |= BIT4;
4495         if (info->signals & SerialSignal_DTR)
4496                 val |= BIT3;
4497         if (info->signals & SerialSignal_RTS)
4498                 val |= BIT2;
4499         if (info->if_mode & MGSL_INTERFACE_LL)
4500                 val |= BIT1;
4501         if (info->if_mode & MGSL_INTERFACE_RL)
4502                 val |= BIT0;
4503         wr_reg8(info, VCR, val);
4504 }
4505
4506 /*
4507  * set state of V24 control (output) signals
4508  */
4509 static void set_gtsignals(struct slgt_info *info)
4510 {
4511         unsigned char val = rd_reg8(info, VCR);
4512         if (info->signals & SerialSignal_DTR)
4513                 val |= BIT3;
4514         else
4515                 val &= ~BIT3;
4516         if (info->signals & SerialSignal_RTS)
4517                 val |= BIT2;
4518         else
4519                 val &= ~BIT2;
4520         wr_reg8(info, VCR, val);
4521 }
4522
4523 /*
4524  * free range of receive DMA buffers (i to last)
4525  */
4526 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4527 {
4528         int done = 0;
4529
4530         while(!done) {
4531                 /* reset current buffer for reuse */
4532                 info->rbufs[i].status = 0;
4533                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4534                 if (i == last)
4535                         done = 1;
4536                 if (++i == info->rbuf_count)
4537                         i = 0;
4538         }
4539         info->rbuf_current = i;
4540 }
4541
4542 /*
4543  * mark all receive DMA buffers as free
4544  */
4545 static void reset_rbufs(struct slgt_info *info)
4546 {
4547         free_rbufs(info, 0, info->rbuf_count - 1);
4548         info->rbuf_fill_index = 0;
4549         info->rbuf_fill_count = 0;
4550 }
4551
4552 /*
4553  * pass receive HDLC frame to upper layer
4554  *
4555  * return true if frame available, otherwise false
4556  */
4557 static bool rx_get_frame(struct slgt_info *info)
4558 {
4559         unsigned int start, end;
4560         unsigned short status;
4561         unsigned int framesize = 0;
4562         unsigned long flags;
4563         struct tty_struct *tty = info->port.tty;
4564         unsigned char addr_field = 0xff;
4565         unsigned int crc_size = 0;
4566
4567         switch (info->params.crc_type & HDLC_CRC_MASK) {
4568         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4569         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4570         }
4571
4572 check_again:
4573
4574         framesize = 0;
4575         addr_field = 0xff;
4576         start = end = info->rbuf_current;
4577
4578         for (;;) {
4579                 if (!desc_complete(info->rbufs[end]))
4580                         goto cleanup;
4581
4582                 if (framesize == 0 && info->params.addr_filter != 0xff)
4583                         addr_field = info->rbufs[end].buf[0];
4584
4585                 framesize += desc_count(info->rbufs[end]);
4586
4587                 if (desc_eof(info->rbufs[end]))
4588                         break;
4589
4590                 if (++end == info->rbuf_count)
4591                         end = 0;
4592
4593                 if (end == info->rbuf_current) {
4594                         if (info->rx_enabled){
4595                                 spin_lock_irqsave(&info->lock,flags);
4596                                 rx_start(info);
4597                                 spin_unlock_irqrestore(&info->lock,flags);
4598                         }
4599                         goto cleanup;
4600                 }
4601         }
4602
4603         /* status
4604          *
4605          * 15      buffer complete
4606          * 14..06  reserved
4607          * 05..04  residue
4608          * 02      eof (end of frame)
4609          * 01      CRC error
4610          * 00      abort
4611          */
4612         status = desc_status(info->rbufs[end]);
4613
4614         /* ignore CRC bit if not using CRC (bit is undefined) */
4615         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4616                 status &= ~BIT1;
4617
4618         if (framesize == 0 ||
4619                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4620                 free_rbufs(info, start, end);
4621                 goto check_again;
4622         }
4623
4624         if (framesize < (2 + crc_size) || status & BIT0) {
4625                 info->icount.rxshort++;
4626                 framesize = 0;
4627         } else if (status & BIT1) {
4628                 info->icount.rxcrc++;
4629                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4630                         framesize = 0;
4631         }
4632
4633 #if SYNCLINK_GENERIC_HDLC
4634         if (framesize == 0) {
4635                 info->netdev->stats.rx_errors++;
4636                 info->netdev->stats.rx_frame_errors++;
4637         }
4638 #endif
4639
4640         DBGBH(("%s rx frame status=%04X size=%d\n",
4641                 info->device_name, status, framesize));
4642         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4643
4644         if (framesize) {
4645                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4646                         framesize -= crc_size;
4647                         crc_size = 0;
4648                 }
4649
4650                 if (framesize > info->max_frame_size + crc_size)
4651                         info->icount.rxlong++;
4652                 else {
4653                         /* copy dma buffer(s) to contiguous temp buffer */
4654                         int copy_count = framesize;
4655                         int i = start;
4656                         unsigned char *p = info->tmp_rbuf;
4657                         info->tmp_rbuf_count = framesize;
4658
4659                         info->icount.rxok++;
4660
4661                         while(copy_count) {
4662                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4663                                 memcpy(p, info->rbufs[i].buf, partial_count);
4664                                 p += partial_count;
4665                                 copy_count -= partial_count;
4666                                 if (++i == info->rbuf_count)
4667                                         i = 0;
4668                         }
4669
4670                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4671                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4672                                 framesize++;
4673                         }
4674
4675 #if SYNCLINK_GENERIC_HDLC
4676                         if (info->netcount)
4677                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4678                         else
4679 #endif
4680                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4681                 }
4682         }
4683         free_rbufs(info, start, end);
4684         return true;
4685
4686 cleanup:
4687         return false;
4688 }
4689
4690 /*
4691  * pass receive buffer (RAW synchronous mode) to tty layer
4692  * return true if buffer available, otherwise false
4693  */
4694 static bool rx_get_buf(struct slgt_info *info)
4695 {
4696         unsigned int i = info->rbuf_current;
4697         unsigned int count;
4698
4699         if (!desc_complete(info->rbufs[i]))
4700                 return false;
4701         count = desc_count(info->rbufs[i]);
4702         switch(info->params.mode) {
4703         case MGSL_MODE_MONOSYNC:
4704         case MGSL_MODE_BISYNC:
4705         case MGSL_MODE_XSYNC:
4706                 /* ignore residue in byte synchronous modes */
4707                 if (desc_residue(info->rbufs[i]))
4708                         count--;
4709                 break;
4710         }
4711         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4712         DBGINFO(("rx_get_buf size=%d\n", count));
4713         if (count)
4714                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4715                                   info->flag_buf, count);
4716         free_rbufs(info, i, i);
4717         return true;
4718 }
4719
4720 static void reset_tbufs(struct slgt_info *info)
4721 {
4722         unsigned int i;
4723         info->tbuf_current = 0;
4724         for (i=0 ; i < info->tbuf_count ; i++) {
4725                 info->tbufs[i].status = 0;
4726                 info->tbufs[i].count  = 0;
4727         }
4728 }
4729
4730 /*
4731  * return number of free transmit DMA buffers
4732  */
4733 static unsigned int free_tbuf_count(struct slgt_info *info)
4734 {
4735         unsigned int count = 0;
4736         unsigned int i = info->tbuf_current;
4737
4738         do
4739         {
4740                 if (desc_count(info->tbufs[i]))
4741                         break; /* buffer in use */
4742                 ++count;
4743                 if (++i == info->tbuf_count)
4744                         i=0;
4745         } while (i != info->tbuf_current);
4746
4747         /* if tx DMA active, last zero count buffer is in use */
4748         if (count && (rd_reg32(info, TDCSR) & BIT0))
4749                 --count;
4750
4751         return count;
4752 }
4753
4754 /*
4755  * return number of bytes in unsent transmit DMA buffers
4756  * and the serial controller tx FIFO
4757  */
4758 static unsigned int tbuf_bytes(struct slgt_info *info)
4759 {
4760         unsigned int total_count = 0;
4761         unsigned int i = info->tbuf_current;
4762         unsigned int reg_value;
4763         unsigned int count;
4764         unsigned int active_buf_count = 0;
4765
4766         /*
4767          * Add descriptor counts for all tx DMA buffers.
4768          * If count is zero (cleared by DMA controller after read),
4769          * the buffer is complete or is actively being read from.
4770          *
4771          * Record buf_count of last buffer with zero count starting
4772          * from current ring position. buf_count is mirror
4773          * copy of count and is not cleared by serial controller.
4774          * If DMA controller is active, that buffer is actively
4775          * being read so add to total.
4776          */
4777         do {
4778                 count = desc_count(info->tbufs[i]);
4779                 if (count)
4780                         total_count += count;
4781                 else if (!total_count)
4782                         active_buf_count = info->tbufs[i].buf_count;
4783                 if (++i == info->tbuf_count)
4784                         i = 0;
4785         } while (i != info->tbuf_current);
4786
4787         /* read tx DMA status register */
4788         reg_value = rd_reg32(info, TDCSR);
4789
4790         /* if tx DMA active, last zero count buffer is in use */
4791         if (reg_value & BIT0)
4792                 total_count += active_buf_count;
4793
4794         /* add tx FIFO count = reg_value[15..8] */
4795         total_count += (reg_value >> 8) & 0xff;
4796
4797         /* if transmitter active add one byte for shift register */
4798         if (info->tx_active)
4799                 total_count++;
4800
4801         return total_count;
4802 }
4803
4804 /*
4805  * load data into transmit DMA buffer ring and start transmitter if needed
4806  * return true if data accepted, otherwise false (buffers full)
4807  */
4808 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4809 {
4810         unsigned short count;
4811         unsigned int i;
4812         struct slgt_desc *d;
4813
4814         /* check required buffer space */
4815         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4816                 return false;
4817
4818         DBGDATA(info, buf, size, "tx");
4819
4820         /*
4821          * copy data to one or more DMA buffers in circular ring
4822          * tbuf_start   = first buffer for this data
4823          * tbuf_current = next free buffer
4824          *
4825          * Copy all data before making data visible to DMA controller by
4826          * setting descriptor count of the first buffer.
4827          * This prevents an active DMA controller from reading the first DMA
4828          * buffers of a frame and stopping before the final buffers are filled.
4829          */
4830
4831         info->tbuf_start = i = info->tbuf_current;
4832
4833         while (size) {
4834                 d = &info->tbufs[i];
4835
4836                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4837                 memcpy(d->buf, buf, count);
4838
4839                 size -= count;
4840                 buf  += count;
4841
4842                 /*
4843                  * set EOF bit for last buffer of HDLC frame or
4844                  * for every buffer in raw mode
4845                  */
4846                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4847                     info->params.mode == MGSL_MODE_RAW)
4848                         set_desc_eof(*d, 1);
4849                 else
4850                         set_desc_eof(*d, 0);
4851
4852                 /* set descriptor count for all but first buffer */
4853                 if (i != info->tbuf_start)
4854                         set_desc_count(*d, count);
4855                 d->buf_count = count;
4856
4857                 if (++i == info->tbuf_count)
4858                         i = 0;
4859         }
4860
4861         info->tbuf_current = i;
4862
4863         /* set first buffer count to make new data visible to DMA controller */
4864         d = &info->tbufs[info->tbuf_start];
4865         set_desc_count(*d, d->buf_count);
4866
4867         /* start transmitter if needed and update transmit timeout */
4868         if (!info->tx_active)
4869                 tx_start(info);
4870         update_tx_timer(info);
4871
4872         return true;
4873 }
4874
4875 static int register_test(struct slgt_info *info)
4876 {
4877         static unsigned short patterns[] =
4878                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4879         static unsigned int count = ARRAY_SIZE(patterns);
4880         unsigned int i;
4881         int rc = 0;
4882
4883         for (i=0 ; i < count ; i++) {
4884                 wr_reg16(info, TIR, patterns[i]);
4885                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4886                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4887                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4888                         rc = -ENODEV;
4889                         break;
4890                 }
4891         }
4892         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4893         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4894         return rc;
4895 }
4896
4897 static int irq_test(struct slgt_info *info)
4898 {
4899         unsigned long timeout;
4900         unsigned long flags;
4901         struct tty_struct *oldtty = info->port.tty;
4902         u32 speed = info->params.data_rate;
4903
4904         info->params.data_rate = 921600;
4905         info->port.tty = NULL;
4906
4907         spin_lock_irqsave(&info->lock, flags);
4908         async_mode(info);
4909         slgt_irq_on(info, IRQ_TXIDLE);
4910
4911         /* enable transmitter */
4912         wr_reg16(info, TCR,
4913                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4914
4915         /* write one byte and wait for tx idle */
4916         wr_reg16(info, TDR, 0);
4917
4918         /* assume failure */
4919         info->init_error = DiagStatus_IrqFailure;
4920         info->irq_occurred = false;
4921
4922         spin_unlock_irqrestore(&info->lock, flags);
4923
4924         timeout=100;
4925         while(timeout-- && !info->irq_occurred)
4926                 msleep_interruptible(10);
4927
4928         spin_lock_irqsave(&info->lock,flags);
4929         reset_port(info);
4930         spin_unlock_irqrestore(&info->lock,flags);
4931
4932         info->params.data_rate = speed;
4933         info->port.tty = oldtty;
4934
4935         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4936         return info->irq_occurred ? 0 : -ENODEV;
4937 }
4938
4939 static int loopback_test_rx(struct slgt_info *info)
4940 {
4941         unsigned char *src, *dest;
4942         int count;
4943
4944         if (desc_complete(info->rbufs[0])) {
4945                 count = desc_count(info->rbufs[0]);
4946                 src   = info->rbufs[0].buf;
4947                 dest  = info->tmp_rbuf;
4948
4949                 for( ; count ; count-=2, src+=2) {
4950                         /* src=data byte (src+1)=status byte */
4951                         if (!(*(src+1) & (BIT9 + BIT8))) {
4952                                 *dest = *src;
4953                                 dest++;
4954                                 info->tmp_rbuf_count++;
4955                         }
4956                 }
4957                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4958                 return 1;
4959         }
4960         return 0;
4961 }
4962
4963 static int loopback_test(struct slgt_info *info)
4964 {
4965 #define TESTFRAMESIZE 20
4966
4967         unsigned long timeout;
4968         u16 count = TESTFRAMESIZE;
4969         unsigned char buf[TESTFRAMESIZE];
4970         int rc = -ENODEV;
4971         unsigned long flags;
4972
4973         struct tty_struct *oldtty = info->port.tty;
4974         MGSL_PARAMS params;
4975
4976         memcpy(&params, &info->params, sizeof(params));
4977
4978         info->params.mode = MGSL_MODE_ASYNC;
4979         info->params.data_rate = 921600;
4980         info->params.loopback = 1;
4981         info->port.tty = NULL;
4982
4983         /* build and send transmit frame */
4984         for (count = 0; count < TESTFRAMESIZE; ++count)
4985                 buf[count] = (unsigned char)count;
4986
4987         info->tmp_rbuf_count = 0;
4988         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4989
4990         /* program hardware for HDLC and enabled receiver */
4991         spin_lock_irqsave(&info->lock,flags);
4992         async_mode(info);
4993         rx_start(info);
4994         tx_load(info, buf, count);
4995         spin_unlock_irqrestore(&info->lock, flags);
4996
4997         /* wait for receive complete */
4998         for (timeout = 100; timeout; --timeout) {
4999                 msleep_interruptible(10);
5000                 if (loopback_test_rx(info)) {
5001                         rc = 0;
5002                         break;
5003                 }
5004         }
5005
5006         /* verify received frame length and contents */
5007         if (!rc && (info->tmp_rbuf_count != count ||
5008                   memcmp(buf, info->tmp_rbuf, count))) {
5009                 rc = -ENODEV;
5010         }
5011
5012         spin_lock_irqsave(&info->lock,flags);
5013         reset_adapter(info);
5014         spin_unlock_irqrestore(&info->lock,flags);
5015
5016         memcpy(&info->params, &params, sizeof(info->params));
5017         info->port.tty = oldtty;
5018
5019         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5020         return rc;
5021 }
5022
5023 static int adapter_test(struct slgt_info *info)
5024 {
5025         DBGINFO(("testing %s\n", info->device_name));
5026         if (register_test(info) < 0) {
5027                 printk("register test failure %s addr=%08X\n",
5028                         info->device_name, info->phys_reg_addr);
5029         } else if (irq_test(info) < 0) {
5030                 printk("IRQ test failure %s IRQ=%d\n",
5031                         info->device_name, info->irq_level);
5032         } else if (loopback_test(info) < 0) {
5033                 printk("loopback test failure %s\n", info->device_name);
5034         }
5035         return info->init_error;
5036 }
5037
5038 /*
5039  * transmit timeout handler
5040  */
5041 static void tx_timeout(struct timer_list *t)
5042 {
5043         struct slgt_info *info = from_timer(info, t, tx_timer);
5044         unsigned long flags;
5045
5046         DBGINFO(("%s tx_timeout\n", info->device_name));
5047         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5048                 info->icount.txtimeout++;
5049         }
5050         spin_lock_irqsave(&info->lock,flags);
5051         tx_stop(info);
5052         spin_unlock_irqrestore(&info->lock,flags);
5053
5054 #if SYNCLINK_GENERIC_HDLC
5055         if (info->netcount)
5056                 hdlcdev_tx_done(info);
5057         else
5058 #endif
5059                 bh_transmit(info);
5060 }
5061
5062 /*
5063  * receive buffer polling timer
5064  */
5065 static void rx_timeout(struct timer_list *t)
5066 {
5067         struct slgt_info *info = from_timer(info, t, rx_timer);
5068         unsigned long flags;
5069
5070         DBGINFO(("%s rx_timeout\n", info->device_name));
5071         spin_lock_irqsave(&info->lock, flags);
5072         info->pending_bh |= BH_RECEIVE;
5073         spin_unlock_irqrestore(&info->lock, flags);
5074         bh_handler(&info->task);
5075 }
5076