1 // SPDX-License-Identifier: GPL-1.0+
3 * Device driver for Microgate SyncLink GT serial adapters.
5 * written by Paul Fulghum for Microgate Corporation
8 * Microgate and SyncLink are trademarks of Microgate Corporation
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 * DEBUG OUTPUT DEFINITIONS
26 * uncomment lines below to enable specific types of debug output
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42 /*#define DBGTBUF(info) dump_tbufs(info)*/
43 /*#define DBGRBUF(info) dump_rbufs(info)*/
46 #include <linux/module.h>
47 #include <linux/errno.h>
48 #include <linux/signal.h>
49 #include <linux/sched.h>
50 #include <linux/timer.h>
51 #include <linux/interrupt.h>
52 #include <linux/pci.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55 #include <linux/serial.h>
56 #include <linux/major.h>
57 #include <linux/string.h>
58 #include <linux/fcntl.h>
59 #include <linux/ptrace.h>
60 #include <linux/ioport.h>
62 #include <linux/seq_file.h>
63 #include <linux/slab.h>
64 #include <linux/netdevice.h>
65 #include <linux/vmalloc.h>
66 #include <linux/init.h>
67 #include <linux/delay.h>
68 #include <linux/ioctl.h>
69 #include <linux/termios.h>
70 #include <linux/bitops.h>
71 #include <linux/workqueue.h>
72 #include <linux/hdlc.h>
73 #include <linux/synclink.h>
78 #include <asm/types.h>
79 #include <linux/uaccess.h>
81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82 #define SYNCLINK_GENERIC_HDLC 1
84 #define SYNCLINK_GENERIC_HDLC 0
88 * module identification
90 static char *driver_name = "SyncLink GT";
91 static char *slgt_driver_name = "synclink_gt";
92 static char *tty_dev_prefix = "ttySLG";
93 MODULE_LICENSE("GPL");
94 #define MGSL_MAGIC 0x5401
95 #define MAX_DEVICES 32
97 static const struct pci_device_id pci_table[] = {
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {0,}, /* terminate list */
104 MODULE_DEVICE_TABLE(pci, pci_table);
106 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
107 static void remove_one(struct pci_dev *dev);
108 static struct pci_driver pci_driver = {
109 .name = "synclink_gt",
110 .id_table = pci_table,
112 .remove = remove_one,
115 static bool pci_registered;
118 * module configuration and status
120 static struct slgt_info *slgt_device_list;
121 static int slgt_device_count;
124 static int debug_level;
125 static int maxframe[MAX_DEVICES];
127 module_param(ttymajor, int, 0);
128 module_param(debug_level, int, 0);
129 module_param_array(maxframe, int, NULL, 0);
131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
136 * tty support and callbacks
138 static struct tty_driver *serial_driver;
140 static void wait_until_sent(struct tty_struct *tty, int timeout);
141 static void flush_buffer(struct tty_struct *tty);
142 static void tx_release(struct tty_struct *tty);
145 * generic HDLC support
147 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
151 * device specific structures, macros and functions
154 #define SLGT_MAX_PORTS 4
155 #define SLGT_REG_SIZE 256
158 * conditional wait facility
161 struct cond_wait *next;
163 wait_queue_entry_t wait;
166 static void flush_cond_wait(struct cond_wait **head);
169 * DMA buffer descriptor and access macros
175 __le32 pbuf; /* physical address of data buffer */
176 __le32 next; /* physical address of next descriptor */
178 /* driver book keeping */
179 char *buf; /* virtual address of data buffer */
180 unsigned int pdesc; /* physical address of this descriptor */
181 dma_addr_t buf_dma_addr;
182 unsigned short buf_count;
185 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
186 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
187 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
188 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
189 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
190 #define desc_count(a) (le16_to_cpu((a).count))
191 #define desc_status(a) (le16_to_cpu((a).status))
192 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
193 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
194 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
195 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
196 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
198 struct _input_signal_events {
210 * device instance data structure
213 void *if_ptr; /* General purpose pointer (used by SPPP) */
214 struct tty_port port;
216 struct slgt_info *next_device; /* device list link */
220 char device_name[25];
221 struct pci_dev *pdev;
223 int port_count; /* count of ports on adapter */
224 int adapter_num; /* adapter instance number */
225 int port_num; /* port instance number */
227 /* array of pointers to port contexts on this adapter */
228 struct slgt_info *port_array[SLGT_MAX_PORTS];
230 int line; /* tty line instance number */
232 struct mgsl_icount icount;
235 int x_char; /* xon/xoff character */
236 unsigned int read_status_mask;
237 unsigned int ignore_status_mask;
239 wait_queue_head_t status_event_wait_q;
240 wait_queue_head_t event_wait_q;
241 struct timer_list tx_timer;
242 struct timer_list rx_timer;
244 unsigned int gpio_present;
245 struct cond_wait *gpio_wait_q;
247 spinlock_t lock; /* spinlock for synchronizing with ISR */
249 struct work_struct task;
255 bool irq_requested; /* true if IRQ requested */
256 bool irq_occurred; /* for diagnostics use */
258 /* device configuration */
260 unsigned int bus_type;
261 unsigned int irq_level;
262 unsigned long irq_flags;
264 unsigned char __iomem * reg_addr; /* memory mapped registers address */
266 bool reg_addr_requested;
268 MGSL_PARAMS params; /* communications parameters */
270 u32 max_frame_size; /* as set by device config */
272 unsigned int rbuf_fill_level;
274 unsigned int if_mode;
275 unsigned int base_clock;
287 unsigned char signals; /* serial signal states */
288 int init_error; /* initialization error */
290 unsigned char *tx_buf;
294 bool drop_rts_on_tx_done;
295 struct _input_signal_events input_signal_events;
297 int dcd_chkcount; /* check counts to prevent */
298 int cts_chkcount; /* too many IRQs if a signal */
299 int dsr_chkcount; /* is floating */
302 char *bufs; /* virtual address of DMA buffer lists */
303 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
305 unsigned int rbuf_count;
306 struct slgt_desc *rbufs;
307 unsigned int rbuf_current;
308 unsigned int rbuf_index;
309 unsigned int rbuf_fill_index;
310 unsigned short rbuf_fill_count;
312 unsigned int tbuf_count;
313 struct slgt_desc *tbufs;
314 unsigned int tbuf_current;
315 unsigned int tbuf_start;
317 unsigned char *tmp_rbuf;
318 unsigned int tmp_rbuf_count;
320 /* SPPP/Cisco HDLC device parts */
324 #if SYNCLINK_GENERIC_HDLC
325 struct net_device *netdev;
330 static MGSL_PARAMS default_params = {
331 .mode = MGSL_MODE_HDLC,
333 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
334 .encoding = HDLC_ENCODING_NRZI_SPACE,
337 .crc_type = HDLC_CRC_16_CCITT,
338 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
339 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
343 .parity = ASYNC_PARITY_NONE
348 #define BH_TRANSMIT 2
350 #define IO_PIN_SHUTDOWN_LIMIT 100
352 #define DMABUFSIZE 256
353 #define DESC_LIST_SIZE 4096
355 #define MASK_PARITY BIT1
356 #define MASK_FRAMING BIT0
357 #define MASK_BREAK BIT14
358 #define MASK_OVERRUN BIT4
360 #define GSR 0x00 /* global status */
361 #define JCR 0x04 /* JTAG control */
362 #define IODR 0x08 /* GPIO direction */
363 #define IOER 0x0c /* GPIO interrupt enable */
364 #define IOVR 0x10 /* GPIO value */
365 #define IOSR 0x14 /* GPIO interrupt status */
366 #define TDR 0x80 /* tx data */
367 #define RDR 0x80 /* rx data */
368 #define TCR 0x82 /* tx control */
369 #define TIR 0x84 /* tx idle */
370 #define TPR 0x85 /* tx preamble */
371 #define RCR 0x86 /* rx control */
372 #define VCR 0x88 /* V.24 control */
373 #define CCR 0x89 /* clock control */
374 #define BDR 0x8a /* baud divisor */
375 #define SCR 0x8c /* serial control */
376 #define SSR 0x8e /* serial status */
377 #define RDCSR 0x90 /* rx DMA control/status */
378 #define TDCSR 0x94 /* tx DMA control/status */
379 #define RDDAR 0x98 /* rx DMA descriptor address */
380 #define TDDAR 0x9c /* tx DMA descriptor address */
381 #define XSR 0x40 /* extended sync pattern */
382 #define XCR 0x44 /* extended control */
385 #define RXBREAK BIT14
386 #define IRQ_TXDATA BIT13
387 #define IRQ_TXIDLE BIT12
388 #define IRQ_TXUNDER BIT11 /* HDLC */
389 #define IRQ_RXDATA BIT10
390 #define IRQ_RXIDLE BIT9 /* HDLC */
391 #define IRQ_RXBREAK BIT9 /* async */
392 #define IRQ_RXOVER BIT8
397 #define IRQ_ALL 0x3ff0
398 #define IRQ_MASTER BIT0
400 #define slgt_irq_on(info, mask) \
401 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
402 #define slgt_irq_off(info, mask) \
403 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
405 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
406 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
407 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
408 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
409 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
410 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
412 static void msc_set_vcr(struct slgt_info *info);
414 static int startup(struct slgt_info *info);
415 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
416 static void shutdown(struct slgt_info *info);
417 static void program_hw(struct slgt_info *info);
418 static void change_params(struct slgt_info *info);
420 static int adapter_test(struct slgt_info *info);
422 static void reset_port(struct slgt_info *info);
423 static void async_mode(struct slgt_info *info);
424 static void sync_mode(struct slgt_info *info);
426 static void rx_stop(struct slgt_info *info);
427 static void rx_start(struct slgt_info *info);
428 static void reset_rbufs(struct slgt_info *info);
429 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
430 static bool rx_get_frame(struct slgt_info *info);
431 static bool rx_get_buf(struct slgt_info *info);
433 static void tx_start(struct slgt_info *info);
434 static void tx_stop(struct slgt_info *info);
435 static void tx_set_idle(struct slgt_info *info);
436 static unsigned int tbuf_bytes(struct slgt_info *info);
437 static void reset_tbufs(struct slgt_info *info);
438 static void tdma_reset(struct slgt_info *info);
439 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
441 static void get_gtsignals(struct slgt_info *info);
442 static void set_gtsignals(struct slgt_info *info);
443 static void set_rate(struct slgt_info *info, u32 data_rate);
445 static void bh_transmit(struct slgt_info *info);
446 static void isr_txeom(struct slgt_info *info, unsigned short status);
448 static void tx_timeout(struct timer_list *t);
449 static void rx_timeout(struct timer_list *t);
454 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
455 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
456 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
457 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
458 static int set_txidle(struct slgt_info *info, int idle_mode);
459 static int tx_enable(struct slgt_info *info, int enable);
460 static int tx_abort(struct slgt_info *info);
461 static int rx_enable(struct slgt_info *info, int enable);
462 static int modem_input_wait(struct slgt_info *info,int arg);
463 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
464 static int get_interface(struct slgt_info *info, int __user *if_mode);
465 static int set_interface(struct slgt_info *info, int if_mode);
466 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
467 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
468 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
469 static int get_xsync(struct slgt_info *info, int __user *if_mode);
470 static int set_xsync(struct slgt_info *info, int if_mode);
471 static int get_xctrl(struct slgt_info *info, int __user *if_mode);
472 static int set_xctrl(struct slgt_info *info, int if_mode);
477 static void release_resources(struct slgt_info *info);
496 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
500 printk("%s %s data:\n",info->device_name, label);
502 linecount = (count > 16) ? 16 : count;
503 for(i=0; i < linecount; i++)
504 printk("%02X ",(unsigned char)data[i]);
507 for(i=0;i<linecount;i++) {
508 if (data[i]>=040 && data[i]<=0176)
509 printk("%c",data[i]);
519 #define DBGDATA(info, buf, size, label)
523 static void dump_tbufs(struct slgt_info *info)
526 printk("tbuf_current=%d\n", info->tbuf_current);
527 for (i=0 ; i < info->tbuf_count ; i++) {
528 printk("%d: count=%04X status=%04X\n",
529 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
533 #define DBGTBUF(info)
537 static void dump_rbufs(struct slgt_info *info)
540 printk("rbuf_current=%d\n", info->rbuf_current);
541 for (i=0 ; i < info->rbuf_count ; i++) {
542 printk("%d: count=%04X status=%04X\n",
543 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
547 #define DBGRBUF(info)
550 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
554 printk("null struct slgt_info for (%s) in %s\n", devname, name);
557 if (info->magic != MGSL_MAGIC) {
558 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
569 * line discipline callback wrappers
571 * The wrappers maintain line discipline references
572 * while calling into the line discipline.
574 * ldisc_receive_buf - pass receive data to line discipline
576 static void ldisc_receive_buf(struct tty_struct *tty,
577 const __u8 *data, char *flags, int count)
579 struct tty_ldisc *ld;
582 ld = tty_ldisc_ref(tty);
584 if (ld->ops->receive_buf)
585 ld->ops->receive_buf(tty, data, flags, count);
592 static int open(struct tty_struct *tty, struct file *filp)
594 struct slgt_info *info;
599 if (line >= slgt_device_count) {
600 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
604 info = slgt_device_list;
605 while(info && info->line != line)
606 info = info->next_device;
607 if (sanity_check(info, tty->name, "open"))
609 if (info->init_error) {
610 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
614 tty->driver_data = info;
615 info->port.tty = tty;
617 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
619 mutex_lock(&info->port.mutex);
620 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
622 spin_lock_irqsave(&info->netlock, flags);
623 if (info->netcount) {
625 spin_unlock_irqrestore(&info->netlock, flags);
626 mutex_unlock(&info->port.mutex);
630 spin_unlock_irqrestore(&info->netlock, flags);
632 if (info->port.count == 1) {
633 /* 1st open on this device, init hardware */
634 retval = startup(info);
636 mutex_unlock(&info->port.mutex);
640 mutex_unlock(&info->port.mutex);
641 retval = block_til_ready(tty, filp, info);
643 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
652 info->port.tty = NULL; /* tty layer will release tty struct */
657 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
661 static void close(struct tty_struct *tty, struct file *filp)
663 struct slgt_info *info = tty->driver_data;
665 if (sanity_check(info, tty->name, "close"))
667 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
669 if (tty_port_close_start(&info->port, tty, filp) == 0)
672 mutex_lock(&info->port.mutex);
673 if (tty_port_initialized(&info->port))
674 wait_until_sent(tty, info->timeout);
676 tty_ldisc_flush(tty);
679 mutex_unlock(&info->port.mutex);
681 tty_port_close_end(&info->port, tty);
682 info->port.tty = NULL;
684 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
687 static void hangup(struct tty_struct *tty)
689 struct slgt_info *info = tty->driver_data;
692 if (sanity_check(info, tty->name, "hangup"))
694 DBGINFO(("%s hangup\n", info->device_name));
698 mutex_lock(&info->port.mutex);
701 spin_lock_irqsave(&info->port.lock, flags);
702 info->port.count = 0;
703 info->port.tty = NULL;
704 spin_unlock_irqrestore(&info->port.lock, flags);
705 tty_port_set_active(&info->port, 0);
706 mutex_unlock(&info->port.mutex);
708 wake_up_interruptible(&info->port.open_wait);
711 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
713 struct slgt_info *info = tty->driver_data;
716 DBGINFO(("%s set_termios\n", tty->driver->name));
720 /* Handle transition to B0 status */
721 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
722 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
723 spin_lock_irqsave(&info->lock,flags);
725 spin_unlock_irqrestore(&info->lock,flags);
728 /* Handle transition away from B0 status */
729 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
730 info->signals |= SerialSignal_DTR;
731 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
732 info->signals |= SerialSignal_RTS;
733 spin_lock_irqsave(&info->lock,flags);
735 spin_unlock_irqrestore(&info->lock,flags);
738 /* Handle turning off CRTSCTS */
739 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
745 static void update_tx_timer(struct slgt_info *info)
748 * use worst case speed of 1200bps to calculate transmit timeout
749 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
751 if (info->params.mode == MGSL_MODE_HDLC) {
752 int timeout = (tbuf_bytes(info) * 7) + 1000;
753 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
757 static int write(struct tty_struct *tty,
758 const unsigned char *buf, int count)
761 struct slgt_info *info = tty->driver_data;
764 if (sanity_check(info, tty->name, "write"))
767 DBGINFO(("%s write count=%d\n", info->device_name, count));
769 if (!info->tx_buf || (count > info->max_frame_size))
772 if (!count || tty->stopped || tty->hw_stopped)
775 spin_lock_irqsave(&info->lock, flags);
777 if (info->tx_count) {
778 /* send accumulated data from send_char() */
779 if (!tx_load(info, info->tx_buf, info->tx_count))
784 if (tx_load(info, buf, count))
788 spin_unlock_irqrestore(&info->lock, flags);
789 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
793 static int put_char(struct tty_struct *tty, unsigned char ch)
795 struct slgt_info *info = tty->driver_data;
799 if (sanity_check(info, tty->name, "put_char"))
801 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
804 spin_lock_irqsave(&info->lock,flags);
805 if (info->tx_count < info->max_frame_size) {
806 info->tx_buf[info->tx_count++] = ch;
809 spin_unlock_irqrestore(&info->lock,flags);
813 static void send_xchar(struct tty_struct *tty, char ch)
815 struct slgt_info *info = tty->driver_data;
818 if (sanity_check(info, tty->name, "send_xchar"))
820 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
823 spin_lock_irqsave(&info->lock,flags);
824 if (!info->tx_enabled)
826 spin_unlock_irqrestore(&info->lock,flags);
830 static void wait_until_sent(struct tty_struct *tty, int timeout)
832 struct slgt_info *info = tty->driver_data;
833 unsigned long orig_jiffies, char_time;
837 if (sanity_check(info, tty->name, "wait_until_sent"))
839 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
840 if (!tty_port_initialized(&info->port))
843 orig_jiffies = jiffies;
845 /* Set check interval to 1/5 of estimated time to
846 * send a character, and make it at least 1. The check
847 * interval should also be less than the timeout.
848 * Note: use tight timings here to satisfy the NIST-PCTS.
851 if (info->params.data_rate) {
852 char_time = info->timeout/(32 * 5);
859 char_time = min_t(unsigned long, char_time, timeout);
861 while (info->tx_active) {
862 msleep_interruptible(jiffies_to_msecs(char_time));
863 if (signal_pending(current))
865 if (timeout && time_after(jiffies, orig_jiffies + timeout))
869 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
872 static int write_room(struct tty_struct *tty)
874 struct slgt_info *info = tty->driver_data;
877 if (sanity_check(info, tty->name, "write_room"))
879 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
880 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
884 static void flush_chars(struct tty_struct *tty)
886 struct slgt_info *info = tty->driver_data;
889 if (sanity_check(info, tty->name, "flush_chars"))
891 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
893 if (info->tx_count <= 0 || tty->stopped ||
894 tty->hw_stopped || !info->tx_buf)
897 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
899 spin_lock_irqsave(&info->lock,flags);
900 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
902 spin_unlock_irqrestore(&info->lock,flags);
905 static void flush_buffer(struct tty_struct *tty)
907 struct slgt_info *info = tty->driver_data;
910 if (sanity_check(info, tty->name, "flush_buffer"))
912 DBGINFO(("%s flush_buffer\n", info->device_name));
914 spin_lock_irqsave(&info->lock, flags);
916 spin_unlock_irqrestore(&info->lock, flags);
922 * throttle (stop) transmitter
924 static void tx_hold(struct tty_struct *tty)
926 struct slgt_info *info = tty->driver_data;
929 if (sanity_check(info, tty->name, "tx_hold"))
931 DBGINFO(("%s tx_hold\n", info->device_name));
932 spin_lock_irqsave(&info->lock,flags);
933 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
935 spin_unlock_irqrestore(&info->lock,flags);
939 * release (start) transmitter
941 static void tx_release(struct tty_struct *tty)
943 struct slgt_info *info = tty->driver_data;
946 if (sanity_check(info, tty->name, "tx_release"))
948 DBGINFO(("%s tx_release\n", info->device_name));
949 spin_lock_irqsave(&info->lock, flags);
950 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
952 spin_unlock_irqrestore(&info->lock, flags);
956 * Service an IOCTL request
960 * tty pointer to tty instance data
961 * cmd IOCTL command code
962 * arg command argument/context
964 * Return 0 if success, otherwise error code
966 static int ioctl(struct tty_struct *tty,
967 unsigned int cmd, unsigned long arg)
969 struct slgt_info *info = tty->driver_data;
970 void __user *argp = (void __user *)arg;
973 if (sanity_check(info, tty->name, "ioctl"))
975 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
977 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
978 (cmd != TIOCMIWAIT)) {
979 if (tty_io_error(tty))
984 case MGSL_IOCWAITEVENT:
985 return wait_mgsl_event(info, argp);
987 return modem_input_wait(info,(int)arg);
989 return set_gpio(info, argp);
991 return get_gpio(info, argp);
992 case MGSL_IOCWAITGPIO:
993 return wait_gpio(info, argp);
995 return get_xsync(info, argp);
997 return set_xsync(info, (int)arg);
999 return get_xctrl(info, argp);
1000 case MGSL_IOCSXCTRL:
1001 return set_xctrl(info, (int)arg);
1003 mutex_lock(&info->port.mutex);
1005 case MGSL_IOCGPARAMS:
1006 ret = get_params(info, argp);
1008 case MGSL_IOCSPARAMS:
1009 ret = set_params(info, argp);
1011 case MGSL_IOCGTXIDLE:
1012 ret = get_txidle(info, argp);
1014 case MGSL_IOCSTXIDLE:
1015 ret = set_txidle(info, (int)arg);
1017 case MGSL_IOCTXENABLE:
1018 ret = tx_enable(info, (int)arg);
1020 case MGSL_IOCRXENABLE:
1021 ret = rx_enable(info, (int)arg);
1023 case MGSL_IOCTXABORT:
1024 ret = tx_abort(info);
1026 case MGSL_IOCGSTATS:
1027 ret = get_stats(info, argp);
1030 ret = get_interface(info, argp);
1033 ret = set_interface(info,(int)arg);
1038 mutex_unlock(&info->port.mutex);
1042 static int get_icount(struct tty_struct *tty,
1043 struct serial_icounter_struct *icount)
1046 struct slgt_info *info = tty->driver_data;
1047 struct mgsl_icount cnow; /* kernel counter temps */
1048 unsigned long flags;
1050 spin_lock_irqsave(&info->lock,flags);
1051 cnow = info->icount;
1052 spin_unlock_irqrestore(&info->lock,flags);
1054 icount->cts = cnow.cts;
1055 icount->dsr = cnow.dsr;
1056 icount->rng = cnow.rng;
1057 icount->dcd = cnow.dcd;
1058 icount->rx = cnow.rx;
1059 icount->tx = cnow.tx;
1060 icount->frame = cnow.frame;
1061 icount->overrun = cnow.overrun;
1062 icount->parity = cnow.parity;
1063 icount->brk = cnow.brk;
1064 icount->buf_overrun = cnow.buf_overrun;
1070 * support for 32 bit ioctl calls on 64 bit systems
1072 #ifdef CONFIG_COMPAT
1073 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1075 struct MGSL_PARAMS32 tmp_params;
1077 DBGINFO(("%s get_params32\n", info->device_name));
1078 memset(&tmp_params, 0, sizeof(tmp_params));
1079 tmp_params.mode = (compat_ulong_t)info->params.mode;
1080 tmp_params.loopback = info->params.loopback;
1081 tmp_params.flags = info->params.flags;
1082 tmp_params.encoding = info->params.encoding;
1083 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1084 tmp_params.addr_filter = info->params.addr_filter;
1085 tmp_params.crc_type = info->params.crc_type;
1086 tmp_params.preamble_length = info->params.preamble_length;
1087 tmp_params.preamble = info->params.preamble;
1088 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1089 tmp_params.data_bits = info->params.data_bits;
1090 tmp_params.stop_bits = info->params.stop_bits;
1091 tmp_params.parity = info->params.parity;
1092 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1097 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1099 struct MGSL_PARAMS32 tmp_params;
1101 DBGINFO(("%s set_params32\n", info->device_name));
1102 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1105 spin_lock(&info->lock);
1106 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1107 info->base_clock = tmp_params.clock_speed;
1109 info->params.mode = tmp_params.mode;
1110 info->params.loopback = tmp_params.loopback;
1111 info->params.flags = tmp_params.flags;
1112 info->params.encoding = tmp_params.encoding;
1113 info->params.clock_speed = tmp_params.clock_speed;
1114 info->params.addr_filter = tmp_params.addr_filter;
1115 info->params.crc_type = tmp_params.crc_type;
1116 info->params.preamble_length = tmp_params.preamble_length;
1117 info->params.preamble = tmp_params.preamble;
1118 info->params.data_rate = tmp_params.data_rate;
1119 info->params.data_bits = tmp_params.data_bits;
1120 info->params.stop_bits = tmp_params.stop_bits;
1121 info->params.parity = tmp_params.parity;
1123 spin_unlock(&info->lock);
1130 static long slgt_compat_ioctl(struct tty_struct *tty,
1131 unsigned int cmd, unsigned long arg)
1133 struct slgt_info *info = tty->driver_data;
1136 if (sanity_check(info, tty->name, "compat_ioctl"))
1138 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1141 case MGSL_IOCSPARAMS32:
1142 rc = set_params32(info, compat_ptr(arg));
1145 case MGSL_IOCGPARAMS32:
1146 rc = get_params32(info, compat_ptr(arg));
1149 case MGSL_IOCGPARAMS:
1150 case MGSL_IOCSPARAMS:
1151 case MGSL_IOCGTXIDLE:
1152 case MGSL_IOCGSTATS:
1153 case MGSL_IOCWAITEVENT:
1157 case MGSL_IOCWAITGPIO:
1158 case MGSL_IOCGXSYNC:
1159 case MGSL_IOCGXCTRL:
1160 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1163 rc = ioctl(tty, cmd, arg);
1165 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1169 #define slgt_compat_ioctl NULL
1170 #endif /* ifdef CONFIG_COMPAT */
1175 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1178 unsigned long flags;
1180 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1181 info->device_name, info->phys_reg_addr,
1182 info->irq_level, info->max_frame_size);
1184 /* output current serial signal states */
1185 spin_lock_irqsave(&info->lock,flags);
1186 get_gtsignals(info);
1187 spin_unlock_irqrestore(&info->lock,flags);
1191 if (info->signals & SerialSignal_RTS)
1192 strcat(stat_buf, "|RTS");
1193 if (info->signals & SerialSignal_CTS)
1194 strcat(stat_buf, "|CTS");
1195 if (info->signals & SerialSignal_DTR)
1196 strcat(stat_buf, "|DTR");
1197 if (info->signals & SerialSignal_DSR)
1198 strcat(stat_buf, "|DSR");
1199 if (info->signals & SerialSignal_DCD)
1200 strcat(stat_buf, "|CD");
1201 if (info->signals & SerialSignal_RI)
1202 strcat(stat_buf, "|RI");
1204 if (info->params.mode != MGSL_MODE_ASYNC) {
1205 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1206 info->icount.txok, info->icount.rxok);
1207 if (info->icount.txunder)
1208 seq_printf(m, " txunder:%d", info->icount.txunder);
1209 if (info->icount.txabort)
1210 seq_printf(m, " txabort:%d", info->icount.txabort);
1211 if (info->icount.rxshort)
1212 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1213 if (info->icount.rxlong)
1214 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1215 if (info->icount.rxover)
1216 seq_printf(m, " rxover:%d", info->icount.rxover);
1217 if (info->icount.rxcrc)
1218 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1220 seq_printf(m, "\tASYNC tx:%d rx:%d",
1221 info->icount.tx, info->icount.rx);
1222 if (info->icount.frame)
1223 seq_printf(m, " fe:%d", info->icount.frame);
1224 if (info->icount.parity)
1225 seq_printf(m, " pe:%d", info->icount.parity);
1226 if (info->icount.brk)
1227 seq_printf(m, " brk:%d", info->icount.brk);
1228 if (info->icount.overrun)
1229 seq_printf(m, " oe:%d", info->icount.overrun);
1232 /* Append serial signal status to end */
1233 seq_printf(m, " %s\n", stat_buf+1);
1235 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1236 info->tx_active,info->bh_requested,info->bh_running,
1240 /* Called to print information about devices
1242 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1244 struct slgt_info *info;
1246 seq_puts(m, "synclink_gt driver\n");
1248 info = slgt_device_list;
1251 info = info->next_device;
1257 * return count of bytes in transmit buffer
1259 static int chars_in_buffer(struct tty_struct *tty)
1261 struct slgt_info *info = tty->driver_data;
1263 if (sanity_check(info, tty->name, "chars_in_buffer"))
1265 count = tbuf_bytes(info);
1266 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1271 * signal remote device to throttle send data (our receive data)
1273 static void throttle(struct tty_struct * tty)
1275 struct slgt_info *info = tty->driver_data;
1276 unsigned long flags;
1278 if (sanity_check(info, tty->name, "throttle"))
1280 DBGINFO(("%s throttle\n", info->device_name));
1282 send_xchar(tty, STOP_CHAR(tty));
1283 if (C_CRTSCTS(tty)) {
1284 spin_lock_irqsave(&info->lock,flags);
1285 info->signals &= ~SerialSignal_RTS;
1286 set_gtsignals(info);
1287 spin_unlock_irqrestore(&info->lock,flags);
1292 * signal remote device to stop throttling send data (our receive data)
1294 static void unthrottle(struct tty_struct * tty)
1296 struct slgt_info *info = tty->driver_data;
1297 unsigned long flags;
1299 if (sanity_check(info, tty->name, "unthrottle"))
1301 DBGINFO(("%s unthrottle\n", info->device_name));
1306 send_xchar(tty, START_CHAR(tty));
1308 if (C_CRTSCTS(tty)) {
1309 spin_lock_irqsave(&info->lock,flags);
1310 info->signals |= SerialSignal_RTS;
1311 set_gtsignals(info);
1312 spin_unlock_irqrestore(&info->lock,flags);
1317 * set or clear transmit break condition
1318 * break_state -1=set break condition, 0=clear
1320 static int set_break(struct tty_struct *tty, int break_state)
1322 struct slgt_info *info = tty->driver_data;
1323 unsigned short value;
1324 unsigned long flags;
1326 if (sanity_check(info, tty->name, "set_break"))
1328 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1330 spin_lock_irqsave(&info->lock,flags);
1331 value = rd_reg16(info, TCR);
1332 if (break_state == -1)
1336 wr_reg16(info, TCR, value);
1337 spin_unlock_irqrestore(&info->lock,flags);
1341 #if SYNCLINK_GENERIC_HDLC
1344 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1345 * set encoding and frame check sequence (FCS) options
1347 * dev pointer to network device structure
1348 * encoding serial encoding setting
1349 * parity FCS setting
1351 * returns 0 if success, otherwise error code
1353 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1354 unsigned short parity)
1356 struct slgt_info *info = dev_to_port(dev);
1357 unsigned char new_encoding;
1358 unsigned short new_crctype;
1360 /* return error if TTY interface open */
1361 if (info->port.count)
1364 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1368 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1369 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1370 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1371 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1372 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1373 default: return -EINVAL;
1378 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1379 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1380 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1381 default: return -EINVAL;
1384 info->params.encoding = new_encoding;
1385 info->params.crc_type = new_crctype;
1387 /* if network interface up, reprogram hardware */
1395 * called by generic HDLC layer to send frame
1397 * skb socket buffer containing HDLC frame
1398 * dev pointer to network device structure
1400 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1401 struct net_device *dev)
1403 struct slgt_info *info = dev_to_port(dev);
1404 unsigned long flags;
1406 DBGINFO(("%s hdlc_xmit\n", dev->name));
1409 return NETDEV_TX_OK;
1411 /* stop sending until this frame completes */
1412 netif_stop_queue(dev);
1414 /* update network statistics */
1415 dev->stats.tx_packets++;
1416 dev->stats.tx_bytes += skb->len;
1418 /* save start time for transmit timeout detection */
1419 netif_trans_update(dev);
1421 spin_lock_irqsave(&info->lock, flags);
1422 tx_load(info, skb->data, skb->len);
1423 spin_unlock_irqrestore(&info->lock, flags);
1425 /* done with socket buffer, so free it */
1428 return NETDEV_TX_OK;
1432 * called by network layer when interface enabled
1433 * claim resources and initialize hardware
1435 * dev pointer to network device structure
1437 * returns 0 if success, otherwise error code
1439 static int hdlcdev_open(struct net_device *dev)
1441 struct slgt_info *info = dev_to_port(dev);
1443 unsigned long flags;
1445 if (!try_module_get(THIS_MODULE))
1448 DBGINFO(("%s hdlcdev_open\n", dev->name));
1450 /* generic HDLC layer open processing */
1451 rc = hdlc_open(dev);
1455 /* arbitrate between network and tty opens */
1456 spin_lock_irqsave(&info->netlock, flags);
1457 if (info->port.count != 0 || info->netcount != 0) {
1458 DBGINFO(("%s hdlc_open busy\n", dev->name));
1459 spin_unlock_irqrestore(&info->netlock, flags);
1463 spin_unlock_irqrestore(&info->netlock, flags);
1465 /* claim resources and init adapter */
1466 if ((rc = startup(info)) != 0) {
1467 spin_lock_irqsave(&info->netlock, flags);
1469 spin_unlock_irqrestore(&info->netlock, flags);
1473 /* assert RTS and DTR, apply hardware settings */
1474 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1477 /* enable network layer transmit */
1478 netif_trans_update(dev);
1479 netif_start_queue(dev);
1481 /* inform generic HDLC layer of current DCD status */
1482 spin_lock_irqsave(&info->lock, flags);
1483 get_gtsignals(info);
1484 spin_unlock_irqrestore(&info->lock, flags);
1485 if (info->signals & SerialSignal_DCD)
1486 netif_carrier_on(dev);
1488 netif_carrier_off(dev);
1493 * called by network layer when interface is disabled
1494 * shutdown hardware and release resources
1496 * dev pointer to network device structure
1498 * returns 0 if success, otherwise error code
1500 static int hdlcdev_close(struct net_device *dev)
1502 struct slgt_info *info = dev_to_port(dev);
1503 unsigned long flags;
1505 DBGINFO(("%s hdlcdev_close\n", dev->name));
1507 netif_stop_queue(dev);
1509 /* shutdown adapter and release resources */
1514 spin_lock_irqsave(&info->netlock, flags);
1516 spin_unlock_irqrestore(&info->netlock, flags);
1518 module_put(THIS_MODULE);
1523 * called by network layer to process IOCTL call to network device
1525 * dev pointer to network device structure
1526 * ifr pointer to network interface request structure
1527 * cmd IOCTL command code
1529 * returns 0 if success, otherwise error code
1531 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1533 const size_t size = sizeof(sync_serial_settings);
1534 sync_serial_settings new_line;
1535 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1536 struct slgt_info *info = dev_to_port(dev);
1539 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1541 /* return error if TTY interface open */
1542 if (info->port.count)
1545 if (cmd != SIOCWANDEV)
1546 return hdlc_ioctl(dev, ifr, cmd);
1548 memset(&new_line, 0, sizeof(new_line));
1550 switch(ifr->ifr_settings.type) {
1551 case IF_GET_IFACE: /* return current sync_serial_settings */
1553 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1554 if (ifr->ifr_settings.size < size) {
1555 ifr->ifr_settings.size = size; /* data size wanted */
1559 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1560 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1561 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1562 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1565 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1566 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1567 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1568 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1569 default: new_line.clock_type = CLOCK_DEFAULT;
1572 new_line.clock_rate = info->params.clock_speed;
1573 new_line.loopback = info->params.loopback ? 1:0;
1575 if (copy_to_user(line, &new_line, size))
1579 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1581 if(!capable(CAP_NET_ADMIN))
1583 if (copy_from_user(&new_line, line, size))
1586 switch (new_line.clock_type)
1588 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1589 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1590 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1591 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1592 case CLOCK_DEFAULT: flags = info->params.flags &
1593 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1594 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1595 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1596 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1597 default: return -EINVAL;
1600 if (new_line.loopback != 0 && new_line.loopback != 1)
1603 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1604 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1605 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1606 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1607 info->params.flags |= flags;
1609 info->params.loopback = new_line.loopback;
1611 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1612 info->params.clock_speed = new_line.clock_rate;
1614 info->params.clock_speed = 0;
1616 /* if network interface up, reprogram hardware */
1622 return hdlc_ioctl(dev, ifr, cmd);
1627 * called by network layer when transmit timeout is detected
1629 * dev pointer to network device structure
1631 static void hdlcdev_tx_timeout(struct net_device *dev)
1633 struct slgt_info *info = dev_to_port(dev);
1634 unsigned long flags;
1636 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1638 dev->stats.tx_errors++;
1639 dev->stats.tx_aborted_errors++;
1641 spin_lock_irqsave(&info->lock,flags);
1643 spin_unlock_irqrestore(&info->lock,flags);
1645 netif_wake_queue(dev);
1649 * called by device driver when transmit completes
1650 * reenable network layer transmit if stopped
1652 * info pointer to device instance information
1654 static void hdlcdev_tx_done(struct slgt_info *info)
1656 if (netif_queue_stopped(info->netdev))
1657 netif_wake_queue(info->netdev);
1661 * called by device driver when frame received
1662 * pass frame to network layer
1664 * info pointer to device instance information
1665 * buf pointer to buffer contianing frame data
1666 * size count of data bytes in buf
1668 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1670 struct sk_buff *skb = dev_alloc_skb(size);
1671 struct net_device *dev = info->netdev;
1673 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1676 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1677 dev->stats.rx_dropped++;
1681 skb_put_data(skb, buf, size);
1683 skb->protocol = hdlc_type_trans(skb, dev);
1685 dev->stats.rx_packets++;
1686 dev->stats.rx_bytes += size;
1691 static const struct net_device_ops hdlcdev_ops = {
1692 .ndo_open = hdlcdev_open,
1693 .ndo_stop = hdlcdev_close,
1694 .ndo_start_xmit = hdlc_start_xmit,
1695 .ndo_do_ioctl = hdlcdev_ioctl,
1696 .ndo_tx_timeout = hdlcdev_tx_timeout,
1700 * called by device driver when adding device instance
1701 * do generic HDLC initialization
1703 * info pointer to device instance information
1705 * returns 0 if success, otherwise error code
1707 static int hdlcdev_init(struct slgt_info *info)
1710 struct net_device *dev;
1713 /* allocate and initialize network and HDLC layer objects */
1715 dev = alloc_hdlcdev(info);
1717 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1721 /* for network layer reporting purposes only */
1722 dev->mem_start = info->phys_reg_addr;
1723 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1724 dev->irq = info->irq_level;
1726 /* network layer callbacks and settings */
1727 dev->netdev_ops = &hdlcdev_ops;
1728 dev->watchdog_timeo = 10 * HZ;
1729 dev->tx_queue_len = 50;
1731 /* generic HDLC layer callbacks and settings */
1732 hdlc = dev_to_hdlc(dev);
1733 hdlc->attach = hdlcdev_attach;
1734 hdlc->xmit = hdlcdev_xmit;
1736 /* register objects with HDLC layer */
1737 rc = register_hdlc_device(dev);
1739 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1749 * called by device driver when removing device instance
1750 * do generic HDLC cleanup
1752 * info pointer to device instance information
1754 static void hdlcdev_exit(struct slgt_info *info)
1756 unregister_hdlc_device(info->netdev);
1757 free_netdev(info->netdev);
1758 info->netdev = NULL;
1761 #endif /* ifdef CONFIG_HDLC */
1764 * get async data from rx DMA buffers
1766 static void rx_async(struct slgt_info *info)
1768 struct mgsl_icount *icount = &info->icount;
1769 unsigned int start, end;
1771 unsigned char status;
1772 struct slgt_desc *bufs = info->rbufs;
1778 start = end = info->rbuf_current;
1780 while(desc_complete(bufs[end])) {
1781 count = desc_count(bufs[end]) - info->rbuf_index;
1782 p = bufs[end].buf + info->rbuf_index;
1784 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1785 DBGDATA(info, p, count, "rx");
1787 for(i=0 ; i < count; i+=2, p+=2) {
1793 status = *(p + 1) & (BIT1 + BIT0);
1797 else if (status & BIT0)
1799 /* discard char if tty control flags say so */
1800 if (status & info->ignore_status_mask)
1804 else if (status & BIT0)
1807 tty_insert_flip_char(&info->port, ch, stat);
1812 /* receive buffer not completed */
1813 info->rbuf_index += i;
1814 mod_timer(&info->rx_timer, jiffies + 1);
1818 info->rbuf_index = 0;
1819 free_rbufs(info, end, end);
1821 if (++end == info->rbuf_count)
1824 /* if entire list searched then no frame available */
1830 tty_flip_buffer_push(&info->port);
1834 * return next bottom half action to perform
1836 static int bh_action(struct slgt_info *info)
1838 unsigned long flags;
1841 spin_lock_irqsave(&info->lock,flags);
1843 if (info->pending_bh & BH_RECEIVE) {
1844 info->pending_bh &= ~BH_RECEIVE;
1846 } else if (info->pending_bh & BH_TRANSMIT) {
1847 info->pending_bh &= ~BH_TRANSMIT;
1849 } else if (info->pending_bh & BH_STATUS) {
1850 info->pending_bh &= ~BH_STATUS;
1853 /* Mark BH routine as complete */
1854 info->bh_running = false;
1855 info->bh_requested = false;
1859 spin_unlock_irqrestore(&info->lock,flags);
1865 * perform bottom half processing
1867 static void bh_handler(struct work_struct *work)
1869 struct slgt_info *info = container_of(work, struct slgt_info, task);
1872 info->bh_running = true;
1874 while((action = bh_action(info))) {
1877 DBGBH(("%s bh receive\n", info->device_name));
1878 switch(info->params.mode) {
1879 case MGSL_MODE_ASYNC:
1882 case MGSL_MODE_HDLC:
1883 while(rx_get_frame(info));
1886 case MGSL_MODE_MONOSYNC:
1887 case MGSL_MODE_BISYNC:
1888 case MGSL_MODE_XSYNC:
1889 while(rx_get_buf(info));
1892 /* restart receiver if rx DMA buffers exhausted */
1893 if (info->rx_restart)
1900 DBGBH(("%s bh status\n", info->device_name));
1901 info->ri_chkcount = 0;
1902 info->dsr_chkcount = 0;
1903 info->dcd_chkcount = 0;
1904 info->cts_chkcount = 0;
1907 DBGBH(("%s unknown action\n", info->device_name));
1911 DBGBH(("%s bh_handler exit\n", info->device_name));
1914 static void bh_transmit(struct slgt_info *info)
1916 struct tty_struct *tty = info->port.tty;
1918 DBGBH(("%s bh_transmit\n", info->device_name));
1923 static void dsr_change(struct slgt_info *info, unsigned short status)
1925 if (status & BIT3) {
1926 info->signals |= SerialSignal_DSR;
1927 info->input_signal_events.dsr_up++;
1929 info->signals &= ~SerialSignal_DSR;
1930 info->input_signal_events.dsr_down++;
1932 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1933 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1934 slgt_irq_off(info, IRQ_DSR);
1938 wake_up_interruptible(&info->status_event_wait_q);
1939 wake_up_interruptible(&info->event_wait_q);
1940 info->pending_bh |= BH_STATUS;
1943 static void cts_change(struct slgt_info *info, unsigned short status)
1945 if (status & BIT2) {
1946 info->signals |= SerialSignal_CTS;
1947 info->input_signal_events.cts_up++;
1949 info->signals &= ~SerialSignal_CTS;
1950 info->input_signal_events.cts_down++;
1952 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1953 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1954 slgt_irq_off(info, IRQ_CTS);
1958 wake_up_interruptible(&info->status_event_wait_q);
1959 wake_up_interruptible(&info->event_wait_q);
1960 info->pending_bh |= BH_STATUS;
1962 if (tty_port_cts_enabled(&info->port)) {
1963 if (info->port.tty) {
1964 if (info->port.tty->hw_stopped) {
1965 if (info->signals & SerialSignal_CTS) {
1966 info->port.tty->hw_stopped = 0;
1967 info->pending_bh |= BH_TRANSMIT;
1971 if (!(info->signals & SerialSignal_CTS))
1972 info->port.tty->hw_stopped = 1;
1978 static void dcd_change(struct slgt_info *info, unsigned short status)
1980 if (status & BIT1) {
1981 info->signals |= SerialSignal_DCD;
1982 info->input_signal_events.dcd_up++;
1984 info->signals &= ~SerialSignal_DCD;
1985 info->input_signal_events.dcd_down++;
1987 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1988 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1989 slgt_irq_off(info, IRQ_DCD);
1993 #if SYNCLINK_GENERIC_HDLC
1994 if (info->netcount) {
1995 if (info->signals & SerialSignal_DCD)
1996 netif_carrier_on(info->netdev);
1998 netif_carrier_off(info->netdev);
2001 wake_up_interruptible(&info->status_event_wait_q);
2002 wake_up_interruptible(&info->event_wait_q);
2003 info->pending_bh |= BH_STATUS;
2005 if (tty_port_check_carrier(&info->port)) {
2006 if (info->signals & SerialSignal_DCD)
2007 wake_up_interruptible(&info->port.open_wait);
2010 tty_hangup(info->port.tty);
2015 static void ri_change(struct slgt_info *info, unsigned short status)
2017 if (status & BIT0) {
2018 info->signals |= SerialSignal_RI;
2019 info->input_signal_events.ri_up++;
2021 info->signals &= ~SerialSignal_RI;
2022 info->input_signal_events.ri_down++;
2024 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2025 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2026 slgt_irq_off(info, IRQ_RI);
2030 wake_up_interruptible(&info->status_event_wait_q);
2031 wake_up_interruptible(&info->event_wait_q);
2032 info->pending_bh |= BH_STATUS;
2035 static void isr_rxdata(struct slgt_info *info)
2037 unsigned int count = info->rbuf_fill_count;
2038 unsigned int i = info->rbuf_fill_index;
2041 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2042 reg = rd_reg16(info, RDR);
2043 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2044 if (desc_complete(info->rbufs[i])) {
2045 /* all buffers full */
2047 info->rx_restart = 1;
2050 info->rbufs[i].buf[count++] = (unsigned char)reg;
2051 /* async mode saves status byte to buffer for each data byte */
2052 if (info->params.mode == MGSL_MODE_ASYNC)
2053 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2054 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2055 /* buffer full or end of frame */
2056 set_desc_count(info->rbufs[i], count);
2057 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2058 info->rbuf_fill_count = count = 0;
2059 if (++i == info->rbuf_count)
2061 info->pending_bh |= BH_RECEIVE;
2065 info->rbuf_fill_index = i;
2066 info->rbuf_fill_count = count;
2069 static void isr_serial(struct slgt_info *info)
2071 unsigned short status = rd_reg16(info, SSR);
2073 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2075 wr_reg16(info, SSR, status); /* clear pending */
2077 info->irq_occurred = true;
2079 if (info->params.mode == MGSL_MODE_ASYNC) {
2080 if (status & IRQ_TXIDLE) {
2081 if (info->tx_active)
2082 isr_txeom(info, status);
2084 if (info->rx_pio && (status & IRQ_RXDATA))
2086 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2088 /* process break detection if tty control allows */
2089 if (info->port.tty) {
2090 if (!(status & info->ignore_status_mask)) {
2091 if (info->read_status_mask & MASK_BREAK) {
2092 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2093 if (info->port.flags & ASYNC_SAK)
2094 do_SAK(info->port.tty);
2100 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2101 isr_txeom(info, status);
2102 if (info->rx_pio && (status & IRQ_RXDATA))
2104 if (status & IRQ_RXIDLE) {
2105 if (status & RXIDLE)
2106 info->icount.rxidle++;
2108 info->icount.exithunt++;
2109 wake_up_interruptible(&info->event_wait_q);
2112 if (status & IRQ_RXOVER)
2116 if (status & IRQ_DSR)
2117 dsr_change(info, status);
2118 if (status & IRQ_CTS)
2119 cts_change(info, status);
2120 if (status & IRQ_DCD)
2121 dcd_change(info, status);
2122 if (status & IRQ_RI)
2123 ri_change(info, status);
2126 static void isr_rdma(struct slgt_info *info)
2128 unsigned int status = rd_reg32(info, RDCSR);
2130 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2132 /* RDCSR (rx DMA control/status)
2135 * 06 save status byte to DMA buffer
2137 * 04 eol (end of list)
2138 * 03 eob (end of buffer)
2143 wr_reg32(info, RDCSR, status); /* clear pending */
2145 if (status & (BIT5 + BIT4)) {
2146 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2147 info->rx_restart = true;
2149 info->pending_bh |= BH_RECEIVE;
2152 static void isr_tdma(struct slgt_info *info)
2154 unsigned int status = rd_reg32(info, TDCSR);
2156 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2158 /* TDCSR (tx DMA control/status)
2162 * 04 eol (end of list)
2163 * 03 eob (end of buffer)
2168 wr_reg32(info, TDCSR, status); /* clear pending */
2170 if (status & (BIT5 + BIT4 + BIT3)) {
2171 // another transmit buffer has completed
2172 // run bottom half to get more send data from user
2173 info->pending_bh |= BH_TRANSMIT;
2178 * return true if there are unsent tx DMA buffers, otherwise false
2180 * if there are unsent buffers then info->tbuf_start
2181 * is set to index of first unsent buffer
2183 static bool unsent_tbufs(struct slgt_info *info)
2185 unsigned int i = info->tbuf_current;
2189 * search backwards from last loaded buffer (precedes tbuf_current)
2190 * for first unsent buffer (desc_count > 0)
2197 i = info->tbuf_count - 1;
2198 if (!desc_count(info->tbufs[i]))
2200 info->tbuf_start = i;
2202 } while (i != info->tbuf_current);
2207 static void isr_txeom(struct slgt_info *info, unsigned short status)
2209 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2211 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2213 if (status & IRQ_TXUNDER) {
2214 unsigned short val = rd_reg16(info, TCR);
2215 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2216 wr_reg16(info, TCR, val); /* clear reset bit */
2219 if (info->tx_active) {
2220 if (info->params.mode != MGSL_MODE_ASYNC) {
2221 if (status & IRQ_TXUNDER)
2222 info->icount.txunder++;
2223 else if (status & IRQ_TXIDLE)
2224 info->icount.txok++;
2227 if (unsent_tbufs(info)) {
2229 update_tx_timer(info);
2232 info->tx_active = false;
2234 del_timer(&info->tx_timer);
2236 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2237 info->signals &= ~SerialSignal_RTS;
2238 info->drop_rts_on_tx_done = false;
2239 set_gtsignals(info);
2242 #if SYNCLINK_GENERIC_HDLC
2244 hdlcdev_tx_done(info);
2248 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2252 info->pending_bh |= BH_TRANSMIT;
2257 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2259 struct cond_wait *w, *prev;
2261 /* wake processes waiting for specific transitions */
2262 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2263 if (w->data & changed) {
2265 wake_up_interruptible(&w->q);
2267 prev->next = w->next;
2269 info->gpio_wait_q = w->next;
2275 /* interrupt service routine
2277 * irq interrupt number
2278 * dev_id device ID supplied during interrupt registration
2280 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2282 struct slgt_info *info = dev_id;
2286 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2288 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2289 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2290 info->irq_occurred = true;
2291 for(i=0; i < info->port_count ; i++) {
2292 if (info->port_array[i] == NULL)
2294 spin_lock(&info->port_array[i]->lock);
2295 if (gsr & (BIT8 << i))
2296 isr_serial(info->port_array[i]);
2297 if (gsr & (BIT16 << (i*2)))
2298 isr_rdma(info->port_array[i]);
2299 if (gsr & (BIT17 << (i*2)))
2300 isr_tdma(info->port_array[i]);
2301 spin_unlock(&info->port_array[i]->lock);
2305 if (info->gpio_present) {
2307 unsigned int changed;
2308 spin_lock(&info->lock);
2309 while ((changed = rd_reg32(info, IOSR)) != 0) {
2310 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2311 /* read latched state of GPIO signals */
2312 state = rd_reg32(info, IOVR);
2313 /* clear pending GPIO interrupt bits */
2314 wr_reg32(info, IOSR, changed);
2315 for (i=0 ; i < info->port_count ; i++) {
2316 if (info->port_array[i] != NULL)
2317 isr_gpio(info->port_array[i], changed, state);
2320 spin_unlock(&info->lock);
2323 for(i=0; i < info->port_count ; i++) {
2324 struct slgt_info *port = info->port_array[i];
2327 spin_lock(&port->lock);
2328 if ((port->port.count || port->netcount) &&
2329 port->pending_bh && !port->bh_running &&
2330 !port->bh_requested) {
2331 DBGISR(("%s bh queued\n", port->device_name));
2332 schedule_work(&port->task);
2333 port->bh_requested = true;
2335 spin_unlock(&port->lock);
2338 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2342 static int startup(struct slgt_info *info)
2344 DBGINFO(("%s startup\n", info->device_name));
2346 if (tty_port_initialized(&info->port))
2349 if (!info->tx_buf) {
2350 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2351 if (!info->tx_buf) {
2352 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2357 info->pending_bh = 0;
2359 memset(&info->icount, 0, sizeof(info->icount));
2361 /* program hardware for current parameters */
2362 change_params(info);
2365 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2367 tty_port_set_initialized(&info->port, 1);
2373 * called by close() and hangup() to shutdown hardware
2375 static void shutdown(struct slgt_info *info)
2377 unsigned long flags;
2379 if (!tty_port_initialized(&info->port))
2382 DBGINFO(("%s shutdown\n", info->device_name));
2384 /* clear status wait queue because status changes */
2385 /* can't happen after shutting down the hardware */
2386 wake_up_interruptible(&info->status_event_wait_q);
2387 wake_up_interruptible(&info->event_wait_q);
2389 del_timer_sync(&info->tx_timer);
2390 del_timer_sync(&info->rx_timer);
2392 kfree(info->tx_buf);
2393 info->tx_buf = NULL;
2395 spin_lock_irqsave(&info->lock,flags);
2400 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2402 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2403 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2404 set_gtsignals(info);
2407 flush_cond_wait(&info->gpio_wait_q);
2409 spin_unlock_irqrestore(&info->lock,flags);
2412 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2414 tty_port_set_initialized(&info->port, 0);
2417 static void program_hw(struct slgt_info *info)
2419 unsigned long flags;
2421 spin_lock_irqsave(&info->lock,flags);
2426 if (info->params.mode != MGSL_MODE_ASYNC ||
2432 set_gtsignals(info);
2434 info->dcd_chkcount = 0;
2435 info->cts_chkcount = 0;
2436 info->ri_chkcount = 0;
2437 info->dsr_chkcount = 0;
2439 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2440 get_gtsignals(info);
2442 if (info->netcount ||
2443 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2446 spin_unlock_irqrestore(&info->lock,flags);
2450 * reconfigure adapter based on new parameters
2452 static void change_params(struct slgt_info *info)
2457 if (!info->port.tty)
2459 DBGINFO(("%s change_params\n", info->device_name));
2461 cflag = info->port.tty->termios.c_cflag;
2463 /* if B0 rate (hangup) specified then negate RTS and DTR */
2464 /* otherwise assert RTS and DTR */
2466 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2468 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2470 /* byte size and parity */
2472 switch (cflag & CSIZE) {
2473 case CS5: info->params.data_bits = 5; break;
2474 case CS6: info->params.data_bits = 6; break;
2475 case CS7: info->params.data_bits = 7; break;
2476 case CS8: info->params.data_bits = 8; break;
2477 default: info->params.data_bits = 7; break;
2480 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2483 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2485 info->params.parity = ASYNC_PARITY_NONE;
2487 /* calculate number of jiffies to transmit a full
2488 * FIFO (32 bytes) at specified data rate
2490 bits_per_char = info->params.data_bits +
2491 info->params.stop_bits + 1;
2493 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2495 if (info->params.data_rate) {
2496 info->timeout = (32*HZ*bits_per_char) /
2497 info->params.data_rate;
2499 info->timeout += HZ/50; /* Add .02 seconds of slop */
2501 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2502 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2504 /* process tty input control flags */
2506 info->read_status_mask = IRQ_RXOVER;
2507 if (I_INPCK(info->port.tty))
2508 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2509 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2510 info->read_status_mask |= MASK_BREAK;
2511 if (I_IGNPAR(info->port.tty))
2512 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2513 if (I_IGNBRK(info->port.tty)) {
2514 info->ignore_status_mask |= MASK_BREAK;
2515 /* If ignoring parity and break indicators, ignore
2516 * overruns too. (For real raw support).
2518 if (I_IGNPAR(info->port.tty))
2519 info->ignore_status_mask |= MASK_OVERRUN;
2525 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2527 DBGINFO(("%s get_stats\n", info->device_name));
2529 memset(&info->icount, 0, sizeof(info->icount));
2531 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2537 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2539 DBGINFO(("%s get_params\n", info->device_name));
2540 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2545 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2547 unsigned long flags;
2548 MGSL_PARAMS tmp_params;
2550 DBGINFO(("%s set_params\n", info->device_name));
2551 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2554 spin_lock_irqsave(&info->lock, flags);
2555 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2556 info->base_clock = tmp_params.clock_speed;
2558 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2559 spin_unlock_irqrestore(&info->lock, flags);
2566 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2568 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2569 if (put_user(info->idle_mode, idle_mode))
2574 static int set_txidle(struct slgt_info *info, int idle_mode)
2576 unsigned long flags;
2577 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2578 spin_lock_irqsave(&info->lock,flags);
2579 info->idle_mode = idle_mode;
2580 if (info->params.mode != MGSL_MODE_ASYNC)
2582 spin_unlock_irqrestore(&info->lock,flags);
2586 static int tx_enable(struct slgt_info *info, int enable)
2588 unsigned long flags;
2589 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2590 spin_lock_irqsave(&info->lock,flags);
2592 if (!info->tx_enabled)
2595 if (info->tx_enabled)
2598 spin_unlock_irqrestore(&info->lock,flags);
2603 * abort transmit HDLC frame
2605 static int tx_abort(struct slgt_info *info)
2607 unsigned long flags;
2608 DBGINFO(("%s tx_abort\n", info->device_name));
2609 spin_lock_irqsave(&info->lock,flags);
2611 spin_unlock_irqrestore(&info->lock,flags);
2615 static int rx_enable(struct slgt_info *info, int enable)
2617 unsigned long flags;
2618 unsigned int rbuf_fill_level;
2619 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2620 spin_lock_irqsave(&info->lock,flags);
2622 * enable[31..16] = receive DMA buffer fill level
2623 * 0 = noop (leave fill level unchanged)
2624 * fill level must be multiple of 4 and <= buffer size
2626 rbuf_fill_level = ((unsigned int)enable) >> 16;
2627 if (rbuf_fill_level) {
2628 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2629 spin_unlock_irqrestore(&info->lock, flags);
2632 info->rbuf_fill_level = rbuf_fill_level;
2633 if (rbuf_fill_level < 128)
2634 info->rx_pio = 1; /* PIO mode */
2636 info->rx_pio = 0; /* DMA mode */
2637 rx_stop(info); /* restart receiver to use new fill level */
2641 * enable[1..0] = receiver enable command
2644 * 2 = enable or force hunt mode if already enabled
2648 if (!info->rx_enabled)
2650 else if (enable == 2) {
2651 /* force hunt mode (write 1 to RCR[3]) */
2652 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2655 if (info->rx_enabled)
2658 spin_unlock_irqrestore(&info->lock,flags);
2663 * wait for specified event to occur
2665 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2667 unsigned long flags;
2670 struct mgsl_icount cprev, cnow;
2673 struct _input_signal_events oldsigs, newsigs;
2674 DECLARE_WAITQUEUE(wait, current);
2676 if (get_user(mask, mask_ptr))
2679 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2681 spin_lock_irqsave(&info->lock,flags);
2683 /* return immediately if state matches requested events */
2684 get_gtsignals(info);
2688 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2689 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2690 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2691 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2693 spin_unlock_irqrestore(&info->lock,flags);
2697 /* save current irq counts */
2698 cprev = info->icount;
2699 oldsigs = info->input_signal_events;
2701 /* enable hunt and idle irqs if needed */
2702 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2703 unsigned short val = rd_reg16(info, SCR);
2704 if (!(val & IRQ_RXIDLE))
2705 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2708 set_current_state(TASK_INTERRUPTIBLE);
2709 add_wait_queue(&info->event_wait_q, &wait);
2711 spin_unlock_irqrestore(&info->lock,flags);
2715 if (signal_pending(current)) {
2720 /* get current irq counts */
2721 spin_lock_irqsave(&info->lock,flags);
2722 cnow = info->icount;
2723 newsigs = info->input_signal_events;
2724 set_current_state(TASK_INTERRUPTIBLE);
2725 spin_unlock_irqrestore(&info->lock,flags);
2727 /* if no change, wait aborted for some reason */
2728 if (newsigs.dsr_up == oldsigs.dsr_up &&
2729 newsigs.dsr_down == oldsigs.dsr_down &&
2730 newsigs.dcd_up == oldsigs.dcd_up &&
2731 newsigs.dcd_down == oldsigs.dcd_down &&
2732 newsigs.cts_up == oldsigs.cts_up &&
2733 newsigs.cts_down == oldsigs.cts_down &&
2734 newsigs.ri_up == oldsigs.ri_up &&
2735 newsigs.ri_down == oldsigs.ri_down &&
2736 cnow.exithunt == cprev.exithunt &&
2737 cnow.rxidle == cprev.rxidle) {
2743 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2744 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2745 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2746 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2747 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2748 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2749 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2750 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2751 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2752 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2760 remove_wait_queue(&info->event_wait_q, &wait);
2761 set_current_state(TASK_RUNNING);
2764 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2765 spin_lock_irqsave(&info->lock,flags);
2766 if (!waitqueue_active(&info->event_wait_q)) {
2767 /* disable enable exit hunt mode/idle rcvd IRQs */
2769 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2771 spin_unlock_irqrestore(&info->lock,flags);
2775 rc = put_user(events, mask_ptr);
2779 static int get_interface(struct slgt_info *info, int __user *if_mode)
2781 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2782 if (put_user(info->if_mode, if_mode))
2787 static int set_interface(struct slgt_info *info, int if_mode)
2789 unsigned long flags;
2792 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2793 spin_lock_irqsave(&info->lock,flags);
2794 info->if_mode = if_mode;
2798 /* TCR (tx control) 07 1=RTS driver control */
2799 val = rd_reg16(info, TCR);
2800 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2804 wr_reg16(info, TCR, val);
2806 spin_unlock_irqrestore(&info->lock,flags);
2810 static int get_xsync(struct slgt_info *info, int __user *xsync)
2812 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2813 if (put_user(info->xsync, xsync))
2819 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2821 * sync pattern is contained in least significant bytes of value
2822 * most significant byte of sync pattern is oldest (1st sent/detected)
2824 static int set_xsync(struct slgt_info *info, int xsync)
2826 unsigned long flags;
2828 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2829 spin_lock_irqsave(&info->lock, flags);
2830 info->xsync = xsync;
2831 wr_reg32(info, XSR, xsync);
2832 spin_unlock_irqrestore(&info->lock, flags);
2836 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2838 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2839 if (put_user(info->xctrl, xctrl))
2845 * set extended control options
2847 * xctrl[31:19] reserved, must be zero
2848 * xctrl[18:17] extended sync pattern length in bytes
2849 * 00 = 1 byte in xsr[7:0]
2850 * 01 = 2 bytes in xsr[15:0]
2851 * 10 = 3 bytes in xsr[23:0]
2852 * 11 = 4 bytes in xsr[31:0]
2853 * xctrl[16] 1 = enable terminal count, 0=disabled
2854 * xctrl[15:0] receive terminal count for fixed length packets
2855 * value is count minus one (0 = 1 byte packet)
2856 * when terminal count is reached, receiver
2857 * automatically returns to hunt mode and receive
2858 * FIFO contents are flushed to DMA buffers with
2859 * end of frame (EOF) status
2861 static int set_xctrl(struct slgt_info *info, int xctrl)
2863 unsigned long flags;
2865 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2866 spin_lock_irqsave(&info->lock, flags);
2867 info->xctrl = xctrl;
2868 wr_reg32(info, XCR, xctrl);
2869 spin_unlock_irqrestore(&info->lock, flags);
2874 * set general purpose IO pin state and direction
2877 * state each bit indicates a pin state
2878 * smask set bit indicates pin state to set
2879 * dir each bit indicates a pin direction (0=input, 1=output)
2880 * dmask set bit indicates pin direction to set
2882 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2884 unsigned long flags;
2885 struct gpio_desc gpio;
2888 if (!info->gpio_present)
2890 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2892 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2893 info->device_name, gpio.state, gpio.smask,
2894 gpio.dir, gpio.dmask));
2896 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2898 data = rd_reg32(info, IODR);
2899 data |= gpio.dmask & gpio.dir;
2900 data &= ~(gpio.dmask & ~gpio.dir);
2901 wr_reg32(info, IODR, data);
2904 data = rd_reg32(info, IOVR);
2905 data |= gpio.smask & gpio.state;
2906 data &= ~(gpio.smask & ~gpio.state);
2907 wr_reg32(info, IOVR, data);
2909 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2915 * get general purpose IO pin state and direction
2917 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2919 struct gpio_desc gpio;
2920 if (!info->gpio_present)
2922 gpio.state = rd_reg32(info, IOVR);
2923 gpio.smask = 0xffffffff;
2924 gpio.dir = rd_reg32(info, IODR);
2925 gpio.dmask = 0xffffffff;
2926 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2928 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2929 info->device_name, gpio.state, gpio.dir));
2934 * conditional wait facility
2936 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2938 init_waitqueue_head(&w->q);
2939 init_waitqueue_entry(&w->wait, current);
2943 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2945 set_current_state(TASK_INTERRUPTIBLE);
2946 add_wait_queue(&w->q, &w->wait);
2951 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2953 struct cond_wait *w, *prev;
2954 remove_wait_queue(&cw->q, &cw->wait);
2955 set_current_state(TASK_RUNNING);
2956 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2959 prev->next = w->next;
2967 static void flush_cond_wait(struct cond_wait **head)
2969 while (*head != NULL) {
2970 wake_up_interruptible(&(*head)->q);
2971 *head = (*head)->next;
2976 * wait for general purpose I/O pin(s) to enter specified state
2979 * state - bit indicates target pin state
2980 * smask - set bit indicates watched pin
2982 * The wait ends when at least one watched pin enters the specified
2983 * state. When 0 (no error) is returned, user_gpio->state is set to the
2984 * state of all GPIO pins when the wait ends.
2986 * Note: Each pin may be a dedicated input, dedicated output, or
2987 * configurable input/output. The number and configuration of pins
2988 * varies with the specific adapter model. Only input pins (dedicated
2989 * or configured) can be monitored with this function.
2991 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2993 unsigned long flags;
2995 struct gpio_desc gpio;
2996 struct cond_wait wait;
2999 if (!info->gpio_present)
3001 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3003 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3004 info->device_name, gpio.state, gpio.smask));
3005 /* ignore output pins identified by set IODR bit */
3006 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3008 init_cond_wait(&wait, gpio.smask);
3010 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3011 /* enable interrupts for watched pins */
3012 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3013 /* get current pin states */
3014 state = rd_reg32(info, IOVR);
3016 if (gpio.smask & ~(state ^ gpio.state)) {
3017 /* already in target state */
3020 /* wait for target state */
3021 add_cond_wait(&info->gpio_wait_q, &wait);
3022 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3024 if (signal_pending(current))
3027 gpio.state = wait.data;
3028 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3029 remove_cond_wait(&info->gpio_wait_q, &wait);
3032 /* disable all GPIO interrupts if no waiting processes */
3033 if (info->gpio_wait_q == NULL)
3034 wr_reg32(info, IOER, 0);
3035 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3037 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3042 static int modem_input_wait(struct slgt_info *info,int arg)
3044 unsigned long flags;
3046 struct mgsl_icount cprev, cnow;
3047 DECLARE_WAITQUEUE(wait, current);
3049 /* save current irq counts */
3050 spin_lock_irqsave(&info->lock,flags);
3051 cprev = info->icount;
3052 add_wait_queue(&info->status_event_wait_q, &wait);
3053 set_current_state(TASK_INTERRUPTIBLE);
3054 spin_unlock_irqrestore(&info->lock,flags);
3058 if (signal_pending(current)) {
3063 /* get new irq counts */
3064 spin_lock_irqsave(&info->lock,flags);
3065 cnow = info->icount;
3066 set_current_state(TASK_INTERRUPTIBLE);
3067 spin_unlock_irqrestore(&info->lock,flags);
3069 /* if no change, wait aborted for some reason */
3070 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3071 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3076 /* check for change in caller specified modem input */
3077 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3078 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3079 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3080 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3087 remove_wait_queue(&info->status_event_wait_q, &wait);
3088 set_current_state(TASK_RUNNING);
3093 * return state of serial control and status signals
3095 static int tiocmget(struct tty_struct *tty)
3097 struct slgt_info *info = tty->driver_data;
3098 unsigned int result;
3099 unsigned long flags;
3101 spin_lock_irqsave(&info->lock,flags);
3102 get_gtsignals(info);
3103 spin_unlock_irqrestore(&info->lock,flags);
3105 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3106 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3107 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3108 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3109 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3110 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3112 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3117 * set modem control signals (DTR/RTS)
3119 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3120 * TIOCMSET = set/clear signal values
3121 * value bit mask for command
3123 static int tiocmset(struct tty_struct *tty,
3124 unsigned int set, unsigned int clear)
3126 struct slgt_info *info = tty->driver_data;
3127 unsigned long flags;
3129 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3131 if (set & TIOCM_RTS)
3132 info->signals |= SerialSignal_RTS;
3133 if (set & TIOCM_DTR)
3134 info->signals |= SerialSignal_DTR;
3135 if (clear & TIOCM_RTS)
3136 info->signals &= ~SerialSignal_RTS;
3137 if (clear & TIOCM_DTR)
3138 info->signals &= ~SerialSignal_DTR;
3140 spin_lock_irqsave(&info->lock,flags);
3141 set_gtsignals(info);
3142 spin_unlock_irqrestore(&info->lock,flags);
3146 static int carrier_raised(struct tty_port *port)
3148 unsigned long flags;
3149 struct slgt_info *info = container_of(port, struct slgt_info, port);
3151 spin_lock_irqsave(&info->lock,flags);
3152 get_gtsignals(info);
3153 spin_unlock_irqrestore(&info->lock,flags);
3154 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3157 static void dtr_rts(struct tty_port *port, int on)
3159 unsigned long flags;
3160 struct slgt_info *info = container_of(port, struct slgt_info, port);
3162 spin_lock_irqsave(&info->lock,flags);
3164 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3166 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3167 set_gtsignals(info);
3168 spin_unlock_irqrestore(&info->lock,flags);
3173 * block current process until the device is ready to open
3175 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3176 struct slgt_info *info)
3178 DECLARE_WAITQUEUE(wait, current);
3180 bool do_clocal = false;
3181 unsigned long flags;
3183 struct tty_port *port = &info->port;
3185 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3187 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3188 /* nonblock mode is set or port is not enabled */
3189 tty_port_set_active(port, 1);
3196 /* Wait for carrier detect and the line to become
3197 * free (i.e., not in use by the callout). While we are in
3198 * this loop, port->count is dropped by one, so that
3199 * close() knows when to free things. We restore it upon
3200 * exit, either normal or abnormal.
3204 add_wait_queue(&port->open_wait, &wait);
3206 spin_lock_irqsave(&info->lock, flags);
3208 spin_unlock_irqrestore(&info->lock, flags);
3209 port->blocked_open++;
3212 if (C_BAUD(tty) && tty_port_initialized(port))
3213 tty_port_raise_dtr_rts(port);
3215 set_current_state(TASK_INTERRUPTIBLE);
3217 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3218 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3219 -EAGAIN : -ERESTARTSYS;
3223 cd = tty_port_carrier_raised(port);
3224 if (do_clocal || cd)
3227 if (signal_pending(current)) {
3228 retval = -ERESTARTSYS;
3232 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3238 set_current_state(TASK_RUNNING);
3239 remove_wait_queue(&port->open_wait, &wait);
3241 if (!tty_hung_up_p(filp))
3243 port->blocked_open--;
3246 tty_port_set_active(port, 1);
3248 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3253 * allocate buffers used for calling line discipline receive_buf
3254 * directly in synchronous mode
3255 * note: add 5 bytes to max frame size to allow appending
3256 * 32-bit CRC and status byte when configured to do so
3258 static int alloc_tmp_rbuf(struct slgt_info *info)
3260 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3261 if (info->tmp_rbuf == NULL)
3263 /* unused flag buffer to satisfy receive_buf calling interface */
3264 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3265 if (!info->flag_buf) {
3266 kfree(info->tmp_rbuf);
3267 info->tmp_rbuf = NULL;
3273 static void free_tmp_rbuf(struct slgt_info *info)
3275 kfree(info->tmp_rbuf);
3276 info->tmp_rbuf = NULL;
3277 kfree(info->flag_buf);
3278 info->flag_buf = NULL;
3282 * allocate DMA descriptor lists.
3284 static int alloc_desc(struct slgt_info *info)
3289 /* allocate memory to hold descriptor lists */
3290 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3291 &info->bufs_dma_addr);
3292 if (info->bufs == NULL)
3295 info->rbufs = (struct slgt_desc*)info->bufs;
3296 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3298 pbufs = (unsigned int)info->bufs_dma_addr;
3301 * Build circular lists of descriptors
3304 for (i=0; i < info->rbuf_count; i++) {
3305 /* physical address of this descriptor */
3306 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3308 /* physical address of next descriptor */
3309 if (i == info->rbuf_count - 1)
3310 info->rbufs[i].next = cpu_to_le32(pbufs);
3312 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3313 set_desc_count(info->rbufs[i], DMABUFSIZE);
3316 for (i=0; i < info->tbuf_count; i++) {
3317 /* physical address of this descriptor */
3318 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3320 /* physical address of next descriptor */
3321 if (i == info->tbuf_count - 1)
3322 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3324 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3330 static void free_desc(struct slgt_info *info)
3332 if (info->bufs != NULL) {
3333 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3340 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3343 for (i=0; i < count; i++) {
3344 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3346 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3351 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3354 for (i=0; i < count; i++) {
3355 if (bufs[i].buf == NULL)
3357 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3362 static int alloc_dma_bufs(struct slgt_info *info)
3364 info->rbuf_count = 32;
3365 info->tbuf_count = 32;
3367 if (alloc_desc(info) < 0 ||
3368 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3369 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3370 alloc_tmp_rbuf(info) < 0) {
3371 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3378 static void free_dma_bufs(struct slgt_info *info)
3381 free_bufs(info, info->rbufs, info->rbuf_count);
3382 free_bufs(info, info->tbufs, info->tbuf_count);
3385 free_tmp_rbuf(info);
3388 static int claim_resources(struct slgt_info *info)
3390 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3391 DBGERR(("%s reg addr conflict, addr=%08X\n",
3392 info->device_name, info->phys_reg_addr));
3393 info->init_error = DiagStatus_AddressConflict;
3397 info->reg_addr_requested = true;
3399 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3400 if (!info->reg_addr) {
3401 DBGERR(("%s can't map device registers, addr=%08X\n",
3402 info->device_name, info->phys_reg_addr));
3403 info->init_error = DiagStatus_CantAssignPciResources;
3409 release_resources(info);
3413 static void release_resources(struct slgt_info *info)
3415 if (info->irq_requested) {
3416 free_irq(info->irq_level, info);
3417 info->irq_requested = false;
3420 if (info->reg_addr_requested) {
3421 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3422 info->reg_addr_requested = false;
3425 if (info->reg_addr) {
3426 iounmap(info->reg_addr);
3427 info->reg_addr = NULL;
3431 /* Add the specified device instance data structure to the
3432 * global linked list of devices and increment the device count.
3434 static void add_device(struct slgt_info *info)
3438 info->next_device = NULL;
3439 info->line = slgt_device_count;
3440 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3442 if (info->line < MAX_DEVICES) {
3443 if (maxframe[info->line])
3444 info->max_frame_size = maxframe[info->line];
3447 slgt_device_count++;
3449 if (!slgt_device_list)
3450 slgt_device_list = info;
3452 struct slgt_info *current_dev = slgt_device_list;
3453 while(current_dev->next_device)
3454 current_dev = current_dev->next_device;
3455 current_dev->next_device = info;
3458 if (info->max_frame_size < 4096)
3459 info->max_frame_size = 4096;
3460 else if (info->max_frame_size > 65535)
3461 info->max_frame_size = 65535;
3463 switch(info->pdev->device) {
3464 case SYNCLINK_GT_DEVICE_ID:
3467 case SYNCLINK_GT2_DEVICE_ID:
3470 case SYNCLINK_GT4_DEVICE_ID:
3473 case SYNCLINK_AC_DEVICE_ID:
3475 info->params.mode = MGSL_MODE_ASYNC;
3478 devstr = "(unknown model)";
3480 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3481 devstr, info->device_name, info->phys_reg_addr,
3482 info->irq_level, info->max_frame_size);
3484 #if SYNCLINK_GENERIC_HDLC
3489 static const struct tty_port_operations slgt_port_ops = {
3490 .carrier_raised = carrier_raised,
3495 * allocate device instance structure, return NULL on failure
3497 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3499 struct slgt_info *info;
3501 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3504 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3505 driver_name, adapter_num, port_num));
3507 tty_port_init(&info->port);
3508 info->port.ops = &slgt_port_ops;
3509 info->magic = MGSL_MAGIC;
3510 INIT_WORK(&info->task, bh_handler);
3511 info->max_frame_size = 4096;
3512 info->base_clock = 14745600;
3513 info->rbuf_fill_level = DMABUFSIZE;
3514 info->port.close_delay = 5*HZ/10;
3515 info->port.closing_wait = 30*HZ;
3516 init_waitqueue_head(&info->status_event_wait_q);
3517 init_waitqueue_head(&info->event_wait_q);
3518 spin_lock_init(&info->netlock);
3519 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3520 info->idle_mode = HDLC_TXIDLE_FLAGS;
3521 info->adapter_num = adapter_num;
3522 info->port_num = port_num;
3524 timer_setup(&info->tx_timer, tx_timeout, 0);
3525 timer_setup(&info->rx_timer, rx_timeout, 0);
3527 /* Copy configuration info to device instance data */
3529 info->irq_level = pdev->irq;
3530 info->phys_reg_addr = pci_resource_start(pdev,0);
3532 info->bus_type = MGSL_BUS_TYPE_PCI;
3533 info->irq_flags = IRQF_SHARED;
3535 info->init_error = -1; /* assume error, set to 0 on successful init */
3541 static void device_init(int adapter_num, struct pci_dev *pdev)
3543 struct slgt_info *port_array[SLGT_MAX_PORTS];
3547 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3549 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3552 /* allocate device instances for all ports */
3553 for (i=0; i < port_count; ++i) {
3554 port_array[i] = alloc_dev(adapter_num, i, pdev);
3555 if (port_array[i] == NULL) {
3556 for (--i; i >= 0; --i) {
3557 tty_port_destroy(&port_array[i]->port);
3558 kfree(port_array[i]);
3564 /* give copy of port_array to all ports and add to device list */
3565 for (i=0; i < port_count; ++i) {
3566 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3567 add_device(port_array[i]);
3568 port_array[i]->port_count = port_count;
3569 spin_lock_init(&port_array[i]->lock);
3572 /* Allocate and claim adapter resources */
3573 if (!claim_resources(port_array[0])) {
3575 alloc_dma_bufs(port_array[0]);
3577 /* copy resource information from first port to others */
3578 for (i = 1; i < port_count; ++i) {
3579 port_array[i]->irq_level = port_array[0]->irq_level;
3580 port_array[i]->reg_addr = port_array[0]->reg_addr;
3581 alloc_dma_bufs(port_array[i]);
3584 if (request_irq(port_array[0]->irq_level,
3586 port_array[0]->irq_flags,
3587 port_array[0]->device_name,
3588 port_array[0]) < 0) {
3589 DBGERR(("%s request_irq failed IRQ=%d\n",
3590 port_array[0]->device_name,
3591 port_array[0]->irq_level));
3593 port_array[0]->irq_requested = true;
3594 adapter_test(port_array[0]);
3595 for (i=1 ; i < port_count ; i++) {
3596 port_array[i]->init_error = port_array[0]->init_error;
3597 port_array[i]->gpio_present = port_array[0]->gpio_present;
3602 for (i = 0; i < port_count; ++i) {
3603 struct slgt_info *info = port_array[i];
3604 tty_port_register_device(&info->port, serial_driver, info->line,
3609 static int init_one(struct pci_dev *dev,
3610 const struct pci_device_id *ent)
3612 if (pci_enable_device(dev)) {
3613 printk("error enabling pci device %p\n", dev);
3616 pci_set_master(dev);
3617 device_init(slgt_device_count, dev);
3621 static void remove_one(struct pci_dev *dev)
3625 static const struct tty_operations ops = {
3629 .put_char = put_char,
3630 .flush_chars = flush_chars,
3631 .write_room = write_room,
3632 .chars_in_buffer = chars_in_buffer,
3633 .flush_buffer = flush_buffer,
3635 .compat_ioctl = slgt_compat_ioctl,
3636 .throttle = throttle,
3637 .unthrottle = unthrottle,
3638 .send_xchar = send_xchar,
3639 .break_ctl = set_break,
3640 .wait_until_sent = wait_until_sent,
3641 .set_termios = set_termios,
3643 .start = tx_release,
3645 .tiocmget = tiocmget,
3646 .tiocmset = tiocmset,
3647 .get_icount = get_icount,
3648 .proc_show = synclink_gt_proc_show,
3651 static void slgt_cleanup(void)
3654 struct slgt_info *info;
3655 struct slgt_info *tmp;
3657 printk(KERN_INFO "unload %s\n", driver_name);
3659 if (serial_driver) {
3660 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3661 tty_unregister_device(serial_driver, info->line);
3662 rc = tty_unregister_driver(serial_driver);
3664 DBGERR(("tty_unregister_driver error=%d\n", rc));
3665 put_tty_driver(serial_driver);
3669 info = slgt_device_list;
3672 info = info->next_device;
3675 /* release devices */
3676 info = slgt_device_list;
3678 #if SYNCLINK_GENERIC_HDLC
3681 free_dma_bufs(info);
3682 free_tmp_rbuf(info);
3683 if (info->port_num == 0)
3684 release_resources(info);
3686 info = info->next_device;
3687 tty_port_destroy(&tmp->port);
3692 pci_unregister_driver(&pci_driver);
3696 * Driver initialization entry point.
3698 static int __init slgt_init(void)
3702 printk(KERN_INFO "%s\n", driver_name);
3704 serial_driver = alloc_tty_driver(MAX_DEVICES);
3705 if (!serial_driver) {
3706 printk("%s can't allocate tty driver\n", driver_name);
3710 /* Initialize the tty_driver structure */
3712 serial_driver->driver_name = slgt_driver_name;
3713 serial_driver->name = tty_dev_prefix;
3714 serial_driver->major = ttymajor;
3715 serial_driver->minor_start = 64;
3716 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3717 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3718 serial_driver->init_termios = tty_std_termios;
3719 serial_driver->init_termios.c_cflag =
3720 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3721 serial_driver->init_termios.c_ispeed = 9600;
3722 serial_driver->init_termios.c_ospeed = 9600;
3723 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3724 tty_set_operations(serial_driver, &ops);
3725 if ((rc = tty_register_driver(serial_driver)) < 0) {
3726 DBGERR(("%s can't register serial driver\n", driver_name));
3727 put_tty_driver(serial_driver);
3728 serial_driver = NULL;
3732 printk(KERN_INFO "%s, tty major#%d\n",
3733 driver_name, serial_driver->major);
3735 slgt_device_count = 0;
3736 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3737 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3740 pci_registered = true;
3742 if (!slgt_device_list)
3743 printk("%s no devices found\n",driver_name);
3752 static void __exit slgt_exit(void)
3757 module_init(slgt_init);
3758 module_exit(slgt_exit);
3761 * register access routines
3764 #define CALC_REGADDR() \
3765 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3767 reg_addr += (info->port_num) * 32; \
3768 else if (addr >= 0x40) \
3769 reg_addr += (info->port_num) * 16;
3771 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3774 return readb((void __iomem *)reg_addr);
3777 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3780 writeb(value, (void __iomem *)reg_addr);
3783 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3786 return readw((void __iomem *)reg_addr);
3789 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3792 writew(value, (void __iomem *)reg_addr);
3795 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3798 return readl((void __iomem *)reg_addr);
3801 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3804 writel(value, (void __iomem *)reg_addr);
3807 static void rdma_reset(struct slgt_info *info)
3812 wr_reg32(info, RDCSR, BIT1);
3814 /* wait for enable bit cleared */
3815 for(i=0 ; i < 1000 ; i++)
3816 if (!(rd_reg32(info, RDCSR) & BIT0))
3820 static void tdma_reset(struct slgt_info *info)
3825 wr_reg32(info, TDCSR, BIT1);
3827 /* wait for enable bit cleared */
3828 for(i=0 ; i < 1000 ; i++)
3829 if (!(rd_reg32(info, TDCSR) & BIT0))
3834 * enable internal loopback
3835 * TxCLK and RxCLK are generated from BRG
3836 * and TxD is looped back to RxD internally.
3838 static void enable_loopback(struct slgt_info *info)
3840 /* SCR (serial control) BIT2=loopback enable */
3841 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3843 if (info->params.mode != MGSL_MODE_ASYNC) {
3844 /* CCR (clock control)
3845 * 07..05 tx clock source (010 = BRG)
3846 * 04..02 rx clock source (010 = BRG)
3847 * 01 auxclk enable (0 = disable)
3848 * 00 BRG enable (1 = enable)
3852 wr_reg8(info, CCR, 0x49);
3854 /* set speed if available, otherwise use default */
3855 if (info->params.clock_speed)
3856 set_rate(info, info->params.clock_speed);
3858 set_rate(info, 3686400);
3863 * set baud rate generator to specified rate
3865 static void set_rate(struct slgt_info *info, u32 rate)
3868 unsigned int osc = info->base_clock;
3870 /* div = osc/rate - 1
3872 * Round div up if osc/rate is not integer to
3873 * force to next slowest rate.
3878 if (!(osc % rate) && div)
3880 wr_reg16(info, BDR, (unsigned short)div);
3884 static void rx_stop(struct slgt_info *info)
3888 /* disable and reset receiver */
3889 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3890 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3891 wr_reg16(info, RCR, val); /* clear reset bit */
3893 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3895 /* clear pending rx interrupts */
3896 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3900 info->rx_enabled = false;
3901 info->rx_restart = false;
3904 static void rx_start(struct slgt_info *info)
3908 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3910 /* clear pending rx overrun IRQ */
3911 wr_reg16(info, SSR, IRQ_RXOVER);
3913 /* reset and disable receiver */
3914 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3915 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3916 wr_reg16(info, RCR, val); /* clear reset bit */
3922 /* rx request when rx FIFO not empty */
3923 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3924 slgt_irq_on(info, IRQ_RXDATA);
3925 if (info->params.mode == MGSL_MODE_ASYNC) {
3926 /* enable saving of rx status */
3927 wr_reg32(info, RDCSR, BIT6);
3930 /* rx request when rx FIFO half full */
3931 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3932 /* set 1st descriptor address */
3933 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3935 if (info->params.mode != MGSL_MODE_ASYNC) {
3936 /* enable rx DMA and DMA interrupt */
3937 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3939 /* enable saving of rx status, rx DMA and DMA interrupt */
3940 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3944 slgt_irq_on(info, IRQ_RXOVER);
3946 /* enable receiver */
3947 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3949 info->rx_restart = false;
3950 info->rx_enabled = true;
3953 static void tx_start(struct slgt_info *info)
3955 if (!info->tx_enabled) {
3957 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3958 info->tx_enabled = true;
3961 if (desc_count(info->tbufs[info->tbuf_start])) {
3962 info->drop_rts_on_tx_done = false;
3964 if (info->params.mode != MGSL_MODE_ASYNC) {
3965 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3966 get_gtsignals(info);
3967 if (!(info->signals & SerialSignal_RTS)) {
3968 info->signals |= SerialSignal_RTS;
3969 set_gtsignals(info);
3970 info->drop_rts_on_tx_done = true;
3974 slgt_irq_off(info, IRQ_TXDATA);
3975 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3976 /* clear tx idle and underrun status bits */
3977 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3979 slgt_irq_off(info, IRQ_TXDATA);
3980 slgt_irq_on(info, IRQ_TXIDLE);
3981 /* clear tx idle status bit */
3982 wr_reg16(info, SSR, IRQ_TXIDLE);
3984 /* set 1st descriptor address and start DMA */
3985 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3986 wr_reg32(info, TDCSR, BIT2 + BIT0);
3987 info->tx_active = true;
3991 static void tx_stop(struct slgt_info *info)
3995 del_timer(&info->tx_timer);
3999 /* reset and disable transmitter */
4000 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4001 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4003 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4005 /* clear tx idle and underrun status bit */
4006 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4010 info->tx_enabled = false;
4011 info->tx_active = false;
4014 static void reset_port(struct slgt_info *info)
4016 if (!info->reg_addr)
4022 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4023 set_gtsignals(info);
4025 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4028 static void reset_adapter(struct slgt_info *info)
4031 for (i=0; i < info->port_count; ++i) {
4032 if (info->port_array[i])
4033 reset_port(info->port_array[i]);
4037 static void async_mode(struct slgt_info *info)
4041 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4047 * 15..13 mode, 010=async
4048 * 12..10 encoding, 000=NRZ
4050 * 08 1=odd parity, 0=even parity
4051 * 07 1=RTS driver control
4053 * 05..04 character length
4058 * 03 0=1 stop bit, 1=2 stop bits
4061 * 00 auto-CTS enable
4065 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4068 if (info->params.parity != ASYNC_PARITY_NONE) {
4070 if (info->params.parity == ASYNC_PARITY_ODD)
4074 switch (info->params.data_bits)
4076 case 6: val |= BIT4; break;
4077 case 7: val |= BIT5; break;
4078 case 8: val |= BIT5 + BIT4; break;
4081 if (info->params.stop_bits != 1)
4084 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4087 wr_reg16(info, TCR, val);
4091 * 15..13 mode, 010=async
4092 * 12..10 encoding, 000=NRZ
4094 * 08 1=odd parity, 0=even parity
4095 * 07..06 reserved, must be 0
4096 * 05..04 character length
4101 * 03 reserved, must be zero
4104 * 00 auto-DCD enable
4108 if (info->params.parity != ASYNC_PARITY_NONE) {
4110 if (info->params.parity == ASYNC_PARITY_ODD)
4114 switch (info->params.data_bits)
4116 case 6: val |= BIT4; break;
4117 case 7: val |= BIT5; break;
4118 case 8: val |= BIT5 + BIT4; break;
4121 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4124 wr_reg16(info, RCR, val);
4126 /* CCR (clock control)
4128 * 07..05 011 = tx clock source is BRG/16
4129 * 04..02 010 = rx clock source is BRG
4130 * 01 0 = auxclk disabled
4131 * 00 1 = BRG enabled
4135 wr_reg8(info, CCR, 0x69);
4139 /* SCR (serial control)
4141 * 15 1=tx req on FIFO half empty
4142 * 14 1=rx req on FIFO half full
4143 * 13 tx data IRQ enable
4144 * 12 tx idle IRQ enable
4145 * 11 rx break on IRQ enable
4146 * 10 rx data IRQ enable
4147 * 09 rx break off IRQ enable
4148 * 08 overrun IRQ enable
4153 * 03 0=16x sampling, 1=8x sampling
4154 * 02 1=txd->rxd internal loopback enable
4155 * 01 reserved, must be zero
4156 * 00 1=master IRQ enable
4158 val = BIT15 + BIT14 + BIT0;
4159 /* JCR[8] : 1 = x8 async mode feature available */
4160 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4161 ((info->base_clock < (info->params.data_rate * 16)) ||
4162 (info->base_clock % (info->params.data_rate * 16)))) {
4163 /* use 8x sampling */
4165 set_rate(info, info->params.data_rate * 8);
4167 /* use 16x sampling */
4168 set_rate(info, info->params.data_rate * 16);
4170 wr_reg16(info, SCR, val);
4172 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4174 if (info->params.loopback)
4175 enable_loopback(info);
4178 static void sync_mode(struct slgt_info *info)
4182 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4190 * 001=raw bit synchronous
4191 * 010=asynchronous/isochronous
4192 * 011=monosync byte synchronous
4193 * 100=bisync byte synchronous
4194 * 101=xsync byte synchronous
4198 * 07 1=RTS driver control
4199 * 06 preamble enable
4200 * 05..04 preamble length
4201 * 03 share open/close flag
4204 * 00 auto-CTS enable
4208 switch(info->params.mode) {
4209 case MGSL_MODE_XSYNC:
4210 val |= BIT15 + BIT13;
4212 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4213 case MGSL_MODE_BISYNC: val |= BIT15; break;
4214 case MGSL_MODE_RAW: val |= BIT13; break;
4216 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4219 switch(info->params.encoding)
4221 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4222 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4223 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4224 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4225 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4226 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4227 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4230 switch (info->params.crc_type & HDLC_CRC_MASK)
4232 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4233 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4236 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4239 switch (info->params.preamble_length)
4241 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4242 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4243 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4246 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4249 wr_reg16(info, TCR, val);
4251 /* TPR (transmit preamble) */
4253 switch (info->params.preamble)
4255 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4256 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4257 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4258 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4259 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4260 default: val = 0x7e; break;
4262 wr_reg8(info, TPR, (unsigned char)val);
4268 * 001=raw bit synchronous
4269 * 010=asynchronous/isochronous
4270 * 011=monosync byte synchronous
4271 * 100=bisync byte synchronous
4272 * 101=xsync byte synchronous
4276 * 07..03 reserved, must be 0
4279 * 00 auto-DCD enable
4283 switch(info->params.mode) {
4284 case MGSL_MODE_XSYNC:
4285 val |= BIT15 + BIT13;
4287 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4288 case MGSL_MODE_BISYNC: val |= BIT15; break;
4289 case MGSL_MODE_RAW: val |= BIT13; break;
4292 switch(info->params.encoding)
4294 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4295 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4296 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4297 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4298 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4299 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4300 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4303 switch (info->params.crc_type & HDLC_CRC_MASK)
4305 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4306 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4309 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4312 wr_reg16(info, RCR, val);
4314 /* CCR (clock control)
4316 * 07..05 tx clock source
4317 * 04..02 rx clock source
4323 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4325 // when RxC source is DPLL, BRG generates 16X DPLL
4326 // reference clock, so take TxC from BRG/16 to get
4327 // transmit clock at actual data rate
4328 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4329 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4331 val |= BIT6; /* 010, txclk = BRG */
4333 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4334 val |= BIT7; /* 100, txclk = DPLL Input */
4335 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4336 val |= BIT5; /* 001, txclk = RXC Input */
4338 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4339 val |= BIT3; /* 010, rxclk = BRG */
4340 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4341 val |= BIT4; /* 100, rxclk = DPLL */
4342 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4343 val |= BIT2; /* 001, rxclk = TXC Input */
4345 if (info->params.clock_speed)
4348 wr_reg8(info, CCR, (unsigned char)val);
4350 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4352 // program DPLL mode
4353 switch(info->params.encoding)
4355 case HDLC_ENCODING_BIPHASE_MARK:
4356 case HDLC_ENCODING_BIPHASE_SPACE:
4358 case HDLC_ENCODING_BIPHASE_LEVEL:
4359 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4360 val = BIT7 + BIT6; break;
4361 default: val = BIT6; // NRZ encodings
4363 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4365 // DPLL requires a 16X reference clock from BRG
4366 set_rate(info, info->params.clock_speed * 16);
4369 set_rate(info, info->params.clock_speed);
4375 /* SCR (serial control)
4377 * 15 1=tx req on FIFO half empty
4378 * 14 1=rx req on FIFO half full
4379 * 13 tx data IRQ enable
4380 * 12 tx idle IRQ enable
4381 * 11 underrun IRQ enable
4382 * 10 rx data IRQ enable
4383 * 09 rx idle IRQ enable
4384 * 08 overrun IRQ enable
4389 * 03 reserved, must be zero
4390 * 02 1=txd->rxd internal loopback enable
4391 * 01 reserved, must be zero
4392 * 00 1=master IRQ enable
4394 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4396 if (info->params.loopback)
4397 enable_loopback(info);
4401 * set transmit idle mode
4403 static void tx_set_idle(struct slgt_info *info)
4408 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4409 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4411 tcr = rd_reg16(info, TCR);
4412 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4413 /* disable preamble, set idle size to 16 bits */
4414 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4415 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4416 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4417 } else if (!(tcr & BIT6)) {
4418 /* preamble is disabled, set idle size to 8 bits */
4419 tcr &= ~(BIT5 + BIT4);
4421 wr_reg16(info, TCR, tcr);
4423 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4424 /* LSB of custom tx idle specified in tx idle register */
4425 val = (unsigned char)(info->idle_mode & 0xff);
4427 /* standard 8 bit idle patterns */
4428 switch(info->idle_mode)
4430 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4431 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4432 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4433 case HDLC_TXIDLE_ZEROS:
4434 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4435 default: val = 0xff;
4439 wr_reg8(info, TIR, val);
4443 * get state of V24 status (input) signals
4445 static void get_gtsignals(struct slgt_info *info)
4447 unsigned short status = rd_reg16(info, SSR);
4449 /* clear all serial signals except RTS and DTR */
4450 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4453 info->signals |= SerialSignal_DSR;
4455 info->signals |= SerialSignal_CTS;
4457 info->signals |= SerialSignal_DCD;
4459 info->signals |= SerialSignal_RI;
4463 * set V.24 Control Register based on current configuration
4465 static void msc_set_vcr(struct slgt_info *info)
4467 unsigned char val = 0;
4469 /* VCR (V.24 control)
4471 * 07..04 serial IF select
4478 switch(info->if_mode & MGSL_INTERFACE_MASK)
4480 case MGSL_INTERFACE_RS232:
4481 val |= BIT5; /* 0010 */
4483 case MGSL_INTERFACE_V35:
4484 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4486 case MGSL_INTERFACE_RS422:
4487 val |= BIT6; /* 0100 */
4491 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4493 if (info->signals & SerialSignal_DTR)
4495 if (info->signals & SerialSignal_RTS)
4497 if (info->if_mode & MGSL_INTERFACE_LL)
4499 if (info->if_mode & MGSL_INTERFACE_RL)
4501 wr_reg8(info, VCR, val);
4505 * set state of V24 control (output) signals
4507 static void set_gtsignals(struct slgt_info *info)
4509 unsigned char val = rd_reg8(info, VCR);
4510 if (info->signals & SerialSignal_DTR)
4514 if (info->signals & SerialSignal_RTS)
4518 wr_reg8(info, VCR, val);
4522 * free range of receive DMA buffers (i to last)
4524 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4529 /* reset current buffer for reuse */
4530 info->rbufs[i].status = 0;
4531 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4534 if (++i == info->rbuf_count)
4537 info->rbuf_current = i;
4541 * mark all receive DMA buffers as free
4543 static void reset_rbufs(struct slgt_info *info)
4545 free_rbufs(info, 0, info->rbuf_count - 1);
4546 info->rbuf_fill_index = 0;
4547 info->rbuf_fill_count = 0;
4551 * pass receive HDLC frame to upper layer
4553 * return true if frame available, otherwise false
4555 static bool rx_get_frame(struct slgt_info *info)
4557 unsigned int start, end;
4558 unsigned short status;
4559 unsigned int framesize = 0;
4560 unsigned long flags;
4561 struct tty_struct *tty = info->port.tty;
4562 unsigned char addr_field = 0xff;
4563 unsigned int crc_size = 0;
4565 switch (info->params.crc_type & HDLC_CRC_MASK) {
4566 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4567 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4574 start = end = info->rbuf_current;
4577 if (!desc_complete(info->rbufs[end]))
4580 if (framesize == 0 && info->params.addr_filter != 0xff)
4581 addr_field = info->rbufs[end].buf[0];
4583 framesize += desc_count(info->rbufs[end]);
4585 if (desc_eof(info->rbufs[end]))
4588 if (++end == info->rbuf_count)
4591 if (end == info->rbuf_current) {
4592 if (info->rx_enabled){
4593 spin_lock_irqsave(&info->lock,flags);
4595 spin_unlock_irqrestore(&info->lock,flags);
4603 * 15 buffer complete
4606 * 02 eof (end of frame)
4610 status = desc_status(info->rbufs[end]);
4612 /* ignore CRC bit if not using CRC (bit is undefined) */
4613 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4616 if (framesize == 0 ||
4617 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4618 free_rbufs(info, start, end);
4622 if (framesize < (2 + crc_size) || status & BIT0) {
4623 info->icount.rxshort++;
4625 } else if (status & BIT1) {
4626 info->icount.rxcrc++;
4627 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4631 #if SYNCLINK_GENERIC_HDLC
4632 if (framesize == 0) {
4633 info->netdev->stats.rx_errors++;
4634 info->netdev->stats.rx_frame_errors++;
4638 DBGBH(("%s rx frame status=%04X size=%d\n",
4639 info->device_name, status, framesize));
4640 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4643 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4644 framesize -= crc_size;
4648 if (framesize > info->max_frame_size + crc_size)
4649 info->icount.rxlong++;
4651 /* copy dma buffer(s) to contiguous temp buffer */
4652 int copy_count = framesize;
4654 unsigned char *p = info->tmp_rbuf;
4655 info->tmp_rbuf_count = framesize;
4657 info->icount.rxok++;
4660 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4661 memcpy(p, info->rbufs[i].buf, partial_count);
4663 copy_count -= partial_count;
4664 if (++i == info->rbuf_count)
4668 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4669 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4673 #if SYNCLINK_GENERIC_HDLC
4675 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4678 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4681 free_rbufs(info, start, end);
4689 * pass receive buffer (RAW synchronous mode) to tty layer
4690 * return true if buffer available, otherwise false
4692 static bool rx_get_buf(struct slgt_info *info)
4694 unsigned int i = info->rbuf_current;
4697 if (!desc_complete(info->rbufs[i]))
4699 count = desc_count(info->rbufs[i]);
4700 switch(info->params.mode) {
4701 case MGSL_MODE_MONOSYNC:
4702 case MGSL_MODE_BISYNC:
4703 case MGSL_MODE_XSYNC:
4704 /* ignore residue in byte synchronous modes */
4705 if (desc_residue(info->rbufs[i]))
4709 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4710 DBGINFO(("rx_get_buf size=%d\n", count));
4712 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4713 info->flag_buf, count);
4714 free_rbufs(info, i, i);
4718 static void reset_tbufs(struct slgt_info *info)
4721 info->tbuf_current = 0;
4722 for (i=0 ; i < info->tbuf_count ; i++) {
4723 info->tbufs[i].status = 0;
4724 info->tbufs[i].count = 0;
4729 * return number of free transmit DMA buffers
4731 static unsigned int free_tbuf_count(struct slgt_info *info)
4733 unsigned int count = 0;
4734 unsigned int i = info->tbuf_current;
4738 if (desc_count(info->tbufs[i]))
4739 break; /* buffer in use */
4741 if (++i == info->tbuf_count)
4743 } while (i != info->tbuf_current);
4745 /* if tx DMA active, last zero count buffer is in use */
4746 if (count && (rd_reg32(info, TDCSR) & BIT0))
4753 * return number of bytes in unsent transmit DMA buffers
4754 * and the serial controller tx FIFO
4756 static unsigned int tbuf_bytes(struct slgt_info *info)
4758 unsigned int total_count = 0;
4759 unsigned int i = info->tbuf_current;
4760 unsigned int reg_value;
4762 unsigned int active_buf_count = 0;
4765 * Add descriptor counts for all tx DMA buffers.
4766 * If count is zero (cleared by DMA controller after read),
4767 * the buffer is complete or is actively being read from.
4769 * Record buf_count of last buffer with zero count starting
4770 * from current ring position. buf_count is mirror
4771 * copy of count and is not cleared by serial controller.
4772 * If DMA controller is active, that buffer is actively
4773 * being read so add to total.
4776 count = desc_count(info->tbufs[i]);
4778 total_count += count;
4779 else if (!total_count)
4780 active_buf_count = info->tbufs[i].buf_count;
4781 if (++i == info->tbuf_count)
4783 } while (i != info->tbuf_current);
4785 /* read tx DMA status register */
4786 reg_value = rd_reg32(info, TDCSR);
4788 /* if tx DMA active, last zero count buffer is in use */
4789 if (reg_value & BIT0)
4790 total_count += active_buf_count;
4792 /* add tx FIFO count = reg_value[15..8] */
4793 total_count += (reg_value >> 8) & 0xff;
4795 /* if transmitter active add one byte for shift register */
4796 if (info->tx_active)
4803 * load data into transmit DMA buffer ring and start transmitter if needed
4804 * return true if data accepted, otherwise false (buffers full)
4806 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4808 unsigned short count;
4810 struct slgt_desc *d;
4812 /* check required buffer space */
4813 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4816 DBGDATA(info, buf, size, "tx");
4819 * copy data to one or more DMA buffers in circular ring
4820 * tbuf_start = first buffer for this data
4821 * tbuf_current = next free buffer
4823 * Copy all data before making data visible to DMA controller by
4824 * setting descriptor count of the first buffer.
4825 * This prevents an active DMA controller from reading the first DMA
4826 * buffers of a frame and stopping before the final buffers are filled.
4829 info->tbuf_start = i = info->tbuf_current;
4832 d = &info->tbufs[i];
4834 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4835 memcpy(d->buf, buf, count);
4841 * set EOF bit for last buffer of HDLC frame or
4842 * for every buffer in raw mode
4844 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4845 info->params.mode == MGSL_MODE_RAW)
4846 set_desc_eof(*d, 1);
4848 set_desc_eof(*d, 0);
4850 /* set descriptor count for all but first buffer */
4851 if (i != info->tbuf_start)
4852 set_desc_count(*d, count);
4853 d->buf_count = count;
4855 if (++i == info->tbuf_count)
4859 info->tbuf_current = i;
4861 /* set first buffer count to make new data visible to DMA controller */
4862 d = &info->tbufs[info->tbuf_start];
4863 set_desc_count(*d, d->buf_count);
4865 /* start transmitter if needed and update transmit timeout */
4866 if (!info->tx_active)
4868 update_tx_timer(info);
4873 static int register_test(struct slgt_info *info)
4875 static unsigned short patterns[] =
4876 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4877 static unsigned int count = ARRAY_SIZE(patterns);
4881 for (i=0 ; i < count ; i++) {
4882 wr_reg16(info, TIR, patterns[i]);
4883 wr_reg16(info, BDR, patterns[(i+1)%count]);
4884 if ((rd_reg16(info, TIR) != patterns[i]) ||
4885 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4890 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4891 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4895 static int irq_test(struct slgt_info *info)
4897 unsigned long timeout;
4898 unsigned long flags;
4899 struct tty_struct *oldtty = info->port.tty;
4900 u32 speed = info->params.data_rate;
4902 info->params.data_rate = 921600;
4903 info->port.tty = NULL;
4905 spin_lock_irqsave(&info->lock, flags);
4907 slgt_irq_on(info, IRQ_TXIDLE);
4909 /* enable transmitter */
4911 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4913 /* write one byte and wait for tx idle */
4914 wr_reg16(info, TDR, 0);
4916 /* assume failure */
4917 info->init_error = DiagStatus_IrqFailure;
4918 info->irq_occurred = false;
4920 spin_unlock_irqrestore(&info->lock, flags);
4923 while(timeout-- && !info->irq_occurred)
4924 msleep_interruptible(10);
4926 spin_lock_irqsave(&info->lock,flags);
4928 spin_unlock_irqrestore(&info->lock,flags);
4930 info->params.data_rate = speed;
4931 info->port.tty = oldtty;
4933 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4934 return info->irq_occurred ? 0 : -ENODEV;
4937 static int loopback_test_rx(struct slgt_info *info)
4939 unsigned char *src, *dest;
4942 if (desc_complete(info->rbufs[0])) {
4943 count = desc_count(info->rbufs[0]);
4944 src = info->rbufs[0].buf;
4945 dest = info->tmp_rbuf;
4947 for( ; count ; count-=2, src+=2) {
4948 /* src=data byte (src+1)=status byte */
4949 if (!(*(src+1) & (BIT9 + BIT8))) {
4952 info->tmp_rbuf_count++;
4955 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4961 static int loopback_test(struct slgt_info *info)
4963 #define TESTFRAMESIZE 20
4965 unsigned long timeout;
4966 u16 count = TESTFRAMESIZE;
4967 unsigned char buf[TESTFRAMESIZE];
4969 unsigned long flags;
4971 struct tty_struct *oldtty = info->port.tty;
4974 memcpy(¶ms, &info->params, sizeof(params));
4976 info->params.mode = MGSL_MODE_ASYNC;
4977 info->params.data_rate = 921600;
4978 info->params.loopback = 1;
4979 info->port.tty = NULL;
4981 /* build and send transmit frame */
4982 for (count = 0; count < TESTFRAMESIZE; ++count)
4983 buf[count] = (unsigned char)count;
4985 info->tmp_rbuf_count = 0;
4986 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4988 /* program hardware for HDLC and enabled receiver */
4989 spin_lock_irqsave(&info->lock,flags);
4992 tx_load(info, buf, count);
4993 spin_unlock_irqrestore(&info->lock, flags);
4995 /* wait for receive complete */
4996 for (timeout = 100; timeout; --timeout) {
4997 msleep_interruptible(10);
4998 if (loopback_test_rx(info)) {
5004 /* verify received frame length and contents */
5005 if (!rc && (info->tmp_rbuf_count != count ||
5006 memcmp(buf, info->tmp_rbuf, count))) {
5010 spin_lock_irqsave(&info->lock,flags);
5011 reset_adapter(info);
5012 spin_unlock_irqrestore(&info->lock,flags);
5014 memcpy(&info->params, ¶ms, sizeof(info->params));
5015 info->port.tty = oldtty;
5017 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5021 static int adapter_test(struct slgt_info *info)
5023 DBGINFO(("testing %s\n", info->device_name));
5024 if (register_test(info) < 0) {
5025 printk("register test failure %s addr=%08X\n",
5026 info->device_name, info->phys_reg_addr);
5027 } else if (irq_test(info) < 0) {
5028 printk("IRQ test failure %s IRQ=%d\n",
5029 info->device_name, info->irq_level);
5030 } else if (loopback_test(info) < 0) {
5031 printk("loopback test failure %s\n", info->device_name);
5033 return info->init_error;
5037 * transmit timeout handler
5039 static void tx_timeout(struct timer_list *t)
5041 struct slgt_info *info = from_timer(info, t, tx_timer);
5042 unsigned long flags;
5044 DBGINFO(("%s tx_timeout\n", info->device_name));
5045 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5046 info->icount.txtimeout++;
5048 spin_lock_irqsave(&info->lock,flags);
5050 spin_unlock_irqrestore(&info->lock,flags);
5052 #if SYNCLINK_GENERIC_HDLC
5054 hdlcdev_tx_done(info);
5061 * receive buffer polling timer
5063 static void rx_timeout(struct timer_list *t)
5065 struct slgt_info *info = from_timer(info, t, rx_timer);
5066 unsigned long flags;
5068 DBGINFO(("%s rx_timeout\n", info->device_name));
5069 spin_lock_irqsave(&info->lock, flags);
5070 info->pending_bh |= BH_RECEIVE;
5071 spin_unlock_irqrestore(&info->lock, flags);
5072 bh_handler(&info->task);