drivers/tty/synclink_gt.c

   1 // SPDX-License-Identifier: GPL-1.0+
   2 /*
   3  * Device driver for Microgate SyncLink GT serial adapters.
   4  *
   5  * written by Paul Fulghum for Microgate Corporation
   6  * paulkf@microgate.com
   7  *
   8  * Microgate and SyncLink are trademarks of Microgate Corporation
   9  *
  10  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  11  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  12  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  13  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  14  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  15  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  16  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  17  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  18  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  19  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  20  * OF THE POSSIBILITY OF SUCH DAMAGE.
  21  */
  22
  23 /*
  24  * DEBUG OUTPUT DEFINITIONS
  25  *
  26  * uncomment lines below to enable specific types of debug output
  27  *
  28  * DBGINFO   information - most verbose output
  29  * DBGERR    serious errors
  30  * DBGBH     bottom half service routine debugging
  31  * DBGISR    interrupt service routine debugging
  32  * DBGDATA   output receive and transmit data
  33  * DBGTBUF   output transmit DMA buffers and registers
  34  * DBGRBUF   output receive DMA buffers and registers
  35  */
  36
  37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  42 /*#define DBGTBUF(info) dump_tbufs(info)*/
  43 /*#define DBGRBUF(info) dump_rbufs(info)*/
  44
  45
  46 #include <linux/module.h>
  47 #include <linux/errno.h>
  48 #include <linux/signal.h>
  49 #include <linux/sched.h>
  50 #include <linux/timer.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/pci.h>
  53 #include <linux/tty.h>
  54 #include <linux/tty_flip.h>
  55 #include <linux/serial.h>
  56 #include <linux/major.h>
  57 #include <linux/string.h>
  58 #include <linux/fcntl.h>
  59 #include <linux/ptrace.h>
  60 #include <linux/ioport.h>
  61 #include <linux/mm.h>
  62 #include <linux/seq_file.h>
  63 #include <linux/slab.h>
  64 #include <linux/netdevice.h>
  65 #include <linux/vmalloc.h>
  66 #include <linux/init.h>
  67 #include <linux/delay.h>
  68 #include <linux/ioctl.h>
  69 #include <linux/termios.h>
  70 #include <linux/bitops.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/hdlc.h>
  73 #include <linux/synclink.h>
  74
  75 #include <asm/io.h>
  76 #include <asm/irq.h>
  77 #include <asm/dma.h>
  78 #include <asm/types.h>
  79 #include <linux/uaccess.h>
  80
  81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  82 #define SYNCLINK_GENERIC_HDLC 1
  83 #else
  84 #define SYNCLINK_GENERIC_HDLC 0
  85 #endif
  86
  87 /*
  88  * module identification
  89  */
  90 static char *driver_name     = "SyncLink GT";
  91 static char *slgt_driver_name = "synclink_gt";
  92 static char *tty_dev_prefix  = "ttySLG";
  93 MODULE_LICENSE("GPL");
  94 #define MGSL_MAGIC 0x5401
  95 #define MAX_DEVICES 32
  96
  97 static const struct pci_device_id pci_table[] = {
  98         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {0,}, /* terminate list */
 103 };
 104 MODULE_DEVICE_TABLE(pci, pci_table);
 105
 106 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 107 static void remove_one(struct pci_dev *dev);
 108 static struct pci_driver pci_driver = {
 109         .name           = "synclink_gt",
 110         .id_table       = pci_table,
 111         .probe          = init_one,
 112         .remove         = remove_one,
 113 };
 114
 115 static bool pci_registered;
 116
 117 /*
 118  * module configuration and status
 119  */
 120 static struct slgt_info *slgt_device_list;
 121 static int slgt_device_count;
 122
 123 static int ttymajor;
 124 static int debug_level;
 125 static int maxframe[MAX_DEVICES];
 126
 127 module_param(ttymajor, int, 0);
 128 module_param(debug_level, int, 0);
 129 module_param_array(maxframe, int, NULL, 0);
 130
 131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 134
 135 /*
 136  * tty support and callbacks
 137  */
 138 static struct tty_driver *serial_driver;
 139
 140 static void wait_until_sent(struct tty_struct *tty, int timeout);
 141 static void flush_buffer(struct tty_struct *tty);
 142 static void tx_release(struct tty_struct *tty);
 143
 144 /*
 145  * generic HDLC support
 146  */
 147 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 148
 149
 150 /*
 151  * device specific structures, macros and functions
 152  */
 153
 154 #define SLGT_MAX_PORTS 4
 155 #define SLGT_REG_SIZE  256
 156
 157 /*
 158  * conditional wait facility
 159  */
 160 struct cond_wait {
 161         struct cond_wait *next;
 162         wait_queue_head_t q;
 163         wait_queue_entry_t wait;
 164         unsigned int data;
 165 };
 166 static void flush_cond_wait(struct cond_wait **head);
 167
 168 /*
 169  * DMA buffer descriptor and access macros
 170  */
 171 struct slgt_desc
 172 {
 173         __le16 count;
 174         __le16 status;
 175         __le32 pbuf;  /* physical address of data buffer */
 176         __le32 next;  /* physical address of next descriptor */
 177
 178         /* driver book keeping */
 179         char *buf;          /* virtual  address of data buffer */
 180         unsigned int pdesc; /* physical address of this descriptor */
 181         dma_addr_t buf_dma_addr;
 182         unsigned short buf_count;
 183 };
 184
 185 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 186 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 187 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 188 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 189 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 190 #define desc_count(a)      (le16_to_cpu((a).count))
 191 #define desc_status(a)     (le16_to_cpu((a).status))
 192 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 193 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 194 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 195 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 196 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 197
 198 struct _input_signal_events {
 199         int ri_up;
 200         int ri_down;
 201         int dsr_up;
 202         int dsr_down;
 203         int dcd_up;
 204         int dcd_down;
 205         int cts_up;
 206         int cts_down;
 207 };
 208
 209 /*
 210  * device instance data structure
 211  */
 212 struct slgt_info {
 213         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 214         struct tty_port port;
 215
 216         struct slgt_info *next_device;  /* device list link */
 217
 218         int magic;
 219
 220         char device_name[25];
 221         struct pci_dev *pdev;
 222
 223         int port_count;  /* count of ports on adapter */
 224         int adapter_num; /* adapter instance number */
 225         int port_num;    /* port instance number */
 226
 227         /* array of pointers to port contexts on this adapter */
 228         struct slgt_info *port_array[SLGT_MAX_PORTS];
 229
 230         int                     line;           /* tty line instance number */
 231
 232         struct mgsl_icount      icount;
 233
 234         int                     timeout;
 235         int                     x_char;         /* xon/xoff character */
 236         unsigned int            read_status_mask;
 237         unsigned int            ignore_status_mask;
 238
 239         wait_queue_head_t       status_event_wait_q;
 240         wait_queue_head_t       event_wait_q;
 241         struct timer_list       tx_timer;
 242         struct timer_list       rx_timer;
 243
 244         unsigned int            gpio_present;
 245         struct cond_wait        *gpio_wait_q;
 246
 247         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 248
 249         struct work_struct task;
 250         u32 pending_bh;
 251         bool bh_requested;
 252         bool bh_running;
 253
 254         int isr_overflow;
 255         bool irq_requested;     /* true if IRQ requested */
 256         bool irq_occurred;      /* for diagnostics use */
 257
 258         /* device configuration */
 259
 260         unsigned int bus_type;
 261         unsigned int irq_level;
 262         unsigned long irq_flags;
 263
 264         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 265         u32 phys_reg_addr;
 266         bool reg_addr_requested;
 267
 268         MGSL_PARAMS params;       /* communications parameters */
 269         u32 idle_mode;
 270         u32 max_frame_size;       /* as set by device config */
 271
 272         unsigned int rbuf_fill_level;
 273         unsigned int rx_pio;
 274         unsigned int if_mode;
 275         unsigned int base_clock;
 276         unsigned int xsync;
 277         unsigned int xctrl;
 278
 279         /* device status */
 280
 281         bool rx_enabled;
 282         bool rx_restart;
 283
 284         bool tx_enabled;
 285         bool tx_active;
 286
 287         unsigned char signals;    /* serial signal states */
 288         int init_error;  /* initialization error */
 289
 290         unsigned char *tx_buf;
 291         int tx_count;
 292
 293         char *flag_buf;
 294         bool drop_rts_on_tx_done;
 295         struct  _input_signal_events    input_signal_events;
 296
 297         int dcd_chkcount;       /* check counts to prevent */
 298         int cts_chkcount;       /* too many IRQs if a signal */
 299         int dsr_chkcount;       /* is floating */
 300         int ri_chkcount;
 301
 302         char *bufs;             /* virtual address of DMA buffer lists */
 303         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 304
 305         unsigned int rbuf_count;
 306         struct slgt_desc *rbufs;
 307         unsigned int rbuf_current;
 308         unsigned int rbuf_index;
 309         unsigned int rbuf_fill_index;
 310         unsigned short rbuf_fill_count;
 311
 312         unsigned int tbuf_count;
 313         struct slgt_desc *tbufs;
 314         unsigned int tbuf_current;
 315         unsigned int tbuf_start;
 316
 317         unsigned char *tmp_rbuf;
 318         unsigned int tmp_rbuf_count;
 319
 320         /* SPPP/Cisco HDLC device parts */
 321
 322         int netcount;
 323         spinlock_t netlock;
 324 #if SYNCLINK_GENERIC_HDLC
 325         struct net_device *netdev;
 326 #endif
 327
 328 };
 329
 330 static MGSL_PARAMS default_params = {
 331         .mode            = MGSL_MODE_HDLC,
 332         .loopback        = 0,
 333         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 334         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 335         .clock_speed     = 0,
 336         .addr_filter     = 0xff,
 337         .crc_type        = HDLC_CRC_16_CCITT,
 338         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 339         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 340         .data_rate       = 9600,
 341         .data_bits       = 8,
 342         .stop_bits       = 1,
 343         .parity          = ASYNC_PARITY_NONE
 344 };
 345
 346
 347 #define BH_RECEIVE  1
 348 #define BH_TRANSMIT 2
 349 #define BH_STATUS   4
 350 #define IO_PIN_SHUTDOWN_LIMIT 100
 351
 352 #define DMABUFSIZE 256
 353 #define DESC_LIST_SIZE 4096
 354
 355 #define MASK_PARITY  BIT1
 356 #define MASK_FRAMING BIT0
 357 #define MASK_BREAK   BIT14
 358 #define MASK_OVERRUN BIT4
 359
 360 #define GSR   0x00 /* global status */
 361 #define JCR   0x04 /* JTAG control */
 362 #define IODR  0x08 /* GPIO direction */
 363 #define IOER  0x0c /* GPIO interrupt enable */
 364 #define IOVR  0x10 /* GPIO value */
 365 #define IOSR  0x14 /* GPIO interrupt status */
 366 #define TDR   0x80 /* tx data */
 367 #define RDR   0x80 /* rx data */
 368 #define TCR   0x82 /* tx control */
 369 #define TIR   0x84 /* tx idle */
 370 #define TPR   0x85 /* tx preamble */
 371 #define RCR   0x86 /* rx control */
 372 #define VCR   0x88 /* V.24 control */
 373 #define CCR   0x89 /* clock control */
 374 #define BDR   0x8a /* baud divisor */
 375 #define SCR   0x8c /* serial control */
 376 #define SSR   0x8e /* serial status */
 377 #define RDCSR 0x90 /* rx DMA control/status */
 378 #define TDCSR 0x94 /* tx DMA control/status */
 379 #define RDDAR 0x98 /* rx DMA descriptor address */
 380 #define TDDAR 0x9c /* tx DMA descriptor address */
 381 #define XSR   0x40 /* extended sync pattern */
 382 #define XCR   0x44 /* extended control */
 383
 384 #define RXIDLE      BIT14
 385 #define RXBREAK     BIT14
 386 #define IRQ_TXDATA  BIT13
 387 #define IRQ_TXIDLE  BIT12
 388 #define IRQ_TXUNDER BIT11 /* HDLC */
 389 #define IRQ_RXDATA  BIT10
 390 #define IRQ_RXIDLE  BIT9  /* HDLC */
 391 #define IRQ_RXBREAK BIT9  /* async */
 392 #define IRQ_RXOVER  BIT8
 393 #define IRQ_DSR     BIT7
 394 #define IRQ_CTS     BIT6
 395 #define IRQ_DCD     BIT5
 396 #define IRQ_RI      BIT4
 397 #define IRQ_ALL     0x3ff0
 398 #define IRQ_MASTER  BIT0
 399
 400 #define slgt_irq_on(info, mask) \
 401         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 402 #define slgt_irq_off(info, mask) \
 403         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 404
 405 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 406 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 407 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 408 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 409 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 410 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 411
 412 static void  msc_set_vcr(struct slgt_info *info);
 413
 414 static int  startup(struct slgt_info *info);
 415 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 416 static void shutdown(struct slgt_info *info);
 417 static void program_hw(struct slgt_info *info);
 418 static void change_params(struct slgt_info *info);
 419
 420 static int  adapter_test(struct slgt_info *info);
 421
 422 static void reset_port(struct slgt_info *info);
 423 static void async_mode(struct slgt_info *info);
 424 static void sync_mode(struct slgt_info *info);
 425
 426 static void rx_stop(struct slgt_info *info);
 427 static void rx_start(struct slgt_info *info);
 428 static void reset_rbufs(struct slgt_info *info);
 429 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 430 static bool rx_get_frame(struct slgt_info *info);
 431 static bool rx_get_buf(struct slgt_info *info);
 432
 433 static void tx_start(struct slgt_info *info);
 434 static void tx_stop(struct slgt_info *info);
 435 static void tx_set_idle(struct slgt_info *info);
 436 static unsigned int tbuf_bytes(struct slgt_info *info);
 437 static void reset_tbufs(struct slgt_info *info);
 438 static void tdma_reset(struct slgt_info *info);
 439 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 440
 441 static void get_gtsignals(struct slgt_info *info);
 442 static void set_gtsignals(struct slgt_info *info);
 443 static void set_rate(struct slgt_info *info, u32 data_rate);
 444
 445 static void bh_transmit(struct slgt_info *info);
 446 static void isr_txeom(struct slgt_info *info, unsigned short status);
 447
 448 static void tx_timeout(struct timer_list *t);
 449 static void rx_timeout(struct timer_list *t);
 450
 451 /*
 452  * ioctl handlers
 453  */
 454 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 455 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 456 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 457 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 458 static int  set_txidle(struct slgt_info *info, int idle_mode);
 459 static int  tx_enable(struct slgt_info *info, int enable);
 460 static int  tx_abort(struct slgt_info *info);
 461 static int  rx_enable(struct slgt_info *info, int enable);
 462 static int  modem_input_wait(struct slgt_info *info,int arg);
 463 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 464 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 465 static int  set_interface(struct slgt_info *info, int if_mode);
 466 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 467 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 468 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 469 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 470 static int  set_xsync(struct slgt_info *info, int if_mode);
 471 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 472 static int  set_xctrl(struct slgt_info *info, int if_mode);
 473
 474 /*
 475  * driver functions
 476  */
 477 static void release_resources(struct slgt_info *info);
 478
 479 /*
 480  * DEBUG OUTPUT CODE
 481  */
 482 #ifndef DBGINFO
 483 #define DBGINFO(fmt)
 484 #endif
 485 #ifndef DBGERR
 486 #define DBGERR(fmt)
 487 #endif
 488 #ifndef DBGBH
 489 #define DBGBH(fmt)
 490 #endif
 491 #ifndef DBGISR
 492 #define DBGISR(fmt)
 493 #endif
 494
 495 #ifdef DBGDATA
 496 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 497 {
 498         int i;
 499         int linecount;
 500         printk("%s %s data:\n",info->device_name, label);
 501         while(count) {
 502                 linecount = (count > 16) ? 16 : count;
 503                 for(i=0; i < linecount; i++)
 504                         printk("%02X ",(unsigned char)data[i]);
 505                 for(;i<17;i++)
 506                         printk("   ");
 507                 for(i=0;i<linecount;i++) {
 508                         if (data[i]>=040 && data[i]<=0176)
 509                                 printk("%c",data[i]);
 510                         else
 511                                 printk(".");
 512                 }
 513                 printk("\n");
 514                 data  += linecount;
 515                 count -= linecount;
 516         }
 517 }
 518 #else
 519 #define DBGDATA(info, buf, size, label)
 520 #endif
 521
 522 #ifdef DBGTBUF
 523 static void dump_tbufs(struct slgt_info *info)
 524 {
 525         int i;
 526         printk("tbuf_current=%d\n", info->tbuf_current);
 527         for (i=0 ; i < info->tbuf_count ; i++) {
 528                 printk("%d: count=%04X status=%04X\n",
 529                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 530         }
 531 }
 532 #else
 533 #define DBGTBUF(info)
 534 #endif
 535
 536 #ifdef DBGRBUF
 537 static void dump_rbufs(struct slgt_info *info)
 538 {
 539         int i;
 540         printk("rbuf_current=%d\n", info->rbuf_current);
 541         for (i=0 ; i < info->rbuf_count ; i++) {
 542                 printk("%d: count=%04X status=%04X\n",
 543                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 544         }
 545 }
 546 #else
 547 #define DBGRBUF(info)
 548 #endif
 549
 550 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 551 {
 552 #ifdef SANITY_CHECK
 553         if (!info) {
 554                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 555                 return 1;
 556         }
 557         if (info->magic != MGSL_MAGIC) {
 558                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 559                 return 1;
 560         }
 561 #else
 562         if (!info)
 563                 return 1;
 564 #endif
 565         return 0;
 566 }
 567
 568 /**
 569  * line discipline callback wrappers
 570  *
 571  * The wrappers maintain line discipline references
 572  * while calling into the line discipline.
 573  *
 574  * ldisc_receive_buf  - pass receive data to line discipline
 575  */
 576 static void ldisc_receive_buf(struct tty_struct *tty,
 577                               const __u8 *data, char *flags, int count)
 578 {
 579         struct tty_ldisc *ld;
 580         if (!tty)
 581                 return;
 582         ld = tty_ldisc_ref(tty);
 583         if (ld) {
 584                 if (ld->ops->receive_buf)
 585                         ld->ops->receive_buf(tty, data, flags, count);
 586                 tty_ldisc_deref(ld);
 587         }
 588 }
 589
 590 /* tty callbacks */
 591
 592 static int open(struct tty_struct *tty, struct file *filp)
 593 {
 594         struct slgt_info *info;
 595         int retval, line;
 596         unsigned long flags;
 597
 598         line = tty->index;
 599         if (line >= slgt_device_count) {
 600                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 601                 return -ENODEV;
 602         }
 603
 604         info = slgt_device_list;
 605         while(info && info->line != line)
 606                 info = info->next_device;
 607         if (sanity_check(info, tty->name, "open"))
 608                 return -ENODEV;
 609         if (info->init_error) {
 610                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 611                 return -ENODEV;
 612         }
 613
 614         tty->driver_data = info;
 615         info->port.tty = tty;
 616
 617         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 618
 619         mutex_lock(&info->port.mutex);
 620         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 621
 622         spin_lock_irqsave(&info->netlock, flags);
 623         if (info->netcount) {
 624                 retval = -EBUSY;
 625                 spin_unlock_irqrestore(&info->netlock, flags);
 626                 mutex_unlock(&info->port.mutex);
 627                 goto cleanup;
 628         }
 629         info->port.count++;
 630         spin_unlock_irqrestore(&info->netlock, flags);
 631
 632         if (info->port.count == 1) {
 633                 /* 1st open on this device, init hardware */
 634                 retval = startup(info);
 635                 if (retval < 0) {
 636                         mutex_unlock(&info->port.mutex);
 637                         goto cleanup;
 638                 }
 639         }
 640         mutex_unlock(&info->port.mutex);
 641         retval = block_til_ready(tty, filp, info);
 642         if (retval) {
 643                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 644                 goto cleanup;
 645         }
 646
 647         retval = 0;
 648
 649 cleanup:
 650         if (retval) {
 651                 if (tty->count == 1)
 652                         info->port.tty = NULL; /* tty layer will release tty struct */
 653                 if(info->port.count)
 654                         info->port.count--;
 655         }
 656
 657         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 658         return retval;
 659 }
 660
 661 static void close(struct tty_struct *tty, struct file *filp)
 662 {
 663         struct slgt_info *info = tty->driver_data;
 664
 665         if (sanity_check(info, tty->name, "close"))
 666                 return;
 667         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 668
 669         if (tty_port_close_start(&info->port, tty, filp) == 0)
 670                 goto cleanup;
 671
 672         mutex_lock(&info->port.mutex);
 673         if (tty_port_initialized(&info->port))
 674                 wait_until_sent(tty, info->timeout);
 675         flush_buffer(tty);
 676         tty_ldisc_flush(tty);
 677
 678         shutdown(info);
 679         mutex_unlock(&info->port.mutex);
 680
 681         tty_port_close_end(&info->port, tty);
 682         info->port.tty = NULL;
 683 cleanup:
 684         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 685 }
 686
 687 static void hangup(struct tty_struct *tty)
 688 {
 689         struct slgt_info *info = tty->driver_data;
 690         unsigned long flags;
 691
 692         if (sanity_check(info, tty->name, "hangup"))
 693                 return;
 694         DBGINFO(("%s hangup\n", info->device_name));
 695
 696         flush_buffer(tty);
 697
 698         mutex_lock(&info->port.mutex);
 699         shutdown(info);
 700
 701         spin_lock_irqsave(&info->port.lock, flags);
 702         info->port.count = 0;
 703         info->port.tty = NULL;
 704         spin_unlock_irqrestore(&info->port.lock, flags);
 705         tty_port_set_active(&info->port, 0);
 706         mutex_unlock(&info->port.mutex);
 707
 708         wake_up_interruptible(&info->port.open_wait);
 709 }
 710
 711 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 712 {
 713         struct slgt_info *info = tty->driver_data;
 714         unsigned long flags;
 715
 716         DBGINFO(("%s set_termios\n", tty->driver->name));
 717
 718         change_params(info);
 719
 720         /* Handle transition to B0 status */
 721         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 722                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 723                 spin_lock_irqsave(&info->lock,flags);
 724                 set_gtsignals(info);
 725                 spin_unlock_irqrestore(&info->lock,flags);
 726         }
 727
 728         /* Handle transition away from B0 status */
 729         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 730                 info->signals |= SerialSignal_DTR;
 731                 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 732                         info->signals |= SerialSignal_RTS;
 733                 spin_lock_irqsave(&info->lock,flags);
 734                 set_gtsignals(info);
 735                 spin_unlock_irqrestore(&info->lock,flags);
 736         }
 737
 738         /* Handle turning off CRTSCTS */
 739         if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
 740                 tty->hw_stopped = 0;
 741                 tx_release(tty);
 742         }
 743 }
 744
 745 static void update_tx_timer(struct slgt_info *info)
 746 {
 747         /*
 748          * use worst case speed of 1200bps to calculate transmit timeout
 749          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 750          */
 751         if (info->params.mode == MGSL_MODE_HDLC) {
 752                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 753                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 754         }
 755 }
 756
 757 static int write(struct tty_struct *tty,
 758                  const unsigned char *buf, int count)
 759 {
 760         int ret = 0;
 761         struct slgt_info *info = tty->driver_data;
 762         unsigned long flags;
 763
 764         if (sanity_check(info, tty->name, "write"))
 765                 return -EIO;
 766
 767         DBGINFO(("%s write count=%d\n", info->device_name, count));
 768
 769         if (!info->tx_buf || (count > info->max_frame_size))
 770                 return -EIO;
 771
 772         if (!count || tty->stopped || tty->hw_stopped)
 773                 return 0;
 774
 775         spin_lock_irqsave(&info->lock, flags);
 776
 777         if (info->tx_count) {
 778                 /* send accumulated data from send_char() */
 779                 if (!tx_load(info, info->tx_buf, info->tx_count))
 780                         goto cleanup;
 781                 info->tx_count = 0;
 782         }
 783
 784         if (tx_load(info, buf, count))
 785                 ret = count;
 786
 787 cleanup:
 788         spin_unlock_irqrestore(&info->lock, flags);
 789         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 790         return ret;
 791 }
 792
 793 static int put_char(struct tty_struct *tty, unsigned char ch)
 794 {
 795         struct slgt_info *info = tty->driver_data;
 796         unsigned long flags;
 797         int ret = 0;
 798
 799         if (sanity_check(info, tty->name, "put_char"))
 800                 return 0;
 801         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 802         if (!info->tx_buf)
 803                 return 0;
 804         spin_lock_irqsave(&info->lock,flags);
 805         if (info->tx_count < info->max_frame_size) {
 806                 info->tx_buf[info->tx_count++] = ch;
 807                 ret = 1;
 808         }
 809         spin_unlock_irqrestore(&info->lock,flags);
 810         return ret;
 811 }
 812
 813 static void send_xchar(struct tty_struct *tty, char ch)
 814 {
 815         struct slgt_info *info = tty->driver_data;
 816         unsigned long flags;
 817
 818         if (sanity_check(info, tty->name, "send_xchar"))
 819                 return;
 820         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 821         info->x_char = ch;
 822         if (ch) {
 823                 spin_lock_irqsave(&info->lock,flags);
 824                 if (!info->tx_enabled)
 825                         tx_start(info);
 826                 spin_unlock_irqrestore(&info->lock,flags);
 827         }
 828 }
 829
 830 static void wait_until_sent(struct tty_struct *tty, int timeout)
 831 {
 832         struct slgt_info *info = tty->driver_data;
 833         unsigned long orig_jiffies, char_time;
 834
 835         if (!info )
 836                 return;
 837         if (sanity_check(info, tty->name, "wait_until_sent"))
 838                 return;
 839         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 840         if (!tty_port_initialized(&info->port))
 841                 goto exit;
 842
 843         orig_jiffies = jiffies;
 844
 845         /* Set check interval to 1/5 of estimated time to
 846          * send a character, and make it at least 1. The check
 847          * interval should also be less than the timeout.
 848          * Note: use tight timings here to satisfy the NIST-PCTS.
 849          */
 850
 851         if (info->params.data_rate) {
 852                 char_time = info->timeout/(32 * 5);
 853                 if (!char_time)
 854                         char_time++;
 855         } else
 856                 char_time = 1;
 857
 858         if (timeout)
 859                 char_time = min_t(unsigned long, char_time, timeout);
 860
 861         while (info->tx_active) {
 862                 msleep_interruptible(jiffies_to_msecs(char_time));
 863                 if (signal_pending(current))
 864                         break;
 865                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 866                         break;
 867         }
 868 exit:
 869         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 870 }
 871
 872 static int write_room(struct tty_struct *tty)
 873 {
 874         struct slgt_info *info = tty->driver_data;
 875         int ret;
 876
 877         if (sanity_check(info, tty->name, "write_room"))
 878                 return 0;
 879         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 880         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 881         return ret;
 882 }
 883
 884 static void flush_chars(struct tty_struct *tty)
 885 {
 886         struct slgt_info *info = tty->driver_data;
 887         unsigned long flags;
 888
 889         if (sanity_check(info, tty->name, "flush_chars"))
 890                 return;
 891         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 892
 893         if (info->tx_count <= 0 || tty->stopped ||
 894             tty->hw_stopped || !info->tx_buf)
 895                 return;
 896
 897         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 898
 899         spin_lock_irqsave(&info->lock,flags);
 900         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 901                 info->tx_count = 0;
 902         spin_unlock_irqrestore(&info->lock,flags);
 903 }
 904
 905 static void flush_buffer(struct tty_struct *tty)
 906 {
 907         struct slgt_info *info = tty->driver_data;
 908         unsigned long flags;
 909
 910         if (sanity_check(info, tty->name, "flush_buffer"))
 911                 return;
 912         DBGINFO(("%s flush_buffer\n", info->device_name));
 913
 914         spin_lock_irqsave(&info->lock, flags);
 915         info->tx_count = 0;
 916         spin_unlock_irqrestore(&info->lock, flags);
 917
 918         tty_wakeup(tty);
 919 }
 920
 921 /*
 922  * throttle (stop) transmitter
 923  */
 924 static void tx_hold(struct tty_struct *tty)
 925 {
 926         struct slgt_info *info = tty->driver_data;
 927         unsigned long flags;
 928
 929         if (sanity_check(info, tty->name, "tx_hold"))
 930                 return;
 931         DBGINFO(("%s tx_hold\n", info->device_name));
 932         spin_lock_irqsave(&info->lock,flags);
 933         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 934                 tx_stop(info);
 935         spin_unlock_irqrestore(&info->lock,flags);
 936 }
 937
 938 /*
 939  * release (start) transmitter
 940  */
 941 static void tx_release(struct tty_struct *tty)
 942 {
 943         struct slgt_info *info = tty->driver_data;
 944         unsigned long flags;
 945
 946         if (sanity_check(info, tty->name, "tx_release"))
 947                 return;
 948         DBGINFO(("%s tx_release\n", info->device_name));
 949         spin_lock_irqsave(&info->lock, flags);
 950         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 951                 info->tx_count = 0;
 952         spin_unlock_irqrestore(&info->lock, flags);
 953 }
 954
 955 /*
 956  * Service an IOCTL request
 957  *
 958  * Arguments
 959  *
 960  *      tty     pointer to tty instance data
 961  *      cmd     IOCTL command code
 962  *      arg     command argument/context
 963  *
 964  * Return 0 if success, otherwise error code
 965  */
 966 static int ioctl(struct tty_struct *tty,
 967                  unsigned int cmd, unsigned long arg)
 968 {
 969         struct slgt_info *info = tty->driver_data;
 970         void __user *argp = (void __user *)arg;
 971         int ret;
 972
 973         if (sanity_check(info, tty->name, "ioctl"))
 974                 return -ENODEV;
 975         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
 976
 977         if (cmd != TIOCMIWAIT) {
 978                 if (tty_io_error(tty))
 979                     return -EIO;
 980         }
 981
 982         switch (cmd) {
 983         case MGSL_IOCWAITEVENT:
 984                 return wait_mgsl_event(info, argp);
 985         case TIOCMIWAIT:
 986                 return modem_input_wait(info,(int)arg);
 987         case MGSL_IOCSGPIO:
 988                 return set_gpio(info, argp);
 989         case MGSL_IOCGGPIO:
 990                 return get_gpio(info, argp);
 991         case MGSL_IOCWAITGPIO:
 992                 return wait_gpio(info, argp);
 993         case MGSL_IOCGXSYNC:
 994                 return get_xsync(info, argp);
 995         case MGSL_IOCSXSYNC:
 996                 return set_xsync(info, (int)arg);
 997         case MGSL_IOCGXCTRL:
 998                 return get_xctrl(info, argp);
 999         case MGSL_IOCSXCTRL:
1000                 return set_xctrl(info, (int)arg);
1001         }
1002         mutex_lock(&info->port.mutex);
1003         switch (cmd) {
1004         case MGSL_IOCGPARAMS:
1005                 ret = get_params(info, argp);
1006                 break;
1007         case MGSL_IOCSPARAMS:
1008                 ret = set_params(info, argp);
1009                 break;
1010         case MGSL_IOCGTXIDLE:
1011                 ret = get_txidle(info, argp);
1012                 break;
1013         case MGSL_IOCSTXIDLE:
1014                 ret = set_txidle(info, (int)arg);
1015                 break;
1016         case MGSL_IOCTXENABLE:
1017                 ret = tx_enable(info, (int)arg);
1018                 break;
1019         case MGSL_IOCRXENABLE:
1020                 ret = rx_enable(info, (int)arg);
1021                 break;
1022         case MGSL_IOCTXABORT:
1023                 ret = tx_abort(info);
1024                 break;
1025         case MGSL_IOCGSTATS:
1026                 ret = get_stats(info, argp);
1027                 break;
1028         case MGSL_IOCGIF:
1029                 ret = get_interface(info, argp);
1030                 break;
1031         case MGSL_IOCSIF:
1032                 ret = set_interface(info,(int)arg);
1033                 break;
1034         default:
1035                 ret = -ENOIOCTLCMD;
1036         }
1037         mutex_unlock(&info->port.mutex);
1038         return ret;
1039 }
1040
1041 static int get_icount(struct tty_struct *tty,
1042                                 struct serial_icounter_struct *icount)
1043
1044 {
1045         struct slgt_info *info = tty->driver_data;
1046         struct mgsl_icount cnow;        /* kernel counter temps */
1047         unsigned long flags;
1048
1049         spin_lock_irqsave(&info->lock,flags);
1050         cnow = info->icount;
1051         spin_unlock_irqrestore(&info->lock,flags);
1052
1053         icount->cts = cnow.cts;
1054         icount->dsr = cnow.dsr;
1055         icount->rng = cnow.rng;
1056         icount->dcd = cnow.dcd;
1057         icount->rx = cnow.rx;
1058         icount->tx = cnow.tx;
1059         icount->frame = cnow.frame;
1060         icount->overrun = cnow.overrun;
1061         icount->parity = cnow.parity;
1062         icount->brk = cnow.brk;
1063         icount->buf_overrun = cnow.buf_overrun;
1064
1065         return 0;
1066 }
1067
1068 /*
1069  * support for 32 bit ioctl calls on 64 bit systems
1070  */
1071 #ifdef CONFIG_COMPAT
1072 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1073 {
1074         struct MGSL_PARAMS32 tmp_params;
1075
1076         DBGINFO(("%s get_params32\n", info->device_name));
1077         memset(&tmp_params, 0, sizeof(tmp_params));
1078         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1079         tmp_params.loopback        = info->params.loopback;
1080         tmp_params.flags           = info->params.flags;
1081         tmp_params.encoding        = info->params.encoding;
1082         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1083         tmp_params.addr_filter     = info->params.addr_filter;
1084         tmp_params.crc_type        = info->params.crc_type;
1085         tmp_params.preamble_length = info->params.preamble_length;
1086         tmp_params.preamble        = info->params.preamble;
1087         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1088         tmp_params.data_bits       = info->params.data_bits;
1089         tmp_params.stop_bits       = info->params.stop_bits;
1090         tmp_params.parity          = info->params.parity;
1091         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1092                 return -EFAULT;
1093         return 0;
1094 }
1095
1096 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1097 {
1098         struct MGSL_PARAMS32 tmp_params;
1099
1100         DBGINFO(("%s set_params32\n", info->device_name));
1101         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1102                 return -EFAULT;
1103
1104         spin_lock(&info->lock);
1105         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1106                 info->base_clock = tmp_params.clock_speed;
1107         } else {
1108                 info->params.mode            = tmp_params.mode;
1109                 info->params.loopback        = tmp_params.loopback;
1110                 info->params.flags           = tmp_params.flags;
1111                 info->params.encoding        = tmp_params.encoding;
1112                 info->params.clock_speed     = tmp_params.clock_speed;
1113                 info->params.addr_filter     = tmp_params.addr_filter;
1114                 info->params.crc_type        = tmp_params.crc_type;
1115                 info->params.preamble_length = tmp_params.preamble_length;
1116                 info->params.preamble        = tmp_params.preamble;
1117                 info->params.data_rate       = tmp_params.data_rate;
1118                 info->params.data_bits       = tmp_params.data_bits;
1119                 info->params.stop_bits       = tmp_params.stop_bits;
1120                 info->params.parity          = tmp_params.parity;
1121         }
1122         spin_unlock(&info->lock);
1123
1124         program_hw(info);
1125
1126         return 0;
1127 }
1128
1129 static long slgt_compat_ioctl(struct tty_struct *tty,
1130                          unsigned int cmd, unsigned long arg)
1131 {
1132         struct slgt_info *info = tty->driver_data;
1133         int rc;
1134
1135         if (sanity_check(info, tty->name, "compat_ioctl"))
1136                 return -ENODEV;
1137         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1138
1139         switch (cmd) {
1140         case MGSL_IOCSPARAMS32:
1141                 rc = set_params32(info, compat_ptr(arg));
1142                 break;
1143
1144         case MGSL_IOCGPARAMS32:
1145                 rc = get_params32(info, compat_ptr(arg));
1146                 break;
1147
1148         case MGSL_IOCGPARAMS:
1149         case MGSL_IOCSPARAMS:
1150         case MGSL_IOCGTXIDLE:
1151         case MGSL_IOCGSTATS:
1152         case MGSL_IOCWAITEVENT:
1153         case MGSL_IOCGIF:
1154         case MGSL_IOCSGPIO:
1155         case MGSL_IOCGGPIO:
1156         case MGSL_IOCWAITGPIO:
1157         case MGSL_IOCGXSYNC:
1158         case MGSL_IOCGXCTRL:
1159                 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1160                 break;
1161         default:
1162                 rc = ioctl(tty, cmd, arg);
1163         }
1164         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1165         return rc;
1166 }
1167 #else
1168 #define slgt_compat_ioctl NULL
1169 #endif /* ifdef CONFIG_COMPAT */
1170
1171 /*
1172  * proc fs support
1173  */
1174 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1175 {
1176         char stat_buf[30];
1177         unsigned long flags;
1178
1179         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1180                       info->device_name, info->phys_reg_addr,
1181                       info->irq_level, info->max_frame_size);
1182
1183         /* output current serial signal states */
1184         spin_lock_irqsave(&info->lock,flags);
1185         get_gtsignals(info);
1186         spin_unlock_irqrestore(&info->lock,flags);
1187
1188         stat_buf[0] = 0;
1189         stat_buf[1] = 0;
1190         if (info->signals & SerialSignal_RTS)
1191                 strcat(stat_buf, "|RTS");
1192         if (info->signals & SerialSignal_CTS)
1193                 strcat(stat_buf, "|CTS");
1194         if (info->signals & SerialSignal_DTR)
1195                 strcat(stat_buf, "|DTR");
1196         if (info->signals & SerialSignal_DSR)
1197                 strcat(stat_buf, "|DSR");
1198         if (info->signals & SerialSignal_DCD)
1199                 strcat(stat_buf, "|CD");
1200         if (info->signals & SerialSignal_RI)
1201                 strcat(stat_buf, "|RI");
1202
1203         if (info->params.mode != MGSL_MODE_ASYNC) {
1204                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1205                                info->icount.txok, info->icount.rxok);
1206                 if (info->icount.txunder)
1207                         seq_printf(m, " txunder:%d", info->icount.txunder);
1208                 if (info->icount.txabort)
1209                         seq_printf(m, " txabort:%d", info->icount.txabort);
1210                 if (info->icount.rxshort)
1211                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1212                 if (info->icount.rxlong)
1213                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1214                 if (info->icount.rxover)
1215                         seq_printf(m, " rxover:%d", info->icount.rxover);
1216                 if (info->icount.rxcrc)
1217                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1218         } else {
1219                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1220                                info->icount.tx, info->icount.rx);
1221                 if (info->icount.frame)
1222                         seq_printf(m, " fe:%d", info->icount.frame);
1223                 if (info->icount.parity)
1224                         seq_printf(m, " pe:%d", info->icount.parity);
1225                 if (info->icount.brk)
1226                         seq_printf(m, " brk:%d", info->icount.brk);
1227                 if (info->icount.overrun)
1228                         seq_printf(m, " oe:%d", info->icount.overrun);
1229         }
1230
1231         /* Append serial signal status to end */
1232         seq_printf(m, " %s\n", stat_buf+1);
1233
1234         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1235                        info->tx_active,info->bh_requested,info->bh_running,
1236                        info->pending_bh);
1237 }
1238
1239 /* Called to print information about devices
1240  */
1241 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1242 {
1243         struct slgt_info *info;
1244
1245         seq_puts(m, "synclink_gt driver\n");
1246
1247         info = slgt_device_list;
1248         while( info ) {
1249                 line_info(m, info);
1250                 info = info->next_device;
1251         }
1252         return 0;
1253 }
1254
1255 /*
1256  * return count of bytes in transmit buffer
1257  */
1258 static int chars_in_buffer(struct tty_struct *tty)
1259 {
1260         struct slgt_info *info = tty->driver_data;
1261         int count;
1262         if (sanity_check(info, tty->name, "chars_in_buffer"))
1263                 return 0;
1264         count = tbuf_bytes(info);
1265         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1266         return count;
1267 }
1268
1269 /*
1270  * signal remote device to throttle send data (our receive data)
1271  */
1272 static void throttle(struct tty_struct * tty)
1273 {
1274         struct slgt_info *info = tty->driver_data;
1275         unsigned long flags;
1276
1277         if (sanity_check(info, tty->name, "throttle"))
1278                 return;
1279         DBGINFO(("%s throttle\n", info->device_name));
1280         if (I_IXOFF(tty))
1281                 send_xchar(tty, STOP_CHAR(tty));
1282         if (C_CRTSCTS(tty)) {
1283                 spin_lock_irqsave(&info->lock,flags);
1284                 info->signals &= ~SerialSignal_RTS;
1285                 set_gtsignals(info);
1286                 spin_unlock_irqrestore(&info->lock,flags);
1287         }
1288 }
1289
1290 /*
1291  * signal remote device to stop throttling send data (our receive data)
1292  */
1293 static void unthrottle(struct tty_struct * tty)
1294 {
1295         struct slgt_info *info = tty->driver_data;
1296         unsigned long flags;
1297
1298         if (sanity_check(info, tty->name, "unthrottle"))
1299                 return;
1300         DBGINFO(("%s unthrottle\n", info->device_name));
1301         if (I_IXOFF(tty)) {
1302                 if (info->x_char)
1303                         info->x_char = 0;
1304                 else
1305                         send_xchar(tty, START_CHAR(tty));
1306         }
1307         if (C_CRTSCTS(tty)) {
1308                 spin_lock_irqsave(&info->lock,flags);
1309                 info->signals |= SerialSignal_RTS;
1310                 set_gtsignals(info);
1311                 spin_unlock_irqrestore(&info->lock,flags);
1312         }
1313 }
1314
1315 /*
1316  * set or clear transmit break condition
1317  * break_state  -1=set break condition, 0=clear
1318  */
1319 static int set_break(struct tty_struct *tty, int break_state)
1320 {
1321         struct slgt_info *info = tty->driver_data;
1322         unsigned short value;
1323         unsigned long flags;
1324
1325         if (sanity_check(info, tty->name, "set_break"))
1326                 return -EINVAL;
1327         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1328
1329         spin_lock_irqsave(&info->lock,flags);
1330         value = rd_reg16(info, TCR);
1331         if (break_state == -1)
1332                 value |= BIT6;
1333         else
1334                 value &= ~BIT6;
1335         wr_reg16(info, TCR, value);
1336         spin_unlock_irqrestore(&info->lock,flags);
1337         return 0;
1338 }
1339
1340 #if SYNCLINK_GENERIC_HDLC
1341
1342 /**
1343  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1344  * set encoding and frame check sequence (FCS) options
1345  *
1346  * dev       pointer to network device structure
1347  * encoding  serial encoding setting
1348  * parity    FCS setting
1349  *
1350  * returns 0 if success, otherwise error code
1351  */
1352 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1353                           unsigned short parity)
1354 {
1355         struct slgt_info *info = dev_to_port(dev);
1356         unsigned char  new_encoding;
1357         unsigned short new_crctype;
1358
1359         /* return error if TTY interface open */
1360         if (info->port.count)
1361                 return -EBUSY;
1362
1363         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1364
1365         switch (encoding)
1366         {
1367         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1368         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1369         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1370         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1371         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1372         default: return -EINVAL;
1373         }
1374
1375         switch (parity)
1376         {
1377         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1378         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1379         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1380         default: return -EINVAL;
1381         }
1382
1383         info->params.encoding = new_encoding;
1384         info->params.crc_type = new_crctype;
1385
1386         /* if network interface up, reprogram hardware */
1387         if (info->netcount)
1388                 program_hw(info);
1389
1390         return 0;
1391 }
1392
1393 /**
1394  * called by generic HDLC layer to send frame
1395  *
1396  * skb  socket buffer containing HDLC frame
1397  * dev  pointer to network device structure
1398  */
1399 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1400                                       struct net_device *dev)
1401 {
1402         struct slgt_info *info = dev_to_port(dev);
1403         unsigned long flags;
1404
1405         DBGINFO(("%s hdlc_xmit\n", dev->name));
1406
1407         if (!skb->len)
1408                 return NETDEV_TX_OK;
1409
1410         /* stop sending until this frame completes */
1411         netif_stop_queue(dev);
1412
1413         /* update network statistics */
1414         dev->stats.tx_packets++;
1415         dev->stats.tx_bytes += skb->len;
1416
1417         /* save start time for transmit timeout detection */
1418         netif_trans_update(dev);
1419
1420         spin_lock_irqsave(&info->lock, flags);
1421         tx_load(info, skb->data, skb->len);
1422         spin_unlock_irqrestore(&info->lock, flags);
1423
1424         /* done with socket buffer, so free it */
1425         dev_kfree_skb(skb);
1426
1427         return NETDEV_TX_OK;
1428 }
1429
1430 /**
1431  * called by network layer when interface enabled
1432  * claim resources and initialize hardware
1433  *
1434  * dev  pointer to network device structure
1435  *
1436  * returns 0 if success, otherwise error code
1437  */
1438 static int hdlcdev_open(struct net_device *dev)
1439 {
1440         struct slgt_info *info = dev_to_port(dev);
1441         int rc;
1442         unsigned long flags;
1443
1444         if (!try_module_get(THIS_MODULE))
1445                 return -EBUSY;
1446
1447         DBGINFO(("%s hdlcdev_open\n", dev->name));
1448
1449         /* generic HDLC layer open processing */
1450         rc = hdlc_open(dev);
1451         if (rc)
1452                 return rc;
1453
1454         /* arbitrate between network and tty opens */
1455         spin_lock_irqsave(&info->netlock, flags);
1456         if (info->port.count != 0 || info->netcount != 0) {
1457                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1458                 spin_unlock_irqrestore(&info->netlock, flags);
1459                 return -EBUSY;
1460         }
1461         info->netcount=1;
1462         spin_unlock_irqrestore(&info->netlock, flags);
1463
1464         /* claim resources and init adapter */
1465         if ((rc = startup(info)) != 0) {
1466                 spin_lock_irqsave(&info->netlock, flags);
1467                 info->netcount=0;
1468                 spin_unlock_irqrestore(&info->netlock, flags);
1469                 return rc;
1470         }
1471
1472         /* assert RTS and DTR, apply hardware settings */
1473         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1474         program_hw(info);
1475
1476         /* enable network layer transmit */
1477         netif_trans_update(dev);
1478         netif_start_queue(dev);
1479
1480         /* inform generic HDLC layer of current DCD status */
1481         spin_lock_irqsave(&info->lock, flags);
1482         get_gtsignals(info);
1483         spin_unlock_irqrestore(&info->lock, flags);
1484         if (info->signals & SerialSignal_DCD)
1485                 netif_carrier_on(dev);
1486         else
1487                 netif_carrier_off(dev);
1488         return 0;
1489 }
1490
1491 /**
1492  * called by network layer when interface is disabled
1493  * shutdown hardware and release resources
1494  *
1495  * dev  pointer to network device structure
1496  *
1497  * returns 0 if success, otherwise error code
1498  */
1499 static int hdlcdev_close(struct net_device *dev)
1500 {
1501         struct slgt_info *info = dev_to_port(dev);
1502         unsigned long flags;
1503
1504         DBGINFO(("%s hdlcdev_close\n", dev->name));
1505
1506         netif_stop_queue(dev);
1507
1508         /* shutdown adapter and release resources */
1509         shutdown(info);
1510
1511         hdlc_close(dev);
1512
1513         spin_lock_irqsave(&info->netlock, flags);
1514         info->netcount=0;
1515         spin_unlock_irqrestore(&info->netlock, flags);
1516
1517         module_put(THIS_MODULE);
1518         return 0;
1519 }
1520
1521 /**
1522  * called by network layer to process IOCTL call to network device
1523  *
1524  * dev  pointer to network device structure
1525  * ifr  pointer to network interface request structure
1526  * cmd  IOCTL command code
1527  *
1528  * returns 0 if success, otherwise error code
1529  */
1530 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1531 {
1532         const size_t size = sizeof(sync_serial_settings);
1533         sync_serial_settings new_line;
1534         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1535         struct slgt_info *info = dev_to_port(dev);
1536         unsigned int flags;
1537
1538         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1539
1540         /* return error if TTY interface open */
1541         if (info->port.count)
1542                 return -EBUSY;
1543
1544         if (cmd != SIOCWANDEV)
1545                 return hdlc_ioctl(dev, ifr, cmd);
1546
1547         memset(&new_line, 0, sizeof(new_line));
1548
1549         switch(ifr->ifr_settings.type) {
1550         case IF_GET_IFACE: /* return current sync_serial_settings */
1551
1552                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1553                 if (ifr->ifr_settings.size < size) {
1554                         ifr->ifr_settings.size = size; /* data size wanted */
1555                         return -ENOBUFS;
1556                 }
1557
1558                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1559                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1560                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1561                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1562
1563                 switch (flags){
1564                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1565                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1566                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1567                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1568                 default: new_line.clock_type = CLOCK_DEFAULT;
1569                 }
1570
1571                 new_line.clock_rate = info->params.clock_speed;
1572                 new_line.loopback   = info->params.loopback ? 1:0;
1573
1574                 if (copy_to_user(line, &new_line, size))
1575                         return -EFAULT;
1576                 return 0;
1577
1578         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1579
1580                 if(!capable(CAP_NET_ADMIN))
1581                         return -EPERM;
1582                 if (copy_from_user(&new_line, line, size))
1583                         return -EFAULT;
1584
1585                 switch (new_line.clock_type)
1586                 {
1587                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1588                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1589                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1590                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1591                 case CLOCK_DEFAULT:  flags = info->params.flags &
1592                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1593                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1594                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1595                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1596                 default: return -EINVAL;
1597                 }
1598
1599                 if (new_line.loopback != 0 && new_line.loopback != 1)
1600                         return -EINVAL;
1601
1602                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1603                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1604                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1605                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1606                 info->params.flags |= flags;
1607
1608                 info->params.loopback = new_line.loopback;
1609
1610                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1611                         info->params.clock_speed = new_line.clock_rate;
1612                 else
1613                         info->params.clock_speed = 0;
1614
1615                 /* if network interface up, reprogram hardware */
1616                 if (info->netcount)
1617                         program_hw(info);
1618                 return 0;
1619
1620         default:
1621                 return hdlc_ioctl(dev, ifr, cmd);
1622         }
1623 }
1624
1625 /**
1626  * called by network layer when transmit timeout is detected
1627  *
1628  * dev  pointer to network device structure
1629  */
1630 static void hdlcdev_tx_timeout(struct net_device *dev)
1631 {
1632         struct slgt_info *info = dev_to_port(dev);
1633         unsigned long flags;
1634
1635         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1636
1637         dev->stats.tx_errors++;
1638         dev->stats.tx_aborted_errors++;
1639
1640         spin_lock_irqsave(&info->lock,flags);
1641         tx_stop(info);
1642         spin_unlock_irqrestore(&info->lock,flags);
1643
1644         netif_wake_queue(dev);
1645 }
1646
1647 /**
1648  * called by device driver when transmit completes
1649  * reenable network layer transmit if stopped
1650  *
1651  * info  pointer to device instance information
1652  */
1653 static void hdlcdev_tx_done(struct slgt_info *info)
1654 {
1655         if (netif_queue_stopped(info->netdev))
1656                 netif_wake_queue(info->netdev);
1657 }
1658
1659 /**
1660  * called by device driver when frame received
1661  * pass frame to network layer
1662  *
1663  * info  pointer to device instance information
1664  * buf   pointer to buffer contianing frame data
1665  * size  count of data bytes in buf
1666  */
1667 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1668 {
1669         struct sk_buff *skb = dev_alloc_skb(size);
1670         struct net_device *dev = info->netdev;
1671
1672         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1673
1674         if (skb == NULL) {
1675                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1676                 dev->stats.rx_dropped++;
1677                 return;
1678         }
1679
1680         skb_put_data(skb, buf, size);
1681
1682         skb->protocol = hdlc_type_trans(skb, dev);
1683
1684         dev->stats.rx_packets++;
1685         dev->stats.rx_bytes += size;
1686
1687         netif_rx(skb);
1688 }
1689
1690 static const struct net_device_ops hdlcdev_ops = {
1691         .ndo_open       = hdlcdev_open,
1692         .ndo_stop       = hdlcdev_close,
1693         .ndo_start_xmit = hdlc_start_xmit,
1694         .ndo_do_ioctl   = hdlcdev_ioctl,
1695         .ndo_tx_timeout = hdlcdev_tx_timeout,
1696 };
1697
1698 /**
1699  * called by device driver when adding device instance
1700  * do generic HDLC initialization
1701  *
1702  * info  pointer to device instance information
1703  *
1704  * returns 0 if success, otherwise error code
1705  */
1706 static int hdlcdev_init(struct slgt_info *info)
1707 {
1708         int rc;
1709         struct net_device *dev;
1710         hdlc_device *hdlc;
1711
1712         /* allocate and initialize network and HDLC layer objects */
1713
1714         dev = alloc_hdlcdev(info);
1715         if (!dev) {
1716                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1717                 return -ENOMEM;
1718         }
1719
1720         /* for network layer reporting purposes only */
1721         dev->mem_start = info->phys_reg_addr;
1722         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1723         dev->irq       = info->irq_level;
1724
1725         /* network layer callbacks and settings */
1726         dev->netdev_ops     = &hdlcdev_ops;
1727         dev->watchdog_timeo = 10 * HZ;
1728         dev->tx_queue_len   = 50;
1729
1730         /* generic HDLC layer callbacks and settings */
1731         hdlc         = dev_to_hdlc(dev);
1732         hdlc->attach = hdlcdev_attach;
1733         hdlc->xmit   = hdlcdev_xmit;
1734
1735         /* register objects with HDLC layer */
1736         rc = register_hdlc_device(dev);
1737         if (rc) {
1738                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1739                 free_netdev(dev);
1740                 return rc;
1741         }
1742
1743         info->netdev = dev;
1744         return 0;
1745 }
1746
1747 /**
1748  * called by device driver when removing device instance
1749  * do generic HDLC cleanup
1750  *
1751  * info  pointer to device instance information
1752  */
1753 static void hdlcdev_exit(struct slgt_info *info)
1754 {
1755         if (!info->netdev)
1756                 return;
1757         unregister_hdlc_device(info->netdev);
1758         free_netdev(info->netdev);
1759         info->netdev = NULL;
1760 }
1761
1762 #endif /* ifdef CONFIG_HDLC */
1763
1764 /*
1765  * get async data from rx DMA buffers
1766  */
1767 static void rx_async(struct slgt_info *info)
1768 {
1769         struct mgsl_icount *icount = &info->icount;
1770         unsigned int start, end;
1771         unsigned char *p;
1772         unsigned char status;
1773         struct slgt_desc *bufs = info->rbufs;
1774         int i, count;
1775         int chars = 0;
1776         int stat;
1777         unsigned char ch;
1778
1779         start = end = info->rbuf_current;
1780
1781         while(desc_complete(bufs[end])) {
1782                 count = desc_count(bufs[end]) - info->rbuf_index;
1783                 p     = bufs[end].buf + info->rbuf_index;
1784
1785                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1786                 DBGDATA(info, p, count, "rx");
1787
1788                 for(i=0 ; i < count; i+=2, p+=2) {
1789                         ch = *p;
1790                         icount->rx++;
1791
1792                         stat = 0;
1793
1794                         status = *(p + 1) & (BIT1 + BIT0);
1795                         if (status) {
1796                                 if (status & BIT1)
1797                                         icount->parity++;
1798                                 else if (status & BIT0)
1799                                         icount->frame++;
1800                                 /* discard char if tty control flags say so */
1801                                 if (status & info->ignore_status_mask)
1802                                         continue;
1803                                 if (status & BIT1)
1804                                         stat = TTY_PARITY;
1805                                 else if (status & BIT0)
1806                                         stat = TTY_FRAME;
1807                         }
1808                         tty_insert_flip_char(&info->port, ch, stat);
1809                         chars++;
1810                 }
1811
1812                 if (i < count) {
1813                         /* receive buffer not completed */
1814                         info->rbuf_index += i;
1815                         mod_timer(&info->rx_timer, jiffies + 1);
1816                         break;
1817                 }
1818
1819                 info->rbuf_index = 0;
1820                 free_rbufs(info, end, end);
1821
1822                 if (++end == info->rbuf_count)
1823                         end = 0;
1824
1825                 /* if entire list searched then no frame available */
1826                 if (end == start)
1827                         break;
1828         }
1829
1830         if (chars)
1831                 tty_flip_buffer_push(&info->port);
1832 }
1833
1834 /*
1835  * return next bottom half action to perform
1836  */
1837 static int bh_action(struct slgt_info *info)
1838 {
1839         unsigned long flags;
1840         int rc;
1841
1842         spin_lock_irqsave(&info->lock,flags);
1843
1844         if (info->pending_bh & BH_RECEIVE) {
1845                 info->pending_bh &= ~BH_RECEIVE;
1846                 rc = BH_RECEIVE;
1847         } else if (info->pending_bh & BH_TRANSMIT) {
1848                 info->pending_bh &= ~BH_TRANSMIT;
1849                 rc = BH_TRANSMIT;
1850         } else if (info->pending_bh & BH_STATUS) {
1851                 info->pending_bh &= ~BH_STATUS;
1852                 rc = BH_STATUS;
1853         } else {
1854                 /* Mark BH routine as complete */
1855                 info->bh_running = false;
1856                 info->bh_requested = false;
1857                 rc = 0;
1858         }
1859
1860         spin_unlock_irqrestore(&info->lock,flags);
1861
1862         return rc;
1863 }
1864
1865 /*
1866  * perform bottom half processing
1867  */
1868 static void bh_handler(struct work_struct *work)
1869 {
1870         struct slgt_info *info = container_of(work, struct slgt_info, task);
1871         int action;
1872
1873         info->bh_running = true;
1874
1875         while((action = bh_action(info))) {
1876                 switch (action) {
1877                 case BH_RECEIVE:
1878                         DBGBH(("%s bh receive\n", info->device_name));
1879                         switch(info->params.mode) {
1880                         case MGSL_MODE_ASYNC:
1881                                 rx_async(info);
1882                                 break;
1883                         case MGSL_MODE_HDLC:
1884                                 while(rx_get_frame(info));
1885                                 break;
1886                         case MGSL_MODE_RAW:
1887                         case MGSL_MODE_MONOSYNC:
1888                         case MGSL_MODE_BISYNC:
1889                         case MGSL_MODE_XSYNC:
1890                                 while(rx_get_buf(info));
1891                                 break;
1892                         }
1893                         /* restart receiver if rx DMA buffers exhausted */
1894                         if (info->rx_restart)
1895                                 rx_start(info);
1896                         break;
1897                 case BH_TRANSMIT:
1898                         bh_transmit(info);
1899                         break;
1900                 case BH_STATUS:
1901                         DBGBH(("%s bh status\n", info->device_name));
1902                         info->ri_chkcount = 0;
1903                         info->dsr_chkcount = 0;
1904                         info->dcd_chkcount = 0;
1905                         info->cts_chkcount = 0;
1906                         break;
1907                 default:
1908                         DBGBH(("%s unknown action\n", info->device_name));
1909                         break;
1910                 }
1911         }
1912         DBGBH(("%s bh_handler exit\n", info->device_name));
1913 }
1914
1915 static void bh_transmit(struct slgt_info *info)
1916 {
1917         struct tty_struct *tty = info->port.tty;
1918
1919         DBGBH(("%s bh_transmit\n", info->device_name));
1920         if (tty)
1921                 tty_wakeup(tty);
1922 }
1923
1924 static void dsr_change(struct slgt_info *info, unsigned short status)
1925 {
1926         if (status & BIT3) {
1927                 info->signals |= SerialSignal_DSR;
1928                 info->input_signal_events.dsr_up++;
1929         } else {
1930                 info->signals &= ~SerialSignal_DSR;
1931                 info->input_signal_events.dsr_down++;
1932         }
1933         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1934         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1935                 slgt_irq_off(info, IRQ_DSR);
1936                 return;
1937         }
1938         info->icount.dsr++;
1939         wake_up_interruptible(&info->status_event_wait_q);
1940         wake_up_interruptible(&info->event_wait_q);
1941         info->pending_bh |= BH_STATUS;
1942 }
1943
1944 static void cts_change(struct slgt_info *info, unsigned short status)
1945 {
1946         if (status & BIT2) {
1947                 info->signals |= SerialSignal_CTS;
1948                 info->input_signal_events.cts_up++;
1949         } else {
1950                 info->signals &= ~SerialSignal_CTS;
1951                 info->input_signal_events.cts_down++;
1952         }
1953         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1954         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1955                 slgt_irq_off(info, IRQ_CTS);
1956                 return;
1957         }
1958         info->icount.cts++;
1959         wake_up_interruptible(&info->status_event_wait_q);
1960         wake_up_interruptible(&info->event_wait_q);
1961         info->pending_bh |= BH_STATUS;
1962
1963         if (tty_port_cts_enabled(&info->port)) {
1964                 if (info->port.tty) {
1965                         if (info->port.tty->hw_stopped) {
1966                                 if (info->signals & SerialSignal_CTS) {
1967                                         info->port.tty->hw_stopped = 0;
1968                                         info->pending_bh |= BH_TRANSMIT;
1969                                         return;
1970                                 }
1971                         } else {
1972                                 if (!(info->signals & SerialSignal_CTS))
1973                                         info->port.tty->hw_stopped = 1;
1974                         }
1975                 }
1976         }
1977 }
1978
1979 static void dcd_change(struct slgt_info *info, unsigned short status)
1980 {
1981         if (status & BIT1) {
1982                 info->signals |= SerialSignal_DCD;
1983                 info->input_signal_events.dcd_up++;
1984         } else {
1985                 info->signals &= ~SerialSignal_DCD;
1986                 info->input_signal_events.dcd_down++;
1987         }
1988         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1989         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1990                 slgt_irq_off(info, IRQ_DCD);
1991                 return;
1992         }
1993         info->icount.dcd++;
1994 #if SYNCLINK_GENERIC_HDLC
1995         if (info->netcount) {
1996                 if (info->signals & SerialSignal_DCD)
1997                         netif_carrier_on(info->netdev);
1998                 else
1999                         netif_carrier_off(info->netdev);
2000         }
2001 #endif
2002         wake_up_interruptible(&info->status_event_wait_q);
2003         wake_up_interruptible(&info->event_wait_q);
2004         info->pending_bh |= BH_STATUS;
2005
2006         if (tty_port_check_carrier(&info->port)) {
2007                 if (info->signals & SerialSignal_DCD)
2008                         wake_up_interruptible(&info->port.open_wait);
2009                 else {
2010                         if (info->port.tty)
2011                                 tty_hangup(info->port.tty);
2012                 }
2013         }
2014 }
2015
2016 static void ri_change(struct slgt_info *info, unsigned short status)
2017 {
2018         if (status & BIT0) {
2019                 info->signals |= SerialSignal_RI;
2020                 info->input_signal_events.ri_up++;
2021         } else {
2022                 info->signals &= ~SerialSignal_RI;
2023                 info->input_signal_events.ri_down++;
2024         }
2025         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2026         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2027                 slgt_irq_off(info, IRQ_RI);
2028                 return;
2029         }
2030         info->icount.rng++;
2031         wake_up_interruptible(&info->status_event_wait_q);
2032         wake_up_interruptible(&info->event_wait_q);
2033         info->pending_bh |= BH_STATUS;
2034 }
2035
2036 static void isr_rxdata(struct slgt_info *info)
2037 {
2038         unsigned int count = info->rbuf_fill_count;
2039         unsigned int i = info->rbuf_fill_index;
2040         unsigned short reg;
2041
2042         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2043                 reg = rd_reg16(info, RDR);
2044                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2045                 if (desc_complete(info->rbufs[i])) {
2046                         /* all buffers full */
2047                         rx_stop(info);
2048                         info->rx_restart = 1;
2049                         continue;
2050                 }
2051                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2052                 /* async mode saves status byte to buffer for each data byte */
2053                 if (info->params.mode == MGSL_MODE_ASYNC)
2054                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2055                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2056                         /* buffer full or end of frame */
2057                         set_desc_count(info->rbufs[i], count);
2058                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2059                         info->rbuf_fill_count = count = 0;
2060                         if (++i == info->rbuf_count)
2061                                 i = 0;
2062                         info->pending_bh |= BH_RECEIVE;
2063                 }
2064         }
2065
2066         info->rbuf_fill_index = i;
2067         info->rbuf_fill_count = count;
2068 }
2069
2070 static void isr_serial(struct slgt_info *info)
2071 {
2072         unsigned short status = rd_reg16(info, SSR);
2073
2074         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2075
2076         wr_reg16(info, SSR, status); /* clear pending */
2077
2078         info->irq_occurred = true;
2079
2080         if (info->params.mode == MGSL_MODE_ASYNC) {
2081                 if (status & IRQ_TXIDLE) {
2082                         if (info->tx_active)
2083                                 isr_txeom(info, status);
2084                 }
2085                 if (info->rx_pio && (status & IRQ_RXDATA))
2086                         isr_rxdata(info);
2087                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2088                         info->icount.brk++;
2089                         /* process break detection if tty control allows */
2090                         if (info->port.tty) {
2091                                 if (!(status & info->ignore_status_mask)) {
2092                                         if (info->read_status_mask & MASK_BREAK) {
2093                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2094                                                 if (info->port.flags & ASYNC_SAK)
2095                                                         do_SAK(info->port.tty);
2096                                         }
2097                                 }
2098                         }
2099                 }
2100         } else {
2101                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2102                         isr_txeom(info, status);
2103                 if (info->rx_pio && (status & IRQ_RXDATA))
2104                         isr_rxdata(info);
2105                 if (status & IRQ_RXIDLE) {
2106                         if (status & RXIDLE)
2107                                 info->icount.rxidle++;
2108                         else
2109                                 info->icount.exithunt++;
2110                         wake_up_interruptible(&info->event_wait_q);
2111                 }
2112
2113                 if (status & IRQ_RXOVER)
2114                         rx_start(info);
2115         }
2116
2117         if (status & IRQ_DSR)
2118                 dsr_change(info, status);
2119         if (status & IRQ_CTS)
2120                 cts_change(info, status);
2121         if (status & IRQ_DCD)
2122                 dcd_change(info, status);
2123         if (status & IRQ_RI)
2124                 ri_change(info, status);
2125 }
2126
2127 static void isr_rdma(struct slgt_info *info)
2128 {
2129         unsigned int status = rd_reg32(info, RDCSR);
2130
2131         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2132
2133         /* RDCSR (rx DMA control/status)
2134          *
2135          * 31..07  reserved
2136          * 06      save status byte to DMA buffer
2137          * 05      error
2138          * 04      eol (end of list)
2139          * 03      eob (end of buffer)
2140          * 02      IRQ enable
2141          * 01      reset
2142          * 00      enable
2143          */
2144         wr_reg32(info, RDCSR, status);  /* clear pending */
2145
2146         if (status & (BIT5 + BIT4)) {
2147                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2148                 info->rx_restart = true;
2149         }
2150         info->pending_bh |= BH_RECEIVE;
2151 }
2152
2153 static void isr_tdma(struct slgt_info *info)
2154 {
2155         unsigned int status = rd_reg32(info, TDCSR);
2156
2157         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2158
2159         /* TDCSR (tx DMA control/status)
2160          *
2161          * 31..06  reserved
2162          * 05      error
2163          * 04      eol (end of list)
2164          * 03      eob (end of buffer)
2165          * 02      IRQ enable
2166          * 01      reset
2167          * 00      enable
2168          */
2169         wr_reg32(info, TDCSR, status);  /* clear pending */
2170
2171         if (status & (BIT5 + BIT4 + BIT3)) {
2172                 // another transmit buffer has completed
2173                 // run bottom half to get more send data from user
2174                 info->pending_bh |= BH_TRANSMIT;
2175         }
2176 }
2177
2178 /*
2179  * return true if there are unsent tx DMA buffers, otherwise false
2180  *
2181  * if there are unsent buffers then info->tbuf_start
2182  * is set to index of first unsent buffer
2183  */
2184 static bool unsent_tbufs(struct slgt_info *info)
2185 {
2186         unsigned int i = info->tbuf_current;
2187         bool rc = false;
2188
2189         /*
2190          * search backwards from last loaded buffer (precedes tbuf_current)
2191          * for first unsent buffer (desc_count > 0)
2192          */
2193
2194         do {
2195                 if (i)
2196                         i--;
2197                 else
2198                         i = info->tbuf_count - 1;
2199                 if (!desc_count(info->tbufs[i]))
2200                         break;
2201                 info->tbuf_start = i;
2202                 rc = true;
2203         } while (i != info->tbuf_current);
2204
2205         return rc;
2206 }
2207
2208 static void isr_txeom(struct slgt_info *info, unsigned short status)
2209 {
2210         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2211
2212         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2213         tdma_reset(info);
2214         if (status & IRQ_TXUNDER) {
2215                 unsigned short val = rd_reg16(info, TCR);
2216                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2217                 wr_reg16(info, TCR, val); /* clear reset bit */
2218         }
2219
2220         if (info->tx_active) {
2221                 if (info->params.mode != MGSL_MODE_ASYNC) {
2222                         if (status & IRQ_TXUNDER)
2223                                 info->icount.txunder++;
2224                         else if (status & IRQ_TXIDLE)
2225                                 info->icount.txok++;
2226                 }
2227
2228                 if (unsent_tbufs(info)) {
2229                         tx_start(info);
2230                         update_tx_timer(info);
2231                         return;
2232                 }
2233                 info->tx_active = false;
2234
2235                 del_timer(&info->tx_timer);
2236
2237                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2238                         info->signals &= ~SerialSignal_RTS;
2239                         info->drop_rts_on_tx_done = false;
2240                         set_gtsignals(info);
2241                 }
2242
2243 #if SYNCLINK_GENERIC_HDLC
2244                 if (info->netcount)
2245                         hdlcdev_tx_done(info);
2246                 else
2247 #endif
2248                 {
2249                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2250                                 tx_stop(info);
2251                                 return;
2252                         }
2253                         info->pending_bh |= BH_TRANSMIT;
2254                 }
2255         }
2256 }
2257
2258 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2259 {
2260         struct cond_wait *w, *prev;
2261
2262         /* wake processes waiting for specific transitions */
2263         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2264                 if (w->data & changed) {
2265                         w->data = state;
2266                         wake_up_interruptible(&w->q);
2267                         if (prev != NULL)
2268                                 prev->next = w->next;
2269                         else
2270                                 info->gpio_wait_q = w->next;
2271                 } else
2272                         prev = w;
2273         }
2274 }
2275
2276 /* interrupt service routine
2277  *
2278  *      irq     interrupt number
2279  *      dev_id  device ID supplied during interrupt registration
2280  */
2281 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2282 {
2283         struct slgt_info *info = dev_id;
2284         unsigned int gsr;
2285         unsigned int i;
2286
2287         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2288
2289         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2290                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2291                 info->irq_occurred = true;
2292                 for(i=0; i < info->port_count ; i++) {
2293                         if (info->port_array[i] == NULL)
2294                                 continue;
2295                         spin_lock(&info->port_array[i]->lock);
2296                         if (gsr & (BIT8 << i))
2297                                 isr_serial(info->port_array[i]);
2298                         if (gsr & (BIT16 << (i*2)))
2299                                 isr_rdma(info->port_array[i]);
2300                         if (gsr & (BIT17 << (i*2)))
2301                                 isr_tdma(info->port_array[i]);
2302                         spin_unlock(&info->port_array[i]->lock);
2303                 }
2304         }
2305
2306         if (info->gpio_present) {
2307                 unsigned int state;
2308                 unsigned int changed;
2309                 spin_lock(&info->lock);
2310                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2311                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2312                         /* read latched state of GPIO signals */
2313                         state = rd_reg32(info, IOVR);
2314                         /* clear pending GPIO interrupt bits */
2315                         wr_reg32(info, IOSR, changed);
2316                         for (i=0 ; i < info->port_count ; i++) {
2317                                 if (info->port_array[i] != NULL)
2318                                         isr_gpio(info->port_array[i], changed, state);
2319                         }
2320                 }
2321                 spin_unlock(&info->lock);
2322         }
2323
2324         for(i=0; i < info->port_count ; i++) {
2325                 struct slgt_info *port = info->port_array[i];
2326                 if (port == NULL)
2327                         continue;
2328                 spin_lock(&port->lock);
2329                 if ((port->port.count || port->netcount) &&
2330                     port->pending_bh && !port->bh_running &&
2331                     !port->bh_requested) {
2332                         DBGISR(("%s bh queued\n", port->device_name));
2333                         schedule_work(&port->task);
2334                         port->bh_requested = true;
2335                 }
2336                 spin_unlock(&port->lock);
2337         }
2338
2339         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2340         return IRQ_HANDLED;
2341 }
2342
2343 static int startup(struct slgt_info *info)
2344 {
2345         DBGINFO(("%s startup\n", info->device_name));
2346
2347         if (tty_port_initialized(&info->port))
2348                 return 0;
2349
2350         if (!info->tx_buf) {
2351                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2352                 if (!info->tx_buf) {
2353                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2354                         return -ENOMEM;
2355                 }
2356         }
2357
2358         info->pending_bh = 0;
2359
2360         memset(&info->icount, 0, sizeof(info->icount));
2361
2362         /* program hardware for current parameters */
2363         change_params(info);
2364
2365         if (info->port.tty)
2366                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2367
2368         tty_port_set_initialized(&info->port, 1);
2369
2370         return 0;
2371 }
2372
2373 /*
2374  *  called by close() and hangup() to shutdown hardware
2375  */
2376 static void shutdown(struct slgt_info *info)
2377 {
2378         unsigned long flags;
2379
2380         if (!tty_port_initialized(&info->port))
2381                 return;
2382
2383         DBGINFO(("%s shutdown\n", info->device_name));
2384
2385         /* clear status wait queue because status changes */
2386         /* can't happen after shutting down the hardware */
2387         wake_up_interruptible(&info->status_event_wait_q);
2388         wake_up_interruptible(&info->event_wait_q);
2389
2390         del_timer_sync(&info->tx_timer);
2391         del_timer_sync(&info->rx_timer);
2392
2393         kfree(info->tx_buf);
2394         info->tx_buf = NULL;
2395
2396         spin_lock_irqsave(&info->lock,flags);
2397
2398         tx_stop(info);
2399         rx_stop(info);
2400
2401         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2402
2403         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2404                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2405                 set_gtsignals(info);
2406         }
2407
2408         flush_cond_wait(&info->gpio_wait_q);
2409
2410         spin_unlock_irqrestore(&info->lock,flags);
2411
2412         if (info->port.tty)
2413                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2414
2415         tty_port_set_initialized(&info->port, 0);
2416 }
2417
2418 static void program_hw(struct slgt_info *info)
2419 {
2420         unsigned long flags;
2421
2422         spin_lock_irqsave(&info->lock,flags);
2423
2424         rx_stop(info);
2425         tx_stop(info);
2426
2427         if (info->params.mode != MGSL_MODE_ASYNC ||
2428             info->netcount)
2429                 sync_mode(info);
2430         else
2431                 async_mode(info);
2432
2433         set_gtsignals(info);
2434
2435         info->dcd_chkcount = 0;
2436         info->cts_chkcount = 0;
2437         info->ri_chkcount = 0;
2438         info->dsr_chkcount = 0;
2439
2440         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2441         get_gtsignals(info);
2442
2443         if (info->netcount ||
2444             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2445                 rx_start(info);
2446
2447         spin_unlock_irqrestore(&info->lock,flags);
2448 }
2449
2450 /*
2451  * reconfigure adapter based on new parameters
2452  */
2453 static void change_params(struct slgt_info *info)
2454 {
2455         unsigned cflag;
2456         int bits_per_char;
2457
2458         if (!info->port.tty)
2459                 return;
2460         DBGINFO(("%s change_params\n", info->device_name));
2461
2462         cflag = info->port.tty->termios.c_cflag;
2463
2464         /* if B0 rate (hangup) specified then negate RTS and DTR */
2465         /* otherwise assert RTS and DTR */
2466         if (cflag & CBAUD)
2467                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2468         else
2469                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2470
2471         /* byte size and parity */
2472
2473         switch (cflag & CSIZE) {
2474         case CS5: info->params.data_bits = 5; break;
2475         case CS6: info->params.data_bits = 6; break;
2476         case CS7: info->params.data_bits = 7; break;
2477         case CS8: info->params.data_bits = 8; break;
2478         default:  info->params.data_bits = 7; break;
2479         }
2480
2481         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2482
2483         if (cflag & PARENB)
2484                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2485         else
2486                 info->params.parity = ASYNC_PARITY_NONE;
2487
2488         /* calculate number of jiffies to transmit a full
2489          * FIFO (32 bytes) at specified data rate
2490          */
2491         bits_per_char = info->params.data_bits +
2492                         info->params.stop_bits + 1;
2493
2494         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2495
2496         if (info->params.data_rate) {
2497                 info->timeout = (32*HZ*bits_per_char) /
2498                                 info->params.data_rate;
2499         }
2500         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2501
2502         tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2503         tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2504
2505         /* process tty input control flags */
2506
2507         info->read_status_mask = IRQ_RXOVER;
2508         if (I_INPCK(info->port.tty))
2509                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2510         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2511                 info->read_status_mask |= MASK_BREAK;
2512         if (I_IGNPAR(info->port.tty))
2513                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2514         if (I_IGNBRK(info->port.tty)) {
2515                 info->ignore_status_mask |= MASK_BREAK;
2516                 /* If ignoring parity and break indicators, ignore
2517                  * overruns too.  (For real raw support).
2518                  */
2519                 if (I_IGNPAR(info->port.tty))
2520                         info->ignore_status_mask |= MASK_OVERRUN;
2521         }
2522
2523         program_hw(info);
2524 }
2525
2526 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2527 {
2528         DBGINFO(("%s get_stats\n",  info->device_name));
2529         if (!user_icount) {
2530                 memset(&info->icount, 0, sizeof(info->icount));
2531         } else {
2532                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2533                         return -EFAULT;
2534         }
2535         return 0;
2536 }
2537
2538 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2539 {
2540         DBGINFO(("%s get_params\n", info->device_name));
2541         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2542                 return -EFAULT;
2543         return 0;
2544 }
2545
2546 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2547 {
2548         unsigned long flags;
2549         MGSL_PARAMS tmp_params;
2550
2551         DBGINFO(("%s set_params\n", info->device_name));
2552         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2553                 return -EFAULT;
2554
2555         spin_lock_irqsave(&info->lock, flags);
2556         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2557                 info->base_clock = tmp_params.clock_speed;
2558         else
2559                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2560         spin_unlock_irqrestore(&info->lock, flags);
2561
2562         program_hw(info);
2563
2564         return 0;
2565 }
2566
2567 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2568 {
2569         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2570         if (put_user(info->idle_mode, idle_mode))
2571                 return -EFAULT;
2572         return 0;
2573 }
2574
2575 static int set_txidle(struct slgt_info *info, int idle_mode)
2576 {
2577         unsigned long flags;
2578         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2579         spin_lock_irqsave(&info->lock,flags);
2580         info->idle_mode = idle_mode;
2581         if (info->params.mode != MGSL_MODE_ASYNC)
2582                 tx_set_idle(info);
2583         spin_unlock_irqrestore(&info->lock,flags);
2584         return 0;
2585 }
2586
2587 static int tx_enable(struct slgt_info *info, int enable)
2588 {
2589         unsigned long flags;
2590         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2591         spin_lock_irqsave(&info->lock,flags);
2592         if (enable) {
2593                 if (!info->tx_enabled)
2594                         tx_start(info);
2595         } else {
2596                 if (info->tx_enabled)
2597                         tx_stop(info);
2598         }
2599         spin_unlock_irqrestore(&info->lock,flags);
2600         return 0;
2601 }
2602
2603 /*
2604  * abort transmit HDLC frame
2605  */
2606 static int tx_abort(struct slgt_info *info)
2607 {
2608         unsigned long flags;
2609         DBGINFO(("%s tx_abort\n", info->device_name));
2610         spin_lock_irqsave(&info->lock,flags);
2611         tdma_reset(info);
2612         spin_unlock_irqrestore(&info->lock,flags);
2613         return 0;
2614 }
2615
2616 static int rx_enable(struct slgt_info *info, int enable)
2617 {
2618         unsigned long flags;
2619         unsigned int rbuf_fill_level;
2620         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2621         spin_lock_irqsave(&info->lock,flags);
2622         /*
2623          * enable[31..16] = receive DMA buffer fill level
2624          * 0 = noop (leave fill level unchanged)
2625          * fill level must be multiple of 4 and <= buffer size
2626          */
2627         rbuf_fill_level = ((unsigned int)enable) >> 16;
2628         if (rbuf_fill_level) {
2629                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2630                         spin_unlock_irqrestore(&info->lock, flags);
2631                         return -EINVAL;
2632                 }
2633                 info->rbuf_fill_level = rbuf_fill_level;
2634                 if (rbuf_fill_level < 128)
2635                         info->rx_pio = 1; /* PIO mode */
2636                 else
2637                         info->rx_pio = 0; /* DMA mode */
2638                 rx_stop(info); /* restart receiver to use new fill level */
2639         }
2640
2641         /*
2642          * enable[1..0] = receiver enable command
2643          * 0 = disable
2644          * 1 = enable
2645          * 2 = enable or force hunt mode if already enabled
2646          */
2647         enable &= 3;
2648         if (enable) {
2649                 if (!info->rx_enabled)
2650                         rx_start(info);
2651                 else if (enable == 2) {
2652                         /* force hunt mode (write 1 to RCR[3]) */
2653                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2654                 }
2655         } else {
2656                 if (info->rx_enabled)
2657                         rx_stop(info);
2658         }
2659         spin_unlock_irqrestore(&info->lock,flags);
2660         return 0;
2661 }
2662
2663 /*
2664  *  wait for specified event to occur
2665  */
2666 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2667 {
2668         unsigned long flags;
2669         int s;
2670         int rc=0;
2671         struct mgsl_icount cprev, cnow;
2672         int events;
2673         int mask;
2674         struct  _input_signal_events oldsigs, newsigs;
2675         DECLARE_WAITQUEUE(wait, current);
2676
2677         if (get_user(mask, mask_ptr))
2678                 return -EFAULT;
2679
2680         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2681
2682         spin_lock_irqsave(&info->lock,flags);
2683
2684         /* return immediately if state matches requested events */
2685         get_gtsignals(info);
2686         s = info->signals;
2687
2688         events = mask &
2689                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2690                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2691                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2692                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2693         if (events) {
2694                 spin_unlock_irqrestore(&info->lock,flags);
2695                 goto exit;
2696         }
2697
2698         /* save current irq counts */
2699         cprev = info->icount;
2700         oldsigs = info->input_signal_events;
2701
2702         /* enable hunt and idle irqs if needed */
2703         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2704                 unsigned short val = rd_reg16(info, SCR);
2705                 if (!(val & IRQ_RXIDLE))
2706                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2707         }
2708
2709         set_current_state(TASK_INTERRUPTIBLE);
2710         add_wait_queue(&info->event_wait_q, &wait);
2711
2712         spin_unlock_irqrestore(&info->lock,flags);
2713
2714         for(;;) {
2715                 schedule();
2716                 if (signal_pending(current)) {
2717                         rc = -ERESTARTSYS;
2718                         break;
2719                 }
2720
2721                 /* get current irq counts */
2722                 spin_lock_irqsave(&info->lock,flags);
2723                 cnow = info->icount;
2724                 newsigs = info->input_signal_events;
2725                 set_current_state(TASK_INTERRUPTIBLE);
2726                 spin_unlock_irqrestore(&info->lock,flags);
2727
2728                 /* if no change, wait aborted for some reason */
2729                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2730                     newsigs.dsr_down == oldsigs.dsr_down &&
2731                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2732                     newsigs.dcd_down == oldsigs.dcd_down &&
2733                     newsigs.cts_up   == oldsigs.cts_up   &&
2734                     newsigs.cts_down == oldsigs.cts_down &&
2735                     newsigs.ri_up    == oldsigs.ri_up    &&
2736                     newsigs.ri_down  == oldsigs.ri_down  &&
2737                     cnow.exithunt    == cprev.exithunt   &&
2738                     cnow.rxidle      == cprev.rxidle) {
2739                         rc = -EIO;
2740                         break;
2741                 }
2742
2743                 events = mask &
2744                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2745                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2746                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2747                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2748                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2749                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2750                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2751                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2752                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2753                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2754                 if (events)
2755                         break;
2756
2757                 cprev = cnow;
2758                 oldsigs = newsigs;
2759         }
2760
2761         remove_wait_queue(&info->event_wait_q, &wait);
2762         set_current_state(TASK_RUNNING);
2763
2764
2765         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2766                 spin_lock_irqsave(&info->lock,flags);
2767                 if (!waitqueue_active(&info->event_wait_q)) {
2768                         /* disable enable exit hunt mode/idle rcvd IRQs */
2769                         wr_reg16(info, SCR,
2770                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2771                 }
2772                 spin_unlock_irqrestore(&info->lock,flags);
2773         }
2774 exit:
2775         if (rc == 0)
2776                 rc = put_user(events, mask_ptr);
2777         return rc;
2778 }
2779
2780 static int get_interface(struct slgt_info *info, int __user *if_mode)
2781 {
2782         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2783         if (put_user(info->if_mode, if_mode))
2784                 return -EFAULT;
2785         return 0;
2786 }
2787
2788 static int set_interface(struct slgt_info *info, int if_mode)
2789 {
2790         unsigned long flags;
2791         unsigned short val;
2792
2793         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2794         spin_lock_irqsave(&info->lock,flags);
2795         info->if_mode = if_mode;
2796
2797         msc_set_vcr(info);
2798
2799         /* TCR (tx control) 07  1=RTS driver control */
2800         val = rd_reg16(info, TCR);
2801         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2802                 val |= BIT7;
2803         else
2804                 val &= ~BIT7;
2805         wr_reg16(info, TCR, val);
2806
2807         spin_unlock_irqrestore(&info->lock,flags);
2808         return 0;
2809 }
2810
2811 static int get_xsync(struct slgt_info *info, int __user *xsync)
2812 {
2813         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2814         if (put_user(info->xsync, xsync))
2815                 return -EFAULT;
2816         return 0;
2817 }
2818
2819 /*
2820  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2821  *
2822  * sync pattern is contained in least significant bytes of value
2823  * most significant byte of sync pattern is oldest (1st sent/detected)
2824  */
2825 static int set_xsync(struct slgt_info *info, int xsync)
2826 {
2827         unsigned long flags;
2828
2829         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2830         spin_lock_irqsave(&info->lock, flags);
2831         info->xsync = xsync;
2832         wr_reg32(info, XSR, xsync);
2833         spin_unlock_irqrestore(&info->lock, flags);
2834         return 0;
2835 }
2836
2837 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2838 {
2839         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2840         if (put_user(info->xctrl, xctrl))
2841                 return -EFAULT;
2842         return 0;
2843 }
2844
2845 /*
2846  * set extended control options
2847  *
2848  * xctrl[31:19] reserved, must be zero
2849  * xctrl[18:17] extended sync pattern length in bytes
2850  *              00 = 1 byte  in xsr[7:0]
2851  *              01 = 2 bytes in xsr[15:0]
2852  *              10 = 3 bytes in xsr[23:0]
2853  *              11 = 4 bytes in xsr[31:0]
2854  * xctrl[16]    1 = enable terminal count, 0=disabled
2855  * xctrl[15:0]  receive terminal count for fixed length packets
2856  *              value is count minus one (0 = 1 byte packet)
2857  *              when terminal count is reached, receiver
2858  *              automatically returns to hunt mode and receive
2859  *              FIFO contents are flushed to DMA buffers with
2860  *              end of frame (EOF) status
2861  */
2862 static int set_xctrl(struct slgt_info *info, int xctrl)
2863 {
2864         unsigned long flags;
2865
2866         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2867         spin_lock_irqsave(&info->lock, flags);
2868         info->xctrl = xctrl;
2869         wr_reg32(info, XCR, xctrl);
2870         spin_unlock_irqrestore(&info->lock, flags);
2871         return 0;
2872 }
2873
2874 /*
2875  * set general purpose IO pin state and direction
2876  *
2877  * user_gpio fields:
2878  * state   each bit indicates a pin state
2879  * smask   set bit indicates pin state to set
2880  * dir     each bit indicates a pin direction (0=input, 1=output)
2881  * dmask   set bit indicates pin direction to set
2882  */
2883 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2884 {
2885         unsigned long flags;
2886         struct gpio_desc gpio;
2887         __u32 data;
2888
2889         if (!info->gpio_present)
2890                 return -EINVAL;
2891         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2892                 return -EFAULT;
2893         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2894                  info->device_name, gpio.state, gpio.smask,
2895                  gpio.dir, gpio.dmask));
2896
2897         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2898         if (gpio.dmask) {
2899                 data = rd_reg32(info, IODR);
2900                 data |= gpio.dmask & gpio.dir;
2901                 data &= ~(gpio.dmask & ~gpio.dir);
2902                 wr_reg32(info, IODR, data);
2903         }
2904         if (gpio.smask) {
2905                 data = rd_reg32(info, IOVR);
2906                 data |= gpio.smask & gpio.state;
2907                 data &= ~(gpio.smask & ~gpio.state);
2908                 wr_reg32(info, IOVR, data);
2909         }
2910         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2911
2912         return 0;
2913 }
2914
2915 /*
2916  * get general purpose IO pin state and direction
2917  */
2918 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2919 {
2920         struct gpio_desc gpio;
2921         if (!info->gpio_present)
2922                 return -EINVAL;
2923         gpio.state = rd_reg32(info, IOVR);
2924         gpio.smask = 0xffffffff;
2925         gpio.dir   = rd_reg32(info, IODR);
2926         gpio.dmask = 0xffffffff;
2927         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2928                 return -EFAULT;
2929         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2930                  info->device_name, gpio.state, gpio.dir));
2931         return 0;
2932 }
2933
2934 /*
2935  * conditional wait facility
2936  */
2937 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2938 {
2939         init_waitqueue_head(&w->q);
2940         init_waitqueue_entry(&w->wait, current);
2941         w->data = data;
2942 }
2943
2944 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2945 {
2946         set_current_state(TASK_INTERRUPTIBLE);
2947         add_wait_queue(&w->q, &w->wait);
2948         w->next = *head;
2949         *head = w;
2950 }
2951
2952 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2953 {
2954         struct cond_wait *w, *prev;
2955         remove_wait_queue(&cw->q, &cw->wait);
2956         set_current_state(TASK_RUNNING);
2957         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2958                 if (w == cw) {
2959                         if (prev != NULL)
2960                                 prev->next = w->next;
2961                         else
2962                                 *head = w->next;
2963                         break;
2964                 }
2965         }
2966 }
2967
2968 static void flush_cond_wait(struct cond_wait **head)
2969 {
2970         while (*head != NULL) {
2971                 wake_up_interruptible(&(*head)->q);
2972                 *head = (*head)->next;
2973         }
2974 }
2975
2976 /*
2977  * wait for general purpose I/O pin(s) to enter specified state
2978  *
2979  * user_gpio fields:
2980  * state - bit indicates target pin state
2981  * smask - set bit indicates watched pin
2982  *
2983  * The wait ends when at least one watched pin enters the specified
2984  * state. When 0 (no error) is returned, user_gpio->state is set to the
2985  * state of all GPIO pins when the wait ends.
2986  *
2987  * Note: Each pin may be a dedicated input, dedicated output, or
2988  * configurable input/output. The number and configuration of pins
2989  * varies with the specific adapter model. Only input pins (dedicated
2990  * or configured) can be monitored with this function.
2991  */
2992 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2993 {
2994         unsigned long flags;
2995         int rc = 0;
2996         struct gpio_desc gpio;
2997         struct cond_wait wait;
2998         u32 state;
2999
3000         if (!info->gpio_present)
3001                 return -EINVAL;
3002         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3003                 return -EFAULT;
3004         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3005                  info->device_name, gpio.state, gpio.smask));
3006         /* ignore output pins identified by set IODR bit */
3007         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3008                 return -EINVAL;
3009         init_cond_wait(&wait, gpio.smask);
3010
3011         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3012         /* enable interrupts for watched pins */
3013         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3014         /* get current pin states */
3015         state = rd_reg32(info, IOVR);
3016
3017         if (gpio.smask & ~(state ^ gpio.state)) {
3018                 /* already in target state */
3019                 gpio.state = state;
3020         } else {
3021                 /* wait for target state */
3022                 add_cond_wait(&info->gpio_wait_q, &wait);
3023                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3024                 schedule();
3025                 if (signal_pending(current))
3026                         rc = -ERESTARTSYS;
3027                 else
3028                         gpio.state = wait.data;
3029                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3030                 remove_cond_wait(&info->gpio_wait_q, &wait);
3031         }
3032
3033         /* disable all GPIO interrupts if no waiting processes */
3034         if (info->gpio_wait_q == NULL)
3035                 wr_reg32(info, IOER, 0);
3036         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3037
3038         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3039                 rc = -EFAULT;
3040         return rc;
3041 }
3042
3043 static int modem_input_wait(struct slgt_info *info,int arg)
3044 {
3045         unsigned long flags;
3046         int rc;
3047         struct mgsl_icount cprev, cnow;
3048         DECLARE_WAITQUEUE(wait, current);
3049
3050         /* save current irq counts */
3051         spin_lock_irqsave(&info->lock,flags);
3052         cprev = info->icount;
3053         add_wait_queue(&info->status_event_wait_q, &wait);
3054         set_current_state(TASK_INTERRUPTIBLE);
3055         spin_unlock_irqrestore(&info->lock,flags);
3056
3057         for(;;) {
3058                 schedule();
3059                 if (signal_pending(current)) {
3060                         rc = -ERESTARTSYS;
3061                         break;
3062                 }
3063
3064                 /* get new irq counts */
3065                 spin_lock_irqsave(&info->lock,flags);
3066                 cnow = info->icount;
3067                 set_current_state(TASK_INTERRUPTIBLE);
3068                 spin_unlock_irqrestore(&info->lock,flags);
3069
3070                 /* if no change, wait aborted for some reason */
3071                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3072                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3073                         rc = -EIO;
3074                         break;
3075                 }
3076
3077                 /* check for change in caller specified modem input */
3078                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3079                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3080                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3081                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3082                         rc = 0;
3083                         break;
3084                 }
3085
3086                 cprev = cnow;
3087         }
3088         remove_wait_queue(&info->status_event_wait_q, &wait);
3089         set_current_state(TASK_RUNNING);
3090         return rc;
3091 }
3092
3093 /*
3094  *  return state of serial control and status signals
3095  */
3096 static int tiocmget(struct tty_struct *tty)
3097 {
3098         struct slgt_info *info = tty->driver_data;
3099         unsigned int result;
3100         unsigned long flags;
3101
3102         spin_lock_irqsave(&info->lock,flags);
3103         get_gtsignals(info);
3104         spin_unlock_irqrestore(&info->lock,flags);
3105
3106         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3107                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3108                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3109                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3110                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3111                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3112
3113         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3114         return result;
3115 }
3116
3117 /*
3118  * set modem control signals (DTR/RTS)
3119  *
3120  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3121  *              TIOCMSET = set/clear signal values
3122  *      value   bit mask for command
3123  */
3124 static int tiocmset(struct tty_struct *tty,
3125                     unsigned int set, unsigned int clear)
3126 {
3127         struct slgt_info *info = tty->driver_data;
3128         unsigned long flags;
3129
3130         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3131
3132         if (set & TIOCM_RTS)
3133                 info->signals |= SerialSignal_RTS;
3134         if (set & TIOCM_DTR)
3135                 info->signals |= SerialSignal_DTR;
3136         if (clear & TIOCM_RTS)
3137                 info->signals &= ~SerialSignal_RTS;
3138         if (clear & TIOCM_DTR)
3139                 info->signals &= ~SerialSignal_DTR;
3140
3141         spin_lock_irqsave(&info->lock,flags);
3142         set_gtsignals(info);
3143         spin_unlock_irqrestore(&info->lock,flags);
3144         return 0;
3145 }
3146
3147 static int carrier_raised(struct tty_port *port)
3148 {
3149         unsigned long flags;
3150         struct slgt_info *info = container_of(port, struct slgt_info, port);
3151
3152         spin_lock_irqsave(&info->lock,flags);
3153         get_gtsignals(info);
3154         spin_unlock_irqrestore(&info->lock,flags);
3155         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3156 }
3157
3158 static void dtr_rts(struct tty_port *port, int on)
3159 {
3160         unsigned long flags;
3161         struct slgt_info *info = container_of(port, struct slgt_info, port);
3162
3163         spin_lock_irqsave(&info->lock,flags);
3164         if (on)
3165                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3166         else
3167                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3168         set_gtsignals(info);
3169         spin_unlock_irqrestore(&info->lock,flags);
3170 }
3171
3172
3173 /*
3174  *  block current process until the device is ready to open
3175  */
3176 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3177                            struct slgt_info *info)
3178 {
3179         DECLARE_WAITQUEUE(wait, current);
3180         int             retval;
3181         bool            do_clocal = false;
3182         unsigned long   flags;
3183         int             cd;
3184         struct tty_port *port = &info->port;
3185
3186         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3187
3188         if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3189                 /* nonblock mode is set or port is not enabled */
3190                 tty_port_set_active(port, 1);
3191                 return 0;
3192         }
3193
3194         if (C_CLOCAL(tty))
3195                 do_clocal = true;
3196
3197         /* Wait for carrier detect and the line to become
3198          * free (i.e., not in use by the callout).  While we are in
3199          * this loop, port->count is dropped by one, so that
3200          * close() knows when to free things.  We restore it upon
3201          * exit, either normal or abnormal.
3202          */
3203
3204         retval = 0;
3205         add_wait_queue(&port->open_wait, &wait);
3206
3207         spin_lock_irqsave(&info->lock, flags);
3208         port->count--;
3209         spin_unlock_irqrestore(&info->lock, flags);
3210         port->blocked_open++;
3211
3212         while (1) {
3213                 if (C_BAUD(tty) && tty_port_initialized(port))
3214                         tty_port_raise_dtr_rts(port);
3215
3216                 set_current_state(TASK_INTERRUPTIBLE);
3217
3218                 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3219                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3220                                         -EAGAIN : -ERESTARTSYS;
3221                         break;
3222                 }
3223
3224                 cd = tty_port_carrier_raised(port);
3225                 if (do_clocal || cd)
3226                         break;
3227
3228                 if (signal_pending(current)) {
3229                         retval = -ERESTARTSYS;
3230                         break;
3231                 }
3232
3233                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3234                 tty_unlock(tty);
3235                 schedule();
3236                 tty_lock(tty);
3237         }
3238
3239         set_current_state(TASK_RUNNING);
3240         remove_wait_queue(&port->open_wait, &wait);
3241
3242         if (!tty_hung_up_p(filp))
3243                 port->count++;
3244         port->blocked_open--;
3245
3246         if (!retval)
3247                 tty_port_set_active(port, 1);
3248
3249         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3250         return retval;
3251 }
3252
3253 /*
3254  * allocate buffers used for calling line discipline receive_buf
3255  * directly in synchronous mode
3256  * note: add 5 bytes to max frame size to allow appending
3257  * 32-bit CRC and status byte when configured to do so
3258  */
3259 static int alloc_tmp_rbuf(struct slgt_info *info)
3260 {
3261         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3262         if (info->tmp_rbuf == NULL)
3263                 return -ENOMEM;
3264         /* unused flag buffer to satisfy receive_buf calling interface */
3265         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3266         if (!info->flag_buf) {
3267                 kfree(info->tmp_rbuf);
3268                 info->tmp_rbuf = NULL;
3269                 return -ENOMEM;
3270         }
3271         return 0;
3272 }
3273
3274 static void free_tmp_rbuf(struct slgt_info *info)
3275 {
3276         kfree(info->tmp_rbuf);
3277         info->tmp_rbuf = NULL;
3278         kfree(info->flag_buf);
3279         info->flag_buf = NULL;
3280 }
3281
3282 /*
3283  * allocate DMA descriptor lists.
3284  */
3285 static int alloc_desc(struct slgt_info *info)
3286 {
3287         unsigned int i;
3288         unsigned int pbufs;
3289
3290         /* allocate memory to hold descriptor lists */
3291         info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3292                                            &info->bufs_dma_addr);
3293         if (info->bufs == NULL)
3294                 return -ENOMEM;
3295
3296         info->rbufs = (struct slgt_desc*)info->bufs;
3297         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3298
3299         pbufs = (unsigned int)info->bufs_dma_addr;
3300
3301         /*
3302          * Build circular lists of descriptors
3303          */
3304
3305         for (i=0; i < info->rbuf_count; i++) {
3306                 /* physical address of this descriptor */
3307                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3308
3309                 /* physical address of next descriptor */
3310                 if (i == info->rbuf_count - 1)
3311                         info->rbufs[i].next = cpu_to_le32(pbufs);
3312                 else
3313                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3314                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3315         }
3316
3317         for (i=0; i < info->tbuf_count; i++) {
3318                 /* physical address of this descriptor */
3319                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3320
3321                 /* physical address of next descriptor */
3322                 if (i == info->tbuf_count - 1)
3323                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3324                 else
3325                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3326         }
3327
3328         return 0;
3329 }
3330
3331 static void free_desc(struct slgt_info *info)
3332 {
3333         if (info->bufs != NULL) {
3334                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3335                 info->bufs  = NULL;
3336                 info->rbufs = NULL;
3337                 info->tbufs = NULL;
3338         }
3339 }
3340
3341 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3342 {
3343         int i;
3344         for (i=0; i < count; i++) {
3345                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3346                         return -ENOMEM;
3347                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3348         }
3349         return 0;
3350 }
3351
3352 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3353 {
3354         int i;
3355         for (i=0; i < count; i++) {
3356                 if (bufs[i].buf == NULL)
3357                         continue;
3358                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3359                 bufs[i].buf = NULL;
3360         }
3361 }
3362
3363 static int alloc_dma_bufs(struct slgt_info *info)
3364 {
3365         info->rbuf_count = 32;
3366         info->tbuf_count = 32;
3367
3368         if (alloc_desc(info) < 0 ||
3369             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3370             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3371             alloc_tmp_rbuf(info) < 0) {
3372                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3373                 return -ENOMEM;
3374         }
3375         reset_rbufs(info);
3376         return 0;
3377 }
3378
3379 static void free_dma_bufs(struct slgt_info *info)
3380 {
3381         if (info->bufs) {
3382                 free_bufs(info, info->rbufs, info->rbuf_count);
3383                 free_bufs(info, info->tbufs, info->tbuf_count);
3384                 free_desc(info);
3385         }
3386         free_tmp_rbuf(info);
3387 }
3388
3389 static int claim_resources(struct slgt_info *info)
3390 {
3391         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3392                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3393                         info->device_name, info->phys_reg_addr));
3394                 info->init_error = DiagStatus_AddressConflict;
3395                 goto errout;
3396         }
3397         else
3398                 info->reg_addr_requested = true;
3399
3400         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3401         if (!info->reg_addr) {
3402                 DBGERR(("%s can't map device registers, addr=%08X\n",
3403                         info->device_name, info->phys_reg_addr));
3404                 info->init_error = DiagStatus_CantAssignPciResources;
3405                 goto errout;
3406         }
3407         return 0;
3408
3409 errout:
3410         release_resources(info);
3411         return -ENODEV;
3412 }
3413
3414 static void release_resources(struct slgt_info *info)
3415 {
3416         if (info->irq_requested) {
3417                 free_irq(info->irq_level, info);
3418                 info->irq_requested = false;
3419         }
3420
3421         if (info->reg_addr_requested) {
3422                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3423                 info->reg_addr_requested = false;
3424         }
3425
3426         if (info->reg_addr) {
3427                 iounmap(info->reg_addr);
3428                 info->reg_addr = NULL;
3429         }
3430 }
3431
3432 /* Add the specified device instance data structure to the
3433  * global linked list of devices and increment the device count.
3434  */
3435 static void add_device(struct slgt_info *info)
3436 {
3437         char *devstr;
3438
3439         info->next_device = NULL;
3440         info->line = slgt_device_count;
3441         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3442
3443         if (info->line < MAX_DEVICES) {
3444                 if (maxframe[info->line])
3445                         info->max_frame_size = maxframe[info->line];
3446         }
3447
3448         slgt_device_count++;
3449
3450         if (!slgt_device_list)
3451                 slgt_device_list = info;
3452         else {
3453                 struct slgt_info *current_dev = slgt_device_list;
3454                 while(current_dev->next_device)
3455                         current_dev = current_dev->next_device;
3456                 current_dev->next_device = info;
3457         }
3458
3459         if (info->max_frame_size < 4096)
3460                 info->max_frame_size = 4096;
3461         else if (info->max_frame_size > 65535)
3462                 info->max_frame_size = 65535;
3463
3464         switch(info->pdev->device) {
3465         case SYNCLINK_GT_DEVICE_ID:
3466                 devstr = "GT";
3467                 break;
3468         case SYNCLINK_GT2_DEVICE_ID:
3469                 devstr = "GT2";
3470                 break;
3471         case SYNCLINK_GT4_DEVICE_ID:
3472                 devstr = "GT4";
3473                 break;
3474         case SYNCLINK_AC_DEVICE_ID:
3475                 devstr = "AC";
3476                 info->params.mode = MGSL_MODE_ASYNC;
3477                 break;
3478         default:
3479                 devstr = "(unknown model)";
3480         }
3481         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3482                 devstr, info->device_name, info->phys_reg_addr,
3483                 info->irq_level, info->max_frame_size);
3484
3485 #if SYNCLINK_GENERIC_HDLC
3486         hdlcdev_init(info);
3487 #endif
3488 }
3489
3490 static const struct tty_port_operations slgt_port_ops = {
3491         .carrier_raised = carrier_raised,
3492         .dtr_rts = dtr_rts,
3493 };
3494
3495 /*
3496  *  allocate device instance structure, return NULL on failure
3497  */
3498 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3499 {
3500         struct slgt_info *info;
3501
3502         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3503
3504         if (!info) {
3505                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3506                         driver_name, adapter_num, port_num));
3507         } else {
3508                 tty_port_init(&info->port);
3509                 info->port.ops = &slgt_port_ops;
3510                 info->magic = MGSL_MAGIC;
3511                 INIT_WORK(&info->task, bh_handler);
3512                 info->max_frame_size = 4096;
3513                 info->base_clock = 14745600;
3514                 info->rbuf_fill_level = DMABUFSIZE;
3515                 info->port.close_delay = 5*HZ/10;
3516                 info->port.closing_wait = 30*HZ;
3517                 init_waitqueue_head(&info->status_event_wait_q);
3518                 init_waitqueue_head(&info->event_wait_q);
3519                 spin_lock_init(&info->netlock);
3520                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3521                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3522                 info->adapter_num = adapter_num;
3523                 info->port_num = port_num;
3524
3525                 timer_setup(&info->tx_timer, tx_timeout, 0);
3526                 timer_setup(&info->rx_timer, rx_timeout, 0);
3527
3528                 /* Copy configuration info to device instance data */
3529                 info->pdev = pdev;
3530                 info->irq_level = pdev->irq;
3531                 info->phys_reg_addr = pci_resource_start(pdev,0);
3532
3533                 info->bus_type = MGSL_BUS_TYPE_PCI;
3534                 info->irq_flags = IRQF_SHARED;
3535
3536                 info->init_error = -1; /* assume error, set to 0 on successful init */
3537         }
3538
3539         return info;
3540 }
3541
3542 static void device_init(int adapter_num, struct pci_dev *pdev)
3543 {
3544         struct slgt_info *port_array[SLGT_MAX_PORTS];
3545         int i;
3546         int port_count = 1;
3547
3548         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3549                 port_count = 2;
3550         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3551                 port_count = 4;
3552
3553         /* allocate device instances for all ports */
3554         for (i=0; i < port_count; ++i) {
3555                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3556                 if (port_array[i] == NULL) {
3557                         for (--i; i >= 0; --i) {
3558                                 tty_port_destroy(&port_array[i]->port);
3559                                 kfree(port_array[i]);
3560                         }
3561                         return;
3562                 }
3563         }
3564
3565         /* give copy of port_array to all ports and add to device list  */
3566         for (i=0; i < port_count; ++i) {
3567                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3568                 add_device(port_array[i]);
3569                 port_array[i]->port_count = port_count;
3570                 spin_lock_init(&port_array[i]->lock);
3571         }
3572
3573         /* Allocate and claim adapter resources */
3574         if (!claim_resources(port_array[0])) {
3575
3576                 alloc_dma_bufs(port_array[0]);
3577
3578                 /* copy resource information from first port to others */
3579                 for (i = 1; i < port_count; ++i) {
3580                         port_array[i]->irq_level = port_array[0]->irq_level;
3581                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3582                         alloc_dma_bufs(port_array[i]);
3583                 }
3584
3585                 if (request_irq(port_array[0]->irq_level,
3586                                         slgt_interrupt,
3587                                         port_array[0]->irq_flags,
3588                                         port_array[0]->device_name,
3589                                         port_array[0]) < 0) {
3590                         DBGERR(("%s request_irq failed IRQ=%d\n",
3591                                 port_array[0]->device_name,
3592                                 port_array[0]->irq_level));
3593                 } else {
3594                         port_array[0]->irq_requested = true;
3595                         adapter_test(port_array[0]);
3596                         for (i=1 ; i < port_count ; i++) {
3597                                 port_array[i]->init_error = port_array[0]->init_error;
3598                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3599                         }
3600                 }
3601         }
3602
3603         for (i = 0; i < port_count; ++i) {
3604                 struct slgt_info *info = port_array[i];
3605                 tty_port_register_device(&info->port, serial_driver, info->line,
3606                                 &info->pdev->dev);
3607         }
3608 }
3609
3610 static int init_one(struct pci_dev *dev,
3611                               const struct pci_device_id *ent)
3612 {
3613         if (pci_enable_device(dev)) {
3614                 printk("error enabling pci device %p\n", dev);
3615                 return -EIO;
3616         }
3617         pci_set_master(dev);
3618         device_init(slgt_device_count, dev);
3619         return 0;
3620 }
3621
3622 static void remove_one(struct pci_dev *dev)
3623 {
3624 }
3625
3626 static const struct tty_operations ops = {
3627         .open = open,
3628         .close = close,
3629         .write = write,
3630         .put_char = put_char,
3631         .flush_chars = flush_chars,
3632         .write_room = write_room,
3633         .chars_in_buffer = chars_in_buffer,
3634         .flush_buffer = flush_buffer,
3635         .ioctl = ioctl,
3636         .compat_ioctl = slgt_compat_ioctl,
3637         .throttle = throttle,
3638         .unthrottle = unthrottle,
3639         .send_xchar = send_xchar,
3640         .break_ctl = set_break,
3641         .wait_until_sent = wait_until_sent,
3642         .set_termios = set_termios,
3643         .stop = tx_hold,
3644         .start = tx_release,
3645         .hangup = hangup,
3646         .tiocmget = tiocmget,
3647         .tiocmset = tiocmset,
3648         .get_icount = get_icount,
3649         .proc_show = synclink_gt_proc_show,
3650 };
3651
3652 static void slgt_cleanup(void)
3653 {
3654         int rc;
3655         struct slgt_info *info;
3656         struct slgt_info *tmp;
3657
3658         printk(KERN_INFO "unload %s\n", driver_name);
3659
3660         if (serial_driver) {
3661                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3662                         tty_unregister_device(serial_driver, info->line);
3663                 rc = tty_unregister_driver(serial_driver);
3664                 if (rc)
3665                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3666                 put_tty_driver(serial_driver);
3667         }
3668
3669         /* reset devices */
3670         info = slgt_device_list;
3671         while(info) {
3672                 reset_port(info);
3673                 info = info->next_device;
3674         }
3675
3676         /* release devices */
3677         info = slgt_device_list;
3678         while(info) {
3679 #if SYNCLINK_GENERIC_HDLC
3680                 hdlcdev_exit(info);
3681 #endif
3682                 free_dma_bufs(info);
3683                 free_tmp_rbuf(info);
3684                 if (info->port_num == 0)
3685                         release_resources(info);
3686                 tmp = info;
3687                 info = info->next_device;
3688                 tty_port_destroy(&tmp->port);
3689                 kfree(tmp);
3690         }
3691
3692         if (pci_registered)
3693                 pci_unregister_driver(&pci_driver);
3694 }
3695
3696 /*
3697  *  Driver initialization entry point.
3698  */
3699 static int __init slgt_init(void)
3700 {
3701         int rc;
3702
3703         printk(KERN_INFO "%s\n", driver_name);
3704
3705         serial_driver = alloc_tty_driver(MAX_DEVICES);
3706         if (!serial_driver) {
3707                 printk("%s can't allocate tty driver\n", driver_name);
3708                 return -ENOMEM;
3709         }
3710
3711         /* Initialize the tty_driver structure */
3712
3713         serial_driver->driver_name = slgt_driver_name;
3714         serial_driver->name = tty_dev_prefix;
3715         serial_driver->major = ttymajor;
3716         serial_driver->minor_start = 64;
3717         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3718         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3719         serial_driver->init_termios = tty_std_termios;
3720         serial_driver->init_termios.c_cflag =
3721                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3722         serial_driver->init_termios.c_ispeed = 9600;
3723         serial_driver->init_termios.c_ospeed = 9600;
3724         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3725         tty_set_operations(serial_driver, &ops);
3726         if ((rc = tty_register_driver(serial_driver)) < 0) {
3727                 DBGERR(("%s can't register serial driver\n", driver_name));
3728                 put_tty_driver(serial_driver);
3729                 serial_driver = NULL;
3730                 goto error;
3731         }
3732
3733         printk(KERN_INFO "%s, tty major#%d\n",
3734                driver_name, serial_driver->major);
3735
3736         slgt_device_count = 0;
3737         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3738                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3739                 goto error;
3740         }
3741         pci_registered = true;
3742
3743         if (!slgt_device_list)
3744                 printk("%s no devices found\n",driver_name);
3745
3746         return 0;
3747
3748 error:
3749         slgt_cleanup();
3750         return rc;
3751 }
3752
3753 static void __exit slgt_exit(void)
3754 {
3755         slgt_cleanup();
3756 }
3757
3758 module_init(slgt_init);
3759 module_exit(slgt_exit);
3760
3761 /*
3762  * register access routines
3763  */
3764
3765 #define CALC_REGADDR() \
3766         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3767         if (addr >= 0x80) \
3768                 reg_addr += (info->port_num) * 32; \
3769         else if (addr >= 0x40)  \
3770                 reg_addr += (info->port_num) * 16;
3771
3772 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3773 {
3774         CALC_REGADDR();
3775         return readb((void __iomem *)reg_addr);
3776 }
3777
3778 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3779 {
3780         CALC_REGADDR();
3781         writeb(value, (void __iomem *)reg_addr);
3782 }
3783
3784 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3785 {
3786         CALC_REGADDR();
3787         return readw((void __iomem *)reg_addr);
3788 }
3789
3790 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3791 {
3792         CALC_REGADDR();
3793         writew(value, (void __iomem *)reg_addr);
3794 }
3795
3796 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3797 {
3798         CALC_REGADDR();
3799         return readl((void __iomem *)reg_addr);
3800 }
3801
3802 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3803 {
3804         CALC_REGADDR();
3805         writel(value, (void __iomem *)reg_addr);
3806 }
3807
3808 static void rdma_reset(struct slgt_info *info)
3809 {
3810         unsigned int i;
3811
3812         /* set reset bit */
3813         wr_reg32(info, RDCSR, BIT1);
3814
3815         /* wait for enable bit cleared */
3816         for(i=0 ; i < 1000 ; i++)
3817                 if (!(rd_reg32(info, RDCSR) & BIT0))
3818                         break;
3819 }
3820
3821 static void tdma_reset(struct slgt_info *info)
3822 {
3823         unsigned int i;
3824
3825         /* set reset bit */
3826         wr_reg32(info, TDCSR, BIT1);
3827
3828         /* wait for enable bit cleared */
3829         for(i=0 ; i < 1000 ; i++)
3830                 if (!(rd_reg32(info, TDCSR) & BIT0))
3831                         break;
3832 }
3833
3834 /*
3835  * enable internal loopback
3836  * TxCLK and RxCLK are generated from BRG
3837  * and TxD is looped back to RxD internally.
3838  */
3839 static void enable_loopback(struct slgt_info *info)
3840 {
3841         /* SCR (serial control) BIT2=loopback enable */
3842         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3843
3844         if (info->params.mode != MGSL_MODE_ASYNC) {
3845                 /* CCR (clock control)
3846                  * 07..05  tx clock source (010 = BRG)
3847                  * 04..02  rx clock source (010 = BRG)
3848                  * 01      auxclk enable   (0 = disable)
3849                  * 00      BRG enable      (1 = enable)
3850                  *
3851                  * 0100 1001
3852                  */
3853                 wr_reg8(info, CCR, 0x49);
3854
3855                 /* set speed if available, otherwise use default */
3856                 if (info->params.clock_speed)
3857                         set_rate(info, info->params.clock_speed);
3858                 else
3859                         set_rate(info, 3686400);
3860         }
3861 }
3862
3863 /*
3864  *  set baud rate generator to specified rate
3865  */
3866 static void set_rate(struct slgt_info *info, u32 rate)
3867 {
3868         unsigned int div;
3869         unsigned int osc = info->base_clock;
3870
3871         /* div = osc/rate - 1
3872          *
3873          * Round div up if osc/rate is not integer to
3874          * force to next slowest rate.
3875          */
3876
3877         if (rate) {
3878                 div = osc/rate;
3879                 if (!(osc % rate) && div)
3880                         div--;
3881                 wr_reg16(info, BDR, (unsigned short)div);
3882         }
3883 }
3884
3885 static void rx_stop(struct slgt_info *info)
3886 {
3887         unsigned short val;
3888
3889         /* disable and reset receiver */
3890         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3891         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3892         wr_reg16(info, RCR, val);                  /* clear reset bit */
3893
3894         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3895
3896         /* clear pending rx interrupts */
3897         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3898
3899         rdma_reset(info);
3900
3901         info->rx_enabled = false;
3902         info->rx_restart = false;
3903 }
3904
3905 static void rx_start(struct slgt_info *info)
3906 {
3907         unsigned short val;
3908
3909         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3910
3911         /* clear pending rx overrun IRQ */
3912         wr_reg16(info, SSR, IRQ_RXOVER);
3913
3914         /* reset and disable receiver */
3915         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3916         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3917         wr_reg16(info, RCR, val);                  /* clear reset bit */
3918
3919         rdma_reset(info);
3920         reset_rbufs(info);
3921
3922         if (info->rx_pio) {
3923                 /* rx request when rx FIFO not empty */
3924                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3925                 slgt_irq_on(info, IRQ_RXDATA);
3926                 if (info->params.mode == MGSL_MODE_ASYNC) {
3927                         /* enable saving of rx status */
3928                         wr_reg32(info, RDCSR, BIT6);
3929                 }
3930         } else {
3931                 /* rx request when rx FIFO half full */
3932                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3933                 /* set 1st descriptor address */
3934                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3935
3936                 if (info->params.mode != MGSL_MODE_ASYNC) {
3937                         /* enable rx DMA and DMA interrupt */
3938                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
3939                 } else {
3940                         /* enable saving of rx status, rx DMA and DMA interrupt */
3941                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3942                 }
3943         }
3944
3945         slgt_irq_on(info, IRQ_RXOVER);
3946
3947         /* enable receiver */
3948         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3949
3950         info->rx_restart = false;
3951         info->rx_enabled = true;
3952 }
3953
3954 static void tx_start(struct slgt_info *info)
3955 {
3956         if (!info->tx_enabled) {
3957                 wr_reg16(info, TCR,
3958                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3959                 info->tx_enabled = true;
3960         }
3961
3962         if (desc_count(info->tbufs[info->tbuf_start])) {
3963                 info->drop_rts_on_tx_done = false;
3964
3965                 if (info->params.mode != MGSL_MODE_ASYNC) {
3966                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3967                                 get_gtsignals(info);
3968                                 if (!(info->signals & SerialSignal_RTS)) {
3969                                         info->signals |= SerialSignal_RTS;
3970                                         set_gtsignals(info);
3971                                         info->drop_rts_on_tx_done = true;
3972                                 }
3973                         }
3974
3975                         slgt_irq_off(info, IRQ_TXDATA);
3976                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3977                         /* clear tx idle and underrun status bits */
3978                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3979                 } else {
3980                         slgt_irq_off(info, IRQ_TXDATA);
3981                         slgt_irq_on(info, IRQ_TXIDLE);
3982                         /* clear tx idle status bit */
3983                         wr_reg16(info, SSR, IRQ_TXIDLE);
3984                 }
3985                 /* set 1st descriptor address and start DMA */
3986                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3987                 wr_reg32(info, TDCSR, BIT2 + BIT0);
3988                 info->tx_active = true;
3989         }
3990 }
3991
3992 static void tx_stop(struct slgt_info *info)
3993 {
3994         unsigned short val;
3995
3996         del_timer(&info->tx_timer);
3997
3998         tdma_reset(info);
3999
4000         /* reset and disable transmitter */
4001         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4002         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4003
4004         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4005
4006         /* clear tx idle and underrun status bit */
4007         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4008
4009         reset_tbufs(info);
4010
4011         info->tx_enabled = false;
4012         info->tx_active = false;
4013 }
4014
4015 static void reset_port(struct slgt_info *info)
4016 {
4017         if (!info->reg_addr)
4018                 return;
4019
4020         tx_stop(info);
4021         rx_stop(info);
4022
4023         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4024         set_gtsignals(info);
4025
4026         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4027 }
4028
4029 static void reset_adapter(struct slgt_info *info)
4030 {
4031         int i;
4032         for (i=0; i < info->port_count; ++i) {
4033                 if (info->port_array[i])
4034                         reset_port(info->port_array[i]);
4035         }
4036 }
4037
4038 static void async_mode(struct slgt_info *info)
4039 {
4040         unsigned short val;
4041
4042         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4043         tx_stop(info);
4044         rx_stop(info);
4045
4046         /* TCR (tx control)
4047          *
4048          * 15..13  mode, 010=async
4049          * 12..10  encoding, 000=NRZ
4050          * 09      parity enable
4051          * 08      1=odd parity, 0=even parity
4052          * 07      1=RTS driver control
4053          * 06      1=break enable
4054          * 05..04  character length
4055          *         00=5 bits
4056          *         01=6 bits
4057          *         10=7 bits
4058          *         11=8 bits
4059          * 03      0=1 stop bit, 1=2 stop bits
4060          * 02      reset
4061          * 01      enable
4062          * 00      auto-CTS enable
4063          */
4064         val = 0x4000;
4065
4066         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4067                 val |= BIT7;
4068
4069         if (info->params.parity != ASYNC_PARITY_NONE) {
4070                 val |= BIT9;
4071                 if (info->params.parity == ASYNC_PARITY_ODD)
4072                         val |= BIT8;
4073         }
4074
4075         switch (info->params.data_bits)
4076         {
4077         case 6: val |= BIT4; break;
4078         case 7: val |= BIT5; break;
4079         case 8: val |= BIT5 + BIT4; break;
4080         }
4081
4082         if (info->params.stop_bits != 1)
4083                 val |= BIT3;
4084
4085         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4086                 val |= BIT0;
4087
4088         wr_reg16(info, TCR, val);
4089
4090         /* RCR (rx control)
4091          *
4092          * 15..13  mode, 010=async
4093          * 12..10  encoding, 000=NRZ
4094          * 09      parity enable
4095          * 08      1=odd parity, 0=even parity
4096          * 07..06  reserved, must be 0
4097          * 05..04  character length
4098          *         00=5 bits
4099          *         01=6 bits
4100          *         10=7 bits
4101          *         11=8 bits
4102          * 03      reserved, must be zero
4103          * 02      reset
4104          * 01      enable
4105          * 00      auto-DCD enable
4106          */
4107         val = 0x4000;
4108
4109         if (info->params.parity != ASYNC_PARITY_NONE) {
4110                 val |= BIT9;
4111                 if (info->params.parity == ASYNC_PARITY_ODD)
4112                         val |= BIT8;
4113         }
4114
4115         switch (info->params.data_bits)
4116         {
4117         case 6: val |= BIT4; break;
4118         case 7: val |= BIT5; break;
4119         case 8: val |= BIT5 + BIT4; break;
4120         }
4121
4122         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4123                 val |= BIT0;
4124
4125         wr_reg16(info, RCR, val);
4126
4127         /* CCR (clock control)
4128          *
4129          * 07..05  011 = tx clock source is BRG/16
4130          * 04..02  010 = rx clock source is BRG
4131          * 01      0 = auxclk disabled
4132          * 00      1 = BRG enabled
4133          *
4134          * 0110 1001
4135          */
4136         wr_reg8(info, CCR, 0x69);
4137
4138         msc_set_vcr(info);
4139
4140         /* SCR (serial control)
4141          *
4142          * 15  1=tx req on FIFO half empty
4143          * 14  1=rx req on FIFO half full
4144          * 13  tx data  IRQ enable
4145          * 12  tx idle  IRQ enable
4146          * 11  rx break on IRQ enable
4147          * 10  rx data  IRQ enable
4148          * 09  rx break off IRQ enable
4149          * 08  overrun  IRQ enable
4150          * 07  DSR      IRQ enable
4151          * 06  CTS      IRQ enable
4152          * 05  DCD      IRQ enable
4153          * 04  RI       IRQ enable
4154          * 03  0=16x sampling, 1=8x sampling
4155          * 02  1=txd->rxd internal loopback enable
4156          * 01  reserved, must be zero
4157          * 00  1=master IRQ enable
4158          */
4159         val = BIT15 + BIT14 + BIT0;
4160         /* JCR[8] : 1 = x8 async mode feature available */
4161         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4162             ((info->base_clock < (info->params.data_rate * 16)) ||
4163              (info->base_clock % (info->params.data_rate * 16)))) {
4164                 /* use 8x sampling */
4165                 val |= BIT3;
4166                 set_rate(info, info->params.data_rate * 8);
4167         } else {
4168                 /* use 16x sampling */
4169                 set_rate(info, info->params.data_rate * 16);
4170         }
4171         wr_reg16(info, SCR, val);
4172
4173         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4174
4175         if (info->params.loopback)
4176                 enable_loopback(info);
4177 }
4178
4179 static void sync_mode(struct slgt_info *info)
4180 {
4181         unsigned short val;
4182
4183         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4184         tx_stop(info);
4185         rx_stop(info);
4186
4187         /* TCR (tx control)
4188          *
4189          * 15..13  mode
4190          *         000=HDLC/SDLC
4191          *         001=raw bit synchronous
4192          *         010=asynchronous/isochronous
4193          *         011=monosync byte synchronous
4194          *         100=bisync byte synchronous
4195          *         101=xsync byte synchronous
4196          * 12..10  encoding
4197          * 09      CRC enable
4198          * 08      CRC32
4199          * 07      1=RTS driver control
4200          * 06      preamble enable
4201          * 05..04  preamble length
4202          * 03      share open/close flag
4203          * 02      reset
4204          * 01      enable
4205          * 00      auto-CTS enable
4206          */
4207         val = BIT2;
4208
4209         switch(info->params.mode) {
4210         case MGSL_MODE_XSYNC:
4211                 val |= BIT15 + BIT13;
4212                 break;
4213         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4214         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4215         case MGSL_MODE_RAW:      val |= BIT13; break;
4216         }
4217         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4218                 val |= BIT7;
4219
4220         switch(info->params.encoding)
4221         {
4222         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4223         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4224         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4225         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4226         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4227         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4228         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4229         }
4230
4231         switch (info->params.crc_type & HDLC_CRC_MASK)
4232         {
4233         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4234         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4235         }
4236
4237         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4238                 val |= BIT6;
4239
4240         switch (info->params.preamble_length)
4241         {
4242         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4243         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4244         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4245         }
4246
4247         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4248                 val |= BIT0;
4249
4250         wr_reg16(info, TCR, val);
4251
4252         /* TPR (transmit preamble) */
4253
4254         switch (info->params.preamble)
4255         {
4256         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4257         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4258         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4259         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4260         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4261         default:                          val = 0x7e; break;
4262         }
4263         wr_reg8(info, TPR, (unsigned char)val);
4264
4265         /* RCR (rx control)
4266          *
4267          * 15..13  mode
4268          *         000=HDLC/SDLC
4269          *         001=raw bit synchronous
4270          *         010=asynchronous/isochronous
4271          *         011=monosync byte synchronous
4272          *         100=bisync byte synchronous
4273          *         101=xsync byte synchronous
4274          * 12..10  encoding
4275          * 09      CRC enable
4276          * 08      CRC32
4277          * 07..03  reserved, must be 0
4278          * 02      reset
4279          * 01      enable
4280          * 00      auto-DCD enable
4281          */
4282         val = 0;
4283
4284         switch(info->params.mode) {
4285         case MGSL_MODE_XSYNC:
4286                 val |= BIT15 + BIT13;
4287                 break;
4288         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4289         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4290         case MGSL_MODE_RAW:      val |= BIT13; break;
4291         }
4292
4293         switch(info->params.encoding)
4294         {
4295         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4296         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4297         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4298         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4299         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4300         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4301         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4302         }
4303
4304         switch (info->params.crc_type & HDLC_CRC_MASK)
4305         {
4306         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4307         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4308         }
4309
4310         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4311                 val |= BIT0;
4312
4313         wr_reg16(info, RCR, val);
4314
4315         /* CCR (clock control)
4316          *
4317          * 07..05  tx clock source
4318          * 04..02  rx clock source
4319          * 01      auxclk enable
4320          * 00      BRG enable
4321          */
4322         val = 0;
4323
4324         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4325         {
4326                 // when RxC source is DPLL, BRG generates 16X DPLL
4327                 // reference clock, so take TxC from BRG/16 to get
4328                 // transmit clock at actual data rate
4329                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4330                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4331                 else
4332                         val |= BIT6;    /* 010, txclk = BRG */
4333         }
4334         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4335                 val |= BIT7;    /* 100, txclk = DPLL Input */
4336         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4337                 val |= BIT5;    /* 001, txclk = RXC Input */
4338
4339         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4340                 val |= BIT3;    /* 010, rxclk = BRG */
4341         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4342                 val |= BIT4;    /* 100, rxclk = DPLL */
4343         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4344                 val |= BIT2;    /* 001, rxclk = TXC Input */
4345
4346         if (info->params.clock_speed)
4347                 val |= BIT1 + BIT0;
4348
4349         wr_reg8(info, CCR, (unsigned char)val);
4350
4351         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4352         {
4353                 // program DPLL mode
4354                 switch(info->params.encoding)
4355                 {
4356                 case HDLC_ENCODING_BIPHASE_MARK:
4357                 case HDLC_ENCODING_BIPHASE_SPACE:
4358                         val = BIT7; break;
4359                 case HDLC_ENCODING_BIPHASE_LEVEL:
4360                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4361                         val = BIT7 + BIT6; break;
4362                 default: val = BIT6;    // NRZ encodings
4363                 }
4364                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4365
4366                 // DPLL requires a 16X reference clock from BRG
4367                 set_rate(info, info->params.clock_speed * 16);
4368         }
4369         else
4370                 set_rate(info, info->params.clock_speed);
4371
4372         tx_set_idle(info);
4373
4374         msc_set_vcr(info);
4375
4376         /* SCR (serial control)
4377          *
4378          * 15  1=tx req on FIFO half empty
4379          * 14  1=rx req on FIFO half full
4380          * 13  tx data  IRQ enable
4381          * 12  tx idle  IRQ enable
4382          * 11  underrun IRQ enable
4383          * 10  rx data  IRQ enable
4384          * 09  rx idle  IRQ enable
4385          * 08  overrun  IRQ enable
4386          * 07  DSR      IRQ enable
4387          * 06  CTS      IRQ enable
4388          * 05  DCD      IRQ enable
4389          * 04  RI       IRQ enable
4390          * 03  reserved, must be zero
4391          * 02  1=txd->rxd internal loopback enable
4392          * 01  reserved, must be zero
4393          * 00  1=master IRQ enable
4394          */
4395         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4396
4397         if (info->params.loopback)
4398                 enable_loopback(info);
4399 }
4400
4401 /*
4402  *  set transmit idle mode
4403  */
4404 static void tx_set_idle(struct slgt_info *info)
4405 {
4406         unsigned char val;
4407         unsigned short tcr;
4408
4409         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4410          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4411          */
4412         tcr = rd_reg16(info, TCR);
4413         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4414                 /* disable preamble, set idle size to 16 bits */
4415                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4416                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4417                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4418         } else if (!(tcr & BIT6)) {
4419                 /* preamble is disabled, set idle size to 8 bits */
4420                 tcr &= ~(BIT5 + BIT4);
4421         }
4422         wr_reg16(info, TCR, tcr);
4423
4424         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4425                 /* LSB of custom tx idle specified in tx idle register */
4426                 val = (unsigned char)(info->idle_mode & 0xff);
4427         } else {
4428                 /* standard 8 bit idle patterns */
4429                 switch(info->idle_mode)
4430                 {
4431                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4432                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4433                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4434                 case HDLC_TXIDLE_ZEROS:
4435                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4436                 default:                         val = 0xff;
4437                 }
4438         }
4439
4440         wr_reg8(info, TIR, val);
4441 }
4442
4443 /*
4444  * get state of V24 status (input) signals
4445  */
4446 static void get_gtsignals(struct slgt_info *info)
4447 {
4448         unsigned short status = rd_reg16(info, SSR);
4449
4450         /* clear all serial signals except RTS and DTR */
4451         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4452
4453         if (status & BIT3)
4454                 info->signals |= SerialSignal_DSR;
4455         if (status & BIT2)
4456                 info->signals |= SerialSignal_CTS;
4457         if (status & BIT1)
4458                 info->signals |= SerialSignal_DCD;
4459         if (status & BIT0)
4460                 info->signals |= SerialSignal_RI;
4461 }
4462
4463 /*
4464  * set V.24 Control Register based on current configuration
4465  */
4466 static void msc_set_vcr(struct slgt_info *info)
4467 {
4468         unsigned char val = 0;
4469
4470         /* VCR (V.24 control)
4471          *
4472          * 07..04  serial IF select
4473          * 03      DTR
4474          * 02      RTS
4475          * 01      LL
4476          * 00      RL
4477          */
4478
4479         switch(info->if_mode & MGSL_INTERFACE_MASK)
4480         {
4481         case MGSL_INTERFACE_RS232:
4482                 val |= BIT5; /* 0010 */
4483                 break;
4484         case MGSL_INTERFACE_V35:
4485                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4486                 break;
4487         case MGSL_INTERFACE_RS422:
4488                 val |= BIT6; /* 0100 */
4489                 break;
4490         }
4491
4492         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4493                 val |= BIT4;
4494         if (info->signals & SerialSignal_DTR)
4495                 val |= BIT3;
4496         if (info->signals & SerialSignal_RTS)
4497                 val |= BIT2;
4498         if (info->if_mode & MGSL_INTERFACE_LL)
4499                 val |= BIT1;
4500         if (info->if_mode & MGSL_INTERFACE_RL)
4501                 val |= BIT0;
4502         wr_reg8(info, VCR, val);
4503 }
4504
4505 /*
4506  * set state of V24 control (output) signals
4507  */
4508 static void set_gtsignals(struct slgt_info *info)
4509 {
4510         unsigned char val = rd_reg8(info, VCR);
4511         if (info->signals & SerialSignal_DTR)
4512                 val |= BIT3;
4513         else
4514                 val &= ~BIT3;
4515         if (info->signals & SerialSignal_RTS)
4516                 val |= BIT2;
4517         else
4518                 val &= ~BIT2;
4519         wr_reg8(info, VCR, val);
4520 }
4521
4522 /*
4523  * free range of receive DMA buffers (i to last)
4524  */
4525 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4526 {
4527         int done = 0;
4528
4529         while(!done) {
4530                 /* reset current buffer for reuse */
4531                 info->rbufs[i].status = 0;
4532                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4533                 if (i == last)
4534                         done = 1;
4535                 if (++i == info->rbuf_count)
4536                         i = 0;
4537         }
4538         info->rbuf_current = i;
4539 }
4540
4541 /*
4542  * mark all receive DMA buffers as free
4543  */
4544 static void reset_rbufs(struct slgt_info *info)
4545 {
4546         free_rbufs(info, 0, info->rbuf_count - 1);
4547         info->rbuf_fill_index = 0;
4548         info->rbuf_fill_count = 0;
4549 }
4550
4551 /*
4552  * pass receive HDLC frame to upper layer
4553  *
4554  * return true if frame available, otherwise false
4555  */
4556 static bool rx_get_frame(struct slgt_info *info)
4557 {
4558         unsigned int start, end;
4559         unsigned short status;
4560         unsigned int framesize = 0;
4561         unsigned long flags;
4562         struct tty_struct *tty = info->port.tty;
4563         unsigned char addr_field = 0xff;
4564         unsigned int crc_size = 0;
4565
4566         switch (info->params.crc_type & HDLC_CRC_MASK) {
4567         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4568         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4569         }
4570
4571 check_again:
4572
4573         framesize = 0;
4574         addr_field = 0xff;
4575         start = end = info->rbuf_current;
4576
4577         for (;;) {
4578                 if (!desc_complete(info->rbufs[end]))
4579                         goto cleanup;
4580
4581                 if (framesize == 0 && info->params.addr_filter != 0xff)
4582                         addr_field = info->rbufs[end].buf[0];
4583
4584                 framesize += desc_count(info->rbufs[end]);
4585
4586                 if (desc_eof(info->rbufs[end]))
4587                         break;
4588
4589                 if (++end == info->rbuf_count)
4590                         end = 0;
4591
4592                 if (end == info->rbuf_current) {
4593                         if (info->rx_enabled){
4594                                 spin_lock_irqsave(&info->lock,flags);
4595                                 rx_start(info);
4596                                 spin_unlock_irqrestore(&info->lock,flags);
4597                         }
4598                         goto cleanup;
4599                 }
4600         }
4601
4602         /* status
4603          *
4604          * 15      buffer complete
4605          * 14..06  reserved
4606          * 05..04  residue
4607          * 02      eof (end of frame)
4608          * 01      CRC error
4609          * 00      abort
4610          */
4611         status = desc_status(info->rbufs[end]);
4612
4613         /* ignore CRC bit if not using CRC (bit is undefined) */
4614         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4615                 status &= ~BIT1;
4616
4617         if (framesize == 0 ||
4618                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4619                 free_rbufs(info, start, end);
4620                 goto check_again;
4621         }
4622
4623         if (framesize < (2 + crc_size) || status & BIT0) {
4624                 info->icount.rxshort++;
4625                 framesize = 0;
4626         } else if (status & BIT1) {
4627                 info->icount.rxcrc++;
4628                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4629                         framesize = 0;
4630         }
4631
4632 #if SYNCLINK_GENERIC_HDLC
4633         if (framesize == 0) {
4634                 info->netdev->stats.rx_errors++;
4635                 info->netdev->stats.rx_frame_errors++;
4636         }
4637 #endif
4638
4639         DBGBH(("%s rx frame status=%04X size=%d\n",
4640                 info->device_name, status, framesize));
4641         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4642
4643         if (framesize) {
4644                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4645                         framesize -= crc_size;
4646                         crc_size = 0;
4647                 }
4648
4649                 if (framesize > info->max_frame_size + crc_size)
4650                         info->icount.rxlong++;
4651                 else {
4652                         /* copy dma buffer(s) to contiguous temp buffer */
4653                         int copy_count = framesize;
4654                         int i = start;
4655                         unsigned char *p = info->tmp_rbuf;
4656                         info->tmp_rbuf_count = framesize;
4657
4658                         info->icount.rxok++;
4659
4660                         while(copy_count) {
4661                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4662                                 memcpy(p, info->rbufs[i].buf, partial_count);
4663                                 p += partial_count;
4664                                 copy_count -= partial_count;
4665                                 if (++i == info->rbuf_count)
4666                                         i = 0;
4667                         }
4668
4669                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4670                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4671                                 framesize++;
4672                         }
4673
4674 #if SYNCLINK_GENERIC_HDLC
4675                         if (info->netcount)
4676                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4677                         else
4678 #endif
4679                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4680                 }
4681         }
4682         free_rbufs(info, start, end);
4683         return true;
4684
4685 cleanup:
4686         return false;
4687 }
4688
4689 /*
4690  * pass receive buffer (RAW synchronous mode) to tty layer
4691  * return true if buffer available, otherwise false
4692  */
4693 static bool rx_get_buf(struct slgt_info *info)
4694 {
4695         unsigned int i = info->rbuf_current;
4696         unsigned int count;
4697
4698         if (!desc_complete(info->rbufs[i]))
4699                 return false;
4700         count = desc_count(info->rbufs[i]);
4701         switch(info->params.mode) {
4702         case MGSL_MODE_MONOSYNC:
4703         case MGSL_MODE_BISYNC:
4704         case MGSL_MODE_XSYNC:
4705                 /* ignore residue in byte synchronous modes */
4706                 if (desc_residue(info->rbufs[i]))
4707                         count--;
4708                 break;
4709         }
4710         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4711         DBGINFO(("rx_get_buf size=%d\n", count));
4712         if (count)
4713                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4714                                   info->flag_buf, count);
4715         free_rbufs(info, i, i);
4716         return true;
4717 }
4718
4719 static void reset_tbufs(struct slgt_info *info)
4720 {
4721         unsigned int i;
4722         info->tbuf_current = 0;
4723         for (i=0 ; i < info->tbuf_count ; i++) {
4724                 info->tbufs[i].status = 0;
4725                 info->tbufs[i].count  = 0;
4726         }
4727 }
4728
4729 /*
4730  * return number of free transmit DMA buffers
4731  */
4732 static unsigned int free_tbuf_count(struct slgt_info *info)
4733 {
4734         unsigned int count = 0;
4735         unsigned int i = info->tbuf_current;
4736
4737         do
4738         {
4739                 if (desc_count(info->tbufs[i]))
4740                         break; /* buffer in use */
4741                 ++count;
4742                 if (++i == info->tbuf_count)
4743                         i=0;
4744         } while (i != info->tbuf_current);
4745
4746         /* if tx DMA active, last zero count buffer is in use */
4747         if (count && (rd_reg32(info, TDCSR) & BIT0))
4748                 --count;
4749
4750         return count;
4751 }
4752
4753 /*
4754  * return number of bytes in unsent transmit DMA buffers
4755  * and the serial controller tx FIFO
4756  */
4757 static unsigned int tbuf_bytes(struct slgt_info *info)
4758 {
4759         unsigned int total_count = 0;
4760         unsigned int i = info->tbuf_current;
4761         unsigned int reg_value;
4762         unsigned int count;
4763         unsigned int active_buf_count = 0;
4764
4765         /*
4766          * Add descriptor counts for all tx DMA buffers.
4767          * If count is zero (cleared by DMA controller after read),
4768          * the buffer is complete or is actively being read from.
4769          *
4770          * Record buf_count of last buffer with zero count starting
4771          * from current ring position. buf_count is mirror
4772          * copy of count and is not cleared by serial controller.
4773          * If DMA controller is active, that buffer is actively
4774          * being read so add to total.
4775          */
4776         do {
4777                 count = desc_count(info->tbufs[i]);
4778                 if (count)
4779                         total_count += count;
4780                 else if (!total_count)
4781                         active_buf_count = info->tbufs[i].buf_count;
4782                 if (++i == info->tbuf_count)
4783                         i = 0;
4784         } while (i != info->tbuf_current);
4785
4786         /* read tx DMA status register */
4787         reg_value = rd_reg32(info, TDCSR);
4788
4789         /* if tx DMA active, last zero count buffer is in use */
4790         if (reg_value & BIT0)
4791                 total_count += active_buf_count;
4792
4793         /* add tx FIFO count = reg_value[15..8] */
4794         total_count += (reg_value >> 8) & 0xff;
4795
4796         /* if transmitter active add one byte for shift register */
4797         if (info->tx_active)
4798                 total_count++;
4799
4800         return total_count;
4801 }
4802
4803 /*
4804  * load data into transmit DMA buffer ring and start transmitter if needed
4805  * return true if data accepted, otherwise false (buffers full)
4806  */
4807 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4808 {
4809         unsigned short count;
4810         unsigned int i;
4811         struct slgt_desc *d;
4812
4813         /* check required buffer space */
4814         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4815                 return false;
4816
4817         DBGDATA(info, buf, size, "tx");
4818
4819         /*
4820          * copy data to one or more DMA buffers in circular ring
4821          * tbuf_start   = first buffer for this data
4822          * tbuf_current = next free buffer
4823          *
4824          * Copy all data before making data visible to DMA controller by
4825          * setting descriptor count of the first buffer.
4826          * This prevents an active DMA controller from reading the first DMA
4827          * buffers of a frame and stopping before the final buffers are filled.
4828          */
4829
4830         info->tbuf_start = i = info->tbuf_current;
4831
4832         while (size) {
4833                 d = &info->tbufs[i];
4834
4835                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4836                 memcpy(d->buf, buf, count);
4837
4838                 size -= count;
4839                 buf  += count;
4840
4841                 /*
4842                  * set EOF bit for last buffer of HDLC frame or
4843                  * for every buffer in raw mode
4844                  */
4845                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4846                     info->params.mode == MGSL_MODE_RAW)
4847                         set_desc_eof(*d, 1);
4848                 else
4849                         set_desc_eof(*d, 0);
4850
4851                 /* set descriptor count for all but first buffer */
4852                 if (i != info->tbuf_start)
4853                         set_desc_count(*d, count);
4854                 d->buf_count = count;
4855
4856                 if (++i == info->tbuf_count)
4857                         i = 0;
4858         }
4859
4860         info->tbuf_current = i;
4861
4862         /* set first buffer count to make new data visible to DMA controller */
4863         d = &info->tbufs[info->tbuf_start];
4864         set_desc_count(*d, d->buf_count);
4865
4866         /* start transmitter if needed and update transmit timeout */
4867         if (!info->tx_active)
4868                 tx_start(info);
4869         update_tx_timer(info);
4870
4871         return true;
4872 }
4873
4874 static int register_test(struct slgt_info *info)
4875 {
4876         static unsigned short patterns[] =
4877                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4878         static unsigned int count = ARRAY_SIZE(patterns);
4879         unsigned int i;
4880         int rc = 0;
4881
4882         for (i=0 ; i < count ; i++) {
4883                 wr_reg16(info, TIR, patterns[i]);
4884                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4885                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4886                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4887                         rc = -ENODEV;
4888                         break;
4889                 }
4890         }
4891         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4892         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4893         return rc;
4894 }
4895
4896 static int irq_test(struct slgt_info *info)
4897 {
4898         unsigned long timeout;
4899         unsigned long flags;
4900         struct tty_struct *oldtty = info->port.tty;
4901         u32 speed = info->params.data_rate;
4902
4903         info->params.data_rate = 921600;
4904         info->port.tty = NULL;
4905
4906         spin_lock_irqsave(&info->lock, flags);
4907         async_mode(info);
4908         slgt_irq_on(info, IRQ_TXIDLE);
4909
4910         /* enable transmitter */
4911         wr_reg16(info, TCR,
4912                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4913
4914         /* write one byte and wait for tx idle */
4915         wr_reg16(info, TDR, 0);
4916
4917         /* assume failure */
4918         info->init_error = DiagStatus_IrqFailure;
4919         info->irq_occurred = false;
4920
4921         spin_unlock_irqrestore(&info->lock, flags);
4922
4923         timeout=100;
4924         while(timeout-- && !info->irq_occurred)
4925                 msleep_interruptible(10);
4926
4927         spin_lock_irqsave(&info->lock,flags);
4928         reset_port(info);
4929         spin_unlock_irqrestore(&info->lock,flags);
4930
4931         info->params.data_rate = speed;
4932         info->port.tty = oldtty;
4933
4934         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4935         return info->irq_occurred ? 0 : -ENODEV;
4936 }
4937
4938 static int loopback_test_rx(struct slgt_info *info)
4939 {
4940         unsigned char *src, *dest;
4941         int count;
4942
4943         if (desc_complete(info->rbufs[0])) {
4944                 count = desc_count(info->rbufs[0]);
4945                 src   = info->rbufs[0].buf;
4946                 dest  = info->tmp_rbuf;
4947
4948                 for( ; count ; count-=2, src+=2) {
4949                         /* src=data byte (src+1)=status byte */
4950                         if (!(*(src+1) & (BIT9 + BIT8))) {
4951                                 *dest = *src;
4952                                 dest++;
4953                                 info->tmp_rbuf_count++;
4954                         }
4955                 }
4956                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4957                 return 1;
4958         }
4959         return 0;
4960 }
4961
4962 static int loopback_test(struct slgt_info *info)
4963 {
4964 #define TESTFRAMESIZE 20
4965
4966         unsigned long timeout;
4967         u16 count = TESTFRAMESIZE;
4968         unsigned char buf[TESTFRAMESIZE];
4969         int rc = -ENODEV;
4970         unsigned long flags;
4971
4972         struct tty_struct *oldtty = info->port.tty;
4973         MGSL_PARAMS params;
4974
4975         memcpy(&params, &info->params, sizeof(params));
4976
4977         info->params.mode = MGSL_MODE_ASYNC;
4978         info->params.data_rate = 921600;
4979         info->params.loopback = 1;
4980         info->port.tty = NULL;
4981
4982         /* build and send transmit frame */
4983         for (count = 0; count < TESTFRAMESIZE; ++count)
4984                 buf[count] = (unsigned char)count;
4985
4986         info->tmp_rbuf_count = 0;
4987         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4988
4989         /* program hardware for HDLC and enabled receiver */
4990         spin_lock_irqsave(&info->lock,flags);
4991         async_mode(info);
4992         rx_start(info);
4993         tx_load(info, buf, count);
4994         spin_unlock_irqrestore(&info->lock, flags);
4995
4996         /* wait for receive complete */
4997         for (timeout = 100; timeout; --timeout) {
4998                 msleep_interruptible(10);
4999                 if (loopback_test_rx(info)) {
5000                         rc = 0;
5001                         break;
5002                 }
5003         }
5004
5005         /* verify received frame length and contents */
5006         if (!rc && (info->tmp_rbuf_count != count ||
5007                   memcmp(buf, info->tmp_rbuf, count))) {
5008                 rc = -ENODEV;
5009         }
5010
5011         spin_lock_irqsave(&info->lock,flags);
5012         reset_adapter(info);
5013         spin_unlock_irqrestore(&info->lock,flags);
5014
5015         memcpy(&info->params, &params, sizeof(info->params));
5016         info->port.tty = oldtty;
5017
5018         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5019         return rc;
5020 }
5021
5022 static int adapter_test(struct slgt_info *info)
5023 {
5024         DBGINFO(("testing %s\n", info->device_name));
5025         if (register_test(info) < 0) {
5026                 printk("register test failure %s addr=%08X\n",
5027                         info->device_name, info->phys_reg_addr);
5028         } else if (irq_test(info) < 0) {
5029                 printk("IRQ test failure %s IRQ=%d\n",
5030                         info->device_name, info->irq_level);
5031         } else if (loopback_test(info) < 0) {
5032                 printk("loopback test failure %s\n", info->device_name);
5033         }
5034         return info->init_error;
5035 }
5036
5037 /*
5038  * transmit timeout handler
5039  */
5040 static void tx_timeout(struct timer_list *t)
5041 {
5042         struct slgt_info *info = from_timer(info, t, tx_timer);
5043         unsigned long flags;
5044
5045         DBGINFO(("%s tx_timeout\n", info->device_name));
5046         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5047                 info->icount.txtimeout++;
5048         }
5049         spin_lock_irqsave(&info->lock,flags);
5050         tx_stop(info);
5051         spin_unlock_irqrestore(&info->lock,flags);
5052
5053 #if SYNCLINK_GENERIC_HDLC
5054         if (info->netcount)
5055                 hdlcdev_tx_done(info);
5056         else
5057 #endif
5058                 bh_transmit(info);
5059 }
5060
5061 /*
5062  * receive buffer polling timer
5063  */
5064 static void rx_timeout(struct timer_list *t)
5065 {
5066         struct slgt_info *info = from_timer(info, t, rx_timer);
5067         unsigned long flags;
5068
5069         DBGINFO(("%s rx_timeout\n", info->device_name));
5070         spin_lock_irqsave(&info->lock, flags);
5071         info->pending_bh |= BH_RECEIVE;
5072         spin_unlock_irqrestore(&info->lock, flags);
5073         bh_handler(&info->task);
5074 }
5075