2 * Device driver for Microgate SyncLink GT serial adapters.
4 * written by Paul Fulghum for Microgate Corporation
7 * Microgate and SyncLink are trademarks of Microgate Corporation
9 * This code is released under the GNU General Public License (GPL)
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
25 * DEBUG OUTPUT DEFINITIONS
27 * uncomment lines below to enable specific types of debug output
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 /*#define DBGTBUF(info) dump_tbufs(info)*/
44 /*#define DBGRBUF(info) dump_rbufs(info)*/
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/netdevice.h>
66 #include <linux/vmalloc.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/ioctl.h>
70 #include <linux/termios.h>
71 #include <linux/bitops.h>
72 #include <linux/workqueue.h>
73 #include <linux/hdlc.h>
74 #include <linux/synclink.h>
79 #include <asm/types.h>
80 #include <asm/uaccess.h>
82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
83 #define SYNCLINK_GENERIC_HDLC 1
85 #define SYNCLINK_GENERIC_HDLC 0
89 * module identification
91 static char *driver_name = "SyncLink GT";
92 static char *tty_driver_name = "synclink_gt";
93 static char *tty_dev_prefix = "ttySLG";
94 MODULE_LICENSE("GPL");
95 #define MGSL_MAGIC 0x5401
96 #define MAX_DEVICES 32
98 static struct pci_device_id pci_table[] = {
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {0,}, /* terminate list */
105 MODULE_DEVICE_TABLE(pci, pci_table);
107 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
108 static void remove_one(struct pci_dev *dev);
109 static struct pci_driver pci_driver = {
110 .name = "synclink_gt",
111 .id_table = pci_table,
113 .remove = remove_one,
116 static bool pci_registered;
119 * module configuration and status
121 static struct slgt_info *slgt_device_list;
122 static int slgt_device_count;
125 static int debug_level;
126 static int maxframe[MAX_DEVICES];
128 module_param(ttymajor, int, 0);
129 module_param(debug_level, int, 0);
130 module_param_array(maxframe, int, NULL, 0);
132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
137 * tty support and callbacks
139 static struct tty_driver *serial_driver;
141 static int open(struct tty_struct *tty, struct file * filp);
142 static void close(struct tty_struct *tty, struct file * filp);
143 static void hangup(struct tty_struct *tty);
144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
146 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
147 static int put_char(struct tty_struct *tty, unsigned char ch);
148 static void send_xchar(struct tty_struct *tty, char ch);
149 static void wait_until_sent(struct tty_struct *tty, int timeout);
150 static int write_room(struct tty_struct *tty);
151 static void flush_chars(struct tty_struct *tty);
152 static void flush_buffer(struct tty_struct *tty);
153 static void tx_hold(struct tty_struct *tty);
154 static void tx_release(struct tty_struct *tty);
156 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
157 static int chars_in_buffer(struct tty_struct *tty);
158 static void throttle(struct tty_struct * tty);
159 static void unthrottle(struct tty_struct * tty);
160 static int set_break(struct tty_struct *tty, int break_state);
163 * generic HDLC support and callbacks
165 #if SYNCLINK_GENERIC_HDLC
166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
167 static void hdlcdev_tx_done(struct slgt_info *info);
168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
169 static int hdlcdev_init(struct slgt_info *info);
170 static void hdlcdev_exit(struct slgt_info *info);
175 * device specific structures, macros and functions
178 #define SLGT_MAX_PORTS 4
179 #define SLGT_REG_SIZE 256
182 * conditional wait facility
185 struct cond_wait *next;
190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void flush_cond_wait(struct cond_wait **head);
196 * DMA buffer descriptor and access macros
202 __le32 pbuf; /* physical address of data buffer */
203 __le32 next; /* physical address of next descriptor */
205 /* driver book keeping */
206 char *buf; /* virtual address of data buffer */
207 unsigned int pdesc; /* physical address of this descriptor */
208 dma_addr_t buf_dma_addr;
209 unsigned short buf_count;
212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
213 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
214 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
215 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
217 #define desc_count(a) (le16_to_cpu((a).count))
218 #define desc_status(a) (le16_to_cpu((a).status))
219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
225 struct _input_signal_events {
237 * device instance data structure
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
243 struct slgt_info *next_device; /* device list link */
247 char device_name[25];
248 struct pci_dev *pdev;
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
257 int line; /* tty line instance number */
259 struct mgsl_icount icount;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
276 struct work_struct task;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
285 /* device configuration */
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
293 bool reg_addr_requested;
295 MGSL_PARAMS params; /* communications parameters */
297 u32 max_frame_size; /* as set by device config */
299 unsigned int rbuf_fill_level;
301 unsigned int if_mode;
302 unsigned int base_clock;
314 unsigned char signals; /* serial signal states */
315 int init_error; /* initialization error */
317 unsigned char *tx_buf;
321 bool drop_rts_on_tx_done;
322 struct _input_signal_events input_signal_events;
324 int dcd_chkcount; /* check counts to prevent */
325 int cts_chkcount; /* too many IRQs if a signal */
326 int dsr_chkcount; /* is floating */
329 char *bufs; /* virtual address of DMA buffer lists */
330 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
332 unsigned int rbuf_count;
333 struct slgt_desc *rbufs;
334 unsigned int rbuf_current;
335 unsigned int rbuf_index;
336 unsigned int rbuf_fill_index;
337 unsigned short rbuf_fill_count;
339 unsigned int tbuf_count;
340 struct slgt_desc *tbufs;
341 unsigned int tbuf_current;
342 unsigned int tbuf_start;
344 unsigned char *tmp_rbuf;
345 unsigned int tmp_rbuf_count;
347 /* SPPP/Cisco HDLC device parts */
351 #if SYNCLINK_GENERIC_HDLC
352 struct net_device *netdev;
357 static MGSL_PARAMS default_params = {
358 .mode = MGSL_MODE_HDLC,
360 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
361 .encoding = HDLC_ENCODING_NRZI_SPACE,
364 .crc_type = HDLC_CRC_16_CCITT,
365 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
366 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
370 .parity = ASYNC_PARITY_NONE
375 #define BH_TRANSMIT 2
377 #define IO_PIN_SHUTDOWN_LIMIT 100
379 #define DMABUFSIZE 256
380 #define DESC_LIST_SIZE 4096
382 #define MASK_PARITY BIT1
383 #define MASK_FRAMING BIT0
384 #define MASK_BREAK BIT14
385 #define MASK_OVERRUN BIT4
387 #define GSR 0x00 /* global status */
388 #define JCR 0x04 /* JTAG control */
389 #define IODR 0x08 /* GPIO direction */
390 #define IOER 0x0c /* GPIO interrupt enable */
391 #define IOVR 0x10 /* GPIO value */
392 #define IOSR 0x14 /* GPIO interrupt status */
393 #define TDR 0x80 /* tx data */
394 #define RDR 0x80 /* rx data */
395 #define TCR 0x82 /* tx control */
396 #define TIR 0x84 /* tx idle */
397 #define TPR 0x85 /* tx preamble */
398 #define RCR 0x86 /* rx control */
399 #define VCR 0x88 /* V.24 control */
400 #define CCR 0x89 /* clock control */
401 #define BDR 0x8a /* baud divisor */
402 #define SCR 0x8c /* serial control */
403 #define SSR 0x8e /* serial status */
404 #define RDCSR 0x90 /* rx DMA control/status */
405 #define TDCSR 0x94 /* tx DMA control/status */
406 #define RDDAR 0x98 /* rx DMA descriptor address */
407 #define TDDAR 0x9c /* tx DMA descriptor address */
408 #define XSR 0x40 /* extended sync pattern */
409 #define XCR 0x44 /* extended control */
412 #define RXBREAK BIT14
413 #define IRQ_TXDATA BIT13
414 #define IRQ_TXIDLE BIT12
415 #define IRQ_TXUNDER BIT11 /* HDLC */
416 #define IRQ_RXDATA BIT10
417 #define IRQ_RXIDLE BIT9 /* HDLC */
418 #define IRQ_RXBREAK BIT9 /* async */
419 #define IRQ_RXOVER BIT8
424 #define IRQ_ALL 0x3ff0
425 #define IRQ_MASTER BIT0
427 #define slgt_irq_on(info, mask) \
428 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
429 #define slgt_irq_off(info, mask) \
430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
432 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
433 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
435 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
437 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
439 static void msc_set_vcr(struct slgt_info *info);
441 static int startup(struct slgt_info *info);
442 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
443 static void shutdown(struct slgt_info *info);
444 static void program_hw(struct slgt_info *info);
445 static void change_params(struct slgt_info *info);
447 static int register_test(struct slgt_info *info);
448 static int irq_test(struct slgt_info *info);
449 static int loopback_test(struct slgt_info *info);
450 static int adapter_test(struct slgt_info *info);
452 static void reset_adapter(struct slgt_info *info);
453 static void reset_port(struct slgt_info *info);
454 static void async_mode(struct slgt_info *info);
455 static void sync_mode(struct slgt_info *info);
457 static void rx_stop(struct slgt_info *info);
458 static void rx_start(struct slgt_info *info);
459 static void reset_rbufs(struct slgt_info *info);
460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
461 static void rdma_reset(struct slgt_info *info);
462 static bool rx_get_frame(struct slgt_info *info);
463 static bool rx_get_buf(struct slgt_info *info);
465 static void tx_start(struct slgt_info *info);
466 static void tx_stop(struct slgt_info *info);
467 static void tx_set_idle(struct slgt_info *info);
468 static unsigned int free_tbuf_count(struct slgt_info *info);
469 static unsigned int tbuf_bytes(struct slgt_info *info);
470 static void reset_tbufs(struct slgt_info *info);
471 static void tdma_reset(struct slgt_info *info);
472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
474 static void get_signals(struct slgt_info *info);
475 static void set_signals(struct slgt_info *info);
476 static void enable_loopback(struct slgt_info *info);
477 static void set_rate(struct slgt_info *info, u32 data_rate);
479 static int bh_action(struct slgt_info *info);
480 static void bh_handler(struct work_struct *work);
481 static void bh_transmit(struct slgt_info *info);
482 static void isr_serial(struct slgt_info *info);
483 static void isr_rdma(struct slgt_info *info);
484 static void isr_txeom(struct slgt_info *info, unsigned short status);
485 static void isr_tdma(struct slgt_info *info);
487 static int alloc_dma_bufs(struct slgt_info *info);
488 static void free_dma_bufs(struct slgt_info *info);
489 static int alloc_desc(struct slgt_info *info);
490 static void free_desc(struct slgt_info *info);
491 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
494 static int alloc_tmp_rbuf(struct slgt_info *info);
495 static void free_tmp_rbuf(struct slgt_info *info);
497 static void tx_timeout(unsigned long context);
498 static void rx_timeout(unsigned long context);
503 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
504 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
505 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
506 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
507 static int set_txidle(struct slgt_info *info, int idle_mode);
508 static int tx_enable(struct slgt_info *info, int enable);
509 static int tx_abort(struct slgt_info *info);
510 static int rx_enable(struct slgt_info *info, int enable);
511 static int modem_input_wait(struct slgt_info *info,int arg);
512 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
513 static int tiocmget(struct tty_struct *tty);
514 static int tiocmset(struct tty_struct *tty,
515 unsigned int set, unsigned int clear);
516 static int set_break(struct tty_struct *tty, int break_state);
517 static int get_interface(struct slgt_info *info, int __user *if_mode);
518 static int set_interface(struct slgt_info *info, int if_mode);
519 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
520 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
521 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522 static int get_xsync(struct slgt_info *info, int __user *if_mode);
523 static int set_xsync(struct slgt_info *info, int if_mode);
524 static int get_xctrl(struct slgt_info *info, int __user *if_mode);
525 static int set_xctrl(struct slgt_info *info, int if_mode);
530 static void add_device(struct slgt_info *info);
531 static void device_init(int adapter_num, struct pci_dev *pdev);
532 static int claim_resources(struct slgt_info *info);
533 static void release_resources(struct slgt_info *info);
552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
556 printk("%s %s data:\n",info->device_name, label);
558 linecount = (count > 16) ? 16 : count;
559 for(i=0; i < linecount; i++)
560 printk("%02X ",(unsigned char)data[i]);
563 for(i=0;i<linecount;i++) {
564 if (data[i]>=040 && data[i]<=0176)
565 printk("%c",data[i]);
575 #define DBGDATA(info, buf, size, label)
579 static void dump_tbufs(struct slgt_info *info)
582 printk("tbuf_current=%d\n", info->tbuf_current);
583 for (i=0 ; i < info->tbuf_count ; i++) {
584 printk("%d: count=%04X status=%04X\n",
585 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
589 #define DBGTBUF(info)
593 static void dump_rbufs(struct slgt_info *info)
596 printk("rbuf_current=%d\n", info->rbuf_current);
597 for (i=0 ; i < info->rbuf_count ; i++) {
598 printk("%d: count=%04X status=%04X\n",
599 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
603 #define DBGRBUF(info)
606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
610 printk("null struct slgt_info for (%s) in %s\n", devname, name);
613 if (info->magic != MGSL_MAGIC) {
614 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
625 * line discipline callback wrappers
627 * The wrappers maintain line discipline references
628 * while calling into the line discipline.
630 * ldisc_receive_buf - pass receive data to line discipline
632 static void ldisc_receive_buf(struct tty_struct *tty,
633 const __u8 *data, char *flags, int count)
635 struct tty_ldisc *ld;
638 ld = tty_ldisc_ref(tty);
640 if (ld->ops->receive_buf)
641 ld->ops->receive_buf(tty, data, flags, count);
648 static int open(struct tty_struct *tty, struct file *filp)
650 struct slgt_info *info;
655 if (line >= slgt_device_count) {
656 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
660 info = slgt_device_list;
661 while(info && info->line != line)
662 info = info->next_device;
663 if (sanity_check(info, tty->name, "open"))
665 if (info->init_error) {
666 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
670 tty->driver_data = info;
671 info->port.tty = tty;
673 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
675 mutex_lock(&info->port.mutex);
676 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
678 spin_lock_irqsave(&info->netlock, flags);
679 if (info->netcount) {
681 spin_unlock_irqrestore(&info->netlock, flags);
682 mutex_unlock(&info->port.mutex);
686 spin_unlock_irqrestore(&info->netlock, flags);
688 if (info->port.count == 1) {
689 /* 1st open on this device, init hardware */
690 retval = startup(info);
692 mutex_unlock(&info->port.mutex);
696 mutex_unlock(&info->port.mutex);
697 retval = block_til_ready(tty, filp, info);
699 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
708 info->port.tty = NULL; /* tty layer will release tty struct */
713 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
717 static void close(struct tty_struct *tty, struct file *filp)
719 struct slgt_info *info = tty->driver_data;
721 if (sanity_check(info, tty->name, "close"))
723 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
725 if (tty_port_close_start(&info->port, tty, filp) == 0)
728 mutex_lock(&info->port.mutex);
729 if (info->port.flags & ASYNC_INITIALIZED)
730 wait_until_sent(tty, info->timeout);
732 tty_ldisc_flush(tty);
735 mutex_unlock(&info->port.mutex);
737 tty_port_close_end(&info->port, tty);
738 info->port.tty = NULL;
740 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
743 static void hangup(struct tty_struct *tty)
745 struct slgt_info *info = tty->driver_data;
748 if (sanity_check(info, tty->name, "hangup"))
750 DBGINFO(("%s hangup\n", info->device_name));
754 mutex_lock(&info->port.mutex);
757 spin_lock_irqsave(&info->port.lock, flags);
758 info->port.count = 0;
759 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
760 info->port.tty = NULL;
761 spin_unlock_irqrestore(&info->port.lock, flags);
762 mutex_unlock(&info->port.mutex);
764 wake_up_interruptible(&info->port.open_wait);
767 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
769 struct slgt_info *info = tty->driver_data;
772 DBGINFO(("%s set_termios\n", tty->driver->name));
776 /* Handle transition to B0 status */
777 if (old_termios->c_cflag & CBAUD &&
778 !(tty->termios.c_cflag & CBAUD)) {
779 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
780 spin_lock_irqsave(&info->lock,flags);
782 spin_unlock_irqrestore(&info->lock,flags);
785 /* Handle transition away from B0 status */
786 if (!(old_termios->c_cflag & CBAUD) &&
787 tty->termios.c_cflag & CBAUD) {
788 info->signals |= SerialSignal_DTR;
789 if (!(tty->termios.c_cflag & CRTSCTS) ||
790 !test_bit(TTY_THROTTLED, &tty->flags)) {
791 info->signals |= SerialSignal_RTS;
793 spin_lock_irqsave(&info->lock,flags);
795 spin_unlock_irqrestore(&info->lock,flags);
798 /* Handle turning off CRTSCTS */
799 if (old_termios->c_cflag & CRTSCTS &&
800 !(tty->termios.c_cflag & CRTSCTS)) {
806 static void update_tx_timer(struct slgt_info *info)
809 * use worst case speed of 1200bps to calculate transmit timeout
810 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
812 if (info->params.mode == MGSL_MODE_HDLC) {
813 int timeout = (tbuf_bytes(info) * 7) + 1000;
814 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
818 static int write(struct tty_struct *tty,
819 const unsigned char *buf, int count)
822 struct slgt_info *info = tty->driver_data;
825 if (sanity_check(info, tty->name, "write"))
828 DBGINFO(("%s write count=%d\n", info->device_name, count));
830 if (!info->tx_buf || (count > info->max_frame_size))
833 if (!count || tty->stopped || tty->hw_stopped)
836 spin_lock_irqsave(&info->lock, flags);
838 if (info->tx_count) {
839 /* send accumulated data from send_char() */
840 if (!tx_load(info, info->tx_buf, info->tx_count))
845 if (tx_load(info, buf, count))
849 spin_unlock_irqrestore(&info->lock, flags);
850 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
854 static int put_char(struct tty_struct *tty, unsigned char ch)
856 struct slgt_info *info = tty->driver_data;
860 if (sanity_check(info, tty->name, "put_char"))
862 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
865 spin_lock_irqsave(&info->lock,flags);
866 if (info->tx_count < info->max_frame_size) {
867 info->tx_buf[info->tx_count++] = ch;
870 spin_unlock_irqrestore(&info->lock,flags);
874 static void send_xchar(struct tty_struct *tty, char ch)
876 struct slgt_info *info = tty->driver_data;
879 if (sanity_check(info, tty->name, "send_xchar"))
881 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
884 spin_lock_irqsave(&info->lock,flags);
885 if (!info->tx_enabled)
887 spin_unlock_irqrestore(&info->lock,flags);
891 static void wait_until_sent(struct tty_struct *tty, int timeout)
893 struct slgt_info *info = tty->driver_data;
894 unsigned long orig_jiffies, char_time;
898 if (sanity_check(info, tty->name, "wait_until_sent"))
900 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
901 if (!(info->port.flags & ASYNC_INITIALIZED))
904 orig_jiffies = jiffies;
906 /* Set check interval to 1/5 of estimated time to
907 * send a character, and make it at least 1. The check
908 * interval should also be less than the timeout.
909 * Note: use tight timings here to satisfy the NIST-PCTS.
912 if (info->params.data_rate) {
913 char_time = info->timeout/(32 * 5);
920 char_time = min_t(unsigned long, char_time, timeout);
922 while (info->tx_active) {
923 msleep_interruptible(jiffies_to_msecs(char_time));
924 if (signal_pending(current))
926 if (timeout && time_after(jiffies, orig_jiffies + timeout))
930 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
933 static int write_room(struct tty_struct *tty)
935 struct slgt_info *info = tty->driver_data;
938 if (sanity_check(info, tty->name, "write_room"))
940 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
941 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
945 static void flush_chars(struct tty_struct *tty)
947 struct slgt_info *info = tty->driver_data;
950 if (sanity_check(info, tty->name, "flush_chars"))
952 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
954 if (info->tx_count <= 0 || tty->stopped ||
955 tty->hw_stopped || !info->tx_buf)
958 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
960 spin_lock_irqsave(&info->lock,flags);
961 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
963 spin_unlock_irqrestore(&info->lock,flags);
966 static void flush_buffer(struct tty_struct *tty)
968 struct slgt_info *info = tty->driver_data;
971 if (sanity_check(info, tty->name, "flush_buffer"))
973 DBGINFO(("%s flush_buffer\n", info->device_name));
975 spin_lock_irqsave(&info->lock, flags);
977 spin_unlock_irqrestore(&info->lock, flags);
983 * throttle (stop) transmitter
985 static void tx_hold(struct tty_struct *tty)
987 struct slgt_info *info = tty->driver_data;
990 if (sanity_check(info, tty->name, "tx_hold"))
992 DBGINFO(("%s tx_hold\n", info->device_name));
993 spin_lock_irqsave(&info->lock,flags);
994 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
996 spin_unlock_irqrestore(&info->lock,flags);
1000 * release (start) transmitter
1002 static void tx_release(struct tty_struct *tty)
1004 struct slgt_info *info = tty->driver_data;
1005 unsigned long flags;
1007 if (sanity_check(info, tty->name, "tx_release"))
1009 DBGINFO(("%s tx_release\n", info->device_name));
1010 spin_lock_irqsave(&info->lock, flags);
1011 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1013 spin_unlock_irqrestore(&info->lock, flags);
1017 * Service an IOCTL request
1021 * tty pointer to tty instance data
1022 * cmd IOCTL command code
1023 * arg command argument/context
1025 * Return 0 if success, otherwise error code
1027 static int ioctl(struct tty_struct *tty,
1028 unsigned int cmd, unsigned long arg)
1030 struct slgt_info *info = tty->driver_data;
1031 void __user *argp = (void __user *)arg;
1034 if (sanity_check(info, tty->name, "ioctl"))
1036 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1038 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1039 (cmd != TIOCMIWAIT)) {
1040 if (tty->flags & (1 << TTY_IO_ERROR))
1045 case MGSL_IOCWAITEVENT:
1046 return wait_mgsl_event(info, argp);
1048 return modem_input_wait(info,(int)arg);
1050 return set_gpio(info, argp);
1052 return get_gpio(info, argp);
1053 case MGSL_IOCWAITGPIO:
1054 return wait_gpio(info, argp);
1055 case MGSL_IOCGXSYNC:
1056 return get_xsync(info, argp);
1057 case MGSL_IOCSXSYNC:
1058 return set_xsync(info, (int)arg);
1059 case MGSL_IOCGXCTRL:
1060 return get_xctrl(info, argp);
1061 case MGSL_IOCSXCTRL:
1062 return set_xctrl(info, (int)arg);
1064 mutex_lock(&info->port.mutex);
1066 case MGSL_IOCGPARAMS:
1067 ret = get_params(info, argp);
1069 case MGSL_IOCSPARAMS:
1070 ret = set_params(info, argp);
1072 case MGSL_IOCGTXIDLE:
1073 ret = get_txidle(info, argp);
1075 case MGSL_IOCSTXIDLE:
1076 ret = set_txidle(info, (int)arg);
1078 case MGSL_IOCTXENABLE:
1079 ret = tx_enable(info, (int)arg);
1081 case MGSL_IOCRXENABLE:
1082 ret = rx_enable(info, (int)arg);
1084 case MGSL_IOCTXABORT:
1085 ret = tx_abort(info);
1087 case MGSL_IOCGSTATS:
1088 ret = get_stats(info, argp);
1091 ret = get_interface(info, argp);
1094 ret = set_interface(info,(int)arg);
1099 mutex_unlock(&info->port.mutex);
1103 static int get_icount(struct tty_struct *tty,
1104 struct serial_icounter_struct *icount)
1107 struct slgt_info *info = tty->driver_data;
1108 struct mgsl_icount cnow; /* kernel counter temps */
1109 unsigned long flags;
1111 spin_lock_irqsave(&info->lock,flags);
1112 cnow = info->icount;
1113 spin_unlock_irqrestore(&info->lock,flags);
1115 icount->cts = cnow.cts;
1116 icount->dsr = cnow.dsr;
1117 icount->rng = cnow.rng;
1118 icount->dcd = cnow.dcd;
1119 icount->rx = cnow.rx;
1120 icount->tx = cnow.tx;
1121 icount->frame = cnow.frame;
1122 icount->overrun = cnow.overrun;
1123 icount->parity = cnow.parity;
1124 icount->brk = cnow.brk;
1125 icount->buf_overrun = cnow.buf_overrun;
1131 * support for 32 bit ioctl calls on 64 bit systems
1133 #ifdef CONFIG_COMPAT
1134 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1136 struct MGSL_PARAMS32 tmp_params;
1138 DBGINFO(("%s get_params32\n", info->device_name));
1139 memset(&tmp_params, 0, sizeof(tmp_params));
1140 tmp_params.mode = (compat_ulong_t)info->params.mode;
1141 tmp_params.loopback = info->params.loopback;
1142 tmp_params.flags = info->params.flags;
1143 tmp_params.encoding = info->params.encoding;
1144 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1145 tmp_params.addr_filter = info->params.addr_filter;
1146 tmp_params.crc_type = info->params.crc_type;
1147 tmp_params.preamble_length = info->params.preamble_length;
1148 tmp_params.preamble = info->params.preamble;
1149 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1150 tmp_params.data_bits = info->params.data_bits;
1151 tmp_params.stop_bits = info->params.stop_bits;
1152 tmp_params.parity = info->params.parity;
1153 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1158 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1160 struct MGSL_PARAMS32 tmp_params;
1162 DBGINFO(("%s set_params32\n", info->device_name));
1163 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1166 spin_lock(&info->lock);
1167 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1168 info->base_clock = tmp_params.clock_speed;
1170 info->params.mode = tmp_params.mode;
1171 info->params.loopback = tmp_params.loopback;
1172 info->params.flags = tmp_params.flags;
1173 info->params.encoding = tmp_params.encoding;
1174 info->params.clock_speed = tmp_params.clock_speed;
1175 info->params.addr_filter = tmp_params.addr_filter;
1176 info->params.crc_type = tmp_params.crc_type;
1177 info->params.preamble_length = tmp_params.preamble_length;
1178 info->params.preamble = tmp_params.preamble;
1179 info->params.data_rate = tmp_params.data_rate;
1180 info->params.data_bits = tmp_params.data_bits;
1181 info->params.stop_bits = tmp_params.stop_bits;
1182 info->params.parity = tmp_params.parity;
1184 spin_unlock(&info->lock);
1191 static long slgt_compat_ioctl(struct tty_struct *tty,
1192 unsigned int cmd, unsigned long arg)
1194 struct slgt_info *info = tty->driver_data;
1197 if (sanity_check(info, tty->name, "compat_ioctl"))
1199 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1202 case MGSL_IOCSPARAMS32:
1203 rc = set_params32(info, compat_ptr(arg));
1206 case MGSL_IOCGPARAMS32:
1207 rc = get_params32(info, compat_ptr(arg));
1210 case MGSL_IOCGPARAMS:
1211 case MGSL_IOCSPARAMS:
1212 case MGSL_IOCGTXIDLE:
1213 case MGSL_IOCGSTATS:
1214 case MGSL_IOCWAITEVENT:
1218 case MGSL_IOCWAITGPIO:
1219 case MGSL_IOCGXSYNC:
1220 case MGSL_IOCGXCTRL:
1221 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1224 rc = ioctl(tty, cmd, arg);
1226 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1230 #define slgt_compat_ioctl NULL
1231 #endif /* ifdef CONFIG_COMPAT */
1236 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1239 unsigned long flags;
1241 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1242 info->device_name, info->phys_reg_addr,
1243 info->irq_level, info->max_frame_size);
1245 /* output current serial signal states */
1246 spin_lock_irqsave(&info->lock,flags);
1248 spin_unlock_irqrestore(&info->lock,flags);
1252 if (info->signals & SerialSignal_RTS)
1253 strcat(stat_buf, "|RTS");
1254 if (info->signals & SerialSignal_CTS)
1255 strcat(stat_buf, "|CTS");
1256 if (info->signals & SerialSignal_DTR)
1257 strcat(stat_buf, "|DTR");
1258 if (info->signals & SerialSignal_DSR)
1259 strcat(stat_buf, "|DSR");
1260 if (info->signals & SerialSignal_DCD)
1261 strcat(stat_buf, "|CD");
1262 if (info->signals & SerialSignal_RI)
1263 strcat(stat_buf, "|RI");
1265 if (info->params.mode != MGSL_MODE_ASYNC) {
1266 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1267 info->icount.txok, info->icount.rxok);
1268 if (info->icount.txunder)
1269 seq_printf(m, " txunder:%d", info->icount.txunder);
1270 if (info->icount.txabort)
1271 seq_printf(m, " txabort:%d", info->icount.txabort);
1272 if (info->icount.rxshort)
1273 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1274 if (info->icount.rxlong)
1275 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1276 if (info->icount.rxover)
1277 seq_printf(m, " rxover:%d", info->icount.rxover);
1278 if (info->icount.rxcrc)
1279 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1281 seq_printf(m, "\tASYNC tx:%d rx:%d",
1282 info->icount.tx, info->icount.rx);
1283 if (info->icount.frame)
1284 seq_printf(m, " fe:%d", info->icount.frame);
1285 if (info->icount.parity)
1286 seq_printf(m, " pe:%d", info->icount.parity);
1287 if (info->icount.brk)
1288 seq_printf(m, " brk:%d", info->icount.brk);
1289 if (info->icount.overrun)
1290 seq_printf(m, " oe:%d", info->icount.overrun);
1293 /* Append serial signal status to end */
1294 seq_printf(m, " %s\n", stat_buf+1);
1296 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1297 info->tx_active,info->bh_requested,info->bh_running,
1301 /* Called to print information about devices
1303 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1305 struct slgt_info *info;
1307 seq_puts(m, "synclink_gt driver\n");
1309 info = slgt_device_list;
1312 info = info->next_device;
1317 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1319 return single_open(file, synclink_gt_proc_show, NULL);
1322 static const struct file_operations synclink_gt_proc_fops = {
1323 .owner = THIS_MODULE,
1324 .open = synclink_gt_proc_open,
1326 .llseek = seq_lseek,
1327 .release = single_release,
1331 * return count of bytes in transmit buffer
1333 static int chars_in_buffer(struct tty_struct *tty)
1335 struct slgt_info *info = tty->driver_data;
1337 if (sanity_check(info, tty->name, "chars_in_buffer"))
1339 count = tbuf_bytes(info);
1340 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1345 * signal remote device to throttle send data (our receive data)
1347 static void throttle(struct tty_struct * tty)
1349 struct slgt_info *info = tty->driver_data;
1350 unsigned long flags;
1352 if (sanity_check(info, tty->name, "throttle"))
1354 DBGINFO(("%s throttle\n", info->device_name));
1356 send_xchar(tty, STOP_CHAR(tty));
1357 if (tty->termios.c_cflag & CRTSCTS) {
1358 spin_lock_irqsave(&info->lock,flags);
1359 info->signals &= ~SerialSignal_RTS;
1361 spin_unlock_irqrestore(&info->lock,flags);
1366 * signal remote device to stop throttling send data (our receive data)
1368 static void unthrottle(struct tty_struct * tty)
1370 struct slgt_info *info = tty->driver_data;
1371 unsigned long flags;
1373 if (sanity_check(info, tty->name, "unthrottle"))
1375 DBGINFO(("%s unthrottle\n", info->device_name));
1380 send_xchar(tty, START_CHAR(tty));
1382 if (tty->termios.c_cflag & CRTSCTS) {
1383 spin_lock_irqsave(&info->lock,flags);
1384 info->signals |= SerialSignal_RTS;
1386 spin_unlock_irqrestore(&info->lock,flags);
1391 * set or clear transmit break condition
1392 * break_state -1=set break condition, 0=clear
1394 static int set_break(struct tty_struct *tty, int break_state)
1396 struct slgt_info *info = tty->driver_data;
1397 unsigned short value;
1398 unsigned long flags;
1400 if (sanity_check(info, tty->name, "set_break"))
1402 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1404 spin_lock_irqsave(&info->lock,flags);
1405 value = rd_reg16(info, TCR);
1406 if (break_state == -1)
1410 wr_reg16(info, TCR, value);
1411 spin_unlock_irqrestore(&info->lock,flags);
1415 #if SYNCLINK_GENERIC_HDLC
1418 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1419 * set encoding and frame check sequence (FCS) options
1421 * dev pointer to network device structure
1422 * encoding serial encoding setting
1423 * parity FCS setting
1425 * returns 0 if success, otherwise error code
1427 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1428 unsigned short parity)
1430 struct slgt_info *info = dev_to_port(dev);
1431 unsigned char new_encoding;
1432 unsigned short new_crctype;
1434 /* return error if TTY interface open */
1435 if (info->port.count)
1438 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1442 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1443 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1444 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1445 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1446 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1447 default: return -EINVAL;
1452 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1453 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1454 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1455 default: return -EINVAL;
1458 info->params.encoding = new_encoding;
1459 info->params.crc_type = new_crctype;
1461 /* if network interface up, reprogram hardware */
1469 * called by generic HDLC layer to send frame
1471 * skb socket buffer containing HDLC frame
1472 * dev pointer to network device structure
1474 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1475 struct net_device *dev)
1477 struct slgt_info *info = dev_to_port(dev);
1478 unsigned long flags;
1480 DBGINFO(("%s hdlc_xmit\n", dev->name));
1483 return NETDEV_TX_OK;
1485 /* stop sending until this frame completes */
1486 netif_stop_queue(dev);
1488 /* update network statistics */
1489 dev->stats.tx_packets++;
1490 dev->stats.tx_bytes += skb->len;
1492 /* save start time for transmit timeout detection */
1493 dev->trans_start = jiffies;
1495 spin_lock_irqsave(&info->lock, flags);
1496 tx_load(info, skb->data, skb->len);
1497 spin_unlock_irqrestore(&info->lock, flags);
1499 /* done with socket buffer, so free it */
1502 return NETDEV_TX_OK;
1506 * called by network layer when interface enabled
1507 * claim resources and initialize hardware
1509 * dev pointer to network device structure
1511 * returns 0 if success, otherwise error code
1513 static int hdlcdev_open(struct net_device *dev)
1515 struct slgt_info *info = dev_to_port(dev);
1517 unsigned long flags;
1519 if (!try_module_get(THIS_MODULE))
1522 DBGINFO(("%s hdlcdev_open\n", dev->name));
1524 /* generic HDLC layer open processing */
1525 rc = hdlc_open(dev);
1529 /* arbitrate between network and tty opens */
1530 spin_lock_irqsave(&info->netlock, flags);
1531 if (info->port.count != 0 || info->netcount != 0) {
1532 DBGINFO(("%s hdlc_open busy\n", dev->name));
1533 spin_unlock_irqrestore(&info->netlock, flags);
1537 spin_unlock_irqrestore(&info->netlock, flags);
1539 /* claim resources and init adapter */
1540 if ((rc = startup(info)) != 0) {
1541 spin_lock_irqsave(&info->netlock, flags);
1543 spin_unlock_irqrestore(&info->netlock, flags);
1547 /* assert RTS and DTR, apply hardware settings */
1548 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1551 /* enable network layer transmit */
1552 dev->trans_start = jiffies;
1553 netif_start_queue(dev);
1555 /* inform generic HDLC layer of current DCD status */
1556 spin_lock_irqsave(&info->lock, flags);
1558 spin_unlock_irqrestore(&info->lock, flags);
1559 if (info->signals & SerialSignal_DCD)
1560 netif_carrier_on(dev);
1562 netif_carrier_off(dev);
1567 * called by network layer when interface is disabled
1568 * shutdown hardware and release resources
1570 * dev pointer to network device structure
1572 * returns 0 if success, otherwise error code
1574 static int hdlcdev_close(struct net_device *dev)
1576 struct slgt_info *info = dev_to_port(dev);
1577 unsigned long flags;
1579 DBGINFO(("%s hdlcdev_close\n", dev->name));
1581 netif_stop_queue(dev);
1583 /* shutdown adapter and release resources */
1588 spin_lock_irqsave(&info->netlock, flags);
1590 spin_unlock_irqrestore(&info->netlock, flags);
1592 module_put(THIS_MODULE);
1597 * called by network layer to process IOCTL call to network device
1599 * dev pointer to network device structure
1600 * ifr pointer to network interface request structure
1601 * cmd IOCTL command code
1603 * returns 0 if success, otherwise error code
1605 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1607 const size_t size = sizeof(sync_serial_settings);
1608 sync_serial_settings new_line;
1609 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1610 struct slgt_info *info = dev_to_port(dev);
1613 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1615 /* return error if TTY interface open */
1616 if (info->port.count)
1619 if (cmd != SIOCWANDEV)
1620 return hdlc_ioctl(dev, ifr, cmd);
1622 memset(&new_line, 0, sizeof(new_line));
1624 switch(ifr->ifr_settings.type) {
1625 case IF_GET_IFACE: /* return current sync_serial_settings */
1627 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1628 if (ifr->ifr_settings.size < size) {
1629 ifr->ifr_settings.size = size; /* data size wanted */
1633 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1634 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1635 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1636 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1639 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1640 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1641 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1642 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1643 default: new_line.clock_type = CLOCK_DEFAULT;
1646 new_line.clock_rate = info->params.clock_speed;
1647 new_line.loopback = info->params.loopback ? 1:0;
1649 if (copy_to_user(line, &new_line, size))
1653 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1655 if(!capable(CAP_NET_ADMIN))
1657 if (copy_from_user(&new_line, line, size))
1660 switch (new_line.clock_type)
1662 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1663 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1664 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1665 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1666 case CLOCK_DEFAULT: flags = info->params.flags &
1667 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1668 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1669 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1670 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1671 default: return -EINVAL;
1674 if (new_line.loopback != 0 && new_line.loopback != 1)
1677 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1678 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1679 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1680 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1681 info->params.flags |= flags;
1683 info->params.loopback = new_line.loopback;
1685 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1686 info->params.clock_speed = new_line.clock_rate;
1688 info->params.clock_speed = 0;
1690 /* if network interface up, reprogram hardware */
1696 return hdlc_ioctl(dev, ifr, cmd);
1701 * called by network layer when transmit timeout is detected
1703 * dev pointer to network device structure
1705 static void hdlcdev_tx_timeout(struct net_device *dev)
1707 struct slgt_info *info = dev_to_port(dev);
1708 unsigned long flags;
1710 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1712 dev->stats.tx_errors++;
1713 dev->stats.tx_aborted_errors++;
1715 spin_lock_irqsave(&info->lock,flags);
1717 spin_unlock_irqrestore(&info->lock,flags);
1719 netif_wake_queue(dev);
1723 * called by device driver when transmit completes
1724 * reenable network layer transmit if stopped
1726 * info pointer to device instance information
1728 static void hdlcdev_tx_done(struct slgt_info *info)
1730 if (netif_queue_stopped(info->netdev))
1731 netif_wake_queue(info->netdev);
1735 * called by device driver when frame received
1736 * pass frame to network layer
1738 * info pointer to device instance information
1739 * buf pointer to buffer contianing frame data
1740 * size count of data bytes in buf
1742 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1744 struct sk_buff *skb = dev_alloc_skb(size);
1745 struct net_device *dev = info->netdev;
1747 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1750 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1751 dev->stats.rx_dropped++;
1755 memcpy(skb_put(skb, size), buf, size);
1757 skb->protocol = hdlc_type_trans(skb, dev);
1759 dev->stats.rx_packets++;
1760 dev->stats.rx_bytes += size;
1765 static const struct net_device_ops hdlcdev_ops = {
1766 .ndo_open = hdlcdev_open,
1767 .ndo_stop = hdlcdev_close,
1768 .ndo_change_mtu = hdlc_change_mtu,
1769 .ndo_start_xmit = hdlc_start_xmit,
1770 .ndo_do_ioctl = hdlcdev_ioctl,
1771 .ndo_tx_timeout = hdlcdev_tx_timeout,
1775 * called by device driver when adding device instance
1776 * do generic HDLC initialization
1778 * info pointer to device instance information
1780 * returns 0 if success, otherwise error code
1782 static int hdlcdev_init(struct slgt_info *info)
1785 struct net_device *dev;
1788 /* allocate and initialize network and HDLC layer objects */
1790 dev = alloc_hdlcdev(info);
1792 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1796 /* for network layer reporting purposes only */
1797 dev->mem_start = info->phys_reg_addr;
1798 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1799 dev->irq = info->irq_level;
1801 /* network layer callbacks and settings */
1802 dev->netdev_ops = &hdlcdev_ops;
1803 dev->watchdog_timeo = 10 * HZ;
1804 dev->tx_queue_len = 50;
1806 /* generic HDLC layer callbacks and settings */
1807 hdlc = dev_to_hdlc(dev);
1808 hdlc->attach = hdlcdev_attach;
1809 hdlc->xmit = hdlcdev_xmit;
1811 /* register objects with HDLC layer */
1812 rc = register_hdlc_device(dev);
1814 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1824 * called by device driver when removing device instance
1825 * do generic HDLC cleanup
1827 * info pointer to device instance information
1829 static void hdlcdev_exit(struct slgt_info *info)
1831 unregister_hdlc_device(info->netdev);
1832 free_netdev(info->netdev);
1833 info->netdev = NULL;
1836 #endif /* ifdef CONFIG_HDLC */
1839 * get async data from rx DMA buffers
1841 static void rx_async(struct slgt_info *info)
1843 struct mgsl_icount *icount = &info->icount;
1844 unsigned int start, end;
1846 unsigned char status;
1847 struct slgt_desc *bufs = info->rbufs;
1853 start = end = info->rbuf_current;
1855 while(desc_complete(bufs[end])) {
1856 count = desc_count(bufs[end]) - info->rbuf_index;
1857 p = bufs[end].buf + info->rbuf_index;
1859 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1860 DBGDATA(info, p, count, "rx");
1862 for(i=0 ; i < count; i+=2, p+=2) {
1868 status = *(p + 1) & (BIT1 + BIT0);
1872 else if (status & BIT0)
1874 /* discard char if tty control flags say so */
1875 if (status & info->ignore_status_mask)
1879 else if (status & BIT0)
1882 tty_insert_flip_char(&info->port, ch, stat);
1887 /* receive buffer not completed */
1888 info->rbuf_index += i;
1889 mod_timer(&info->rx_timer, jiffies + 1);
1893 info->rbuf_index = 0;
1894 free_rbufs(info, end, end);
1896 if (++end == info->rbuf_count)
1899 /* if entire list searched then no frame available */
1905 tty_flip_buffer_push(&info->port);
1909 * return next bottom half action to perform
1911 static int bh_action(struct slgt_info *info)
1913 unsigned long flags;
1916 spin_lock_irqsave(&info->lock,flags);
1918 if (info->pending_bh & BH_RECEIVE) {
1919 info->pending_bh &= ~BH_RECEIVE;
1921 } else if (info->pending_bh & BH_TRANSMIT) {
1922 info->pending_bh &= ~BH_TRANSMIT;
1924 } else if (info->pending_bh & BH_STATUS) {
1925 info->pending_bh &= ~BH_STATUS;
1928 /* Mark BH routine as complete */
1929 info->bh_running = false;
1930 info->bh_requested = false;
1934 spin_unlock_irqrestore(&info->lock,flags);
1940 * perform bottom half processing
1942 static void bh_handler(struct work_struct *work)
1944 struct slgt_info *info = container_of(work, struct slgt_info, task);
1947 info->bh_running = true;
1949 while((action = bh_action(info))) {
1952 DBGBH(("%s bh receive\n", info->device_name));
1953 switch(info->params.mode) {
1954 case MGSL_MODE_ASYNC:
1957 case MGSL_MODE_HDLC:
1958 while(rx_get_frame(info));
1961 case MGSL_MODE_MONOSYNC:
1962 case MGSL_MODE_BISYNC:
1963 case MGSL_MODE_XSYNC:
1964 while(rx_get_buf(info));
1967 /* restart receiver if rx DMA buffers exhausted */
1968 if (info->rx_restart)
1975 DBGBH(("%s bh status\n", info->device_name));
1976 info->ri_chkcount = 0;
1977 info->dsr_chkcount = 0;
1978 info->dcd_chkcount = 0;
1979 info->cts_chkcount = 0;
1982 DBGBH(("%s unknown action\n", info->device_name));
1986 DBGBH(("%s bh_handler exit\n", info->device_name));
1989 static void bh_transmit(struct slgt_info *info)
1991 struct tty_struct *tty = info->port.tty;
1993 DBGBH(("%s bh_transmit\n", info->device_name));
1998 static void dsr_change(struct slgt_info *info, unsigned short status)
2000 if (status & BIT3) {
2001 info->signals |= SerialSignal_DSR;
2002 info->input_signal_events.dsr_up++;
2004 info->signals &= ~SerialSignal_DSR;
2005 info->input_signal_events.dsr_down++;
2007 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2008 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2009 slgt_irq_off(info, IRQ_DSR);
2013 wake_up_interruptible(&info->status_event_wait_q);
2014 wake_up_interruptible(&info->event_wait_q);
2015 info->pending_bh |= BH_STATUS;
2018 static void cts_change(struct slgt_info *info, unsigned short status)
2020 if (status & BIT2) {
2021 info->signals |= SerialSignal_CTS;
2022 info->input_signal_events.cts_up++;
2024 info->signals &= ~SerialSignal_CTS;
2025 info->input_signal_events.cts_down++;
2027 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2028 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2029 slgt_irq_off(info, IRQ_CTS);
2033 wake_up_interruptible(&info->status_event_wait_q);
2034 wake_up_interruptible(&info->event_wait_q);
2035 info->pending_bh |= BH_STATUS;
2037 if (tty_port_cts_enabled(&info->port)) {
2038 if (info->port.tty) {
2039 if (info->port.tty->hw_stopped) {
2040 if (info->signals & SerialSignal_CTS) {
2041 info->port.tty->hw_stopped = 0;
2042 info->pending_bh |= BH_TRANSMIT;
2046 if (!(info->signals & SerialSignal_CTS))
2047 info->port.tty->hw_stopped = 1;
2053 static void dcd_change(struct slgt_info *info, unsigned short status)
2055 if (status & BIT1) {
2056 info->signals |= SerialSignal_DCD;
2057 info->input_signal_events.dcd_up++;
2059 info->signals &= ~SerialSignal_DCD;
2060 info->input_signal_events.dcd_down++;
2062 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2063 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2064 slgt_irq_off(info, IRQ_DCD);
2068 #if SYNCLINK_GENERIC_HDLC
2069 if (info->netcount) {
2070 if (info->signals & SerialSignal_DCD)
2071 netif_carrier_on(info->netdev);
2073 netif_carrier_off(info->netdev);
2076 wake_up_interruptible(&info->status_event_wait_q);
2077 wake_up_interruptible(&info->event_wait_q);
2078 info->pending_bh |= BH_STATUS;
2080 if (info->port.flags & ASYNC_CHECK_CD) {
2081 if (info->signals & SerialSignal_DCD)
2082 wake_up_interruptible(&info->port.open_wait);
2085 tty_hangup(info->port.tty);
2090 static void ri_change(struct slgt_info *info, unsigned short status)
2092 if (status & BIT0) {
2093 info->signals |= SerialSignal_RI;
2094 info->input_signal_events.ri_up++;
2096 info->signals &= ~SerialSignal_RI;
2097 info->input_signal_events.ri_down++;
2099 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2100 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2101 slgt_irq_off(info, IRQ_RI);
2105 wake_up_interruptible(&info->status_event_wait_q);
2106 wake_up_interruptible(&info->event_wait_q);
2107 info->pending_bh |= BH_STATUS;
2110 static void isr_rxdata(struct slgt_info *info)
2112 unsigned int count = info->rbuf_fill_count;
2113 unsigned int i = info->rbuf_fill_index;
2116 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2117 reg = rd_reg16(info, RDR);
2118 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2119 if (desc_complete(info->rbufs[i])) {
2120 /* all buffers full */
2122 info->rx_restart = 1;
2125 info->rbufs[i].buf[count++] = (unsigned char)reg;
2126 /* async mode saves status byte to buffer for each data byte */
2127 if (info->params.mode == MGSL_MODE_ASYNC)
2128 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2129 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2130 /* buffer full or end of frame */
2131 set_desc_count(info->rbufs[i], count);
2132 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2133 info->rbuf_fill_count = count = 0;
2134 if (++i == info->rbuf_count)
2136 info->pending_bh |= BH_RECEIVE;
2140 info->rbuf_fill_index = i;
2141 info->rbuf_fill_count = count;
2144 static void isr_serial(struct slgt_info *info)
2146 unsigned short status = rd_reg16(info, SSR);
2148 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2150 wr_reg16(info, SSR, status); /* clear pending */
2152 info->irq_occurred = true;
2154 if (info->params.mode == MGSL_MODE_ASYNC) {
2155 if (status & IRQ_TXIDLE) {
2156 if (info->tx_active)
2157 isr_txeom(info, status);
2159 if (info->rx_pio && (status & IRQ_RXDATA))
2161 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2163 /* process break detection if tty control allows */
2164 if (info->port.tty) {
2165 if (!(status & info->ignore_status_mask)) {
2166 if (info->read_status_mask & MASK_BREAK) {
2167 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2168 if (info->port.flags & ASYNC_SAK)
2169 do_SAK(info->port.tty);
2175 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2176 isr_txeom(info, status);
2177 if (info->rx_pio && (status & IRQ_RXDATA))
2179 if (status & IRQ_RXIDLE) {
2180 if (status & RXIDLE)
2181 info->icount.rxidle++;
2183 info->icount.exithunt++;
2184 wake_up_interruptible(&info->event_wait_q);
2187 if (status & IRQ_RXOVER)
2191 if (status & IRQ_DSR)
2192 dsr_change(info, status);
2193 if (status & IRQ_CTS)
2194 cts_change(info, status);
2195 if (status & IRQ_DCD)
2196 dcd_change(info, status);
2197 if (status & IRQ_RI)
2198 ri_change(info, status);
2201 static void isr_rdma(struct slgt_info *info)
2203 unsigned int status = rd_reg32(info, RDCSR);
2205 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2207 /* RDCSR (rx DMA control/status)
2210 * 06 save status byte to DMA buffer
2212 * 04 eol (end of list)
2213 * 03 eob (end of buffer)
2218 wr_reg32(info, RDCSR, status); /* clear pending */
2220 if (status & (BIT5 + BIT4)) {
2221 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2222 info->rx_restart = true;
2224 info->pending_bh |= BH_RECEIVE;
2227 static void isr_tdma(struct slgt_info *info)
2229 unsigned int status = rd_reg32(info, TDCSR);
2231 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2233 /* TDCSR (tx DMA control/status)
2237 * 04 eol (end of list)
2238 * 03 eob (end of buffer)
2243 wr_reg32(info, TDCSR, status); /* clear pending */
2245 if (status & (BIT5 + BIT4 + BIT3)) {
2246 // another transmit buffer has completed
2247 // run bottom half to get more send data from user
2248 info->pending_bh |= BH_TRANSMIT;
2253 * return true if there are unsent tx DMA buffers, otherwise false
2255 * if there are unsent buffers then info->tbuf_start
2256 * is set to index of first unsent buffer
2258 static bool unsent_tbufs(struct slgt_info *info)
2260 unsigned int i = info->tbuf_current;
2264 * search backwards from last loaded buffer (precedes tbuf_current)
2265 * for first unsent buffer (desc_count > 0)
2272 i = info->tbuf_count - 1;
2273 if (!desc_count(info->tbufs[i]))
2275 info->tbuf_start = i;
2277 } while (i != info->tbuf_current);
2282 static void isr_txeom(struct slgt_info *info, unsigned short status)
2284 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2286 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2288 if (status & IRQ_TXUNDER) {
2289 unsigned short val = rd_reg16(info, TCR);
2290 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2291 wr_reg16(info, TCR, val); /* clear reset bit */
2294 if (info->tx_active) {
2295 if (info->params.mode != MGSL_MODE_ASYNC) {
2296 if (status & IRQ_TXUNDER)
2297 info->icount.txunder++;
2298 else if (status & IRQ_TXIDLE)
2299 info->icount.txok++;
2302 if (unsent_tbufs(info)) {
2304 update_tx_timer(info);
2307 info->tx_active = false;
2309 del_timer(&info->tx_timer);
2311 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2312 info->signals &= ~SerialSignal_RTS;
2313 info->drop_rts_on_tx_done = false;
2317 #if SYNCLINK_GENERIC_HDLC
2319 hdlcdev_tx_done(info);
2323 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2327 info->pending_bh |= BH_TRANSMIT;
2332 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2334 struct cond_wait *w, *prev;
2336 /* wake processes waiting for specific transitions */
2337 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2338 if (w->data & changed) {
2340 wake_up_interruptible(&w->q);
2342 prev->next = w->next;
2344 info->gpio_wait_q = w->next;
2350 /* interrupt service routine
2352 * irq interrupt number
2353 * dev_id device ID supplied during interrupt registration
2355 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2357 struct slgt_info *info = dev_id;
2361 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2363 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2364 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2365 info->irq_occurred = true;
2366 for(i=0; i < info->port_count ; i++) {
2367 if (info->port_array[i] == NULL)
2369 spin_lock(&info->port_array[i]->lock);
2370 if (gsr & (BIT8 << i))
2371 isr_serial(info->port_array[i]);
2372 if (gsr & (BIT16 << (i*2)))
2373 isr_rdma(info->port_array[i]);
2374 if (gsr & (BIT17 << (i*2)))
2375 isr_tdma(info->port_array[i]);
2376 spin_unlock(&info->port_array[i]->lock);
2380 if (info->gpio_present) {
2382 unsigned int changed;
2383 spin_lock(&info->lock);
2384 while ((changed = rd_reg32(info, IOSR)) != 0) {
2385 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2386 /* read latched state of GPIO signals */
2387 state = rd_reg32(info, IOVR);
2388 /* clear pending GPIO interrupt bits */
2389 wr_reg32(info, IOSR, changed);
2390 for (i=0 ; i < info->port_count ; i++) {
2391 if (info->port_array[i] != NULL)
2392 isr_gpio(info->port_array[i], changed, state);
2395 spin_unlock(&info->lock);
2398 for(i=0; i < info->port_count ; i++) {
2399 struct slgt_info *port = info->port_array[i];
2402 spin_lock(&port->lock);
2403 if ((port->port.count || port->netcount) &&
2404 port->pending_bh && !port->bh_running &&
2405 !port->bh_requested) {
2406 DBGISR(("%s bh queued\n", port->device_name));
2407 schedule_work(&port->task);
2408 port->bh_requested = true;
2410 spin_unlock(&port->lock);
2413 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2417 static int startup(struct slgt_info *info)
2419 DBGINFO(("%s startup\n", info->device_name));
2421 if (info->port.flags & ASYNC_INITIALIZED)
2424 if (!info->tx_buf) {
2425 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2426 if (!info->tx_buf) {
2427 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2432 info->pending_bh = 0;
2434 memset(&info->icount, 0, sizeof(info->icount));
2436 /* program hardware for current parameters */
2437 change_params(info);
2440 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2442 info->port.flags |= ASYNC_INITIALIZED;
2448 * called by close() and hangup() to shutdown hardware
2450 static void shutdown(struct slgt_info *info)
2452 unsigned long flags;
2454 if (!(info->port.flags & ASYNC_INITIALIZED))
2457 DBGINFO(("%s shutdown\n", info->device_name));
2459 /* clear status wait queue because status changes */
2460 /* can't happen after shutting down the hardware */
2461 wake_up_interruptible(&info->status_event_wait_q);
2462 wake_up_interruptible(&info->event_wait_q);
2464 del_timer_sync(&info->tx_timer);
2465 del_timer_sync(&info->rx_timer);
2467 kfree(info->tx_buf);
2468 info->tx_buf = NULL;
2470 spin_lock_irqsave(&info->lock,flags);
2475 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2477 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2478 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2482 flush_cond_wait(&info->gpio_wait_q);
2484 spin_unlock_irqrestore(&info->lock,flags);
2487 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2489 info->port.flags &= ~ASYNC_INITIALIZED;
2492 static void program_hw(struct slgt_info *info)
2494 unsigned long flags;
2496 spin_lock_irqsave(&info->lock,flags);
2501 if (info->params.mode != MGSL_MODE_ASYNC ||
2509 info->dcd_chkcount = 0;
2510 info->cts_chkcount = 0;
2511 info->ri_chkcount = 0;
2512 info->dsr_chkcount = 0;
2514 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2517 if (info->netcount ||
2518 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2521 spin_unlock_irqrestore(&info->lock,flags);
2525 * reconfigure adapter based on new parameters
2527 static void change_params(struct slgt_info *info)
2532 if (!info->port.tty)
2534 DBGINFO(("%s change_params\n", info->device_name));
2536 cflag = info->port.tty->termios.c_cflag;
2538 /* if B0 rate (hangup) specified then negate RTS and DTR */
2539 /* otherwise assert RTS and DTR */
2541 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2543 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2545 /* byte size and parity */
2547 switch (cflag & CSIZE) {
2548 case CS5: info->params.data_bits = 5; break;
2549 case CS6: info->params.data_bits = 6; break;
2550 case CS7: info->params.data_bits = 7; break;
2551 case CS8: info->params.data_bits = 8; break;
2552 default: info->params.data_bits = 7; break;
2555 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2558 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2560 info->params.parity = ASYNC_PARITY_NONE;
2562 /* calculate number of jiffies to transmit a full
2563 * FIFO (32 bytes) at specified data rate
2565 bits_per_char = info->params.data_bits +
2566 info->params.stop_bits + 1;
2568 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2570 if (info->params.data_rate) {
2571 info->timeout = (32*HZ*bits_per_char) /
2572 info->params.data_rate;
2574 info->timeout += HZ/50; /* Add .02 seconds of slop */
2576 if (cflag & CRTSCTS)
2577 info->port.flags |= ASYNC_CTS_FLOW;
2579 info->port.flags &= ~ASYNC_CTS_FLOW;
2582 info->port.flags &= ~ASYNC_CHECK_CD;
2584 info->port.flags |= ASYNC_CHECK_CD;
2586 /* process tty input control flags */
2588 info->read_status_mask = IRQ_RXOVER;
2589 if (I_INPCK(info->port.tty))
2590 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2591 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2592 info->read_status_mask |= MASK_BREAK;
2593 if (I_IGNPAR(info->port.tty))
2594 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2595 if (I_IGNBRK(info->port.tty)) {
2596 info->ignore_status_mask |= MASK_BREAK;
2597 /* If ignoring parity and break indicators, ignore
2598 * overruns too. (For real raw support).
2600 if (I_IGNPAR(info->port.tty))
2601 info->ignore_status_mask |= MASK_OVERRUN;
2607 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2609 DBGINFO(("%s get_stats\n", info->device_name));
2611 memset(&info->icount, 0, sizeof(info->icount));
2613 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2619 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2621 DBGINFO(("%s get_params\n", info->device_name));
2622 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2627 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2629 unsigned long flags;
2630 MGSL_PARAMS tmp_params;
2632 DBGINFO(("%s set_params\n", info->device_name));
2633 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2636 spin_lock_irqsave(&info->lock, flags);
2637 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2638 info->base_clock = tmp_params.clock_speed;
2640 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2641 spin_unlock_irqrestore(&info->lock, flags);
2648 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2650 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2651 if (put_user(info->idle_mode, idle_mode))
2656 static int set_txidle(struct slgt_info *info, int idle_mode)
2658 unsigned long flags;
2659 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2660 spin_lock_irqsave(&info->lock,flags);
2661 info->idle_mode = idle_mode;
2662 if (info->params.mode != MGSL_MODE_ASYNC)
2664 spin_unlock_irqrestore(&info->lock,flags);
2668 static int tx_enable(struct slgt_info *info, int enable)
2670 unsigned long flags;
2671 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2672 spin_lock_irqsave(&info->lock,flags);
2674 if (!info->tx_enabled)
2677 if (info->tx_enabled)
2680 spin_unlock_irqrestore(&info->lock,flags);
2685 * abort transmit HDLC frame
2687 static int tx_abort(struct slgt_info *info)
2689 unsigned long flags;
2690 DBGINFO(("%s tx_abort\n", info->device_name));
2691 spin_lock_irqsave(&info->lock,flags);
2693 spin_unlock_irqrestore(&info->lock,flags);
2697 static int rx_enable(struct slgt_info *info, int enable)
2699 unsigned long flags;
2700 unsigned int rbuf_fill_level;
2701 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2702 spin_lock_irqsave(&info->lock,flags);
2704 * enable[31..16] = receive DMA buffer fill level
2705 * 0 = noop (leave fill level unchanged)
2706 * fill level must be multiple of 4 and <= buffer size
2708 rbuf_fill_level = ((unsigned int)enable) >> 16;
2709 if (rbuf_fill_level) {
2710 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2711 spin_unlock_irqrestore(&info->lock, flags);
2714 info->rbuf_fill_level = rbuf_fill_level;
2715 if (rbuf_fill_level < 128)
2716 info->rx_pio = 1; /* PIO mode */
2718 info->rx_pio = 0; /* DMA mode */
2719 rx_stop(info); /* restart receiver to use new fill level */
2723 * enable[1..0] = receiver enable command
2726 * 2 = enable or force hunt mode if already enabled
2730 if (!info->rx_enabled)
2732 else if (enable == 2) {
2733 /* force hunt mode (write 1 to RCR[3]) */
2734 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2737 if (info->rx_enabled)
2740 spin_unlock_irqrestore(&info->lock,flags);
2745 * wait for specified event to occur
2747 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2749 unsigned long flags;
2752 struct mgsl_icount cprev, cnow;
2755 struct _input_signal_events oldsigs, newsigs;
2756 DECLARE_WAITQUEUE(wait, current);
2758 if (get_user(mask, mask_ptr))
2761 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2763 spin_lock_irqsave(&info->lock,flags);
2765 /* return immediately if state matches requested events */
2770 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2771 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2772 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2773 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2775 spin_unlock_irqrestore(&info->lock,flags);
2779 /* save current irq counts */
2780 cprev = info->icount;
2781 oldsigs = info->input_signal_events;
2783 /* enable hunt and idle irqs if needed */
2784 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2785 unsigned short val = rd_reg16(info, SCR);
2786 if (!(val & IRQ_RXIDLE))
2787 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2790 set_current_state(TASK_INTERRUPTIBLE);
2791 add_wait_queue(&info->event_wait_q, &wait);
2793 spin_unlock_irqrestore(&info->lock,flags);
2797 if (signal_pending(current)) {
2802 /* get current irq counts */
2803 spin_lock_irqsave(&info->lock,flags);
2804 cnow = info->icount;
2805 newsigs = info->input_signal_events;
2806 set_current_state(TASK_INTERRUPTIBLE);
2807 spin_unlock_irqrestore(&info->lock,flags);
2809 /* if no change, wait aborted for some reason */
2810 if (newsigs.dsr_up == oldsigs.dsr_up &&
2811 newsigs.dsr_down == oldsigs.dsr_down &&
2812 newsigs.dcd_up == oldsigs.dcd_up &&
2813 newsigs.dcd_down == oldsigs.dcd_down &&
2814 newsigs.cts_up == oldsigs.cts_up &&
2815 newsigs.cts_down == oldsigs.cts_down &&
2816 newsigs.ri_up == oldsigs.ri_up &&
2817 newsigs.ri_down == oldsigs.ri_down &&
2818 cnow.exithunt == cprev.exithunt &&
2819 cnow.rxidle == cprev.rxidle) {
2825 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2826 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2827 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2828 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2829 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2830 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2831 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2832 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2833 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2834 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2842 remove_wait_queue(&info->event_wait_q, &wait);
2843 set_current_state(TASK_RUNNING);
2846 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2847 spin_lock_irqsave(&info->lock,flags);
2848 if (!waitqueue_active(&info->event_wait_q)) {
2849 /* disable enable exit hunt mode/idle rcvd IRQs */
2851 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2853 spin_unlock_irqrestore(&info->lock,flags);
2857 rc = put_user(events, mask_ptr);
2861 static int get_interface(struct slgt_info *info, int __user *if_mode)
2863 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2864 if (put_user(info->if_mode, if_mode))
2869 static int set_interface(struct slgt_info *info, int if_mode)
2871 unsigned long flags;
2874 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2875 spin_lock_irqsave(&info->lock,flags);
2876 info->if_mode = if_mode;
2880 /* TCR (tx control) 07 1=RTS driver control */
2881 val = rd_reg16(info, TCR);
2882 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2886 wr_reg16(info, TCR, val);
2888 spin_unlock_irqrestore(&info->lock,flags);
2892 static int get_xsync(struct slgt_info *info, int __user *xsync)
2894 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2895 if (put_user(info->xsync, xsync))
2901 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2903 * sync pattern is contained in least significant bytes of value
2904 * most significant byte of sync pattern is oldest (1st sent/detected)
2906 static int set_xsync(struct slgt_info *info, int xsync)
2908 unsigned long flags;
2910 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2911 spin_lock_irqsave(&info->lock, flags);
2912 info->xsync = xsync;
2913 wr_reg32(info, XSR, xsync);
2914 spin_unlock_irqrestore(&info->lock, flags);
2918 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2920 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2921 if (put_user(info->xctrl, xctrl))
2927 * set extended control options
2929 * xctrl[31:19] reserved, must be zero
2930 * xctrl[18:17] extended sync pattern length in bytes
2931 * 00 = 1 byte in xsr[7:0]
2932 * 01 = 2 bytes in xsr[15:0]
2933 * 10 = 3 bytes in xsr[23:0]
2934 * 11 = 4 bytes in xsr[31:0]
2935 * xctrl[16] 1 = enable terminal count, 0=disabled
2936 * xctrl[15:0] receive terminal count for fixed length packets
2937 * value is count minus one (0 = 1 byte packet)
2938 * when terminal count is reached, receiver
2939 * automatically returns to hunt mode and receive
2940 * FIFO contents are flushed to DMA buffers with
2941 * end of frame (EOF) status
2943 static int set_xctrl(struct slgt_info *info, int xctrl)
2945 unsigned long flags;
2947 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2948 spin_lock_irqsave(&info->lock, flags);
2949 info->xctrl = xctrl;
2950 wr_reg32(info, XCR, xctrl);
2951 spin_unlock_irqrestore(&info->lock, flags);
2956 * set general purpose IO pin state and direction
2959 * state each bit indicates a pin state
2960 * smask set bit indicates pin state to set
2961 * dir each bit indicates a pin direction (0=input, 1=output)
2962 * dmask set bit indicates pin direction to set
2964 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2966 unsigned long flags;
2967 struct gpio_desc gpio;
2970 if (!info->gpio_present)
2972 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2974 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2975 info->device_name, gpio.state, gpio.smask,
2976 gpio.dir, gpio.dmask));
2978 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2980 data = rd_reg32(info, IODR);
2981 data |= gpio.dmask & gpio.dir;
2982 data &= ~(gpio.dmask & ~gpio.dir);
2983 wr_reg32(info, IODR, data);
2986 data = rd_reg32(info, IOVR);
2987 data |= gpio.smask & gpio.state;
2988 data &= ~(gpio.smask & ~gpio.state);
2989 wr_reg32(info, IOVR, data);
2991 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2997 * get general purpose IO pin state and direction
2999 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3001 struct gpio_desc gpio;
3002 if (!info->gpio_present)
3004 gpio.state = rd_reg32(info, IOVR);
3005 gpio.smask = 0xffffffff;
3006 gpio.dir = rd_reg32(info, IODR);
3007 gpio.dmask = 0xffffffff;
3008 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3010 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3011 info->device_name, gpio.state, gpio.dir));
3016 * conditional wait facility
3018 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3020 init_waitqueue_head(&w->q);
3021 init_waitqueue_entry(&w->wait, current);
3025 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3027 set_current_state(TASK_INTERRUPTIBLE);
3028 add_wait_queue(&w->q, &w->wait);
3033 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3035 struct cond_wait *w, *prev;
3036 remove_wait_queue(&cw->q, &cw->wait);
3037 set_current_state(TASK_RUNNING);
3038 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3041 prev->next = w->next;
3049 static void flush_cond_wait(struct cond_wait **head)
3051 while (*head != NULL) {
3052 wake_up_interruptible(&(*head)->q);
3053 *head = (*head)->next;
3058 * wait for general purpose I/O pin(s) to enter specified state
3061 * state - bit indicates target pin state
3062 * smask - set bit indicates watched pin
3064 * The wait ends when at least one watched pin enters the specified
3065 * state. When 0 (no error) is returned, user_gpio->state is set to the
3066 * state of all GPIO pins when the wait ends.
3068 * Note: Each pin may be a dedicated input, dedicated output, or
3069 * configurable input/output. The number and configuration of pins
3070 * varies with the specific adapter model. Only input pins (dedicated
3071 * or configured) can be monitored with this function.
3073 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3075 unsigned long flags;
3077 struct gpio_desc gpio;
3078 struct cond_wait wait;
3081 if (!info->gpio_present)
3083 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3085 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3086 info->device_name, gpio.state, gpio.smask));
3087 /* ignore output pins identified by set IODR bit */
3088 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3090 init_cond_wait(&wait, gpio.smask);
3092 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3093 /* enable interrupts for watched pins */
3094 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3095 /* get current pin states */
3096 state = rd_reg32(info, IOVR);
3098 if (gpio.smask & ~(state ^ gpio.state)) {
3099 /* already in target state */
3102 /* wait for target state */
3103 add_cond_wait(&info->gpio_wait_q, &wait);
3104 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3106 if (signal_pending(current))
3109 gpio.state = wait.data;
3110 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3111 remove_cond_wait(&info->gpio_wait_q, &wait);
3114 /* disable all GPIO interrupts if no waiting processes */
3115 if (info->gpio_wait_q == NULL)
3116 wr_reg32(info, IOER, 0);
3117 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3119 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3124 static int modem_input_wait(struct slgt_info *info,int arg)
3126 unsigned long flags;
3128 struct mgsl_icount cprev, cnow;
3129 DECLARE_WAITQUEUE(wait, current);
3131 /* save current irq counts */
3132 spin_lock_irqsave(&info->lock,flags);
3133 cprev = info->icount;
3134 add_wait_queue(&info->status_event_wait_q, &wait);
3135 set_current_state(TASK_INTERRUPTIBLE);
3136 spin_unlock_irqrestore(&info->lock,flags);
3140 if (signal_pending(current)) {
3145 /* get new irq counts */
3146 spin_lock_irqsave(&info->lock,flags);
3147 cnow = info->icount;
3148 set_current_state(TASK_INTERRUPTIBLE);
3149 spin_unlock_irqrestore(&info->lock,flags);
3151 /* if no change, wait aborted for some reason */
3152 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3153 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3158 /* check for change in caller specified modem input */
3159 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3160 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3161 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3162 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3169 remove_wait_queue(&info->status_event_wait_q, &wait);
3170 set_current_state(TASK_RUNNING);
3175 * return state of serial control and status signals
3177 static int tiocmget(struct tty_struct *tty)
3179 struct slgt_info *info = tty->driver_data;
3180 unsigned int result;
3181 unsigned long flags;
3183 spin_lock_irqsave(&info->lock,flags);
3185 spin_unlock_irqrestore(&info->lock,flags);
3187 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3188 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3189 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3190 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3191 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3192 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3194 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3199 * set modem control signals (DTR/RTS)
3201 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3202 * TIOCMSET = set/clear signal values
3203 * value bit mask for command
3205 static int tiocmset(struct tty_struct *tty,
3206 unsigned int set, unsigned int clear)
3208 struct slgt_info *info = tty->driver_data;
3209 unsigned long flags;
3211 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3213 if (set & TIOCM_RTS)
3214 info->signals |= SerialSignal_RTS;
3215 if (set & TIOCM_DTR)
3216 info->signals |= SerialSignal_DTR;
3217 if (clear & TIOCM_RTS)
3218 info->signals &= ~SerialSignal_RTS;
3219 if (clear & TIOCM_DTR)
3220 info->signals &= ~SerialSignal_DTR;
3222 spin_lock_irqsave(&info->lock,flags);
3224 spin_unlock_irqrestore(&info->lock,flags);
3228 static int carrier_raised(struct tty_port *port)
3230 unsigned long flags;
3231 struct slgt_info *info = container_of(port, struct slgt_info, port);
3233 spin_lock_irqsave(&info->lock,flags);
3235 spin_unlock_irqrestore(&info->lock,flags);
3236 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3239 static void dtr_rts(struct tty_port *port, int on)
3241 unsigned long flags;
3242 struct slgt_info *info = container_of(port, struct slgt_info, port);
3244 spin_lock_irqsave(&info->lock,flags);
3246 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3248 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3250 spin_unlock_irqrestore(&info->lock,flags);
3255 * block current process until the device is ready to open
3257 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3258 struct slgt_info *info)
3260 DECLARE_WAITQUEUE(wait, current);
3262 bool do_clocal = false;
3263 unsigned long flags;
3265 struct tty_port *port = &info->port;
3267 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3269 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3270 /* nonblock mode is set or port is not enabled */
3271 port->flags |= ASYNC_NORMAL_ACTIVE;
3275 if (tty->termios.c_cflag & CLOCAL)
3278 /* Wait for carrier detect and the line to become
3279 * free (i.e., not in use by the callout). While we are in
3280 * this loop, port->count is dropped by one, so that
3281 * close() knows when to free things. We restore it upon
3282 * exit, either normal or abnormal.
3286 add_wait_queue(&port->open_wait, &wait);
3288 spin_lock_irqsave(&info->lock, flags);
3290 spin_unlock_irqrestore(&info->lock, flags);
3291 port->blocked_open++;
3294 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3295 tty_port_raise_dtr_rts(port);
3297 set_current_state(TASK_INTERRUPTIBLE);
3299 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3300 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3301 -EAGAIN : -ERESTARTSYS;
3305 cd = tty_port_carrier_raised(port);
3306 if (do_clocal || cd)
3309 if (signal_pending(current)) {
3310 retval = -ERESTARTSYS;
3314 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3320 set_current_state(TASK_RUNNING);
3321 remove_wait_queue(&port->open_wait, &wait);
3323 if (!tty_hung_up_p(filp))
3325 port->blocked_open--;
3328 port->flags |= ASYNC_NORMAL_ACTIVE;
3330 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3335 * allocate buffers used for calling line discipline receive_buf
3336 * directly in synchronous mode
3337 * note: add 5 bytes to max frame size to allow appending
3338 * 32-bit CRC and status byte when configured to do so
3340 static int alloc_tmp_rbuf(struct slgt_info *info)
3342 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3343 if (info->tmp_rbuf == NULL)
3345 /* unused flag buffer to satisfy receive_buf calling interface */
3346 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3347 if (!info->flag_buf) {
3348 kfree(info->tmp_rbuf);
3349 info->tmp_rbuf = NULL;
3355 static void free_tmp_rbuf(struct slgt_info *info)
3357 kfree(info->tmp_rbuf);
3358 info->tmp_rbuf = NULL;
3359 kfree(info->flag_buf);
3360 info->flag_buf = NULL;
3364 * allocate DMA descriptor lists.
3366 static int alloc_desc(struct slgt_info *info)
3371 /* allocate memory to hold descriptor lists */
3372 info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3373 &info->bufs_dma_addr);
3374 if (info->bufs == NULL)
3377 info->rbufs = (struct slgt_desc*)info->bufs;
3378 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3380 pbufs = (unsigned int)info->bufs_dma_addr;
3383 * Build circular lists of descriptors
3386 for (i=0; i < info->rbuf_count; i++) {
3387 /* physical address of this descriptor */
3388 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3390 /* physical address of next descriptor */
3391 if (i == info->rbuf_count - 1)
3392 info->rbufs[i].next = cpu_to_le32(pbufs);
3394 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3395 set_desc_count(info->rbufs[i], DMABUFSIZE);
3398 for (i=0; i < info->tbuf_count; i++) {
3399 /* physical address of this descriptor */
3400 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3402 /* physical address of next descriptor */
3403 if (i == info->tbuf_count - 1)
3404 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3406 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3412 static void free_desc(struct slgt_info *info)
3414 if (info->bufs != NULL) {
3415 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3422 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3425 for (i=0; i < count; i++) {
3426 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3428 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3433 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3436 for (i=0; i < count; i++) {
3437 if (bufs[i].buf == NULL)
3439 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3444 static int alloc_dma_bufs(struct slgt_info *info)
3446 info->rbuf_count = 32;
3447 info->tbuf_count = 32;
3449 if (alloc_desc(info) < 0 ||
3450 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3451 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3452 alloc_tmp_rbuf(info) < 0) {
3453 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3460 static void free_dma_bufs(struct slgt_info *info)
3463 free_bufs(info, info->rbufs, info->rbuf_count);
3464 free_bufs(info, info->tbufs, info->tbuf_count);
3467 free_tmp_rbuf(info);
3470 static int claim_resources(struct slgt_info *info)
3472 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3473 DBGERR(("%s reg addr conflict, addr=%08X\n",
3474 info->device_name, info->phys_reg_addr));
3475 info->init_error = DiagStatus_AddressConflict;
3479 info->reg_addr_requested = true;
3481 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3482 if (!info->reg_addr) {
3483 DBGERR(("%s can't map device registers, addr=%08X\n",
3484 info->device_name, info->phys_reg_addr));
3485 info->init_error = DiagStatus_CantAssignPciResources;
3491 release_resources(info);
3495 static void release_resources(struct slgt_info *info)
3497 if (info->irq_requested) {
3498 free_irq(info->irq_level, info);
3499 info->irq_requested = false;
3502 if (info->reg_addr_requested) {
3503 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3504 info->reg_addr_requested = false;
3507 if (info->reg_addr) {
3508 iounmap(info->reg_addr);
3509 info->reg_addr = NULL;
3513 /* Add the specified device instance data structure to the
3514 * global linked list of devices and increment the device count.
3516 static void add_device(struct slgt_info *info)
3520 info->next_device = NULL;
3521 info->line = slgt_device_count;
3522 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3524 if (info->line < MAX_DEVICES) {
3525 if (maxframe[info->line])
3526 info->max_frame_size = maxframe[info->line];
3529 slgt_device_count++;
3531 if (!slgt_device_list)
3532 slgt_device_list = info;
3534 struct slgt_info *current_dev = slgt_device_list;
3535 while(current_dev->next_device)
3536 current_dev = current_dev->next_device;
3537 current_dev->next_device = info;
3540 if (info->max_frame_size < 4096)
3541 info->max_frame_size = 4096;
3542 else if (info->max_frame_size > 65535)
3543 info->max_frame_size = 65535;
3545 switch(info->pdev->device) {
3546 case SYNCLINK_GT_DEVICE_ID:
3549 case SYNCLINK_GT2_DEVICE_ID:
3552 case SYNCLINK_GT4_DEVICE_ID:
3555 case SYNCLINK_AC_DEVICE_ID:
3557 info->params.mode = MGSL_MODE_ASYNC;
3560 devstr = "(unknown model)";
3562 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3563 devstr, info->device_name, info->phys_reg_addr,
3564 info->irq_level, info->max_frame_size);
3566 #if SYNCLINK_GENERIC_HDLC
3571 static const struct tty_port_operations slgt_port_ops = {
3572 .carrier_raised = carrier_raised,
3577 * allocate device instance structure, return NULL on failure
3579 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3581 struct slgt_info *info;
3583 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3586 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3587 driver_name, adapter_num, port_num));
3589 tty_port_init(&info->port);
3590 info->port.ops = &slgt_port_ops;
3591 info->magic = MGSL_MAGIC;
3592 INIT_WORK(&info->task, bh_handler);
3593 info->max_frame_size = 4096;
3594 info->base_clock = 14745600;
3595 info->rbuf_fill_level = DMABUFSIZE;
3596 info->port.close_delay = 5*HZ/10;
3597 info->port.closing_wait = 30*HZ;
3598 init_waitqueue_head(&info->status_event_wait_q);
3599 init_waitqueue_head(&info->event_wait_q);
3600 spin_lock_init(&info->netlock);
3601 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3602 info->idle_mode = HDLC_TXIDLE_FLAGS;
3603 info->adapter_num = adapter_num;
3604 info->port_num = port_num;
3606 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3607 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3609 /* Copy configuration info to device instance data */
3611 info->irq_level = pdev->irq;
3612 info->phys_reg_addr = pci_resource_start(pdev,0);
3614 info->bus_type = MGSL_BUS_TYPE_PCI;
3615 info->irq_flags = IRQF_SHARED;
3617 info->init_error = -1; /* assume error, set to 0 on successful init */
3623 static void device_init(int adapter_num, struct pci_dev *pdev)
3625 struct slgt_info *port_array[SLGT_MAX_PORTS];
3629 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3631 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3634 /* allocate device instances for all ports */
3635 for (i=0; i < port_count; ++i) {
3636 port_array[i] = alloc_dev(adapter_num, i, pdev);
3637 if (port_array[i] == NULL) {
3638 for (--i; i >= 0; --i) {
3639 tty_port_destroy(&port_array[i]->port);
3640 kfree(port_array[i]);
3646 /* give copy of port_array to all ports and add to device list */
3647 for (i=0; i < port_count; ++i) {
3648 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3649 add_device(port_array[i]);
3650 port_array[i]->port_count = port_count;
3651 spin_lock_init(&port_array[i]->lock);
3654 /* Allocate and claim adapter resources */
3655 if (!claim_resources(port_array[0])) {
3657 alloc_dma_bufs(port_array[0]);
3659 /* copy resource information from first port to others */
3660 for (i = 1; i < port_count; ++i) {
3661 port_array[i]->irq_level = port_array[0]->irq_level;
3662 port_array[i]->reg_addr = port_array[0]->reg_addr;
3663 alloc_dma_bufs(port_array[i]);
3666 if (request_irq(port_array[0]->irq_level,
3668 port_array[0]->irq_flags,
3669 port_array[0]->device_name,
3670 port_array[0]) < 0) {
3671 DBGERR(("%s request_irq failed IRQ=%d\n",
3672 port_array[0]->device_name,
3673 port_array[0]->irq_level));
3675 port_array[0]->irq_requested = true;
3676 adapter_test(port_array[0]);
3677 for (i=1 ; i < port_count ; i++) {
3678 port_array[i]->init_error = port_array[0]->init_error;
3679 port_array[i]->gpio_present = port_array[0]->gpio_present;
3684 for (i = 0; i < port_count; ++i) {
3685 struct slgt_info *info = port_array[i];
3686 tty_port_register_device(&info->port, serial_driver, info->line,
3691 static int init_one(struct pci_dev *dev,
3692 const struct pci_device_id *ent)
3694 if (pci_enable_device(dev)) {
3695 printk("error enabling pci device %p\n", dev);
3698 pci_set_master(dev);
3699 device_init(slgt_device_count, dev);
3703 static void remove_one(struct pci_dev *dev)
3707 static const struct tty_operations ops = {
3711 .put_char = put_char,
3712 .flush_chars = flush_chars,
3713 .write_room = write_room,
3714 .chars_in_buffer = chars_in_buffer,
3715 .flush_buffer = flush_buffer,
3717 .compat_ioctl = slgt_compat_ioctl,
3718 .throttle = throttle,
3719 .unthrottle = unthrottle,
3720 .send_xchar = send_xchar,
3721 .break_ctl = set_break,
3722 .wait_until_sent = wait_until_sent,
3723 .set_termios = set_termios,
3725 .start = tx_release,
3727 .tiocmget = tiocmget,
3728 .tiocmset = tiocmset,
3729 .get_icount = get_icount,
3730 .proc_fops = &synclink_gt_proc_fops,
3733 static void slgt_cleanup(void)
3736 struct slgt_info *info;
3737 struct slgt_info *tmp;
3739 printk(KERN_INFO "unload %s\n", driver_name);
3741 if (serial_driver) {
3742 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3743 tty_unregister_device(serial_driver, info->line);
3744 rc = tty_unregister_driver(serial_driver);
3746 DBGERR(("tty_unregister_driver error=%d\n", rc));
3747 put_tty_driver(serial_driver);
3751 info = slgt_device_list;
3754 info = info->next_device;
3757 /* release devices */
3758 info = slgt_device_list;
3760 #if SYNCLINK_GENERIC_HDLC
3763 free_dma_bufs(info);
3764 free_tmp_rbuf(info);
3765 if (info->port_num == 0)
3766 release_resources(info);
3768 info = info->next_device;
3769 tty_port_destroy(&tmp->port);
3774 pci_unregister_driver(&pci_driver);
3778 * Driver initialization entry point.
3780 static int __init slgt_init(void)
3784 printk(KERN_INFO "%s\n", driver_name);
3786 serial_driver = alloc_tty_driver(MAX_DEVICES);
3787 if (!serial_driver) {
3788 printk("%s can't allocate tty driver\n", driver_name);
3792 /* Initialize the tty_driver structure */
3794 serial_driver->driver_name = tty_driver_name;
3795 serial_driver->name = tty_dev_prefix;
3796 serial_driver->major = ttymajor;
3797 serial_driver->minor_start = 64;
3798 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3799 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3800 serial_driver->init_termios = tty_std_termios;
3801 serial_driver->init_termios.c_cflag =
3802 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3803 serial_driver->init_termios.c_ispeed = 9600;
3804 serial_driver->init_termios.c_ospeed = 9600;
3805 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3806 tty_set_operations(serial_driver, &ops);
3807 if ((rc = tty_register_driver(serial_driver)) < 0) {
3808 DBGERR(("%s can't register serial driver\n", driver_name));
3809 put_tty_driver(serial_driver);
3810 serial_driver = NULL;
3814 printk(KERN_INFO "%s, tty major#%d\n",
3815 driver_name, serial_driver->major);
3817 slgt_device_count = 0;
3818 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3819 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3822 pci_registered = true;
3824 if (!slgt_device_list)
3825 printk("%s no devices found\n",driver_name);
3834 static void __exit slgt_exit(void)
3839 module_init(slgt_init);
3840 module_exit(slgt_exit);
3843 * register access routines
3846 #define CALC_REGADDR() \
3847 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3849 reg_addr += (info->port_num) * 32; \
3850 else if (addr >= 0x40) \
3851 reg_addr += (info->port_num) * 16;
3853 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3856 return readb((void __iomem *)reg_addr);
3859 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3862 writeb(value, (void __iomem *)reg_addr);
3865 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3868 return readw((void __iomem *)reg_addr);
3871 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3874 writew(value, (void __iomem *)reg_addr);
3877 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3880 return readl((void __iomem *)reg_addr);
3883 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3886 writel(value, (void __iomem *)reg_addr);
3889 static void rdma_reset(struct slgt_info *info)
3894 wr_reg32(info, RDCSR, BIT1);
3896 /* wait for enable bit cleared */
3897 for(i=0 ; i < 1000 ; i++)
3898 if (!(rd_reg32(info, RDCSR) & BIT0))
3902 static void tdma_reset(struct slgt_info *info)
3907 wr_reg32(info, TDCSR, BIT1);
3909 /* wait for enable bit cleared */
3910 for(i=0 ; i < 1000 ; i++)
3911 if (!(rd_reg32(info, TDCSR) & BIT0))
3916 * enable internal loopback
3917 * TxCLK and RxCLK are generated from BRG
3918 * and TxD is looped back to RxD internally.
3920 static void enable_loopback(struct slgt_info *info)
3922 /* SCR (serial control) BIT2=loopback enable */
3923 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3925 if (info->params.mode != MGSL_MODE_ASYNC) {
3926 /* CCR (clock control)
3927 * 07..05 tx clock source (010 = BRG)
3928 * 04..02 rx clock source (010 = BRG)
3929 * 01 auxclk enable (0 = disable)
3930 * 00 BRG enable (1 = enable)
3934 wr_reg8(info, CCR, 0x49);
3936 /* set speed if available, otherwise use default */
3937 if (info->params.clock_speed)
3938 set_rate(info, info->params.clock_speed);
3940 set_rate(info, 3686400);
3945 * set baud rate generator to specified rate
3947 static void set_rate(struct slgt_info *info, u32 rate)
3950 unsigned int osc = info->base_clock;
3952 /* div = osc/rate - 1
3954 * Round div up if osc/rate is not integer to
3955 * force to next slowest rate.
3960 if (!(osc % rate) && div)
3962 wr_reg16(info, BDR, (unsigned short)div);
3966 static void rx_stop(struct slgt_info *info)
3970 /* disable and reset receiver */
3971 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3972 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3973 wr_reg16(info, RCR, val); /* clear reset bit */
3975 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3977 /* clear pending rx interrupts */
3978 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3982 info->rx_enabled = false;
3983 info->rx_restart = false;
3986 static void rx_start(struct slgt_info *info)
3990 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3992 /* clear pending rx overrun IRQ */
3993 wr_reg16(info, SSR, IRQ_RXOVER);
3995 /* reset and disable receiver */
3996 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3997 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3998 wr_reg16(info, RCR, val); /* clear reset bit */
4004 /* rx request when rx FIFO not empty */
4005 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4006 slgt_irq_on(info, IRQ_RXDATA);
4007 if (info->params.mode == MGSL_MODE_ASYNC) {
4008 /* enable saving of rx status */
4009 wr_reg32(info, RDCSR, BIT6);
4012 /* rx request when rx FIFO half full */
4013 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4014 /* set 1st descriptor address */
4015 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4017 if (info->params.mode != MGSL_MODE_ASYNC) {
4018 /* enable rx DMA and DMA interrupt */
4019 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4021 /* enable saving of rx status, rx DMA and DMA interrupt */
4022 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4026 slgt_irq_on(info, IRQ_RXOVER);
4028 /* enable receiver */
4029 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4031 info->rx_restart = false;
4032 info->rx_enabled = true;
4035 static void tx_start(struct slgt_info *info)
4037 if (!info->tx_enabled) {
4039 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4040 info->tx_enabled = true;
4043 if (desc_count(info->tbufs[info->tbuf_start])) {
4044 info->drop_rts_on_tx_done = false;
4046 if (info->params.mode != MGSL_MODE_ASYNC) {
4047 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4049 if (!(info->signals & SerialSignal_RTS)) {
4050 info->signals |= SerialSignal_RTS;
4052 info->drop_rts_on_tx_done = true;
4056 slgt_irq_off(info, IRQ_TXDATA);
4057 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4058 /* clear tx idle and underrun status bits */
4059 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4061 slgt_irq_off(info, IRQ_TXDATA);
4062 slgt_irq_on(info, IRQ_TXIDLE);
4063 /* clear tx idle status bit */
4064 wr_reg16(info, SSR, IRQ_TXIDLE);
4066 /* set 1st descriptor address and start DMA */
4067 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4068 wr_reg32(info, TDCSR, BIT2 + BIT0);
4069 info->tx_active = true;
4073 static void tx_stop(struct slgt_info *info)
4077 del_timer(&info->tx_timer);
4081 /* reset and disable transmitter */
4082 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4083 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4085 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4087 /* clear tx idle and underrun status bit */
4088 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4092 info->tx_enabled = false;
4093 info->tx_active = false;
4096 static void reset_port(struct slgt_info *info)
4098 if (!info->reg_addr)
4104 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4107 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4110 static void reset_adapter(struct slgt_info *info)
4113 for (i=0; i < info->port_count; ++i) {
4114 if (info->port_array[i])
4115 reset_port(info->port_array[i]);
4119 static void async_mode(struct slgt_info *info)
4123 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4129 * 15..13 mode, 010=async
4130 * 12..10 encoding, 000=NRZ
4132 * 08 1=odd parity, 0=even parity
4133 * 07 1=RTS driver control
4135 * 05..04 character length
4140 * 03 0=1 stop bit, 1=2 stop bits
4143 * 00 auto-CTS enable
4147 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4150 if (info->params.parity != ASYNC_PARITY_NONE) {
4152 if (info->params.parity == ASYNC_PARITY_ODD)
4156 switch (info->params.data_bits)
4158 case 6: val |= BIT4; break;
4159 case 7: val |= BIT5; break;
4160 case 8: val |= BIT5 + BIT4; break;
4163 if (info->params.stop_bits != 1)
4166 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4169 wr_reg16(info, TCR, val);
4173 * 15..13 mode, 010=async
4174 * 12..10 encoding, 000=NRZ
4176 * 08 1=odd parity, 0=even parity
4177 * 07..06 reserved, must be 0
4178 * 05..04 character length
4183 * 03 reserved, must be zero
4186 * 00 auto-DCD enable
4190 if (info->params.parity != ASYNC_PARITY_NONE) {
4192 if (info->params.parity == ASYNC_PARITY_ODD)
4196 switch (info->params.data_bits)
4198 case 6: val |= BIT4; break;
4199 case 7: val |= BIT5; break;
4200 case 8: val |= BIT5 + BIT4; break;
4203 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4206 wr_reg16(info, RCR, val);
4208 /* CCR (clock control)
4210 * 07..05 011 = tx clock source is BRG/16
4211 * 04..02 010 = rx clock source is BRG
4212 * 01 0 = auxclk disabled
4213 * 00 1 = BRG enabled
4217 wr_reg8(info, CCR, 0x69);
4221 /* SCR (serial control)
4223 * 15 1=tx req on FIFO half empty
4224 * 14 1=rx req on FIFO half full
4225 * 13 tx data IRQ enable
4226 * 12 tx idle IRQ enable
4227 * 11 rx break on IRQ enable
4228 * 10 rx data IRQ enable
4229 * 09 rx break off IRQ enable
4230 * 08 overrun IRQ enable
4235 * 03 0=16x sampling, 1=8x sampling
4236 * 02 1=txd->rxd internal loopback enable
4237 * 01 reserved, must be zero
4238 * 00 1=master IRQ enable
4240 val = BIT15 + BIT14 + BIT0;
4241 /* JCR[8] : 1 = x8 async mode feature available */
4242 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4243 ((info->base_clock < (info->params.data_rate * 16)) ||
4244 (info->base_clock % (info->params.data_rate * 16)))) {
4245 /* use 8x sampling */
4247 set_rate(info, info->params.data_rate * 8);
4249 /* use 16x sampling */
4250 set_rate(info, info->params.data_rate * 16);
4252 wr_reg16(info, SCR, val);
4254 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4256 if (info->params.loopback)
4257 enable_loopback(info);
4260 static void sync_mode(struct slgt_info *info)
4264 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4272 * 001=raw bit synchronous
4273 * 010=asynchronous/isochronous
4274 * 011=monosync byte synchronous
4275 * 100=bisync byte synchronous
4276 * 101=xsync byte synchronous
4280 * 07 1=RTS driver control
4281 * 06 preamble enable
4282 * 05..04 preamble length
4283 * 03 share open/close flag
4286 * 00 auto-CTS enable
4290 switch(info->params.mode) {
4291 case MGSL_MODE_XSYNC:
4292 val |= BIT15 + BIT13;
4294 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4295 case MGSL_MODE_BISYNC: val |= BIT15; break;
4296 case MGSL_MODE_RAW: val |= BIT13; break;
4298 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4301 switch(info->params.encoding)
4303 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4304 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4305 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4306 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4307 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4308 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4309 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4312 switch (info->params.crc_type & HDLC_CRC_MASK)
4314 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4315 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4318 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4321 switch (info->params.preamble_length)
4323 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4324 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4325 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4328 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4331 wr_reg16(info, TCR, val);
4333 /* TPR (transmit preamble) */
4335 switch (info->params.preamble)
4337 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4338 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4339 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4340 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4341 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4342 default: val = 0x7e; break;
4344 wr_reg8(info, TPR, (unsigned char)val);
4350 * 001=raw bit synchronous
4351 * 010=asynchronous/isochronous
4352 * 011=monosync byte synchronous
4353 * 100=bisync byte synchronous
4354 * 101=xsync byte synchronous
4358 * 07..03 reserved, must be 0
4361 * 00 auto-DCD enable
4365 switch(info->params.mode) {
4366 case MGSL_MODE_XSYNC:
4367 val |= BIT15 + BIT13;
4369 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4370 case MGSL_MODE_BISYNC: val |= BIT15; break;
4371 case MGSL_MODE_RAW: val |= BIT13; break;
4374 switch(info->params.encoding)
4376 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4377 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4378 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4379 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4380 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4381 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4382 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4385 switch (info->params.crc_type & HDLC_CRC_MASK)
4387 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4388 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4391 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4394 wr_reg16(info, RCR, val);
4396 /* CCR (clock control)
4398 * 07..05 tx clock source
4399 * 04..02 rx clock source
4405 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4407 // when RxC source is DPLL, BRG generates 16X DPLL
4408 // reference clock, so take TxC from BRG/16 to get
4409 // transmit clock at actual data rate
4410 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4411 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4413 val |= BIT6; /* 010, txclk = BRG */
4415 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4416 val |= BIT7; /* 100, txclk = DPLL Input */
4417 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4418 val |= BIT5; /* 001, txclk = RXC Input */
4420 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4421 val |= BIT3; /* 010, rxclk = BRG */
4422 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4423 val |= BIT4; /* 100, rxclk = DPLL */
4424 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4425 val |= BIT2; /* 001, rxclk = TXC Input */
4427 if (info->params.clock_speed)
4430 wr_reg8(info, CCR, (unsigned char)val);
4432 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4434 // program DPLL mode
4435 switch(info->params.encoding)
4437 case HDLC_ENCODING_BIPHASE_MARK:
4438 case HDLC_ENCODING_BIPHASE_SPACE:
4440 case HDLC_ENCODING_BIPHASE_LEVEL:
4441 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4442 val = BIT7 + BIT6; break;
4443 default: val = BIT6; // NRZ encodings
4445 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4447 // DPLL requires a 16X reference clock from BRG
4448 set_rate(info, info->params.clock_speed * 16);
4451 set_rate(info, info->params.clock_speed);
4457 /* SCR (serial control)
4459 * 15 1=tx req on FIFO half empty
4460 * 14 1=rx req on FIFO half full
4461 * 13 tx data IRQ enable
4462 * 12 tx idle IRQ enable
4463 * 11 underrun IRQ enable
4464 * 10 rx data IRQ enable
4465 * 09 rx idle IRQ enable
4466 * 08 overrun IRQ enable
4471 * 03 reserved, must be zero
4472 * 02 1=txd->rxd internal loopback enable
4473 * 01 reserved, must be zero
4474 * 00 1=master IRQ enable
4476 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4478 if (info->params.loopback)
4479 enable_loopback(info);
4483 * set transmit idle mode
4485 static void tx_set_idle(struct slgt_info *info)
4490 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4491 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4493 tcr = rd_reg16(info, TCR);
4494 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4495 /* disable preamble, set idle size to 16 bits */
4496 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4497 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4498 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4499 } else if (!(tcr & BIT6)) {
4500 /* preamble is disabled, set idle size to 8 bits */
4501 tcr &= ~(BIT5 + BIT4);
4503 wr_reg16(info, TCR, tcr);
4505 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4506 /* LSB of custom tx idle specified in tx idle register */
4507 val = (unsigned char)(info->idle_mode & 0xff);
4509 /* standard 8 bit idle patterns */
4510 switch(info->idle_mode)
4512 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4513 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4514 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4515 case HDLC_TXIDLE_ZEROS:
4516 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4517 default: val = 0xff;
4521 wr_reg8(info, TIR, val);
4525 * get state of V24 status (input) signals
4527 static void get_signals(struct slgt_info *info)
4529 unsigned short status = rd_reg16(info, SSR);
4531 /* clear all serial signals except RTS and DTR */
4532 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4535 info->signals |= SerialSignal_DSR;
4537 info->signals |= SerialSignal_CTS;
4539 info->signals |= SerialSignal_DCD;
4541 info->signals |= SerialSignal_RI;
4545 * set V.24 Control Register based on current configuration
4547 static void msc_set_vcr(struct slgt_info *info)
4549 unsigned char val = 0;
4551 /* VCR (V.24 control)
4553 * 07..04 serial IF select
4560 switch(info->if_mode & MGSL_INTERFACE_MASK)
4562 case MGSL_INTERFACE_RS232:
4563 val |= BIT5; /* 0010 */
4565 case MGSL_INTERFACE_V35:
4566 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4568 case MGSL_INTERFACE_RS422:
4569 val |= BIT6; /* 0100 */
4573 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4575 if (info->signals & SerialSignal_DTR)
4577 if (info->signals & SerialSignal_RTS)
4579 if (info->if_mode & MGSL_INTERFACE_LL)
4581 if (info->if_mode & MGSL_INTERFACE_RL)
4583 wr_reg8(info, VCR, val);
4587 * set state of V24 control (output) signals
4589 static void set_signals(struct slgt_info *info)
4591 unsigned char val = rd_reg8(info, VCR);
4592 if (info->signals & SerialSignal_DTR)
4596 if (info->signals & SerialSignal_RTS)
4600 wr_reg8(info, VCR, val);
4604 * free range of receive DMA buffers (i to last)
4606 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4611 /* reset current buffer for reuse */
4612 info->rbufs[i].status = 0;
4613 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4616 if (++i == info->rbuf_count)
4619 info->rbuf_current = i;
4623 * mark all receive DMA buffers as free
4625 static void reset_rbufs(struct slgt_info *info)
4627 free_rbufs(info, 0, info->rbuf_count - 1);
4628 info->rbuf_fill_index = 0;
4629 info->rbuf_fill_count = 0;
4633 * pass receive HDLC frame to upper layer
4635 * return true if frame available, otherwise false
4637 static bool rx_get_frame(struct slgt_info *info)
4639 unsigned int start, end;
4640 unsigned short status;
4641 unsigned int framesize = 0;
4642 unsigned long flags;
4643 struct tty_struct *tty = info->port.tty;
4644 unsigned char addr_field = 0xff;
4645 unsigned int crc_size = 0;
4647 switch (info->params.crc_type & HDLC_CRC_MASK) {
4648 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4649 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4656 start = end = info->rbuf_current;
4659 if (!desc_complete(info->rbufs[end]))
4662 if (framesize == 0 && info->params.addr_filter != 0xff)
4663 addr_field = info->rbufs[end].buf[0];
4665 framesize += desc_count(info->rbufs[end]);
4667 if (desc_eof(info->rbufs[end]))
4670 if (++end == info->rbuf_count)
4673 if (end == info->rbuf_current) {
4674 if (info->rx_enabled){
4675 spin_lock_irqsave(&info->lock,flags);
4677 spin_unlock_irqrestore(&info->lock,flags);
4685 * 15 buffer complete
4688 * 02 eof (end of frame)
4692 status = desc_status(info->rbufs[end]);
4694 /* ignore CRC bit if not using CRC (bit is undefined) */
4695 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4698 if (framesize == 0 ||
4699 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4700 free_rbufs(info, start, end);
4704 if (framesize < (2 + crc_size) || status & BIT0) {
4705 info->icount.rxshort++;
4707 } else if (status & BIT1) {
4708 info->icount.rxcrc++;
4709 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4713 #if SYNCLINK_GENERIC_HDLC
4714 if (framesize == 0) {
4715 info->netdev->stats.rx_errors++;
4716 info->netdev->stats.rx_frame_errors++;
4720 DBGBH(("%s rx frame status=%04X size=%d\n",
4721 info->device_name, status, framesize));
4722 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4725 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4726 framesize -= crc_size;
4730 if (framesize > info->max_frame_size + crc_size)
4731 info->icount.rxlong++;
4733 /* copy dma buffer(s) to contiguous temp buffer */
4734 int copy_count = framesize;
4736 unsigned char *p = info->tmp_rbuf;
4737 info->tmp_rbuf_count = framesize;
4739 info->icount.rxok++;
4742 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4743 memcpy(p, info->rbufs[i].buf, partial_count);
4745 copy_count -= partial_count;
4746 if (++i == info->rbuf_count)
4750 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4751 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4755 #if SYNCLINK_GENERIC_HDLC
4757 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4760 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4763 free_rbufs(info, start, end);
4771 * pass receive buffer (RAW synchronous mode) to tty layer
4772 * return true if buffer available, otherwise false
4774 static bool rx_get_buf(struct slgt_info *info)
4776 unsigned int i = info->rbuf_current;
4779 if (!desc_complete(info->rbufs[i]))
4781 count = desc_count(info->rbufs[i]);
4782 switch(info->params.mode) {
4783 case MGSL_MODE_MONOSYNC:
4784 case MGSL_MODE_BISYNC:
4785 case MGSL_MODE_XSYNC:
4786 /* ignore residue in byte synchronous modes */
4787 if (desc_residue(info->rbufs[i]))
4791 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4792 DBGINFO(("rx_get_buf size=%d\n", count));
4794 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4795 info->flag_buf, count);
4796 free_rbufs(info, i, i);
4800 static void reset_tbufs(struct slgt_info *info)
4803 info->tbuf_current = 0;
4804 for (i=0 ; i < info->tbuf_count ; i++) {
4805 info->tbufs[i].status = 0;
4806 info->tbufs[i].count = 0;
4811 * return number of free transmit DMA buffers
4813 static unsigned int free_tbuf_count(struct slgt_info *info)
4815 unsigned int count = 0;
4816 unsigned int i = info->tbuf_current;
4820 if (desc_count(info->tbufs[i]))
4821 break; /* buffer in use */
4823 if (++i == info->tbuf_count)
4825 } while (i != info->tbuf_current);
4827 /* if tx DMA active, last zero count buffer is in use */
4828 if (count && (rd_reg32(info, TDCSR) & BIT0))
4835 * return number of bytes in unsent transmit DMA buffers
4836 * and the serial controller tx FIFO
4838 static unsigned int tbuf_bytes(struct slgt_info *info)
4840 unsigned int total_count = 0;
4841 unsigned int i = info->tbuf_current;
4842 unsigned int reg_value;
4844 unsigned int active_buf_count = 0;
4847 * Add descriptor counts for all tx DMA buffers.
4848 * If count is zero (cleared by DMA controller after read),
4849 * the buffer is complete or is actively being read from.
4851 * Record buf_count of last buffer with zero count starting
4852 * from current ring position. buf_count is mirror
4853 * copy of count and is not cleared by serial controller.
4854 * If DMA controller is active, that buffer is actively
4855 * being read so add to total.
4858 count = desc_count(info->tbufs[i]);
4860 total_count += count;
4861 else if (!total_count)
4862 active_buf_count = info->tbufs[i].buf_count;
4863 if (++i == info->tbuf_count)
4865 } while (i != info->tbuf_current);
4867 /* read tx DMA status register */
4868 reg_value = rd_reg32(info, TDCSR);
4870 /* if tx DMA active, last zero count buffer is in use */
4871 if (reg_value & BIT0)
4872 total_count += active_buf_count;
4874 /* add tx FIFO count = reg_value[15..8] */
4875 total_count += (reg_value >> 8) & 0xff;
4877 /* if transmitter active add one byte for shift register */
4878 if (info->tx_active)
4885 * load data into transmit DMA buffer ring and start transmitter if needed
4886 * return true if data accepted, otherwise false (buffers full)
4888 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4890 unsigned short count;
4892 struct slgt_desc *d;
4894 /* check required buffer space */
4895 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4898 DBGDATA(info, buf, size, "tx");
4901 * copy data to one or more DMA buffers in circular ring
4902 * tbuf_start = first buffer for this data
4903 * tbuf_current = next free buffer
4905 * Copy all data before making data visible to DMA controller by
4906 * setting descriptor count of the first buffer.
4907 * This prevents an active DMA controller from reading the first DMA
4908 * buffers of a frame and stopping before the final buffers are filled.
4911 info->tbuf_start = i = info->tbuf_current;
4914 d = &info->tbufs[i];
4916 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4917 memcpy(d->buf, buf, count);
4923 * set EOF bit for last buffer of HDLC frame or
4924 * for every buffer in raw mode
4926 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4927 info->params.mode == MGSL_MODE_RAW)
4928 set_desc_eof(*d, 1);
4930 set_desc_eof(*d, 0);
4932 /* set descriptor count for all but first buffer */
4933 if (i != info->tbuf_start)
4934 set_desc_count(*d, count);
4935 d->buf_count = count;
4937 if (++i == info->tbuf_count)
4941 info->tbuf_current = i;
4943 /* set first buffer count to make new data visible to DMA controller */
4944 d = &info->tbufs[info->tbuf_start];
4945 set_desc_count(*d, d->buf_count);
4947 /* start transmitter if needed and update transmit timeout */
4948 if (!info->tx_active)
4950 update_tx_timer(info);
4955 static int register_test(struct slgt_info *info)
4957 static unsigned short patterns[] =
4958 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4959 static unsigned int count = ARRAY_SIZE(patterns);
4963 for (i=0 ; i < count ; i++) {
4964 wr_reg16(info, TIR, patterns[i]);
4965 wr_reg16(info, BDR, patterns[(i+1)%count]);
4966 if ((rd_reg16(info, TIR) != patterns[i]) ||
4967 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4972 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4973 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4977 static int irq_test(struct slgt_info *info)
4979 unsigned long timeout;
4980 unsigned long flags;
4981 struct tty_struct *oldtty = info->port.tty;
4982 u32 speed = info->params.data_rate;
4984 info->params.data_rate = 921600;
4985 info->port.tty = NULL;
4987 spin_lock_irqsave(&info->lock, flags);
4989 slgt_irq_on(info, IRQ_TXIDLE);
4991 /* enable transmitter */
4993 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4995 /* write one byte and wait for tx idle */
4996 wr_reg16(info, TDR, 0);
4998 /* assume failure */
4999 info->init_error = DiagStatus_IrqFailure;
5000 info->irq_occurred = false;
5002 spin_unlock_irqrestore(&info->lock, flags);
5005 while(timeout-- && !info->irq_occurred)
5006 msleep_interruptible(10);
5008 spin_lock_irqsave(&info->lock,flags);
5010 spin_unlock_irqrestore(&info->lock,flags);
5012 info->params.data_rate = speed;
5013 info->port.tty = oldtty;
5015 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5016 return info->irq_occurred ? 0 : -ENODEV;
5019 static int loopback_test_rx(struct slgt_info *info)
5021 unsigned char *src, *dest;
5024 if (desc_complete(info->rbufs[0])) {
5025 count = desc_count(info->rbufs[0]);
5026 src = info->rbufs[0].buf;
5027 dest = info->tmp_rbuf;
5029 for( ; count ; count-=2, src+=2) {
5030 /* src=data byte (src+1)=status byte */
5031 if (!(*(src+1) & (BIT9 + BIT8))) {
5034 info->tmp_rbuf_count++;
5037 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5043 static int loopback_test(struct slgt_info *info)
5045 #define TESTFRAMESIZE 20
5047 unsigned long timeout;
5048 u16 count = TESTFRAMESIZE;
5049 unsigned char buf[TESTFRAMESIZE];
5051 unsigned long flags;
5053 struct tty_struct *oldtty = info->port.tty;
5056 memcpy(¶ms, &info->params, sizeof(params));
5058 info->params.mode = MGSL_MODE_ASYNC;
5059 info->params.data_rate = 921600;
5060 info->params.loopback = 1;
5061 info->port.tty = NULL;
5063 /* build and send transmit frame */
5064 for (count = 0; count < TESTFRAMESIZE; ++count)
5065 buf[count] = (unsigned char)count;
5067 info->tmp_rbuf_count = 0;
5068 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5070 /* program hardware for HDLC and enabled receiver */
5071 spin_lock_irqsave(&info->lock,flags);
5074 tx_load(info, buf, count);
5075 spin_unlock_irqrestore(&info->lock, flags);
5077 /* wait for receive complete */
5078 for (timeout = 100; timeout; --timeout) {
5079 msleep_interruptible(10);
5080 if (loopback_test_rx(info)) {
5086 /* verify received frame length and contents */
5087 if (!rc && (info->tmp_rbuf_count != count ||
5088 memcmp(buf, info->tmp_rbuf, count))) {
5092 spin_lock_irqsave(&info->lock,flags);
5093 reset_adapter(info);
5094 spin_unlock_irqrestore(&info->lock,flags);
5096 memcpy(&info->params, ¶ms, sizeof(info->params));
5097 info->port.tty = oldtty;
5099 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5103 static int adapter_test(struct slgt_info *info)
5105 DBGINFO(("testing %s\n", info->device_name));
5106 if (register_test(info) < 0) {
5107 printk("register test failure %s addr=%08X\n",
5108 info->device_name, info->phys_reg_addr);
5109 } else if (irq_test(info) < 0) {
5110 printk("IRQ test failure %s IRQ=%d\n",
5111 info->device_name, info->irq_level);
5112 } else if (loopback_test(info) < 0) {
5113 printk("loopback test failure %s\n", info->device_name);
5115 return info->init_error;
5119 * transmit timeout handler
5121 static void tx_timeout(unsigned long context)
5123 struct slgt_info *info = (struct slgt_info*)context;
5124 unsigned long flags;
5126 DBGINFO(("%s tx_timeout\n", info->device_name));
5127 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5128 info->icount.txtimeout++;
5130 spin_lock_irqsave(&info->lock,flags);
5132 spin_unlock_irqrestore(&info->lock,flags);
5134 #if SYNCLINK_GENERIC_HDLC
5136 hdlcdev_tx_done(info);
5143 * receive buffer polling timer
5145 static void rx_timeout(unsigned long context)
5147 struct slgt_info *info = (struct slgt_info*)context;
5148 unsigned long flags;
5150 DBGINFO(("%s rx_timeout\n", info->device_name));
5151 spin_lock_irqsave(&info->lock, flags);
5152 info->pending_bh |= BH_RECEIVE;
5153 spin_unlock_irqrestore(&info->lock, flags);
5154 bh_handler(&info->task);