drivers/tty/synclink_gt.c

   1 /*
   2  * Device driver for Microgate SyncLink GT serial adapters.
   3  *
   4  * written by Paul Fulghum for Microgate Corporation
   5  * paulkf@microgate.com
   6  *
   7  * Microgate and SyncLink are trademarks of Microgate Corporation
   8  *
   9  * This code is released under the GNU General Public License (GPL)
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21  * OF THE POSSIBILITY OF SUCH DAMAGE.
  22  */
  23
  24 /*
  25  * DEBUG OUTPUT DEFINITIONS
  26  *
  27  * uncomment lines below to enable specific types of debug output
  28  *
  29  * DBGINFO   information - most verbose output
  30  * DBGERR    serious errors
  31  * DBGBH     bottom half service routine debugging
  32  * DBGISR    interrupt service routine debugging
  33  * DBGDATA   output receive and transmit data
  34  * DBGTBUF   output transmit DMA buffers and registers
  35  * DBGRBUF   output receive DMA buffers and registers
  36  */
  37
  38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43 /*#define DBGTBUF(info) dump_tbufs(info)*/
  44 /*#define DBGRBUF(info) dump_rbufs(info)*/
  45
  46
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/signal.h>
  50 #include <linux/sched.h>
  51 #include <linux/timer.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/tty.h>
  55 #include <linux/tty_flip.h>
  56 #include <linux/serial.h>
  57 #include <linux/major.h>
  58 #include <linux/string.h>
  59 #include <linux/fcntl.h>
  60 #include <linux/ptrace.h>
  61 #include <linux/ioport.h>
  62 #include <linux/mm.h>
  63 #include <linux/seq_file.h>
  64 #include <linux/slab.h>
  65 #include <linux/netdevice.h>
  66 #include <linux/vmalloc.h>
  67 #include <linux/init.h>
  68 #include <linux/delay.h>
  69 #include <linux/ioctl.h>
  70 #include <linux/termios.h>
  71 #include <linux/bitops.h>
  72 #include <linux/workqueue.h>
  73 #include <linux/hdlc.h>
  74 #include <linux/synclink.h>
  75
  76 #include <asm/io.h>
  77 #include <asm/irq.h>
  78 #include <asm/dma.h>
  79 #include <asm/types.h>
  80 #include <asm/uaccess.h>
  81
  82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  83 #define SYNCLINK_GENERIC_HDLC 1
  84 #else
  85 #define SYNCLINK_GENERIC_HDLC 0
  86 #endif
  87
  88 /*
  89  * module identification
  90  */
  91 static char *driver_name     = "SyncLink GT";
  92 static char *slgt_driver_name = "synclink_gt";
  93 static char *tty_dev_prefix  = "ttySLG";
  94 MODULE_LICENSE("GPL");
  95 #define MGSL_MAGIC 0x5401
  96 #define MAX_DEVICES 32
  97
  98 static struct pci_device_id pci_table[] = {
  99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {0,}, /* terminate list */
 104 };
 105 MODULE_DEVICE_TABLE(pci, pci_table);
 106
 107 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 108 static void remove_one(struct pci_dev *dev);
 109 static struct pci_driver pci_driver = {
 110         .name           = "synclink_gt",
 111         .id_table       = pci_table,
 112         .probe          = init_one,
 113         .remove         = remove_one,
 114 };
 115
 116 static bool pci_registered;
 117
 118 /*
 119  * module configuration and status
 120  */
 121 static struct slgt_info *slgt_device_list;
 122 static int slgt_device_count;
 123
 124 static int ttymajor;
 125 static int debug_level;
 126 static int maxframe[MAX_DEVICES];
 127
 128 module_param(ttymajor, int, 0);
 129 module_param(debug_level, int, 0);
 130 module_param_array(maxframe, int, NULL, 0);
 131
 132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 135
 136 /*
 137  * tty support and callbacks
 138  */
 139 static struct tty_driver *serial_driver;
 140
 141 static int  open(struct tty_struct *tty, struct file * filp);
 142 static void close(struct tty_struct *tty, struct file * filp);
 143 static void hangup(struct tty_struct *tty);
 144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 145
 146 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 147 static int put_char(struct tty_struct *tty, unsigned char ch);
 148 static void send_xchar(struct tty_struct *tty, char ch);
 149 static void wait_until_sent(struct tty_struct *tty, int timeout);
 150 static int  write_room(struct tty_struct *tty);
 151 static void flush_chars(struct tty_struct *tty);
 152 static void flush_buffer(struct tty_struct *tty);
 153 static void tx_hold(struct tty_struct *tty);
 154 static void tx_release(struct tty_struct *tty);
 155
 156 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
 157 static int  chars_in_buffer(struct tty_struct *tty);
 158 static void throttle(struct tty_struct * tty);
 159 static void unthrottle(struct tty_struct * tty);
 160 static int set_break(struct tty_struct *tty, int break_state);
 161
 162 /*
 163  * generic HDLC support and callbacks
 164  */
 165 #if SYNCLINK_GENERIC_HDLC
 166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 167 static void hdlcdev_tx_done(struct slgt_info *info);
 168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 169 static int  hdlcdev_init(struct slgt_info *info);
 170 static void hdlcdev_exit(struct slgt_info *info);
 171 #endif
 172
 173
 174 /*
 175  * device specific structures, macros and functions
 176  */
 177
 178 #define SLGT_MAX_PORTS 4
 179 #define SLGT_REG_SIZE  256
 180
 181 /*
 182  * conditional wait facility
 183  */
 184 struct cond_wait {
 185         struct cond_wait *next;
 186         wait_queue_head_t q;
 187         wait_queue_t wait;
 188         unsigned int data;
 189 };
 190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 193 static void flush_cond_wait(struct cond_wait **head);
 194
 195 /*
 196  * DMA buffer descriptor and access macros
 197  */
 198 struct slgt_desc
 199 {
 200         __le16 count;
 201         __le16 status;
 202         __le32 pbuf;  /* physical address of data buffer */
 203         __le32 next;  /* physical address of next descriptor */
 204
 205         /* driver book keeping */
 206         char *buf;          /* virtual  address of data buffer */
 207         unsigned int pdesc; /* physical address of this descriptor */
 208         dma_addr_t buf_dma_addr;
 209         unsigned short buf_count;
 210 };
 211
 212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 213 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 214 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 215 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 217 #define desc_count(a)      (le16_to_cpu((a).count))
 218 #define desc_status(a)     (le16_to_cpu((a).status))
 219 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 220 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 221 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 222 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 223 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 224
 225 struct _input_signal_events {
 226         int ri_up;
 227         int ri_down;
 228         int dsr_up;
 229         int dsr_down;
 230         int dcd_up;
 231         int dcd_down;
 232         int cts_up;
 233         int cts_down;
 234 };
 235
 236 /*
 237  * device instance data structure
 238  */
 239 struct slgt_info {
 240         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 241         struct tty_port port;
 242
 243         struct slgt_info *next_device;  /* device list link */
 244
 245         int magic;
 246
 247         char device_name[25];
 248         struct pci_dev *pdev;
 249
 250         int port_count;  /* count of ports on adapter */
 251         int adapter_num; /* adapter instance number */
 252         int port_num;    /* port instance number */
 253
 254         /* array of pointers to port contexts on this adapter */
 255         struct slgt_info *port_array[SLGT_MAX_PORTS];
 256
 257         int                     line;           /* tty line instance number */
 258
 259         struct mgsl_icount      icount;
 260
 261         int                     timeout;
 262         int                     x_char;         /* xon/xoff character */
 263         unsigned int            read_status_mask;
 264         unsigned int            ignore_status_mask;
 265
 266         wait_queue_head_t       status_event_wait_q;
 267         wait_queue_head_t       event_wait_q;
 268         struct timer_list       tx_timer;
 269         struct timer_list       rx_timer;
 270
 271         unsigned int            gpio_present;
 272         struct cond_wait        *gpio_wait_q;
 273
 274         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 275
 276         struct work_struct task;
 277         u32 pending_bh;
 278         bool bh_requested;
 279         bool bh_running;
 280
 281         int isr_overflow;
 282         bool irq_requested;     /* true if IRQ requested */
 283         bool irq_occurred;      /* for diagnostics use */
 284
 285         /* device configuration */
 286
 287         unsigned int bus_type;
 288         unsigned int irq_level;
 289         unsigned long irq_flags;
 290
 291         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 292         u32 phys_reg_addr;
 293         bool reg_addr_requested;
 294
 295         MGSL_PARAMS params;       /* communications parameters */
 296         u32 idle_mode;
 297         u32 max_frame_size;       /* as set by device config */
 298
 299         unsigned int rbuf_fill_level;
 300         unsigned int rx_pio;
 301         unsigned int if_mode;
 302         unsigned int base_clock;
 303         unsigned int xsync;
 304         unsigned int xctrl;
 305
 306         /* device status */
 307
 308         bool rx_enabled;
 309         bool rx_restart;
 310
 311         bool tx_enabled;
 312         bool tx_active;
 313
 314         unsigned char signals;    /* serial signal states */
 315         int init_error;  /* initialization error */
 316
 317         unsigned char *tx_buf;
 318         int tx_count;
 319
 320         char *flag_buf;
 321         bool drop_rts_on_tx_done;
 322         struct  _input_signal_events    input_signal_events;
 323
 324         int dcd_chkcount;       /* check counts to prevent */
 325         int cts_chkcount;       /* too many IRQs if a signal */
 326         int dsr_chkcount;       /* is floating */
 327         int ri_chkcount;
 328
 329         char *bufs;             /* virtual address of DMA buffer lists */
 330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332         unsigned int rbuf_count;
 333         struct slgt_desc *rbufs;
 334         unsigned int rbuf_current;
 335         unsigned int rbuf_index;
 336         unsigned int rbuf_fill_index;
 337         unsigned short rbuf_fill_count;
 338
 339         unsigned int tbuf_count;
 340         struct slgt_desc *tbufs;
 341         unsigned int tbuf_current;
 342         unsigned int tbuf_start;
 343
 344         unsigned char *tmp_rbuf;
 345         unsigned int tmp_rbuf_count;
 346
 347         /* SPPP/Cisco HDLC device parts */
 348
 349         int netcount;
 350         spinlock_t netlock;
 351 #if SYNCLINK_GENERIC_HDLC
 352         struct net_device *netdev;
 353 #endif
 354
 355 };
 356
 357 static MGSL_PARAMS default_params = {
 358         .mode            = MGSL_MODE_HDLC,
 359         .loopback        = 0,
 360         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 361         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 362         .clock_speed     = 0,
 363         .addr_filter     = 0xff,
 364         .crc_type        = HDLC_CRC_16_CCITT,
 365         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 366         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 367         .data_rate       = 9600,
 368         .data_bits       = 8,
 369         .stop_bits       = 1,
 370         .parity          = ASYNC_PARITY_NONE
 371 };
 372
 373
 374 #define BH_RECEIVE  1
 375 #define BH_TRANSMIT 2
 376 #define BH_STATUS   4
 377 #define IO_PIN_SHUTDOWN_LIMIT 100
 378
 379 #define DMABUFSIZE 256
 380 #define DESC_LIST_SIZE 4096
 381
 382 #define MASK_PARITY  BIT1
 383 #define MASK_FRAMING BIT0
 384 #define MASK_BREAK   BIT14
 385 #define MASK_OVERRUN BIT4
 386
 387 #define GSR   0x00 /* global status */
 388 #define JCR   0x04 /* JTAG control */
 389 #define IODR  0x08 /* GPIO direction */
 390 #define IOER  0x0c /* GPIO interrupt enable */
 391 #define IOVR  0x10 /* GPIO value */
 392 #define IOSR  0x14 /* GPIO interrupt status */
 393 #define TDR   0x80 /* tx data */
 394 #define RDR   0x80 /* rx data */
 395 #define TCR   0x82 /* tx control */
 396 #define TIR   0x84 /* tx idle */
 397 #define TPR   0x85 /* tx preamble */
 398 #define RCR   0x86 /* rx control */
 399 #define VCR   0x88 /* V.24 control */
 400 #define CCR   0x89 /* clock control */
 401 #define BDR   0x8a /* baud divisor */
 402 #define SCR   0x8c /* serial control */
 403 #define SSR   0x8e /* serial status */
 404 #define RDCSR 0x90 /* rx DMA control/status */
 405 #define TDCSR 0x94 /* tx DMA control/status */
 406 #define RDDAR 0x98 /* rx DMA descriptor address */
 407 #define TDDAR 0x9c /* tx DMA descriptor address */
 408 #define XSR   0x40 /* extended sync pattern */
 409 #define XCR   0x44 /* extended control */
 410
 411 #define RXIDLE      BIT14
 412 #define RXBREAK     BIT14
 413 #define IRQ_TXDATA  BIT13
 414 #define IRQ_TXIDLE  BIT12
 415 #define IRQ_TXUNDER BIT11 /* HDLC */
 416 #define IRQ_RXDATA  BIT10
 417 #define IRQ_RXIDLE  BIT9  /* HDLC */
 418 #define IRQ_RXBREAK BIT9  /* async */
 419 #define IRQ_RXOVER  BIT8
 420 #define IRQ_DSR     BIT7
 421 #define IRQ_CTS     BIT6
 422 #define IRQ_DCD     BIT5
 423 #define IRQ_RI      BIT4
 424 #define IRQ_ALL     0x3ff0
 425 #define IRQ_MASTER  BIT0
 426
 427 #define slgt_irq_on(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 429 #define slgt_irq_off(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 431
 432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 438
 439 static void  msc_set_vcr(struct slgt_info *info);
 440
 441 static int  startup(struct slgt_info *info);
 442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 443 static void shutdown(struct slgt_info *info);
 444 static void program_hw(struct slgt_info *info);
 445 static void change_params(struct slgt_info *info);
 446
 447 static int  register_test(struct slgt_info *info);
 448 static int  irq_test(struct slgt_info *info);
 449 static int  loopback_test(struct slgt_info *info);
 450 static int  adapter_test(struct slgt_info *info);
 451
 452 static void reset_adapter(struct slgt_info *info);
 453 static void reset_port(struct slgt_info *info);
 454 static void async_mode(struct slgt_info *info);
 455 static void sync_mode(struct slgt_info *info);
 456
 457 static void rx_stop(struct slgt_info *info);
 458 static void rx_start(struct slgt_info *info);
 459 static void reset_rbufs(struct slgt_info *info);
 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 461 static void rdma_reset(struct slgt_info *info);
 462 static bool rx_get_frame(struct slgt_info *info);
 463 static bool rx_get_buf(struct slgt_info *info);
 464
 465 static void tx_start(struct slgt_info *info);
 466 static void tx_stop(struct slgt_info *info);
 467 static void tx_set_idle(struct slgt_info *info);
 468 static unsigned int free_tbuf_count(struct slgt_info *info);
 469 static unsigned int tbuf_bytes(struct slgt_info *info);
 470 static void reset_tbufs(struct slgt_info *info);
 471 static void tdma_reset(struct slgt_info *info);
 472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 473
 474 static void get_signals(struct slgt_info *info);
 475 static void set_signals(struct slgt_info *info);
 476 static void enable_loopback(struct slgt_info *info);
 477 static void set_rate(struct slgt_info *info, u32 data_rate);
 478
 479 static int  bh_action(struct slgt_info *info);
 480 static void bh_handler(struct work_struct *work);
 481 static void bh_transmit(struct slgt_info *info);
 482 static void isr_serial(struct slgt_info *info);
 483 static void isr_rdma(struct slgt_info *info);
 484 static void isr_txeom(struct slgt_info *info, unsigned short status);
 485 static void isr_tdma(struct slgt_info *info);
 486
 487 static int  alloc_dma_bufs(struct slgt_info *info);
 488 static void free_dma_bufs(struct slgt_info *info);
 489 static int  alloc_desc(struct slgt_info *info);
 490 static void free_desc(struct slgt_info *info);
 491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 493
 494 static int  alloc_tmp_rbuf(struct slgt_info *info);
 495 static void free_tmp_rbuf(struct slgt_info *info);
 496
 497 static void tx_timeout(unsigned long context);
 498 static void rx_timeout(unsigned long context);
 499
 500 /*
 501  * ioctl handlers
 502  */
 503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 507 static int  set_txidle(struct slgt_info *info, int idle_mode);
 508 static int  tx_enable(struct slgt_info *info, int enable);
 509 static int  tx_abort(struct slgt_info *info);
 510 static int  rx_enable(struct slgt_info *info, int enable);
 511 static int  modem_input_wait(struct slgt_info *info,int arg);
 512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 513 static int  tiocmget(struct tty_struct *tty);
 514 static int  tiocmset(struct tty_struct *tty,
 515                                 unsigned int set, unsigned int clear);
 516 static int set_break(struct tty_struct *tty, int break_state);
 517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 518 static int  set_interface(struct slgt_info *info, int if_mode);
 519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 523 static int  set_xsync(struct slgt_info *info, int if_mode);
 524 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 525 static int  set_xctrl(struct slgt_info *info, int if_mode);
 526
 527 /*
 528  * driver functions
 529  */
 530 static void add_device(struct slgt_info *info);
 531 static void device_init(int adapter_num, struct pci_dev *pdev);
 532 static int  claim_resources(struct slgt_info *info);
 533 static void release_resources(struct slgt_info *info);
 534
 535 /*
 536  * DEBUG OUTPUT CODE
 537  */
 538 #ifndef DBGINFO
 539 #define DBGINFO(fmt)
 540 #endif
 541 #ifndef DBGERR
 542 #define DBGERR(fmt)
 543 #endif
 544 #ifndef DBGBH
 545 #define DBGBH(fmt)
 546 #endif
 547 #ifndef DBGISR
 548 #define DBGISR(fmt)
 549 #endif
 550
 551 #ifdef DBGDATA
 552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 553 {
 554         int i;
 555         int linecount;
 556         printk("%s %s data:\n",info->device_name, label);
 557         while(count) {
 558                 linecount = (count > 16) ? 16 : count;
 559                 for(i=0; i < linecount; i++)
 560                         printk("%02X ",(unsigned char)data[i]);
 561                 for(;i<17;i++)
 562                         printk("   ");
 563                 for(i=0;i<linecount;i++) {
 564                         if (data[i]>=040 && data[i]<=0176)
 565                                 printk("%c",data[i]);
 566                         else
 567                                 printk(".");
 568                 }
 569                 printk("\n");
 570                 data  += linecount;
 571                 count -= linecount;
 572         }
 573 }
 574 #else
 575 #define DBGDATA(info, buf, size, label)
 576 #endif
 577
 578 #ifdef DBGTBUF
 579 static void dump_tbufs(struct slgt_info *info)
 580 {
 581         int i;
 582         printk("tbuf_current=%d\n", info->tbuf_current);
 583         for (i=0 ; i < info->tbuf_count ; i++) {
 584                 printk("%d: count=%04X status=%04X\n",
 585                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 586         }
 587 }
 588 #else
 589 #define DBGTBUF(info)
 590 #endif
 591
 592 #ifdef DBGRBUF
 593 static void dump_rbufs(struct slgt_info *info)
 594 {
 595         int i;
 596         printk("rbuf_current=%d\n", info->rbuf_current);
 597         for (i=0 ; i < info->rbuf_count ; i++) {
 598                 printk("%d: count=%04X status=%04X\n",
 599                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 600         }
 601 }
 602 #else
 603 #define DBGRBUF(info)
 604 #endif
 605
 606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 607 {
 608 #ifdef SANITY_CHECK
 609         if (!info) {
 610                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 611                 return 1;
 612         }
 613         if (info->magic != MGSL_MAGIC) {
 614                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 615                 return 1;
 616         }
 617 #else
 618         if (!info)
 619                 return 1;
 620 #endif
 621         return 0;
 622 }
 623
 624 /**
 625  * line discipline callback wrappers
 626  *
 627  * The wrappers maintain line discipline references
 628  * while calling into the line discipline.
 629  *
 630  * ldisc_receive_buf  - pass receive data to line discipline
 631  */
 632 static void ldisc_receive_buf(struct tty_struct *tty,
 633                               const __u8 *data, char *flags, int count)
 634 {
 635         struct tty_ldisc *ld;
 636         if (!tty)
 637                 return;
 638         ld = tty_ldisc_ref(tty);
 639         if (ld) {
 640                 if (ld->ops->receive_buf)
 641                         ld->ops->receive_buf(tty, data, flags, count);
 642                 tty_ldisc_deref(ld);
 643         }
 644 }
 645
 646 /* tty callbacks */
 647
 648 static int open(struct tty_struct *tty, struct file *filp)
 649 {
 650         struct slgt_info *info;
 651         int retval, line;
 652         unsigned long flags;
 653
 654         line = tty->index;
 655         if (line >= slgt_device_count) {
 656                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 657                 return -ENODEV;
 658         }
 659
 660         info = slgt_device_list;
 661         while(info && info->line != line)
 662                 info = info->next_device;
 663         if (sanity_check(info, tty->name, "open"))
 664                 return -ENODEV;
 665         if (info->init_error) {
 666                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 667                 return -ENODEV;
 668         }
 669
 670         tty->driver_data = info;
 671         info->port.tty = tty;
 672
 673         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 674
 675         mutex_lock(&info->port.mutex);
 676         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 677
 678         spin_lock_irqsave(&info->netlock, flags);
 679         if (info->netcount) {
 680                 retval = -EBUSY;
 681                 spin_unlock_irqrestore(&info->netlock, flags);
 682                 mutex_unlock(&info->port.mutex);
 683                 goto cleanup;
 684         }
 685         info->port.count++;
 686         spin_unlock_irqrestore(&info->netlock, flags);
 687
 688         if (info->port.count == 1) {
 689                 /* 1st open on this device, init hardware */
 690                 retval = startup(info);
 691                 if (retval < 0) {
 692                         mutex_unlock(&info->port.mutex);
 693                         goto cleanup;
 694                 }
 695         }
 696         mutex_unlock(&info->port.mutex);
 697         retval = block_til_ready(tty, filp, info);
 698         if (retval) {
 699                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 700                 goto cleanup;
 701         }
 702
 703         retval = 0;
 704
 705 cleanup:
 706         if (retval) {
 707                 if (tty->count == 1)
 708                         info->port.tty = NULL; /* tty layer will release tty struct */
 709                 if(info->port.count)
 710                         info->port.count--;
 711         }
 712
 713         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 714         return retval;
 715 }
 716
 717 static void close(struct tty_struct *tty, struct file *filp)
 718 {
 719         struct slgt_info *info = tty->driver_data;
 720
 721         if (sanity_check(info, tty->name, "close"))
 722                 return;
 723         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 724
 725         if (tty_port_close_start(&info->port, tty, filp) == 0)
 726                 goto cleanup;
 727
 728         mutex_lock(&info->port.mutex);
 729         if (tty_port_initialized(&info->port))
 730                 wait_until_sent(tty, info->timeout);
 731         flush_buffer(tty);
 732         tty_ldisc_flush(tty);
 733
 734         shutdown(info);
 735         mutex_unlock(&info->port.mutex);
 736
 737         tty_port_close_end(&info->port, tty);
 738         info->port.tty = NULL;
 739 cleanup:
 740         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 741 }
 742
 743 static void hangup(struct tty_struct *tty)
 744 {
 745         struct slgt_info *info = tty->driver_data;
 746         unsigned long flags;
 747
 748         if (sanity_check(info, tty->name, "hangup"))
 749                 return;
 750         DBGINFO(("%s hangup\n", info->device_name));
 751
 752         flush_buffer(tty);
 753
 754         mutex_lock(&info->port.mutex);
 755         shutdown(info);
 756
 757         spin_lock_irqsave(&info->port.lock, flags);
 758         info->port.count = 0;
 759         info->port.tty = NULL;
 760         spin_unlock_irqrestore(&info->port.lock, flags);
 761         tty_port_set_active(&info->port, 0);
 762         mutex_unlock(&info->port.mutex);
 763
 764         wake_up_interruptible(&info->port.open_wait);
 765 }
 766
 767 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 768 {
 769         struct slgt_info *info = tty->driver_data;
 770         unsigned long flags;
 771
 772         DBGINFO(("%s set_termios\n", tty->driver->name));
 773
 774         change_params(info);
 775
 776         /* Handle transition to B0 status */
 777         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 778                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 779                 spin_lock_irqsave(&info->lock,flags);
 780                 set_signals(info);
 781                 spin_unlock_irqrestore(&info->lock,flags);
 782         }
 783
 784         /* Handle transition away from B0 status */
 785         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 786                 info->signals |= SerialSignal_DTR;
 787                 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 788                         info->signals |= SerialSignal_RTS;
 789                 spin_lock_irqsave(&info->lock,flags);
 790                 set_signals(info);
 791                 spin_unlock_irqrestore(&info->lock,flags);
 792         }
 793
 794         /* Handle turning off CRTSCTS */
 795         if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
 796                 tty->hw_stopped = 0;
 797                 tx_release(tty);
 798         }
 799 }
 800
 801 static void update_tx_timer(struct slgt_info *info)
 802 {
 803         /*
 804          * use worst case speed of 1200bps to calculate transmit timeout
 805          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 806          */
 807         if (info->params.mode == MGSL_MODE_HDLC) {
 808                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 809                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 810         }
 811 }
 812
 813 static int write(struct tty_struct *tty,
 814                  const unsigned char *buf, int count)
 815 {
 816         int ret = 0;
 817         struct slgt_info *info = tty->driver_data;
 818         unsigned long flags;
 819
 820         if (sanity_check(info, tty->name, "write"))
 821                 return -EIO;
 822
 823         DBGINFO(("%s write count=%d\n", info->device_name, count));
 824
 825         if (!info->tx_buf || (count > info->max_frame_size))
 826                 return -EIO;
 827
 828         if (!count || tty->stopped || tty->hw_stopped)
 829                 return 0;
 830
 831         spin_lock_irqsave(&info->lock, flags);
 832
 833         if (info->tx_count) {
 834                 /* send accumulated data from send_char() */
 835                 if (!tx_load(info, info->tx_buf, info->tx_count))
 836                         goto cleanup;
 837                 info->tx_count = 0;
 838         }
 839
 840         if (tx_load(info, buf, count))
 841                 ret = count;
 842
 843 cleanup:
 844         spin_unlock_irqrestore(&info->lock, flags);
 845         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 846         return ret;
 847 }
 848
 849 static int put_char(struct tty_struct *tty, unsigned char ch)
 850 {
 851         struct slgt_info *info = tty->driver_data;
 852         unsigned long flags;
 853         int ret = 0;
 854
 855         if (sanity_check(info, tty->name, "put_char"))
 856                 return 0;
 857         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 858         if (!info->tx_buf)
 859                 return 0;
 860         spin_lock_irqsave(&info->lock,flags);
 861         if (info->tx_count < info->max_frame_size) {
 862                 info->tx_buf[info->tx_count++] = ch;
 863                 ret = 1;
 864         }
 865         spin_unlock_irqrestore(&info->lock,flags);
 866         return ret;
 867 }
 868
 869 static void send_xchar(struct tty_struct *tty, char ch)
 870 {
 871         struct slgt_info *info = tty->driver_data;
 872         unsigned long flags;
 873
 874         if (sanity_check(info, tty->name, "send_xchar"))
 875                 return;
 876         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 877         info->x_char = ch;
 878         if (ch) {
 879                 spin_lock_irqsave(&info->lock,flags);
 880                 if (!info->tx_enabled)
 881                         tx_start(info);
 882                 spin_unlock_irqrestore(&info->lock,flags);
 883         }
 884 }
 885
 886 static void wait_until_sent(struct tty_struct *tty, int timeout)
 887 {
 888         struct slgt_info *info = tty->driver_data;
 889         unsigned long orig_jiffies, char_time;
 890
 891         if (!info )
 892                 return;
 893         if (sanity_check(info, tty->name, "wait_until_sent"))
 894                 return;
 895         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 896         if (!tty_port_initialized(&info->port))
 897                 goto exit;
 898
 899         orig_jiffies = jiffies;
 900
 901         /* Set check interval to 1/5 of estimated time to
 902          * send a character, and make it at least 1. The check
 903          * interval should also be less than the timeout.
 904          * Note: use tight timings here to satisfy the NIST-PCTS.
 905          */
 906
 907         if (info->params.data_rate) {
 908                 char_time = info->timeout/(32 * 5);
 909                 if (!char_time)
 910                         char_time++;
 911         } else
 912                 char_time = 1;
 913
 914         if (timeout)
 915                 char_time = min_t(unsigned long, char_time, timeout);
 916
 917         while (info->tx_active) {
 918                 msleep_interruptible(jiffies_to_msecs(char_time));
 919                 if (signal_pending(current))
 920                         break;
 921                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 922                         break;
 923         }
 924 exit:
 925         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 926 }
 927
 928 static int write_room(struct tty_struct *tty)
 929 {
 930         struct slgt_info *info = tty->driver_data;
 931         int ret;
 932
 933         if (sanity_check(info, tty->name, "write_room"))
 934                 return 0;
 935         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 936         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 937         return ret;
 938 }
 939
 940 static void flush_chars(struct tty_struct *tty)
 941 {
 942         struct slgt_info *info = tty->driver_data;
 943         unsigned long flags;
 944
 945         if (sanity_check(info, tty->name, "flush_chars"))
 946                 return;
 947         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 948
 949         if (info->tx_count <= 0 || tty->stopped ||
 950             tty->hw_stopped || !info->tx_buf)
 951                 return;
 952
 953         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 954
 955         spin_lock_irqsave(&info->lock,flags);
 956         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 957                 info->tx_count = 0;
 958         spin_unlock_irqrestore(&info->lock,flags);
 959 }
 960
 961 static void flush_buffer(struct tty_struct *tty)
 962 {
 963         struct slgt_info *info = tty->driver_data;
 964         unsigned long flags;
 965
 966         if (sanity_check(info, tty->name, "flush_buffer"))
 967                 return;
 968         DBGINFO(("%s flush_buffer\n", info->device_name));
 969
 970         spin_lock_irqsave(&info->lock, flags);
 971         info->tx_count = 0;
 972         spin_unlock_irqrestore(&info->lock, flags);
 973
 974         tty_wakeup(tty);
 975 }
 976
 977 /*
 978  * throttle (stop) transmitter
 979  */
 980 static void tx_hold(struct tty_struct *tty)
 981 {
 982         struct slgt_info *info = tty->driver_data;
 983         unsigned long flags;
 984
 985         if (sanity_check(info, tty->name, "tx_hold"))
 986                 return;
 987         DBGINFO(("%s tx_hold\n", info->device_name));
 988         spin_lock_irqsave(&info->lock,flags);
 989         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 990                 tx_stop(info);
 991         spin_unlock_irqrestore(&info->lock,flags);
 992 }
 993
 994 /*
 995  * release (start) transmitter
 996  */
 997 static void tx_release(struct tty_struct *tty)
 998 {
 999         struct slgt_info *info = tty->driver_data;
1000         unsigned long flags;
1001
1002         if (sanity_check(info, tty->name, "tx_release"))
1003                 return;
1004         DBGINFO(("%s tx_release\n", info->device_name));
1005         spin_lock_irqsave(&info->lock, flags);
1006         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1007                 info->tx_count = 0;
1008         spin_unlock_irqrestore(&info->lock, flags);
1009 }
1010
1011 /*
1012  * Service an IOCTL request
1013  *
1014  * Arguments
1015  *
1016  *      tty     pointer to tty instance data
1017  *      cmd     IOCTL command code
1018  *      arg     command argument/context
1019  *
1020  * Return 0 if success, otherwise error code
1021  */
1022 static int ioctl(struct tty_struct *tty,
1023                  unsigned int cmd, unsigned long arg)
1024 {
1025         struct slgt_info *info = tty->driver_data;
1026         void __user *argp = (void __user *)arg;
1027         int ret;
1028
1029         if (sanity_check(info, tty->name, "ioctl"))
1030                 return -ENODEV;
1031         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1032
1033         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1034             (cmd != TIOCMIWAIT)) {
1035                 if (tty_io_error(tty))
1036                     return -EIO;
1037         }
1038
1039         switch (cmd) {
1040         case MGSL_IOCWAITEVENT:
1041                 return wait_mgsl_event(info, argp);
1042         case TIOCMIWAIT:
1043                 return modem_input_wait(info,(int)arg);
1044         case MGSL_IOCSGPIO:
1045                 return set_gpio(info, argp);
1046         case MGSL_IOCGGPIO:
1047                 return get_gpio(info, argp);
1048         case MGSL_IOCWAITGPIO:
1049                 return wait_gpio(info, argp);
1050         case MGSL_IOCGXSYNC:
1051                 return get_xsync(info, argp);
1052         case MGSL_IOCSXSYNC:
1053                 return set_xsync(info, (int)arg);
1054         case MGSL_IOCGXCTRL:
1055                 return get_xctrl(info, argp);
1056         case MGSL_IOCSXCTRL:
1057                 return set_xctrl(info, (int)arg);
1058         }
1059         mutex_lock(&info->port.mutex);
1060         switch (cmd) {
1061         case MGSL_IOCGPARAMS:
1062                 ret = get_params(info, argp);
1063                 break;
1064         case MGSL_IOCSPARAMS:
1065                 ret = set_params(info, argp);
1066                 break;
1067         case MGSL_IOCGTXIDLE:
1068                 ret = get_txidle(info, argp);
1069                 break;
1070         case MGSL_IOCSTXIDLE:
1071                 ret = set_txidle(info, (int)arg);
1072                 break;
1073         case MGSL_IOCTXENABLE:
1074                 ret = tx_enable(info, (int)arg);
1075                 break;
1076         case MGSL_IOCRXENABLE:
1077                 ret = rx_enable(info, (int)arg);
1078                 break;
1079         case MGSL_IOCTXABORT:
1080                 ret = tx_abort(info);
1081                 break;
1082         case MGSL_IOCGSTATS:
1083                 ret = get_stats(info, argp);
1084                 break;
1085         case MGSL_IOCGIF:
1086                 ret = get_interface(info, argp);
1087                 break;
1088         case MGSL_IOCSIF:
1089                 ret = set_interface(info,(int)arg);
1090                 break;
1091         default:
1092                 ret = -ENOIOCTLCMD;
1093         }
1094         mutex_unlock(&info->port.mutex);
1095         return ret;
1096 }
1097
1098 static int get_icount(struct tty_struct *tty,
1099                                 struct serial_icounter_struct *icount)
1100
1101 {
1102         struct slgt_info *info = tty->driver_data;
1103         struct mgsl_icount cnow;        /* kernel counter temps */
1104         unsigned long flags;
1105
1106         spin_lock_irqsave(&info->lock,flags);
1107         cnow = info->icount;
1108         spin_unlock_irqrestore(&info->lock,flags);
1109
1110         icount->cts = cnow.cts;
1111         icount->dsr = cnow.dsr;
1112         icount->rng = cnow.rng;
1113         icount->dcd = cnow.dcd;
1114         icount->rx = cnow.rx;
1115         icount->tx = cnow.tx;
1116         icount->frame = cnow.frame;
1117         icount->overrun = cnow.overrun;
1118         icount->parity = cnow.parity;
1119         icount->brk = cnow.brk;
1120         icount->buf_overrun = cnow.buf_overrun;
1121
1122         return 0;
1123 }
1124
1125 /*
1126  * support for 32 bit ioctl calls on 64 bit systems
1127  */
1128 #ifdef CONFIG_COMPAT
1129 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1130 {
1131         struct MGSL_PARAMS32 tmp_params;
1132
1133         DBGINFO(("%s get_params32\n", info->device_name));
1134         memset(&tmp_params, 0, sizeof(tmp_params));
1135         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1136         tmp_params.loopback        = info->params.loopback;
1137         tmp_params.flags           = info->params.flags;
1138         tmp_params.encoding        = info->params.encoding;
1139         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1140         tmp_params.addr_filter     = info->params.addr_filter;
1141         tmp_params.crc_type        = info->params.crc_type;
1142         tmp_params.preamble_length = info->params.preamble_length;
1143         tmp_params.preamble        = info->params.preamble;
1144         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1145         tmp_params.data_bits       = info->params.data_bits;
1146         tmp_params.stop_bits       = info->params.stop_bits;
1147         tmp_params.parity          = info->params.parity;
1148         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1149                 return -EFAULT;
1150         return 0;
1151 }
1152
1153 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1154 {
1155         struct MGSL_PARAMS32 tmp_params;
1156
1157         DBGINFO(("%s set_params32\n", info->device_name));
1158         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1159                 return -EFAULT;
1160
1161         spin_lock(&info->lock);
1162         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1163                 info->base_clock = tmp_params.clock_speed;
1164         } else {
1165                 info->params.mode            = tmp_params.mode;
1166                 info->params.loopback        = tmp_params.loopback;
1167                 info->params.flags           = tmp_params.flags;
1168                 info->params.encoding        = tmp_params.encoding;
1169                 info->params.clock_speed     = tmp_params.clock_speed;
1170                 info->params.addr_filter     = tmp_params.addr_filter;
1171                 info->params.crc_type        = tmp_params.crc_type;
1172                 info->params.preamble_length = tmp_params.preamble_length;
1173                 info->params.preamble        = tmp_params.preamble;
1174                 info->params.data_rate       = tmp_params.data_rate;
1175                 info->params.data_bits       = tmp_params.data_bits;
1176                 info->params.stop_bits       = tmp_params.stop_bits;
1177                 info->params.parity          = tmp_params.parity;
1178         }
1179         spin_unlock(&info->lock);
1180
1181         program_hw(info);
1182
1183         return 0;
1184 }
1185
1186 static long slgt_compat_ioctl(struct tty_struct *tty,
1187                          unsigned int cmd, unsigned long arg)
1188 {
1189         struct slgt_info *info = tty->driver_data;
1190         int rc;
1191
1192         if (sanity_check(info, tty->name, "compat_ioctl"))
1193                 return -ENODEV;
1194         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1195
1196         switch (cmd) {
1197         case MGSL_IOCSPARAMS32:
1198                 rc = set_params32(info, compat_ptr(arg));
1199                 break;
1200
1201         case MGSL_IOCGPARAMS32:
1202                 rc = get_params32(info, compat_ptr(arg));
1203                 break;
1204
1205         case MGSL_IOCGPARAMS:
1206         case MGSL_IOCSPARAMS:
1207         case MGSL_IOCGTXIDLE:
1208         case MGSL_IOCGSTATS:
1209         case MGSL_IOCWAITEVENT:
1210         case MGSL_IOCGIF:
1211         case MGSL_IOCSGPIO:
1212         case MGSL_IOCGGPIO:
1213         case MGSL_IOCWAITGPIO:
1214         case MGSL_IOCGXSYNC:
1215         case MGSL_IOCGXCTRL:
1216                 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1217                 break;
1218         default:
1219                 rc = ioctl(tty, cmd, arg);
1220         }
1221         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1222         return rc;
1223 }
1224 #else
1225 #define slgt_compat_ioctl NULL
1226 #endif /* ifdef CONFIG_COMPAT */
1227
1228 /*
1229  * proc fs support
1230  */
1231 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1232 {
1233         char stat_buf[30];
1234         unsigned long flags;
1235
1236         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1237                       info->device_name, info->phys_reg_addr,
1238                       info->irq_level, info->max_frame_size);
1239
1240         /* output current serial signal states */
1241         spin_lock_irqsave(&info->lock,flags);
1242         get_signals(info);
1243         spin_unlock_irqrestore(&info->lock,flags);
1244
1245         stat_buf[0] = 0;
1246         stat_buf[1] = 0;
1247         if (info->signals & SerialSignal_RTS)
1248                 strcat(stat_buf, "|RTS");
1249         if (info->signals & SerialSignal_CTS)
1250                 strcat(stat_buf, "|CTS");
1251         if (info->signals & SerialSignal_DTR)
1252                 strcat(stat_buf, "|DTR");
1253         if (info->signals & SerialSignal_DSR)
1254                 strcat(stat_buf, "|DSR");
1255         if (info->signals & SerialSignal_DCD)
1256                 strcat(stat_buf, "|CD");
1257         if (info->signals & SerialSignal_RI)
1258                 strcat(stat_buf, "|RI");
1259
1260         if (info->params.mode != MGSL_MODE_ASYNC) {
1261                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1262                                info->icount.txok, info->icount.rxok);
1263                 if (info->icount.txunder)
1264                         seq_printf(m, " txunder:%d", info->icount.txunder);
1265                 if (info->icount.txabort)
1266                         seq_printf(m, " txabort:%d", info->icount.txabort);
1267                 if (info->icount.rxshort)
1268                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1269                 if (info->icount.rxlong)
1270                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1271                 if (info->icount.rxover)
1272                         seq_printf(m, " rxover:%d", info->icount.rxover);
1273                 if (info->icount.rxcrc)
1274                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1275         } else {
1276                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1277                                info->icount.tx, info->icount.rx);
1278                 if (info->icount.frame)
1279                         seq_printf(m, " fe:%d", info->icount.frame);
1280                 if (info->icount.parity)
1281                         seq_printf(m, " pe:%d", info->icount.parity);
1282                 if (info->icount.brk)
1283                         seq_printf(m, " brk:%d", info->icount.brk);
1284                 if (info->icount.overrun)
1285                         seq_printf(m, " oe:%d", info->icount.overrun);
1286         }
1287
1288         /* Append serial signal status to end */
1289         seq_printf(m, " %s\n", stat_buf+1);
1290
1291         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1292                        info->tx_active,info->bh_requested,info->bh_running,
1293                        info->pending_bh);
1294 }
1295
1296 /* Called to print information about devices
1297  */
1298 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1299 {
1300         struct slgt_info *info;
1301
1302         seq_puts(m, "synclink_gt driver\n");
1303
1304         info = slgt_device_list;
1305         while( info ) {
1306                 line_info(m, info);
1307                 info = info->next_device;
1308         }
1309         return 0;
1310 }
1311
1312 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1313 {
1314         return single_open(file, synclink_gt_proc_show, NULL);
1315 }
1316
1317 static const struct file_operations synclink_gt_proc_fops = {
1318         .owner          = THIS_MODULE,
1319         .open           = synclink_gt_proc_open,
1320         .read           = seq_read,
1321         .llseek         = seq_lseek,
1322         .release        = single_release,
1323 };
1324
1325 /*
1326  * return count of bytes in transmit buffer
1327  */
1328 static int chars_in_buffer(struct tty_struct *tty)
1329 {
1330         struct slgt_info *info = tty->driver_data;
1331         int count;
1332         if (sanity_check(info, tty->name, "chars_in_buffer"))
1333                 return 0;
1334         count = tbuf_bytes(info);
1335         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1336         return count;
1337 }
1338
1339 /*
1340  * signal remote device to throttle send data (our receive data)
1341  */
1342 static void throttle(struct tty_struct * tty)
1343 {
1344         struct slgt_info *info = tty->driver_data;
1345         unsigned long flags;
1346
1347         if (sanity_check(info, tty->name, "throttle"))
1348                 return;
1349         DBGINFO(("%s throttle\n", info->device_name));
1350         if (I_IXOFF(tty))
1351                 send_xchar(tty, STOP_CHAR(tty));
1352         if (C_CRTSCTS(tty)) {
1353                 spin_lock_irqsave(&info->lock,flags);
1354                 info->signals &= ~SerialSignal_RTS;
1355                 set_signals(info);
1356                 spin_unlock_irqrestore(&info->lock,flags);
1357         }
1358 }
1359
1360 /*
1361  * signal remote device to stop throttling send data (our receive data)
1362  */
1363 static void unthrottle(struct tty_struct * tty)
1364 {
1365         struct slgt_info *info = tty->driver_data;
1366         unsigned long flags;
1367
1368         if (sanity_check(info, tty->name, "unthrottle"))
1369                 return;
1370         DBGINFO(("%s unthrottle\n", info->device_name));
1371         if (I_IXOFF(tty)) {
1372                 if (info->x_char)
1373                         info->x_char = 0;
1374                 else
1375                         send_xchar(tty, START_CHAR(tty));
1376         }
1377         if (C_CRTSCTS(tty)) {
1378                 spin_lock_irqsave(&info->lock,flags);
1379                 info->signals |= SerialSignal_RTS;
1380                 set_signals(info);
1381                 spin_unlock_irqrestore(&info->lock,flags);
1382         }
1383 }
1384
1385 /*
1386  * set or clear transmit break condition
1387  * break_state  -1=set break condition, 0=clear
1388  */
1389 static int set_break(struct tty_struct *tty, int break_state)
1390 {
1391         struct slgt_info *info = tty->driver_data;
1392         unsigned short value;
1393         unsigned long flags;
1394
1395         if (sanity_check(info, tty->name, "set_break"))
1396                 return -EINVAL;
1397         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1398
1399         spin_lock_irqsave(&info->lock,flags);
1400         value = rd_reg16(info, TCR);
1401         if (break_state == -1)
1402                 value |= BIT6;
1403         else
1404                 value &= ~BIT6;
1405         wr_reg16(info, TCR, value);
1406         spin_unlock_irqrestore(&info->lock,flags);
1407         return 0;
1408 }
1409
1410 #if SYNCLINK_GENERIC_HDLC
1411
1412 /**
1413  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1414  * set encoding and frame check sequence (FCS) options
1415  *
1416  * dev       pointer to network device structure
1417  * encoding  serial encoding setting
1418  * parity    FCS setting
1419  *
1420  * returns 0 if success, otherwise error code
1421  */
1422 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1423                           unsigned short parity)
1424 {
1425         struct slgt_info *info = dev_to_port(dev);
1426         unsigned char  new_encoding;
1427         unsigned short new_crctype;
1428
1429         /* return error if TTY interface open */
1430         if (info->port.count)
1431                 return -EBUSY;
1432
1433         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1434
1435         switch (encoding)
1436         {
1437         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1438         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1439         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1440         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1441         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1442         default: return -EINVAL;
1443         }
1444
1445         switch (parity)
1446         {
1447         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1448         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1449         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1450         default: return -EINVAL;
1451         }
1452
1453         info->params.encoding = new_encoding;
1454         info->params.crc_type = new_crctype;
1455
1456         /* if network interface up, reprogram hardware */
1457         if (info->netcount)
1458                 program_hw(info);
1459
1460         return 0;
1461 }
1462
1463 /**
1464  * called by generic HDLC layer to send frame
1465  *
1466  * skb  socket buffer containing HDLC frame
1467  * dev  pointer to network device structure
1468  */
1469 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1470                                       struct net_device *dev)
1471 {
1472         struct slgt_info *info = dev_to_port(dev);
1473         unsigned long flags;
1474
1475         DBGINFO(("%s hdlc_xmit\n", dev->name));
1476
1477         if (!skb->len)
1478                 return NETDEV_TX_OK;
1479
1480         /* stop sending until this frame completes */
1481         netif_stop_queue(dev);
1482
1483         /* update network statistics */
1484         dev->stats.tx_packets++;
1485         dev->stats.tx_bytes += skb->len;
1486
1487         /* save start time for transmit timeout detection */
1488         netif_trans_update(dev);
1489
1490         spin_lock_irqsave(&info->lock, flags);
1491         tx_load(info, skb->data, skb->len);
1492         spin_unlock_irqrestore(&info->lock, flags);
1493
1494         /* done with socket buffer, so free it */
1495         dev_kfree_skb(skb);
1496
1497         return NETDEV_TX_OK;
1498 }
1499
1500 /**
1501  * called by network layer when interface enabled
1502  * claim resources and initialize hardware
1503  *
1504  * dev  pointer to network device structure
1505  *
1506  * returns 0 if success, otherwise error code
1507  */
1508 static int hdlcdev_open(struct net_device *dev)
1509 {
1510         struct slgt_info *info = dev_to_port(dev);
1511         int rc;
1512         unsigned long flags;
1513
1514         if (!try_module_get(THIS_MODULE))
1515                 return -EBUSY;
1516
1517         DBGINFO(("%s hdlcdev_open\n", dev->name));
1518
1519         /* generic HDLC layer open processing */
1520         rc = hdlc_open(dev);
1521         if (rc)
1522                 return rc;
1523
1524         /* arbitrate between network and tty opens */
1525         spin_lock_irqsave(&info->netlock, flags);
1526         if (info->port.count != 0 || info->netcount != 0) {
1527                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1528                 spin_unlock_irqrestore(&info->netlock, flags);
1529                 return -EBUSY;
1530         }
1531         info->netcount=1;
1532         spin_unlock_irqrestore(&info->netlock, flags);
1533
1534         /* claim resources and init adapter */
1535         if ((rc = startup(info)) != 0) {
1536                 spin_lock_irqsave(&info->netlock, flags);
1537                 info->netcount=0;
1538                 spin_unlock_irqrestore(&info->netlock, flags);
1539                 return rc;
1540         }
1541
1542         /* assert RTS and DTR, apply hardware settings */
1543         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1544         program_hw(info);
1545
1546         /* enable network layer transmit */
1547         netif_trans_update(dev);
1548         netif_start_queue(dev);
1549
1550         /* inform generic HDLC layer of current DCD status */
1551         spin_lock_irqsave(&info->lock, flags);
1552         get_signals(info);
1553         spin_unlock_irqrestore(&info->lock, flags);
1554         if (info->signals & SerialSignal_DCD)
1555                 netif_carrier_on(dev);
1556         else
1557                 netif_carrier_off(dev);
1558         return 0;
1559 }
1560
1561 /**
1562  * called by network layer when interface is disabled
1563  * shutdown hardware and release resources
1564  *
1565  * dev  pointer to network device structure
1566  *
1567  * returns 0 if success, otherwise error code
1568  */
1569 static int hdlcdev_close(struct net_device *dev)
1570 {
1571         struct slgt_info *info = dev_to_port(dev);
1572         unsigned long flags;
1573
1574         DBGINFO(("%s hdlcdev_close\n", dev->name));
1575
1576         netif_stop_queue(dev);
1577
1578         /* shutdown adapter and release resources */
1579         shutdown(info);
1580
1581         hdlc_close(dev);
1582
1583         spin_lock_irqsave(&info->netlock, flags);
1584         info->netcount=0;
1585         spin_unlock_irqrestore(&info->netlock, flags);
1586
1587         module_put(THIS_MODULE);
1588         return 0;
1589 }
1590
1591 /**
1592  * called by network layer to process IOCTL call to network device
1593  *
1594  * dev  pointer to network device structure
1595  * ifr  pointer to network interface request structure
1596  * cmd  IOCTL command code
1597  *
1598  * returns 0 if success, otherwise error code
1599  */
1600 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1601 {
1602         const size_t size = sizeof(sync_serial_settings);
1603         sync_serial_settings new_line;
1604         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1605         struct slgt_info *info = dev_to_port(dev);
1606         unsigned int flags;
1607
1608         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1609
1610         /* return error if TTY interface open */
1611         if (info->port.count)
1612                 return -EBUSY;
1613
1614         if (cmd != SIOCWANDEV)
1615                 return hdlc_ioctl(dev, ifr, cmd);
1616
1617         memset(&new_line, 0, sizeof(new_line));
1618
1619         switch(ifr->ifr_settings.type) {
1620         case IF_GET_IFACE: /* return current sync_serial_settings */
1621
1622                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1623                 if (ifr->ifr_settings.size < size) {
1624                         ifr->ifr_settings.size = size; /* data size wanted */
1625                         return -ENOBUFS;
1626                 }
1627
1628                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1629                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1630                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1631                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1632
1633                 switch (flags){
1634                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1635                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1636                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1637                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1638                 default: new_line.clock_type = CLOCK_DEFAULT;
1639                 }
1640
1641                 new_line.clock_rate = info->params.clock_speed;
1642                 new_line.loopback   = info->params.loopback ? 1:0;
1643
1644                 if (copy_to_user(line, &new_line, size))
1645                         return -EFAULT;
1646                 return 0;
1647
1648         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1649
1650                 if(!capable(CAP_NET_ADMIN))
1651                         return -EPERM;
1652                 if (copy_from_user(&new_line, line, size))
1653                         return -EFAULT;
1654
1655                 switch (new_line.clock_type)
1656                 {
1657                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1658                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1659                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1660                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1661                 case CLOCK_DEFAULT:  flags = info->params.flags &
1662                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1663                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1664                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1665                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1666                 default: return -EINVAL;
1667                 }
1668
1669                 if (new_line.loopback != 0 && new_line.loopback != 1)
1670                         return -EINVAL;
1671
1672                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1673                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1674                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1675                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1676                 info->params.flags |= flags;
1677
1678                 info->params.loopback = new_line.loopback;
1679
1680                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1681                         info->params.clock_speed = new_line.clock_rate;
1682                 else
1683                         info->params.clock_speed = 0;
1684
1685                 /* if network interface up, reprogram hardware */
1686                 if (info->netcount)
1687                         program_hw(info);
1688                 return 0;
1689
1690         default:
1691                 return hdlc_ioctl(dev, ifr, cmd);
1692         }
1693 }
1694
1695 /**
1696  * called by network layer when transmit timeout is detected
1697  *
1698  * dev  pointer to network device structure
1699  */
1700 static void hdlcdev_tx_timeout(struct net_device *dev)
1701 {
1702         struct slgt_info *info = dev_to_port(dev);
1703         unsigned long flags;
1704
1705         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1706
1707         dev->stats.tx_errors++;
1708         dev->stats.tx_aborted_errors++;
1709
1710         spin_lock_irqsave(&info->lock,flags);
1711         tx_stop(info);
1712         spin_unlock_irqrestore(&info->lock,flags);
1713
1714         netif_wake_queue(dev);
1715 }
1716
1717 /**
1718  * called by device driver when transmit completes
1719  * reenable network layer transmit if stopped
1720  *
1721  * info  pointer to device instance information
1722  */
1723 static void hdlcdev_tx_done(struct slgt_info *info)
1724 {
1725         if (netif_queue_stopped(info->netdev))
1726                 netif_wake_queue(info->netdev);
1727 }
1728
1729 /**
1730  * called by device driver when frame received
1731  * pass frame to network layer
1732  *
1733  * info  pointer to device instance information
1734  * buf   pointer to buffer contianing frame data
1735  * size  count of data bytes in buf
1736  */
1737 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1738 {
1739         struct sk_buff *skb = dev_alloc_skb(size);
1740         struct net_device *dev = info->netdev;
1741
1742         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1743
1744         if (skb == NULL) {
1745                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1746                 dev->stats.rx_dropped++;
1747                 return;
1748         }
1749
1750         memcpy(skb_put(skb, size), buf, size);
1751
1752         skb->protocol = hdlc_type_trans(skb, dev);
1753
1754         dev->stats.rx_packets++;
1755         dev->stats.rx_bytes += size;
1756
1757         netif_rx(skb);
1758 }
1759
1760 static const struct net_device_ops hdlcdev_ops = {
1761         .ndo_open       = hdlcdev_open,
1762         .ndo_stop       = hdlcdev_close,
1763         .ndo_change_mtu = hdlc_change_mtu,
1764         .ndo_start_xmit = hdlc_start_xmit,
1765         .ndo_do_ioctl   = hdlcdev_ioctl,
1766         .ndo_tx_timeout = hdlcdev_tx_timeout,
1767 };
1768
1769 /**
1770  * called by device driver when adding device instance
1771  * do generic HDLC initialization
1772  *
1773  * info  pointer to device instance information
1774  *
1775  * returns 0 if success, otherwise error code
1776  */
1777 static int hdlcdev_init(struct slgt_info *info)
1778 {
1779         int rc;
1780         struct net_device *dev;
1781         hdlc_device *hdlc;
1782
1783         /* allocate and initialize network and HDLC layer objects */
1784
1785         dev = alloc_hdlcdev(info);
1786         if (!dev) {
1787                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1788                 return -ENOMEM;
1789         }
1790
1791         /* for network layer reporting purposes only */
1792         dev->mem_start = info->phys_reg_addr;
1793         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1794         dev->irq       = info->irq_level;
1795
1796         /* network layer callbacks and settings */
1797         dev->netdev_ops     = &hdlcdev_ops;
1798         dev->watchdog_timeo = 10 * HZ;
1799         dev->tx_queue_len   = 50;
1800
1801         /* generic HDLC layer callbacks and settings */
1802         hdlc         = dev_to_hdlc(dev);
1803         hdlc->attach = hdlcdev_attach;
1804         hdlc->xmit   = hdlcdev_xmit;
1805
1806         /* register objects with HDLC layer */
1807         rc = register_hdlc_device(dev);
1808         if (rc) {
1809                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1810                 free_netdev(dev);
1811                 return rc;
1812         }
1813
1814         info->netdev = dev;
1815         return 0;
1816 }
1817
1818 /**
1819  * called by device driver when removing device instance
1820  * do generic HDLC cleanup
1821  *
1822  * info  pointer to device instance information
1823  */
1824 static void hdlcdev_exit(struct slgt_info *info)
1825 {
1826         unregister_hdlc_device(info->netdev);
1827         free_netdev(info->netdev);
1828         info->netdev = NULL;
1829 }
1830
1831 #endif /* ifdef CONFIG_HDLC */
1832
1833 /*
1834  * get async data from rx DMA buffers
1835  */
1836 static void rx_async(struct slgt_info *info)
1837 {
1838         struct mgsl_icount *icount = &info->icount;
1839         unsigned int start, end;
1840         unsigned char *p;
1841         unsigned char status;
1842         struct slgt_desc *bufs = info->rbufs;
1843         int i, count;
1844         int chars = 0;
1845         int stat;
1846         unsigned char ch;
1847
1848         start = end = info->rbuf_current;
1849
1850         while(desc_complete(bufs[end])) {
1851                 count = desc_count(bufs[end]) - info->rbuf_index;
1852                 p     = bufs[end].buf + info->rbuf_index;
1853
1854                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1855                 DBGDATA(info, p, count, "rx");
1856
1857                 for(i=0 ; i < count; i+=2, p+=2) {
1858                         ch = *p;
1859                         icount->rx++;
1860
1861                         stat = 0;
1862
1863                         status = *(p + 1) & (BIT1 + BIT0);
1864                         if (status) {
1865                                 if (status & BIT1)
1866                                         icount->parity++;
1867                                 else if (status & BIT0)
1868                                         icount->frame++;
1869                                 /* discard char if tty control flags say so */
1870                                 if (status & info->ignore_status_mask)
1871                                         continue;
1872                                 if (status & BIT1)
1873                                         stat = TTY_PARITY;
1874                                 else if (status & BIT0)
1875                                         stat = TTY_FRAME;
1876                         }
1877                         tty_insert_flip_char(&info->port, ch, stat);
1878                         chars++;
1879                 }
1880
1881                 if (i < count) {
1882                         /* receive buffer not completed */
1883                         info->rbuf_index += i;
1884                         mod_timer(&info->rx_timer, jiffies + 1);
1885                         break;
1886                 }
1887
1888                 info->rbuf_index = 0;
1889                 free_rbufs(info, end, end);
1890
1891                 if (++end == info->rbuf_count)
1892                         end = 0;
1893
1894                 /* if entire list searched then no frame available */
1895                 if (end == start)
1896                         break;
1897         }
1898
1899         if (chars)
1900                 tty_flip_buffer_push(&info->port);
1901 }
1902
1903 /*
1904  * return next bottom half action to perform
1905  */
1906 static int bh_action(struct slgt_info *info)
1907 {
1908         unsigned long flags;
1909         int rc;
1910
1911         spin_lock_irqsave(&info->lock,flags);
1912
1913         if (info->pending_bh & BH_RECEIVE) {
1914                 info->pending_bh &= ~BH_RECEIVE;
1915                 rc = BH_RECEIVE;
1916         } else if (info->pending_bh & BH_TRANSMIT) {
1917                 info->pending_bh &= ~BH_TRANSMIT;
1918                 rc = BH_TRANSMIT;
1919         } else if (info->pending_bh & BH_STATUS) {
1920                 info->pending_bh &= ~BH_STATUS;
1921                 rc = BH_STATUS;
1922         } else {
1923                 /* Mark BH routine as complete */
1924                 info->bh_running = false;
1925                 info->bh_requested = false;
1926                 rc = 0;
1927         }
1928
1929         spin_unlock_irqrestore(&info->lock,flags);
1930
1931         return rc;
1932 }
1933
1934 /*
1935  * perform bottom half processing
1936  */
1937 static void bh_handler(struct work_struct *work)
1938 {
1939         struct slgt_info *info = container_of(work, struct slgt_info, task);
1940         int action;
1941
1942         info->bh_running = true;
1943
1944         while((action = bh_action(info))) {
1945                 switch (action) {
1946                 case BH_RECEIVE:
1947                         DBGBH(("%s bh receive\n", info->device_name));
1948                         switch(info->params.mode) {
1949                         case MGSL_MODE_ASYNC:
1950                                 rx_async(info);
1951                                 break;
1952                         case MGSL_MODE_HDLC:
1953                                 while(rx_get_frame(info));
1954                                 break;
1955                         case MGSL_MODE_RAW:
1956                         case MGSL_MODE_MONOSYNC:
1957                         case MGSL_MODE_BISYNC:
1958                         case MGSL_MODE_XSYNC:
1959                                 while(rx_get_buf(info));
1960                                 break;
1961                         }
1962                         /* restart receiver if rx DMA buffers exhausted */
1963                         if (info->rx_restart)
1964                                 rx_start(info);
1965                         break;
1966                 case BH_TRANSMIT:
1967                         bh_transmit(info);
1968                         break;
1969                 case BH_STATUS:
1970                         DBGBH(("%s bh status\n", info->device_name));
1971                         info->ri_chkcount = 0;
1972                         info->dsr_chkcount = 0;
1973                         info->dcd_chkcount = 0;
1974                         info->cts_chkcount = 0;
1975                         break;
1976                 default:
1977                         DBGBH(("%s unknown action\n", info->device_name));
1978                         break;
1979                 }
1980         }
1981         DBGBH(("%s bh_handler exit\n", info->device_name));
1982 }
1983
1984 static void bh_transmit(struct slgt_info *info)
1985 {
1986         struct tty_struct *tty = info->port.tty;
1987
1988         DBGBH(("%s bh_transmit\n", info->device_name));
1989         if (tty)
1990                 tty_wakeup(tty);
1991 }
1992
1993 static void dsr_change(struct slgt_info *info, unsigned short status)
1994 {
1995         if (status & BIT3) {
1996                 info->signals |= SerialSignal_DSR;
1997                 info->input_signal_events.dsr_up++;
1998         } else {
1999                 info->signals &= ~SerialSignal_DSR;
2000                 info->input_signal_events.dsr_down++;
2001         }
2002         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2003         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2004                 slgt_irq_off(info, IRQ_DSR);
2005                 return;
2006         }
2007         info->icount.dsr++;
2008         wake_up_interruptible(&info->status_event_wait_q);
2009         wake_up_interruptible(&info->event_wait_q);
2010         info->pending_bh |= BH_STATUS;
2011 }
2012
2013 static void cts_change(struct slgt_info *info, unsigned short status)
2014 {
2015         if (status & BIT2) {
2016                 info->signals |= SerialSignal_CTS;
2017                 info->input_signal_events.cts_up++;
2018         } else {
2019                 info->signals &= ~SerialSignal_CTS;
2020                 info->input_signal_events.cts_down++;
2021         }
2022         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2023         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2024                 slgt_irq_off(info, IRQ_CTS);
2025                 return;
2026         }
2027         info->icount.cts++;
2028         wake_up_interruptible(&info->status_event_wait_q);
2029         wake_up_interruptible(&info->event_wait_q);
2030         info->pending_bh |= BH_STATUS;
2031
2032         if (tty_port_cts_enabled(&info->port)) {
2033                 if (info->port.tty) {
2034                         if (info->port.tty->hw_stopped) {
2035                                 if (info->signals & SerialSignal_CTS) {
2036                                         info->port.tty->hw_stopped = 0;
2037                                         info->pending_bh |= BH_TRANSMIT;
2038                                         return;
2039                                 }
2040                         } else {
2041                                 if (!(info->signals & SerialSignal_CTS))
2042                                         info->port.tty->hw_stopped = 1;
2043                         }
2044                 }
2045         }
2046 }
2047
2048 static void dcd_change(struct slgt_info *info, unsigned short status)
2049 {
2050         if (status & BIT1) {
2051                 info->signals |= SerialSignal_DCD;
2052                 info->input_signal_events.dcd_up++;
2053         } else {
2054                 info->signals &= ~SerialSignal_DCD;
2055                 info->input_signal_events.dcd_down++;
2056         }
2057         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2058         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2059                 slgt_irq_off(info, IRQ_DCD);
2060                 return;
2061         }
2062         info->icount.dcd++;
2063 #if SYNCLINK_GENERIC_HDLC
2064         if (info->netcount) {
2065                 if (info->signals & SerialSignal_DCD)
2066                         netif_carrier_on(info->netdev);
2067                 else
2068                         netif_carrier_off(info->netdev);
2069         }
2070 #endif
2071         wake_up_interruptible(&info->status_event_wait_q);
2072         wake_up_interruptible(&info->event_wait_q);
2073         info->pending_bh |= BH_STATUS;
2074
2075         if (tty_port_check_carrier(&info->port)) {
2076                 if (info->signals & SerialSignal_DCD)
2077                         wake_up_interruptible(&info->port.open_wait);
2078                 else {
2079                         if (info->port.tty)
2080                                 tty_hangup(info->port.tty);
2081                 }
2082         }
2083 }
2084
2085 static void ri_change(struct slgt_info *info, unsigned short status)
2086 {
2087         if (status & BIT0) {
2088                 info->signals |= SerialSignal_RI;
2089                 info->input_signal_events.ri_up++;
2090         } else {
2091                 info->signals &= ~SerialSignal_RI;
2092                 info->input_signal_events.ri_down++;
2093         }
2094         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2095         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2096                 slgt_irq_off(info, IRQ_RI);
2097                 return;
2098         }
2099         info->icount.rng++;
2100         wake_up_interruptible(&info->status_event_wait_q);
2101         wake_up_interruptible(&info->event_wait_q);
2102         info->pending_bh |= BH_STATUS;
2103 }
2104
2105 static void isr_rxdata(struct slgt_info *info)
2106 {
2107         unsigned int count = info->rbuf_fill_count;
2108         unsigned int i = info->rbuf_fill_index;
2109         unsigned short reg;
2110
2111         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2112                 reg = rd_reg16(info, RDR);
2113                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2114                 if (desc_complete(info->rbufs[i])) {
2115                         /* all buffers full */
2116                         rx_stop(info);
2117                         info->rx_restart = 1;
2118                         continue;
2119                 }
2120                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2121                 /* async mode saves status byte to buffer for each data byte */
2122                 if (info->params.mode == MGSL_MODE_ASYNC)
2123                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2124                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2125                         /* buffer full or end of frame */
2126                         set_desc_count(info->rbufs[i], count);
2127                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2128                         info->rbuf_fill_count = count = 0;
2129                         if (++i == info->rbuf_count)
2130                                 i = 0;
2131                         info->pending_bh |= BH_RECEIVE;
2132                 }
2133         }
2134
2135         info->rbuf_fill_index = i;
2136         info->rbuf_fill_count = count;
2137 }
2138
2139 static void isr_serial(struct slgt_info *info)
2140 {
2141         unsigned short status = rd_reg16(info, SSR);
2142
2143         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2144
2145         wr_reg16(info, SSR, status); /* clear pending */
2146
2147         info->irq_occurred = true;
2148
2149         if (info->params.mode == MGSL_MODE_ASYNC) {
2150                 if (status & IRQ_TXIDLE) {
2151                         if (info->tx_active)
2152                                 isr_txeom(info, status);
2153                 }
2154                 if (info->rx_pio && (status & IRQ_RXDATA))
2155                         isr_rxdata(info);
2156                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2157                         info->icount.brk++;
2158                         /* process break detection if tty control allows */
2159                         if (info->port.tty) {
2160                                 if (!(status & info->ignore_status_mask)) {
2161                                         if (info->read_status_mask & MASK_BREAK) {
2162                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2163                                                 if (info->port.flags & ASYNC_SAK)
2164                                                         do_SAK(info->port.tty);
2165                                         }
2166                                 }
2167                         }
2168                 }
2169         } else {
2170                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2171                         isr_txeom(info, status);
2172                 if (info->rx_pio && (status & IRQ_RXDATA))
2173                         isr_rxdata(info);
2174                 if (status & IRQ_RXIDLE) {
2175                         if (status & RXIDLE)
2176                                 info->icount.rxidle++;
2177                         else
2178                                 info->icount.exithunt++;
2179                         wake_up_interruptible(&info->event_wait_q);
2180                 }
2181
2182                 if (status & IRQ_RXOVER)
2183                         rx_start(info);
2184         }
2185
2186         if (status & IRQ_DSR)
2187                 dsr_change(info, status);
2188         if (status & IRQ_CTS)
2189                 cts_change(info, status);
2190         if (status & IRQ_DCD)
2191                 dcd_change(info, status);
2192         if (status & IRQ_RI)
2193                 ri_change(info, status);
2194 }
2195
2196 static void isr_rdma(struct slgt_info *info)
2197 {
2198         unsigned int status = rd_reg32(info, RDCSR);
2199
2200         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2201
2202         /* RDCSR (rx DMA control/status)
2203          *
2204          * 31..07  reserved
2205          * 06      save status byte to DMA buffer
2206          * 05      error
2207          * 04      eol (end of list)
2208          * 03      eob (end of buffer)
2209          * 02      IRQ enable
2210          * 01      reset
2211          * 00      enable
2212          */
2213         wr_reg32(info, RDCSR, status);  /* clear pending */
2214
2215         if (status & (BIT5 + BIT4)) {
2216                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2217                 info->rx_restart = true;
2218         }
2219         info->pending_bh |= BH_RECEIVE;
2220 }
2221
2222 static void isr_tdma(struct slgt_info *info)
2223 {
2224         unsigned int status = rd_reg32(info, TDCSR);
2225
2226         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2227
2228         /* TDCSR (tx DMA control/status)
2229          *
2230          * 31..06  reserved
2231          * 05      error
2232          * 04      eol (end of list)
2233          * 03      eob (end of buffer)
2234          * 02      IRQ enable
2235          * 01      reset
2236          * 00      enable
2237          */
2238         wr_reg32(info, TDCSR, status);  /* clear pending */
2239
2240         if (status & (BIT5 + BIT4 + BIT3)) {
2241                 // another transmit buffer has completed
2242                 // run bottom half to get more send data from user
2243                 info->pending_bh |= BH_TRANSMIT;
2244         }
2245 }
2246
2247 /*
2248  * return true if there are unsent tx DMA buffers, otherwise false
2249  *
2250  * if there are unsent buffers then info->tbuf_start
2251  * is set to index of first unsent buffer
2252  */
2253 static bool unsent_tbufs(struct slgt_info *info)
2254 {
2255         unsigned int i = info->tbuf_current;
2256         bool rc = false;
2257
2258         /*
2259          * search backwards from last loaded buffer (precedes tbuf_current)
2260          * for first unsent buffer (desc_count > 0)
2261          */
2262
2263         do {
2264                 if (i)
2265                         i--;
2266                 else
2267                         i = info->tbuf_count - 1;
2268                 if (!desc_count(info->tbufs[i]))
2269                         break;
2270                 info->tbuf_start = i;
2271                 rc = true;
2272         } while (i != info->tbuf_current);
2273
2274         return rc;
2275 }
2276
2277 static void isr_txeom(struct slgt_info *info, unsigned short status)
2278 {
2279         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2280
2281         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2282         tdma_reset(info);
2283         if (status & IRQ_TXUNDER) {
2284                 unsigned short val = rd_reg16(info, TCR);
2285                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2286                 wr_reg16(info, TCR, val); /* clear reset bit */
2287         }
2288
2289         if (info->tx_active) {
2290                 if (info->params.mode != MGSL_MODE_ASYNC) {
2291                         if (status & IRQ_TXUNDER)
2292                                 info->icount.txunder++;
2293                         else if (status & IRQ_TXIDLE)
2294                                 info->icount.txok++;
2295                 }
2296
2297                 if (unsent_tbufs(info)) {
2298                         tx_start(info);
2299                         update_tx_timer(info);
2300                         return;
2301                 }
2302                 info->tx_active = false;
2303
2304                 del_timer(&info->tx_timer);
2305
2306                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2307                         info->signals &= ~SerialSignal_RTS;
2308                         info->drop_rts_on_tx_done = false;
2309                         set_signals(info);
2310                 }
2311
2312 #if SYNCLINK_GENERIC_HDLC
2313                 if (info->netcount)
2314                         hdlcdev_tx_done(info);
2315                 else
2316 #endif
2317                 {
2318                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2319                                 tx_stop(info);
2320                                 return;
2321                         }
2322                         info->pending_bh |= BH_TRANSMIT;
2323                 }
2324         }
2325 }
2326
2327 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2328 {
2329         struct cond_wait *w, *prev;
2330
2331         /* wake processes waiting for specific transitions */
2332         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2333                 if (w->data & changed) {
2334                         w->data = state;
2335                         wake_up_interruptible(&w->q);
2336                         if (prev != NULL)
2337                                 prev->next = w->next;
2338                         else
2339                                 info->gpio_wait_q = w->next;
2340                 } else
2341                         prev = w;
2342         }
2343 }
2344
2345 /* interrupt service routine
2346  *
2347  *      irq     interrupt number
2348  *      dev_id  device ID supplied during interrupt registration
2349  */
2350 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2351 {
2352         struct slgt_info *info = dev_id;
2353         unsigned int gsr;
2354         unsigned int i;
2355
2356         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2357
2358         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2359                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2360                 info->irq_occurred = true;
2361                 for(i=0; i < info->port_count ; i++) {
2362                         if (info->port_array[i] == NULL)
2363                                 continue;
2364                         spin_lock(&info->port_array[i]->lock);
2365                         if (gsr & (BIT8 << i))
2366                                 isr_serial(info->port_array[i]);
2367                         if (gsr & (BIT16 << (i*2)))
2368                                 isr_rdma(info->port_array[i]);
2369                         if (gsr & (BIT17 << (i*2)))
2370                                 isr_tdma(info->port_array[i]);
2371                         spin_unlock(&info->port_array[i]->lock);
2372                 }
2373         }
2374
2375         if (info->gpio_present) {
2376                 unsigned int state;
2377                 unsigned int changed;
2378                 spin_lock(&info->lock);
2379                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2380                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2381                         /* read latched state of GPIO signals */
2382                         state = rd_reg32(info, IOVR);
2383                         /* clear pending GPIO interrupt bits */
2384                         wr_reg32(info, IOSR, changed);
2385                         for (i=0 ; i < info->port_count ; i++) {
2386                                 if (info->port_array[i] != NULL)
2387                                         isr_gpio(info->port_array[i], changed, state);
2388                         }
2389                 }
2390                 spin_unlock(&info->lock);
2391         }
2392
2393         for(i=0; i < info->port_count ; i++) {
2394                 struct slgt_info *port = info->port_array[i];
2395                 if (port == NULL)
2396                         continue;
2397                 spin_lock(&port->lock);
2398                 if ((port->port.count || port->netcount) &&
2399                     port->pending_bh && !port->bh_running &&
2400                     !port->bh_requested) {
2401                         DBGISR(("%s bh queued\n", port->device_name));
2402                         schedule_work(&port->task);
2403                         port->bh_requested = true;
2404                 }
2405                 spin_unlock(&port->lock);
2406         }
2407
2408         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2409         return IRQ_HANDLED;
2410 }
2411
2412 static int startup(struct slgt_info *info)
2413 {
2414         DBGINFO(("%s startup\n", info->device_name));
2415
2416         if (tty_port_initialized(&info->port))
2417                 return 0;
2418
2419         if (!info->tx_buf) {
2420                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2421                 if (!info->tx_buf) {
2422                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2423                         return -ENOMEM;
2424                 }
2425         }
2426
2427         info->pending_bh = 0;
2428
2429         memset(&info->icount, 0, sizeof(info->icount));
2430
2431         /* program hardware for current parameters */
2432         change_params(info);
2433
2434         if (info->port.tty)
2435                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2436
2437         tty_port_set_initialized(&info->port, 1);
2438
2439         return 0;
2440 }
2441
2442 /*
2443  *  called by close() and hangup() to shutdown hardware
2444  */
2445 static void shutdown(struct slgt_info *info)
2446 {
2447         unsigned long flags;
2448
2449         if (!tty_port_initialized(&info->port))
2450                 return;
2451
2452         DBGINFO(("%s shutdown\n", info->device_name));
2453
2454         /* clear status wait queue because status changes */
2455         /* can't happen after shutting down the hardware */
2456         wake_up_interruptible(&info->status_event_wait_q);
2457         wake_up_interruptible(&info->event_wait_q);
2458
2459         del_timer_sync(&info->tx_timer);
2460         del_timer_sync(&info->rx_timer);
2461
2462         kfree(info->tx_buf);
2463         info->tx_buf = NULL;
2464
2465         spin_lock_irqsave(&info->lock,flags);
2466
2467         tx_stop(info);
2468         rx_stop(info);
2469
2470         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2471
2472         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2473                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2474                 set_signals(info);
2475         }
2476
2477         flush_cond_wait(&info->gpio_wait_q);
2478
2479         spin_unlock_irqrestore(&info->lock,flags);
2480
2481         if (info->port.tty)
2482                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2483
2484         tty_port_set_initialized(&info->port, 0);
2485 }
2486
2487 static void program_hw(struct slgt_info *info)
2488 {
2489         unsigned long flags;
2490
2491         spin_lock_irqsave(&info->lock,flags);
2492
2493         rx_stop(info);
2494         tx_stop(info);
2495
2496         if (info->params.mode != MGSL_MODE_ASYNC ||
2497             info->netcount)
2498                 sync_mode(info);
2499         else
2500                 async_mode(info);
2501
2502         set_signals(info);
2503
2504         info->dcd_chkcount = 0;
2505         info->cts_chkcount = 0;
2506         info->ri_chkcount = 0;
2507         info->dsr_chkcount = 0;
2508
2509         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2510         get_signals(info);
2511
2512         if (info->netcount ||
2513             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2514                 rx_start(info);
2515
2516         spin_unlock_irqrestore(&info->lock,flags);
2517 }
2518
2519 /*
2520  * reconfigure adapter based on new parameters
2521  */
2522 static void change_params(struct slgt_info *info)
2523 {
2524         unsigned cflag;
2525         int bits_per_char;
2526
2527         if (!info->port.tty)
2528                 return;
2529         DBGINFO(("%s change_params\n", info->device_name));
2530
2531         cflag = info->port.tty->termios.c_cflag;
2532
2533         /* if B0 rate (hangup) specified then negate RTS and DTR */
2534         /* otherwise assert RTS and DTR */
2535         if (cflag & CBAUD)
2536                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2537         else
2538                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2539
2540         /* byte size and parity */
2541
2542         switch (cflag & CSIZE) {
2543         case CS5: info->params.data_bits = 5; break;
2544         case CS6: info->params.data_bits = 6; break;
2545         case CS7: info->params.data_bits = 7; break;
2546         case CS8: info->params.data_bits = 8; break;
2547         default:  info->params.data_bits = 7; break;
2548         }
2549
2550         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2551
2552         if (cflag & PARENB)
2553                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2554         else
2555                 info->params.parity = ASYNC_PARITY_NONE;
2556
2557         /* calculate number of jiffies to transmit a full
2558          * FIFO (32 bytes) at specified data rate
2559          */
2560         bits_per_char = info->params.data_bits +
2561                         info->params.stop_bits + 1;
2562
2563         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2564
2565         if (info->params.data_rate) {
2566                 info->timeout = (32*HZ*bits_per_char) /
2567                                 info->params.data_rate;
2568         }
2569         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2570
2571         tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2572         tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2573
2574         /* process tty input control flags */
2575
2576         info->read_status_mask = IRQ_RXOVER;
2577         if (I_INPCK(info->port.tty))
2578                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2579         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2580                 info->read_status_mask |= MASK_BREAK;
2581         if (I_IGNPAR(info->port.tty))
2582                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2583         if (I_IGNBRK(info->port.tty)) {
2584                 info->ignore_status_mask |= MASK_BREAK;
2585                 /* If ignoring parity and break indicators, ignore
2586                  * overruns too.  (For real raw support).
2587                  */
2588                 if (I_IGNPAR(info->port.tty))
2589                         info->ignore_status_mask |= MASK_OVERRUN;
2590         }
2591
2592         program_hw(info);
2593 }
2594
2595 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2596 {
2597         DBGINFO(("%s get_stats\n",  info->device_name));
2598         if (!user_icount) {
2599                 memset(&info->icount, 0, sizeof(info->icount));
2600         } else {
2601                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2602                         return -EFAULT;
2603         }
2604         return 0;
2605 }
2606
2607 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2608 {
2609         DBGINFO(("%s get_params\n", info->device_name));
2610         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2611                 return -EFAULT;
2612         return 0;
2613 }
2614
2615 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2616 {
2617         unsigned long flags;
2618         MGSL_PARAMS tmp_params;
2619
2620         DBGINFO(("%s set_params\n", info->device_name));
2621         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2622                 return -EFAULT;
2623
2624         spin_lock_irqsave(&info->lock, flags);
2625         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2626                 info->base_clock = tmp_params.clock_speed;
2627         else
2628                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2629         spin_unlock_irqrestore(&info->lock, flags);
2630
2631         program_hw(info);
2632
2633         return 0;
2634 }
2635
2636 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2637 {
2638         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2639         if (put_user(info->idle_mode, idle_mode))
2640                 return -EFAULT;
2641         return 0;
2642 }
2643
2644 static int set_txidle(struct slgt_info *info, int idle_mode)
2645 {
2646         unsigned long flags;
2647         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2648         spin_lock_irqsave(&info->lock,flags);
2649         info->idle_mode = idle_mode;
2650         if (info->params.mode != MGSL_MODE_ASYNC)
2651                 tx_set_idle(info);
2652         spin_unlock_irqrestore(&info->lock,flags);
2653         return 0;
2654 }
2655
2656 static int tx_enable(struct slgt_info *info, int enable)
2657 {
2658         unsigned long flags;
2659         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2660         spin_lock_irqsave(&info->lock,flags);
2661         if (enable) {
2662                 if (!info->tx_enabled)
2663                         tx_start(info);
2664         } else {
2665                 if (info->tx_enabled)
2666                         tx_stop(info);
2667         }
2668         spin_unlock_irqrestore(&info->lock,flags);
2669         return 0;
2670 }
2671
2672 /*
2673  * abort transmit HDLC frame
2674  */
2675 static int tx_abort(struct slgt_info *info)
2676 {
2677         unsigned long flags;
2678         DBGINFO(("%s tx_abort\n", info->device_name));
2679         spin_lock_irqsave(&info->lock,flags);
2680         tdma_reset(info);
2681         spin_unlock_irqrestore(&info->lock,flags);
2682         return 0;
2683 }
2684
2685 static int rx_enable(struct slgt_info *info, int enable)
2686 {
2687         unsigned long flags;
2688         unsigned int rbuf_fill_level;
2689         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2690         spin_lock_irqsave(&info->lock,flags);
2691         /*
2692          * enable[31..16] = receive DMA buffer fill level
2693          * 0 = noop (leave fill level unchanged)
2694          * fill level must be multiple of 4 and <= buffer size
2695          */
2696         rbuf_fill_level = ((unsigned int)enable) >> 16;
2697         if (rbuf_fill_level) {
2698                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2699                         spin_unlock_irqrestore(&info->lock, flags);
2700                         return -EINVAL;
2701                 }
2702                 info->rbuf_fill_level = rbuf_fill_level;
2703                 if (rbuf_fill_level < 128)
2704                         info->rx_pio = 1; /* PIO mode */
2705                 else
2706                         info->rx_pio = 0; /* DMA mode */
2707                 rx_stop(info); /* restart receiver to use new fill level */
2708         }
2709
2710         /*
2711          * enable[1..0] = receiver enable command
2712          * 0 = disable
2713          * 1 = enable
2714          * 2 = enable or force hunt mode if already enabled
2715          */
2716         enable &= 3;
2717         if (enable) {
2718                 if (!info->rx_enabled)
2719                         rx_start(info);
2720                 else if (enable == 2) {
2721                         /* force hunt mode (write 1 to RCR[3]) */
2722                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2723                 }
2724         } else {
2725                 if (info->rx_enabled)
2726                         rx_stop(info);
2727         }
2728         spin_unlock_irqrestore(&info->lock,flags);
2729         return 0;
2730 }
2731
2732 /*
2733  *  wait for specified event to occur
2734  */
2735 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2736 {
2737         unsigned long flags;
2738         int s;
2739         int rc=0;
2740         struct mgsl_icount cprev, cnow;
2741         int events;
2742         int mask;
2743         struct  _input_signal_events oldsigs, newsigs;
2744         DECLARE_WAITQUEUE(wait, current);
2745
2746         if (get_user(mask, mask_ptr))
2747                 return -EFAULT;
2748
2749         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2750
2751         spin_lock_irqsave(&info->lock,flags);
2752
2753         /* return immediately if state matches requested events */
2754         get_signals(info);
2755         s = info->signals;
2756
2757         events = mask &
2758                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2759                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2760                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2761                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2762         if (events) {
2763                 spin_unlock_irqrestore(&info->lock,flags);
2764                 goto exit;
2765         }
2766
2767         /* save current irq counts */
2768         cprev = info->icount;
2769         oldsigs = info->input_signal_events;
2770
2771         /* enable hunt and idle irqs if needed */
2772         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2773                 unsigned short val = rd_reg16(info, SCR);
2774                 if (!(val & IRQ_RXIDLE))
2775                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2776         }
2777
2778         set_current_state(TASK_INTERRUPTIBLE);
2779         add_wait_queue(&info->event_wait_q, &wait);
2780
2781         spin_unlock_irqrestore(&info->lock,flags);
2782
2783         for(;;) {
2784                 schedule();
2785                 if (signal_pending(current)) {
2786                         rc = -ERESTARTSYS;
2787                         break;
2788                 }
2789
2790                 /* get current irq counts */
2791                 spin_lock_irqsave(&info->lock,flags);
2792                 cnow = info->icount;
2793                 newsigs = info->input_signal_events;
2794                 set_current_state(TASK_INTERRUPTIBLE);
2795                 spin_unlock_irqrestore(&info->lock,flags);
2796
2797                 /* if no change, wait aborted for some reason */
2798                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2799                     newsigs.dsr_down == oldsigs.dsr_down &&
2800                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2801                     newsigs.dcd_down == oldsigs.dcd_down &&
2802                     newsigs.cts_up   == oldsigs.cts_up   &&
2803                     newsigs.cts_down == oldsigs.cts_down &&
2804                     newsigs.ri_up    == oldsigs.ri_up    &&
2805                     newsigs.ri_down  == oldsigs.ri_down  &&
2806                     cnow.exithunt    == cprev.exithunt   &&
2807                     cnow.rxidle      == cprev.rxidle) {
2808                         rc = -EIO;
2809                         break;
2810                 }
2811
2812                 events = mask &
2813                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2814                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2815                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2816                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2817                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2818                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2819                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2820                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2821                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2822                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2823                 if (events)
2824                         break;
2825
2826                 cprev = cnow;
2827                 oldsigs = newsigs;
2828         }
2829
2830         remove_wait_queue(&info->event_wait_q, &wait);
2831         set_current_state(TASK_RUNNING);
2832
2833
2834         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2835                 spin_lock_irqsave(&info->lock,flags);
2836                 if (!waitqueue_active(&info->event_wait_q)) {
2837                         /* disable enable exit hunt mode/idle rcvd IRQs */
2838                         wr_reg16(info, SCR,
2839                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2840                 }
2841                 spin_unlock_irqrestore(&info->lock,flags);
2842         }
2843 exit:
2844         if (rc == 0)
2845                 rc = put_user(events, mask_ptr);
2846         return rc;
2847 }
2848
2849 static int get_interface(struct slgt_info *info, int __user *if_mode)
2850 {
2851         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2852         if (put_user(info->if_mode, if_mode))
2853                 return -EFAULT;
2854         return 0;
2855 }
2856
2857 static int set_interface(struct slgt_info *info, int if_mode)
2858 {
2859         unsigned long flags;
2860         unsigned short val;
2861
2862         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2863         spin_lock_irqsave(&info->lock,flags);
2864         info->if_mode = if_mode;
2865
2866         msc_set_vcr(info);
2867
2868         /* TCR (tx control) 07  1=RTS driver control */
2869         val = rd_reg16(info, TCR);
2870         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2871                 val |= BIT7;
2872         else
2873                 val &= ~BIT7;
2874         wr_reg16(info, TCR, val);
2875
2876         spin_unlock_irqrestore(&info->lock,flags);
2877         return 0;
2878 }
2879
2880 static int get_xsync(struct slgt_info *info, int __user *xsync)
2881 {
2882         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2883         if (put_user(info->xsync, xsync))
2884                 return -EFAULT;
2885         return 0;
2886 }
2887
2888 /*
2889  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2890  *
2891  * sync pattern is contained in least significant bytes of value
2892  * most significant byte of sync pattern is oldest (1st sent/detected)
2893  */
2894 static int set_xsync(struct slgt_info *info, int xsync)
2895 {
2896         unsigned long flags;
2897
2898         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2899         spin_lock_irqsave(&info->lock, flags);
2900         info->xsync = xsync;
2901         wr_reg32(info, XSR, xsync);
2902         spin_unlock_irqrestore(&info->lock, flags);
2903         return 0;
2904 }
2905
2906 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2907 {
2908         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2909         if (put_user(info->xctrl, xctrl))
2910                 return -EFAULT;
2911         return 0;
2912 }
2913
2914 /*
2915  * set extended control options
2916  *
2917  * xctrl[31:19] reserved, must be zero
2918  * xctrl[18:17] extended sync pattern length in bytes
2919  *              00 = 1 byte  in xsr[7:0]
2920  *              01 = 2 bytes in xsr[15:0]
2921  *              10 = 3 bytes in xsr[23:0]
2922  *              11 = 4 bytes in xsr[31:0]
2923  * xctrl[16]    1 = enable terminal count, 0=disabled
2924  * xctrl[15:0]  receive terminal count for fixed length packets
2925  *              value is count minus one (0 = 1 byte packet)
2926  *              when terminal count is reached, receiver
2927  *              automatically returns to hunt mode and receive
2928  *              FIFO contents are flushed to DMA buffers with
2929  *              end of frame (EOF) status
2930  */
2931 static int set_xctrl(struct slgt_info *info, int xctrl)
2932 {
2933         unsigned long flags;
2934
2935         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2936         spin_lock_irqsave(&info->lock, flags);
2937         info->xctrl = xctrl;
2938         wr_reg32(info, XCR, xctrl);
2939         spin_unlock_irqrestore(&info->lock, flags);
2940         return 0;
2941 }
2942
2943 /*
2944  * set general purpose IO pin state and direction
2945  *
2946  * user_gpio fields:
2947  * state   each bit indicates a pin state
2948  * smask   set bit indicates pin state to set
2949  * dir     each bit indicates a pin direction (0=input, 1=output)
2950  * dmask   set bit indicates pin direction to set
2951  */
2952 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2953 {
2954         unsigned long flags;
2955         struct gpio_desc gpio;
2956         __u32 data;
2957
2958         if (!info->gpio_present)
2959                 return -EINVAL;
2960         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2961                 return -EFAULT;
2962         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2963                  info->device_name, gpio.state, gpio.smask,
2964                  gpio.dir, gpio.dmask));
2965
2966         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2967         if (gpio.dmask) {
2968                 data = rd_reg32(info, IODR);
2969                 data |= gpio.dmask & gpio.dir;
2970                 data &= ~(gpio.dmask & ~gpio.dir);
2971                 wr_reg32(info, IODR, data);
2972         }
2973         if (gpio.smask) {
2974                 data = rd_reg32(info, IOVR);
2975                 data |= gpio.smask & gpio.state;
2976                 data &= ~(gpio.smask & ~gpio.state);
2977                 wr_reg32(info, IOVR, data);
2978         }
2979         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2980
2981         return 0;
2982 }
2983
2984 /*
2985  * get general purpose IO pin state and direction
2986  */
2987 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2988 {
2989         struct gpio_desc gpio;
2990         if (!info->gpio_present)
2991                 return -EINVAL;
2992         gpio.state = rd_reg32(info, IOVR);
2993         gpio.smask = 0xffffffff;
2994         gpio.dir   = rd_reg32(info, IODR);
2995         gpio.dmask = 0xffffffff;
2996         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2997                 return -EFAULT;
2998         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2999                  info->device_name, gpio.state, gpio.dir));
3000         return 0;
3001 }
3002
3003 /*
3004  * conditional wait facility
3005  */
3006 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3007 {
3008         init_waitqueue_head(&w->q);
3009         init_waitqueue_entry(&w->wait, current);
3010         w->data = data;
3011 }
3012
3013 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3014 {
3015         set_current_state(TASK_INTERRUPTIBLE);
3016         add_wait_queue(&w->q, &w->wait);
3017         w->next = *head;
3018         *head = w;
3019 }
3020
3021 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3022 {
3023         struct cond_wait *w, *prev;
3024         remove_wait_queue(&cw->q, &cw->wait);
3025         set_current_state(TASK_RUNNING);
3026         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3027                 if (w == cw) {
3028                         if (prev != NULL)
3029                                 prev->next = w->next;
3030                         else
3031                                 *head = w->next;
3032                         break;
3033                 }
3034         }
3035 }
3036
3037 static void flush_cond_wait(struct cond_wait **head)
3038 {
3039         while (*head != NULL) {
3040                 wake_up_interruptible(&(*head)->q);
3041                 *head = (*head)->next;
3042         }
3043 }
3044
3045 /*
3046  * wait for general purpose I/O pin(s) to enter specified state
3047  *
3048  * user_gpio fields:
3049  * state - bit indicates target pin state
3050  * smask - set bit indicates watched pin
3051  *
3052  * The wait ends when at least one watched pin enters the specified
3053  * state. When 0 (no error) is returned, user_gpio->state is set to the
3054  * state of all GPIO pins when the wait ends.
3055  *
3056  * Note: Each pin may be a dedicated input, dedicated output, or
3057  * configurable input/output. The number and configuration of pins
3058  * varies with the specific adapter model. Only input pins (dedicated
3059  * or configured) can be monitored with this function.
3060  */
3061 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3062 {
3063         unsigned long flags;
3064         int rc = 0;
3065         struct gpio_desc gpio;
3066         struct cond_wait wait;
3067         u32 state;
3068
3069         if (!info->gpio_present)
3070                 return -EINVAL;
3071         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3072                 return -EFAULT;
3073         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3074                  info->device_name, gpio.state, gpio.smask));
3075         /* ignore output pins identified by set IODR bit */
3076         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3077                 return -EINVAL;
3078         init_cond_wait(&wait, gpio.smask);
3079
3080         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3081         /* enable interrupts for watched pins */
3082         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3083         /* get current pin states */
3084         state = rd_reg32(info, IOVR);
3085
3086         if (gpio.smask & ~(state ^ gpio.state)) {
3087                 /* already in target state */
3088                 gpio.state = state;
3089         } else {
3090                 /* wait for target state */
3091                 add_cond_wait(&info->gpio_wait_q, &wait);
3092                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3093                 schedule();
3094                 if (signal_pending(current))
3095                         rc = -ERESTARTSYS;
3096                 else
3097                         gpio.state = wait.data;
3098                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3099                 remove_cond_wait(&info->gpio_wait_q, &wait);
3100         }
3101
3102         /* disable all GPIO interrupts if no waiting processes */
3103         if (info->gpio_wait_q == NULL)
3104                 wr_reg32(info, IOER, 0);
3105         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3106
3107         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3108                 rc = -EFAULT;
3109         return rc;
3110 }
3111
3112 static int modem_input_wait(struct slgt_info *info,int arg)
3113 {
3114         unsigned long flags;
3115         int rc;
3116         struct mgsl_icount cprev, cnow;
3117         DECLARE_WAITQUEUE(wait, current);
3118
3119         /* save current irq counts */
3120         spin_lock_irqsave(&info->lock,flags);
3121         cprev = info->icount;
3122         add_wait_queue(&info->status_event_wait_q, &wait);
3123         set_current_state(TASK_INTERRUPTIBLE);
3124         spin_unlock_irqrestore(&info->lock,flags);
3125
3126         for(;;) {
3127                 schedule();
3128                 if (signal_pending(current)) {
3129                         rc = -ERESTARTSYS;
3130                         break;
3131                 }
3132
3133                 /* get new irq counts */
3134                 spin_lock_irqsave(&info->lock,flags);
3135                 cnow = info->icount;
3136                 set_current_state(TASK_INTERRUPTIBLE);
3137                 spin_unlock_irqrestore(&info->lock,flags);
3138
3139                 /* if no change, wait aborted for some reason */
3140                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3141                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3142                         rc = -EIO;
3143                         break;
3144                 }
3145
3146                 /* check for change in caller specified modem input */
3147                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3148                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3149                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3150                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3151                         rc = 0;
3152                         break;
3153                 }
3154
3155                 cprev = cnow;
3156         }
3157         remove_wait_queue(&info->status_event_wait_q, &wait);
3158         set_current_state(TASK_RUNNING);
3159         return rc;
3160 }
3161
3162 /*
3163  *  return state of serial control and status signals
3164  */
3165 static int tiocmget(struct tty_struct *tty)
3166 {
3167         struct slgt_info *info = tty->driver_data;
3168         unsigned int result;
3169         unsigned long flags;
3170
3171         spin_lock_irqsave(&info->lock,flags);
3172         get_signals(info);
3173         spin_unlock_irqrestore(&info->lock,flags);
3174
3175         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3176                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3177                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3178                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3179                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3180                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3181
3182         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3183         return result;
3184 }
3185
3186 /*
3187  * set modem control signals (DTR/RTS)
3188  *
3189  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3190  *              TIOCMSET = set/clear signal values
3191  *      value   bit mask for command
3192  */
3193 static int tiocmset(struct tty_struct *tty,
3194                     unsigned int set, unsigned int clear)
3195 {
3196         struct slgt_info *info = tty->driver_data;
3197         unsigned long flags;
3198
3199         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3200
3201         if (set & TIOCM_RTS)
3202                 info->signals |= SerialSignal_RTS;
3203         if (set & TIOCM_DTR)
3204                 info->signals |= SerialSignal_DTR;
3205         if (clear & TIOCM_RTS)
3206                 info->signals &= ~SerialSignal_RTS;
3207         if (clear & TIOCM_DTR)
3208                 info->signals &= ~SerialSignal_DTR;
3209
3210         spin_lock_irqsave(&info->lock,flags);
3211         set_signals(info);
3212         spin_unlock_irqrestore(&info->lock,flags);
3213         return 0;
3214 }
3215
3216 static int carrier_raised(struct tty_port *port)
3217 {
3218         unsigned long flags;
3219         struct slgt_info *info = container_of(port, struct slgt_info, port);
3220
3221         spin_lock_irqsave(&info->lock,flags);
3222         get_signals(info);
3223         spin_unlock_irqrestore(&info->lock,flags);
3224         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3225 }
3226
3227 static void dtr_rts(struct tty_port *port, int on)
3228 {
3229         unsigned long flags;
3230         struct slgt_info *info = container_of(port, struct slgt_info, port);
3231
3232         spin_lock_irqsave(&info->lock,flags);
3233         if (on)
3234                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3235         else
3236                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3237         set_signals(info);
3238         spin_unlock_irqrestore(&info->lock,flags);
3239 }
3240
3241
3242 /*
3243  *  block current process until the device is ready to open
3244  */
3245 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3246                            struct slgt_info *info)
3247 {
3248         DECLARE_WAITQUEUE(wait, current);
3249         int             retval;
3250         bool            do_clocal = false;
3251         unsigned long   flags;
3252         int             cd;
3253         struct tty_port *port = &info->port;
3254
3255         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3256
3257         if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3258                 /* nonblock mode is set or port is not enabled */
3259                 tty_port_set_active(port, 1);
3260                 return 0;
3261         }
3262
3263         if (C_CLOCAL(tty))
3264                 do_clocal = true;
3265
3266         /* Wait for carrier detect and the line to become
3267          * free (i.e., not in use by the callout).  While we are in
3268          * this loop, port->count is dropped by one, so that
3269          * close() knows when to free things.  We restore it upon
3270          * exit, either normal or abnormal.
3271          */
3272
3273         retval = 0;
3274         add_wait_queue(&port->open_wait, &wait);
3275
3276         spin_lock_irqsave(&info->lock, flags);
3277         port->count--;
3278         spin_unlock_irqrestore(&info->lock, flags);
3279         port->blocked_open++;
3280
3281         while (1) {
3282                 if (C_BAUD(tty) && tty_port_initialized(port))
3283                         tty_port_raise_dtr_rts(port);
3284
3285                 set_current_state(TASK_INTERRUPTIBLE);
3286
3287                 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3288                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3289                                         -EAGAIN : -ERESTARTSYS;
3290                         break;
3291                 }
3292
3293                 cd = tty_port_carrier_raised(port);
3294                 if (do_clocal || cd)
3295                         break;
3296
3297                 if (signal_pending(current)) {
3298                         retval = -ERESTARTSYS;
3299                         break;
3300                 }
3301
3302                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3303                 tty_unlock(tty);
3304                 schedule();
3305                 tty_lock(tty);
3306         }
3307
3308         set_current_state(TASK_RUNNING);
3309         remove_wait_queue(&port->open_wait, &wait);
3310
3311         if (!tty_hung_up_p(filp))
3312                 port->count++;
3313         port->blocked_open--;
3314
3315         if (!retval)
3316                 tty_port_set_active(port, 1);
3317
3318         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3319         return retval;
3320 }
3321
3322 /*
3323  * allocate buffers used for calling line discipline receive_buf
3324  * directly in synchronous mode
3325  * note: add 5 bytes to max frame size to allow appending
3326  * 32-bit CRC and status byte when configured to do so
3327  */
3328 static int alloc_tmp_rbuf(struct slgt_info *info)
3329 {
3330         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3331         if (info->tmp_rbuf == NULL)
3332                 return -ENOMEM;
3333         /* unused flag buffer to satisfy receive_buf calling interface */
3334         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3335         if (!info->flag_buf) {
3336                 kfree(info->tmp_rbuf);
3337                 info->tmp_rbuf = NULL;
3338                 return -ENOMEM;
3339         }
3340         return 0;
3341 }
3342
3343 static void free_tmp_rbuf(struct slgt_info *info)
3344 {
3345         kfree(info->tmp_rbuf);
3346         info->tmp_rbuf = NULL;
3347         kfree(info->flag_buf);
3348         info->flag_buf = NULL;
3349 }
3350
3351 /*
3352  * allocate DMA descriptor lists.
3353  */
3354 static int alloc_desc(struct slgt_info *info)
3355 {
3356         unsigned int i;
3357         unsigned int pbufs;
3358
3359         /* allocate memory to hold descriptor lists */
3360         info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3361                                            &info->bufs_dma_addr);
3362         if (info->bufs == NULL)
3363                 return -ENOMEM;
3364
3365         info->rbufs = (struct slgt_desc*)info->bufs;
3366         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3367
3368         pbufs = (unsigned int)info->bufs_dma_addr;
3369
3370         /*
3371          * Build circular lists of descriptors
3372          */
3373
3374         for (i=0; i < info->rbuf_count; i++) {
3375                 /* physical address of this descriptor */
3376                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3377
3378                 /* physical address of next descriptor */
3379                 if (i == info->rbuf_count - 1)
3380                         info->rbufs[i].next = cpu_to_le32(pbufs);
3381                 else
3382                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3383                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3384         }
3385
3386         for (i=0; i < info->tbuf_count; i++) {
3387                 /* physical address of this descriptor */
3388                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3389
3390                 /* physical address of next descriptor */
3391                 if (i == info->tbuf_count - 1)
3392                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3393                 else
3394                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3395         }
3396
3397         return 0;
3398 }
3399
3400 static void free_desc(struct slgt_info *info)
3401 {
3402         if (info->bufs != NULL) {
3403                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3404                 info->bufs  = NULL;
3405                 info->rbufs = NULL;
3406                 info->tbufs = NULL;
3407         }
3408 }
3409
3410 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3411 {
3412         int i;
3413         for (i=0; i < count; i++) {
3414                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3415                         return -ENOMEM;
3416                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3417         }
3418         return 0;
3419 }
3420
3421 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3422 {
3423         int i;
3424         for (i=0; i < count; i++) {
3425                 if (bufs[i].buf == NULL)
3426                         continue;
3427                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3428                 bufs[i].buf = NULL;
3429         }
3430 }
3431
3432 static int alloc_dma_bufs(struct slgt_info *info)
3433 {
3434         info->rbuf_count = 32;
3435         info->tbuf_count = 32;
3436
3437         if (alloc_desc(info) < 0 ||
3438             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3439             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3440             alloc_tmp_rbuf(info) < 0) {
3441                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3442                 return -ENOMEM;
3443         }
3444         reset_rbufs(info);
3445         return 0;
3446 }
3447
3448 static void free_dma_bufs(struct slgt_info *info)
3449 {
3450         if (info->bufs) {
3451                 free_bufs(info, info->rbufs, info->rbuf_count);
3452                 free_bufs(info, info->tbufs, info->tbuf_count);
3453                 free_desc(info);
3454         }
3455         free_tmp_rbuf(info);
3456 }
3457
3458 static int claim_resources(struct slgt_info *info)
3459 {
3460         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3461                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3462                         info->device_name, info->phys_reg_addr));
3463                 info->init_error = DiagStatus_AddressConflict;
3464                 goto errout;
3465         }
3466         else
3467                 info->reg_addr_requested = true;
3468
3469         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3470         if (!info->reg_addr) {
3471                 DBGERR(("%s can't map device registers, addr=%08X\n",
3472                         info->device_name, info->phys_reg_addr));
3473                 info->init_error = DiagStatus_CantAssignPciResources;
3474                 goto errout;
3475         }
3476         return 0;
3477
3478 errout:
3479         release_resources(info);
3480         return -ENODEV;
3481 }
3482
3483 static void release_resources(struct slgt_info *info)
3484 {
3485         if (info->irq_requested) {
3486                 free_irq(info->irq_level, info);
3487                 info->irq_requested = false;
3488         }
3489
3490         if (info->reg_addr_requested) {
3491                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3492                 info->reg_addr_requested = false;
3493         }
3494
3495         if (info->reg_addr) {
3496                 iounmap(info->reg_addr);
3497                 info->reg_addr = NULL;
3498         }
3499 }
3500
3501 /* Add the specified device instance data structure to the
3502  * global linked list of devices and increment the device count.
3503  */
3504 static void add_device(struct slgt_info *info)
3505 {
3506         char *devstr;
3507
3508         info->next_device = NULL;
3509         info->line = slgt_device_count;
3510         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3511
3512         if (info->line < MAX_DEVICES) {
3513                 if (maxframe[info->line])
3514                         info->max_frame_size = maxframe[info->line];
3515         }
3516
3517         slgt_device_count++;
3518
3519         if (!slgt_device_list)
3520                 slgt_device_list = info;
3521         else {
3522                 struct slgt_info *current_dev = slgt_device_list;
3523                 while(current_dev->next_device)
3524                         current_dev = current_dev->next_device;
3525                 current_dev->next_device = info;
3526         }
3527
3528         if (info->max_frame_size < 4096)
3529                 info->max_frame_size = 4096;
3530         else if (info->max_frame_size > 65535)
3531                 info->max_frame_size = 65535;
3532
3533         switch(info->pdev->device) {
3534         case SYNCLINK_GT_DEVICE_ID:
3535                 devstr = "GT";
3536                 break;
3537         case SYNCLINK_GT2_DEVICE_ID:
3538                 devstr = "GT2";
3539                 break;
3540         case SYNCLINK_GT4_DEVICE_ID:
3541                 devstr = "GT4";
3542                 break;
3543         case SYNCLINK_AC_DEVICE_ID:
3544                 devstr = "AC";
3545                 info->params.mode = MGSL_MODE_ASYNC;
3546                 break;
3547         default:
3548                 devstr = "(unknown model)";
3549         }
3550         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3551                 devstr, info->device_name, info->phys_reg_addr,
3552                 info->irq_level, info->max_frame_size);
3553
3554 #if SYNCLINK_GENERIC_HDLC
3555         hdlcdev_init(info);
3556 #endif
3557 }
3558
3559 static const struct tty_port_operations slgt_port_ops = {
3560         .carrier_raised = carrier_raised,
3561         .dtr_rts = dtr_rts,
3562 };
3563
3564 /*
3565  *  allocate device instance structure, return NULL on failure
3566  */
3567 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3568 {
3569         struct slgt_info *info;
3570
3571         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3572
3573         if (!info) {
3574                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3575                         driver_name, adapter_num, port_num));
3576         } else {
3577                 tty_port_init(&info->port);
3578                 info->port.ops = &slgt_port_ops;
3579                 info->magic = MGSL_MAGIC;
3580                 INIT_WORK(&info->task, bh_handler);
3581                 info->max_frame_size = 4096;
3582                 info->base_clock = 14745600;
3583                 info->rbuf_fill_level = DMABUFSIZE;
3584                 info->port.close_delay = 5*HZ/10;
3585                 info->port.closing_wait = 30*HZ;
3586                 init_waitqueue_head(&info->status_event_wait_q);
3587                 init_waitqueue_head(&info->event_wait_q);
3588                 spin_lock_init(&info->netlock);
3589                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3590                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3591                 info->adapter_num = adapter_num;
3592                 info->port_num = port_num;
3593
3594                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3595                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3596
3597                 /* Copy configuration info to device instance data */
3598                 info->pdev = pdev;
3599                 info->irq_level = pdev->irq;
3600                 info->phys_reg_addr = pci_resource_start(pdev,0);
3601
3602                 info->bus_type = MGSL_BUS_TYPE_PCI;
3603                 info->irq_flags = IRQF_SHARED;
3604
3605                 info->init_error = -1; /* assume error, set to 0 on successful init */
3606         }
3607
3608         return info;
3609 }
3610
3611 static void device_init(int adapter_num, struct pci_dev *pdev)
3612 {
3613         struct slgt_info *port_array[SLGT_MAX_PORTS];
3614         int i;
3615         int port_count = 1;
3616
3617         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3618                 port_count = 2;
3619         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3620                 port_count = 4;
3621
3622         /* allocate device instances for all ports */
3623         for (i=0; i < port_count; ++i) {
3624                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3625                 if (port_array[i] == NULL) {
3626                         for (--i; i >= 0; --i) {
3627                                 tty_port_destroy(&port_array[i]->port);
3628                                 kfree(port_array[i]);
3629                         }
3630                         return;
3631                 }
3632         }
3633
3634         /* give copy of port_array to all ports and add to device list  */
3635         for (i=0; i < port_count; ++i) {
3636                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3637                 add_device(port_array[i]);
3638                 port_array[i]->port_count = port_count;
3639                 spin_lock_init(&port_array[i]->lock);
3640         }
3641
3642         /* Allocate and claim adapter resources */
3643         if (!claim_resources(port_array[0])) {
3644
3645                 alloc_dma_bufs(port_array[0]);
3646
3647                 /* copy resource information from first port to others */
3648                 for (i = 1; i < port_count; ++i) {
3649                         port_array[i]->irq_level = port_array[0]->irq_level;
3650                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3651                         alloc_dma_bufs(port_array[i]);
3652                 }
3653
3654                 if (request_irq(port_array[0]->irq_level,
3655                                         slgt_interrupt,
3656                                         port_array[0]->irq_flags,
3657                                         port_array[0]->device_name,
3658                                         port_array[0]) < 0) {
3659                         DBGERR(("%s request_irq failed IRQ=%d\n",
3660                                 port_array[0]->device_name,
3661                                 port_array[0]->irq_level));
3662                 } else {
3663                         port_array[0]->irq_requested = true;
3664                         adapter_test(port_array[0]);
3665                         for (i=1 ; i < port_count ; i++) {
3666                                 port_array[i]->init_error = port_array[0]->init_error;
3667                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3668                         }
3669                 }
3670         }
3671
3672         for (i = 0; i < port_count; ++i) {
3673                 struct slgt_info *info = port_array[i];
3674                 tty_port_register_device(&info->port, serial_driver, info->line,
3675                                 &info->pdev->dev);
3676         }
3677 }
3678
3679 static int init_one(struct pci_dev *dev,
3680                               const struct pci_device_id *ent)
3681 {
3682         if (pci_enable_device(dev)) {
3683                 printk("error enabling pci device %p\n", dev);
3684                 return -EIO;
3685         }
3686         pci_set_master(dev);
3687         device_init(slgt_device_count, dev);
3688         return 0;
3689 }
3690
3691 static void remove_one(struct pci_dev *dev)
3692 {
3693 }
3694
3695 static const struct tty_operations ops = {
3696         .open = open,
3697         .close = close,
3698         .write = write,
3699         .put_char = put_char,
3700         .flush_chars = flush_chars,
3701         .write_room = write_room,
3702         .chars_in_buffer = chars_in_buffer,
3703         .flush_buffer = flush_buffer,
3704         .ioctl = ioctl,
3705         .compat_ioctl = slgt_compat_ioctl,
3706         .throttle = throttle,
3707         .unthrottle = unthrottle,
3708         .send_xchar = send_xchar,
3709         .break_ctl = set_break,
3710         .wait_until_sent = wait_until_sent,
3711         .set_termios = set_termios,
3712         .stop = tx_hold,
3713         .start = tx_release,
3714         .hangup = hangup,
3715         .tiocmget = tiocmget,
3716         .tiocmset = tiocmset,
3717         .get_icount = get_icount,
3718         .proc_fops = &synclink_gt_proc_fops,
3719 };
3720
3721 static void slgt_cleanup(void)
3722 {
3723         int rc;
3724         struct slgt_info *info;
3725         struct slgt_info *tmp;
3726
3727         printk(KERN_INFO "unload %s\n", driver_name);
3728
3729         if (serial_driver) {
3730                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3731                         tty_unregister_device(serial_driver, info->line);
3732                 rc = tty_unregister_driver(serial_driver);
3733                 if (rc)
3734                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3735                 put_tty_driver(serial_driver);
3736         }
3737
3738         /* reset devices */
3739         info = slgt_device_list;
3740         while(info) {
3741                 reset_port(info);
3742                 info = info->next_device;
3743         }
3744
3745         /* release devices */
3746         info = slgt_device_list;
3747         while(info) {
3748 #if SYNCLINK_GENERIC_HDLC
3749                 hdlcdev_exit(info);
3750 #endif
3751                 free_dma_bufs(info);
3752                 free_tmp_rbuf(info);
3753                 if (info->port_num == 0)
3754                         release_resources(info);
3755                 tmp = info;
3756                 info = info->next_device;
3757                 tty_port_destroy(&tmp->port);
3758                 kfree(tmp);
3759         }
3760
3761         if (pci_registered)
3762                 pci_unregister_driver(&pci_driver);
3763 }
3764
3765 /*
3766  *  Driver initialization entry point.
3767  */
3768 static int __init slgt_init(void)
3769 {
3770         int rc;
3771
3772         printk(KERN_INFO "%s\n", driver_name);
3773
3774         serial_driver = alloc_tty_driver(MAX_DEVICES);
3775         if (!serial_driver) {
3776                 printk("%s can't allocate tty driver\n", driver_name);
3777                 return -ENOMEM;
3778         }
3779
3780         /* Initialize the tty_driver structure */
3781
3782         serial_driver->driver_name = slgt_driver_name;
3783         serial_driver->name = tty_dev_prefix;
3784         serial_driver->major = ttymajor;
3785         serial_driver->minor_start = 64;
3786         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3787         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3788         serial_driver->init_termios = tty_std_termios;
3789         serial_driver->init_termios.c_cflag =
3790                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3791         serial_driver->init_termios.c_ispeed = 9600;
3792         serial_driver->init_termios.c_ospeed = 9600;
3793         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3794         tty_set_operations(serial_driver, &ops);
3795         if ((rc = tty_register_driver(serial_driver)) < 0) {
3796                 DBGERR(("%s can't register serial driver\n", driver_name));
3797                 put_tty_driver(serial_driver);
3798                 serial_driver = NULL;
3799                 goto error;
3800         }
3801
3802         printk(KERN_INFO "%s, tty major#%d\n",
3803                driver_name, serial_driver->major);
3804
3805         slgt_device_count = 0;
3806         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3807                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3808                 goto error;
3809         }
3810         pci_registered = true;
3811
3812         if (!slgt_device_list)
3813                 printk("%s no devices found\n",driver_name);
3814
3815         return 0;
3816
3817 error:
3818         slgt_cleanup();
3819         return rc;
3820 }
3821
3822 static void __exit slgt_exit(void)
3823 {
3824         slgt_cleanup();
3825 }
3826
3827 module_init(slgt_init);
3828 module_exit(slgt_exit);
3829
3830 /*
3831  * register access routines
3832  */
3833
3834 #define CALC_REGADDR() \
3835         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3836         if (addr >= 0x80) \
3837                 reg_addr += (info->port_num) * 32; \
3838         else if (addr >= 0x40)  \
3839                 reg_addr += (info->port_num) * 16;
3840
3841 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3842 {
3843         CALC_REGADDR();
3844         return readb((void __iomem *)reg_addr);
3845 }
3846
3847 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3848 {
3849         CALC_REGADDR();
3850         writeb(value, (void __iomem *)reg_addr);
3851 }
3852
3853 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3854 {
3855         CALC_REGADDR();
3856         return readw((void __iomem *)reg_addr);
3857 }
3858
3859 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3860 {
3861         CALC_REGADDR();
3862         writew(value, (void __iomem *)reg_addr);
3863 }
3864
3865 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3866 {
3867         CALC_REGADDR();
3868         return readl((void __iomem *)reg_addr);
3869 }
3870
3871 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3872 {
3873         CALC_REGADDR();
3874         writel(value, (void __iomem *)reg_addr);
3875 }
3876
3877 static void rdma_reset(struct slgt_info *info)
3878 {
3879         unsigned int i;
3880
3881         /* set reset bit */
3882         wr_reg32(info, RDCSR, BIT1);
3883
3884         /* wait for enable bit cleared */
3885         for(i=0 ; i < 1000 ; i++)
3886                 if (!(rd_reg32(info, RDCSR) & BIT0))
3887                         break;
3888 }
3889
3890 static void tdma_reset(struct slgt_info *info)
3891 {
3892         unsigned int i;
3893
3894         /* set reset bit */
3895         wr_reg32(info, TDCSR, BIT1);
3896
3897         /* wait for enable bit cleared */
3898         for(i=0 ; i < 1000 ; i++)
3899                 if (!(rd_reg32(info, TDCSR) & BIT0))
3900                         break;
3901 }
3902
3903 /*
3904  * enable internal loopback
3905  * TxCLK and RxCLK are generated from BRG
3906  * and TxD is looped back to RxD internally.
3907  */
3908 static void enable_loopback(struct slgt_info *info)
3909 {
3910         /* SCR (serial control) BIT2=loopback enable */
3911         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3912
3913         if (info->params.mode != MGSL_MODE_ASYNC) {
3914                 /* CCR (clock control)
3915                  * 07..05  tx clock source (010 = BRG)
3916                  * 04..02  rx clock source (010 = BRG)
3917                  * 01      auxclk enable   (0 = disable)
3918                  * 00      BRG enable      (1 = enable)
3919                  *
3920                  * 0100 1001
3921                  */
3922                 wr_reg8(info, CCR, 0x49);
3923
3924                 /* set speed if available, otherwise use default */
3925                 if (info->params.clock_speed)
3926                         set_rate(info, info->params.clock_speed);
3927                 else
3928                         set_rate(info, 3686400);
3929         }
3930 }
3931
3932 /*
3933  *  set baud rate generator to specified rate
3934  */
3935 static void set_rate(struct slgt_info *info, u32 rate)
3936 {
3937         unsigned int div;
3938         unsigned int osc = info->base_clock;
3939
3940         /* div = osc/rate - 1
3941          *
3942          * Round div up if osc/rate is not integer to
3943          * force to next slowest rate.
3944          */
3945
3946         if (rate) {
3947                 div = osc/rate;
3948                 if (!(osc % rate) && div)
3949                         div--;
3950                 wr_reg16(info, BDR, (unsigned short)div);
3951         }
3952 }
3953
3954 static void rx_stop(struct slgt_info *info)
3955 {
3956         unsigned short val;
3957
3958         /* disable and reset receiver */
3959         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3960         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3961         wr_reg16(info, RCR, val);                  /* clear reset bit */
3962
3963         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3964
3965         /* clear pending rx interrupts */
3966         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3967
3968         rdma_reset(info);
3969
3970         info->rx_enabled = false;
3971         info->rx_restart = false;
3972 }
3973
3974 static void rx_start(struct slgt_info *info)
3975 {
3976         unsigned short val;
3977
3978         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3979
3980         /* clear pending rx overrun IRQ */
3981         wr_reg16(info, SSR, IRQ_RXOVER);
3982
3983         /* reset and disable receiver */
3984         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3985         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3986         wr_reg16(info, RCR, val);                  /* clear reset bit */
3987
3988         rdma_reset(info);
3989         reset_rbufs(info);
3990
3991         if (info->rx_pio) {
3992                 /* rx request when rx FIFO not empty */
3993                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3994                 slgt_irq_on(info, IRQ_RXDATA);
3995                 if (info->params.mode == MGSL_MODE_ASYNC) {
3996                         /* enable saving of rx status */
3997                         wr_reg32(info, RDCSR, BIT6);
3998                 }
3999         } else {
4000                 /* rx request when rx FIFO half full */
4001                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4002                 /* set 1st descriptor address */
4003                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4004
4005                 if (info->params.mode != MGSL_MODE_ASYNC) {
4006                         /* enable rx DMA and DMA interrupt */
4007                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
4008                 } else {
4009                         /* enable saving of rx status, rx DMA and DMA interrupt */
4010                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4011                 }
4012         }
4013
4014         slgt_irq_on(info, IRQ_RXOVER);
4015
4016         /* enable receiver */
4017         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4018
4019         info->rx_restart = false;
4020         info->rx_enabled = true;
4021 }
4022
4023 static void tx_start(struct slgt_info *info)
4024 {
4025         if (!info->tx_enabled) {
4026                 wr_reg16(info, TCR,
4027                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4028                 info->tx_enabled = true;
4029         }
4030
4031         if (desc_count(info->tbufs[info->tbuf_start])) {
4032                 info->drop_rts_on_tx_done = false;
4033
4034                 if (info->params.mode != MGSL_MODE_ASYNC) {
4035                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4036                                 get_signals(info);
4037                                 if (!(info->signals & SerialSignal_RTS)) {
4038                                         info->signals |= SerialSignal_RTS;
4039                                         set_signals(info);
4040                                         info->drop_rts_on_tx_done = true;
4041                                 }
4042                         }
4043
4044                         slgt_irq_off(info, IRQ_TXDATA);
4045                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4046                         /* clear tx idle and underrun status bits */
4047                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4048                 } else {
4049                         slgt_irq_off(info, IRQ_TXDATA);
4050                         slgt_irq_on(info, IRQ_TXIDLE);
4051                         /* clear tx idle status bit */
4052                         wr_reg16(info, SSR, IRQ_TXIDLE);
4053                 }
4054                 /* set 1st descriptor address and start DMA */
4055                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4056                 wr_reg32(info, TDCSR, BIT2 + BIT0);
4057                 info->tx_active = true;
4058         }
4059 }
4060
4061 static void tx_stop(struct slgt_info *info)
4062 {
4063         unsigned short val;
4064
4065         del_timer(&info->tx_timer);
4066
4067         tdma_reset(info);
4068
4069         /* reset and disable transmitter */
4070         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4071         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4072
4073         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4074
4075         /* clear tx idle and underrun status bit */
4076         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4077
4078         reset_tbufs(info);
4079
4080         info->tx_enabled = false;
4081         info->tx_active = false;
4082 }
4083
4084 static void reset_port(struct slgt_info *info)
4085 {
4086         if (!info->reg_addr)
4087                 return;
4088
4089         tx_stop(info);
4090         rx_stop(info);
4091
4092         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4093         set_signals(info);
4094
4095         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4096 }
4097
4098 static void reset_adapter(struct slgt_info *info)
4099 {
4100         int i;
4101         for (i=0; i < info->port_count; ++i) {
4102                 if (info->port_array[i])
4103                         reset_port(info->port_array[i]);
4104         }
4105 }
4106
4107 static void async_mode(struct slgt_info *info)
4108 {
4109         unsigned short val;
4110
4111         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4112         tx_stop(info);
4113         rx_stop(info);
4114
4115         /* TCR (tx control)
4116          *
4117          * 15..13  mode, 010=async
4118          * 12..10  encoding, 000=NRZ
4119          * 09      parity enable
4120          * 08      1=odd parity, 0=even parity
4121          * 07      1=RTS driver control
4122          * 06      1=break enable
4123          * 05..04  character length
4124          *         00=5 bits
4125          *         01=6 bits
4126          *         10=7 bits
4127          *         11=8 bits
4128          * 03      0=1 stop bit, 1=2 stop bits
4129          * 02      reset
4130          * 01      enable
4131          * 00      auto-CTS enable
4132          */
4133         val = 0x4000;
4134
4135         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4136                 val |= BIT7;
4137
4138         if (info->params.parity != ASYNC_PARITY_NONE) {
4139                 val |= BIT9;
4140                 if (info->params.parity == ASYNC_PARITY_ODD)
4141                         val |= BIT8;
4142         }
4143
4144         switch (info->params.data_bits)
4145         {
4146         case 6: val |= BIT4; break;
4147         case 7: val |= BIT5; break;
4148         case 8: val |= BIT5 + BIT4; break;
4149         }
4150
4151         if (info->params.stop_bits != 1)
4152                 val |= BIT3;
4153
4154         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4155                 val |= BIT0;
4156
4157         wr_reg16(info, TCR, val);
4158
4159         /* RCR (rx control)
4160          *
4161          * 15..13  mode, 010=async
4162          * 12..10  encoding, 000=NRZ
4163          * 09      parity enable
4164          * 08      1=odd parity, 0=even parity
4165          * 07..06  reserved, must be 0
4166          * 05..04  character length
4167          *         00=5 bits
4168          *         01=6 bits
4169          *         10=7 bits
4170          *         11=8 bits
4171          * 03      reserved, must be zero
4172          * 02      reset
4173          * 01      enable
4174          * 00      auto-DCD enable
4175          */
4176         val = 0x4000;
4177
4178         if (info->params.parity != ASYNC_PARITY_NONE) {
4179                 val |= BIT9;
4180                 if (info->params.parity == ASYNC_PARITY_ODD)
4181                         val |= BIT8;
4182         }
4183
4184         switch (info->params.data_bits)
4185         {
4186         case 6: val |= BIT4; break;
4187         case 7: val |= BIT5; break;
4188         case 8: val |= BIT5 + BIT4; break;
4189         }
4190
4191         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4192                 val |= BIT0;
4193
4194         wr_reg16(info, RCR, val);
4195
4196         /* CCR (clock control)
4197          *
4198          * 07..05  011 = tx clock source is BRG/16
4199          * 04..02  010 = rx clock source is BRG
4200          * 01      0 = auxclk disabled
4201          * 00      1 = BRG enabled
4202          *
4203          * 0110 1001
4204          */
4205         wr_reg8(info, CCR, 0x69);
4206
4207         msc_set_vcr(info);
4208
4209         /* SCR (serial control)
4210          *
4211          * 15  1=tx req on FIFO half empty
4212          * 14  1=rx req on FIFO half full
4213          * 13  tx data  IRQ enable
4214          * 12  tx idle  IRQ enable
4215          * 11  rx break on IRQ enable
4216          * 10  rx data  IRQ enable
4217          * 09  rx break off IRQ enable
4218          * 08  overrun  IRQ enable
4219          * 07  DSR      IRQ enable
4220          * 06  CTS      IRQ enable
4221          * 05  DCD      IRQ enable
4222          * 04  RI       IRQ enable
4223          * 03  0=16x sampling, 1=8x sampling
4224          * 02  1=txd->rxd internal loopback enable
4225          * 01  reserved, must be zero
4226          * 00  1=master IRQ enable
4227          */
4228         val = BIT15 + BIT14 + BIT0;
4229         /* JCR[8] : 1 = x8 async mode feature available */
4230         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4231             ((info->base_clock < (info->params.data_rate * 16)) ||
4232              (info->base_clock % (info->params.data_rate * 16)))) {
4233                 /* use 8x sampling */
4234                 val |= BIT3;
4235                 set_rate(info, info->params.data_rate * 8);
4236         } else {
4237                 /* use 16x sampling */
4238                 set_rate(info, info->params.data_rate * 16);
4239         }
4240         wr_reg16(info, SCR, val);
4241
4242         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4243
4244         if (info->params.loopback)
4245                 enable_loopback(info);
4246 }
4247
4248 static void sync_mode(struct slgt_info *info)
4249 {
4250         unsigned short val;
4251
4252         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4253         tx_stop(info);
4254         rx_stop(info);
4255
4256         /* TCR (tx control)
4257          *
4258          * 15..13  mode
4259          *         000=HDLC/SDLC
4260          *         001=raw bit synchronous
4261          *         010=asynchronous/isochronous
4262          *         011=monosync byte synchronous
4263          *         100=bisync byte synchronous
4264          *         101=xsync byte synchronous
4265          * 12..10  encoding
4266          * 09      CRC enable
4267          * 08      CRC32
4268          * 07      1=RTS driver control
4269          * 06      preamble enable
4270          * 05..04  preamble length
4271          * 03      share open/close flag
4272          * 02      reset
4273          * 01      enable
4274          * 00      auto-CTS enable
4275          */
4276         val = BIT2;
4277
4278         switch(info->params.mode) {
4279         case MGSL_MODE_XSYNC:
4280                 val |= BIT15 + BIT13;
4281                 break;
4282         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4283         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4284         case MGSL_MODE_RAW:      val |= BIT13; break;
4285         }
4286         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4287                 val |= BIT7;
4288
4289         switch(info->params.encoding)
4290         {
4291         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4292         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4293         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4294         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4295         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4296         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4297         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4298         }
4299
4300         switch (info->params.crc_type & HDLC_CRC_MASK)
4301         {
4302         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4303         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4304         }
4305
4306         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4307                 val |= BIT6;
4308
4309         switch (info->params.preamble_length)
4310         {
4311         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4312         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4313         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4314         }
4315
4316         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4317                 val |= BIT0;
4318
4319         wr_reg16(info, TCR, val);
4320
4321         /* TPR (transmit preamble) */
4322
4323         switch (info->params.preamble)
4324         {
4325         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4326         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4327         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4328         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4329         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4330         default:                          val = 0x7e; break;
4331         }
4332         wr_reg8(info, TPR, (unsigned char)val);
4333
4334         /* RCR (rx control)
4335          *
4336          * 15..13  mode
4337          *         000=HDLC/SDLC
4338          *         001=raw bit synchronous
4339          *         010=asynchronous/isochronous
4340          *         011=monosync byte synchronous
4341          *         100=bisync byte synchronous
4342          *         101=xsync byte synchronous
4343          * 12..10  encoding
4344          * 09      CRC enable
4345          * 08      CRC32
4346          * 07..03  reserved, must be 0
4347          * 02      reset
4348          * 01      enable
4349          * 00      auto-DCD enable
4350          */
4351         val = 0;
4352
4353         switch(info->params.mode) {
4354         case MGSL_MODE_XSYNC:
4355                 val |= BIT15 + BIT13;
4356                 break;
4357         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4358         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4359         case MGSL_MODE_RAW:      val |= BIT13; break;
4360         }
4361
4362         switch(info->params.encoding)
4363         {
4364         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4365         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4366         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4367         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4368         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4369         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4370         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4371         }
4372
4373         switch (info->params.crc_type & HDLC_CRC_MASK)
4374         {
4375         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4376         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4377         }
4378
4379         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4380                 val |= BIT0;
4381
4382         wr_reg16(info, RCR, val);
4383
4384         /* CCR (clock control)
4385          *
4386          * 07..05  tx clock source
4387          * 04..02  rx clock source
4388          * 01      auxclk enable
4389          * 00      BRG enable
4390          */
4391         val = 0;
4392
4393         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4394         {
4395                 // when RxC source is DPLL, BRG generates 16X DPLL
4396                 // reference clock, so take TxC from BRG/16 to get
4397                 // transmit clock at actual data rate
4398                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4399                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4400                 else
4401                         val |= BIT6;    /* 010, txclk = BRG */
4402         }
4403         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4404                 val |= BIT7;    /* 100, txclk = DPLL Input */
4405         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4406                 val |= BIT5;    /* 001, txclk = RXC Input */
4407
4408         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4409                 val |= BIT3;    /* 010, rxclk = BRG */
4410         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4411                 val |= BIT4;    /* 100, rxclk = DPLL */
4412         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4413                 val |= BIT2;    /* 001, rxclk = TXC Input */
4414
4415         if (info->params.clock_speed)
4416                 val |= BIT1 + BIT0;
4417
4418         wr_reg8(info, CCR, (unsigned char)val);
4419
4420         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4421         {
4422                 // program DPLL mode
4423                 switch(info->params.encoding)
4424                 {
4425                 case HDLC_ENCODING_BIPHASE_MARK:
4426                 case HDLC_ENCODING_BIPHASE_SPACE:
4427                         val = BIT7; break;
4428                 case HDLC_ENCODING_BIPHASE_LEVEL:
4429                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4430                         val = BIT7 + BIT6; break;
4431                 default: val = BIT6;    // NRZ encodings
4432                 }
4433                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4434
4435                 // DPLL requires a 16X reference clock from BRG
4436                 set_rate(info, info->params.clock_speed * 16);
4437         }
4438         else
4439                 set_rate(info, info->params.clock_speed);
4440
4441         tx_set_idle(info);
4442
4443         msc_set_vcr(info);
4444
4445         /* SCR (serial control)
4446          *
4447          * 15  1=tx req on FIFO half empty
4448          * 14  1=rx req on FIFO half full
4449          * 13  tx data  IRQ enable
4450          * 12  tx idle  IRQ enable
4451          * 11  underrun IRQ enable
4452          * 10  rx data  IRQ enable
4453          * 09  rx idle  IRQ enable
4454          * 08  overrun  IRQ enable
4455          * 07  DSR      IRQ enable
4456          * 06  CTS      IRQ enable
4457          * 05  DCD      IRQ enable
4458          * 04  RI       IRQ enable
4459          * 03  reserved, must be zero
4460          * 02  1=txd->rxd internal loopback enable
4461          * 01  reserved, must be zero
4462          * 00  1=master IRQ enable
4463          */
4464         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4465
4466         if (info->params.loopback)
4467                 enable_loopback(info);
4468 }
4469
4470 /*
4471  *  set transmit idle mode
4472  */
4473 static void tx_set_idle(struct slgt_info *info)
4474 {
4475         unsigned char val;
4476         unsigned short tcr;
4477
4478         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4479          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4480          */
4481         tcr = rd_reg16(info, TCR);
4482         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4483                 /* disable preamble, set idle size to 16 bits */
4484                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4485                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4486                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4487         } else if (!(tcr & BIT6)) {
4488                 /* preamble is disabled, set idle size to 8 bits */
4489                 tcr &= ~(BIT5 + BIT4);
4490         }
4491         wr_reg16(info, TCR, tcr);
4492
4493         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4494                 /* LSB of custom tx idle specified in tx idle register */
4495                 val = (unsigned char)(info->idle_mode & 0xff);
4496         } else {
4497                 /* standard 8 bit idle patterns */
4498                 switch(info->idle_mode)
4499                 {
4500                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4501                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4502                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4503                 case HDLC_TXIDLE_ZEROS:
4504                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4505                 default:                         val = 0xff;
4506                 }
4507         }
4508
4509         wr_reg8(info, TIR, val);
4510 }
4511
4512 /*
4513  * get state of V24 status (input) signals
4514  */
4515 static void get_signals(struct slgt_info *info)
4516 {
4517         unsigned short status = rd_reg16(info, SSR);
4518
4519         /* clear all serial signals except RTS and DTR */
4520         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4521
4522         if (status & BIT3)
4523                 info->signals |= SerialSignal_DSR;
4524         if (status & BIT2)
4525                 info->signals |= SerialSignal_CTS;
4526         if (status & BIT1)
4527                 info->signals |= SerialSignal_DCD;
4528         if (status & BIT0)
4529                 info->signals |= SerialSignal_RI;
4530 }
4531
4532 /*
4533  * set V.24 Control Register based on current configuration
4534  */
4535 static void msc_set_vcr(struct slgt_info *info)
4536 {
4537         unsigned char val = 0;
4538
4539         /* VCR (V.24 control)
4540          *
4541          * 07..04  serial IF select
4542          * 03      DTR
4543          * 02      RTS
4544          * 01      LL
4545          * 00      RL
4546          */
4547
4548         switch(info->if_mode & MGSL_INTERFACE_MASK)
4549         {
4550         case MGSL_INTERFACE_RS232:
4551                 val |= BIT5; /* 0010 */
4552                 break;
4553         case MGSL_INTERFACE_V35:
4554                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4555                 break;
4556         case MGSL_INTERFACE_RS422:
4557                 val |= BIT6; /* 0100 */
4558                 break;
4559         }
4560
4561         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4562                 val |= BIT4;
4563         if (info->signals & SerialSignal_DTR)
4564                 val |= BIT3;
4565         if (info->signals & SerialSignal_RTS)
4566                 val |= BIT2;
4567         if (info->if_mode & MGSL_INTERFACE_LL)
4568                 val |= BIT1;
4569         if (info->if_mode & MGSL_INTERFACE_RL)
4570                 val |= BIT0;
4571         wr_reg8(info, VCR, val);
4572 }
4573
4574 /*
4575  * set state of V24 control (output) signals
4576  */
4577 static void set_signals(struct slgt_info *info)
4578 {
4579         unsigned char val = rd_reg8(info, VCR);
4580         if (info->signals & SerialSignal_DTR)
4581                 val |= BIT3;
4582         else
4583                 val &= ~BIT3;
4584         if (info->signals & SerialSignal_RTS)
4585                 val |= BIT2;
4586         else
4587                 val &= ~BIT2;
4588         wr_reg8(info, VCR, val);
4589 }
4590
4591 /*
4592  * free range of receive DMA buffers (i to last)
4593  */
4594 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4595 {
4596         int done = 0;
4597
4598         while(!done) {
4599                 /* reset current buffer for reuse */
4600                 info->rbufs[i].status = 0;
4601                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4602                 if (i == last)
4603                         done = 1;
4604                 if (++i == info->rbuf_count)
4605                         i = 0;
4606         }
4607         info->rbuf_current = i;
4608 }
4609
4610 /*
4611  * mark all receive DMA buffers as free
4612  */
4613 static void reset_rbufs(struct slgt_info *info)
4614 {
4615         free_rbufs(info, 0, info->rbuf_count - 1);
4616         info->rbuf_fill_index = 0;
4617         info->rbuf_fill_count = 0;
4618 }
4619
4620 /*
4621  * pass receive HDLC frame to upper layer
4622  *
4623  * return true if frame available, otherwise false
4624  */
4625 static bool rx_get_frame(struct slgt_info *info)
4626 {
4627         unsigned int start, end;
4628         unsigned short status;
4629         unsigned int framesize = 0;
4630         unsigned long flags;
4631         struct tty_struct *tty = info->port.tty;
4632         unsigned char addr_field = 0xff;
4633         unsigned int crc_size = 0;
4634
4635         switch (info->params.crc_type & HDLC_CRC_MASK) {
4636         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4637         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4638         }
4639
4640 check_again:
4641
4642         framesize = 0;
4643         addr_field = 0xff;
4644         start = end = info->rbuf_current;
4645
4646         for (;;) {
4647                 if (!desc_complete(info->rbufs[end]))
4648                         goto cleanup;
4649
4650                 if (framesize == 0 && info->params.addr_filter != 0xff)
4651                         addr_field = info->rbufs[end].buf[0];
4652
4653                 framesize += desc_count(info->rbufs[end]);
4654
4655                 if (desc_eof(info->rbufs[end]))
4656                         break;
4657
4658                 if (++end == info->rbuf_count)
4659                         end = 0;
4660
4661                 if (end == info->rbuf_current) {
4662                         if (info->rx_enabled){
4663                                 spin_lock_irqsave(&info->lock,flags);
4664                                 rx_start(info);
4665                                 spin_unlock_irqrestore(&info->lock,flags);
4666                         }
4667                         goto cleanup;
4668                 }
4669         }
4670
4671         /* status
4672          *
4673          * 15      buffer complete
4674          * 14..06  reserved
4675          * 05..04  residue
4676          * 02      eof (end of frame)
4677          * 01      CRC error
4678          * 00      abort
4679          */
4680         status = desc_status(info->rbufs[end]);
4681
4682         /* ignore CRC bit if not using CRC (bit is undefined) */
4683         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4684                 status &= ~BIT1;
4685
4686         if (framesize == 0 ||
4687                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4688                 free_rbufs(info, start, end);
4689                 goto check_again;
4690         }
4691
4692         if (framesize < (2 + crc_size) || status & BIT0) {
4693                 info->icount.rxshort++;
4694                 framesize = 0;
4695         } else if (status & BIT1) {
4696                 info->icount.rxcrc++;
4697                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4698                         framesize = 0;
4699         }
4700
4701 #if SYNCLINK_GENERIC_HDLC
4702         if (framesize == 0) {
4703                 info->netdev->stats.rx_errors++;
4704                 info->netdev->stats.rx_frame_errors++;
4705         }
4706 #endif
4707
4708         DBGBH(("%s rx frame status=%04X size=%d\n",
4709                 info->device_name, status, framesize));
4710         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4711
4712         if (framesize) {
4713                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4714                         framesize -= crc_size;
4715                         crc_size = 0;
4716                 }
4717
4718                 if (framesize > info->max_frame_size + crc_size)
4719                         info->icount.rxlong++;
4720                 else {
4721                         /* copy dma buffer(s) to contiguous temp buffer */
4722                         int copy_count = framesize;
4723                         int i = start;
4724                         unsigned char *p = info->tmp_rbuf;
4725                         info->tmp_rbuf_count = framesize;
4726
4727                         info->icount.rxok++;
4728
4729                         while(copy_count) {
4730                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4731                                 memcpy(p, info->rbufs[i].buf, partial_count);
4732                                 p += partial_count;
4733                                 copy_count -= partial_count;
4734                                 if (++i == info->rbuf_count)
4735                                         i = 0;
4736                         }
4737
4738                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4739                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4740                                 framesize++;
4741                         }
4742
4743 #if SYNCLINK_GENERIC_HDLC
4744                         if (info->netcount)
4745                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4746                         else
4747 #endif
4748                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4749                 }
4750         }
4751         free_rbufs(info, start, end);
4752         return true;
4753
4754 cleanup:
4755         return false;
4756 }
4757
4758 /*
4759  * pass receive buffer (RAW synchronous mode) to tty layer
4760  * return true if buffer available, otherwise false
4761  */
4762 static bool rx_get_buf(struct slgt_info *info)
4763 {
4764         unsigned int i = info->rbuf_current;
4765         unsigned int count;
4766
4767         if (!desc_complete(info->rbufs[i]))
4768                 return false;
4769         count = desc_count(info->rbufs[i]);
4770         switch(info->params.mode) {
4771         case MGSL_MODE_MONOSYNC:
4772         case MGSL_MODE_BISYNC:
4773         case MGSL_MODE_XSYNC:
4774                 /* ignore residue in byte synchronous modes */
4775                 if (desc_residue(info->rbufs[i]))
4776                         count--;
4777                 break;
4778         }
4779         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4780         DBGINFO(("rx_get_buf size=%d\n", count));
4781         if (count)
4782                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4783                                   info->flag_buf, count);
4784         free_rbufs(info, i, i);
4785         return true;
4786 }
4787
4788 static void reset_tbufs(struct slgt_info *info)
4789 {
4790         unsigned int i;
4791         info->tbuf_current = 0;
4792         for (i=0 ; i < info->tbuf_count ; i++) {
4793                 info->tbufs[i].status = 0;
4794                 info->tbufs[i].count  = 0;
4795         }
4796 }
4797
4798 /*
4799  * return number of free transmit DMA buffers
4800  */
4801 static unsigned int free_tbuf_count(struct slgt_info *info)
4802 {
4803         unsigned int count = 0;
4804         unsigned int i = info->tbuf_current;
4805
4806         do
4807         {
4808                 if (desc_count(info->tbufs[i]))
4809                         break; /* buffer in use */
4810                 ++count;
4811                 if (++i == info->tbuf_count)
4812                         i=0;
4813         } while (i != info->tbuf_current);
4814
4815         /* if tx DMA active, last zero count buffer is in use */
4816         if (count && (rd_reg32(info, TDCSR) & BIT0))
4817                 --count;
4818
4819         return count;
4820 }
4821
4822 /*
4823  * return number of bytes in unsent transmit DMA buffers
4824  * and the serial controller tx FIFO
4825  */
4826 static unsigned int tbuf_bytes(struct slgt_info *info)
4827 {
4828         unsigned int total_count = 0;
4829         unsigned int i = info->tbuf_current;
4830         unsigned int reg_value;
4831         unsigned int count;
4832         unsigned int active_buf_count = 0;
4833
4834         /*
4835          * Add descriptor counts for all tx DMA buffers.
4836          * If count is zero (cleared by DMA controller after read),
4837          * the buffer is complete or is actively being read from.
4838          *
4839          * Record buf_count of last buffer with zero count starting
4840          * from current ring position. buf_count is mirror
4841          * copy of count and is not cleared by serial controller.
4842          * If DMA controller is active, that buffer is actively
4843          * being read so add to total.
4844          */
4845         do {
4846                 count = desc_count(info->tbufs[i]);
4847                 if (count)
4848                         total_count += count;
4849                 else if (!total_count)
4850                         active_buf_count = info->tbufs[i].buf_count;
4851                 if (++i == info->tbuf_count)
4852                         i = 0;
4853         } while (i != info->tbuf_current);
4854
4855         /* read tx DMA status register */
4856         reg_value = rd_reg32(info, TDCSR);
4857
4858         /* if tx DMA active, last zero count buffer is in use */
4859         if (reg_value & BIT0)
4860                 total_count += active_buf_count;
4861
4862         /* add tx FIFO count = reg_value[15..8] */
4863         total_count += (reg_value >> 8) & 0xff;
4864
4865         /* if transmitter active add one byte for shift register */
4866         if (info->tx_active)
4867                 total_count++;
4868
4869         return total_count;
4870 }
4871
4872 /*
4873  * load data into transmit DMA buffer ring and start transmitter if needed
4874  * return true if data accepted, otherwise false (buffers full)
4875  */
4876 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4877 {
4878         unsigned short count;
4879         unsigned int i;
4880         struct slgt_desc *d;
4881
4882         /* check required buffer space */
4883         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4884                 return false;
4885
4886         DBGDATA(info, buf, size, "tx");
4887
4888         /*
4889          * copy data to one or more DMA buffers in circular ring
4890          * tbuf_start   = first buffer for this data
4891          * tbuf_current = next free buffer
4892          *
4893          * Copy all data before making data visible to DMA controller by
4894          * setting descriptor count of the first buffer.
4895          * This prevents an active DMA controller from reading the first DMA
4896          * buffers of a frame and stopping before the final buffers are filled.
4897          */
4898
4899         info->tbuf_start = i = info->tbuf_current;
4900
4901         while (size) {
4902                 d = &info->tbufs[i];
4903
4904                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4905                 memcpy(d->buf, buf, count);
4906
4907                 size -= count;
4908                 buf  += count;
4909
4910                 /*
4911                  * set EOF bit for last buffer of HDLC frame or
4912                  * for every buffer in raw mode
4913                  */
4914                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4915                     info->params.mode == MGSL_MODE_RAW)
4916                         set_desc_eof(*d, 1);
4917                 else
4918                         set_desc_eof(*d, 0);
4919
4920                 /* set descriptor count for all but first buffer */
4921                 if (i != info->tbuf_start)
4922                         set_desc_count(*d, count);
4923                 d->buf_count = count;
4924
4925                 if (++i == info->tbuf_count)
4926                         i = 0;
4927         }
4928
4929         info->tbuf_current = i;
4930
4931         /* set first buffer count to make new data visible to DMA controller */
4932         d = &info->tbufs[info->tbuf_start];
4933         set_desc_count(*d, d->buf_count);
4934
4935         /* start transmitter if needed and update transmit timeout */
4936         if (!info->tx_active)
4937                 tx_start(info);
4938         update_tx_timer(info);
4939
4940         return true;
4941 }
4942
4943 static int register_test(struct slgt_info *info)
4944 {
4945         static unsigned short patterns[] =
4946                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4947         static unsigned int count = ARRAY_SIZE(patterns);
4948         unsigned int i;
4949         int rc = 0;
4950
4951         for (i=0 ; i < count ; i++) {
4952                 wr_reg16(info, TIR, patterns[i]);
4953                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4954                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4955                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4956                         rc = -ENODEV;
4957                         break;
4958                 }
4959         }
4960         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4961         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4962         return rc;
4963 }
4964
4965 static int irq_test(struct slgt_info *info)
4966 {
4967         unsigned long timeout;
4968         unsigned long flags;
4969         struct tty_struct *oldtty = info->port.tty;
4970         u32 speed = info->params.data_rate;
4971
4972         info->params.data_rate = 921600;
4973         info->port.tty = NULL;
4974
4975         spin_lock_irqsave(&info->lock, flags);
4976         async_mode(info);
4977         slgt_irq_on(info, IRQ_TXIDLE);
4978
4979         /* enable transmitter */
4980         wr_reg16(info, TCR,
4981                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4982
4983         /* write one byte and wait for tx idle */
4984         wr_reg16(info, TDR, 0);
4985
4986         /* assume failure */
4987         info->init_error = DiagStatus_IrqFailure;
4988         info->irq_occurred = false;
4989
4990         spin_unlock_irqrestore(&info->lock, flags);
4991
4992         timeout=100;
4993         while(timeout-- && !info->irq_occurred)
4994                 msleep_interruptible(10);
4995
4996         spin_lock_irqsave(&info->lock,flags);
4997         reset_port(info);
4998         spin_unlock_irqrestore(&info->lock,flags);
4999
5000         info->params.data_rate = speed;
5001         info->port.tty = oldtty;
5002
5003         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5004         return info->irq_occurred ? 0 : -ENODEV;
5005 }
5006
5007 static int loopback_test_rx(struct slgt_info *info)
5008 {
5009         unsigned char *src, *dest;
5010         int count;
5011
5012         if (desc_complete(info->rbufs[0])) {
5013                 count = desc_count(info->rbufs[0]);
5014                 src   = info->rbufs[0].buf;
5015                 dest  = info->tmp_rbuf;
5016
5017                 for( ; count ; count-=2, src+=2) {
5018                         /* src=data byte (src+1)=status byte */
5019                         if (!(*(src+1) & (BIT9 + BIT8))) {
5020                                 *dest = *src;
5021                                 dest++;
5022                                 info->tmp_rbuf_count++;
5023                         }
5024                 }
5025                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5026                 return 1;
5027         }
5028         return 0;
5029 }
5030
5031 static int loopback_test(struct slgt_info *info)
5032 {
5033 #define TESTFRAMESIZE 20
5034
5035         unsigned long timeout;
5036         u16 count = TESTFRAMESIZE;
5037         unsigned char buf[TESTFRAMESIZE];
5038         int rc = -ENODEV;
5039         unsigned long flags;
5040
5041         struct tty_struct *oldtty = info->port.tty;
5042         MGSL_PARAMS params;
5043
5044         memcpy(&params, &info->params, sizeof(params));
5045
5046         info->params.mode = MGSL_MODE_ASYNC;
5047         info->params.data_rate = 921600;
5048         info->params.loopback = 1;
5049         info->port.tty = NULL;
5050
5051         /* build and send transmit frame */
5052         for (count = 0; count < TESTFRAMESIZE; ++count)
5053                 buf[count] = (unsigned char)count;
5054
5055         info->tmp_rbuf_count = 0;
5056         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5057
5058         /* program hardware for HDLC and enabled receiver */
5059         spin_lock_irqsave(&info->lock,flags);
5060         async_mode(info);
5061         rx_start(info);
5062         tx_load(info, buf, count);
5063         spin_unlock_irqrestore(&info->lock, flags);
5064
5065         /* wait for receive complete */
5066         for (timeout = 100; timeout; --timeout) {
5067                 msleep_interruptible(10);
5068                 if (loopback_test_rx(info)) {
5069                         rc = 0;
5070                         break;
5071                 }
5072         }
5073
5074         /* verify received frame length and contents */
5075         if (!rc && (info->tmp_rbuf_count != count ||
5076                   memcmp(buf, info->tmp_rbuf, count))) {
5077                 rc = -ENODEV;
5078         }
5079
5080         spin_lock_irqsave(&info->lock,flags);
5081         reset_adapter(info);
5082         spin_unlock_irqrestore(&info->lock,flags);
5083
5084         memcpy(&info->params, &params, sizeof(info->params));
5085         info->port.tty = oldtty;
5086
5087         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5088         return rc;
5089 }
5090
5091 static int adapter_test(struct slgt_info *info)
5092 {
5093         DBGINFO(("testing %s\n", info->device_name));
5094         if (register_test(info) < 0) {
5095                 printk("register test failure %s addr=%08X\n",
5096                         info->device_name, info->phys_reg_addr);
5097         } else if (irq_test(info) < 0) {
5098                 printk("IRQ test failure %s IRQ=%d\n",
5099                         info->device_name, info->irq_level);
5100         } else if (loopback_test(info) < 0) {
5101                 printk("loopback test failure %s\n", info->device_name);
5102         }
5103         return info->init_error;
5104 }
5105
5106 /*
5107  * transmit timeout handler
5108  */
5109 static void tx_timeout(unsigned long context)
5110 {
5111         struct slgt_info *info = (struct slgt_info*)context;
5112         unsigned long flags;
5113
5114         DBGINFO(("%s tx_timeout\n", info->device_name));
5115         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5116                 info->icount.txtimeout++;
5117         }
5118         spin_lock_irqsave(&info->lock,flags);
5119         tx_stop(info);
5120         spin_unlock_irqrestore(&info->lock,flags);
5121
5122 #if SYNCLINK_GENERIC_HDLC
5123         if (info->netcount)
5124                 hdlcdev_tx_done(info);
5125         else
5126 #endif
5127                 bh_transmit(info);
5128 }
5129
5130 /*
5131  * receive buffer polling timer
5132  */
5133 static void rx_timeout(unsigned long context)
5134 {
5135         struct slgt_info *info = (struct slgt_info*)context;
5136         unsigned long flags;
5137
5138         DBGINFO(("%s rx_timeout\n", info->device_name));
5139         spin_lock_irqsave(&info->lock, flags);
5140         info->pending_bh |= BH_RECEIVE;
5141         spin_unlock_irqrestore(&info->lock, flags);
5142         bh_handler(&info->task);
5143 }
5144