drivers/tty/synclink_gt.c

   1 // SPDX-License-Identifier: GPL-1.0+
   2 /*
   3  * Device driver for Microgate SyncLink GT serial adapters.
   4  *
   5  * written by Paul Fulghum for Microgate Corporation
   6  * paulkf@microgate.com
   7  *
   8  * Microgate and SyncLink are trademarks of Microgate Corporation
   9  *
  10  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  11  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  12  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  13  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  14  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  15  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  16  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  17  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  18  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  19  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  20  * OF THE POSSIBILITY OF SUCH DAMAGE.
  21  */
  22
  23 /*
  24  * DEBUG OUTPUT DEFINITIONS
  25  *
  26  * uncomment lines below to enable specific types of debug output
  27  *
  28  * DBGINFO   information - most verbose output
  29  * DBGERR    serious errors
  30  * DBGBH     bottom half service routine debugging
  31  * DBGISR    interrupt service routine debugging
  32  * DBGDATA   output receive and transmit data
  33  * DBGTBUF   output transmit DMA buffers and registers
  34  * DBGRBUF   output receive DMA buffers and registers
  35  */
  36
  37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  42 /*#define DBGTBUF(info) dump_tbufs(info)*/
  43 /*#define DBGRBUF(info) dump_rbufs(info)*/
  44
  45
  46 #include <linux/module.h>
  47 #include <linux/errno.h>
  48 #include <linux/signal.h>
  49 #include <linux/sched.h>
  50 #include <linux/timer.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/pci.h>
  53 #include <linux/tty.h>
  54 #include <linux/tty_flip.h>
  55 #include <linux/serial.h>
  56 #include <linux/major.h>
  57 #include <linux/string.h>
  58 #include <linux/fcntl.h>
  59 #include <linux/ptrace.h>
  60 #include <linux/ioport.h>
  61 #include <linux/mm.h>
  62 #include <linux/seq_file.h>
  63 #include <linux/slab.h>
  64 #include <linux/netdevice.h>
  65 #include <linux/vmalloc.h>
  66 #include <linux/init.h>
  67 #include <linux/delay.h>
  68 #include <linux/ioctl.h>
  69 #include <linux/termios.h>
  70 #include <linux/bitops.h>
  71 #include <linux/workqueue.h>
  72 #include <linux/hdlc.h>
  73 #include <linux/synclink.h>
  74
  75 #include <asm/io.h>
  76 #include <asm/irq.h>
  77 #include <asm/dma.h>
  78 #include <asm/types.h>
  79 #include <linux/uaccess.h>
  80
  81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  82 #define SYNCLINK_GENERIC_HDLC 1
  83 #else
  84 #define SYNCLINK_GENERIC_HDLC 0
  85 #endif
  86
  87 /*
  88  * module identification
  89  */
  90 static char *driver_name     = "SyncLink GT";
  91 static char *slgt_driver_name = "synclink_gt";
  92 static char *tty_dev_prefix  = "ttySLG";
  93 MODULE_LICENSE("GPL");
  94 #define MGSL_MAGIC 0x5401
  95 #define MAX_DEVICES 32
  96
  97 static const struct pci_device_id pci_table[] = {
  98         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
  99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {0,}, /* terminate list */
 103 };
 104 MODULE_DEVICE_TABLE(pci, pci_table);
 105
 106 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 107 static void remove_one(struct pci_dev *dev);
 108 static struct pci_driver pci_driver = {
 109         .name           = "synclink_gt",
 110         .id_table       = pci_table,
 111         .probe          = init_one,
 112         .remove         = remove_one,
 113 };
 114
 115 static bool pci_registered;
 116
 117 /*
 118  * module configuration and status
 119  */
 120 static struct slgt_info *slgt_device_list;
 121 static int slgt_device_count;
 122
 123 static int ttymajor;
 124 static int debug_level;
 125 static int maxframe[MAX_DEVICES];
 126
 127 module_param(ttymajor, int, 0);
 128 module_param(debug_level, int, 0);
 129 module_param_array(maxframe, int, NULL, 0);
 130
 131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 134
 135 /*
 136  * tty support and callbacks
 137  */
 138 static struct tty_driver *serial_driver;
 139
 140 static void wait_until_sent(struct tty_struct *tty, int timeout);
 141 static void flush_buffer(struct tty_struct *tty);
 142 static void tx_release(struct tty_struct *tty);
 143
 144 /*
 145  * generic HDLC support
 146  */
 147 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 148
 149
 150 /*
 151  * device specific structures, macros and functions
 152  */
 153
 154 #define SLGT_MAX_PORTS 4
 155 #define SLGT_REG_SIZE  256
 156
 157 /*
 158  * conditional wait facility
 159  */
 160 struct cond_wait {
 161         struct cond_wait *next;
 162         wait_queue_head_t q;
 163         wait_queue_entry_t wait;
 164         unsigned int data;
 165 };
 166 static void flush_cond_wait(struct cond_wait **head);
 167
 168 /*
 169  * DMA buffer descriptor and access macros
 170  */
 171 struct slgt_desc
 172 {
 173         __le16 count;
 174         __le16 status;
 175         __le32 pbuf;  /* physical address of data buffer */
 176         __le32 next;  /* physical address of next descriptor */
 177
 178         /* driver book keeping */
 179         char *buf;          /* virtual  address of data buffer */
 180         unsigned int pdesc; /* physical address of this descriptor */
 181         dma_addr_t buf_dma_addr;
 182         unsigned short buf_count;
 183 };
 184
 185 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 186 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 187 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 188 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 189 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 190 #define desc_count(a)      (le16_to_cpu((a).count))
 191 #define desc_status(a)     (le16_to_cpu((a).status))
 192 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 193 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 194 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 195 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 196 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 197
 198 struct _input_signal_events {
 199         int ri_up;
 200         int ri_down;
 201         int dsr_up;
 202         int dsr_down;
 203         int dcd_up;
 204         int dcd_down;
 205         int cts_up;
 206         int cts_down;
 207 };
 208
 209 /*
 210  * device instance data structure
 211  */
 212 struct slgt_info {
 213         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 214         struct tty_port port;
 215
 216         struct slgt_info *next_device;  /* device list link */
 217
 218         int magic;
 219
 220         char device_name[25];
 221         struct pci_dev *pdev;
 222
 223         int port_count;  /* count of ports on adapter */
 224         int adapter_num; /* adapter instance number */
 225         int port_num;    /* port instance number */
 226
 227         /* array of pointers to port contexts on this adapter */
 228         struct slgt_info *port_array[SLGT_MAX_PORTS];
 229
 230         int                     line;           /* tty line instance number */
 231
 232         struct mgsl_icount      icount;
 233
 234         int                     timeout;
 235         int                     x_char;         /* xon/xoff character */
 236         unsigned int            read_status_mask;
 237         unsigned int            ignore_status_mask;
 238
 239         wait_queue_head_t       status_event_wait_q;
 240         wait_queue_head_t       event_wait_q;
 241         struct timer_list       tx_timer;
 242         struct timer_list       rx_timer;
 243
 244         unsigned int            gpio_present;
 245         struct cond_wait        *gpio_wait_q;
 246
 247         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 248
 249         struct work_struct task;
 250         u32 pending_bh;
 251         bool bh_requested;
 252         bool bh_running;
 253
 254         int isr_overflow;
 255         bool irq_requested;     /* true if IRQ requested */
 256         bool irq_occurred;      /* for diagnostics use */
 257
 258         /* device configuration */
 259
 260         unsigned int bus_type;
 261         unsigned int irq_level;
 262         unsigned long irq_flags;
 263
 264         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 265         u32 phys_reg_addr;
 266         bool reg_addr_requested;
 267
 268         MGSL_PARAMS params;       /* communications parameters */
 269         u32 idle_mode;
 270         u32 max_frame_size;       /* as set by device config */
 271
 272         unsigned int rbuf_fill_level;
 273         unsigned int rx_pio;
 274         unsigned int if_mode;
 275         unsigned int base_clock;
 276         unsigned int xsync;
 277         unsigned int xctrl;
 278
 279         /* device status */
 280
 281         bool rx_enabled;
 282         bool rx_restart;
 283
 284         bool tx_enabled;
 285         bool tx_active;
 286
 287         unsigned char signals;    /* serial signal states */
 288         int init_error;  /* initialization error */
 289
 290         unsigned char *tx_buf;
 291         int tx_count;
 292
 293         char *flag_buf;
 294         bool drop_rts_on_tx_done;
 295         struct  _input_signal_events    input_signal_events;
 296
 297         int dcd_chkcount;       /* check counts to prevent */
 298         int cts_chkcount;       /* too many IRQs if a signal */
 299         int dsr_chkcount;       /* is floating */
 300         int ri_chkcount;
 301
 302         char *bufs;             /* virtual address of DMA buffer lists */
 303         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 304
 305         unsigned int rbuf_count;
 306         struct slgt_desc *rbufs;
 307         unsigned int rbuf_current;
 308         unsigned int rbuf_index;
 309         unsigned int rbuf_fill_index;
 310         unsigned short rbuf_fill_count;
 311
 312         unsigned int tbuf_count;
 313         struct slgt_desc *tbufs;
 314         unsigned int tbuf_current;
 315         unsigned int tbuf_start;
 316
 317         unsigned char *tmp_rbuf;
 318         unsigned int tmp_rbuf_count;
 319
 320         /* SPPP/Cisco HDLC device parts */
 321
 322         int netcount;
 323         spinlock_t netlock;
 324 #if SYNCLINK_GENERIC_HDLC
 325         struct net_device *netdev;
 326 #endif
 327
 328 };
 329
 330 static MGSL_PARAMS default_params = {
 331         .mode            = MGSL_MODE_HDLC,
 332         .loopback        = 0,
 333         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 334         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 335         .clock_speed     = 0,
 336         .addr_filter     = 0xff,
 337         .crc_type        = HDLC_CRC_16_CCITT,
 338         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 339         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 340         .data_rate       = 9600,
 341         .data_bits       = 8,
 342         .stop_bits       = 1,
 343         .parity          = ASYNC_PARITY_NONE
 344 };
 345
 346
 347 #define BH_RECEIVE  1
 348 #define BH_TRANSMIT 2
 349 #define BH_STATUS   4
 350 #define IO_PIN_SHUTDOWN_LIMIT 100
 351
 352 #define DMABUFSIZE 256
 353 #define DESC_LIST_SIZE 4096
 354
 355 #define MASK_PARITY  BIT1
 356 #define MASK_FRAMING BIT0
 357 #define MASK_BREAK   BIT14
 358 #define MASK_OVERRUN BIT4
 359
 360 #define GSR   0x00 /* global status */
 361 #define JCR   0x04 /* JTAG control */
 362 #define IODR  0x08 /* GPIO direction */
 363 #define IOER  0x0c /* GPIO interrupt enable */
 364 #define IOVR  0x10 /* GPIO value */
 365 #define IOSR  0x14 /* GPIO interrupt status */
 366 #define TDR   0x80 /* tx data */
 367 #define RDR   0x80 /* rx data */
 368 #define TCR   0x82 /* tx control */
 369 #define TIR   0x84 /* tx idle */
 370 #define TPR   0x85 /* tx preamble */
 371 #define RCR   0x86 /* rx control */
 372 #define VCR   0x88 /* V.24 control */
 373 #define CCR   0x89 /* clock control */
 374 #define BDR   0x8a /* baud divisor */
 375 #define SCR   0x8c /* serial control */
 376 #define SSR   0x8e /* serial status */
 377 #define RDCSR 0x90 /* rx DMA control/status */
 378 #define TDCSR 0x94 /* tx DMA control/status */
 379 #define RDDAR 0x98 /* rx DMA descriptor address */
 380 #define TDDAR 0x9c /* tx DMA descriptor address */
 381 #define XSR   0x40 /* extended sync pattern */
 382 #define XCR   0x44 /* extended control */
 383
 384 #define RXIDLE      BIT14
 385 #define RXBREAK     BIT14
 386 #define IRQ_TXDATA  BIT13
 387 #define IRQ_TXIDLE  BIT12
 388 #define IRQ_TXUNDER BIT11 /* HDLC */
 389 #define IRQ_RXDATA  BIT10
 390 #define IRQ_RXIDLE  BIT9  /* HDLC */
 391 #define IRQ_RXBREAK BIT9  /* async */
 392 #define IRQ_RXOVER  BIT8
 393 #define IRQ_DSR     BIT7
 394 #define IRQ_CTS     BIT6
 395 #define IRQ_DCD     BIT5
 396 #define IRQ_RI      BIT4
 397 #define IRQ_ALL     0x3ff0
 398 #define IRQ_MASTER  BIT0
 399
 400 #define slgt_irq_on(info, mask) \
 401         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 402 #define slgt_irq_off(info, mask) \
 403         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 404
 405 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 406 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 407 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 408 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 409 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 410 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 411
 412 static void  msc_set_vcr(struct slgt_info *info);
 413
 414 static int  startup(struct slgt_info *info);
 415 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 416 static void shutdown(struct slgt_info *info);
 417 static void program_hw(struct slgt_info *info);
 418 static void change_params(struct slgt_info *info);
 419
 420 static int  adapter_test(struct slgt_info *info);
 421
 422 static void reset_port(struct slgt_info *info);
 423 static void async_mode(struct slgt_info *info);
 424 static void sync_mode(struct slgt_info *info);
 425
 426 static void rx_stop(struct slgt_info *info);
 427 static void rx_start(struct slgt_info *info);
 428 static void reset_rbufs(struct slgt_info *info);
 429 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 430 static bool rx_get_frame(struct slgt_info *info);
 431 static bool rx_get_buf(struct slgt_info *info);
 432
 433 static void tx_start(struct slgt_info *info);
 434 static void tx_stop(struct slgt_info *info);
 435 static void tx_set_idle(struct slgt_info *info);
 436 static unsigned int tbuf_bytes(struct slgt_info *info);
 437 static void reset_tbufs(struct slgt_info *info);
 438 static void tdma_reset(struct slgt_info *info);
 439 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 440
 441 static void get_signals(struct slgt_info *info);
 442 static void set_signals(struct slgt_info *info);
 443 static void set_rate(struct slgt_info *info, u32 data_rate);
 444
 445 static void bh_transmit(struct slgt_info *info);
 446 static void isr_txeom(struct slgt_info *info, unsigned short status);
 447
 448 static void tx_timeout(struct timer_list *t);
 449 static void rx_timeout(struct timer_list *t);
 450
 451 /*
 452  * ioctl handlers
 453  */
 454 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 455 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 456 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 457 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 458 static int  set_txidle(struct slgt_info *info, int idle_mode);
 459 static int  tx_enable(struct slgt_info *info, int enable);
 460 static int  tx_abort(struct slgt_info *info);
 461 static int  rx_enable(struct slgt_info *info, int enable);
 462 static int  modem_input_wait(struct slgt_info *info,int arg);
 463 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 464 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 465 static int  set_interface(struct slgt_info *info, int if_mode);
 466 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 467 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 468 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 469 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 470 static int  set_xsync(struct slgt_info *info, int if_mode);
 471 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 472 static int  set_xctrl(struct slgt_info *info, int if_mode);
 473
 474 /*
 475  * driver functions
 476  */
 477 static void release_resources(struct slgt_info *info);
 478
 479 /*
 480  * DEBUG OUTPUT CODE
 481  */
 482 #ifndef DBGINFO
 483 #define DBGINFO(fmt)
 484 #endif
 485 #ifndef DBGERR
 486 #define DBGERR(fmt)
 487 #endif
 488 #ifndef DBGBH
 489 #define DBGBH(fmt)
 490 #endif
 491 #ifndef DBGISR
 492 #define DBGISR(fmt)
 493 #endif
 494
 495 #ifdef DBGDATA
 496 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 497 {
 498         int i;
 499         int linecount;
 500         printk("%s %s data:\n",info->device_name, label);
 501         while(count) {
 502                 linecount = (count > 16) ? 16 : count;
 503                 for(i=0; i < linecount; i++)
 504                         printk("%02X ",(unsigned char)data[i]);
 505                 for(;i<17;i++)
 506                         printk("   ");
 507                 for(i=0;i<linecount;i++) {
 508                         if (data[i]>=040 && data[i]<=0176)
 509                                 printk("%c",data[i]);
 510                         else
 511                                 printk(".");
 512                 }
 513                 printk("\n");
 514                 data  += linecount;
 515                 count -= linecount;
 516         }
 517 }
 518 #else
 519 #define DBGDATA(info, buf, size, label)
 520 #endif
 521
 522 #ifdef DBGTBUF
 523 static void dump_tbufs(struct slgt_info *info)
 524 {
 525         int i;
 526         printk("tbuf_current=%d\n", info->tbuf_current);
 527         for (i=0 ; i < info->tbuf_count ; i++) {
 528                 printk("%d: count=%04X status=%04X\n",
 529                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 530         }
 531 }
 532 #else
 533 #define DBGTBUF(info)
 534 #endif
 535
 536 #ifdef DBGRBUF
 537 static void dump_rbufs(struct slgt_info *info)
 538 {
 539         int i;
 540         printk("rbuf_current=%d\n", info->rbuf_current);
 541         for (i=0 ; i < info->rbuf_count ; i++) {
 542                 printk("%d: count=%04X status=%04X\n",
 543                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 544         }
 545 }
 546 #else
 547 #define DBGRBUF(info)
 548 #endif
 549
 550 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 551 {
 552 #ifdef SANITY_CHECK
 553         if (!info) {
 554                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 555                 return 1;
 556         }
 557         if (info->magic != MGSL_MAGIC) {
 558                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 559                 return 1;
 560         }
 561 #else
 562         if (!info)
 563                 return 1;
 564 #endif
 565         return 0;
 566 }
 567
 568 /*
 569  * line discipline callback wrappers
 570  *
 571  * The wrappers maintain line discipline references
 572  * while calling into the line discipline.
 573  *
 574  * ldisc_receive_buf  - pass receive data to line discipline
 575  */
 576 static void ldisc_receive_buf(struct tty_struct *tty,
 577                               const __u8 *data, char *flags, int count)
 578 {
 579         struct tty_ldisc *ld;
 580         if (!tty)
 581                 return;
 582         ld = tty_ldisc_ref(tty);
 583         if (ld) {
 584                 if (ld->ops->receive_buf)
 585                         ld->ops->receive_buf(tty, data, flags, count);
 586                 tty_ldisc_deref(ld);
 587         }
 588 }
 589
 590 /* tty callbacks */
 591
 592 static int open(struct tty_struct *tty, struct file *filp)
 593 {
 594         struct slgt_info *info;
 595         int retval, line;
 596         unsigned long flags;
 597
 598         line = tty->index;
 599         if (line >= slgt_device_count) {
 600                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 601                 return -ENODEV;
 602         }
 603
 604         info = slgt_device_list;
 605         while(info && info->line != line)
 606                 info = info->next_device;
 607         if (sanity_check(info, tty->name, "open"))
 608                 return -ENODEV;
 609         if (info->init_error) {
 610                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 611                 return -ENODEV;
 612         }
 613
 614         tty->driver_data = info;
 615         info->port.tty = tty;
 616
 617         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 618
 619         mutex_lock(&info->port.mutex);
 620
 621         spin_lock_irqsave(&info->netlock, flags);
 622         if (info->netcount) {
 623                 retval = -EBUSY;
 624                 spin_unlock_irqrestore(&info->netlock, flags);
 625                 mutex_unlock(&info->port.mutex);
 626                 goto cleanup;
 627         }
 628         info->port.count++;
 629         spin_unlock_irqrestore(&info->netlock, flags);
 630
 631         if (info->port.count == 1) {
 632                 /* 1st open on this device, init hardware */
 633                 retval = startup(info);
 634                 if (retval < 0) {
 635                         mutex_unlock(&info->port.mutex);
 636                         goto cleanup;
 637                 }
 638         }
 639         mutex_unlock(&info->port.mutex);
 640         retval = block_til_ready(tty, filp, info);
 641         if (retval) {
 642                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 643                 goto cleanup;
 644         }
 645
 646         retval = 0;
 647
 648 cleanup:
 649         if (retval) {
 650                 if (tty->count == 1)
 651                         info->port.tty = NULL; /* tty layer will release tty struct */
 652                 if(info->port.count)
 653                         info->port.count--;
 654         }
 655
 656         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 657         return retval;
 658 }
 659
 660 static void close(struct tty_struct *tty, struct file *filp)
 661 {
 662         struct slgt_info *info = tty->driver_data;
 663
 664         if (sanity_check(info, tty->name, "close"))
 665                 return;
 666         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 667
 668         if (tty_port_close_start(&info->port, tty, filp) == 0)
 669                 goto cleanup;
 670
 671         mutex_lock(&info->port.mutex);
 672         if (tty_port_initialized(&info->port))
 673                 wait_until_sent(tty, info->timeout);
 674         flush_buffer(tty);
 675         tty_ldisc_flush(tty);
 676
 677         shutdown(info);
 678         mutex_unlock(&info->port.mutex);
 679
 680         tty_port_close_end(&info->port, tty);
 681         info->port.tty = NULL;
 682 cleanup:
 683         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 684 }
 685
 686 static void hangup(struct tty_struct *tty)
 687 {
 688         struct slgt_info *info = tty->driver_data;
 689         unsigned long flags;
 690
 691         if (sanity_check(info, tty->name, "hangup"))
 692                 return;
 693         DBGINFO(("%s hangup\n", info->device_name));
 694
 695         flush_buffer(tty);
 696
 697         mutex_lock(&info->port.mutex);
 698         shutdown(info);
 699
 700         spin_lock_irqsave(&info->port.lock, flags);
 701         info->port.count = 0;
 702         info->port.tty = NULL;
 703         spin_unlock_irqrestore(&info->port.lock, flags);
 704         tty_port_set_active(&info->port, 0);
 705         mutex_unlock(&info->port.mutex);
 706
 707         wake_up_interruptible(&info->port.open_wait);
 708 }
 709
 710 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 711 {
 712         struct slgt_info *info = tty->driver_data;
 713         unsigned long flags;
 714
 715         DBGINFO(("%s set_termios\n", tty->driver->name));
 716
 717         change_params(info);
 718
 719         /* Handle transition to B0 status */
 720         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 721                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 722                 spin_lock_irqsave(&info->lock,flags);
 723                 set_signals(info);
 724                 spin_unlock_irqrestore(&info->lock,flags);
 725         }
 726
 727         /* Handle transition away from B0 status */
 728         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 729                 info->signals |= SerialSignal_DTR;
 730                 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 731                         info->signals |= SerialSignal_RTS;
 732                 spin_lock_irqsave(&info->lock,flags);
 733                 set_signals(info);
 734                 spin_unlock_irqrestore(&info->lock,flags);
 735         }
 736
 737         /* Handle turning off CRTSCTS */
 738         if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
 739                 tty->hw_stopped = 0;
 740                 tx_release(tty);
 741         }
 742 }
 743
 744 static void update_tx_timer(struct slgt_info *info)
 745 {
 746         /*
 747          * use worst case speed of 1200bps to calculate transmit timeout
 748          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 749          */
 750         if (info->params.mode == MGSL_MODE_HDLC) {
 751                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 752                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 753         }
 754 }
 755
 756 static int write(struct tty_struct *tty,
 757                  const unsigned char *buf, int count)
 758 {
 759         int ret = 0;
 760         struct slgt_info *info = tty->driver_data;
 761         unsigned long flags;
 762
 763         if (sanity_check(info, tty->name, "write"))
 764                 return -EIO;
 765
 766         DBGINFO(("%s write count=%d\n", info->device_name, count));
 767
 768         if (!info->tx_buf || (count > info->max_frame_size))
 769                 return -EIO;
 770
 771         if (!count || tty->stopped || tty->hw_stopped)
 772                 return 0;
 773
 774         spin_lock_irqsave(&info->lock, flags);
 775
 776         if (info->tx_count) {
 777                 /* send accumulated data from send_char() */
 778                 if (!tx_load(info, info->tx_buf, info->tx_count))
 779                         goto cleanup;
 780                 info->tx_count = 0;
 781         }
 782
 783         if (tx_load(info, buf, count))
 784                 ret = count;
 785
 786 cleanup:
 787         spin_unlock_irqrestore(&info->lock, flags);
 788         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 789         return ret;
 790 }
 791
 792 static int put_char(struct tty_struct *tty, unsigned char ch)
 793 {
 794         struct slgt_info *info = tty->driver_data;
 795         unsigned long flags;
 796         int ret = 0;
 797
 798         if (sanity_check(info, tty->name, "put_char"))
 799                 return 0;
 800         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 801         if (!info->tx_buf)
 802                 return 0;
 803         spin_lock_irqsave(&info->lock,flags);
 804         if (info->tx_count < info->max_frame_size) {
 805                 info->tx_buf[info->tx_count++] = ch;
 806                 ret = 1;
 807         }
 808         spin_unlock_irqrestore(&info->lock,flags);
 809         return ret;
 810 }
 811
 812 static void send_xchar(struct tty_struct *tty, char ch)
 813 {
 814         struct slgt_info *info = tty->driver_data;
 815         unsigned long flags;
 816
 817         if (sanity_check(info, tty->name, "send_xchar"))
 818                 return;
 819         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 820         info->x_char = ch;
 821         if (ch) {
 822                 spin_lock_irqsave(&info->lock,flags);
 823                 if (!info->tx_enabled)
 824                         tx_start(info);
 825                 spin_unlock_irqrestore(&info->lock,flags);
 826         }
 827 }
 828
 829 static void wait_until_sent(struct tty_struct *tty, int timeout)
 830 {
 831         struct slgt_info *info = tty->driver_data;
 832         unsigned long orig_jiffies, char_time;
 833
 834         if (!info )
 835                 return;
 836         if (sanity_check(info, tty->name, "wait_until_sent"))
 837                 return;
 838         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 839         if (!tty_port_initialized(&info->port))
 840                 goto exit;
 841
 842         orig_jiffies = jiffies;
 843
 844         /* Set check interval to 1/5 of estimated time to
 845          * send a character, and make it at least 1. The check
 846          * interval should also be less than the timeout.
 847          * Note: use tight timings here to satisfy the NIST-PCTS.
 848          */
 849
 850         if (info->params.data_rate) {
 851                 char_time = info->timeout/(32 * 5);
 852                 if (!char_time)
 853                         char_time++;
 854         } else
 855                 char_time = 1;
 856
 857         if (timeout)
 858                 char_time = min_t(unsigned long, char_time, timeout);
 859
 860         while (info->tx_active) {
 861                 msleep_interruptible(jiffies_to_msecs(char_time));
 862                 if (signal_pending(current))
 863                         break;
 864                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 865                         break;
 866         }
 867 exit:
 868         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 869 }
 870
 871 static int write_room(struct tty_struct *tty)
 872 {
 873         struct slgt_info *info = tty->driver_data;
 874         int ret;
 875
 876         if (sanity_check(info, tty->name, "write_room"))
 877                 return 0;
 878         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 879         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 880         return ret;
 881 }
 882
 883 static void flush_chars(struct tty_struct *tty)
 884 {
 885         struct slgt_info *info = tty->driver_data;
 886         unsigned long flags;
 887
 888         if (sanity_check(info, tty->name, "flush_chars"))
 889                 return;
 890         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 891
 892         if (info->tx_count <= 0 || tty->stopped ||
 893             tty->hw_stopped || !info->tx_buf)
 894                 return;
 895
 896         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 897
 898         spin_lock_irqsave(&info->lock,flags);
 899         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 900                 info->tx_count = 0;
 901         spin_unlock_irqrestore(&info->lock,flags);
 902 }
 903
 904 static void flush_buffer(struct tty_struct *tty)
 905 {
 906         struct slgt_info *info = tty->driver_data;
 907         unsigned long flags;
 908
 909         if (sanity_check(info, tty->name, "flush_buffer"))
 910                 return;
 911         DBGINFO(("%s flush_buffer\n", info->device_name));
 912
 913         spin_lock_irqsave(&info->lock, flags);
 914         info->tx_count = 0;
 915         spin_unlock_irqrestore(&info->lock, flags);
 916
 917         tty_wakeup(tty);
 918 }
 919
 920 /*
 921  * throttle (stop) transmitter
 922  */
 923 static void tx_hold(struct tty_struct *tty)
 924 {
 925         struct slgt_info *info = tty->driver_data;
 926         unsigned long flags;
 927
 928         if (sanity_check(info, tty->name, "tx_hold"))
 929                 return;
 930         DBGINFO(("%s tx_hold\n", info->device_name));
 931         spin_lock_irqsave(&info->lock,flags);
 932         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 933                 tx_stop(info);
 934         spin_unlock_irqrestore(&info->lock,flags);
 935 }
 936
 937 /*
 938  * release (start) transmitter
 939  */
 940 static void tx_release(struct tty_struct *tty)
 941 {
 942         struct slgt_info *info = tty->driver_data;
 943         unsigned long flags;
 944
 945         if (sanity_check(info, tty->name, "tx_release"))
 946                 return;
 947         DBGINFO(("%s tx_release\n", info->device_name));
 948         spin_lock_irqsave(&info->lock, flags);
 949         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 950                 info->tx_count = 0;
 951         spin_unlock_irqrestore(&info->lock, flags);
 952 }
 953
 954 /*
 955  * Service an IOCTL request
 956  *
 957  * Arguments
 958  *
 959  *      tty     pointer to tty instance data
 960  *      cmd     IOCTL command code
 961  *      arg     command argument/context
 962  *
 963  * Return 0 if success, otherwise error code
 964  */
 965 static int ioctl(struct tty_struct *tty,
 966                  unsigned int cmd, unsigned long arg)
 967 {
 968         struct slgt_info *info = tty->driver_data;
 969         void __user *argp = (void __user *)arg;
 970         int ret;
 971
 972         if (sanity_check(info, tty->name, "ioctl"))
 973                 return -ENODEV;
 974         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
 975
 976         if (cmd != TIOCMIWAIT) {
 977                 if (tty_io_error(tty))
 978                     return -EIO;
 979         }
 980
 981         switch (cmd) {
 982         case MGSL_IOCWAITEVENT:
 983                 return wait_mgsl_event(info, argp);
 984         case TIOCMIWAIT:
 985                 return modem_input_wait(info,(int)arg);
 986         case MGSL_IOCSGPIO:
 987                 return set_gpio(info, argp);
 988         case MGSL_IOCGGPIO:
 989                 return get_gpio(info, argp);
 990         case MGSL_IOCWAITGPIO:
 991                 return wait_gpio(info, argp);
 992         case MGSL_IOCGXSYNC:
 993                 return get_xsync(info, argp);
 994         case MGSL_IOCSXSYNC:
 995                 return set_xsync(info, (int)arg);
 996         case MGSL_IOCGXCTRL:
 997                 return get_xctrl(info, argp);
 998         case MGSL_IOCSXCTRL:
 999                 return set_xctrl(info, (int)arg);
1000         }
1001         mutex_lock(&info->port.mutex);
1002         switch (cmd) {
1003         case MGSL_IOCGPARAMS:
1004                 ret = get_params(info, argp);
1005                 break;
1006         case MGSL_IOCSPARAMS:
1007                 ret = set_params(info, argp);
1008                 break;
1009         case MGSL_IOCGTXIDLE:
1010                 ret = get_txidle(info, argp);
1011                 break;
1012         case MGSL_IOCSTXIDLE:
1013                 ret = set_txidle(info, (int)arg);
1014                 break;
1015         case MGSL_IOCTXENABLE:
1016                 ret = tx_enable(info, (int)arg);
1017                 break;
1018         case MGSL_IOCRXENABLE:
1019                 ret = rx_enable(info, (int)arg);
1020                 break;
1021         case MGSL_IOCTXABORT:
1022                 ret = tx_abort(info);
1023                 break;
1024         case MGSL_IOCGSTATS:
1025                 ret = get_stats(info, argp);
1026                 break;
1027         case MGSL_IOCGIF:
1028                 ret = get_interface(info, argp);
1029                 break;
1030         case MGSL_IOCSIF:
1031                 ret = set_interface(info,(int)arg);
1032                 break;
1033         default:
1034                 ret = -ENOIOCTLCMD;
1035         }
1036         mutex_unlock(&info->port.mutex);
1037         return ret;
1038 }
1039
1040 static int get_icount(struct tty_struct *tty,
1041                                 struct serial_icounter_struct *icount)
1042
1043 {
1044         struct slgt_info *info = tty->driver_data;
1045         struct mgsl_icount cnow;        /* kernel counter temps */
1046         unsigned long flags;
1047
1048         spin_lock_irqsave(&info->lock,flags);
1049         cnow = info->icount;
1050         spin_unlock_irqrestore(&info->lock,flags);
1051
1052         icount->cts = cnow.cts;
1053         icount->dsr = cnow.dsr;
1054         icount->rng = cnow.rng;
1055         icount->dcd = cnow.dcd;
1056         icount->rx = cnow.rx;
1057         icount->tx = cnow.tx;
1058         icount->frame = cnow.frame;
1059         icount->overrun = cnow.overrun;
1060         icount->parity = cnow.parity;
1061         icount->brk = cnow.brk;
1062         icount->buf_overrun = cnow.buf_overrun;
1063
1064         return 0;
1065 }
1066
1067 /*
1068  * support for 32 bit ioctl calls on 64 bit systems
1069  */
1070 #ifdef CONFIG_COMPAT
1071 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1072 {
1073         struct MGSL_PARAMS32 tmp_params;
1074
1075         DBGINFO(("%s get_params32\n", info->device_name));
1076         memset(&tmp_params, 0, sizeof(tmp_params));
1077         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1078         tmp_params.loopback        = info->params.loopback;
1079         tmp_params.flags           = info->params.flags;
1080         tmp_params.encoding        = info->params.encoding;
1081         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1082         tmp_params.addr_filter     = info->params.addr_filter;
1083         tmp_params.crc_type        = info->params.crc_type;
1084         tmp_params.preamble_length = info->params.preamble_length;
1085         tmp_params.preamble        = info->params.preamble;
1086         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1087         tmp_params.data_bits       = info->params.data_bits;
1088         tmp_params.stop_bits       = info->params.stop_bits;
1089         tmp_params.parity          = info->params.parity;
1090         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1091                 return -EFAULT;
1092         return 0;
1093 }
1094
1095 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1096 {
1097         struct MGSL_PARAMS32 tmp_params;
1098
1099         DBGINFO(("%s set_params32\n", info->device_name));
1100         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1101                 return -EFAULT;
1102
1103         spin_lock(&info->lock);
1104         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1105                 info->base_clock = tmp_params.clock_speed;
1106         } else {
1107                 info->params.mode            = tmp_params.mode;
1108                 info->params.loopback        = tmp_params.loopback;
1109                 info->params.flags           = tmp_params.flags;
1110                 info->params.encoding        = tmp_params.encoding;
1111                 info->params.clock_speed     = tmp_params.clock_speed;
1112                 info->params.addr_filter     = tmp_params.addr_filter;
1113                 info->params.crc_type        = tmp_params.crc_type;
1114                 info->params.preamble_length = tmp_params.preamble_length;
1115                 info->params.preamble        = tmp_params.preamble;
1116                 info->params.data_rate       = tmp_params.data_rate;
1117                 info->params.data_bits       = tmp_params.data_bits;
1118                 info->params.stop_bits       = tmp_params.stop_bits;
1119                 info->params.parity          = tmp_params.parity;
1120         }
1121         spin_unlock(&info->lock);
1122
1123         program_hw(info);
1124
1125         return 0;
1126 }
1127
1128 static long slgt_compat_ioctl(struct tty_struct *tty,
1129                          unsigned int cmd, unsigned long arg)
1130 {
1131         struct slgt_info *info = tty->driver_data;
1132         int rc;
1133
1134         if (sanity_check(info, tty->name, "compat_ioctl"))
1135                 return -ENODEV;
1136         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1137
1138         switch (cmd) {
1139         case MGSL_IOCSPARAMS32:
1140                 rc = set_params32(info, compat_ptr(arg));
1141                 break;
1142
1143         case MGSL_IOCGPARAMS32:
1144                 rc = get_params32(info, compat_ptr(arg));
1145                 break;
1146
1147         case MGSL_IOCGPARAMS:
1148         case MGSL_IOCSPARAMS:
1149         case MGSL_IOCGTXIDLE:
1150         case MGSL_IOCGSTATS:
1151         case MGSL_IOCWAITEVENT:
1152         case MGSL_IOCGIF:
1153         case MGSL_IOCSGPIO:
1154         case MGSL_IOCGGPIO:
1155         case MGSL_IOCWAITGPIO:
1156         case MGSL_IOCGXSYNC:
1157         case MGSL_IOCGXCTRL:
1158                 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1159                 break;
1160         default:
1161                 rc = ioctl(tty, cmd, arg);
1162         }
1163         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1164         return rc;
1165 }
1166 #else
1167 #define slgt_compat_ioctl NULL
1168 #endif /* ifdef CONFIG_COMPAT */
1169
1170 /*
1171  * proc fs support
1172  */
1173 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1174 {
1175         char stat_buf[30];
1176         unsigned long flags;
1177
1178         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1179                       info->device_name, info->phys_reg_addr,
1180                       info->irq_level, info->max_frame_size);
1181
1182         /* output current serial signal states */
1183         spin_lock_irqsave(&info->lock,flags);
1184         get_signals(info);
1185         spin_unlock_irqrestore(&info->lock,flags);
1186
1187         stat_buf[0] = 0;
1188         stat_buf[1] = 0;
1189         if (info->signals & SerialSignal_RTS)
1190                 strcat(stat_buf, "|RTS");
1191         if (info->signals & SerialSignal_CTS)
1192                 strcat(stat_buf, "|CTS");
1193         if (info->signals & SerialSignal_DTR)
1194                 strcat(stat_buf, "|DTR");
1195         if (info->signals & SerialSignal_DSR)
1196                 strcat(stat_buf, "|DSR");
1197         if (info->signals & SerialSignal_DCD)
1198                 strcat(stat_buf, "|CD");
1199         if (info->signals & SerialSignal_RI)
1200                 strcat(stat_buf, "|RI");
1201
1202         if (info->params.mode != MGSL_MODE_ASYNC) {
1203                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1204                                info->icount.txok, info->icount.rxok);
1205                 if (info->icount.txunder)
1206                         seq_printf(m, " txunder:%d", info->icount.txunder);
1207                 if (info->icount.txabort)
1208                         seq_printf(m, " txabort:%d", info->icount.txabort);
1209                 if (info->icount.rxshort)
1210                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1211                 if (info->icount.rxlong)
1212                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1213                 if (info->icount.rxover)
1214                         seq_printf(m, " rxover:%d", info->icount.rxover);
1215                 if (info->icount.rxcrc)
1216                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1217         } else {
1218                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1219                                info->icount.tx, info->icount.rx);
1220                 if (info->icount.frame)
1221                         seq_printf(m, " fe:%d", info->icount.frame);
1222                 if (info->icount.parity)
1223                         seq_printf(m, " pe:%d", info->icount.parity);
1224                 if (info->icount.brk)
1225                         seq_printf(m, " brk:%d", info->icount.brk);
1226                 if (info->icount.overrun)
1227                         seq_printf(m, " oe:%d", info->icount.overrun);
1228         }
1229
1230         /* Append serial signal status to end */
1231         seq_printf(m, " %s\n", stat_buf+1);
1232
1233         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1234                        info->tx_active,info->bh_requested,info->bh_running,
1235                        info->pending_bh);
1236 }
1237
1238 /* Called to print information about devices
1239  */
1240 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1241 {
1242         struct slgt_info *info;
1243
1244         seq_puts(m, "synclink_gt driver\n");
1245
1246         info = slgt_device_list;
1247         while( info ) {
1248                 line_info(m, info);
1249                 info = info->next_device;
1250         }
1251         return 0;
1252 }
1253
1254 /*
1255  * return count of bytes in transmit buffer
1256  */
1257 static int chars_in_buffer(struct tty_struct *tty)
1258 {
1259         struct slgt_info *info = tty->driver_data;
1260         int count;
1261         if (sanity_check(info, tty->name, "chars_in_buffer"))
1262                 return 0;
1263         count = tbuf_bytes(info);
1264         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1265         return count;
1266 }
1267
1268 /*
1269  * signal remote device to throttle send data (our receive data)
1270  */
1271 static void throttle(struct tty_struct * tty)
1272 {
1273         struct slgt_info *info = tty->driver_data;
1274         unsigned long flags;
1275
1276         if (sanity_check(info, tty->name, "throttle"))
1277                 return;
1278         DBGINFO(("%s throttle\n", info->device_name));
1279         if (I_IXOFF(tty))
1280                 send_xchar(tty, STOP_CHAR(tty));
1281         if (C_CRTSCTS(tty)) {
1282                 spin_lock_irqsave(&info->lock,flags);
1283                 info->signals &= ~SerialSignal_RTS;
1284                 set_signals(info);
1285                 spin_unlock_irqrestore(&info->lock,flags);
1286         }
1287 }
1288
1289 /*
1290  * signal remote device to stop throttling send data (our receive data)
1291  */
1292 static void unthrottle(struct tty_struct * tty)
1293 {
1294         struct slgt_info *info = tty->driver_data;
1295         unsigned long flags;
1296
1297         if (sanity_check(info, tty->name, "unthrottle"))
1298                 return;
1299         DBGINFO(("%s unthrottle\n", info->device_name));
1300         if (I_IXOFF(tty)) {
1301                 if (info->x_char)
1302                         info->x_char = 0;
1303                 else
1304                         send_xchar(tty, START_CHAR(tty));
1305         }
1306         if (C_CRTSCTS(tty)) {
1307                 spin_lock_irqsave(&info->lock,flags);
1308                 info->signals |= SerialSignal_RTS;
1309                 set_signals(info);
1310                 spin_unlock_irqrestore(&info->lock,flags);
1311         }
1312 }
1313
1314 /*
1315  * set or clear transmit break condition
1316  * break_state  -1=set break condition, 0=clear
1317  */
1318 static int set_break(struct tty_struct *tty, int break_state)
1319 {
1320         struct slgt_info *info = tty->driver_data;
1321         unsigned short value;
1322         unsigned long flags;
1323
1324         if (sanity_check(info, tty->name, "set_break"))
1325                 return -EINVAL;
1326         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1327
1328         spin_lock_irqsave(&info->lock,flags);
1329         value = rd_reg16(info, TCR);
1330         if (break_state == -1)
1331                 value |= BIT6;
1332         else
1333                 value &= ~BIT6;
1334         wr_reg16(info, TCR, value);
1335         spin_unlock_irqrestore(&info->lock,flags);
1336         return 0;
1337 }
1338
1339 #if SYNCLINK_GENERIC_HDLC
1340
1341 /**
1342  * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1343  * @dev:      pointer to network device structure
1344  * @encoding: serial encoding setting
1345  * @parity:   FCS setting
1346  *
1347  * Set encoding and frame check sequence (FCS) options.
1348  *
1349  * Return: 0 if success, otherwise error code
1350  */
1351 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1352                           unsigned short parity)
1353 {
1354         struct slgt_info *info = dev_to_port(dev);
1355         unsigned char  new_encoding;
1356         unsigned short new_crctype;
1357
1358         /* return error if TTY interface open */
1359         if (info->port.count)
1360                 return -EBUSY;
1361
1362         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1363
1364         switch (encoding)
1365         {
1366         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1367         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1368         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1369         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1370         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1371         default: return -EINVAL;
1372         }
1373
1374         switch (parity)
1375         {
1376         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1377         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1378         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1379         default: return -EINVAL;
1380         }
1381
1382         info->params.encoding = new_encoding;
1383         info->params.crc_type = new_crctype;
1384
1385         /* if network interface up, reprogram hardware */
1386         if (info->netcount)
1387                 program_hw(info);
1388
1389         return 0;
1390 }
1391
1392 /**
1393  * hdlcdev_xmit - called by generic HDLC layer to send a frame
1394  * @skb: socket buffer containing HDLC frame
1395  * @dev: pointer to network device structure
1396  */
1397 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1398                                       struct net_device *dev)
1399 {
1400         struct slgt_info *info = dev_to_port(dev);
1401         unsigned long flags;
1402
1403         DBGINFO(("%s hdlc_xmit\n", dev->name));
1404
1405         if (!skb->len)
1406                 return NETDEV_TX_OK;
1407
1408         /* stop sending until this frame completes */
1409         netif_stop_queue(dev);
1410
1411         /* update network statistics */
1412         dev->stats.tx_packets++;
1413         dev->stats.tx_bytes += skb->len;
1414
1415         /* save start time for transmit timeout detection */
1416         netif_trans_update(dev);
1417
1418         spin_lock_irqsave(&info->lock, flags);
1419         tx_load(info, skb->data, skb->len);
1420         spin_unlock_irqrestore(&info->lock, flags);
1421
1422         /* done with socket buffer, so free it */
1423         dev_kfree_skb(skb);
1424
1425         return NETDEV_TX_OK;
1426 }
1427
1428 /**
1429  * hdlcdev_open - called by network layer when interface enabled
1430  * @dev: pointer to network device structure
1431  *
1432  * Claim resources and initialize hardware.
1433  *
1434  * Return: 0 if success, otherwise error code
1435  */
1436 static int hdlcdev_open(struct net_device *dev)
1437 {
1438         struct slgt_info *info = dev_to_port(dev);
1439         int rc;
1440         unsigned long flags;
1441
1442         if (!try_module_get(THIS_MODULE))
1443                 return -EBUSY;
1444
1445         DBGINFO(("%s hdlcdev_open\n", dev->name));
1446
1447         /* generic HDLC layer open processing */
1448         rc = hdlc_open(dev);
1449         if (rc)
1450                 return rc;
1451
1452         /* arbitrate between network and tty opens */
1453         spin_lock_irqsave(&info->netlock, flags);
1454         if (info->port.count != 0 || info->netcount != 0) {
1455                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1456                 spin_unlock_irqrestore(&info->netlock, flags);
1457                 return -EBUSY;
1458         }
1459         info->netcount=1;
1460         spin_unlock_irqrestore(&info->netlock, flags);
1461
1462         /* claim resources and init adapter */
1463         if ((rc = startup(info)) != 0) {
1464                 spin_lock_irqsave(&info->netlock, flags);
1465                 info->netcount=0;
1466                 spin_unlock_irqrestore(&info->netlock, flags);
1467                 return rc;
1468         }
1469
1470         /* assert RTS and DTR, apply hardware settings */
1471         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1472         program_hw(info);
1473
1474         /* enable network layer transmit */
1475         netif_trans_update(dev);
1476         netif_start_queue(dev);
1477
1478         /* inform generic HDLC layer of current DCD status */
1479         spin_lock_irqsave(&info->lock, flags);
1480         get_signals(info);
1481         spin_unlock_irqrestore(&info->lock, flags);
1482         if (info->signals & SerialSignal_DCD)
1483                 netif_carrier_on(dev);
1484         else
1485                 netif_carrier_off(dev);
1486         return 0;
1487 }
1488
1489 /**
1490  * hdlcdev_close - called by network layer when interface is disabled
1491  * @dev:  pointer to network device structure
1492  *
1493  * Shutdown hardware and release resources.
1494  *
1495  * Return: 0 if success, otherwise error code
1496  */
1497 static int hdlcdev_close(struct net_device *dev)
1498 {
1499         struct slgt_info *info = dev_to_port(dev);
1500         unsigned long flags;
1501
1502         DBGINFO(("%s hdlcdev_close\n", dev->name));
1503
1504         netif_stop_queue(dev);
1505
1506         /* shutdown adapter and release resources */
1507         shutdown(info);
1508
1509         hdlc_close(dev);
1510
1511         spin_lock_irqsave(&info->netlock, flags);
1512         info->netcount=0;
1513         spin_unlock_irqrestore(&info->netlock, flags);
1514
1515         module_put(THIS_MODULE);
1516         return 0;
1517 }
1518
1519 /**
1520  * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1521  * @dev: pointer to network device structure
1522  * @ifr: pointer to network interface request structure
1523  * @cmd: IOCTL command code
1524  *
1525  * Return: 0 if success, otherwise error code
1526  */
1527 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1528 {
1529         const size_t size = sizeof(sync_serial_settings);
1530         sync_serial_settings new_line;
1531         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1532         struct slgt_info *info = dev_to_port(dev);
1533         unsigned int flags;
1534
1535         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1536
1537         /* return error if TTY interface open */
1538         if (info->port.count)
1539                 return -EBUSY;
1540
1541         if (cmd != SIOCWANDEV)
1542                 return hdlc_ioctl(dev, ifr, cmd);
1543
1544         memset(&new_line, 0, sizeof(new_line));
1545
1546         switch(ifr->ifr_settings.type) {
1547         case IF_GET_IFACE: /* return current sync_serial_settings */
1548
1549                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1550                 if (ifr->ifr_settings.size < size) {
1551                         ifr->ifr_settings.size = size; /* data size wanted */
1552                         return -ENOBUFS;
1553                 }
1554
1555                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1556                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1557                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1558                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1559
1560                 switch (flags){
1561                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1562                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1563                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1564                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1565                 default: new_line.clock_type = CLOCK_DEFAULT;
1566                 }
1567
1568                 new_line.clock_rate = info->params.clock_speed;
1569                 new_line.loopback   = info->params.loopback ? 1:0;
1570
1571                 if (copy_to_user(line, &new_line, size))
1572                         return -EFAULT;
1573                 return 0;
1574
1575         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1576
1577                 if(!capable(CAP_NET_ADMIN))
1578                         return -EPERM;
1579                 if (copy_from_user(&new_line, line, size))
1580                         return -EFAULT;
1581
1582                 switch (new_line.clock_type)
1583                 {
1584                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1585                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1586                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1587                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1588                 case CLOCK_DEFAULT:  flags = info->params.flags &
1589                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1590                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1591                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1592                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1593                 default: return -EINVAL;
1594                 }
1595
1596                 if (new_line.loopback != 0 && new_line.loopback != 1)
1597                         return -EINVAL;
1598
1599                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1600                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1601                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1602                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1603                 info->params.flags |= flags;
1604
1605                 info->params.loopback = new_line.loopback;
1606
1607                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1608                         info->params.clock_speed = new_line.clock_rate;
1609                 else
1610                         info->params.clock_speed = 0;
1611
1612                 /* if network interface up, reprogram hardware */
1613                 if (info->netcount)
1614                         program_hw(info);
1615                 return 0;
1616
1617         default:
1618                 return hdlc_ioctl(dev, ifr, cmd);
1619         }
1620 }
1621
1622 /**
1623  * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1624  * @dev: pointer to network device structure
1625  * @txqueue: unused
1626  */
1627 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1628 {
1629         struct slgt_info *info = dev_to_port(dev);
1630         unsigned long flags;
1631
1632         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1633
1634         dev->stats.tx_errors++;
1635         dev->stats.tx_aborted_errors++;
1636
1637         spin_lock_irqsave(&info->lock,flags);
1638         tx_stop(info);
1639         spin_unlock_irqrestore(&info->lock,flags);
1640
1641         netif_wake_queue(dev);
1642 }
1643
1644 /**
1645  * hdlcdev_tx_done - called by device driver when transmit completes
1646  * @info: pointer to device instance information
1647  *
1648  * Reenable network layer transmit if stopped.
1649  */
1650 static void hdlcdev_tx_done(struct slgt_info *info)
1651 {
1652         if (netif_queue_stopped(info->netdev))
1653                 netif_wake_queue(info->netdev);
1654 }
1655
1656 /**
1657  * hdlcdev_rx - called by device driver when frame received
1658  * @info: pointer to device instance information
1659  * @buf:  pointer to buffer contianing frame data
1660  * @size: count of data bytes in buf
1661  *
1662  * Pass frame to network layer.
1663  */
1664 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1665 {
1666         struct sk_buff *skb = dev_alloc_skb(size);
1667         struct net_device *dev = info->netdev;
1668
1669         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1670
1671         if (skb == NULL) {
1672                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1673                 dev->stats.rx_dropped++;
1674                 return;
1675         }
1676
1677         skb_put_data(skb, buf, size);
1678
1679         skb->protocol = hdlc_type_trans(skb, dev);
1680
1681         dev->stats.rx_packets++;
1682         dev->stats.rx_bytes += size;
1683
1684         netif_rx(skb);
1685 }
1686
1687 static const struct net_device_ops hdlcdev_ops = {
1688         .ndo_open       = hdlcdev_open,
1689         .ndo_stop       = hdlcdev_close,
1690         .ndo_start_xmit = hdlc_start_xmit,
1691         .ndo_do_ioctl   = hdlcdev_ioctl,
1692         .ndo_tx_timeout = hdlcdev_tx_timeout,
1693 };
1694
1695 /**
1696  * hdlcdev_init - called by device driver when adding device instance
1697  * @info: pointer to device instance information
1698  *
1699  * Do generic HDLC initialization.
1700  *
1701  * Return: 0 if success, otherwise error code
1702  */
1703 static int hdlcdev_init(struct slgt_info *info)
1704 {
1705         int rc;
1706         struct net_device *dev;
1707         hdlc_device *hdlc;
1708
1709         /* allocate and initialize network and HDLC layer objects */
1710
1711         dev = alloc_hdlcdev(info);
1712         if (!dev) {
1713                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1714                 return -ENOMEM;
1715         }
1716
1717         /* for network layer reporting purposes only */
1718         dev->mem_start = info->phys_reg_addr;
1719         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1720         dev->irq       = info->irq_level;
1721
1722         /* network layer callbacks and settings */
1723         dev->netdev_ops     = &hdlcdev_ops;
1724         dev->watchdog_timeo = 10 * HZ;
1725         dev->tx_queue_len   = 50;
1726
1727         /* generic HDLC layer callbacks and settings */
1728         hdlc         = dev_to_hdlc(dev);
1729         hdlc->attach = hdlcdev_attach;
1730         hdlc->xmit   = hdlcdev_xmit;
1731
1732         /* register objects with HDLC layer */
1733         rc = register_hdlc_device(dev);
1734         if (rc) {
1735                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1736                 free_netdev(dev);
1737                 return rc;
1738         }
1739
1740         info->netdev = dev;
1741         return 0;
1742 }
1743
1744 /**
1745  * hdlcdev_exit - called by device driver when removing device instance
1746  * @info: pointer to device instance information
1747  *
1748  * Do generic HDLC cleanup.
1749  */
1750 static void hdlcdev_exit(struct slgt_info *info)
1751 {
1752         unregister_hdlc_device(info->netdev);
1753         free_netdev(info->netdev);
1754         info->netdev = NULL;
1755 }
1756
1757 #endif /* ifdef CONFIG_HDLC */
1758
1759 /*
1760  * get async data from rx DMA buffers
1761  */
1762 static void rx_async(struct slgt_info *info)
1763 {
1764         struct mgsl_icount *icount = &info->icount;
1765         unsigned int start, end;
1766         unsigned char *p;
1767         unsigned char status;
1768         struct slgt_desc *bufs = info->rbufs;
1769         int i, count;
1770         int chars = 0;
1771         int stat;
1772         unsigned char ch;
1773
1774         start = end = info->rbuf_current;
1775
1776         while(desc_complete(bufs[end])) {
1777                 count = desc_count(bufs[end]) - info->rbuf_index;
1778                 p     = bufs[end].buf + info->rbuf_index;
1779
1780                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1781                 DBGDATA(info, p, count, "rx");
1782
1783                 for(i=0 ; i < count; i+=2, p+=2) {
1784                         ch = *p;
1785                         icount->rx++;
1786
1787                         stat = 0;
1788
1789                         status = *(p + 1) & (BIT1 + BIT0);
1790                         if (status) {
1791                                 if (status & BIT1)
1792                                         icount->parity++;
1793                                 else if (status & BIT0)
1794                                         icount->frame++;
1795                                 /* discard char if tty control flags say so */
1796                                 if (status & info->ignore_status_mask)
1797                                         continue;
1798                                 if (status & BIT1)
1799                                         stat = TTY_PARITY;
1800                                 else if (status & BIT0)
1801                                         stat = TTY_FRAME;
1802                         }
1803                         tty_insert_flip_char(&info->port, ch, stat);
1804                         chars++;
1805                 }
1806
1807                 if (i < count) {
1808                         /* receive buffer not completed */
1809                         info->rbuf_index += i;
1810                         mod_timer(&info->rx_timer, jiffies + 1);
1811                         break;
1812                 }
1813
1814                 info->rbuf_index = 0;
1815                 free_rbufs(info, end, end);
1816
1817                 if (++end == info->rbuf_count)
1818                         end = 0;
1819
1820                 /* if entire list searched then no frame available */
1821                 if (end == start)
1822                         break;
1823         }
1824
1825         if (chars)
1826                 tty_flip_buffer_push(&info->port);
1827 }
1828
1829 /*
1830  * return next bottom half action to perform
1831  */
1832 static int bh_action(struct slgt_info *info)
1833 {
1834         unsigned long flags;
1835         int rc;
1836
1837         spin_lock_irqsave(&info->lock,flags);
1838
1839         if (info->pending_bh & BH_RECEIVE) {
1840                 info->pending_bh &= ~BH_RECEIVE;
1841                 rc = BH_RECEIVE;
1842         } else if (info->pending_bh & BH_TRANSMIT) {
1843                 info->pending_bh &= ~BH_TRANSMIT;
1844                 rc = BH_TRANSMIT;
1845         } else if (info->pending_bh & BH_STATUS) {
1846                 info->pending_bh &= ~BH_STATUS;
1847                 rc = BH_STATUS;
1848         } else {
1849                 /* Mark BH routine as complete */
1850                 info->bh_running = false;
1851                 info->bh_requested = false;
1852                 rc = 0;
1853         }
1854
1855         spin_unlock_irqrestore(&info->lock,flags);
1856
1857         return rc;
1858 }
1859
1860 /*
1861  * perform bottom half processing
1862  */
1863 static void bh_handler(struct work_struct *work)
1864 {
1865         struct slgt_info *info = container_of(work, struct slgt_info, task);
1866         int action;
1867
1868         info->bh_running = true;
1869
1870         while((action = bh_action(info))) {
1871                 switch (action) {
1872                 case BH_RECEIVE:
1873                         DBGBH(("%s bh receive\n", info->device_name));
1874                         switch(info->params.mode) {
1875                         case MGSL_MODE_ASYNC:
1876                                 rx_async(info);
1877                                 break;
1878                         case MGSL_MODE_HDLC:
1879                                 while(rx_get_frame(info));
1880                                 break;
1881                         case MGSL_MODE_RAW:
1882                         case MGSL_MODE_MONOSYNC:
1883                         case MGSL_MODE_BISYNC:
1884                         case MGSL_MODE_XSYNC:
1885                                 while(rx_get_buf(info));
1886                                 break;
1887                         }
1888                         /* restart receiver if rx DMA buffers exhausted */
1889                         if (info->rx_restart)
1890                                 rx_start(info);
1891                         break;
1892                 case BH_TRANSMIT:
1893                         bh_transmit(info);
1894                         break;
1895                 case BH_STATUS:
1896                         DBGBH(("%s bh status\n", info->device_name));
1897                         info->ri_chkcount = 0;
1898                         info->dsr_chkcount = 0;
1899                         info->dcd_chkcount = 0;
1900                         info->cts_chkcount = 0;
1901                         break;
1902                 default:
1903                         DBGBH(("%s unknown action\n", info->device_name));
1904                         break;
1905                 }
1906         }
1907         DBGBH(("%s bh_handler exit\n", info->device_name));
1908 }
1909
1910 static void bh_transmit(struct slgt_info *info)
1911 {
1912         struct tty_struct *tty = info->port.tty;
1913
1914         DBGBH(("%s bh_transmit\n", info->device_name));
1915         if (tty)
1916                 tty_wakeup(tty);
1917 }
1918
1919 static void dsr_change(struct slgt_info *info, unsigned short status)
1920 {
1921         if (status & BIT3) {
1922                 info->signals |= SerialSignal_DSR;
1923                 info->input_signal_events.dsr_up++;
1924         } else {
1925                 info->signals &= ~SerialSignal_DSR;
1926                 info->input_signal_events.dsr_down++;
1927         }
1928         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1929         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1930                 slgt_irq_off(info, IRQ_DSR);
1931                 return;
1932         }
1933         info->icount.dsr++;
1934         wake_up_interruptible(&info->status_event_wait_q);
1935         wake_up_interruptible(&info->event_wait_q);
1936         info->pending_bh |= BH_STATUS;
1937 }
1938
1939 static void cts_change(struct slgt_info *info, unsigned short status)
1940 {
1941         if (status & BIT2) {
1942                 info->signals |= SerialSignal_CTS;
1943                 info->input_signal_events.cts_up++;
1944         } else {
1945                 info->signals &= ~SerialSignal_CTS;
1946                 info->input_signal_events.cts_down++;
1947         }
1948         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1949         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1950                 slgt_irq_off(info, IRQ_CTS);
1951                 return;
1952         }
1953         info->icount.cts++;
1954         wake_up_interruptible(&info->status_event_wait_q);
1955         wake_up_interruptible(&info->event_wait_q);
1956         info->pending_bh |= BH_STATUS;
1957
1958         if (tty_port_cts_enabled(&info->port)) {
1959                 if (info->port.tty) {
1960                         if (info->port.tty->hw_stopped) {
1961                                 if (info->signals & SerialSignal_CTS) {
1962                                         info->port.tty->hw_stopped = 0;
1963                                         info->pending_bh |= BH_TRANSMIT;
1964                                         return;
1965                                 }
1966                         } else {
1967                                 if (!(info->signals & SerialSignal_CTS))
1968                                         info->port.tty->hw_stopped = 1;
1969                         }
1970                 }
1971         }
1972 }
1973
1974 static void dcd_change(struct slgt_info *info, unsigned short status)
1975 {
1976         if (status & BIT1) {
1977                 info->signals |= SerialSignal_DCD;
1978                 info->input_signal_events.dcd_up++;
1979         } else {
1980                 info->signals &= ~SerialSignal_DCD;
1981                 info->input_signal_events.dcd_down++;
1982         }
1983         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1984         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1985                 slgt_irq_off(info, IRQ_DCD);
1986                 return;
1987         }
1988         info->icount.dcd++;
1989 #if SYNCLINK_GENERIC_HDLC
1990         if (info->netcount) {
1991                 if (info->signals & SerialSignal_DCD)
1992                         netif_carrier_on(info->netdev);
1993                 else
1994                         netif_carrier_off(info->netdev);
1995         }
1996 #endif
1997         wake_up_interruptible(&info->status_event_wait_q);
1998         wake_up_interruptible(&info->event_wait_q);
1999         info->pending_bh |= BH_STATUS;
2000
2001         if (tty_port_check_carrier(&info->port)) {
2002                 if (info->signals & SerialSignal_DCD)
2003                         wake_up_interruptible(&info->port.open_wait);
2004                 else {
2005                         if (info->port.tty)
2006                                 tty_hangup(info->port.tty);
2007                 }
2008         }
2009 }
2010
2011 static void ri_change(struct slgt_info *info, unsigned short status)
2012 {
2013         if (status & BIT0) {
2014                 info->signals |= SerialSignal_RI;
2015                 info->input_signal_events.ri_up++;
2016         } else {
2017                 info->signals &= ~SerialSignal_RI;
2018                 info->input_signal_events.ri_down++;
2019         }
2020         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2021         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2022                 slgt_irq_off(info, IRQ_RI);
2023                 return;
2024         }
2025         info->icount.rng++;
2026         wake_up_interruptible(&info->status_event_wait_q);
2027         wake_up_interruptible(&info->event_wait_q);
2028         info->pending_bh |= BH_STATUS;
2029 }
2030
2031 static void isr_rxdata(struct slgt_info *info)
2032 {
2033         unsigned int count = info->rbuf_fill_count;
2034         unsigned int i = info->rbuf_fill_index;
2035         unsigned short reg;
2036
2037         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2038                 reg = rd_reg16(info, RDR);
2039                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2040                 if (desc_complete(info->rbufs[i])) {
2041                         /* all buffers full */
2042                         rx_stop(info);
2043                         info->rx_restart = true;
2044                         continue;
2045                 }
2046                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2047                 /* async mode saves status byte to buffer for each data byte */
2048                 if (info->params.mode == MGSL_MODE_ASYNC)
2049                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2050                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2051                         /* buffer full or end of frame */
2052                         set_desc_count(info->rbufs[i], count);
2053                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2054                         info->rbuf_fill_count = count = 0;
2055                         if (++i == info->rbuf_count)
2056                                 i = 0;
2057                         info->pending_bh |= BH_RECEIVE;
2058                 }
2059         }
2060
2061         info->rbuf_fill_index = i;
2062         info->rbuf_fill_count = count;
2063 }
2064
2065 static void isr_serial(struct slgt_info *info)
2066 {
2067         unsigned short status = rd_reg16(info, SSR);
2068
2069         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2070
2071         wr_reg16(info, SSR, status); /* clear pending */
2072
2073         info->irq_occurred = true;
2074
2075         if (info->params.mode == MGSL_MODE_ASYNC) {
2076                 if (status & IRQ_TXIDLE) {
2077                         if (info->tx_active)
2078                                 isr_txeom(info, status);
2079                 }
2080                 if (info->rx_pio && (status & IRQ_RXDATA))
2081                         isr_rxdata(info);
2082                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2083                         info->icount.brk++;
2084                         /* process break detection if tty control allows */
2085                         if (info->port.tty) {
2086                                 if (!(status & info->ignore_status_mask)) {
2087                                         if (info->read_status_mask & MASK_BREAK) {
2088                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2089                                                 if (info->port.flags & ASYNC_SAK)
2090                                                         do_SAK(info->port.tty);
2091                                         }
2092                                 }
2093                         }
2094                 }
2095         } else {
2096                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2097                         isr_txeom(info, status);
2098                 if (info->rx_pio && (status & IRQ_RXDATA))
2099                         isr_rxdata(info);
2100                 if (status & IRQ_RXIDLE) {
2101                         if (status & RXIDLE)
2102                                 info->icount.rxidle++;
2103                         else
2104                                 info->icount.exithunt++;
2105                         wake_up_interruptible(&info->event_wait_q);
2106                 }
2107
2108                 if (status & IRQ_RXOVER)
2109                         rx_start(info);
2110         }
2111
2112         if (status & IRQ_DSR)
2113                 dsr_change(info, status);
2114         if (status & IRQ_CTS)
2115                 cts_change(info, status);
2116         if (status & IRQ_DCD)
2117                 dcd_change(info, status);
2118         if (status & IRQ_RI)
2119                 ri_change(info, status);
2120 }
2121
2122 static void isr_rdma(struct slgt_info *info)
2123 {
2124         unsigned int status = rd_reg32(info, RDCSR);
2125
2126         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2127
2128         /* RDCSR (rx DMA control/status)
2129          *
2130          * 31..07  reserved
2131          * 06      save status byte to DMA buffer
2132          * 05      error
2133          * 04      eol (end of list)
2134          * 03      eob (end of buffer)
2135          * 02      IRQ enable
2136          * 01      reset
2137          * 00      enable
2138          */
2139         wr_reg32(info, RDCSR, status);  /* clear pending */
2140
2141         if (status & (BIT5 + BIT4)) {
2142                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2143                 info->rx_restart = true;
2144         }
2145         info->pending_bh |= BH_RECEIVE;
2146 }
2147
2148 static void isr_tdma(struct slgt_info *info)
2149 {
2150         unsigned int status = rd_reg32(info, TDCSR);
2151
2152         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2153
2154         /* TDCSR (tx DMA control/status)
2155          *
2156          * 31..06  reserved
2157          * 05      error
2158          * 04      eol (end of list)
2159          * 03      eob (end of buffer)
2160          * 02      IRQ enable
2161          * 01      reset
2162          * 00      enable
2163          */
2164         wr_reg32(info, TDCSR, status);  /* clear pending */
2165
2166         if (status & (BIT5 + BIT4 + BIT3)) {
2167                 // another transmit buffer has completed
2168                 // run bottom half to get more send data from user
2169                 info->pending_bh |= BH_TRANSMIT;
2170         }
2171 }
2172
2173 /*
2174  * return true if there are unsent tx DMA buffers, otherwise false
2175  *
2176  * if there are unsent buffers then info->tbuf_start
2177  * is set to index of first unsent buffer
2178  */
2179 static bool unsent_tbufs(struct slgt_info *info)
2180 {
2181         unsigned int i = info->tbuf_current;
2182         bool rc = false;
2183
2184         /*
2185          * search backwards from last loaded buffer (precedes tbuf_current)
2186          * for first unsent buffer (desc_count > 0)
2187          */
2188
2189         do {
2190                 if (i)
2191                         i--;
2192                 else
2193                         i = info->tbuf_count - 1;
2194                 if (!desc_count(info->tbufs[i]))
2195                         break;
2196                 info->tbuf_start = i;
2197                 rc = true;
2198         } while (i != info->tbuf_current);
2199
2200         return rc;
2201 }
2202
2203 static void isr_txeom(struct slgt_info *info, unsigned short status)
2204 {
2205         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2206
2207         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2208         tdma_reset(info);
2209         if (status & IRQ_TXUNDER) {
2210                 unsigned short val = rd_reg16(info, TCR);
2211                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2212                 wr_reg16(info, TCR, val); /* clear reset bit */
2213         }
2214
2215         if (info->tx_active) {
2216                 if (info->params.mode != MGSL_MODE_ASYNC) {
2217                         if (status & IRQ_TXUNDER)
2218                                 info->icount.txunder++;
2219                         else if (status & IRQ_TXIDLE)
2220                                 info->icount.txok++;
2221                 }
2222
2223                 if (unsent_tbufs(info)) {
2224                         tx_start(info);
2225                         update_tx_timer(info);
2226                         return;
2227                 }
2228                 info->tx_active = false;
2229
2230                 del_timer(&info->tx_timer);
2231
2232                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2233                         info->signals &= ~SerialSignal_RTS;
2234                         info->drop_rts_on_tx_done = false;
2235                         set_signals(info);
2236                 }
2237
2238 #if SYNCLINK_GENERIC_HDLC
2239                 if (info->netcount)
2240                         hdlcdev_tx_done(info);
2241                 else
2242 #endif
2243                 {
2244                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2245                                 tx_stop(info);
2246                                 return;
2247                         }
2248                         info->pending_bh |= BH_TRANSMIT;
2249                 }
2250         }
2251 }
2252
2253 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2254 {
2255         struct cond_wait *w, *prev;
2256
2257         /* wake processes waiting for specific transitions */
2258         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2259                 if (w->data & changed) {
2260                         w->data = state;
2261                         wake_up_interruptible(&w->q);
2262                         if (prev != NULL)
2263                                 prev->next = w->next;
2264                         else
2265                                 info->gpio_wait_q = w->next;
2266                 } else
2267                         prev = w;
2268         }
2269 }
2270
2271 /* interrupt service routine
2272  *
2273  *      irq     interrupt number
2274  *      dev_id  device ID supplied during interrupt registration
2275  */
2276 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2277 {
2278         struct slgt_info *info = dev_id;
2279         unsigned int gsr;
2280         unsigned int i;
2281
2282         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2283
2284         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2285                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2286                 info->irq_occurred = true;
2287                 for(i=0; i < info->port_count ; i++) {
2288                         if (info->port_array[i] == NULL)
2289                                 continue;
2290                         spin_lock(&info->port_array[i]->lock);
2291                         if (gsr & (BIT8 << i))
2292                                 isr_serial(info->port_array[i]);
2293                         if (gsr & (BIT16 << (i*2)))
2294                                 isr_rdma(info->port_array[i]);
2295                         if (gsr & (BIT17 << (i*2)))
2296                                 isr_tdma(info->port_array[i]);
2297                         spin_unlock(&info->port_array[i]->lock);
2298                 }
2299         }
2300
2301         if (info->gpio_present) {
2302                 unsigned int state;
2303                 unsigned int changed;
2304                 spin_lock(&info->lock);
2305                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2306                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2307                         /* read latched state of GPIO signals */
2308                         state = rd_reg32(info, IOVR);
2309                         /* clear pending GPIO interrupt bits */
2310                         wr_reg32(info, IOSR, changed);
2311                         for (i=0 ; i < info->port_count ; i++) {
2312                                 if (info->port_array[i] != NULL)
2313                                         isr_gpio(info->port_array[i], changed, state);
2314                         }
2315                 }
2316                 spin_unlock(&info->lock);
2317         }
2318
2319         for(i=0; i < info->port_count ; i++) {
2320                 struct slgt_info *port = info->port_array[i];
2321                 if (port == NULL)
2322                         continue;
2323                 spin_lock(&port->lock);
2324                 if ((port->port.count || port->netcount) &&
2325                     port->pending_bh && !port->bh_running &&
2326                     !port->bh_requested) {
2327                         DBGISR(("%s bh queued\n", port->device_name));
2328                         schedule_work(&port->task);
2329                         port->bh_requested = true;
2330                 }
2331                 spin_unlock(&port->lock);
2332         }
2333
2334         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2335         return IRQ_HANDLED;
2336 }
2337
2338 static int startup(struct slgt_info *info)
2339 {
2340         DBGINFO(("%s startup\n", info->device_name));
2341
2342         if (tty_port_initialized(&info->port))
2343                 return 0;
2344
2345         if (!info->tx_buf) {
2346                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2347                 if (!info->tx_buf) {
2348                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2349                         return -ENOMEM;
2350                 }
2351         }
2352
2353         info->pending_bh = 0;
2354
2355         memset(&info->icount, 0, sizeof(info->icount));
2356
2357         /* program hardware for current parameters */
2358         change_params(info);
2359
2360         if (info->port.tty)
2361                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2362
2363         tty_port_set_initialized(&info->port, 1);
2364
2365         return 0;
2366 }
2367
2368 /*
2369  *  called by close() and hangup() to shutdown hardware
2370  */
2371 static void shutdown(struct slgt_info *info)
2372 {
2373         unsigned long flags;
2374
2375         if (!tty_port_initialized(&info->port))
2376                 return;
2377
2378         DBGINFO(("%s shutdown\n", info->device_name));
2379
2380         /* clear status wait queue because status changes */
2381         /* can't happen after shutting down the hardware */
2382         wake_up_interruptible(&info->status_event_wait_q);
2383         wake_up_interruptible(&info->event_wait_q);
2384
2385         del_timer_sync(&info->tx_timer);
2386         del_timer_sync(&info->rx_timer);
2387
2388         kfree(info->tx_buf);
2389         info->tx_buf = NULL;
2390
2391         spin_lock_irqsave(&info->lock,flags);
2392
2393         tx_stop(info);
2394         rx_stop(info);
2395
2396         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2397
2398         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2399                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2400                 set_signals(info);
2401         }
2402
2403         flush_cond_wait(&info->gpio_wait_q);
2404
2405         spin_unlock_irqrestore(&info->lock,flags);
2406
2407         if (info->port.tty)
2408                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2409
2410         tty_port_set_initialized(&info->port, 0);
2411 }
2412
2413 static void program_hw(struct slgt_info *info)
2414 {
2415         unsigned long flags;
2416
2417         spin_lock_irqsave(&info->lock,flags);
2418
2419         rx_stop(info);
2420         tx_stop(info);
2421
2422         if (info->params.mode != MGSL_MODE_ASYNC ||
2423             info->netcount)
2424                 sync_mode(info);
2425         else
2426                 async_mode(info);
2427
2428         set_signals(info);
2429
2430         info->dcd_chkcount = 0;
2431         info->cts_chkcount = 0;
2432         info->ri_chkcount = 0;
2433         info->dsr_chkcount = 0;
2434
2435         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2436         get_signals(info);
2437
2438         if (info->netcount ||
2439             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2440                 rx_start(info);
2441
2442         spin_unlock_irqrestore(&info->lock,flags);
2443 }
2444
2445 /*
2446  * reconfigure adapter based on new parameters
2447  */
2448 static void change_params(struct slgt_info *info)
2449 {
2450         unsigned cflag;
2451         int bits_per_char;
2452
2453         if (!info->port.tty)
2454                 return;
2455         DBGINFO(("%s change_params\n", info->device_name));
2456
2457         cflag = info->port.tty->termios.c_cflag;
2458
2459         /* if B0 rate (hangup) specified then negate RTS and DTR */
2460         /* otherwise assert RTS and DTR */
2461         if (cflag & CBAUD)
2462                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2463         else
2464                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2465
2466         /* byte size and parity */
2467
2468         switch (cflag & CSIZE) {
2469         case CS5: info->params.data_bits = 5; break;
2470         case CS6: info->params.data_bits = 6; break;
2471         case CS7: info->params.data_bits = 7; break;
2472         case CS8: info->params.data_bits = 8; break;
2473         default:  info->params.data_bits = 7; break;
2474         }
2475
2476         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2477
2478         if (cflag & PARENB)
2479                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2480         else
2481                 info->params.parity = ASYNC_PARITY_NONE;
2482
2483         /* calculate number of jiffies to transmit a full
2484          * FIFO (32 bytes) at specified data rate
2485          */
2486         bits_per_char = info->params.data_bits +
2487                         info->params.stop_bits + 1;
2488
2489         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2490
2491         if (info->params.data_rate) {
2492                 info->timeout = (32*HZ*bits_per_char) /
2493                                 info->params.data_rate;
2494         }
2495         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2496
2497         tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2498         tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2499
2500         /* process tty input control flags */
2501
2502         info->read_status_mask = IRQ_RXOVER;
2503         if (I_INPCK(info->port.tty))
2504                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2505         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2506                 info->read_status_mask |= MASK_BREAK;
2507         if (I_IGNPAR(info->port.tty))
2508                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2509         if (I_IGNBRK(info->port.tty)) {
2510                 info->ignore_status_mask |= MASK_BREAK;
2511                 /* If ignoring parity and break indicators, ignore
2512                  * overruns too.  (For real raw support).
2513                  */
2514                 if (I_IGNPAR(info->port.tty))
2515                         info->ignore_status_mask |= MASK_OVERRUN;
2516         }
2517
2518         program_hw(info);
2519 }
2520
2521 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2522 {
2523         DBGINFO(("%s get_stats\n",  info->device_name));
2524         if (!user_icount) {
2525                 memset(&info->icount, 0, sizeof(info->icount));
2526         } else {
2527                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2528                         return -EFAULT;
2529         }
2530         return 0;
2531 }
2532
2533 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2534 {
2535         DBGINFO(("%s get_params\n", info->device_name));
2536         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2537                 return -EFAULT;
2538         return 0;
2539 }
2540
2541 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2542 {
2543         unsigned long flags;
2544         MGSL_PARAMS tmp_params;
2545
2546         DBGINFO(("%s set_params\n", info->device_name));
2547         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2548                 return -EFAULT;
2549
2550         spin_lock_irqsave(&info->lock, flags);
2551         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2552                 info->base_clock = tmp_params.clock_speed;
2553         else
2554                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2555         spin_unlock_irqrestore(&info->lock, flags);
2556
2557         program_hw(info);
2558
2559         return 0;
2560 }
2561
2562 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2563 {
2564         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2565         if (put_user(info->idle_mode, idle_mode))
2566                 return -EFAULT;
2567         return 0;
2568 }
2569
2570 static int set_txidle(struct slgt_info *info, int idle_mode)
2571 {
2572         unsigned long flags;
2573         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2574         spin_lock_irqsave(&info->lock,flags);
2575         info->idle_mode = idle_mode;
2576         if (info->params.mode != MGSL_MODE_ASYNC)
2577                 tx_set_idle(info);
2578         spin_unlock_irqrestore(&info->lock,flags);
2579         return 0;
2580 }
2581
2582 static int tx_enable(struct slgt_info *info, int enable)
2583 {
2584         unsigned long flags;
2585         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2586         spin_lock_irqsave(&info->lock,flags);
2587         if (enable) {
2588                 if (!info->tx_enabled)
2589                         tx_start(info);
2590         } else {
2591                 if (info->tx_enabled)
2592                         tx_stop(info);
2593         }
2594         spin_unlock_irqrestore(&info->lock,flags);
2595         return 0;
2596 }
2597
2598 /*
2599  * abort transmit HDLC frame
2600  */
2601 static int tx_abort(struct slgt_info *info)
2602 {
2603         unsigned long flags;
2604         DBGINFO(("%s tx_abort\n", info->device_name));
2605         spin_lock_irqsave(&info->lock,flags);
2606         tdma_reset(info);
2607         spin_unlock_irqrestore(&info->lock,flags);
2608         return 0;
2609 }
2610
2611 static int rx_enable(struct slgt_info *info, int enable)
2612 {
2613         unsigned long flags;
2614         unsigned int rbuf_fill_level;
2615         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2616         spin_lock_irqsave(&info->lock,flags);
2617         /*
2618          * enable[31..16] = receive DMA buffer fill level
2619          * 0 = noop (leave fill level unchanged)
2620          * fill level must be multiple of 4 and <= buffer size
2621          */
2622         rbuf_fill_level = ((unsigned int)enable) >> 16;
2623         if (rbuf_fill_level) {
2624                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2625                         spin_unlock_irqrestore(&info->lock, flags);
2626                         return -EINVAL;
2627                 }
2628                 info->rbuf_fill_level = rbuf_fill_level;
2629                 if (rbuf_fill_level < 128)
2630                         info->rx_pio = 1; /* PIO mode */
2631                 else
2632                         info->rx_pio = 0; /* DMA mode */
2633                 rx_stop(info); /* restart receiver to use new fill level */
2634         }
2635
2636         /*
2637          * enable[1..0] = receiver enable command
2638          * 0 = disable
2639          * 1 = enable
2640          * 2 = enable or force hunt mode if already enabled
2641          */
2642         enable &= 3;
2643         if (enable) {
2644                 if (!info->rx_enabled)
2645                         rx_start(info);
2646                 else if (enable == 2) {
2647                         /* force hunt mode (write 1 to RCR[3]) */
2648                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2649                 }
2650         } else {
2651                 if (info->rx_enabled)
2652                         rx_stop(info);
2653         }
2654         spin_unlock_irqrestore(&info->lock,flags);
2655         return 0;
2656 }
2657
2658 /*
2659  *  wait for specified event to occur
2660  */
2661 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2662 {
2663         unsigned long flags;
2664         int s;
2665         int rc=0;
2666         struct mgsl_icount cprev, cnow;
2667         int events;
2668         int mask;
2669         struct  _input_signal_events oldsigs, newsigs;
2670         DECLARE_WAITQUEUE(wait, current);
2671
2672         if (get_user(mask, mask_ptr))
2673                 return -EFAULT;
2674
2675         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2676
2677         spin_lock_irqsave(&info->lock,flags);
2678
2679         /* return immediately if state matches requested events */
2680         get_signals(info);
2681         s = info->signals;
2682
2683         events = mask &
2684                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2685                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2686                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2687                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2688         if (events) {
2689                 spin_unlock_irqrestore(&info->lock,flags);
2690                 goto exit;
2691         }
2692
2693         /* save current irq counts */
2694         cprev = info->icount;
2695         oldsigs = info->input_signal_events;
2696
2697         /* enable hunt and idle irqs if needed */
2698         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2699                 unsigned short val = rd_reg16(info, SCR);
2700                 if (!(val & IRQ_RXIDLE))
2701                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2702         }
2703
2704         set_current_state(TASK_INTERRUPTIBLE);
2705         add_wait_queue(&info->event_wait_q, &wait);
2706
2707         spin_unlock_irqrestore(&info->lock,flags);
2708
2709         for(;;) {
2710                 schedule();
2711                 if (signal_pending(current)) {
2712                         rc = -ERESTARTSYS;
2713                         break;
2714                 }
2715
2716                 /* get current irq counts */
2717                 spin_lock_irqsave(&info->lock,flags);
2718                 cnow = info->icount;
2719                 newsigs = info->input_signal_events;
2720                 set_current_state(TASK_INTERRUPTIBLE);
2721                 spin_unlock_irqrestore(&info->lock,flags);
2722
2723                 /* if no change, wait aborted for some reason */
2724                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2725                     newsigs.dsr_down == oldsigs.dsr_down &&
2726                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2727                     newsigs.dcd_down == oldsigs.dcd_down &&
2728                     newsigs.cts_up   == oldsigs.cts_up   &&
2729                     newsigs.cts_down == oldsigs.cts_down &&
2730                     newsigs.ri_up    == oldsigs.ri_up    &&
2731                     newsigs.ri_down  == oldsigs.ri_down  &&
2732                     cnow.exithunt    == cprev.exithunt   &&
2733                     cnow.rxidle      == cprev.rxidle) {
2734                         rc = -EIO;
2735                         break;
2736                 }
2737
2738                 events = mask &
2739                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2740                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2741                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2742                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2743                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2744                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2745                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2746                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2747                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2748                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2749                 if (events)
2750                         break;
2751
2752                 cprev = cnow;
2753                 oldsigs = newsigs;
2754         }
2755
2756         remove_wait_queue(&info->event_wait_q, &wait);
2757         set_current_state(TASK_RUNNING);
2758
2759
2760         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2761                 spin_lock_irqsave(&info->lock,flags);
2762                 if (!waitqueue_active(&info->event_wait_q)) {
2763                         /* disable enable exit hunt mode/idle rcvd IRQs */
2764                         wr_reg16(info, SCR,
2765                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2766                 }
2767                 spin_unlock_irqrestore(&info->lock,flags);
2768         }
2769 exit:
2770         if (rc == 0)
2771                 rc = put_user(events, mask_ptr);
2772         return rc;
2773 }
2774
2775 static int get_interface(struct slgt_info *info, int __user *if_mode)
2776 {
2777         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2778         if (put_user(info->if_mode, if_mode))
2779                 return -EFAULT;
2780         return 0;
2781 }
2782
2783 static int set_interface(struct slgt_info *info, int if_mode)
2784 {
2785         unsigned long flags;
2786         unsigned short val;
2787
2788         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2789         spin_lock_irqsave(&info->lock,flags);
2790         info->if_mode = if_mode;
2791
2792         msc_set_vcr(info);
2793
2794         /* TCR (tx control) 07  1=RTS driver control */
2795         val = rd_reg16(info, TCR);
2796         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2797                 val |= BIT7;
2798         else
2799                 val &= ~BIT7;
2800         wr_reg16(info, TCR, val);
2801
2802         spin_unlock_irqrestore(&info->lock,flags);
2803         return 0;
2804 }
2805
2806 static int get_xsync(struct slgt_info *info, int __user *xsync)
2807 {
2808         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2809         if (put_user(info->xsync, xsync))
2810                 return -EFAULT;
2811         return 0;
2812 }
2813
2814 /*
2815  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2816  *
2817  * sync pattern is contained in least significant bytes of value
2818  * most significant byte of sync pattern is oldest (1st sent/detected)
2819  */
2820 static int set_xsync(struct slgt_info *info, int xsync)
2821 {
2822         unsigned long flags;
2823
2824         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2825         spin_lock_irqsave(&info->lock, flags);
2826         info->xsync = xsync;
2827         wr_reg32(info, XSR, xsync);
2828         spin_unlock_irqrestore(&info->lock, flags);
2829         return 0;
2830 }
2831
2832 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2833 {
2834         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2835         if (put_user(info->xctrl, xctrl))
2836                 return -EFAULT;
2837         return 0;
2838 }
2839
2840 /*
2841  * set extended control options
2842  *
2843  * xctrl[31:19] reserved, must be zero
2844  * xctrl[18:17] extended sync pattern length in bytes
2845  *              00 = 1 byte  in xsr[7:0]
2846  *              01 = 2 bytes in xsr[15:0]
2847  *              10 = 3 bytes in xsr[23:0]
2848  *              11 = 4 bytes in xsr[31:0]
2849  * xctrl[16]    1 = enable terminal count, 0=disabled
2850  * xctrl[15:0]  receive terminal count for fixed length packets
2851  *              value is count minus one (0 = 1 byte packet)
2852  *              when terminal count is reached, receiver
2853  *              automatically returns to hunt mode and receive
2854  *              FIFO contents are flushed to DMA buffers with
2855  *              end of frame (EOF) status
2856  */
2857 static int set_xctrl(struct slgt_info *info, int xctrl)
2858 {
2859         unsigned long flags;
2860
2861         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2862         spin_lock_irqsave(&info->lock, flags);
2863         info->xctrl = xctrl;
2864         wr_reg32(info, XCR, xctrl);
2865         spin_unlock_irqrestore(&info->lock, flags);
2866         return 0;
2867 }
2868
2869 /*
2870  * set general purpose IO pin state and direction
2871  *
2872  * user_gpio fields:
2873  * state   each bit indicates a pin state
2874  * smask   set bit indicates pin state to set
2875  * dir     each bit indicates a pin direction (0=input, 1=output)
2876  * dmask   set bit indicates pin direction to set
2877  */
2878 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2879 {
2880         unsigned long flags;
2881         struct gpio_desc gpio;
2882         __u32 data;
2883
2884         if (!info->gpio_present)
2885                 return -EINVAL;
2886         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2887                 return -EFAULT;
2888         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2889                  info->device_name, gpio.state, gpio.smask,
2890                  gpio.dir, gpio.dmask));
2891
2892         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2893         if (gpio.dmask) {
2894                 data = rd_reg32(info, IODR);
2895                 data |= gpio.dmask & gpio.dir;
2896                 data &= ~(gpio.dmask & ~gpio.dir);
2897                 wr_reg32(info, IODR, data);
2898         }
2899         if (gpio.smask) {
2900                 data = rd_reg32(info, IOVR);
2901                 data |= gpio.smask & gpio.state;
2902                 data &= ~(gpio.smask & ~gpio.state);
2903                 wr_reg32(info, IOVR, data);
2904         }
2905         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2906
2907         return 0;
2908 }
2909
2910 /*
2911  * get general purpose IO pin state and direction
2912  */
2913 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2914 {
2915         struct gpio_desc gpio;
2916         if (!info->gpio_present)
2917                 return -EINVAL;
2918         gpio.state = rd_reg32(info, IOVR);
2919         gpio.smask = 0xffffffff;
2920         gpio.dir   = rd_reg32(info, IODR);
2921         gpio.dmask = 0xffffffff;
2922         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2923                 return -EFAULT;
2924         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2925                  info->device_name, gpio.state, gpio.dir));
2926         return 0;
2927 }
2928
2929 /*
2930  * conditional wait facility
2931  */
2932 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2933 {
2934         init_waitqueue_head(&w->q);
2935         init_waitqueue_entry(&w->wait, current);
2936         w->data = data;
2937 }
2938
2939 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2940 {
2941         set_current_state(TASK_INTERRUPTIBLE);
2942         add_wait_queue(&w->q, &w->wait);
2943         w->next = *head;
2944         *head = w;
2945 }
2946
2947 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2948 {
2949         struct cond_wait *w, *prev;
2950         remove_wait_queue(&cw->q, &cw->wait);
2951         set_current_state(TASK_RUNNING);
2952         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2953                 if (w == cw) {
2954                         if (prev != NULL)
2955                                 prev->next = w->next;
2956                         else
2957                                 *head = w->next;
2958                         break;
2959                 }
2960         }
2961 }
2962
2963 static void flush_cond_wait(struct cond_wait **head)
2964 {
2965         while (*head != NULL) {
2966                 wake_up_interruptible(&(*head)->q);
2967                 *head = (*head)->next;
2968         }
2969 }
2970
2971 /*
2972  * wait for general purpose I/O pin(s) to enter specified state
2973  *
2974  * user_gpio fields:
2975  * state - bit indicates target pin state
2976  * smask - set bit indicates watched pin
2977  *
2978  * The wait ends when at least one watched pin enters the specified
2979  * state. When 0 (no error) is returned, user_gpio->state is set to the
2980  * state of all GPIO pins when the wait ends.
2981  *
2982  * Note: Each pin may be a dedicated input, dedicated output, or
2983  * configurable input/output. The number and configuration of pins
2984  * varies with the specific adapter model. Only input pins (dedicated
2985  * or configured) can be monitored with this function.
2986  */
2987 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2988 {
2989         unsigned long flags;
2990         int rc = 0;
2991         struct gpio_desc gpio;
2992         struct cond_wait wait;
2993         u32 state;
2994
2995         if (!info->gpio_present)
2996                 return -EINVAL;
2997         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2998                 return -EFAULT;
2999         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3000                  info->device_name, gpio.state, gpio.smask));
3001         /* ignore output pins identified by set IODR bit */
3002         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3003                 return -EINVAL;
3004         init_cond_wait(&wait, gpio.smask);
3005
3006         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3007         /* enable interrupts for watched pins */
3008         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3009         /* get current pin states */
3010         state = rd_reg32(info, IOVR);
3011
3012         if (gpio.smask & ~(state ^ gpio.state)) {
3013                 /* already in target state */
3014                 gpio.state = state;
3015         } else {
3016                 /* wait for target state */
3017                 add_cond_wait(&info->gpio_wait_q, &wait);
3018                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3019                 schedule();
3020                 if (signal_pending(current))
3021                         rc = -ERESTARTSYS;
3022                 else
3023                         gpio.state = wait.data;
3024                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3025                 remove_cond_wait(&info->gpio_wait_q, &wait);
3026         }
3027
3028         /* disable all GPIO interrupts if no waiting processes */
3029         if (info->gpio_wait_q == NULL)
3030                 wr_reg32(info, IOER, 0);
3031         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3032
3033         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3034                 rc = -EFAULT;
3035         return rc;
3036 }
3037
3038 static int modem_input_wait(struct slgt_info *info,int arg)
3039 {
3040         unsigned long flags;
3041         int rc;
3042         struct mgsl_icount cprev, cnow;
3043         DECLARE_WAITQUEUE(wait, current);
3044
3045         /* save current irq counts */
3046         spin_lock_irqsave(&info->lock,flags);
3047         cprev = info->icount;
3048         add_wait_queue(&info->status_event_wait_q, &wait);
3049         set_current_state(TASK_INTERRUPTIBLE);
3050         spin_unlock_irqrestore(&info->lock,flags);
3051
3052         for(;;) {
3053                 schedule();
3054                 if (signal_pending(current)) {
3055                         rc = -ERESTARTSYS;
3056                         break;
3057                 }
3058
3059                 /* get new irq counts */
3060                 spin_lock_irqsave(&info->lock,flags);
3061                 cnow = info->icount;
3062                 set_current_state(TASK_INTERRUPTIBLE);
3063                 spin_unlock_irqrestore(&info->lock,flags);
3064
3065                 /* if no change, wait aborted for some reason */
3066                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3067                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3068                         rc = -EIO;
3069                         break;
3070                 }
3071
3072                 /* check for change in caller specified modem input */
3073                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3074                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3075                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3076                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3077                         rc = 0;
3078                         break;
3079                 }
3080
3081                 cprev = cnow;
3082         }
3083         remove_wait_queue(&info->status_event_wait_q, &wait);
3084         set_current_state(TASK_RUNNING);
3085         return rc;
3086 }
3087
3088 /*
3089  *  return state of serial control and status signals
3090  */
3091 static int tiocmget(struct tty_struct *tty)
3092 {
3093         struct slgt_info *info = tty->driver_data;
3094         unsigned int result;
3095         unsigned long flags;
3096
3097         spin_lock_irqsave(&info->lock,flags);
3098         get_signals(info);
3099         spin_unlock_irqrestore(&info->lock,flags);
3100
3101         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3102                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3103                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3104                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3105                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3106                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3107
3108         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3109         return result;
3110 }
3111
3112 /*
3113  * set modem control signals (DTR/RTS)
3114  *
3115  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3116  *              TIOCMSET = set/clear signal values
3117  *      value   bit mask for command
3118  */
3119 static int tiocmset(struct tty_struct *tty,
3120                     unsigned int set, unsigned int clear)
3121 {
3122         struct slgt_info *info = tty->driver_data;
3123         unsigned long flags;
3124
3125         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3126
3127         if (set & TIOCM_RTS)
3128                 info->signals |= SerialSignal_RTS;
3129         if (set & TIOCM_DTR)
3130                 info->signals |= SerialSignal_DTR;
3131         if (clear & TIOCM_RTS)
3132                 info->signals &= ~SerialSignal_RTS;
3133         if (clear & TIOCM_DTR)
3134                 info->signals &= ~SerialSignal_DTR;
3135
3136         spin_lock_irqsave(&info->lock,flags);
3137         set_signals(info);
3138         spin_unlock_irqrestore(&info->lock,flags);
3139         return 0;
3140 }
3141
3142 static int carrier_raised(struct tty_port *port)
3143 {
3144         unsigned long flags;
3145         struct slgt_info *info = container_of(port, struct slgt_info, port);
3146
3147         spin_lock_irqsave(&info->lock,flags);
3148         get_signals(info);
3149         spin_unlock_irqrestore(&info->lock,flags);
3150         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3151 }
3152
3153 static void dtr_rts(struct tty_port *port, int on)
3154 {
3155         unsigned long flags;
3156         struct slgt_info *info = container_of(port, struct slgt_info, port);
3157
3158         spin_lock_irqsave(&info->lock,flags);
3159         if (on)
3160                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3161         else
3162                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3163         set_signals(info);
3164         spin_unlock_irqrestore(&info->lock,flags);
3165 }
3166
3167
3168 /*
3169  *  block current process until the device is ready to open
3170  */
3171 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3172                            struct slgt_info *info)
3173 {
3174         DECLARE_WAITQUEUE(wait, current);
3175         int             retval;
3176         bool            do_clocal = false;
3177         unsigned long   flags;
3178         int             cd;
3179         struct tty_port *port = &info->port;
3180
3181         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3182
3183         if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3184                 /* nonblock mode is set or port is not enabled */
3185                 tty_port_set_active(port, 1);
3186                 return 0;
3187         }
3188
3189         if (C_CLOCAL(tty))
3190                 do_clocal = true;
3191
3192         /* Wait for carrier detect and the line to become
3193          * free (i.e., not in use by the callout).  While we are in
3194          * this loop, port->count is dropped by one, so that
3195          * close() knows when to free things.  We restore it upon
3196          * exit, either normal or abnormal.
3197          */
3198
3199         retval = 0;
3200         add_wait_queue(&port->open_wait, &wait);
3201
3202         spin_lock_irqsave(&info->lock, flags);
3203         port->count--;
3204         spin_unlock_irqrestore(&info->lock, flags);
3205         port->blocked_open++;
3206
3207         while (1) {
3208                 if (C_BAUD(tty) && tty_port_initialized(port))
3209                         tty_port_raise_dtr_rts(port);
3210
3211                 set_current_state(TASK_INTERRUPTIBLE);
3212
3213                 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3214                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3215                                         -EAGAIN : -ERESTARTSYS;
3216                         break;
3217                 }
3218
3219                 cd = tty_port_carrier_raised(port);
3220                 if (do_clocal || cd)
3221                         break;
3222
3223                 if (signal_pending(current)) {
3224                         retval = -ERESTARTSYS;
3225                         break;
3226                 }
3227
3228                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3229                 tty_unlock(tty);
3230                 schedule();
3231                 tty_lock(tty);
3232         }
3233
3234         set_current_state(TASK_RUNNING);
3235         remove_wait_queue(&port->open_wait, &wait);
3236
3237         if (!tty_hung_up_p(filp))
3238                 port->count++;
3239         port->blocked_open--;
3240
3241         if (!retval)
3242                 tty_port_set_active(port, 1);
3243
3244         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3245         return retval;
3246 }
3247
3248 /*
3249  * allocate buffers used for calling line discipline receive_buf
3250  * directly in synchronous mode
3251  * note: add 5 bytes to max frame size to allow appending
3252  * 32-bit CRC and status byte when configured to do so
3253  */
3254 static int alloc_tmp_rbuf(struct slgt_info *info)
3255 {
3256         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3257         if (info->tmp_rbuf == NULL)
3258                 return -ENOMEM;
3259         /* unused flag buffer to satisfy receive_buf calling interface */
3260         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3261         if (!info->flag_buf) {
3262                 kfree(info->tmp_rbuf);
3263                 info->tmp_rbuf = NULL;
3264                 return -ENOMEM;
3265         }
3266         return 0;
3267 }
3268
3269 static void free_tmp_rbuf(struct slgt_info *info)
3270 {
3271         kfree(info->tmp_rbuf);
3272         info->tmp_rbuf = NULL;
3273         kfree(info->flag_buf);
3274         info->flag_buf = NULL;
3275 }
3276
3277 /*
3278  * allocate DMA descriptor lists.
3279  */
3280 static int alloc_desc(struct slgt_info *info)
3281 {
3282         unsigned int i;
3283         unsigned int pbufs;
3284
3285         /* allocate memory to hold descriptor lists */
3286         info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3287                                         &info->bufs_dma_addr, GFP_KERNEL);
3288         if (info->bufs == NULL)
3289                 return -ENOMEM;
3290
3291         info->rbufs = (struct slgt_desc*)info->bufs;
3292         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3293
3294         pbufs = (unsigned int)info->bufs_dma_addr;
3295
3296         /*
3297          * Build circular lists of descriptors
3298          */
3299
3300         for (i=0; i < info->rbuf_count; i++) {
3301                 /* physical address of this descriptor */
3302                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3303
3304                 /* physical address of next descriptor */
3305                 if (i == info->rbuf_count - 1)
3306                         info->rbufs[i].next = cpu_to_le32(pbufs);
3307                 else
3308                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3309                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3310         }
3311
3312         for (i=0; i < info->tbuf_count; i++) {
3313                 /* physical address of this descriptor */
3314                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3315
3316                 /* physical address of next descriptor */
3317                 if (i == info->tbuf_count - 1)
3318                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3319                 else
3320                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3321         }
3322
3323         return 0;
3324 }
3325
3326 static void free_desc(struct slgt_info *info)
3327 {
3328         if (info->bufs != NULL) {
3329                 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3330                                   info->bufs, info->bufs_dma_addr);
3331                 info->bufs  = NULL;
3332                 info->rbufs = NULL;
3333                 info->tbufs = NULL;
3334         }
3335 }
3336
3337 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3338 {
3339         int i;
3340         for (i=0; i < count; i++) {
3341                 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3342                                                  &bufs[i].buf_dma_addr, GFP_KERNEL);
3343                 if (!bufs[i].buf)
3344                         return -ENOMEM;
3345                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3346         }
3347         return 0;
3348 }
3349
3350 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3351 {
3352         int i;
3353         for (i=0; i < count; i++) {
3354                 if (bufs[i].buf == NULL)
3355                         continue;
3356                 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3357                                   bufs[i].buf_dma_addr);
3358                 bufs[i].buf = NULL;
3359         }
3360 }
3361
3362 static int alloc_dma_bufs(struct slgt_info *info)
3363 {
3364         info->rbuf_count = 32;
3365         info->tbuf_count = 32;
3366
3367         if (alloc_desc(info) < 0 ||
3368             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3369             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3370             alloc_tmp_rbuf(info) < 0) {
3371                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3372                 return -ENOMEM;
3373         }
3374         reset_rbufs(info);
3375         return 0;
3376 }
3377
3378 static void free_dma_bufs(struct slgt_info *info)
3379 {
3380         if (info->bufs) {
3381                 free_bufs(info, info->rbufs, info->rbuf_count);
3382                 free_bufs(info, info->tbufs, info->tbuf_count);
3383                 free_desc(info);
3384         }
3385         free_tmp_rbuf(info);
3386 }
3387
3388 static int claim_resources(struct slgt_info *info)
3389 {
3390         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3391                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3392                         info->device_name, info->phys_reg_addr));
3393                 info->init_error = DiagStatus_AddressConflict;
3394                 goto errout;
3395         }
3396         else
3397                 info->reg_addr_requested = true;
3398
3399         info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3400         if (!info->reg_addr) {
3401                 DBGERR(("%s can't map device registers, addr=%08X\n",
3402                         info->device_name, info->phys_reg_addr));
3403                 info->init_error = DiagStatus_CantAssignPciResources;
3404                 goto errout;
3405         }
3406         return 0;
3407
3408 errout:
3409         release_resources(info);
3410         return -ENODEV;
3411 }
3412
3413 static void release_resources(struct slgt_info *info)
3414 {
3415         if (info->irq_requested) {
3416                 free_irq(info->irq_level, info);
3417                 info->irq_requested = false;
3418         }
3419
3420         if (info->reg_addr_requested) {
3421                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3422                 info->reg_addr_requested = false;
3423         }
3424
3425         if (info->reg_addr) {
3426                 iounmap(info->reg_addr);
3427                 info->reg_addr = NULL;
3428         }
3429 }
3430
3431 /* Add the specified device instance data structure to the
3432  * global linked list of devices and increment the device count.
3433  */
3434 static void add_device(struct slgt_info *info)
3435 {
3436         char *devstr;
3437
3438         info->next_device = NULL;
3439         info->line = slgt_device_count;
3440         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3441
3442         if (info->line < MAX_DEVICES) {
3443                 if (maxframe[info->line])
3444                         info->max_frame_size = maxframe[info->line];
3445         }
3446
3447         slgt_device_count++;
3448
3449         if (!slgt_device_list)
3450                 slgt_device_list = info;
3451         else {
3452                 struct slgt_info *current_dev = slgt_device_list;
3453                 while(current_dev->next_device)
3454                         current_dev = current_dev->next_device;
3455                 current_dev->next_device = info;
3456         }
3457
3458         if (info->max_frame_size < 4096)
3459                 info->max_frame_size = 4096;
3460         else if (info->max_frame_size > 65535)
3461                 info->max_frame_size = 65535;
3462
3463         switch(info->pdev->device) {
3464         case SYNCLINK_GT_DEVICE_ID:
3465                 devstr = "GT";
3466                 break;
3467         case SYNCLINK_GT2_DEVICE_ID:
3468                 devstr = "GT2";
3469                 break;
3470         case SYNCLINK_GT4_DEVICE_ID:
3471                 devstr = "GT4";
3472                 break;
3473         case SYNCLINK_AC_DEVICE_ID:
3474                 devstr = "AC";
3475                 info->params.mode = MGSL_MODE_ASYNC;
3476                 break;
3477         default:
3478                 devstr = "(unknown model)";
3479         }
3480         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3481                 devstr, info->device_name, info->phys_reg_addr,
3482                 info->irq_level, info->max_frame_size);
3483
3484 #if SYNCLINK_GENERIC_HDLC
3485         hdlcdev_init(info);
3486 #endif
3487 }
3488
3489 static const struct tty_port_operations slgt_port_ops = {
3490         .carrier_raised = carrier_raised,
3491         .dtr_rts = dtr_rts,
3492 };
3493
3494 /*
3495  *  allocate device instance structure, return NULL on failure
3496  */
3497 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3498 {
3499         struct slgt_info *info;
3500
3501         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3502
3503         if (!info) {
3504                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3505                         driver_name, adapter_num, port_num));
3506         } else {
3507                 tty_port_init(&info->port);
3508                 info->port.ops = &slgt_port_ops;
3509                 info->magic = MGSL_MAGIC;
3510                 INIT_WORK(&info->task, bh_handler);
3511                 info->max_frame_size = 4096;
3512                 info->base_clock = 14745600;
3513                 info->rbuf_fill_level = DMABUFSIZE;
3514                 init_waitqueue_head(&info->status_event_wait_q);
3515                 init_waitqueue_head(&info->event_wait_q);
3516                 spin_lock_init(&info->netlock);
3517                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3518                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3519                 info->adapter_num = adapter_num;
3520                 info->port_num = port_num;
3521
3522                 timer_setup(&info->tx_timer, tx_timeout, 0);
3523                 timer_setup(&info->rx_timer, rx_timeout, 0);
3524
3525                 /* Copy configuration info to device instance data */
3526                 info->pdev = pdev;
3527                 info->irq_level = pdev->irq;
3528                 info->phys_reg_addr = pci_resource_start(pdev,0);
3529
3530                 info->bus_type = MGSL_BUS_TYPE_PCI;
3531                 info->irq_flags = IRQF_SHARED;
3532
3533                 info->init_error = -1; /* assume error, set to 0 on successful init */
3534         }
3535
3536         return info;
3537 }
3538
3539 static void device_init(int adapter_num, struct pci_dev *pdev)
3540 {
3541         struct slgt_info *port_array[SLGT_MAX_PORTS];
3542         int i;
3543         int port_count = 1;
3544
3545         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3546                 port_count = 2;
3547         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3548                 port_count = 4;
3549
3550         /* allocate device instances for all ports */
3551         for (i=0; i < port_count; ++i) {
3552                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3553                 if (port_array[i] == NULL) {
3554                         for (--i; i >= 0; --i) {
3555                                 tty_port_destroy(&port_array[i]->port);
3556                                 kfree(port_array[i]);
3557                         }
3558                         return;
3559                 }
3560         }
3561
3562         /* give copy of port_array to all ports and add to device list  */
3563         for (i=0; i < port_count; ++i) {
3564                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3565                 add_device(port_array[i]);
3566                 port_array[i]->port_count = port_count;
3567                 spin_lock_init(&port_array[i]->lock);
3568         }
3569
3570         /* Allocate and claim adapter resources */
3571         if (!claim_resources(port_array[0])) {
3572
3573                 alloc_dma_bufs(port_array[0]);
3574
3575                 /* copy resource information from first port to others */
3576                 for (i = 1; i < port_count; ++i) {
3577                         port_array[i]->irq_level = port_array[0]->irq_level;
3578                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3579                         alloc_dma_bufs(port_array[i]);
3580                 }
3581
3582                 if (request_irq(port_array[0]->irq_level,
3583                                         slgt_interrupt,
3584                                         port_array[0]->irq_flags,
3585                                         port_array[0]->device_name,
3586                                         port_array[0]) < 0) {
3587                         DBGERR(("%s request_irq failed IRQ=%d\n",
3588                                 port_array[0]->device_name,
3589                                 port_array[0]->irq_level));
3590                 } else {
3591                         port_array[0]->irq_requested = true;
3592                         adapter_test(port_array[0]);
3593                         for (i=1 ; i < port_count ; i++) {
3594                                 port_array[i]->init_error = port_array[0]->init_error;
3595                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3596                         }
3597                 }
3598         }
3599
3600         for (i = 0; i < port_count; ++i) {
3601                 struct slgt_info *info = port_array[i];
3602                 tty_port_register_device(&info->port, serial_driver, info->line,
3603                                 &info->pdev->dev);
3604         }
3605 }
3606
3607 static int init_one(struct pci_dev *dev,
3608                               const struct pci_device_id *ent)
3609 {
3610         if (pci_enable_device(dev)) {
3611                 printk("error enabling pci device %p\n", dev);
3612                 return -EIO;
3613         }
3614         pci_set_master(dev);
3615         device_init(slgt_device_count, dev);
3616         return 0;
3617 }
3618
3619 static void remove_one(struct pci_dev *dev)
3620 {
3621 }
3622
3623 static const struct tty_operations ops = {
3624         .open = open,
3625         .close = close,
3626         .write = write,
3627         .put_char = put_char,
3628         .flush_chars = flush_chars,
3629         .write_room = write_room,
3630         .chars_in_buffer = chars_in_buffer,
3631         .flush_buffer = flush_buffer,
3632         .ioctl = ioctl,
3633         .compat_ioctl = slgt_compat_ioctl,
3634         .throttle = throttle,
3635         .unthrottle = unthrottle,
3636         .send_xchar = send_xchar,
3637         .break_ctl = set_break,
3638         .wait_until_sent = wait_until_sent,
3639         .set_termios = set_termios,
3640         .stop = tx_hold,
3641         .start = tx_release,
3642         .hangup = hangup,
3643         .tiocmget = tiocmget,
3644         .tiocmset = tiocmset,
3645         .get_icount = get_icount,
3646         .proc_show = synclink_gt_proc_show,
3647 };
3648
3649 static void slgt_cleanup(void)
3650 {
3651         struct slgt_info *info;
3652         struct slgt_info *tmp;
3653
3654         printk(KERN_INFO "unload %s\n", driver_name);
3655
3656         if (serial_driver) {
3657                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3658                         tty_unregister_device(serial_driver, info->line);
3659                 tty_unregister_driver(serial_driver);
3660                 put_tty_driver(serial_driver);
3661         }
3662
3663         /* reset devices */
3664         info = slgt_device_list;
3665         while(info) {
3666                 reset_port(info);
3667                 info = info->next_device;
3668         }
3669
3670         /* release devices */
3671         info = slgt_device_list;
3672         while(info) {
3673 #if SYNCLINK_GENERIC_HDLC
3674                 hdlcdev_exit(info);
3675 #endif
3676                 free_dma_bufs(info);
3677                 free_tmp_rbuf(info);
3678                 if (info->port_num == 0)
3679                         release_resources(info);
3680                 tmp = info;
3681                 info = info->next_device;
3682                 tty_port_destroy(&tmp->port);
3683                 kfree(tmp);
3684         }
3685
3686         if (pci_registered)
3687                 pci_unregister_driver(&pci_driver);
3688 }
3689
3690 /*
3691  *  Driver initialization entry point.
3692  */
3693 static int __init slgt_init(void)
3694 {
3695         int rc;
3696
3697         printk(KERN_INFO "%s\n", driver_name);
3698
3699         serial_driver = alloc_tty_driver(MAX_DEVICES);
3700         if (!serial_driver) {
3701                 printk("%s can't allocate tty driver\n", driver_name);
3702                 return -ENOMEM;
3703         }
3704
3705         /* Initialize the tty_driver structure */
3706
3707         serial_driver->driver_name = slgt_driver_name;
3708         serial_driver->name = tty_dev_prefix;
3709         serial_driver->major = ttymajor;
3710         serial_driver->minor_start = 64;
3711         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3712         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3713         serial_driver->init_termios = tty_std_termios;
3714         serial_driver->init_termios.c_cflag =
3715                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3716         serial_driver->init_termios.c_ispeed = 9600;
3717         serial_driver->init_termios.c_ospeed = 9600;
3718         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3719         tty_set_operations(serial_driver, &ops);
3720         if ((rc = tty_register_driver(serial_driver)) < 0) {
3721                 DBGERR(("%s can't register serial driver\n", driver_name));
3722                 put_tty_driver(serial_driver);
3723                 serial_driver = NULL;
3724                 goto error;
3725         }
3726
3727         printk(KERN_INFO "%s, tty major#%d\n",
3728                driver_name, serial_driver->major);
3729
3730         slgt_device_count = 0;
3731         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3732                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3733                 goto error;
3734         }
3735         pci_registered = true;
3736
3737         if (!slgt_device_list)
3738                 printk("%s no devices found\n",driver_name);
3739
3740         return 0;
3741
3742 error:
3743         slgt_cleanup();
3744         return rc;
3745 }
3746
3747 static void __exit slgt_exit(void)
3748 {
3749         slgt_cleanup();
3750 }
3751
3752 module_init(slgt_init);
3753 module_exit(slgt_exit);
3754
3755 /*
3756  * register access routines
3757  */
3758
3759 #define CALC_REGADDR() \
3760         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3761         if (addr >= 0x80) \
3762                 reg_addr += (info->port_num) * 32; \
3763         else if (addr >= 0x40)  \
3764                 reg_addr += (info->port_num) * 16;
3765
3766 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3767 {
3768         CALC_REGADDR();
3769         return readb((void __iomem *)reg_addr);
3770 }
3771
3772 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3773 {
3774         CALC_REGADDR();
3775         writeb(value, (void __iomem *)reg_addr);
3776 }
3777
3778 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3779 {
3780         CALC_REGADDR();
3781         return readw((void __iomem *)reg_addr);
3782 }
3783
3784 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3785 {
3786         CALC_REGADDR();
3787         writew(value, (void __iomem *)reg_addr);
3788 }
3789
3790 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3791 {
3792         CALC_REGADDR();
3793         return readl((void __iomem *)reg_addr);
3794 }
3795
3796 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3797 {
3798         CALC_REGADDR();
3799         writel(value, (void __iomem *)reg_addr);
3800 }
3801
3802 static void rdma_reset(struct slgt_info *info)
3803 {
3804         unsigned int i;
3805
3806         /* set reset bit */
3807         wr_reg32(info, RDCSR, BIT1);
3808
3809         /* wait for enable bit cleared */
3810         for(i=0 ; i < 1000 ; i++)
3811                 if (!(rd_reg32(info, RDCSR) & BIT0))
3812                         break;
3813 }
3814
3815 static void tdma_reset(struct slgt_info *info)
3816 {
3817         unsigned int i;
3818
3819         /* set reset bit */
3820         wr_reg32(info, TDCSR, BIT1);
3821
3822         /* wait for enable bit cleared */
3823         for(i=0 ; i < 1000 ; i++)
3824                 if (!(rd_reg32(info, TDCSR) & BIT0))
3825                         break;
3826 }
3827
3828 /*
3829  * enable internal loopback
3830  * TxCLK and RxCLK are generated from BRG
3831  * and TxD is looped back to RxD internally.
3832  */
3833 static void enable_loopback(struct slgt_info *info)
3834 {
3835         /* SCR (serial control) BIT2=loopback enable */
3836         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3837
3838         if (info->params.mode != MGSL_MODE_ASYNC) {
3839                 /* CCR (clock control)
3840                  * 07..05  tx clock source (010 = BRG)
3841                  * 04..02  rx clock source (010 = BRG)
3842                  * 01      auxclk enable   (0 = disable)
3843                  * 00      BRG enable      (1 = enable)
3844                  *
3845                  * 0100 1001
3846                  */
3847                 wr_reg8(info, CCR, 0x49);
3848
3849                 /* set speed if available, otherwise use default */
3850                 if (info->params.clock_speed)
3851                         set_rate(info, info->params.clock_speed);
3852                 else
3853                         set_rate(info, 3686400);
3854         }
3855 }
3856
3857 /*
3858  *  set baud rate generator to specified rate
3859  */
3860 static void set_rate(struct slgt_info *info, u32 rate)
3861 {
3862         unsigned int div;
3863         unsigned int osc = info->base_clock;
3864
3865         /* div = osc/rate - 1
3866          *
3867          * Round div up if osc/rate is not integer to
3868          * force to next slowest rate.
3869          */
3870
3871         if (rate) {
3872                 div = osc/rate;
3873                 if (!(osc % rate) && div)
3874                         div--;
3875                 wr_reg16(info, BDR, (unsigned short)div);
3876         }
3877 }
3878
3879 static void rx_stop(struct slgt_info *info)
3880 {
3881         unsigned short val;
3882
3883         /* disable and reset receiver */
3884         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3885         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3886         wr_reg16(info, RCR, val);                  /* clear reset bit */
3887
3888         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3889
3890         /* clear pending rx interrupts */
3891         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3892
3893         rdma_reset(info);
3894
3895         info->rx_enabled = false;
3896         info->rx_restart = false;
3897 }
3898
3899 static void rx_start(struct slgt_info *info)
3900 {
3901         unsigned short val;
3902
3903         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3904
3905         /* clear pending rx overrun IRQ */
3906         wr_reg16(info, SSR, IRQ_RXOVER);
3907
3908         /* reset and disable receiver */
3909         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3910         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3911         wr_reg16(info, RCR, val);                  /* clear reset bit */
3912
3913         rdma_reset(info);
3914         reset_rbufs(info);
3915
3916         if (info->rx_pio) {
3917                 /* rx request when rx FIFO not empty */
3918                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3919                 slgt_irq_on(info, IRQ_RXDATA);
3920                 if (info->params.mode == MGSL_MODE_ASYNC) {
3921                         /* enable saving of rx status */
3922                         wr_reg32(info, RDCSR, BIT6);
3923                 }
3924         } else {
3925                 /* rx request when rx FIFO half full */
3926                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3927                 /* set 1st descriptor address */
3928                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3929
3930                 if (info->params.mode != MGSL_MODE_ASYNC) {
3931                         /* enable rx DMA and DMA interrupt */
3932                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
3933                 } else {
3934                         /* enable saving of rx status, rx DMA and DMA interrupt */
3935                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3936                 }
3937         }
3938
3939         slgt_irq_on(info, IRQ_RXOVER);
3940
3941         /* enable receiver */
3942         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3943
3944         info->rx_restart = false;
3945         info->rx_enabled = true;
3946 }
3947
3948 static void tx_start(struct slgt_info *info)
3949 {
3950         if (!info->tx_enabled) {
3951                 wr_reg16(info, TCR,
3952                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3953                 info->tx_enabled = true;
3954         }
3955
3956         if (desc_count(info->tbufs[info->tbuf_start])) {
3957                 info->drop_rts_on_tx_done = false;
3958
3959                 if (info->params.mode != MGSL_MODE_ASYNC) {
3960                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3961                                 get_signals(info);
3962                                 if (!(info->signals & SerialSignal_RTS)) {
3963                                         info->signals |= SerialSignal_RTS;
3964                                         set_signals(info);
3965                                         info->drop_rts_on_tx_done = true;
3966                                 }
3967                         }
3968
3969                         slgt_irq_off(info, IRQ_TXDATA);
3970                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3971                         /* clear tx idle and underrun status bits */
3972                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3973                 } else {
3974                         slgt_irq_off(info, IRQ_TXDATA);
3975                         slgt_irq_on(info, IRQ_TXIDLE);
3976                         /* clear tx idle status bit */
3977                         wr_reg16(info, SSR, IRQ_TXIDLE);
3978                 }
3979                 /* set 1st descriptor address and start DMA */
3980                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3981                 wr_reg32(info, TDCSR, BIT2 + BIT0);
3982                 info->tx_active = true;
3983         }
3984 }
3985
3986 static void tx_stop(struct slgt_info *info)
3987 {
3988         unsigned short val;
3989
3990         del_timer(&info->tx_timer);
3991
3992         tdma_reset(info);
3993
3994         /* reset and disable transmitter */
3995         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3996         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3997
3998         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3999
4000         /* clear tx idle and underrun status bit */
4001         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4002
4003         reset_tbufs(info);
4004
4005         info->tx_enabled = false;
4006         info->tx_active = false;
4007 }
4008
4009 static void reset_port(struct slgt_info *info)
4010 {
4011         if (!info->reg_addr)
4012                 return;
4013
4014         tx_stop(info);
4015         rx_stop(info);
4016
4017         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4018         set_signals(info);
4019
4020         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4021 }
4022
4023 static void reset_adapter(struct slgt_info *info)
4024 {
4025         int i;
4026         for (i=0; i < info->port_count; ++i) {
4027                 if (info->port_array[i])
4028                         reset_port(info->port_array[i]);
4029         }
4030 }
4031
4032 static void async_mode(struct slgt_info *info)
4033 {
4034         unsigned short val;
4035
4036         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4037         tx_stop(info);
4038         rx_stop(info);
4039
4040         /* TCR (tx control)
4041          *
4042          * 15..13  mode, 010=async
4043          * 12..10  encoding, 000=NRZ
4044          * 09      parity enable
4045          * 08      1=odd parity, 0=even parity
4046          * 07      1=RTS driver control
4047          * 06      1=break enable
4048          * 05..04  character length
4049          *         00=5 bits
4050          *         01=6 bits
4051          *         10=7 bits
4052          *         11=8 bits
4053          * 03      0=1 stop bit, 1=2 stop bits
4054          * 02      reset
4055          * 01      enable
4056          * 00      auto-CTS enable
4057          */
4058         val = 0x4000;
4059
4060         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4061                 val |= BIT7;
4062
4063         if (info->params.parity != ASYNC_PARITY_NONE) {
4064                 val |= BIT9;
4065                 if (info->params.parity == ASYNC_PARITY_ODD)
4066                         val |= BIT8;
4067         }
4068
4069         switch (info->params.data_bits)
4070         {
4071         case 6: val |= BIT4; break;
4072         case 7: val |= BIT5; break;
4073         case 8: val |= BIT5 + BIT4; break;
4074         }
4075
4076         if (info->params.stop_bits != 1)
4077                 val |= BIT3;
4078
4079         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4080                 val |= BIT0;
4081
4082         wr_reg16(info, TCR, val);
4083
4084         /* RCR (rx control)
4085          *
4086          * 15..13  mode, 010=async
4087          * 12..10  encoding, 000=NRZ
4088          * 09      parity enable
4089          * 08      1=odd parity, 0=even parity
4090          * 07..06  reserved, must be 0
4091          * 05..04  character length
4092          *         00=5 bits
4093          *         01=6 bits
4094          *         10=7 bits
4095          *         11=8 bits
4096          * 03      reserved, must be zero
4097          * 02      reset
4098          * 01      enable
4099          * 00      auto-DCD enable
4100          */
4101         val = 0x4000;
4102
4103         if (info->params.parity != ASYNC_PARITY_NONE) {
4104                 val |= BIT9;
4105                 if (info->params.parity == ASYNC_PARITY_ODD)
4106                         val |= BIT8;
4107         }
4108
4109         switch (info->params.data_bits)
4110         {
4111         case 6: val |= BIT4; break;
4112         case 7: val |= BIT5; break;
4113         case 8: val |= BIT5 + BIT4; break;
4114         }
4115
4116         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4117                 val |= BIT0;
4118
4119         wr_reg16(info, RCR, val);
4120
4121         /* CCR (clock control)
4122          *
4123          * 07..05  011 = tx clock source is BRG/16
4124          * 04..02  010 = rx clock source is BRG
4125          * 01      0 = auxclk disabled
4126          * 00      1 = BRG enabled
4127          *
4128          * 0110 1001
4129          */
4130         wr_reg8(info, CCR, 0x69);
4131
4132         msc_set_vcr(info);
4133
4134         /* SCR (serial control)
4135          *
4136          * 15  1=tx req on FIFO half empty
4137          * 14  1=rx req on FIFO half full
4138          * 13  tx data  IRQ enable
4139          * 12  tx idle  IRQ enable
4140          * 11  rx break on IRQ enable
4141          * 10  rx data  IRQ enable
4142          * 09  rx break off IRQ enable
4143          * 08  overrun  IRQ enable
4144          * 07  DSR      IRQ enable
4145          * 06  CTS      IRQ enable
4146          * 05  DCD      IRQ enable
4147          * 04  RI       IRQ enable
4148          * 03  0=16x sampling, 1=8x sampling
4149          * 02  1=txd->rxd internal loopback enable
4150          * 01  reserved, must be zero
4151          * 00  1=master IRQ enable
4152          */
4153         val = BIT15 + BIT14 + BIT0;
4154         /* JCR[8] : 1 = x8 async mode feature available */
4155         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4156             ((info->base_clock < (info->params.data_rate * 16)) ||
4157              (info->base_clock % (info->params.data_rate * 16)))) {
4158                 /* use 8x sampling */
4159                 val |= BIT3;
4160                 set_rate(info, info->params.data_rate * 8);
4161         } else {
4162                 /* use 16x sampling */
4163                 set_rate(info, info->params.data_rate * 16);
4164         }
4165         wr_reg16(info, SCR, val);
4166
4167         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4168
4169         if (info->params.loopback)
4170                 enable_loopback(info);
4171 }
4172
4173 static void sync_mode(struct slgt_info *info)
4174 {
4175         unsigned short val;
4176
4177         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4178         tx_stop(info);
4179         rx_stop(info);
4180
4181         /* TCR (tx control)
4182          *
4183          * 15..13  mode
4184          *         000=HDLC/SDLC
4185          *         001=raw bit synchronous
4186          *         010=asynchronous/isochronous
4187          *         011=monosync byte synchronous
4188          *         100=bisync byte synchronous
4189          *         101=xsync byte synchronous
4190          * 12..10  encoding
4191          * 09      CRC enable
4192          * 08      CRC32
4193          * 07      1=RTS driver control
4194          * 06      preamble enable
4195          * 05..04  preamble length
4196          * 03      share open/close flag
4197          * 02      reset
4198          * 01      enable
4199          * 00      auto-CTS enable
4200          */
4201         val = BIT2;
4202
4203         switch(info->params.mode) {
4204         case MGSL_MODE_XSYNC:
4205                 val |= BIT15 + BIT13;
4206                 break;
4207         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4208         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4209         case MGSL_MODE_RAW:      val |= BIT13; break;
4210         }
4211         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4212                 val |= BIT7;
4213
4214         switch(info->params.encoding)
4215         {
4216         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4217         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4218         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4219         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4220         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4221         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4222         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4223         }
4224
4225         switch (info->params.crc_type & HDLC_CRC_MASK)
4226         {
4227         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4228         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4229         }
4230
4231         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4232                 val |= BIT6;
4233
4234         switch (info->params.preamble_length)
4235         {
4236         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4237         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4238         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4239         }
4240
4241         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4242                 val |= BIT0;
4243
4244         wr_reg16(info, TCR, val);
4245
4246         /* TPR (transmit preamble) */
4247
4248         switch (info->params.preamble)
4249         {
4250         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4251         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4252         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4253         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4254         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4255         default:                          val = 0x7e; break;
4256         }
4257         wr_reg8(info, TPR, (unsigned char)val);
4258
4259         /* RCR (rx control)
4260          *
4261          * 15..13  mode
4262          *         000=HDLC/SDLC
4263          *         001=raw bit synchronous
4264          *         010=asynchronous/isochronous
4265          *         011=monosync byte synchronous
4266          *         100=bisync byte synchronous
4267          *         101=xsync byte synchronous
4268          * 12..10  encoding
4269          * 09      CRC enable
4270          * 08      CRC32
4271          * 07..03  reserved, must be 0
4272          * 02      reset
4273          * 01      enable
4274          * 00      auto-DCD enable
4275          */
4276         val = 0;
4277
4278         switch(info->params.mode) {
4279         case MGSL_MODE_XSYNC:
4280                 val |= BIT15 + BIT13;
4281                 break;
4282         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4283         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4284         case MGSL_MODE_RAW:      val |= BIT13; break;
4285         }
4286
4287         switch(info->params.encoding)
4288         {
4289         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4290         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4291         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4292         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4293         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4294         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4295         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4296         }
4297
4298         switch (info->params.crc_type & HDLC_CRC_MASK)
4299         {
4300         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4301         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4302         }
4303
4304         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4305                 val |= BIT0;
4306
4307         wr_reg16(info, RCR, val);
4308
4309         /* CCR (clock control)
4310          *
4311          * 07..05  tx clock source
4312          * 04..02  rx clock source
4313          * 01      auxclk enable
4314          * 00      BRG enable
4315          */
4316         val = 0;
4317
4318         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4319         {
4320                 // when RxC source is DPLL, BRG generates 16X DPLL
4321                 // reference clock, so take TxC from BRG/16 to get
4322                 // transmit clock at actual data rate
4323                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4324                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4325                 else
4326                         val |= BIT6;    /* 010, txclk = BRG */
4327         }
4328         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4329                 val |= BIT7;    /* 100, txclk = DPLL Input */
4330         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4331                 val |= BIT5;    /* 001, txclk = RXC Input */
4332
4333         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4334                 val |= BIT3;    /* 010, rxclk = BRG */
4335         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4336                 val |= BIT4;    /* 100, rxclk = DPLL */
4337         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4338                 val |= BIT2;    /* 001, rxclk = TXC Input */
4339
4340         if (info->params.clock_speed)
4341                 val |= BIT1 + BIT0;
4342
4343         wr_reg8(info, CCR, (unsigned char)val);
4344
4345         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4346         {
4347                 // program DPLL mode
4348                 switch(info->params.encoding)
4349                 {
4350                 case HDLC_ENCODING_BIPHASE_MARK:
4351                 case HDLC_ENCODING_BIPHASE_SPACE:
4352                         val = BIT7; break;
4353                 case HDLC_ENCODING_BIPHASE_LEVEL:
4354                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4355                         val = BIT7 + BIT6; break;
4356                 default: val = BIT6;    // NRZ encodings
4357                 }
4358                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4359
4360                 // DPLL requires a 16X reference clock from BRG
4361                 set_rate(info, info->params.clock_speed * 16);
4362         }
4363         else
4364                 set_rate(info, info->params.clock_speed);
4365
4366         tx_set_idle(info);
4367
4368         msc_set_vcr(info);
4369
4370         /* SCR (serial control)
4371          *
4372          * 15  1=tx req on FIFO half empty
4373          * 14  1=rx req on FIFO half full
4374          * 13  tx data  IRQ enable
4375          * 12  tx idle  IRQ enable
4376          * 11  underrun IRQ enable
4377          * 10  rx data  IRQ enable
4378          * 09  rx idle  IRQ enable
4379          * 08  overrun  IRQ enable
4380          * 07  DSR      IRQ enable
4381          * 06  CTS      IRQ enable
4382          * 05  DCD      IRQ enable
4383          * 04  RI       IRQ enable
4384          * 03  reserved, must be zero
4385          * 02  1=txd->rxd internal loopback enable
4386          * 01  reserved, must be zero
4387          * 00  1=master IRQ enable
4388          */
4389         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4390
4391         if (info->params.loopback)
4392                 enable_loopback(info);
4393 }
4394
4395 /*
4396  *  set transmit idle mode
4397  */
4398 static void tx_set_idle(struct slgt_info *info)
4399 {
4400         unsigned char val;
4401         unsigned short tcr;
4402
4403         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4404          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4405          */
4406         tcr = rd_reg16(info, TCR);
4407         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4408                 /* disable preamble, set idle size to 16 bits */
4409                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4410                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4411                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4412         } else if (!(tcr & BIT6)) {
4413                 /* preamble is disabled, set idle size to 8 bits */
4414                 tcr &= ~(BIT5 + BIT4);
4415         }
4416         wr_reg16(info, TCR, tcr);
4417
4418         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4419                 /* LSB of custom tx idle specified in tx idle register */
4420                 val = (unsigned char)(info->idle_mode & 0xff);
4421         } else {
4422                 /* standard 8 bit idle patterns */
4423                 switch(info->idle_mode)
4424                 {
4425                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4426                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4427                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4428                 case HDLC_TXIDLE_ZEROS:
4429                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4430                 default:                         val = 0xff;
4431                 }
4432         }
4433
4434         wr_reg8(info, TIR, val);
4435 }
4436
4437 /*
4438  * get state of V24 status (input) signals
4439  */
4440 static void get_signals(struct slgt_info *info)
4441 {
4442         unsigned short status = rd_reg16(info, SSR);
4443
4444         /* clear all serial signals except RTS and DTR */
4445         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4446
4447         if (status & BIT3)
4448                 info->signals |= SerialSignal_DSR;
4449         if (status & BIT2)
4450                 info->signals |= SerialSignal_CTS;
4451         if (status & BIT1)
4452                 info->signals |= SerialSignal_DCD;
4453         if (status & BIT0)
4454                 info->signals |= SerialSignal_RI;
4455 }
4456
4457 /*
4458  * set V.24 Control Register based on current configuration
4459  */
4460 static void msc_set_vcr(struct slgt_info *info)
4461 {
4462         unsigned char val = 0;
4463
4464         /* VCR (V.24 control)
4465          *
4466          * 07..04  serial IF select
4467          * 03      DTR
4468          * 02      RTS
4469          * 01      LL
4470          * 00      RL
4471          */
4472
4473         switch(info->if_mode & MGSL_INTERFACE_MASK)
4474         {
4475         case MGSL_INTERFACE_RS232:
4476                 val |= BIT5; /* 0010 */
4477                 break;
4478         case MGSL_INTERFACE_V35:
4479                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4480                 break;
4481         case MGSL_INTERFACE_RS422:
4482                 val |= BIT6; /* 0100 */
4483                 break;
4484         }
4485
4486         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4487                 val |= BIT4;
4488         if (info->signals & SerialSignal_DTR)
4489                 val |= BIT3;
4490         if (info->signals & SerialSignal_RTS)
4491                 val |= BIT2;
4492         if (info->if_mode & MGSL_INTERFACE_LL)
4493                 val |= BIT1;
4494         if (info->if_mode & MGSL_INTERFACE_RL)
4495                 val |= BIT0;
4496         wr_reg8(info, VCR, val);
4497 }
4498
4499 /*
4500  * set state of V24 control (output) signals
4501  */
4502 static void set_signals(struct slgt_info *info)
4503 {
4504         unsigned char val = rd_reg8(info, VCR);
4505         if (info->signals & SerialSignal_DTR)
4506                 val |= BIT3;
4507         else
4508                 val &= ~BIT3;
4509         if (info->signals & SerialSignal_RTS)
4510                 val |= BIT2;
4511         else
4512                 val &= ~BIT2;
4513         wr_reg8(info, VCR, val);
4514 }
4515
4516 /*
4517  * free range of receive DMA buffers (i to last)
4518  */
4519 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4520 {
4521         int done = 0;
4522
4523         while(!done) {
4524                 /* reset current buffer for reuse */
4525                 info->rbufs[i].status = 0;
4526                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4527                 if (i == last)
4528                         done = 1;
4529                 if (++i == info->rbuf_count)
4530                         i = 0;
4531         }
4532         info->rbuf_current = i;
4533 }
4534
4535 /*
4536  * mark all receive DMA buffers as free
4537  */
4538 static void reset_rbufs(struct slgt_info *info)
4539 {
4540         free_rbufs(info, 0, info->rbuf_count - 1);
4541         info->rbuf_fill_index = 0;
4542         info->rbuf_fill_count = 0;
4543 }
4544
4545 /*
4546  * pass receive HDLC frame to upper layer
4547  *
4548  * return true if frame available, otherwise false
4549  */
4550 static bool rx_get_frame(struct slgt_info *info)
4551 {
4552         unsigned int start, end;
4553         unsigned short status;
4554         unsigned int framesize = 0;
4555         unsigned long flags;
4556         struct tty_struct *tty = info->port.tty;
4557         unsigned char addr_field = 0xff;
4558         unsigned int crc_size = 0;
4559
4560         switch (info->params.crc_type & HDLC_CRC_MASK) {
4561         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4562         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4563         }
4564
4565 check_again:
4566
4567         framesize = 0;
4568         addr_field = 0xff;
4569         start = end = info->rbuf_current;
4570
4571         for (;;) {
4572                 if (!desc_complete(info->rbufs[end]))
4573                         goto cleanup;
4574
4575                 if (framesize == 0 && info->params.addr_filter != 0xff)
4576                         addr_field = info->rbufs[end].buf[0];
4577
4578                 framesize += desc_count(info->rbufs[end]);
4579
4580                 if (desc_eof(info->rbufs[end]))
4581                         break;
4582
4583                 if (++end == info->rbuf_count)
4584                         end = 0;
4585
4586                 if (end == info->rbuf_current) {
4587                         if (info->rx_enabled){
4588                                 spin_lock_irqsave(&info->lock,flags);
4589                                 rx_start(info);
4590                                 spin_unlock_irqrestore(&info->lock,flags);
4591                         }
4592                         goto cleanup;
4593                 }
4594         }
4595
4596         /* status
4597          *
4598          * 15      buffer complete
4599          * 14..06  reserved
4600          * 05..04  residue
4601          * 02      eof (end of frame)
4602          * 01      CRC error
4603          * 00      abort
4604          */
4605         status = desc_status(info->rbufs[end]);
4606
4607         /* ignore CRC bit if not using CRC (bit is undefined) */
4608         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4609                 status &= ~BIT1;
4610
4611         if (framesize == 0 ||
4612                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4613                 free_rbufs(info, start, end);
4614                 goto check_again;
4615         }
4616
4617         if (framesize < (2 + crc_size) || status & BIT0) {
4618                 info->icount.rxshort++;
4619                 framesize = 0;
4620         } else if (status & BIT1) {
4621                 info->icount.rxcrc++;
4622                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4623                         framesize = 0;
4624         }
4625
4626 #if SYNCLINK_GENERIC_HDLC
4627         if (framesize == 0) {
4628                 info->netdev->stats.rx_errors++;
4629                 info->netdev->stats.rx_frame_errors++;
4630         }
4631 #endif
4632
4633         DBGBH(("%s rx frame status=%04X size=%d\n",
4634                 info->device_name, status, framesize));
4635         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4636
4637         if (framesize) {
4638                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4639                         framesize -= crc_size;
4640                         crc_size = 0;
4641                 }
4642
4643                 if (framesize > info->max_frame_size + crc_size)
4644                         info->icount.rxlong++;
4645                 else {
4646                         /* copy dma buffer(s) to contiguous temp buffer */
4647                         int copy_count = framesize;
4648                         int i = start;
4649                         unsigned char *p = info->tmp_rbuf;
4650                         info->tmp_rbuf_count = framesize;
4651
4652                         info->icount.rxok++;
4653
4654                         while(copy_count) {
4655                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4656                                 memcpy(p, info->rbufs[i].buf, partial_count);
4657                                 p += partial_count;
4658                                 copy_count -= partial_count;
4659                                 if (++i == info->rbuf_count)
4660                                         i = 0;
4661                         }
4662
4663                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4664                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4665                                 framesize++;
4666                         }
4667
4668 #if SYNCLINK_GENERIC_HDLC
4669                         if (info->netcount)
4670                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4671                         else
4672 #endif
4673                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4674                 }
4675         }
4676         free_rbufs(info, start, end);
4677         return true;
4678
4679 cleanup:
4680         return false;
4681 }
4682
4683 /*
4684  * pass receive buffer (RAW synchronous mode) to tty layer
4685  * return true if buffer available, otherwise false
4686  */
4687 static bool rx_get_buf(struct slgt_info *info)
4688 {
4689         unsigned int i = info->rbuf_current;
4690         unsigned int count;
4691
4692         if (!desc_complete(info->rbufs[i]))
4693                 return false;
4694         count = desc_count(info->rbufs[i]);
4695         switch(info->params.mode) {
4696         case MGSL_MODE_MONOSYNC:
4697         case MGSL_MODE_BISYNC:
4698         case MGSL_MODE_XSYNC:
4699                 /* ignore residue in byte synchronous modes */
4700                 if (desc_residue(info->rbufs[i]))
4701                         count--;
4702                 break;
4703         }
4704         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4705         DBGINFO(("rx_get_buf size=%d\n", count));
4706         if (count)
4707                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4708                                   info->flag_buf, count);
4709         free_rbufs(info, i, i);
4710         return true;
4711 }
4712
4713 static void reset_tbufs(struct slgt_info *info)
4714 {
4715         unsigned int i;
4716         info->tbuf_current = 0;
4717         for (i=0 ; i < info->tbuf_count ; i++) {
4718                 info->tbufs[i].status = 0;
4719                 info->tbufs[i].count  = 0;
4720         }
4721 }
4722
4723 /*
4724  * return number of free transmit DMA buffers
4725  */
4726 static unsigned int free_tbuf_count(struct slgt_info *info)
4727 {
4728         unsigned int count = 0;
4729         unsigned int i = info->tbuf_current;
4730
4731         do
4732         {
4733                 if (desc_count(info->tbufs[i]))
4734                         break; /* buffer in use */
4735                 ++count;
4736                 if (++i == info->tbuf_count)
4737                         i=0;
4738         } while (i != info->tbuf_current);
4739
4740         /* if tx DMA active, last zero count buffer is in use */
4741         if (count && (rd_reg32(info, TDCSR) & BIT0))
4742                 --count;
4743
4744         return count;
4745 }
4746
4747 /*
4748  * return number of bytes in unsent transmit DMA buffers
4749  * and the serial controller tx FIFO
4750  */
4751 static unsigned int tbuf_bytes(struct slgt_info *info)
4752 {
4753         unsigned int total_count = 0;
4754         unsigned int i = info->tbuf_current;
4755         unsigned int reg_value;
4756         unsigned int count;
4757         unsigned int active_buf_count = 0;
4758
4759         /*
4760          * Add descriptor counts for all tx DMA buffers.
4761          * If count is zero (cleared by DMA controller after read),
4762          * the buffer is complete or is actively being read from.
4763          *
4764          * Record buf_count of last buffer with zero count starting
4765          * from current ring position. buf_count is mirror
4766          * copy of count and is not cleared by serial controller.
4767          * If DMA controller is active, that buffer is actively
4768          * being read so add to total.
4769          */
4770         do {
4771                 count = desc_count(info->tbufs[i]);
4772                 if (count)
4773                         total_count += count;
4774                 else if (!total_count)
4775                         active_buf_count = info->tbufs[i].buf_count;
4776                 if (++i == info->tbuf_count)
4777                         i = 0;
4778         } while (i != info->tbuf_current);
4779
4780         /* read tx DMA status register */
4781         reg_value = rd_reg32(info, TDCSR);
4782
4783         /* if tx DMA active, last zero count buffer is in use */
4784         if (reg_value & BIT0)
4785                 total_count += active_buf_count;
4786
4787         /* add tx FIFO count = reg_value[15..8] */
4788         total_count += (reg_value >> 8) & 0xff;
4789
4790         /* if transmitter active add one byte for shift register */
4791         if (info->tx_active)
4792                 total_count++;
4793
4794         return total_count;
4795 }
4796
4797 /*
4798  * load data into transmit DMA buffer ring and start transmitter if needed
4799  * return true if data accepted, otherwise false (buffers full)
4800  */
4801 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4802 {
4803         unsigned short count;
4804         unsigned int i;
4805         struct slgt_desc *d;
4806
4807         /* check required buffer space */
4808         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4809                 return false;
4810
4811         DBGDATA(info, buf, size, "tx");
4812
4813         /*
4814          * copy data to one or more DMA buffers in circular ring
4815          * tbuf_start   = first buffer for this data
4816          * tbuf_current = next free buffer
4817          *
4818          * Copy all data before making data visible to DMA controller by
4819          * setting descriptor count of the first buffer.
4820          * This prevents an active DMA controller from reading the first DMA
4821          * buffers of a frame and stopping before the final buffers are filled.
4822          */
4823
4824         info->tbuf_start = i = info->tbuf_current;
4825
4826         while (size) {
4827                 d = &info->tbufs[i];
4828
4829                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4830                 memcpy(d->buf, buf, count);
4831
4832                 size -= count;
4833                 buf  += count;
4834
4835                 /*
4836                  * set EOF bit for last buffer of HDLC frame or
4837                  * for every buffer in raw mode
4838                  */
4839                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4840                     info->params.mode == MGSL_MODE_RAW)
4841                         set_desc_eof(*d, 1);
4842                 else
4843                         set_desc_eof(*d, 0);
4844
4845                 /* set descriptor count for all but first buffer */
4846                 if (i != info->tbuf_start)
4847                         set_desc_count(*d, count);
4848                 d->buf_count = count;
4849
4850                 if (++i == info->tbuf_count)
4851                         i = 0;
4852         }
4853
4854         info->tbuf_current = i;
4855
4856         /* set first buffer count to make new data visible to DMA controller */
4857         d = &info->tbufs[info->tbuf_start];
4858         set_desc_count(*d, d->buf_count);
4859
4860         /* start transmitter if needed and update transmit timeout */
4861         if (!info->tx_active)
4862                 tx_start(info);
4863         update_tx_timer(info);
4864
4865         return true;
4866 }
4867
4868 static int register_test(struct slgt_info *info)
4869 {
4870         static unsigned short patterns[] =
4871                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4872         static unsigned int count = ARRAY_SIZE(patterns);
4873         unsigned int i;
4874         int rc = 0;
4875
4876         for (i=0 ; i < count ; i++) {
4877                 wr_reg16(info, TIR, patterns[i]);
4878                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4879                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4880                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4881                         rc = -ENODEV;
4882                         break;
4883                 }
4884         }
4885         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4886         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4887         return rc;
4888 }
4889
4890 static int irq_test(struct slgt_info *info)
4891 {
4892         unsigned long timeout;
4893         unsigned long flags;
4894         struct tty_struct *oldtty = info->port.tty;
4895         u32 speed = info->params.data_rate;
4896
4897         info->params.data_rate = 921600;
4898         info->port.tty = NULL;
4899
4900         spin_lock_irqsave(&info->lock, flags);
4901         async_mode(info);
4902         slgt_irq_on(info, IRQ_TXIDLE);
4903
4904         /* enable transmitter */
4905         wr_reg16(info, TCR,
4906                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4907
4908         /* write one byte and wait for tx idle */
4909         wr_reg16(info, TDR, 0);
4910
4911         /* assume failure */
4912         info->init_error = DiagStatus_IrqFailure;
4913         info->irq_occurred = false;
4914
4915         spin_unlock_irqrestore(&info->lock, flags);
4916
4917         timeout=100;
4918         while(timeout-- && !info->irq_occurred)
4919                 msleep_interruptible(10);
4920
4921         spin_lock_irqsave(&info->lock,flags);
4922         reset_port(info);
4923         spin_unlock_irqrestore(&info->lock,flags);
4924
4925         info->params.data_rate = speed;
4926         info->port.tty = oldtty;
4927
4928         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4929         return info->irq_occurred ? 0 : -ENODEV;
4930 }
4931
4932 static int loopback_test_rx(struct slgt_info *info)
4933 {
4934         unsigned char *src, *dest;
4935         int count;
4936
4937         if (desc_complete(info->rbufs[0])) {
4938                 count = desc_count(info->rbufs[0]);
4939                 src   = info->rbufs[0].buf;
4940                 dest  = info->tmp_rbuf;
4941
4942                 for( ; count ; count-=2, src+=2) {
4943                         /* src=data byte (src+1)=status byte */
4944                         if (!(*(src+1) & (BIT9 + BIT8))) {
4945                                 *dest = *src;
4946                                 dest++;
4947                                 info->tmp_rbuf_count++;
4948                         }
4949                 }
4950                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4951                 return 1;
4952         }
4953         return 0;
4954 }
4955
4956 static int loopback_test(struct slgt_info *info)
4957 {
4958 #define TESTFRAMESIZE 20
4959
4960         unsigned long timeout;
4961         u16 count;
4962         unsigned char buf[TESTFRAMESIZE];
4963         int rc = -ENODEV;
4964         unsigned long flags;
4965
4966         struct tty_struct *oldtty = info->port.tty;
4967         MGSL_PARAMS params;
4968
4969         memcpy(&params, &info->params, sizeof(params));
4970
4971         info->params.mode = MGSL_MODE_ASYNC;
4972         info->params.data_rate = 921600;
4973         info->params.loopback = 1;
4974         info->port.tty = NULL;
4975
4976         /* build and send transmit frame */
4977         for (count = 0; count < TESTFRAMESIZE; ++count)
4978                 buf[count] = (unsigned char)count;
4979
4980         info->tmp_rbuf_count = 0;
4981         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4982
4983         /* program hardware for HDLC and enabled receiver */
4984         spin_lock_irqsave(&info->lock,flags);
4985         async_mode(info);
4986         rx_start(info);
4987         tx_load(info, buf, count);
4988         spin_unlock_irqrestore(&info->lock, flags);
4989
4990         /* wait for receive complete */
4991         for (timeout = 100; timeout; --timeout) {
4992                 msleep_interruptible(10);
4993                 if (loopback_test_rx(info)) {
4994                         rc = 0;
4995                         break;
4996                 }
4997         }
4998
4999         /* verify received frame length and contents */
5000         if (!rc && (info->tmp_rbuf_count != count ||
5001                   memcmp(buf, info->tmp_rbuf, count))) {
5002                 rc = -ENODEV;
5003         }
5004
5005         spin_lock_irqsave(&info->lock,flags);
5006         reset_adapter(info);
5007         spin_unlock_irqrestore(&info->lock,flags);
5008
5009         memcpy(&info->params, &params, sizeof(info->params));
5010         info->port.tty = oldtty;
5011
5012         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5013         return rc;
5014 }
5015
5016 static int adapter_test(struct slgt_info *info)
5017 {
5018         DBGINFO(("testing %s\n", info->device_name));
5019         if (register_test(info) < 0) {
5020                 printk("register test failure %s addr=%08X\n",
5021                         info->device_name, info->phys_reg_addr);
5022         } else if (irq_test(info) < 0) {
5023                 printk("IRQ test failure %s IRQ=%d\n",
5024                         info->device_name, info->irq_level);
5025         } else if (loopback_test(info) < 0) {
5026                 printk("loopback test failure %s\n", info->device_name);
5027         }
5028         return info->init_error;
5029 }
5030
5031 /*
5032  * transmit timeout handler
5033  */
5034 static void tx_timeout(struct timer_list *t)
5035 {
5036         struct slgt_info *info = from_timer(info, t, tx_timer);
5037         unsigned long flags;
5038
5039         DBGINFO(("%s tx_timeout\n", info->device_name));
5040         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5041                 info->icount.txtimeout++;
5042         }
5043         spin_lock_irqsave(&info->lock,flags);
5044         tx_stop(info);
5045         spin_unlock_irqrestore(&info->lock,flags);
5046
5047 #if SYNCLINK_GENERIC_HDLC
5048         if (info->netcount)
5049                 hdlcdev_tx_done(info);
5050         else
5051 #endif
5052                 bh_transmit(info);
5053 }
5054
5055 /*
5056  * receive buffer polling timer
5057  */
5058 static void rx_timeout(struct timer_list *t)
5059 {
5060         struct slgt_info *info = from_timer(info, t, rx_timer);
5061         unsigned long flags;
5062
5063         DBGINFO(("%s rx_timeout\n", info->device_name));
5064         spin_lock_irqsave(&info->lock, flags);
5065         info->pending_bh |= BH_RECEIVE;
5066         spin_unlock_irqrestore(&info->lock, flags);
5067         bh_handler(&info->task);
5068 }
5069