drivers/tty/synclink_gt.c

   1 /*
   2  * Device driver for Microgate SyncLink GT serial adapters.
   3  *
   4  * written by Paul Fulghum for Microgate Corporation
   5  * paulkf@microgate.com
   6  *
   7  * Microgate and SyncLink are trademarks of Microgate Corporation
   8  *
   9  * This code is released under the GNU General Public License (GPL)
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21  * OF THE POSSIBILITY OF SUCH DAMAGE.
  22  */
  23
  24 /*
  25  * DEBUG OUTPUT DEFINITIONS
  26  *
  27  * uncomment lines below to enable specific types of debug output
  28  *
  29  * DBGINFO   information - most verbose output
  30  * DBGERR    serious errors
  31  * DBGBH     bottom half service routine debugging
  32  * DBGISR    interrupt service routine debugging
  33  * DBGDATA   output receive and transmit data
  34  * DBGTBUF   output transmit DMA buffers and registers
  35  * DBGRBUF   output receive DMA buffers and registers
  36  */
  37
  38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43 /*#define DBGTBUF(info) dump_tbufs(info)*/
  44 /*#define DBGRBUF(info) dump_rbufs(info)*/
  45
  46
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/signal.h>
  50 #include <linux/sched.h>
  51 #include <linux/timer.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/tty.h>
  55 #include <linux/tty_flip.h>
  56 #include <linux/serial.h>
  57 #include <linux/major.h>
  58 #include <linux/string.h>
  59 #include <linux/fcntl.h>
  60 #include <linux/ptrace.h>
  61 #include <linux/ioport.h>
  62 #include <linux/mm.h>
  63 #include <linux/seq_file.h>
  64 #include <linux/slab.h>
  65 #include <linux/netdevice.h>
  66 #include <linux/vmalloc.h>
  67 #include <linux/init.h>
  68 #include <linux/delay.h>
  69 #include <linux/ioctl.h>
  70 #include <linux/termios.h>
  71 #include <linux/bitops.h>
  72 #include <linux/workqueue.h>
  73 #include <linux/hdlc.h>
  74 #include <linux/synclink.h>
  75
  76 #include <asm/io.h>
  77 #include <asm/irq.h>
  78 #include <asm/dma.h>
  79 #include <asm/types.h>
  80 #include <linux/uaccess.h>
  81
  82 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  83 #define SYNCLINK_GENERIC_HDLC 1
  84 #else
  85 #define SYNCLINK_GENERIC_HDLC 0
  86 #endif
  87
  88 /*
  89  * module identification
  90  */
  91 static char *driver_name     = "SyncLink GT";
  92 static char *slgt_driver_name = "synclink_gt";
  93 static char *tty_dev_prefix  = "ttySLG";
  94 MODULE_LICENSE("GPL");
  95 #define MGSL_MAGIC 0x5401
  96 #define MAX_DEVICES 32
  97
  98 static const struct pci_device_id pci_table[] = {
  99         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {0,}, /* terminate list */
 104 };
 105 MODULE_DEVICE_TABLE(pci, pci_table);
 106
 107 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 108 static void remove_one(struct pci_dev *dev);
 109 static struct pci_driver pci_driver = {
 110         .name           = "synclink_gt",
 111         .id_table       = pci_table,
 112         .probe          = init_one,
 113         .remove         = remove_one,
 114 };
 115
 116 static bool pci_registered;
 117
 118 /*
 119  * module configuration and status
 120  */
 121 static struct slgt_info *slgt_device_list;
 122 static int slgt_device_count;
 123
 124 static int ttymajor;
 125 static int debug_level;
 126 static int maxframe[MAX_DEVICES];
 127
 128 module_param(ttymajor, int, 0);
 129 module_param(debug_level, int, 0);
 130 module_param_array(maxframe, int, NULL, 0);
 131
 132 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 133 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 134 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 135
 136 /*
 137  * tty support and callbacks
 138  */
 139 static struct tty_driver *serial_driver;
 140
 141 static int  open(struct tty_struct *tty, struct file * filp);
 142 static void close(struct tty_struct *tty, struct file * filp);
 143 static void hangup(struct tty_struct *tty);
 144 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 145
 146 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 147 static int put_char(struct tty_struct *tty, unsigned char ch);
 148 static void send_xchar(struct tty_struct *tty, char ch);
 149 static void wait_until_sent(struct tty_struct *tty, int timeout);
 150 static int  write_room(struct tty_struct *tty);
 151 static void flush_chars(struct tty_struct *tty);
 152 static void flush_buffer(struct tty_struct *tty);
 153 static void tx_hold(struct tty_struct *tty);
 154 static void tx_release(struct tty_struct *tty);
 155
 156 static int  ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
 157 static int  chars_in_buffer(struct tty_struct *tty);
 158 static void throttle(struct tty_struct * tty);
 159 static void unthrottle(struct tty_struct * tty);
 160 static int set_break(struct tty_struct *tty, int break_state);
 161
 162 /*
 163  * generic HDLC support and callbacks
 164  */
 165 #if SYNCLINK_GENERIC_HDLC
 166 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 167 static void hdlcdev_tx_done(struct slgt_info *info);
 168 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 169 static int  hdlcdev_init(struct slgt_info *info);
 170 static void hdlcdev_exit(struct slgt_info *info);
 171 #endif
 172
 173
 174 /*
 175  * device specific structures, macros and functions
 176  */
 177
 178 #define SLGT_MAX_PORTS 4
 179 #define SLGT_REG_SIZE  256
 180
 181 /*
 182  * conditional wait facility
 183  */
 184 struct cond_wait {
 185         struct cond_wait *next;
 186         wait_queue_head_t q;
 187         wait_queue_entry_t wait;
 188         unsigned int data;
 189 };
 190 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 191 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 192 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 193 static void flush_cond_wait(struct cond_wait **head);
 194
 195 /*
 196  * DMA buffer descriptor and access macros
 197  */
 198 struct slgt_desc
 199 {
 200         __le16 count;
 201         __le16 status;
 202         __le32 pbuf;  /* physical address of data buffer */
 203         __le32 next;  /* physical address of next descriptor */
 204
 205         /* driver book keeping */
 206         char *buf;          /* virtual  address of data buffer */
 207         unsigned int pdesc; /* physical address of this descriptor */
 208         dma_addr_t buf_dma_addr;
 209         unsigned short buf_count;
 210 };
 211
 212 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 213 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 214 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 215 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 216 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 217 #define desc_count(a)      (le16_to_cpu((a).count))
 218 #define desc_status(a)     (le16_to_cpu((a).status))
 219 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 220 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 221 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 222 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 223 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 224
 225 struct _input_signal_events {
 226         int ri_up;
 227         int ri_down;
 228         int dsr_up;
 229         int dsr_down;
 230         int dcd_up;
 231         int dcd_down;
 232         int cts_up;
 233         int cts_down;
 234 };
 235
 236 /*
 237  * device instance data structure
 238  */
 239 struct slgt_info {
 240         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 241         struct tty_port port;
 242
 243         struct slgt_info *next_device;  /* device list link */
 244
 245         int magic;
 246
 247         char device_name[25];
 248         struct pci_dev *pdev;
 249
 250         int port_count;  /* count of ports on adapter */
 251         int adapter_num; /* adapter instance number */
 252         int port_num;    /* port instance number */
 253
 254         /* array of pointers to port contexts on this adapter */
 255         struct slgt_info *port_array[SLGT_MAX_PORTS];
 256
 257         int                     line;           /* tty line instance number */
 258
 259         struct mgsl_icount      icount;
 260
 261         int                     timeout;
 262         int                     x_char;         /* xon/xoff character */
 263         unsigned int            read_status_mask;
 264         unsigned int            ignore_status_mask;
 265
 266         wait_queue_head_t       status_event_wait_q;
 267         wait_queue_head_t       event_wait_q;
 268         struct timer_list       tx_timer;
 269         struct timer_list       rx_timer;
 270
 271         unsigned int            gpio_present;
 272         struct cond_wait        *gpio_wait_q;
 273
 274         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 275
 276         struct work_struct task;
 277         u32 pending_bh;
 278         bool bh_requested;
 279         bool bh_running;
 280
 281         int isr_overflow;
 282         bool irq_requested;     /* true if IRQ requested */
 283         bool irq_occurred;      /* for diagnostics use */
 284
 285         /* device configuration */
 286
 287         unsigned int bus_type;
 288         unsigned int irq_level;
 289         unsigned long irq_flags;
 290
 291         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 292         u32 phys_reg_addr;
 293         bool reg_addr_requested;
 294
 295         MGSL_PARAMS params;       /* communications parameters */
 296         u32 idle_mode;
 297         u32 max_frame_size;       /* as set by device config */
 298
 299         unsigned int rbuf_fill_level;
 300         unsigned int rx_pio;
 301         unsigned int if_mode;
 302         unsigned int base_clock;
 303         unsigned int xsync;
 304         unsigned int xctrl;
 305
 306         /* device status */
 307
 308         bool rx_enabled;
 309         bool rx_restart;
 310
 311         bool tx_enabled;
 312         bool tx_active;
 313
 314         unsigned char signals;    /* serial signal states */
 315         int init_error;  /* initialization error */
 316
 317         unsigned char *tx_buf;
 318         int tx_count;
 319
 320         char *flag_buf;
 321         bool drop_rts_on_tx_done;
 322         struct  _input_signal_events    input_signal_events;
 323
 324         int dcd_chkcount;       /* check counts to prevent */
 325         int cts_chkcount;       /* too many IRQs if a signal */
 326         int dsr_chkcount;       /* is floating */
 327         int ri_chkcount;
 328
 329         char *bufs;             /* virtual address of DMA buffer lists */
 330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332         unsigned int rbuf_count;
 333         struct slgt_desc *rbufs;
 334         unsigned int rbuf_current;
 335         unsigned int rbuf_index;
 336         unsigned int rbuf_fill_index;
 337         unsigned short rbuf_fill_count;
 338
 339         unsigned int tbuf_count;
 340         struct slgt_desc *tbufs;
 341         unsigned int tbuf_current;
 342         unsigned int tbuf_start;
 343
 344         unsigned char *tmp_rbuf;
 345         unsigned int tmp_rbuf_count;
 346
 347         /* SPPP/Cisco HDLC device parts */
 348
 349         int netcount;
 350         spinlock_t netlock;
 351 #if SYNCLINK_GENERIC_HDLC
 352         struct net_device *netdev;
 353 #endif
 354
 355 };
 356
 357 static MGSL_PARAMS default_params = {
 358         .mode            = MGSL_MODE_HDLC,
 359         .loopback        = 0,
 360         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 361         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 362         .clock_speed     = 0,
 363         .addr_filter     = 0xff,
 364         .crc_type        = HDLC_CRC_16_CCITT,
 365         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 366         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 367         .data_rate       = 9600,
 368         .data_bits       = 8,
 369         .stop_bits       = 1,
 370         .parity          = ASYNC_PARITY_NONE
 371 };
 372
 373
 374 #define BH_RECEIVE  1
 375 #define BH_TRANSMIT 2
 376 #define BH_STATUS   4
 377 #define IO_PIN_SHUTDOWN_LIMIT 100
 378
 379 #define DMABUFSIZE 256
 380 #define DESC_LIST_SIZE 4096
 381
 382 #define MASK_PARITY  BIT1
 383 #define MASK_FRAMING BIT0
 384 #define MASK_BREAK   BIT14
 385 #define MASK_OVERRUN BIT4
 386
 387 #define GSR   0x00 /* global status */
 388 #define JCR   0x04 /* JTAG control */
 389 #define IODR  0x08 /* GPIO direction */
 390 #define IOER  0x0c /* GPIO interrupt enable */
 391 #define IOVR  0x10 /* GPIO value */
 392 #define IOSR  0x14 /* GPIO interrupt status */
 393 #define TDR   0x80 /* tx data */
 394 #define RDR   0x80 /* rx data */
 395 #define TCR   0x82 /* tx control */
 396 #define TIR   0x84 /* tx idle */
 397 #define TPR   0x85 /* tx preamble */
 398 #define RCR   0x86 /* rx control */
 399 #define VCR   0x88 /* V.24 control */
 400 #define CCR   0x89 /* clock control */
 401 #define BDR   0x8a /* baud divisor */
 402 #define SCR   0x8c /* serial control */
 403 #define SSR   0x8e /* serial status */
 404 #define RDCSR 0x90 /* rx DMA control/status */
 405 #define TDCSR 0x94 /* tx DMA control/status */
 406 #define RDDAR 0x98 /* rx DMA descriptor address */
 407 #define TDDAR 0x9c /* tx DMA descriptor address */
 408 #define XSR   0x40 /* extended sync pattern */
 409 #define XCR   0x44 /* extended control */
 410
 411 #define RXIDLE      BIT14
 412 #define RXBREAK     BIT14
 413 #define IRQ_TXDATA  BIT13
 414 #define IRQ_TXIDLE  BIT12
 415 #define IRQ_TXUNDER BIT11 /* HDLC */
 416 #define IRQ_RXDATA  BIT10
 417 #define IRQ_RXIDLE  BIT9  /* HDLC */
 418 #define IRQ_RXBREAK BIT9  /* async */
 419 #define IRQ_RXOVER  BIT8
 420 #define IRQ_DSR     BIT7
 421 #define IRQ_CTS     BIT6
 422 #define IRQ_DCD     BIT5
 423 #define IRQ_RI      BIT4
 424 #define IRQ_ALL     0x3ff0
 425 #define IRQ_MASTER  BIT0
 426
 427 #define slgt_irq_on(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 429 #define slgt_irq_off(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 431
 432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 438
 439 static void  msc_set_vcr(struct slgt_info *info);
 440
 441 static int  startup(struct slgt_info *info);
 442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 443 static void shutdown(struct slgt_info *info);
 444 static void program_hw(struct slgt_info *info);
 445 static void change_params(struct slgt_info *info);
 446
 447 static int  register_test(struct slgt_info *info);
 448 static int  irq_test(struct slgt_info *info);
 449 static int  loopback_test(struct slgt_info *info);
 450 static int  adapter_test(struct slgt_info *info);
 451
 452 static void reset_adapter(struct slgt_info *info);
 453 static void reset_port(struct slgt_info *info);
 454 static void async_mode(struct slgt_info *info);
 455 static void sync_mode(struct slgt_info *info);
 456
 457 static void rx_stop(struct slgt_info *info);
 458 static void rx_start(struct slgt_info *info);
 459 static void reset_rbufs(struct slgt_info *info);
 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 461 static void rdma_reset(struct slgt_info *info);
 462 static bool rx_get_frame(struct slgt_info *info);
 463 static bool rx_get_buf(struct slgt_info *info);
 464
 465 static void tx_start(struct slgt_info *info);
 466 static void tx_stop(struct slgt_info *info);
 467 static void tx_set_idle(struct slgt_info *info);
 468 static unsigned int free_tbuf_count(struct slgt_info *info);
 469 static unsigned int tbuf_bytes(struct slgt_info *info);
 470 static void reset_tbufs(struct slgt_info *info);
 471 static void tdma_reset(struct slgt_info *info);
 472 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 473
 474 static void get_signals(struct slgt_info *info);
 475 static void set_signals(struct slgt_info *info);
 476 static void enable_loopback(struct slgt_info *info);
 477 static void set_rate(struct slgt_info *info, u32 data_rate);
 478
 479 static int  bh_action(struct slgt_info *info);
 480 static void bh_handler(struct work_struct *work);
 481 static void bh_transmit(struct slgt_info *info);
 482 static void isr_serial(struct slgt_info *info);
 483 static void isr_rdma(struct slgt_info *info);
 484 static void isr_txeom(struct slgt_info *info, unsigned short status);
 485 static void isr_tdma(struct slgt_info *info);
 486
 487 static int  alloc_dma_bufs(struct slgt_info *info);
 488 static void free_dma_bufs(struct slgt_info *info);
 489 static int  alloc_desc(struct slgt_info *info);
 490 static void free_desc(struct slgt_info *info);
 491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 493
 494 static int  alloc_tmp_rbuf(struct slgt_info *info);
 495 static void free_tmp_rbuf(struct slgt_info *info);
 496
 497 static void tx_timeout(unsigned long context);
 498 static void rx_timeout(unsigned long context);
 499
 500 /*
 501  * ioctl handlers
 502  */
 503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 507 static int  set_txidle(struct slgt_info *info, int idle_mode);
 508 static int  tx_enable(struct slgt_info *info, int enable);
 509 static int  tx_abort(struct slgt_info *info);
 510 static int  rx_enable(struct slgt_info *info, int enable);
 511 static int  modem_input_wait(struct slgt_info *info,int arg);
 512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 513 static int  tiocmget(struct tty_struct *tty);
 514 static int  tiocmset(struct tty_struct *tty,
 515                                 unsigned int set, unsigned int clear);
 516 static int set_break(struct tty_struct *tty, int break_state);
 517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 518 static int  set_interface(struct slgt_info *info, int if_mode);
 519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522 static int  get_xsync(struct slgt_info *info, int __user *if_mode);
 523 static int  set_xsync(struct slgt_info *info, int if_mode);
 524 static int  get_xctrl(struct slgt_info *info, int __user *if_mode);
 525 static int  set_xctrl(struct slgt_info *info, int if_mode);
 526
 527 /*
 528  * driver functions
 529  */
 530 static void add_device(struct slgt_info *info);
 531 static void device_init(int adapter_num, struct pci_dev *pdev);
 532 static int  claim_resources(struct slgt_info *info);
 533 static void release_resources(struct slgt_info *info);
 534
 535 /*
 536  * DEBUG OUTPUT CODE
 537  */
 538 #ifndef DBGINFO
 539 #define DBGINFO(fmt)
 540 #endif
 541 #ifndef DBGERR
 542 #define DBGERR(fmt)
 543 #endif
 544 #ifndef DBGBH
 545 #define DBGBH(fmt)
 546 #endif
 547 #ifndef DBGISR
 548 #define DBGISR(fmt)
 549 #endif
 550
 551 #ifdef DBGDATA
 552 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 553 {
 554         int i;
 555         int linecount;
 556         printk("%s %s data:\n",info->device_name, label);
 557         while(count) {
 558                 linecount = (count > 16) ? 16 : count;
 559                 for(i=0; i < linecount; i++)
 560                         printk("%02X ",(unsigned char)data[i]);
 561                 for(;i<17;i++)
 562                         printk("   ");
 563                 for(i=0;i<linecount;i++) {
 564                         if (data[i]>=040 && data[i]<=0176)
 565                                 printk("%c",data[i]);
 566                         else
 567                                 printk(".");
 568                 }
 569                 printk("\n");
 570                 data  += linecount;
 571                 count -= linecount;
 572         }
 573 }
 574 #else
 575 #define DBGDATA(info, buf, size, label)
 576 #endif
 577
 578 #ifdef DBGTBUF
 579 static void dump_tbufs(struct slgt_info *info)
 580 {
 581         int i;
 582         printk("tbuf_current=%d\n", info->tbuf_current);
 583         for (i=0 ; i < info->tbuf_count ; i++) {
 584                 printk("%d: count=%04X status=%04X\n",
 585                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 586         }
 587 }
 588 #else
 589 #define DBGTBUF(info)
 590 #endif
 591
 592 #ifdef DBGRBUF
 593 static void dump_rbufs(struct slgt_info *info)
 594 {
 595         int i;
 596         printk("rbuf_current=%d\n", info->rbuf_current);
 597         for (i=0 ; i < info->rbuf_count ; i++) {
 598                 printk("%d: count=%04X status=%04X\n",
 599                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 600         }
 601 }
 602 #else
 603 #define DBGRBUF(info)
 604 #endif
 605
 606 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 607 {
 608 #ifdef SANITY_CHECK
 609         if (!info) {
 610                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 611                 return 1;
 612         }
 613         if (info->magic != MGSL_MAGIC) {
 614                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 615                 return 1;
 616         }
 617 #else
 618         if (!info)
 619                 return 1;
 620 #endif
 621         return 0;
 622 }
 623
 624 /**
 625  * line discipline callback wrappers
 626  *
 627  * The wrappers maintain line discipline references
 628  * while calling into the line discipline.
 629  *
 630  * ldisc_receive_buf  - pass receive data to line discipline
 631  */
 632 static void ldisc_receive_buf(struct tty_struct *tty,
 633                               const __u8 *data, char *flags, int count)
 634 {
 635         struct tty_ldisc *ld;
 636         if (!tty)
 637                 return;
 638         ld = tty_ldisc_ref(tty);
 639         if (ld) {
 640                 if (ld->ops->receive_buf)
 641                         ld->ops->receive_buf(tty, data, flags, count);
 642                 tty_ldisc_deref(ld);
 643         }
 644 }
 645
 646 /* tty callbacks */
 647
 648 static int open(struct tty_struct *tty, struct file *filp)
 649 {
 650         struct slgt_info *info;
 651         int retval, line;
 652         unsigned long flags;
 653
 654         line = tty->index;
 655         if (line >= slgt_device_count) {
 656                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 657                 return -ENODEV;
 658         }
 659
 660         info = slgt_device_list;
 661         while(info && info->line != line)
 662                 info = info->next_device;
 663         if (sanity_check(info, tty->name, "open"))
 664                 return -ENODEV;
 665         if (info->init_error) {
 666                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 667                 return -ENODEV;
 668         }
 669
 670         tty->driver_data = info;
 671         info->port.tty = tty;
 672
 673         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 674
 675         mutex_lock(&info->port.mutex);
 676         info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 677
 678         spin_lock_irqsave(&info->netlock, flags);
 679         if (info->netcount) {
 680                 retval = -EBUSY;
 681                 spin_unlock_irqrestore(&info->netlock, flags);
 682                 mutex_unlock(&info->port.mutex);
 683                 goto cleanup;
 684         }
 685         info->port.count++;
 686         spin_unlock_irqrestore(&info->netlock, flags);
 687
 688         if (info->port.count == 1) {
 689                 /* 1st open on this device, init hardware */
 690                 retval = startup(info);
 691                 if (retval < 0) {
 692                         mutex_unlock(&info->port.mutex);
 693                         goto cleanup;
 694                 }
 695         }
 696         mutex_unlock(&info->port.mutex);
 697         retval = block_til_ready(tty, filp, info);
 698         if (retval) {
 699                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 700                 goto cleanup;
 701         }
 702
 703         retval = 0;
 704
 705 cleanup:
 706         if (retval) {
 707                 if (tty->count == 1)
 708                         info->port.tty = NULL; /* tty layer will release tty struct */
 709                 if(info->port.count)
 710                         info->port.count--;
 711         }
 712
 713         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 714         return retval;
 715 }
 716
 717 static void close(struct tty_struct *tty, struct file *filp)
 718 {
 719         struct slgt_info *info = tty->driver_data;
 720
 721         if (sanity_check(info, tty->name, "close"))
 722                 return;
 723         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 724
 725         if (tty_port_close_start(&info->port, tty, filp) == 0)
 726                 goto cleanup;
 727
 728         mutex_lock(&info->port.mutex);
 729         if (tty_port_initialized(&info->port))
 730                 wait_until_sent(tty, info->timeout);
 731         flush_buffer(tty);
 732         tty_ldisc_flush(tty);
 733
 734         shutdown(info);
 735         mutex_unlock(&info->port.mutex);
 736
 737         tty_port_close_end(&info->port, tty);
 738         info->port.tty = NULL;
 739 cleanup:
 740         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 741 }
 742
 743 static void hangup(struct tty_struct *tty)
 744 {
 745         struct slgt_info *info = tty->driver_data;
 746         unsigned long flags;
 747
 748         if (sanity_check(info, tty->name, "hangup"))
 749                 return;
 750         DBGINFO(("%s hangup\n", info->device_name));
 751
 752         flush_buffer(tty);
 753
 754         mutex_lock(&info->port.mutex);
 755         shutdown(info);
 756
 757         spin_lock_irqsave(&info->port.lock, flags);
 758         info->port.count = 0;
 759         info->port.tty = NULL;
 760         spin_unlock_irqrestore(&info->port.lock, flags);
 761         tty_port_set_active(&info->port, 0);
 762         mutex_unlock(&info->port.mutex);
 763
 764         wake_up_interruptible(&info->port.open_wait);
 765 }
 766
 767 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 768 {
 769         struct slgt_info *info = tty->driver_data;
 770         unsigned long flags;
 771
 772         DBGINFO(("%s set_termios\n", tty->driver->name));
 773
 774         change_params(info);
 775
 776         /* Handle transition to B0 status */
 777         if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
 778                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
 779                 spin_lock_irqsave(&info->lock,flags);
 780                 set_signals(info);
 781                 spin_unlock_irqrestore(&info->lock,flags);
 782         }
 783
 784         /* Handle transition away from B0 status */
 785         if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
 786                 info->signals |= SerialSignal_DTR;
 787                 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
 788                         info->signals |= SerialSignal_RTS;
 789                 spin_lock_irqsave(&info->lock,flags);
 790                 set_signals(info);
 791                 spin_unlock_irqrestore(&info->lock,flags);
 792         }
 793
 794         /* Handle turning off CRTSCTS */
 795         if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
 796                 tty->hw_stopped = 0;
 797                 tx_release(tty);
 798         }
 799 }
 800
 801 static void update_tx_timer(struct slgt_info *info)
 802 {
 803         /*
 804          * use worst case speed of 1200bps to calculate transmit timeout
 805          * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
 806          */
 807         if (info->params.mode == MGSL_MODE_HDLC) {
 808                 int timeout  = (tbuf_bytes(info) * 7) + 1000;
 809                 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
 810         }
 811 }
 812
 813 static int write(struct tty_struct *tty,
 814                  const unsigned char *buf, int count)
 815 {
 816         int ret = 0;
 817         struct slgt_info *info = tty->driver_data;
 818         unsigned long flags;
 819
 820         if (sanity_check(info, tty->name, "write"))
 821                 return -EIO;
 822
 823         DBGINFO(("%s write count=%d\n", info->device_name, count));
 824
 825         if (!info->tx_buf || (count > info->max_frame_size))
 826                 return -EIO;
 827
 828         if (!count || tty->stopped || tty->hw_stopped)
 829                 return 0;
 830
 831         spin_lock_irqsave(&info->lock, flags);
 832
 833         if (info->tx_count) {
 834                 /* send accumulated data from send_char() */
 835                 if (!tx_load(info, info->tx_buf, info->tx_count))
 836                         goto cleanup;
 837                 info->tx_count = 0;
 838         }
 839
 840         if (tx_load(info, buf, count))
 841                 ret = count;
 842
 843 cleanup:
 844         spin_unlock_irqrestore(&info->lock, flags);
 845         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 846         return ret;
 847 }
 848
 849 static int put_char(struct tty_struct *tty, unsigned char ch)
 850 {
 851         struct slgt_info *info = tty->driver_data;
 852         unsigned long flags;
 853         int ret = 0;
 854
 855         if (sanity_check(info, tty->name, "put_char"))
 856                 return 0;
 857         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 858         if (!info->tx_buf)
 859                 return 0;
 860         spin_lock_irqsave(&info->lock,flags);
 861         if (info->tx_count < info->max_frame_size) {
 862                 info->tx_buf[info->tx_count++] = ch;
 863                 ret = 1;
 864         }
 865         spin_unlock_irqrestore(&info->lock,flags);
 866         return ret;
 867 }
 868
 869 static void send_xchar(struct tty_struct *tty, char ch)
 870 {
 871         struct slgt_info *info = tty->driver_data;
 872         unsigned long flags;
 873
 874         if (sanity_check(info, tty->name, "send_xchar"))
 875                 return;
 876         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 877         info->x_char = ch;
 878         if (ch) {
 879                 spin_lock_irqsave(&info->lock,flags);
 880                 if (!info->tx_enabled)
 881                         tx_start(info);
 882                 spin_unlock_irqrestore(&info->lock,flags);
 883         }
 884 }
 885
 886 static void wait_until_sent(struct tty_struct *tty, int timeout)
 887 {
 888         struct slgt_info *info = tty->driver_data;
 889         unsigned long orig_jiffies, char_time;
 890
 891         if (!info )
 892                 return;
 893         if (sanity_check(info, tty->name, "wait_until_sent"))
 894                 return;
 895         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 896         if (!tty_port_initialized(&info->port))
 897                 goto exit;
 898
 899         orig_jiffies = jiffies;
 900
 901         /* Set check interval to 1/5 of estimated time to
 902          * send a character, and make it at least 1. The check
 903          * interval should also be less than the timeout.
 904          * Note: use tight timings here to satisfy the NIST-PCTS.
 905          */
 906
 907         if (info->params.data_rate) {
 908                 char_time = info->timeout/(32 * 5);
 909                 if (!char_time)
 910                         char_time++;
 911         } else
 912                 char_time = 1;
 913
 914         if (timeout)
 915                 char_time = min_t(unsigned long, char_time, timeout);
 916
 917         while (info->tx_active) {
 918                 msleep_interruptible(jiffies_to_msecs(char_time));
 919                 if (signal_pending(current))
 920                         break;
 921                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 922                         break;
 923         }
 924 exit:
 925         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 926 }
 927
 928 static int write_room(struct tty_struct *tty)
 929 {
 930         struct slgt_info *info = tty->driver_data;
 931         int ret;
 932
 933         if (sanity_check(info, tty->name, "write_room"))
 934                 return 0;
 935         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 936         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 937         return ret;
 938 }
 939
 940 static void flush_chars(struct tty_struct *tty)
 941 {
 942         struct slgt_info *info = tty->driver_data;
 943         unsigned long flags;
 944
 945         if (sanity_check(info, tty->name, "flush_chars"))
 946                 return;
 947         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 948
 949         if (info->tx_count <= 0 || tty->stopped ||
 950             tty->hw_stopped || !info->tx_buf)
 951                 return;
 952
 953         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 954
 955         spin_lock_irqsave(&info->lock,flags);
 956         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
 957                 info->tx_count = 0;
 958         spin_unlock_irqrestore(&info->lock,flags);
 959 }
 960
 961 static void flush_buffer(struct tty_struct *tty)
 962 {
 963         struct slgt_info *info = tty->driver_data;
 964         unsigned long flags;
 965
 966         if (sanity_check(info, tty->name, "flush_buffer"))
 967                 return;
 968         DBGINFO(("%s flush_buffer\n", info->device_name));
 969
 970         spin_lock_irqsave(&info->lock, flags);
 971         info->tx_count = 0;
 972         spin_unlock_irqrestore(&info->lock, flags);
 973
 974         tty_wakeup(tty);
 975 }
 976
 977 /*
 978  * throttle (stop) transmitter
 979  */
 980 static void tx_hold(struct tty_struct *tty)
 981 {
 982         struct slgt_info *info = tty->driver_data;
 983         unsigned long flags;
 984
 985         if (sanity_check(info, tty->name, "tx_hold"))
 986                 return;
 987         DBGINFO(("%s tx_hold\n", info->device_name));
 988         spin_lock_irqsave(&info->lock,flags);
 989         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 990                 tx_stop(info);
 991         spin_unlock_irqrestore(&info->lock,flags);
 992 }
 993
 994 /*
 995  * release (start) transmitter
 996  */
 997 static void tx_release(struct tty_struct *tty)
 998 {
 999         struct slgt_info *info = tty->driver_data;
1000         unsigned long flags;
1001
1002         if (sanity_check(info, tty->name, "tx_release"))
1003                 return;
1004         DBGINFO(("%s tx_release\n", info->device_name));
1005         spin_lock_irqsave(&info->lock, flags);
1006         if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1007                 info->tx_count = 0;
1008         spin_unlock_irqrestore(&info->lock, flags);
1009 }
1010
1011 /*
1012  * Service an IOCTL request
1013  *
1014  * Arguments
1015  *
1016  *      tty     pointer to tty instance data
1017  *      cmd     IOCTL command code
1018  *      arg     command argument/context
1019  *
1020  * Return 0 if success, otherwise error code
1021  */
1022 static int ioctl(struct tty_struct *tty,
1023                  unsigned int cmd, unsigned long arg)
1024 {
1025         struct slgt_info *info = tty->driver_data;
1026         void __user *argp = (void __user *)arg;
1027         int ret;
1028
1029         if (sanity_check(info, tty->name, "ioctl"))
1030                 return -ENODEV;
1031         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1032
1033         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1034             (cmd != TIOCMIWAIT)) {
1035                 if (tty_io_error(tty))
1036                     return -EIO;
1037         }
1038
1039         switch (cmd) {
1040         case MGSL_IOCWAITEVENT:
1041                 return wait_mgsl_event(info, argp);
1042         case TIOCMIWAIT:
1043                 return modem_input_wait(info,(int)arg);
1044         case MGSL_IOCSGPIO:
1045                 return set_gpio(info, argp);
1046         case MGSL_IOCGGPIO:
1047                 return get_gpio(info, argp);
1048         case MGSL_IOCWAITGPIO:
1049                 return wait_gpio(info, argp);
1050         case MGSL_IOCGXSYNC:
1051                 return get_xsync(info, argp);
1052         case MGSL_IOCSXSYNC:
1053                 return set_xsync(info, (int)arg);
1054         case MGSL_IOCGXCTRL:
1055                 return get_xctrl(info, argp);
1056         case MGSL_IOCSXCTRL:
1057                 return set_xctrl(info, (int)arg);
1058         }
1059         mutex_lock(&info->port.mutex);
1060         switch (cmd) {
1061         case MGSL_IOCGPARAMS:
1062                 ret = get_params(info, argp);
1063                 break;
1064         case MGSL_IOCSPARAMS:
1065                 ret = set_params(info, argp);
1066                 break;
1067         case MGSL_IOCGTXIDLE:
1068                 ret = get_txidle(info, argp);
1069                 break;
1070         case MGSL_IOCSTXIDLE:
1071                 ret = set_txidle(info, (int)arg);
1072                 break;
1073         case MGSL_IOCTXENABLE:
1074                 ret = tx_enable(info, (int)arg);
1075                 break;
1076         case MGSL_IOCRXENABLE:
1077                 ret = rx_enable(info, (int)arg);
1078                 break;
1079         case MGSL_IOCTXABORT:
1080                 ret = tx_abort(info);
1081                 break;
1082         case MGSL_IOCGSTATS:
1083                 ret = get_stats(info, argp);
1084                 break;
1085         case MGSL_IOCGIF:
1086                 ret = get_interface(info, argp);
1087                 break;
1088         case MGSL_IOCSIF:
1089                 ret = set_interface(info,(int)arg);
1090                 break;
1091         default:
1092                 ret = -ENOIOCTLCMD;
1093         }
1094         mutex_unlock(&info->port.mutex);
1095         return ret;
1096 }
1097
1098 static int get_icount(struct tty_struct *tty,
1099                                 struct serial_icounter_struct *icount)
1100
1101 {
1102         struct slgt_info *info = tty->driver_data;
1103         struct mgsl_icount cnow;        /* kernel counter temps */
1104         unsigned long flags;
1105
1106         spin_lock_irqsave(&info->lock,flags);
1107         cnow = info->icount;
1108         spin_unlock_irqrestore(&info->lock,flags);
1109
1110         icount->cts = cnow.cts;
1111         icount->dsr = cnow.dsr;
1112         icount->rng = cnow.rng;
1113         icount->dcd = cnow.dcd;
1114         icount->rx = cnow.rx;
1115         icount->tx = cnow.tx;
1116         icount->frame = cnow.frame;
1117         icount->overrun = cnow.overrun;
1118         icount->parity = cnow.parity;
1119         icount->brk = cnow.brk;
1120         icount->buf_overrun = cnow.buf_overrun;
1121
1122         return 0;
1123 }
1124
1125 /*
1126  * support for 32 bit ioctl calls on 64 bit systems
1127  */
1128 #ifdef CONFIG_COMPAT
1129 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1130 {
1131         struct MGSL_PARAMS32 tmp_params;
1132
1133         DBGINFO(("%s get_params32\n", info->device_name));
1134         memset(&tmp_params, 0, sizeof(tmp_params));
1135         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1136         tmp_params.loopback        = info->params.loopback;
1137         tmp_params.flags           = info->params.flags;
1138         tmp_params.encoding        = info->params.encoding;
1139         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1140         tmp_params.addr_filter     = info->params.addr_filter;
1141         tmp_params.crc_type        = info->params.crc_type;
1142         tmp_params.preamble_length = info->params.preamble_length;
1143         tmp_params.preamble        = info->params.preamble;
1144         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1145         tmp_params.data_bits       = info->params.data_bits;
1146         tmp_params.stop_bits       = info->params.stop_bits;
1147         tmp_params.parity          = info->params.parity;
1148         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1149                 return -EFAULT;
1150         return 0;
1151 }
1152
1153 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1154 {
1155         struct MGSL_PARAMS32 tmp_params;
1156
1157         DBGINFO(("%s set_params32\n", info->device_name));
1158         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1159                 return -EFAULT;
1160
1161         spin_lock(&info->lock);
1162         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1163                 info->base_clock = tmp_params.clock_speed;
1164         } else {
1165                 info->params.mode            = tmp_params.mode;
1166                 info->params.loopback        = tmp_params.loopback;
1167                 info->params.flags           = tmp_params.flags;
1168                 info->params.encoding        = tmp_params.encoding;
1169                 info->params.clock_speed     = tmp_params.clock_speed;
1170                 info->params.addr_filter     = tmp_params.addr_filter;
1171                 info->params.crc_type        = tmp_params.crc_type;
1172                 info->params.preamble_length = tmp_params.preamble_length;
1173                 info->params.preamble        = tmp_params.preamble;
1174                 info->params.data_rate       = tmp_params.data_rate;
1175                 info->params.data_bits       = tmp_params.data_bits;
1176                 info->params.stop_bits       = tmp_params.stop_bits;
1177                 info->params.parity          = tmp_params.parity;
1178         }
1179         spin_unlock(&info->lock);
1180
1181         program_hw(info);
1182
1183         return 0;
1184 }
1185
1186 static long slgt_compat_ioctl(struct tty_struct *tty,
1187                          unsigned int cmd, unsigned long arg)
1188 {
1189         struct slgt_info *info = tty->driver_data;
1190         int rc;
1191
1192         if (sanity_check(info, tty->name, "compat_ioctl"))
1193                 return -ENODEV;
1194         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1195
1196         switch (cmd) {
1197         case MGSL_IOCSPARAMS32:
1198                 rc = set_params32(info, compat_ptr(arg));
1199                 break;
1200
1201         case MGSL_IOCGPARAMS32:
1202                 rc = get_params32(info, compat_ptr(arg));
1203                 break;
1204
1205         case MGSL_IOCGPARAMS:
1206         case MGSL_IOCSPARAMS:
1207         case MGSL_IOCGTXIDLE:
1208         case MGSL_IOCGSTATS:
1209         case MGSL_IOCWAITEVENT:
1210         case MGSL_IOCGIF:
1211         case MGSL_IOCSGPIO:
1212         case MGSL_IOCGGPIO:
1213         case MGSL_IOCWAITGPIO:
1214         case MGSL_IOCGXSYNC:
1215         case MGSL_IOCGXCTRL:
1216                 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1217                 break;
1218         default:
1219                 rc = ioctl(tty, cmd, arg);
1220         }
1221         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1222         return rc;
1223 }
1224 #else
1225 #define slgt_compat_ioctl NULL
1226 #endif /* ifdef CONFIG_COMPAT */
1227
1228 /*
1229  * proc fs support
1230  */
1231 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1232 {
1233         char stat_buf[30];
1234         unsigned long flags;
1235
1236         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1237                       info->device_name, info->phys_reg_addr,
1238                       info->irq_level, info->max_frame_size);
1239
1240         /* output current serial signal states */
1241         spin_lock_irqsave(&info->lock,flags);
1242         get_signals(info);
1243         spin_unlock_irqrestore(&info->lock,flags);
1244
1245         stat_buf[0] = 0;
1246         stat_buf[1] = 0;
1247         if (info->signals & SerialSignal_RTS)
1248                 strcat(stat_buf, "|RTS");
1249         if (info->signals & SerialSignal_CTS)
1250                 strcat(stat_buf, "|CTS");
1251         if (info->signals & SerialSignal_DTR)
1252                 strcat(stat_buf, "|DTR");
1253         if (info->signals & SerialSignal_DSR)
1254                 strcat(stat_buf, "|DSR");
1255         if (info->signals & SerialSignal_DCD)
1256                 strcat(stat_buf, "|CD");
1257         if (info->signals & SerialSignal_RI)
1258                 strcat(stat_buf, "|RI");
1259
1260         if (info->params.mode != MGSL_MODE_ASYNC) {
1261                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1262                                info->icount.txok, info->icount.rxok);
1263                 if (info->icount.txunder)
1264                         seq_printf(m, " txunder:%d", info->icount.txunder);
1265                 if (info->icount.txabort)
1266                         seq_printf(m, " txabort:%d", info->icount.txabort);
1267                 if (info->icount.rxshort)
1268                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1269                 if (info->icount.rxlong)
1270                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1271                 if (info->icount.rxover)
1272                         seq_printf(m, " rxover:%d", info->icount.rxover);
1273                 if (info->icount.rxcrc)
1274                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1275         } else {
1276                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1277                                info->icount.tx, info->icount.rx);
1278                 if (info->icount.frame)
1279                         seq_printf(m, " fe:%d", info->icount.frame);
1280                 if (info->icount.parity)
1281                         seq_printf(m, " pe:%d", info->icount.parity);
1282                 if (info->icount.brk)
1283                         seq_printf(m, " brk:%d", info->icount.brk);
1284                 if (info->icount.overrun)
1285                         seq_printf(m, " oe:%d", info->icount.overrun);
1286         }
1287
1288         /* Append serial signal status to end */
1289         seq_printf(m, " %s\n", stat_buf+1);
1290
1291         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1292                        info->tx_active,info->bh_requested,info->bh_running,
1293                        info->pending_bh);
1294 }
1295
1296 /* Called to print information about devices
1297  */
1298 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1299 {
1300         struct slgt_info *info;
1301
1302         seq_puts(m, "synclink_gt driver\n");
1303
1304         info = slgt_device_list;
1305         while( info ) {
1306                 line_info(m, info);
1307                 info = info->next_device;
1308         }
1309         return 0;
1310 }
1311
1312 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1313 {
1314         return single_open(file, synclink_gt_proc_show, NULL);
1315 }
1316
1317 static const struct file_operations synclink_gt_proc_fops = {
1318         .owner          = THIS_MODULE,
1319         .open           = synclink_gt_proc_open,
1320         .read           = seq_read,
1321         .llseek         = seq_lseek,
1322         .release        = single_release,
1323 };
1324
1325 /*
1326  * return count of bytes in transmit buffer
1327  */
1328 static int chars_in_buffer(struct tty_struct *tty)
1329 {
1330         struct slgt_info *info = tty->driver_data;
1331         int count;
1332         if (sanity_check(info, tty->name, "chars_in_buffer"))
1333                 return 0;
1334         count = tbuf_bytes(info);
1335         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1336         return count;
1337 }
1338
1339 /*
1340  * signal remote device to throttle send data (our receive data)
1341  */
1342 static void throttle(struct tty_struct * tty)
1343 {
1344         struct slgt_info *info = tty->driver_data;
1345         unsigned long flags;
1346
1347         if (sanity_check(info, tty->name, "throttle"))
1348                 return;
1349         DBGINFO(("%s throttle\n", info->device_name));
1350         if (I_IXOFF(tty))
1351                 send_xchar(tty, STOP_CHAR(tty));
1352         if (C_CRTSCTS(tty)) {
1353                 spin_lock_irqsave(&info->lock,flags);
1354                 info->signals &= ~SerialSignal_RTS;
1355                 set_signals(info);
1356                 spin_unlock_irqrestore(&info->lock,flags);
1357         }
1358 }
1359
1360 /*
1361  * signal remote device to stop throttling send data (our receive data)
1362  */
1363 static void unthrottle(struct tty_struct * tty)
1364 {
1365         struct slgt_info *info = tty->driver_data;
1366         unsigned long flags;
1367
1368         if (sanity_check(info, tty->name, "unthrottle"))
1369                 return;
1370         DBGINFO(("%s unthrottle\n", info->device_name));
1371         if (I_IXOFF(tty)) {
1372                 if (info->x_char)
1373                         info->x_char = 0;
1374                 else
1375                         send_xchar(tty, START_CHAR(tty));
1376         }
1377         if (C_CRTSCTS(tty)) {
1378                 spin_lock_irqsave(&info->lock,flags);
1379                 info->signals |= SerialSignal_RTS;
1380                 set_signals(info);
1381                 spin_unlock_irqrestore(&info->lock,flags);
1382         }
1383 }
1384
1385 /*
1386  * set or clear transmit break condition
1387  * break_state  -1=set break condition, 0=clear
1388  */
1389 static int set_break(struct tty_struct *tty, int break_state)
1390 {
1391         struct slgt_info *info = tty->driver_data;
1392         unsigned short value;
1393         unsigned long flags;
1394
1395         if (sanity_check(info, tty->name, "set_break"))
1396                 return -EINVAL;
1397         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1398
1399         spin_lock_irqsave(&info->lock,flags);
1400         value = rd_reg16(info, TCR);
1401         if (break_state == -1)
1402                 value |= BIT6;
1403         else
1404                 value &= ~BIT6;
1405         wr_reg16(info, TCR, value);
1406         spin_unlock_irqrestore(&info->lock,flags);
1407         return 0;
1408 }
1409
1410 #if SYNCLINK_GENERIC_HDLC
1411
1412 /**
1413  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1414  * set encoding and frame check sequence (FCS) options
1415  *
1416  * dev       pointer to network device structure
1417  * encoding  serial encoding setting
1418  * parity    FCS setting
1419  *
1420  * returns 0 if success, otherwise error code
1421  */
1422 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1423                           unsigned short parity)
1424 {
1425         struct slgt_info *info = dev_to_port(dev);
1426         unsigned char  new_encoding;
1427         unsigned short new_crctype;
1428
1429         /* return error if TTY interface open */
1430         if (info->port.count)
1431                 return -EBUSY;
1432
1433         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1434
1435         switch (encoding)
1436         {
1437         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1438         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1439         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1440         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1441         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1442         default: return -EINVAL;
1443         }
1444
1445         switch (parity)
1446         {
1447         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1448         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1449         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1450         default: return -EINVAL;
1451         }
1452
1453         info->params.encoding = new_encoding;
1454         info->params.crc_type = new_crctype;
1455
1456         /* if network interface up, reprogram hardware */
1457         if (info->netcount)
1458                 program_hw(info);
1459
1460         return 0;
1461 }
1462
1463 /**
1464  * called by generic HDLC layer to send frame
1465  *
1466  * skb  socket buffer containing HDLC frame
1467  * dev  pointer to network device structure
1468  */
1469 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1470                                       struct net_device *dev)
1471 {
1472         struct slgt_info *info = dev_to_port(dev);
1473         unsigned long flags;
1474
1475         DBGINFO(("%s hdlc_xmit\n", dev->name));
1476
1477         if (!skb->len)
1478                 return NETDEV_TX_OK;
1479
1480         /* stop sending until this frame completes */
1481         netif_stop_queue(dev);
1482
1483         /* update network statistics */
1484         dev->stats.tx_packets++;
1485         dev->stats.tx_bytes += skb->len;
1486
1487         /* save start time for transmit timeout detection */
1488         netif_trans_update(dev);
1489
1490         spin_lock_irqsave(&info->lock, flags);
1491         tx_load(info, skb->data, skb->len);
1492         spin_unlock_irqrestore(&info->lock, flags);
1493
1494         /* done with socket buffer, so free it */
1495         dev_kfree_skb(skb);
1496
1497         return NETDEV_TX_OK;
1498 }
1499
1500 /**
1501  * called by network layer when interface enabled
1502  * claim resources and initialize hardware
1503  *
1504  * dev  pointer to network device structure
1505  *
1506  * returns 0 if success, otherwise error code
1507  */
1508 static int hdlcdev_open(struct net_device *dev)
1509 {
1510         struct slgt_info *info = dev_to_port(dev);
1511         int rc;
1512         unsigned long flags;
1513
1514         if (!try_module_get(THIS_MODULE))
1515                 return -EBUSY;
1516
1517         DBGINFO(("%s hdlcdev_open\n", dev->name));
1518
1519         /* generic HDLC layer open processing */
1520         rc = hdlc_open(dev);
1521         if (rc)
1522                 return rc;
1523
1524         /* arbitrate between network and tty opens */
1525         spin_lock_irqsave(&info->netlock, flags);
1526         if (info->port.count != 0 || info->netcount != 0) {
1527                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1528                 spin_unlock_irqrestore(&info->netlock, flags);
1529                 return -EBUSY;
1530         }
1531         info->netcount=1;
1532         spin_unlock_irqrestore(&info->netlock, flags);
1533
1534         /* claim resources and init adapter */
1535         if ((rc = startup(info)) != 0) {
1536                 spin_lock_irqsave(&info->netlock, flags);
1537                 info->netcount=0;
1538                 spin_unlock_irqrestore(&info->netlock, flags);
1539                 return rc;
1540         }
1541
1542         /* assert RTS and DTR, apply hardware settings */
1543         info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1544         program_hw(info);
1545
1546         /* enable network layer transmit */
1547         netif_trans_update(dev);
1548         netif_start_queue(dev);
1549
1550         /* inform generic HDLC layer of current DCD status */
1551         spin_lock_irqsave(&info->lock, flags);
1552         get_signals(info);
1553         spin_unlock_irqrestore(&info->lock, flags);
1554         if (info->signals & SerialSignal_DCD)
1555                 netif_carrier_on(dev);
1556         else
1557                 netif_carrier_off(dev);
1558         return 0;
1559 }
1560
1561 /**
1562  * called by network layer when interface is disabled
1563  * shutdown hardware and release resources
1564  *
1565  * dev  pointer to network device structure
1566  *
1567  * returns 0 if success, otherwise error code
1568  */
1569 static int hdlcdev_close(struct net_device *dev)
1570 {
1571         struct slgt_info *info = dev_to_port(dev);
1572         unsigned long flags;
1573
1574         DBGINFO(("%s hdlcdev_close\n", dev->name));
1575
1576         netif_stop_queue(dev);
1577
1578         /* shutdown adapter and release resources */
1579         shutdown(info);
1580
1581         hdlc_close(dev);
1582
1583         spin_lock_irqsave(&info->netlock, flags);
1584         info->netcount=0;
1585         spin_unlock_irqrestore(&info->netlock, flags);
1586
1587         module_put(THIS_MODULE);
1588         return 0;
1589 }
1590
1591 /**
1592  * called by network layer to process IOCTL call to network device
1593  *
1594  * dev  pointer to network device structure
1595  * ifr  pointer to network interface request structure
1596  * cmd  IOCTL command code
1597  *
1598  * returns 0 if success, otherwise error code
1599  */
1600 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1601 {
1602         const size_t size = sizeof(sync_serial_settings);
1603         sync_serial_settings new_line;
1604         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1605         struct slgt_info *info = dev_to_port(dev);
1606         unsigned int flags;
1607
1608         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1609
1610         /* return error if TTY interface open */
1611         if (info->port.count)
1612                 return -EBUSY;
1613
1614         if (cmd != SIOCWANDEV)
1615                 return hdlc_ioctl(dev, ifr, cmd);
1616
1617         memset(&new_line, 0, sizeof(new_line));
1618
1619         switch(ifr->ifr_settings.type) {
1620         case IF_GET_IFACE: /* return current sync_serial_settings */
1621
1622                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1623                 if (ifr->ifr_settings.size < size) {
1624                         ifr->ifr_settings.size = size; /* data size wanted */
1625                         return -ENOBUFS;
1626                 }
1627
1628                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1629                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1630                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1631                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1632
1633                 switch (flags){
1634                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1635                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1636                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1637                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1638                 default: new_line.clock_type = CLOCK_DEFAULT;
1639                 }
1640
1641                 new_line.clock_rate = info->params.clock_speed;
1642                 new_line.loopback   = info->params.loopback ? 1:0;
1643
1644                 if (copy_to_user(line, &new_line, size))
1645                         return -EFAULT;
1646                 return 0;
1647
1648         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1649
1650                 if(!capable(CAP_NET_ADMIN))
1651                         return -EPERM;
1652                 if (copy_from_user(&new_line, line, size))
1653                         return -EFAULT;
1654
1655                 switch (new_line.clock_type)
1656                 {
1657                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1658                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1659                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1660                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1661                 case CLOCK_DEFAULT:  flags = info->params.flags &
1662                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1663                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1664                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1665                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1666                 default: return -EINVAL;
1667                 }
1668
1669                 if (new_line.loopback != 0 && new_line.loopback != 1)
1670                         return -EINVAL;
1671
1672                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1673                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1674                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1675                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1676                 info->params.flags |= flags;
1677
1678                 info->params.loopback = new_line.loopback;
1679
1680                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1681                         info->params.clock_speed = new_line.clock_rate;
1682                 else
1683                         info->params.clock_speed = 0;
1684
1685                 /* if network interface up, reprogram hardware */
1686                 if (info->netcount)
1687                         program_hw(info);
1688                 return 0;
1689
1690         default:
1691                 return hdlc_ioctl(dev, ifr, cmd);
1692         }
1693 }
1694
1695 /**
1696  * called by network layer when transmit timeout is detected
1697  *
1698  * dev  pointer to network device structure
1699  */
1700 static void hdlcdev_tx_timeout(struct net_device *dev)
1701 {
1702         struct slgt_info *info = dev_to_port(dev);
1703         unsigned long flags;
1704
1705         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1706
1707         dev->stats.tx_errors++;
1708         dev->stats.tx_aborted_errors++;
1709
1710         spin_lock_irqsave(&info->lock,flags);
1711         tx_stop(info);
1712         spin_unlock_irqrestore(&info->lock,flags);
1713
1714         netif_wake_queue(dev);
1715 }
1716
1717 /**
1718  * called by device driver when transmit completes
1719  * reenable network layer transmit if stopped
1720  *
1721  * info  pointer to device instance information
1722  */
1723 static void hdlcdev_tx_done(struct slgt_info *info)
1724 {
1725         if (netif_queue_stopped(info->netdev))
1726                 netif_wake_queue(info->netdev);
1727 }
1728
1729 /**
1730  * called by device driver when frame received
1731  * pass frame to network layer
1732  *
1733  * info  pointer to device instance information
1734  * buf   pointer to buffer contianing frame data
1735  * size  count of data bytes in buf
1736  */
1737 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1738 {
1739         struct sk_buff *skb = dev_alloc_skb(size);
1740         struct net_device *dev = info->netdev;
1741
1742         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1743
1744         if (skb == NULL) {
1745                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1746                 dev->stats.rx_dropped++;
1747                 return;
1748         }
1749
1750         skb_put_data(skb, buf, size);
1751
1752         skb->protocol = hdlc_type_trans(skb, dev);
1753
1754         dev->stats.rx_packets++;
1755         dev->stats.rx_bytes += size;
1756
1757         netif_rx(skb);
1758 }
1759
1760 static const struct net_device_ops hdlcdev_ops = {
1761         .ndo_open       = hdlcdev_open,
1762         .ndo_stop       = hdlcdev_close,
1763         .ndo_start_xmit = hdlc_start_xmit,
1764         .ndo_do_ioctl   = hdlcdev_ioctl,
1765         .ndo_tx_timeout = hdlcdev_tx_timeout,
1766 };
1767
1768 /**
1769  * called by device driver when adding device instance
1770  * do generic HDLC initialization
1771  *
1772  * info  pointer to device instance information
1773  *
1774  * returns 0 if success, otherwise error code
1775  */
1776 static int hdlcdev_init(struct slgt_info *info)
1777 {
1778         int rc;
1779         struct net_device *dev;
1780         hdlc_device *hdlc;
1781
1782         /* allocate and initialize network and HDLC layer objects */
1783
1784         dev = alloc_hdlcdev(info);
1785         if (!dev) {
1786                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1787                 return -ENOMEM;
1788         }
1789
1790         /* for network layer reporting purposes only */
1791         dev->mem_start = info->phys_reg_addr;
1792         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1793         dev->irq       = info->irq_level;
1794
1795         /* network layer callbacks and settings */
1796         dev->netdev_ops     = &hdlcdev_ops;
1797         dev->watchdog_timeo = 10 * HZ;
1798         dev->tx_queue_len   = 50;
1799
1800         /* generic HDLC layer callbacks and settings */
1801         hdlc         = dev_to_hdlc(dev);
1802         hdlc->attach = hdlcdev_attach;
1803         hdlc->xmit   = hdlcdev_xmit;
1804
1805         /* register objects with HDLC layer */
1806         rc = register_hdlc_device(dev);
1807         if (rc) {
1808                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1809                 free_netdev(dev);
1810                 return rc;
1811         }
1812
1813         info->netdev = dev;
1814         return 0;
1815 }
1816
1817 /**
1818  * called by device driver when removing device instance
1819  * do generic HDLC cleanup
1820  *
1821  * info  pointer to device instance information
1822  */
1823 static void hdlcdev_exit(struct slgt_info *info)
1824 {
1825         if (!info->netdev)
1826                 return;
1827         unregister_hdlc_device(info->netdev);
1828         free_netdev(info->netdev);
1829         info->netdev = NULL;
1830 }
1831
1832 #endif /* ifdef CONFIG_HDLC */
1833
1834 /*
1835  * get async data from rx DMA buffers
1836  */
1837 static void rx_async(struct slgt_info *info)
1838 {
1839         struct mgsl_icount *icount = &info->icount;
1840         unsigned int start, end;
1841         unsigned char *p;
1842         unsigned char status;
1843         struct slgt_desc *bufs = info->rbufs;
1844         int i, count;
1845         int chars = 0;
1846         int stat;
1847         unsigned char ch;
1848
1849         start = end = info->rbuf_current;
1850
1851         while(desc_complete(bufs[end])) {
1852                 count = desc_count(bufs[end]) - info->rbuf_index;
1853                 p     = bufs[end].buf + info->rbuf_index;
1854
1855                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1856                 DBGDATA(info, p, count, "rx");
1857
1858                 for(i=0 ; i < count; i+=2, p+=2) {
1859                         ch = *p;
1860                         icount->rx++;
1861
1862                         stat = 0;
1863
1864                         status = *(p + 1) & (BIT1 + BIT0);
1865                         if (status) {
1866                                 if (status & BIT1)
1867                                         icount->parity++;
1868                                 else if (status & BIT0)
1869                                         icount->frame++;
1870                                 /* discard char if tty control flags say so */
1871                                 if (status & info->ignore_status_mask)
1872                                         continue;
1873                                 if (status & BIT1)
1874                                         stat = TTY_PARITY;
1875                                 else if (status & BIT0)
1876                                         stat = TTY_FRAME;
1877                         }
1878                         tty_insert_flip_char(&info->port, ch, stat);
1879                         chars++;
1880                 }
1881
1882                 if (i < count) {
1883                         /* receive buffer not completed */
1884                         info->rbuf_index += i;
1885                         mod_timer(&info->rx_timer, jiffies + 1);
1886                         break;
1887                 }
1888
1889                 info->rbuf_index = 0;
1890                 free_rbufs(info, end, end);
1891
1892                 if (++end == info->rbuf_count)
1893                         end = 0;
1894
1895                 /* if entire list searched then no frame available */
1896                 if (end == start)
1897                         break;
1898         }
1899
1900         if (chars)
1901                 tty_flip_buffer_push(&info->port);
1902 }
1903
1904 /*
1905  * return next bottom half action to perform
1906  */
1907 static int bh_action(struct slgt_info *info)
1908 {
1909         unsigned long flags;
1910         int rc;
1911
1912         spin_lock_irqsave(&info->lock,flags);
1913
1914         if (info->pending_bh & BH_RECEIVE) {
1915                 info->pending_bh &= ~BH_RECEIVE;
1916                 rc = BH_RECEIVE;
1917         } else if (info->pending_bh & BH_TRANSMIT) {
1918                 info->pending_bh &= ~BH_TRANSMIT;
1919                 rc = BH_TRANSMIT;
1920         } else if (info->pending_bh & BH_STATUS) {
1921                 info->pending_bh &= ~BH_STATUS;
1922                 rc = BH_STATUS;
1923         } else {
1924                 /* Mark BH routine as complete */
1925                 info->bh_running = false;
1926                 info->bh_requested = false;
1927                 rc = 0;
1928         }
1929
1930         spin_unlock_irqrestore(&info->lock,flags);
1931
1932         return rc;
1933 }
1934
1935 /*
1936  * perform bottom half processing
1937  */
1938 static void bh_handler(struct work_struct *work)
1939 {
1940         struct slgt_info *info = container_of(work, struct slgt_info, task);
1941         int action;
1942
1943         info->bh_running = true;
1944
1945         while((action = bh_action(info))) {
1946                 switch (action) {
1947                 case BH_RECEIVE:
1948                         DBGBH(("%s bh receive\n", info->device_name));
1949                         switch(info->params.mode) {
1950                         case MGSL_MODE_ASYNC:
1951                                 rx_async(info);
1952                                 break;
1953                         case MGSL_MODE_HDLC:
1954                                 while(rx_get_frame(info));
1955                                 break;
1956                         case MGSL_MODE_RAW:
1957                         case MGSL_MODE_MONOSYNC:
1958                         case MGSL_MODE_BISYNC:
1959                         case MGSL_MODE_XSYNC:
1960                                 while(rx_get_buf(info));
1961                                 break;
1962                         }
1963                         /* restart receiver if rx DMA buffers exhausted */
1964                         if (info->rx_restart)
1965                                 rx_start(info);
1966                         break;
1967                 case BH_TRANSMIT:
1968                         bh_transmit(info);
1969                         break;
1970                 case BH_STATUS:
1971                         DBGBH(("%s bh status\n", info->device_name));
1972                         info->ri_chkcount = 0;
1973                         info->dsr_chkcount = 0;
1974                         info->dcd_chkcount = 0;
1975                         info->cts_chkcount = 0;
1976                         break;
1977                 default:
1978                         DBGBH(("%s unknown action\n", info->device_name));
1979                         break;
1980                 }
1981         }
1982         DBGBH(("%s bh_handler exit\n", info->device_name));
1983 }
1984
1985 static void bh_transmit(struct slgt_info *info)
1986 {
1987         struct tty_struct *tty = info->port.tty;
1988
1989         DBGBH(("%s bh_transmit\n", info->device_name));
1990         if (tty)
1991                 tty_wakeup(tty);
1992 }
1993
1994 static void dsr_change(struct slgt_info *info, unsigned short status)
1995 {
1996         if (status & BIT3) {
1997                 info->signals |= SerialSignal_DSR;
1998                 info->input_signal_events.dsr_up++;
1999         } else {
2000                 info->signals &= ~SerialSignal_DSR;
2001                 info->input_signal_events.dsr_down++;
2002         }
2003         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2004         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2005                 slgt_irq_off(info, IRQ_DSR);
2006                 return;
2007         }
2008         info->icount.dsr++;
2009         wake_up_interruptible(&info->status_event_wait_q);
2010         wake_up_interruptible(&info->event_wait_q);
2011         info->pending_bh |= BH_STATUS;
2012 }
2013
2014 static void cts_change(struct slgt_info *info, unsigned short status)
2015 {
2016         if (status & BIT2) {
2017                 info->signals |= SerialSignal_CTS;
2018                 info->input_signal_events.cts_up++;
2019         } else {
2020                 info->signals &= ~SerialSignal_CTS;
2021                 info->input_signal_events.cts_down++;
2022         }
2023         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2024         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2025                 slgt_irq_off(info, IRQ_CTS);
2026                 return;
2027         }
2028         info->icount.cts++;
2029         wake_up_interruptible(&info->status_event_wait_q);
2030         wake_up_interruptible(&info->event_wait_q);
2031         info->pending_bh |= BH_STATUS;
2032
2033         if (tty_port_cts_enabled(&info->port)) {
2034                 if (info->port.tty) {
2035                         if (info->port.tty->hw_stopped) {
2036                                 if (info->signals & SerialSignal_CTS) {
2037                                         info->port.tty->hw_stopped = 0;
2038                                         info->pending_bh |= BH_TRANSMIT;
2039                                         return;
2040                                 }
2041                         } else {
2042                                 if (!(info->signals & SerialSignal_CTS))
2043                                         info->port.tty->hw_stopped = 1;
2044                         }
2045                 }
2046         }
2047 }
2048
2049 static void dcd_change(struct slgt_info *info, unsigned short status)
2050 {
2051         if (status & BIT1) {
2052                 info->signals |= SerialSignal_DCD;
2053                 info->input_signal_events.dcd_up++;
2054         } else {
2055                 info->signals &= ~SerialSignal_DCD;
2056                 info->input_signal_events.dcd_down++;
2057         }
2058         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2059         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2060                 slgt_irq_off(info, IRQ_DCD);
2061                 return;
2062         }
2063         info->icount.dcd++;
2064 #if SYNCLINK_GENERIC_HDLC
2065         if (info->netcount) {
2066                 if (info->signals & SerialSignal_DCD)
2067                         netif_carrier_on(info->netdev);
2068                 else
2069                         netif_carrier_off(info->netdev);
2070         }
2071 #endif
2072         wake_up_interruptible(&info->status_event_wait_q);
2073         wake_up_interruptible(&info->event_wait_q);
2074         info->pending_bh |= BH_STATUS;
2075
2076         if (tty_port_check_carrier(&info->port)) {
2077                 if (info->signals & SerialSignal_DCD)
2078                         wake_up_interruptible(&info->port.open_wait);
2079                 else {
2080                         if (info->port.tty)
2081                                 tty_hangup(info->port.tty);
2082                 }
2083         }
2084 }
2085
2086 static void ri_change(struct slgt_info *info, unsigned short status)
2087 {
2088         if (status & BIT0) {
2089                 info->signals |= SerialSignal_RI;
2090                 info->input_signal_events.ri_up++;
2091         } else {
2092                 info->signals &= ~SerialSignal_RI;
2093                 info->input_signal_events.ri_down++;
2094         }
2095         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2096         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2097                 slgt_irq_off(info, IRQ_RI);
2098                 return;
2099         }
2100         info->icount.rng++;
2101         wake_up_interruptible(&info->status_event_wait_q);
2102         wake_up_interruptible(&info->event_wait_q);
2103         info->pending_bh |= BH_STATUS;
2104 }
2105
2106 static void isr_rxdata(struct slgt_info *info)
2107 {
2108         unsigned int count = info->rbuf_fill_count;
2109         unsigned int i = info->rbuf_fill_index;
2110         unsigned short reg;
2111
2112         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2113                 reg = rd_reg16(info, RDR);
2114                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2115                 if (desc_complete(info->rbufs[i])) {
2116                         /* all buffers full */
2117                         rx_stop(info);
2118                         info->rx_restart = 1;
2119                         continue;
2120                 }
2121                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2122                 /* async mode saves status byte to buffer for each data byte */
2123                 if (info->params.mode == MGSL_MODE_ASYNC)
2124                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2125                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2126                         /* buffer full or end of frame */
2127                         set_desc_count(info->rbufs[i], count);
2128                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2129                         info->rbuf_fill_count = count = 0;
2130                         if (++i == info->rbuf_count)
2131                                 i = 0;
2132                         info->pending_bh |= BH_RECEIVE;
2133                 }
2134         }
2135
2136         info->rbuf_fill_index = i;
2137         info->rbuf_fill_count = count;
2138 }
2139
2140 static void isr_serial(struct slgt_info *info)
2141 {
2142         unsigned short status = rd_reg16(info, SSR);
2143
2144         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2145
2146         wr_reg16(info, SSR, status); /* clear pending */
2147
2148         info->irq_occurred = true;
2149
2150         if (info->params.mode == MGSL_MODE_ASYNC) {
2151                 if (status & IRQ_TXIDLE) {
2152                         if (info->tx_active)
2153                                 isr_txeom(info, status);
2154                 }
2155                 if (info->rx_pio && (status & IRQ_RXDATA))
2156                         isr_rxdata(info);
2157                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2158                         info->icount.brk++;
2159                         /* process break detection if tty control allows */
2160                         if (info->port.tty) {
2161                                 if (!(status & info->ignore_status_mask)) {
2162                                         if (info->read_status_mask & MASK_BREAK) {
2163                                                 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2164                                                 if (info->port.flags & ASYNC_SAK)
2165                                                         do_SAK(info->port.tty);
2166                                         }
2167                                 }
2168                         }
2169                 }
2170         } else {
2171                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2172                         isr_txeom(info, status);
2173                 if (info->rx_pio && (status & IRQ_RXDATA))
2174                         isr_rxdata(info);
2175                 if (status & IRQ_RXIDLE) {
2176                         if (status & RXIDLE)
2177                                 info->icount.rxidle++;
2178                         else
2179                                 info->icount.exithunt++;
2180                         wake_up_interruptible(&info->event_wait_q);
2181                 }
2182
2183                 if (status & IRQ_RXOVER)
2184                         rx_start(info);
2185         }
2186
2187         if (status & IRQ_DSR)
2188                 dsr_change(info, status);
2189         if (status & IRQ_CTS)
2190                 cts_change(info, status);
2191         if (status & IRQ_DCD)
2192                 dcd_change(info, status);
2193         if (status & IRQ_RI)
2194                 ri_change(info, status);
2195 }
2196
2197 static void isr_rdma(struct slgt_info *info)
2198 {
2199         unsigned int status = rd_reg32(info, RDCSR);
2200
2201         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2202
2203         /* RDCSR (rx DMA control/status)
2204          *
2205          * 31..07  reserved
2206          * 06      save status byte to DMA buffer
2207          * 05      error
2208          * 04      eol (end of list)
2209          * 03      eob (end of buffer)
2210          * 02      IRQ enable
2211          * 01      reset
2212          * 00      enable
2213          */
2214         wr_reg32(info, RDCSR, status);  /* clear pending */
2215
2216         if (status & (BIT5 + BIT4)) {
2217                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2218                 info->rx_restart = true;
2219         }
2220         info->pending_bh |= BH_RECEIVE;
2221 }
2222
2223 static void isr_tdma(struct slgt_info *info)
2224 {
2225         unsigned int status = rd_reg32(info, TDCSR);
2226
2227         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2228
2229         /* TDCSR (tx DMA control/status)
2230          *
2231          * 31..06  reserved
2232          * 05      error
2233          * 04      eol (end of list)
2234          * 03      eob (end of buffer)
2235          * 02      IRQ enable
2236          * 01      reset
2237          * 00      enable
2238          */
2239         wr_reg32(info, TDCSR, status);  /* clear pending */
2240
2241         if (status & (BIT5 + BIT4 + BIT3)) {
2242                 // another transmit buffer has completed
2243                 // run bottom half to get more send data from user
2244                 info->pending_bh |= BH_TRANSMIT;
2245         }
2246 }
2247
2248 /*
2249  * return true if there are unsent tx DMA buffers, otherwise false
2250  *
2251  * if there are unsent buffers then info->tbuf_start
2252  * is set to index of first unsent buffer
2253  */
2254 static bool unsent_tbufs(struct slgt_info *info)
2255 {
2256         unsigned int i = info->tbuf_current;
2257         bool rc = false;
2258
2259         /*
2260          * search backwards from last loaded buffer (precedes tbuf_current)
2261          * for first unsent buffer (desc_count > 0)
2262          */
2263
2264         do {
2265                 if (i)
2266                         i--;
2267                 else
2268                         i = info->tbuf_count - 1;
2269                 if (!desc_count(info->tbufs[i]))
2270                         break;
2271                 info->tbuf_start = i;
2272                 rc = true;
2273         } while (i != info->tbuf_current);
2274
2275         return rc;
2276 }
2277
2278 static void isr_txeom(struct slgt_info *info, unsigned short status)
2279 {
2280         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2281
2282         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2283         tdma_reset(info);
2284         if (status & IRQ_TXUNDER) {
2285                 unsigned short val = rd_reg16(info, TCR);
2286                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2287                 wr_reg16(info, TCR, val); /* clear reset bit */
2288         }
2289
2290         if (info->tx_active) {
2291                 if (info->params.mode != MGSL_MODE_ASYNC) {
2292                         if (status & IRQ_TXUNDER)
2293                                 info->icount.txunder++;
2294                         else if (status & IRQ_TXIDLE)
2295                                 info->icount.txok++;
2296                 }
2297
2298                 if (unsent_tbufs(info)) {
2299                         tx_start(info);
2300                         update_tx_timer(info);
2301                         return;
2302                 }
2303                 info->tx_active = false;
2304
2305                 del_timer(&info->tx_timer);
2306
2307                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2308                         info->signals &= ~SerialSignal_RTS;
2309                         info->drop_rts_on_tx_done = false;
2310                         set_signals(info);
2311                 }
2312
2313 #if SYNCLINK_GENERIC_HDLC
2314                 if (info->netcount)
2315                         hdlcdev_tx_done(info);
2316                 else
2317 #endif
2318                 {
2319                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2320                                 tx_stop(info);
2321                                 return;
2322                         }
2323                         info->pending_bh |= BH_TRANSMIT;
2324                 }
2325         }
2326 }
2327
2328 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2329 {
2330         struct cond_wait *w, *prev;
2331
2332         /* wake processes waiting for specific transitions */
2333         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2334                 if (w->data & changed) {
2335                         w->data = state;
2336                         wake_up_interruptible(&w->q);
2337                         if (prev != NULL)
2338                                 prev->next = w->next;
2339                         else
2340                                 info->gpio_wait_q = w->next;
2341                 } else
2342                         prev = w;
2343         }
2344 }
2345
2346 /* interrupt service routine
2347  *
2348  *      irq     interrupt number
2349  *      dev_id  device ID supplied during interrupt registration
2350  */
2351 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2352 {
2353         struct slgt_info *info = dev_id;
2354         unsigned int gsr;
2355         unsigned int i;
2356
2357         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2358
2359         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2360                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2361                 info->irq_occurred = true;
2362                 for(i=0; i < info->port_count ; i++) {
2363                         if (info->port_array[i] == NULL)
2364                                 continue;
2365                         spin_lock(&info->port_array[i]->lock);
2366                         if (gsr & (BIT8 << i))
2367                                 isr_serial(info->port_array[i]);
2368                         if (gsr & (BIT16 << (i*2)))
2369                                 isr_rdma(info->port_array[i]);
2370                         if (gsr & (BIT17 << (i*2)))
2371                                 isr_tdma(info->port_array[i]);
2372                         spin_unlock(&info->port_array[i]->lock);
2373                 }
2374         }
2375
2376         if (info->gpio_present) {
2377                 unsigned int state;
2378                 unsigned int changed;
2379                 spin_lock(&info->lock);
2380                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2381                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2382                         /* read latched state of GPIO signals */
2383                         state = rd_reg32(info, IOVR);
2384                         /* clear pending GPIO interrupt bits */
2385                         wr_reg32(info, IOSR, changed);
2386                         for (i=0 ; i < info->port_count ; i++) {
2387                                 if (info->port_array[i] != NULL)
2388                                         isr_gpio(info->port_array[i], changed, state);
2389                         }
2390                 }
2391                 spin_unlock(&info->lock);
2392         }
2393
2394         for(i=0; i < info->port_count ; i++) {
2395                 struct slgt_info *port = info->port_array[i];
2396                 if (port == NULL)
2397                         continue;
2398                 spin_lock(&port->lock);
2399                 if ((port->port.count || port->netcount) &&
2400                     port->pending_bh && !port->bh_running &&
2401                     !port->bh_requested) {
2402                         DBGISR(("%s bh queued\n", port->device_name));
2403                         schedule_work(&port->task);
2404                         port->bh_requested = true;
2405                 }
2406                 spin_unlock(&port->lock);
2407         }
2408
2409         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2410         return IRQ_HANDLED;
2411 }
2412
2413 static int startup(struct slgt_info *info)
2414 {
2415         DBGINFO(("%s startup\n", info->device_name));
2416
2417         if (tty_port_initialized(&info->port))
2418                 return 0;
2419
2420         if (!info->tx_buf) {
2421                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2422                 if (!info->tx_buf) {
2423                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2424                         return -ENOMEM;
2425                 }
2426         }
2427
2428         info->pending_bh = 0;
2429
2430         memset(&info->icount, 0, sizeof(info->icount));
2431
2432         /* program hardware for current parameters */
2433         change_params(info);
2434
2435         if (info->port.tty)
2436                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2437
2438         tty_port_set_initialized(&info->port, 1);
2439
2440         return 0;
2441 }
2442
2443 /*
2444  *  called by close() and hangup() to shutdown hardware
2445  */
2446 static void shutdown(struct slgt_info *info)
2447 {
2448         unsigned long flags;
2449
2450         if (!tty_port_initialized(&info->port))
2451                 return;
2452
2453         DBGINFO(("%s shutdown\n", info->device_name));
2454
2455         /* clear status wait queue because status changes */
2456         /* can't happen after shutting down the hardware */
2457         wake_up_interruptible(&info->status_event_wait_q);
2458         wake_up_interruptible(&info->event_wait_q);
2459
2460         del_timer_sync(&info->tx_timer);
2461         del_timer_sync(&info->rx_timer);
2462
2463         kfree(info->tx_buf);
2464         info->tx_buf = NULL;
2465
2466         spin_lock_irqsave(&info->lock,flags);
2467
2468         tx_stop(info);
2469         rx_stop(info);
2470
2471         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2472
2473         if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2474                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2475                 set_signals(info);
2476         }
2477
2478         flush_cond_wait(&info->gpio_wait_q);
2479
2480         spin_unlock_irqrestore(&info->lock,flags);
2481
2482         if (info->port.tty)
2483                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2484
2485         tty_port_set_initialized(&info->port, 0);
2486 }
2487
2488 static void program_hw(struct slgt_info *info)
2489 {
2490         unsigned long flags;
2491
2492         spin_lock_irqsave(&info->lock,flags);
2493
2494         rx_stop(info);
2495         tx_stop(info);
2496
2497         if (info->params.mode != MGSL_MODE_ASYNC ||
2498             info->netcount)
2499                 sync_mode(info);
2500         else
2501                 async_mode(info);
2502
2503         set_signals(info);
2504
2505         info->dcd_chkcount = 0;
2506         info->cts_chkcount = 0;
2507         info->ri_chkcount = 0;
2508         info->dsr_chkcount = 0;
2509
2510         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2511         get_signals(info);
2512
2513         if (info->netcount ||
2514             (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2515                 rx_start(info);
2516
2517         spin_unlock_irqrestore(&info->lock,flags);
2518 }
2519
2520 /*
2521  * reconfigure adapter based on new parameters
2522  */
2523 static void change_params(struct slgt_info *info)
2524 {
2525         unsigned cflag;
2526         int bits_per_char;
2527
2528         if (!info->port.tty)
2529                 return;
2530         DBGINFO(("%s change_params\n", info->device_name));
2531
2532         cflag = info->port.tty->termios.c_cflag;
2533
2534         /* if B0 rate (hangup) specified then negate RTS and DTR */
2535         /* otherwise assert RTS and DTR */
2536         if (cflag & CBAUD)
2537                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2538         else
2539                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2540
2541         /* byte size and parity */
2542
2543         switch (cflag & CSIZE) {
2544         case CS5: info->params.data_bits = 5; break;
2545         case CS6: info->params.data_bits = 6; break;
2546         case CS7: info->params.data_bits = 7; break;
2547         case CS8: info->params.data_bits = 8; break;
2548         default:  info->params.data_bits = 7; break;
2549         }
2550
2551         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2552
2553         if (cflag & PARENB)
2554                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2555         else
2556                 info->params.parity = ASYNC_PARITY_NONE;
2557
2558         /* calculate number of jiffies to transmit a full
2559          * FIFO (32 bytes) at specified data rate
2560          */
2561         bits_per_char = info->params.data_bits +
2562                         info->params.stop_bits + 1;
2563
2564         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2565
2566         if (info->params.data_rate) {
2567                 info->timeout = (32*HZ*bits_per_char) /
2568                                 info->params.data_rate;
2569         }
2570         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2571
2572         tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2573         tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2574
2575         /* process tty input control flags */
2576
2577         info->read_status_mask = IRQ_RXOVER;
2578         if (I_INPCK(info->port.tty))
2579                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2580         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2581                 info->read_status_mask |= MASK_BREAK;
2582         if (I_IGNPAR(info->port.tty))
2583                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2584         if (I_IGNBRK(info->port.tty)) {
2585                 info->ignore_status_mask |= MASK_BREAK;
2586                 /* If ignoring parity and break indicators, ignore
2587                  * overruns too.  (For real raw support).
2588                  */
2589                 if (I_IGNPAR(info->port.tty))
2590                         info->ignore_status_mask |= MASK_OVERRUN;
2591         }
2592
2593         program_hw(info);
2594 }
2595
2596 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2597 {
2598         DBGINFO(("%s get_stats\n",  info->device_name));
2599         if (!user_icount) {
2600                 memset(&info->icount, 0, sizeof(info->icount));
2601         } else {
2602                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2603                         return -EFAULT;
2604         }
2605         return 0;
2606 }
2607
2608 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2609 {
2610         DBGINFO(("%s get_params\n", info->device_name));
2611         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2612                 return -EFAULT;
2613         return 0;
2614 }
2615
2616 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2617 {
2618         unsigned long flags;
2619         MGSL_PARAMS tmp_params;
2620
2621         DBGINFO(("%s set_params\n", info->device_name));
2622         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2623                 return -EFAULT;
2624
2625         spin_lock_irqsave(&info->lock, flags);
2626         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2627                 info->base_clock = tmp_params.clock_speed;
2628         else
2629                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2630         spin_unlock_irqrestore(&info->lock, flags);
2631
2632         program_hw(info);
2633
2634         return 0;
2635 }
2636
2637 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2638 {
2639         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2640         if (put_user(info->idle_mode, idle_mode))
2641                 return -EFAULT;
2642         return 0;
2643 }
2644
2645 static int set_txidle(struct slgt_info *info, int idle_mode)
2646 {
2647         unsigned long flags;
2648         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2649         spin_lock_irqsave(&info->lock,flags);
2650         info->idle_mode = idle_mode;
2651         if (info->params.mode != MGSL_MODE_ASYNC)
2652                 tx_set_idle(info);
2653         spin_unlock_irqrestore(&info->lock,flags);
2654         return 0;
2655 }
2656
2657 static int tx_enable(struct slgt_info *info, int enable)
2658 {
2659         unsigned long flags;
2660         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2661         spin_lock_irqsave(&info->lock,flags);
2662         if (enable) {
2663                 if (!info->tx_enabled)
2664                         tx_start(info);
2665         } else {
2666                 if (info->tx_enabled)
2667                         tx_stop(info);
2668         }
2669         spin_unlock_irqrestore(&info->lock,flags);
2670         return 0;
2671 }
2672
2673 /*
2674  * abort transmit HDLC frame
2675  */
2676 static int tx_abort(struct slgt_info *info)
2677 {
2678         unsigned long flags;
2679         DBGINFO(("%s tx_abort\n", info->device_name));
2680         spin_lock_irqsave(&info->lock,flags);
2681         tdma_reset(info);
2682         spin_unlock_irqrestore(&info->lock,flags);
2683         return 0;
2684 }
2685
2686 static int rx_enable(struct slgt_info *info, int enable)
2687 {
2688         unsigned long flags;
2689         unsigned int rbuf_fill_level;
2690         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2691         spin_lock_irqsave(&info->lock,flags);
2692         /*
2693          * enable[31..16] = receive DMA buffer fill level
2694          * 0 = noop (leave fill level unchanged)
2695          * fill level must be multiple of 4 and <= buffer size
2696          */
2697         rbuf_fill_level = ((unsigned int)enable) >> 16;
2698         if (rbuf_fill_level) {
2699                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2700                         spin_unlock_irqrestore(&info->lock, flags);
2701                         return -EINVAL;
2702                 }
2703                 info->rbuf_fill_level = rbuf_fill_level;
2704                 if (rbuf_fill_level < 128)
2705                         info->rx_pio = 1; /* PIO mode */
2706                 else
2707                         info->rx_pio = 0; /* DMA mode */
2708                 rx_stop(info); /* restart receiver to use new fill level */
2709         }
2710
2711         /*
2712          * enable[1..0] = receiver enable command
2713          * 0 = disable
2714          * 1 = enable
2715          * 2 = enable or force hunt mode if already enabled
2716          */
2717         enable &= 3;
2718         if (enable) {
2719                 if (!info->rx_enabled)
2720                         rx_start(info);
2721                 else if (enable == 2) {
2722                         /* force hunt mode (write 1 to RCR[3]) */
2723                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2724                 }
2725         } else {
2726                 if (info->rx_enabled)
2727                         rx_stop(info);
2728         }
2729         spin_unlock_irqrestore(&info->lock,flags);
2730         return 0;
2731 }
2732
2733 /*
2734  *  wait for specified event to occur
2735  */
2736 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2737 {
2738         unsigned long flags;
2739         int s;
2740         int rc=0;
2741         struct mgsl_icount cprev, cnow;
2742         int events;
2743         int mask;
2744         struct  _input_signal_events oldsigs, newsigs;
2745         DECLARE_WAITQUEUE(wait, current);
2746
2747         if (get_user(mask, mask_ptr))
2748                 return -EFAULT;
2749
2750         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2751
2752         spin_lock_irqsave(&info->lock,flags);
2753
2754         /* return immediately if state matches requested events */
2755         get_signals(info);
2756         s = info->signals;
2757
2758         events = mask &
2759                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2760                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2761                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2762                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2763         if (events) {
2764                 spin_unlock_irqrestore(&info->lock,flags);
2765                 goto exit;
2766         }
2767
2768         /* save current irq counts */
2769         cprev = info->icount;
2770         oldsigs = info->input_signal_events;
2771
2772         /* enable hunt and idle irqs if needed */
2773         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2774                 unsigned short val = rd_reg16(info, SCR);
2775                 if (!(val & IRQ_RXIDLE))
2776                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2777         }
2778
2779         set_current_state(TASK_INTERRUPTIBLE);
2780         add_wait_queue(&info->event_wait_q, &wait);
2781
2782         spin_unlock_irqrestore(&info->lock,flags);
2783
2784         for(;;) {
2785                 schedule();
2786                 if (signal_pending(current)) {
2787                         rc = -ERESTARTSYS;
2788                         break;
2789                 }
2790
2791                 /* get current irq counts */
2792                 spin_lock_irqsave(&info->lock,flags);
2793                 cnow = info->icount;
2794                 newsigs = info->input_signal_events;
2795                 set_current_state(TASK_INTERRUPTIBLE);
2796                 spin_unlock_irqrestore(&info->lock,flags);
2797
2798                 /* if no change, wait aborted for some reason */
2799                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2800                     newsigs.dsr_down == oldsigs.dsr_down &&
2801                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2802                     newsigs.dcd_down == oldsigs.dcd_down &&
2803                     newsigs.cts_up   == oldsigs.cts_up   &&
2804                     newsigs.cts_down == oldsigs.cts_down &&
2805                     newsigs.ri_up    == oldsigs.ri_up    &&
2806                     newsigs.ri_down  == oldsigs.ri_down  &&
2807                     cnow.exithunt    == cprev.exithunt   &&
2808                     cnow.rxidle      == cprev.rxidle) {
2809                         rc = -EIO;
2810                         break;
2811                 }
2812
2813                 events = mask &
2814                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2815                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2816                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2817                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2818                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2819                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2820                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2821                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2822                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2823                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2824                 if (events)
2825                         break;
2826
2827                 cprev = cnow;
2828                 oldsigs = newsigs;
2829         }
2830
2831         remove_wait_queue(&info->event_wait_q, &wait);
2832         set_current_state(TASK_RUNNING);
2833
2834
2835         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2836                 spin_lock_irqsave(&info->lock,flags);
2837                 if (!waitqueue_active(&info->event_wait_q)) {
2838                         /* disable enable exit hunt mode/idle rcvd IRQs */
2839                         wr_reg16(info, SCR,
2840                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2841                 }
2842                 spin_unlock_irqrestore(&info->lock,flags);
2843         }
2844 exit:
2845         if (rc == 0)
2846                 rc = put_user(events, mask_ptr);
2847         return rc;
2848 }
2849
2850 static int get_interface(struct slgt_info *info, int __user *if_mode)
2851 {
2852         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2853         if (put_user(info->if_mode, if_mode))
2854                 return -EFAULT;
2855         return 0;
2856 }
2857
2858 static int set_interface(struct slgt_info *info, int if_mode)
2859 {
2860         unsigned long flags;
2861         unsigned short val;
2862
2863         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2864         spin_lock_irqsave(&info->lock,flags);
2865         info->if_mode = if_mode;
2866
2867         msc_set_vcr(info);
2868
2869         /* TCR (tx control) 07  1=RTS driver control */
2870         val = rd_reg16(info, TCR);
2871         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2872                 val |= BIT7;
2873         else
2874                 val &= ~BIT7;
2875         wr_reg16(info, TCR, val);
2876
2877         spin_unlock_irqrestore(&info->lock,flags);
2878         return 0;
2879 }
2880
2881 static int get_xsync(struct slgt_info *info, int __user *xsync)
2882 {
2883         DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2884         if (put_user(info->xsync, xsync))
2885                 return -EFAULT;
2886         return 0;
2887 }
2888
2889 /*
2890  * set extended sync pattern (1 to 4 bytes) for extended sync mode
2891  *
2892  * sync pattern is contained in least significant bytes of value
2893  * most significant byte of sync pattern is oldest (1st sent/detected)
2894  */
2895 static int set_xsync(struct slgt_info *info, int xsync)
2896 {
2897         unsigned long flags;
2898
2899         DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2900         spin_lock_irqsave(&info->lock, flags);
2901         info->xsync = xsync;
2902         wr_reg32(info, XSR, xsync);
2903         spin_unlock_irqrestore(&info->lock, flags);
2904         return 0;
2905 }
2906
2907 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2908 {
2909         DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2910         if (put_user(info->xctrl, xctrl))
2911                 return -EFAULT;
2912         return 0;
2913 }
2914
2915 /*
2916  * set extended control options
2917  *
2918  * xctrl[31:19] reserved, must be zero
2919  * xctrl[18:17] extended sync pattern length in bytes
2920  *              00 = 1 byte  in xsr[7:0]
2921  *              01 = 2 bytes in xsr[15:0]
2922  *              10 = 3 bytes in xsr[23:0]
2923  *              11 = 4 bytes in xsr[31:0]
2924  * xctrl[16]    1 = enable terminal count, 0=disabled
2925  * xctrl[15:0]  receive terminal count for fixed length packets
2926  *              value is count minus one (0 = 1 byte packet)
2927  *              when terminal count is reached, receiver
2928  *              automatically returns to hunt mode and receive
2929  *              FIFO contents are flushed to DMA buffers with
2930  *              end of frame (EOF) status
2931  */
2932 static int set_xctrl(struct slgt_info *info, int xctrl)
2933 {
2934         unsigned long flags;
2935
2936         DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2937         spin_lock_irqsave(&info->lock, flags);
2938         info->xctrl = xctrl;
2939         wr_reg32(info, XCR, xctrl);
2940         spin_unlock_irqrestore(&info->lock, flags);
2941         return 0;
2942 }
2943
2944 /*
2945  * set general purpose IO pin state and direction
2946  *
2947  * user_gpio fields:
2948  * state   each bit indicates a pin state
2949  * smask   set bit indicates pin state to set
2950  * dir     each bit indicates a pin direction (0=input, 1=output)
2951  * dmask   set bit indicates pin direction to set
2952  */
2953 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2954 {
2955         unsigned long flags;
2956         struct gpio_desc gpio;
2957         __u32 data;
2958
2959         if (!info->gpio_present)
2960                 return -EINVAL;
2961         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2962                 return -EFAULT;
2963         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2964                  info->device_name, gpio.state, gpio.smask,
2965                  gpio.dir, gpio.dmask));
2966
2967         spin_lock_irqsave(&info->port_array[0]->lock, flags);
2968         if (gpio.dmask) {
2969                 data = rd_reg32(info, IODR);
2970                 data |= gpio.dmask & gpio.dir;
2971                 data &= ~(gpio.dmask & ~gpio.dir);
2972                 wr_reg32(info, IODR, data);
2973         }
2974         if (gpio.smask) {
2975                 data = rd_reg32(info, IOVR);
2976                 data |= gpio.smask & gpio.state;
2977                 data &= ~(gpio.smask & ~gpio.state);
2978                 wr_reg32(info, IOVR, data);
2979         }
2980         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2981
2982         return 0;
2983 }
2984
2985 /*
2986  * get general purpose IO pin state and direction
2987  */
2988 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2989 {
2990         struct gpio_desc gpio;
2991         if (!info->gpio_present)
2992                 return -EINVAL;
2993         gpio.state = rd_reg32(info, IOVR);
2994         gpio.smask = 0xffffffff;
2995         gpio.dir   = rd_reg32(info, IODR);
2996         gpio.dmask = 0xffffffff;
2997         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2998                 return -EFAULT;
2999         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3000                  info->device_name, gpio.state, gpio.dir));
3001         return 0;
3002 }
3003
3004 /*
3005  * conditional wait facility
3006  */
3007 static void init_cond_wait(struct cond_wait *w, unsigned int data)
3008 {
3009         init_waitqueue_head(&w->q);
3010         init_waitqueue_entry(&w->wait, current);
3011         w->data = data;
3012 }
3013
3014 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3015 {
3016         set_current_state(TASK_INTERRUPTIBLE);
3017         add_wait_queue(&w->q, &w->wait);
3018         w->next = *head;
3019         *head = w;
3020 }
3021
3022 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3023 {
3024         struct cond_wait *w, *prev;
3025         remove_wait_queue(&cw->q, &cw->wait);
3026         set_current_state(TASK_RUNNING);
3027         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3028                 if (w == cw) {
3029                         if (prev != NULL)
3030                                 prev->next = w->next;
3031                         else
3032                                 *head = w->next;
3033                         break;
3034                 }
3035         }
3036 }
3037
3038 static void flush_cond_wait(struct cond_wait **head)
3039 {
3040         while (*head != NULL) {
3041                 wake_up_interruptible(&(*head)->q);
3042                 *head = (*head)->next;
3043         }
3044 }
3045
3046 /*
3047  * wait for general purpose I/O pin(s) to enter specified state
3048  *
3049  * user_gpio fields:
3050  * state - bit indicates target pin state
3051  * smask - set bit indicates watched pin
3052  *
3053  * The wait ends when at least one watched pin enters the specified
3054  * state. When 0 (no error) is returned, user_gpio->state is set to the
3055  * state of all GPIO pins when the wait ends.
3056  *
3057  * Note: Each pin may be a dedicated input, dedicated output, or
3058  * configurable input/output. The number and configuration of pins
3059  * varies with the specific adapter model. Only input pins (dedicated
3060  * or configured) can be monitored with this function.
3061  */
3062 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3063 {
3064         unsigned long flags;
3065         int rc = 0;
3066         struct gpio_desc gpio;
3067         struct cond_wait wait;
3068         u32 state;
3069
3070         if (!info->gpio_present)
3071                 return -EINVAL;
3072         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3073                 return -EFAULT;
3074         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3075                  info->device_name, gpio.state, gpio.smask));
3076         /* ignore output pins identified by set IODR bit */
3077         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3078                 return -EINVAL;
3079         init_cond_wait(&wait, gpio.smask);
3080
3081         spin_lock_irqsave(&info->port_array[0]->lock, flags);
3082         /* enable interrupts for watched pins */
3083         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3084         /* get current pin states */
3085         state = rd_reg32(info, IOVR);
3086
3087         if (gpio.smask & ~(state ^ gpio.state)) {
3088                 /* already in target state */
3089                 gpio.state = state;
3090         } else {
3091                 /* wait for target state */
3092                 add_cond_wait(&info->gpio_wait_q, &wait);
3093                 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3094                 schedule();
3095                 if (signal_pending(current))
3096                         rc = -ERESTARTSYS;
3097                 else
3098                         gpio.state = wait.data;
3099                 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3100                 remove_cond_wait(&info->gpio_wait_q, &wait);
3101         }
3102
3103         /* disable all GPIO interrupts if no waiting processes */
3104         if (info->gpio_wait_q == NULL)
3105                 wr_reg32(info, IOER, 0);
3106         spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3107
3108         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3109                 rc = -EFAULT;
3110         return rc;
3111 }
3112
3113 static int modem_input_wait(struct slgt_info *info,int arg)
3114 {
3115         unsigned long flags;
3116         int rc;
3117         struct mgsl_icount cprev, cnow;
3118         DECLARE_WAITQUEUE(wait, current);
3119
3120         /* save current irq counts */
3121         spin_lock_irqsave(&info->lock,flags);
3122         cprev = info->icount;
3123         add_wait_queue(&info->status_event_wait_q, &wait);
3124         set_current_state(TASK_INTERRUPTIBLE);
3125         spin_unlock_irqrestore(&info->lock,flags);
3126
3127         for(;;) {
3128                 schedule();
3129                 if (signal_pending(current)) {
3130                         rc = -ERESTARTSYS;
3131                         break;
3132                 }
3133
3134                 /* get new irq counts */
3135                 spin_lock_irqsave(&info->lock,flags);
3136                 cnow = info->icount;
3137                 set_current_state(TASK_INTERRUPTIBLE);
3138                 spin_unlock_irqrestore(&info->lock,flags);
3139
3140                 /* if no change, wait aborted for some reason */
3141                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3142                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3143                         rc = -EIO;
3144                         break;
3145                 }
3146
3147                 /* check for change in caller specified modem input */
3148                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3149                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3150                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3151                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3152                         rc = 0;
3153                         break;
3154                 }
3155
3156                 cprev = cnow;
3157         }
3158         remove_wait_queue(&info->status_event_wait_q, &wait);
3159         set_current_state(TASK_RUNNING);
3160         return rc;
3161 }
3162
3163 /*
3164  *  return state of serial control and status signals
3165  */
3166 static int tiocmget(struct tty_struct *tty)
3167 {
3168         struct slgt_info *info = tty->driver_data;
3169         unsigned int result;
3170         unsigned long flags;
3171
3172         spin_lock_irqsave(&info->lock,flags);
3173         get_signals(info);
3174         spin_unlock_irqrestore(&info->lock,flags);
3175
3176         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3177                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3178                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3179                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3180                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3181                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3182
3183         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3184         return result;
3185 }
3186
3187 /*
3188  * set modem control signals (DTR/RTS)
3189  *
3190  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3191  *              TIOCMSET = set/clear signal values
3192  *      value   bit mask for command
3193  */
3194 static int tiocmset(struct tty_struct *tty,
3195                     unsigned int set, unsigned int clear)
3196 {
3197         struct slgt_info *info = tty->driver_data;
3198         unsigned long flags;
3199
3200         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3201
3202         if (set & TIOCM_RTS)
3203                 info->signals |= SerialSignal_RTS;
3204         if (set & TIOCM_DTR)
3205                 info->signals |= SerialSignal_DTR;
3206         if (clear & TIOCM_RTS)
3207                 info->signals &= ~SerialSignal_RTS;
3208         if (clear & TIOCM_DTR)
3209                 info->signals &= ~SerialSignal_DTR;
3210
3211         spin_lock_irqsave(&info->lock,flags);
3212         set_signals(info);
3213         spin_unlock_irqrestore(&info->lock,flags);
3214         return 0;
3215 }
3216
3217 static int carrier_raised(struct tty_port *port)
3218 {
3219         unsigned long flags;
3220         struct slgt_info *info = container_of(port, struct slgt_info, port);
3221
3222         spin_lock_irqsave(&info->lock,flags);
3223         get_signals(info);
3224         spin_unlock_irqrestore(&info->lock,flags);
3225         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3226 }
3227
3228 static void dtr_rts(struct tty_port *port, int on)
3229 {
3230         unsigned long flags;
3231         struct slgt_info *info = container_of(port, struct slgt_info, port);
3232
3233         spin_lock_irqsave(&info->lock,flags);
3234         if (on)
3235                 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3236         else
3237                 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3238         set_signals(info);
3239         spin_unlock_irqrestore(&info->lock,flags);
3240 }
3241
3242
3243 /*
3244  *  block current process until the device is ready to open
3245  */
3246 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3247                            struct slgt_info *info)
3248 {
3249         DECLARE_WAITQUEUE(wait, current);
3250         int             retval;
3251         bool            do_clocal = false;
3252         unsigned long   flags;
3253         int             cd;
3254         struct tty_port *port = &info->port;
3255
3256         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3257
3258         if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3259                 /* nonblock mode is set or port is not enabled */
3260                 tty_port_set_active(port, 1);
3261                 return 0;
3262         }
3263
3264         if (C_CLOCAL(tty))
3265                 do_clocal = true;
3266
3267         /* Wait for carrier detect and the line to become
3268          * free (i.e., not in use by the callout).  While we are in
3269          * this loop, port->count is dropped by one, so that
3270          * close() knows when to free things.  We restore it upon
3271          * exit, either normal or abnormal.
3272          */
3273
3274         retval = 0;
3275         add_wait_queue(&port->open_wait, &wait);
3276
3277         spin_lock_irqsave(&info->lock, flags);
3278         port->count--;
3279         spin_unlock_irqrestore(&info->lock, flags);
3280         port->blocked_open++;
3281
3282         while (1) {
3283                 if (C_BAUD(tty) && tty_port_initialized(port))
3284                         tty_port_raise_dtr_rts(port);
3285
3286                 set_current_state(TASK_INTERRUPTIBLE);
3287
3288                 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3289                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3290                                         -EAGAIN : -ERESTARTSYS;
3291                         break;
3292                 }
3293
3294                 cd = tty_port_carrier_raised(port);
3295                 if (do_clocal || cd)
3296                         break;
3297
3298                 if (signal_pending(current)) {
3299                         retval = -ERESTARTSYS;
3300                         break;
3301                 }
3302
3303                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3304                 tty_unlock(tty);
3305                 schedule();
3306                 tty_lock(tty);
3307         }
3308
3309         set_current_state(TASK_RUNNING);
3310         remove_wait_queue(&port->open_wait, &wait);
3311
3312         if (!tty_hung_up_p(filp))
3313                 port->count++;
3314         port->blocked_open--;
3315
3316         if (!retval)
3317                 tty_port_set_active(port, 1);
3318
3319         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3320         return retval;
3321 }
3322
3323 /*
3324  * allocate buffers used for calling line discipline receive_buf
3325  * directly in synchronous mode
3326  * note: add 5 bytes to max frame size to allow appending
3327  * 32-bit CRC and status byte when configured to do so
3328  */
3329 static int alloc_tmp_rbuf(struct slgt_info *info)
3330 {
3331         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3332         if (info->tmp_rbuf == NULL)
3333                 return -ENOMEM;
3334         /* unused flag buffer to satisfy receive_buf calling interface */
3335         info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3336         if (!info->flag_buf) {
3337                 kfree(info->tmp_rbuf);
3338                 info->tmp_rbuf = NULL;
3339                 return -ENOMEM;
3340         }
3341         return 0;
3342 }
3343
3344 static void free_tmp_rbuf(struct slgt_info *info)
3345 {
3346         kfree(info->tmp_rbuf);
3347         info->tmp_rbuf = NULL;
3348         kfree(info->flag_buf);
3349         info->flag_buf = NULL;
3350 }
3351
3352 /*
3353  * allocate DMA descriptor lists.
3354  */
3355 static int alloc_desc(struct slgt_info *info)
3356 {
3357         unsigned int i;
3358         unsigned int pbufs;
3359
3360         /* allocate memory to hold descriptor lists */
3361         info->bufs = pci_zalloc_consistent(info->pdev, DESC_LIST_SIZE,
3362                                            &info->bufs_dma_addr);
3363         if (info->bufs == NULL)
3364                 return -ENOMEM;
3365
3366         info->rbufs = (struct slgt_desc*)info->bufs;
3367         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3368
3369         pbufs = (unsigned int)info->bufs_dma_addr;
3370
3371         /*
3372          * Build circular lists of descriptors
3373          */
3374
3375         for (i=0; i < info->rbuf_count; i++) {
3376                 /* physical address of this descriptor */
3377                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3378
3379                 /* physical address of next descriptor */
3380                 if (i == info->rbuf_count - 1)
3381                         info->rbufs[i].next = cpu_to_le32(pbufs);
3382                 else
3383                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3384                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3385         }
3386
3387         for (i=0; i < info->tbuf_count; i++) {
3388                 /* physical address of this descriptor */
3389                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3390
3391                 /* physical address of next descriptor */
3392                 if (i == info->tbuf_count - 1)
3393                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3394                 else
3395                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3396         }
3397
3398         return 0;
3399 }
3400
3401 static void free_desc(struct slgt_info *info)
3402 {
3403         if (info->bufs != NULL) {
3404                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3405                 info->bufs  = NULL;
3406                 info->rbufs = NULL;
3407                 info->tbufs = NULL;
3408         }
3409 }
3410
3411 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3412 {
3413         int i;
3414         for (i=0; i < count; i++) {
3415                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3416                         return -ENOMEM;
3417                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3418         }
3419         return 0;
3420 }
3421
3422 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3423 {
3424         int i;
3425         for (i=0; i < count; i++) {
3426                 if (bufs[i].buf == NULL)
3427                         continue;
3428                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3429                 bufs[i].buf = NULL;
3430         }
3431 }
3432
3433 static int alloc_dma_bufs(struct slgt_info *info)
3434 {
3435         info->rbuf_count = 32;
3436         info->tbuf_count = 32;
3437
3438         if (alloc_desc(info) < 0 ||
3439             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3440             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3441             alloc_tmp_rbuf(info) < 0) {
3442                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3443                 return -ENOMEM;
3444         }
3445         reset_rbufs(info);
3446         return 0;
3447 }
3448
3449 static void free_dma_bufs(struct slgt_info *info)
3450 {
3451         if (info->bufs) {
3452                 free_bufs(info, info->rbufs, info->rbuf_count);
3453                 free_bufs(info, info->tbufs, info->tbuf_count);
3454                 free_desc(info);
3455         }
3456         free_tmp_rbuf(info);
3457 }
3458
3459 static int claim_resources(struct slgt_info *info)
3460 {
3461         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3462                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3463                         info->device_name, info->phys_reg_addr));
3464                 info->init_error = DiagStatus_AddressConflict;
3465                 goto errout;
3466         }
3467         else
3468                 info->reg_addr_requested = true;
3469
3470         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3471         if (!info->reg_addr) {
3472                 DBGERR(("%s can't map device registers, addr=%08X\n",
3473                         info->device_name, info->phys_reg_addr));
3474                 info->init_error = DiagStatus_CantAssignPciResources;
3475                 goto errout;
3476         }
3477         return 0;
3478
3479 errout:
3480         release_resources(info);
3481         return -ENODEV;
3482 }
3483
3484 static void release_resources(struct slgt_info *info)
3485 {
3486         if (info->irq_requested) {
3487                 free_irq(info->irq_level, info);
3488                 info->irq_requested = false;
3489         }
3490
3491         if (info->reg_addr_requested) {
3492                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3493                 info->reg_addr_requested = false;
3494         }
3495
3496         if (info->reg_addr) {
3497                 iounmap(info->reg_addr);
3498                 info->reg_addr = NULL;
3499         }
3500 }
3501
3502 /* Add the specified device instance data structure to the
3503  * global linked list of devices and increment the device count.
3504  */
3505 static void add_device(struct slgt_info *info)
3506 {
3507         char *devstr;
3508
3509         info->next_device = NULL;
3510         info->line = slgt_device_count;
3511         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3512
3513         if (info->line < MAX_DEVICES) {
3514                 if (maxframe[info->line])
3515                         info->max_frame_size = maxframe[info->line];
3516         }
3517
3518         slgt_device_count++;
3519
3520         if (!slgt_device_list)
3521                 slgt_device_list = info;
3522         else {
3523                 struct slgt_info *current_dev = slgt_device_list;
3524                 while(current_dev->next_device)
3525                         current_dev = current_dev->next_device;
3526                 current_dev->next_device = info;
3527         }
3528
3529         if (info->max_frame_size < 4096)
3530                 info->max_frame_size = 4096;
3531         else if (info->max_frame_size > 65535)
3532                 info->max_frame_size = 65535;
3533
3534         switch(info->pdev->device) {
3535         case SYNCLINK_GT_DEVICE_ID:
3536                 devstr = "GT";
3537                 break;
3538         case SYNCLINK_GT2_DEVICE_ID:
3539                 devstr = "GT2";
3540                 break;
3541         case SYNCLINK_GT4_DEVICE_ID:
3542                 devstr = "GT4";
3543                 break;
3544         case SYNCLINK_AC_DEVICE_ID:
3545                 devstr = "AC";
3546                 info->params.mode = MGSL_MODE_ASYNC;
3547                 break;
3548         default:
3549                 devstr = "(unknown model)";
3550         }
3551         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3552                 devstr, info->device_name, info->phys_reg_addr,
3553                 info->irq_level, info->max_frame_size);
3554
3555 #if SYNCLINK_GENERIC_HDLC
3556         hdlcdev_init(info);
3557 #endif
3558 }
3559
3560 static const struct tty_port_operations slgt_port_ops = {
3561         .carrier_raised = carrier_raised,
3562         .dtr_rts = dtr_rts,
3563 };
3564
3565 /*
3566  *  allocate device instance structure, return NULL on failure
3567  */
3568 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3569 {
3570         struct slgt_info *info;
3571
3572         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3573
3574         if (!info) {
3575                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3576                         driver_name, adapter_num, port_num));
3577         } else {
3578                 tty_port_init(&info->port);
3579                 info->port.ops = &slgt_port_ops;
3580                 info->magic = MGSL_MAGIC;
3581                 INIT_WORK(&info->task, bh_handler);
3582                 info->max_frame_size = 4096;
3583                 info->base_clock = 14745600;
3584                 info->rbuf_fill_level = DMABUFSIZE;
3585                 info->port.close_delay = 5*HZ/10;
3586                 info->port.closing_wait = 30*HZ;
3587                 init_waitqueue_head(&info->status_event_wait_q);
3588                 init_waitqueue_head(&info->event_wait_q);
3589                 spin_lock_init(&info->netlock);
3590                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3591                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3592                 info->adapter_num = adapter_num;
3593                 info->port_num = port_num;
3594
3595                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3596                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3597
3598                 /* Copy configuration info to device instance data */
3599                 info->pdev = pdev;
3600                 info->irq_level = pdev->irq;
3601                 info->phys_reg_addr = pci_resource_start(pdev,0);
3602
3603                 info->bus_type = MGSL_BUS_TYPE_PCI;
3604                 info->irq_flags = IRQF_SHARED;
3605
3606                 info->init_error = -1; /* assume error, set to 0 on successful init */
3607         }
3608
3609         return info;
3610 }
3611
3612 static void device_init(int adapter_num, struct pci_dev *pdev)
3613 {
3614         struct slgt_info *port_array[SLGT_MAX_PORTS];
3615         int i;
3616         int port_count = 1;
3617
3618         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3619                 port_count = 2;
3620         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3621                 port_count = 4;
3622
3623         /* allocate device instances for all ports */
3624         for (i=0; i < port_count; ++i) {
3625                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3626                 if (port_array[i] == NULL) {
3627                         for (--i; i >= 0; --i) {
3628                                 tty_port_destroy(&port_array[i]->port);
3629                                 kfree(port_array[i]);
3630                         }
3631                         return;
3632                 }
3633         }
3634
3635         /* give copy of port_array to all ports and add to device list  */
3636         for (i=0; i < port_count; ++i) {
3637                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3638                 add_device(port_array[i]);
3639                 port_array[i]->port_count = port_count;
3640                 spin_lock_init(&port_array[i]->lock);
3641         }
3642
3643         /* Allocate and claim adapter resources */
3644         if (!claim_resources(port_array[0])) {
3645
3646                 alloc_dma_bufs(port_array[0]);
3647
3648                 /* copy resource information from first port to others */
3649                 for (i = 1; i < port_count; ++i) {
3650                         port_array[i]->irq_level = port_array[0]->irq_level;
3651                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3652                         alloc_dma_bufs(port_array[i]);
3653                 }
3654
3655                 if (request_irq(port_array[0]->irq_level,
3656                                         slgt_interrupt,
3657                                         port_array[0]->irq_flags,
3658                                         port_array[0]->device_name,
3659                                         port_array[0]) < 0) {
3660                         DBGERR(("%s request_irq failed IRQ=%d\n",
3661                                 port_array[0]->device_name,
3662                                 port_array[0]->irq_level));
3663                 } else {
3664                         port_array[0]->irq_requested = true;
3665                         adapter_test(port_array[0]);
3666                         for (i=1 ; i < port_count ; i++) {
3667                                 port_array[i]->init_error = port_array[0]->init_error;
3668                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3669                         }
3670                 }
3671         }
3672
3673         for (i = 0; i < port_count; ++i) {
3674                 struct slgt_info *info = port_array[i];
3675                 tty_port_register_device(&info->port, serial_driver, info->line,
3676                                 &info->pdev->dev);
3677         }
3678 }
3679
3680 static int init_one(struct pci_dev *dev,
3681                               const struct pci_device_id *ent)
3682 {
3683         if (pci_enable_device(dev)) {
3684                 printk("error enabling pci device %p\n", dev);
3685                 return -EIO;
3686         }
3687         pci_set_master(dev);
3688         device_init(slgt_device_count, dev);
3689         return 0;
3690 }
3691
3692 static void remove_one(struct pci_dev *dev)
3693 {
3694 }
3695
3696 static const struct tty_operations ops = {
3697         .open = open,
3698         .close = close,
3699         .write = write,
3700         .put_char = put_char,
3701         .flush_chars = flush_chars,
3702         .write_room = write_room,
3703         .chars_in_buffer = chars_in_buffer,
3704         .flush_buffer = flush_buffer,
3705         .ioctl = ioctl,
3706         .compat_ioctl = slgt_compat_ioctl,
3707         .throttle = throttle,
3708         .unthrottle = unthrottle,
3709         .send_xchar = send_xchar,
3710         .break_ctl = set_break,
3711         .wait_until_sent = wait_until_sent,
3712         .set_termios = set_termios,
3713         .stop = tx_hold,
3714         .start = tx_release,
3715         .hangup = hangup,
3716         .tiocmget = tiocmget,
3717         .tiocmset = tiocmset,
3718         .get_icount = get_icount,
3719         .proc_fops = &synclink_gt_proc_fops,
3720 };
3721
3722 static void slgt_cleanup(void)
3723 {
3724         int rc;
3725         struct slgt_info *info;
3726         struct slgt_info *tmp;
3727
3728         printk(KERN_INFO "unload %s\n", driver_name);
3729
3730         if (serial_driver) {
3731                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3732                         tty_unregister_device(serial_driver, info->line);
3733                 rc = tty_unregister_driver(serial_driver);
3734                 if (rc)
3735                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3736                 put_tty_driver(serial_driver);
3737         }
3738
3739         /* reset devices */
3740         info = slgt_device_list;
3741         while(info) {
3742                 reset_port(info);
3743                 info = info->next_device;
3744         }
3745
3746         /* release devices */
3747         info = slgt_device_list;
3748         while(info) {
3749 #if SYNCLINK_GENERIC_HDLC
3750                 hdlcdev_exit(info);
3751 #endif
3752                 free_dma_bufs(info);
3753                 free_tmp_rbuf(info);
3754                 if (info->port_num == 0)
3755                         release_resources(info);
3756                 tmp = info;
3757                 info = info->next_device;
3758                 tty_port_destroy(&tmp->port);
3759                 kfree(tmp);
3760         }
3761
3762         if (pci_registered)
3763                 pci_unregister_driver(&pci_driver);
3764 }
3765
3766 /*
3767  *  Driver initialization entry point.
3768  */
3769 static int __init slgt_init(void)
3770 {
3771         int rc;
3772
3773         printk(KERN_INFO "%s\n", driver_name);
3774
3775         serial_driver = alloc_tty_driver(MAX_DEVICES);
3776         if (!serial_driver) {
3777                 printk("%s can't allocate tty driver\n", driver_name);
3778                 return -ENOMEM;
3779         }
3780
3781         /* Initialize the tty_driver structure */
3782
3783         serial_driver->driver_name = slgt_driver_name;
3784         serial_driver->name = tty_dev_prefix;
3785         serial_driver->major = ttymajor;
3786         serial_driver->minor_start = 64;
3787         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3788         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3789         serial_driver->init_termios = tty_std_termios;
3790         serial_driver->init_termios.c_cflag =
3791                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3792         serial_driver->init_termios.c_ispeed = 9600;
3793         serial_driver->init_termios.c_ospeed = 9600;
3794         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3795         tty_set_operations(serial_driver, &ops);
3796         if ((rc = tty_register_driver(serial_driver)) < 0) {
3797                 DBGERR(("%s can't register serial driver\n", driver_name));
3798                 put_tty_driver(serial_driver);
3799                 serial_driver = NULL;
3800                 goto error;
3801         }
3802
3803         printk(KERN_INFO "%s, tty major#%d\n",
3804                driver_name, serial_driver->major);
3805
3806         slgt_device_count = 0;
3807         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3808                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3809                 goto error;
3810         }
3811         pci_registered = true;
3812
3813         if (!slgt_device_list)
3814                 printk("%s no devices found\n",driver_name);
3815
3816         return 0;
3817
3818 error:
3819         slgt_cleanup();
3820         return rc;
3821 }
3822
3823 static void __exit slgt_exit(void)
3824 {
3825         slgt_cleanup();
3826 }
3827
3828 module_init(slgt_init);
3829 module_exit(slgt_exit);
3830
3831 /*
3832  * register access routines
3833  */
3834
3835 #define CALC_REGADDR() \
3836         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3837         if (addr >= 0x80) \
3838                 reg_addr += (info->port_num) * 32; \
3839         else if (addr >= 0x40)  \
3840                 reg_addr += (info->port_num) * 16;
3841
3842 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3843 {
3844         CALC_REGADDR();
3845         return readb((void __iomem *)reg_addr);
3846 }
3847
3848 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3849 {
3850         CALC_REGADDR();
3851         writeb(value, (void __iomem *)reg_addr);
3852 }
3853
3854 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3855 {
3856         CALC_REGADDR();
3857         return readw((void __iomem *)reg_addr);
3858 }
3859
3860 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3861 {
3862         CALC_REGADDR();
3863         writew(value, (void __iomem *)reg_addr);
3864 }
3865
3866 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3867 {
3868         CALC_REGADDR();
3869         return readl((void __iomem *)reg_addr);
3870 }
3871
3872 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3873 {
3874         CALC_REGADDR();
3875         writel(value, (void __iomem *)reg_addr);
3876 }
3877
3878 static void rdma_reset(struct slgt_info *info)
3879 {
3880         unsigned int i;
3881
3882         /* set reset bit */
3883         wr_reg32(info, RDCSR, BIT1);
3884
3885         /* wait for enable bit cleared */
3886         for(i=0 ; i < 1000 ; i++)
3887                 if (!(rd_reg32(info, RDCSR) & BIT0))
3888                         break;
3889 }
3890
3891 static void tdma_reset(struct slgt_info *info)
3892 {
3893         unsigned int i;
3894
3895         /* set reset bit */
3896         wr_reg32(info, TDCSR, BIT1);
3897
3898         /* wait for enable bit cleared */
3899         for(i=0 ; i < 1000 ; i++)
3900                 if (!(rd_reg32(info, TDCSR) & BIT0))
3901                         break;
3902 }
3903
3904 /*
3905  * enable internal loopback
3906  * TxCLK and RxCLK are generated from BRG
3907  * and TxD is looped back to RxD internally.
3908  */
3909 static void enable_loopback(struct slgt_info *info)
3910 {
3911         /* SCR (serial control) BIT2=loopback enable */
3912         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3913
3914         if (info->params.mode != MGSL_MODE_ASYNC) {
3915                 /* CCR (clock control)
3916                  * 07..05  tx clock source (010 = BRG)
3917                  * 04..02  rx clock source (010 = BRG)
3918                  * 01      auxclk enable   (0 = disable)
3919                  * 00      BRG enable      (1 = enable)
3920                  *
3921                  * 0100 1001
3922                  */
3923                 wr_reg8(info, CCR, 0x49);
3924
3925                 /* set speed if available, otherwise use default */
3926                 if (info->params.clock_speed)
3927                         set_rate(info, info->params.clock_speed);
3928                 else
3929                         set_rate(info, 3686400);
3930         }
3931 }
3932
3933 /*
3934  *  set baud rate generator to specified rate
3935  */
3936 static void set_rate(struct slgt_info *info, u32 rate)
3937 {
3938         unsigned int div;
3939         unsigned int osc = info->base_clock;
3940
3941         /* div = osc/rate - 1
3942          *
3943          * Round div up if osc/rate is not integer to
3944          * force to next slowest rate.
3945          */
3946
3947         if (rate) {
3948                 div = osc/rate;
3949                 if (!(osc % rate) && div)
3950                         div--;
3951                 wr_reg16(info, BDR, (unsigned short)div);
3952         }
3953 }
3954
3955 static void rx_stop(struct slgt_info *info)
3956 {
3957         unsigned short val;
3958
3959         /* disable and reset receiver */
3960         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3961         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3962         wr_reg16(info, RCR, val);                  /* clear reset bit */
3963
3964         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3965
3966         /* clear pending rx interrupts */
3967         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3968
3969         rdma_reset(info);
3970
3971         info->rx_enabled = false;
3972         info->rx_restart = false;
3973 }
3974
3975 static void rx_start(struct slgt_info *info)
3976 {
3977         unsigned short val;
3978
3979         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3980
3981         /* clear pending rx overrun IRQ */
3982         wr_reg16(info, SSR, IRQ_RXOVER);
3983
3984         /* reset and disable receiver */
3985         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3986         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3987         wr_reg16(info, RCR, val);                  /* clear reset bit */
3988
3989         rdma_reset(info);
3990         reset_rbufs(info);
3991
3992         if (info->rx_pio) {
3993                 /* rx request when rx FIFO not empty */
3994                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3995                 slgt_irq_on(info, IRQ_RXDATA);
3996                 if (info->params.mode == MGSL_MODE_ASYNC) {
3997                         /* enable saving of rx status */
3998                         wr_reg32(info, RDCSR, BIT6);
3999                 }
4000         } else {
4001                 /* rx request when rx FIFO half full */
4002                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4003                 /* set 1st descriptor address */
4004                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4005
4006                 if (info->params.mode != MGSL_MODE_ASYNC) {
4007                         /* enable rx DMA and DMA interrupt */
4008                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
4009                 } else {
4010                         /* enable saving of rx status, rx DMA and DMA interrupt */
4011                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4012                 }
4013         }
4014
4015         slgt_irq_on(info, IRQ_RXOVER);
4016
4017         /* enable receiver */
4018         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4019
4020         info->rx_restart = false;
4021         info->rx_enabled = true;
4022 }
4023
4024 static void tx_start(struct slgt_info *info)
4025 {
4026         if (!info->tx_enabled) {
4027                 wr_reg16(info, TCR,
4028                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4029                 info->tx_enabled = true;
4030         }
4031
4032         if (desc_count(info->tbufs[info->tbuf_start])) {
4033                 info->drop_rts_on_tx_done = false;
4034
4035                 if (info->params.mode != MGSL_MODE_ASYNC) {
4036                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4037                                 get_signals(info);
4038                                 if (!(info->signals & SerialSignal_RTS)) {
4039                                         info->signals |= SerialSignal_RTS;
4040                                         set_signals(info);
4041                                         info->drop_rts_on_tx_done = true;
4042                                 }
4043                         }
4044
4045                         slgt_irq_off(info, IRQ_TXDATA);
4046                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4047                         /* clear tx idle and underrun status bits */
4048                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4049                 } else {
4050                         slgt_irq_off(info, IRQ_TXDATA);
4051                         slgt_irq_on(info, IRQ_TXIDLE);
4052                         /* clear tx idle status bit */
4053                         wr_reg16(info, SSR, IRQ_TXIDLE);
4054                 }
4055                 /* set 1st descriptor address and start DMA */
4056                 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4057                 wr_reg32(info, TDCSR, BIT2 + BIT0);
4058                 info->tx_active = true;
4059         }
4060 }
4061
4062 static void tx_stop(struct slgt_info *info)
4063 {
4064         unsigned short val;
4065
4066         del_timer(&info->tx_timer);
4067
4068         tdma_reset(info);
4069
4070         /* reset and disable transmitter */
4071         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4072         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4073
4074         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4075
4076         /* clear tx idle and underrun status bit */
4077         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4078
4079         reset_tbufs(info);
4080
4081         info->tx_enabled = false;
4082         info->tx_active = false;
4083 }
4084
4085 static void reset_port(struct slgt_info *info)
4086 {
4087         if (!info->reg_addr)
4088                 return;
4089
4090         tx_stop(info);
4091         rx_stop(info);
4092
4093         info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4094         set_signals(info);
4095
4096         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4097 }
4098
4099 static void reset_adapter(struct slgt_info *info)
4100 {
4101         int i;
4102         for (i=0; i < info->port_count; ++i) {
4103                 if (info->port_array[i])
4104                         reset_port(info->port_array[i]);
4105         }
4106 }
4107
4108 static void async_mode(struct slgt_info *info)
4109 {
4110         unsigned short val;
4111
4112         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4113         tx_stop(info);
4114         rx_stop(info);
4115
4116         /* TCR (tx control)
4117          *
4118          * 15..13  mode, 010=async
4119          * 12..10  encoding, 000=NRZ
4120          * 09      parity enable
4121          * 08      1=odd parity, 0=even parity
4122          * 07      1=RTS driver control
4123          * 06      1=break enable
4124          * 05..04  character length
4125          *         00=5 bits
4126          *         01=6 bits
4127          *         10=7 bits
4128          *         11=8 bits
4129          * 03      0=1 stop bit, 1=2 stop bits
4130          * 02      reset
4131          * 01      enable
4132          * 00      auto-CTS enable
4133          */
4134         val = 0x4000;
4135
4136         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4137                 val |= BIT7;
4138
4139         if (info->params.parity != ASYNC_PARITY_NONE) {
4140                 val |= BIT9;
4141                 if (info->params.parity == ASYNC_PARITY_ODD)
4142                         val |= BIT8;
4143         }
4144
4145         switch (info->params.data_bits)
4146         {
4147         case 6: val |= BIT4; break;
4148         case 7: val |= BIT5; break;
4149         case 8: val |= BIT5 + BIT4; break;
4150         }
4151
4152         if (info->params.stop_bits != 1)
4153                 val |= BIT3;
4154
4155         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4156                 val |= BIT0;
4157
4158         wr_reg16(info, TCR, val);
4159
4160         /* RCR (rx control)
4161          *
4162          * 15..13  mode, 010=async
4163          * 12..10  encoding, 000=NRZ
4164          * 09      parity enable
4165          * 08      1=odd parity, 0=even parity
4166          * 07..06  reserved, must be 0
4167          * 05..04  character length
4168          *         00=5 bits
4169          *         01=6 bits
4170          *         10=7 bits
4171          *         11=8 bits
4172          * 03      reserved, must be zero
4173          * 02      reset
4174          * 01      enable
4175          * 00      auto-DCD enable
4176          */
4177         val = 0x4000;
4178
4179         if (info->params.parity != ASYNC_PARITY_NONE) {
4180                 val |= BIT9;
4181                 if (info->params.parity == ASYNC_PARITY_ODD)
4182                         val |= BIT8;
4183         }
4184
4185         switch (info->params.data_bits)
4186         {
4187         case 6: val |= BIT4; break;
4188         case 7: val |= BIT5; break;
4189         case 8: val |= BIT5 + BIT4; break;
4190         }
4191
4192         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4193                 val |= BIT0;
4194
4195         wr_reg16(info, RCR, val);
4196
4197         /* CCR (clock control)
4198          *
4199          * 07..05  011 = tx clock source is BRG/16
4200          * 04..02  010 = rx clock source is BRG
4201          * 01      0 = auxclk disabled
4202          * 00      1 = BRG enabled
4203          *
4204          * 0110 1001
4205          */
4206         wr_reg8(info, CCR, 0x69);
4207
4208         msc_set_vcr(info);
4209
4210         /* SCR (serial control)
4211          *
4212          * 15  1=tx req on FIFO half empty
4213          * 14  1=rx req on FIFO half full
4214          * 13  tx data  IRQ enable
4215          * 12  tx idle  IRQ enable
4216          * 11  rx break on IRQ enable
4217          * 10  rx data  IRQ enable
4218          * 09  rx break off IRQ enable
4219          * 08  overrun  IRQ enable
4220          * 07  DSR      IRQ enable
4221          * 06  CTS      IRQ enable
4222          * 05  DCD      IRQ enable
4223          * 04  RI       IRQ enable
4224          * 03  0=16x sampling, 1=8x sampling
4225          * 02  1=txd->rxd internal loopback enable
4226          * 01  reserved, must be zero
4227          * 00  1=master IRQ enable
4228          */
4229         val = BIT15 + BIT14 + BIT0;
4230         /* JCR[8] : 1 = x8 async mode feature available */
4231         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4232             ((info->base_clock < (info->params.data_rate * 16)) ||
4233              (info->base_clock % (info->params.data_rate * 16)))) {
4234                 /* use 8x sampling */
4235                 val |= BIT3;
4236                 set_rate(info, info->params.data_rate * 8);
4237         } else {
4238                 /* use 16x sampling */
4239                 set_rate(info, info->params.data_rate * 16);
4240         }
4241         wr_reg16(info, SCR, val);
4242
4243         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4244
4245         if (info->params.loopback)
4246                 enable_loopback(info);
4247 }
4248
4249 static void sync_mode(struct slgt_info *info)
4250 {
4251         unsigned short val;
4252
4253         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4254         tx_stop(info);
4255         rx_stop(info);
4256
4257         /* TCR (tx control)
4258          *
4259          * 15..13  mode
4260          *         000=HDLC/SDLC
4261          *         001=raw bit synchronous
4262          *         010=asynchronous/isochronous
4263          *         011=monosync byte synchronous
4264          *         100=bisync byte synchronous
4265          *         101=xsync byte synchronous
4266          * 12..10  encoding
4267          * 09      CRC enable
4268          * 08      CRC32
4269          * 07      1=RTS driver control
4270          * 06      preamble enable
4271          * 05..04  preamble length
4272          * 03      share open/close flag
4273          * 02      reset
4274          * 01      enable
4275          * 00      auto-CTS enable
4276          */
4277         val = BIT2;
4278
4279         switch(info->params.mode) {
4280         case MGSL_MODE_XSYNC:
4281                 val |= BIT15 + BIT13;
4282                 break;
4283         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4284         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4285         case MGSL_MODE_RAW:      val |= BIT13; break;
4286         }
4287         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4288                 val |= BIT7;
4289
4290         switch(info->params.encoding)
4291         {
4292         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4293         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4294         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4295         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4296         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4297         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4298         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4299         }
4300
4301         switch (info->params.crc_type & HDLC_CRC_MASK)
4302         {
4303         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4304         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4305         }
4306
4307         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4308                 val |= BIT6;
4309
4310         switch (info->params.preamble_length)
4311         {
4312         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4313         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4314         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4315         }
4316
4317         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4318                 val |= BIT0;
4319
4320         wr_reg16(info, TCR, val);
4321
4322         /* TPR (transmit preamble) */
4323
4324         switch (info->params.preamble)
4325         {
4326         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4327         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4328         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4329         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4330         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4331         default:                          val = 0x7e; break;
4332         }
4333         wr_reg8(info, TPR, (unsigned char)val);
4334
4335         /* RCR (rx control)
4336          *
4337          * 15..13  mode
4338          *         000=HDLC/SDLC
4339          *         001=raw bit synchronous
4340          *         010=asynchronous/isochronous
4341          *         011=monosync byte synchronous
4342          *         100=bisync byte synchronous
4343          *         101=xsync byte synchronous
4344          * 12..10  encoding
4345          * 09      CRC enable
4346          * 08      CRC32
4347          * 07..03  reserved, must be 0
4348          * 02      reset
4349          * 01      enable
4350          * 00      auto-DCD enable
4351          */
4352         val = 0;
4353
4354         switch(info->params.mode) {
4355         case MGSL_MODE_XSYNC:
4356                 val |= BIT15 + BIT13;
4357                 break;
4358         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4359         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4360         case MGSL_MODE_RAW:      val |= BIT13; break;
4361         }
4362
4363         switch(info->params.encoding)
4364         {
4365         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4366         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4367         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4368         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4369         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4370         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4371         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4372         }
4373
4374         switch (info->params.crc_type & HDLC_CRC_MASK)
4375         {
4376         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4377         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4378         }
4379
4380         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4381                 val |= BIT0;
4382
4383         wr_reg16(info, RCR, val);
4384
4385         /* CCR (clock control)
4386          *
4387          * 07..05  tx clock source
4388          * 04..02  rx clock source
4389          * 01      auxclk enable
4390          * 00      BRG enable
4391          */
4392         val = 0;
4393
4394         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4395         {
4396                 // when RxC source is DPLL, BRG generates 16X DPLL
4397                 // reference clock, so take TxC from BRG/16 to get
4398                 // transmit clock at actual data rate
4399                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4400                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4401                 else
4402                         val |= BIT6;    /* 010, txclk = BRG */
4403         }
4404         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4405                 val |= BIT7;    /* 100, txclk = DPLL Input */
4406         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4407                 val |= BIT5;    /* 001, txclk = RXC Input */
4408
4409         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4410                 val |= BIT3;    /* 010, rxclk = BRG */
4411         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4412                 val |= BIT4;    /* 100, rxclk = DPLL */
4413         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4414                 val |= BIT2;    /* 001, rxclk = TXC Input */
4415
4416         if (info->params.clock_speed)
4417                 val |= BIT1 + BIT0;
4418
4419         wr_reg8(info, CCR, (unsigned char)val);
4420
4421         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4422         {
4423                 // program DPLL mode
4424                 switch(info->params.encoding)
4425                 {
4426                 case HDLC_ENCODING_BIPHASE_MARK:
4427                 case HDLC_ENCODING_BIPHASE_SPACE:
4428                         val = BIT7; break;
4429                 case HDLC_ENCODING_BIPHASE_LEVEL:
4430                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4431                         val = BIT7 + BIT6; break;
4432                 default: val = BIT6;    // NRZ encodings
4433                 }
4434                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4435
4436                 // DPLL requires a 16X reference clock from BRG
4437                 set_rate(info, info->params.clock_speed * 16);
4438         }
4439         else
4440                 set_rate(info, info->params.clock_speed);
4441
4442         tx_set_idle(info);
4443
4444         msc_set_vcr(info);
4445
4446         /* SCR (serial control)
4447          *
4448          * 15  1=tx req on FIFO half empty
4449          * 14  1=rx req on FIFO half full
4450          * 13  tx data  IRQ enable
4451          * 12  tx idle  IRQ enable
4452          * 11  underrun IRQ enable
4453          * 10  rx data  IRQ enable
4454          * 09  rx idle  IRQ enable
4455          * 08  overrun  IRQ enable
4456          * 07  DSR      IRQ enable
4457          * 06  CTS      IRQ enable
4458          * 05  DCD      IRQ enable
4459          * 04  RI       IRQ enable
4460          * 03  reserved, must be zero
4461          * 02  1=txd->rxd internal loopback enable
4462          * 01  reserved, must be zero
4463          * 00  1=master IRQ enable
4464          */
4465         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4466
4467         if (info->params.loopback)
4468                 enable_loopback(info);
4469 }
4470
4471 /*
4472  *  set transmit idle mode
4473  */
4474 static void tx_set_idle(struct slgt_info *info)
4475 {
4476         unsigned char val;
4477         unsigned short tcr;
4478
4479         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4480          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4481          */
4482         tcr = rd_reg16(info, TCR);
4483         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4484                 /* disable preamble, set idle size to 16 bits */
4485                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4486                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4487                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4488         } else if (!(tcr & BIT6)) {
4489                 /* preamble is disabled, set idle size to 8 bits */
4490                 tcr &= ~(BIT5 + BIT4);
4491         }
4492         wr_reg16(info, TCR, tcr);
4493
4494         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4495                 /* LSB of custom tx idle specified in tx idle register */
4496                 val = (unsigned char)(info->idle_mode & 0xff);
4497         } else {
4498                 /* standard 8 bit idle patterns */
4499                 switch(info->idle_mode)
4500                 {
4501                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4502                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4503                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4504                 case HDLC_TXIDLE_ZEROS:
4505                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4506                 default:                         val = 0xff;
4507                 }
4508         }
4509
4510         wr_reg8(info, TIR, val);
4511 }
4512
4513 /*
4514  * get state of V24 status (input) signals
4515  */
4516 static void get_signals(struct slgt_info *info)
4517 {
4518         unsigned short status = rd_reg16(info, SSR);
4519
4520         /* clear all serial signals except RTS and DTR */
4521         info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4522
4523         if (status & BIT3)
4524                 info->signals |= SerialSignal_DSR;
4525         if (status & BIT2)
4526                 info->signals |= SerialSignal_CTS;
4527         if (status & BIT1)
4528                 info->signals |= SerialSignal_DCD;
4529         if (status & BIT0)
4530                 info->signals |= SerialSignal_RI;
4531 }
4532
4533 /*
4534  * set V.24 Control Register based on current configuration
4535  */
4536 static void msc_set_vcr(struct slgt_info *info)
4537 {
4538         unsigned char val = 0;
4539
4540         /* VCR (V.24 control)
4541          *
4542          * 07..04  serial IF select
4543          * 03      DTR
4544          * 02      RTS
4545          * 01      LL
4546          * 00      RL
4547          */
4548
4549         switch(info->if_mode & MGSL_INTERFACE_MASK)
4550         {
4551         case MGSL_INTERFACE_RS232:
4552                 val |= BIT5; /* 0010 */
4553                 break;
4554         case MGSL_INTERFACE_V35:
4555                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4556                 break;
4557         case MGSL_INTERFACE_RS422:
4558                 val |= BIT6; /* 0100 */
4559                 break;
4560         }
4561
4562         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4563                 val |= BIT4;
4564         if (info->signals & SerialSignal_DTR)
4565                 val |= BIT3;
4566         if (info->signals & SerialSignal_RTS)
4567                 val |= BIT2;
4568         if (info->if_mode & MGSL_INTERFACE_LL)
4569                 val |= BIT1;
4570         if (info->if_mode & MGSL_INTERFACE_RL)
4571                 val |= BIT0;
4572         wr_reg8(info, VCR, val);
4573 }
4574
4575 /*
4576  * set state of V24 control (output) signals
4577  */
4578 static void set_signals(struct slgt_info *info)
4579 {
4580         unsigned char val = rd_reg8(info, VCR);
4581         if (info->signals & SerialSignal_DTR)
4582                 val |= BIT3;
4583         else
4584                 val &= ~BIT3;
4585         if (info->signals & SerialSignal_RTS)
4586                 val |= BIT2;
4587         else
4588                 val &= ~BIT2;
4589         wr_reg8(info, VCR, val);
4590 }
4591
4592 /*
4593  * free range of receive DMA buffers (i to last)
4594  */
4595 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4596 {
4597         int done = 0;
4598
4599         while(!done) {
4600                 /* reset current buffer for reuse */
4601                 info->rbufs[i].status = 0;
4602                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4603                 if (i == last)
4604                         done = 1;
4605                 if (++i == info->rbuf_count)
4606                         i = 0;
4607         }
4608         info->rbuf_current = i;
4609 }
4610
4611 /*
4612  * mark all receive DMA buffers as free
4613  */
4614 static void reset_rbufs(struct slgt_info *info)
4615 {
4616         free_rbufs(info, 0, info->rbuf_count - 1);
4617         info->rbuf_fill_index = 0;
4618         info->rbuf_fill_count = 0;
4619 }
4620
4621 /*
4622  * pass receive HDLC frame to upper layer
4623  *
4624  * return true if frame available, otherwise false
4625  */
4626 static bool rx_get_frame(struct slgt_info *info)
4627 {
4628         unsigned int start, end;
4629         unsigned short status;
4630         unsigned int framesize = 0;
4631         unsigned long flags;
4632         struct tty_struct *tty = info->port.tty;
4633         unsigned char addr_field = 0xff;
4634         unsigned int crc_size = 0;
4635
4636         switch (info->params.crc_type & HDLC_CRC_MASK) {
4637         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4638         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4639         }
4640
4641 check_again:
4642
4643         framesize = 0;
4644         addr_field = 0xff;
4645         start = end = info->rbuf_current;
4646
4647         for (;;) {
4648                 if (!desc_complete(info->rbufs[end]))
4649                         goto cleanup;
4650
4651                 if (framesize == 0 && info->params.addr_filter != 0xff)
4652                         addr_field = info->rbufs[end].buf[0];
4653
4654                 framesize += desc_count(info->rbufs[end]);
4655
4656                 if (desc_eof(info->rbufs[end]))
4657                         break;
4658
4659                 if (++end == info->rbuf_count)
4660                         end = 0;
4661
4662                 if (end == info->rbuf_current) {
4663                         if (info->rx_enabled){
4664                                 spin_lock_irqsave(&info->lock,flags);
4665                                 rx_start(info);
4666                                 spin_unlock_irqrestore(&info->lock,flags);
4667                         }
4668                         goto cleanup;
4669                 }
4670         }
4671
4672         /* status
4673          *
4674          * 15      buffer complete
4675          * 14..06  reserved
4676          * 05..04  residue
4677          * 02      eof (end of frame)
4678          * 01      CRC error
4679          * 00      abort
4680          */
4681         status = desc_status(info->rbufs[end]);
4682
4683         /* ignore CRC bit if not using CRC (bit is undefined) */
4684         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4685                 status &= ~BIT1;
4686
4687         if (framesize == 0 ||
4688                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4689                 free_rbufs(info, start, end);
4690                 goto check_again;
4691         }
4692
4693         if (framesize < (2 + crc_size) || status & BIT0) {
4694                 info->icount.rxshort++;
4695                 framesize = 0;
4696         } else if (status & BIT1) {
4697                 info->icount.rxcrc++;
4698                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4699                         framesize = 0;
4700         }
4701
4702 #if SYNCLINK_GENERIC_HDLC
4703         if (framesize == 0) {
4704                 info->netdev->stats.rx_errors++;
4705                 info->netdev->stats.rx_frame_errors++;
4706         }
4707 #endif
4708
4709         DBGBH(("%s rx frame status=%04X size=%d\n",
4710                 info->device_name, status, framesize));
4711         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4712
4713         if (framesize) {
4714                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4715                         framesize -= crc_size;
4716                         crc_size = 0;
4717                 }
4718
4719                 if (framesize > info->max_frame_size + crc_size)
4720                         info->icount.rxlong++;
4721                 else {
4722                         /* copy dma buffer(s) to contiguous temp buffer */
4723                         int copy_count = framesize;
4724                         int i = start;
4725                         unsigned char *p = info->tmp_rbuf;
4726                         info->tmp_rbuf_count = framesize;
4727
4728                         info->icount.rxok++;
4729
4730                         while(copy_count) {
4731                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4732                                 memcpy(p, info->rbufs[i].buf, partial_count);
4733                                 p += partial_count;
4734                                 copy_count -= partial_count;
4735                                 if (++i == info->rbuf_count)
4736                                         i = 0;
4737                         }
4738
4739                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4740                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4741                                 framesize++;
4742                         }
4743
4744 #if SYNCLINK_GENERIC_HDLC
4745                         if (info->netcount)
4746                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4747                         else
4748 #endif
4749                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4750                 }
4751         }
4752         free_rbufs(info, start, end);
4753         return true;
4754
4755 cleanup:
4756         return false;
4757 }
4758
4759 /*
4760  * pass receive buffer (RAW synchronous mode) to tty layer
4761  * return true if buffer available, otherwise false
4762  */
4763 static bool rx_get_buf(struct slgt_info *info)
4764 {
4765         unsigned int i = info->rbuf_current;
4766         unsigned int count;
4767
4768         if (!desc_complete(info->rbufs[i]))
4769                 return false;
4770         count = desc_count(info->rbufs[i]);
4771         switch(info->params.mode) {
4772         case MGSL_MODE_MONOSYNC:
4773         case MGSL_MODE_BISYNC:
4774         case MGSL_MODE_XSYNC:
4775                 /* ignore residue in byte synchronous modes */
4776                 if (desc_residue(info->rbufs[i]))
4777                         count--;
4778                 break;
4779         }
4780         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4781         DBGINFO(("rx_get_buf size=%d\n", count));
4782         if (count)
4783                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4784                                   info->flag_buf, count);
4785         free_rbufs(info, i, i);
4786         return true;
4787 }
4788
4789 static void reset_tbufs(struct slgt_info *info)
4790 {
4791         unsigned int i;
4792         info->tbuf_current = 0;
4793         for (i=0 ; i < info->tbuf_count ; i++) {
4794                 info->tbufs[i].status = 0;
4795                 info->tbufs[i].count  = 0;
4796         }
4797 }
4798
4799 /*
4800  * return number of free transmit DMA buffers
4801  */
4802 static unsigned int free_tbuf_count(struct slgt_info *info)
4803 {
4804         unsigned int count = 0;
4805         unsigned int i = info->tbuf_current;
4806
4807         do
4808         {
4809                 if (desc_count(info->tbufs[i]))
4810                         break; /* buffer in use */
4811                 ++count;
4812                 if (++i == info->tbuf_count)
4813                         i=0;
4814         } while (i != info->tbuf_current);
4815
4816         /* if tx DMA active, last zero count buffer is in use */
4817         if (count && (rd_reg32(info, TDCSR) & BIT0))
4818                 --count;
4819
4820         return count;
4821 }
4822
4823 /*
4824  * return number of bytes in unsent transmit DMA buffers
4825  * and the serial controller tx FIFO
4826  */
4827 static unsigned int tbuf_bytes(struct slgt_info *info)
4828 {
4829         unsigned int total_count = 0;
4830         unsigned int i = info->tbuf_current;
4831         unsigned int reg_value;
4832         unsigned int count;
4833         unsigned int active_buf_count = 0;
4834
4835         /*
4836          * Add descriptor counts for all tx DMA buffers.
4837          * If count is zero (cleared by DMA controller after read),
4838          * the buffer is complete or is actively being read from.
4839          *
4840          * Record buf_count of last buffer with zero count starting
4841          * from current ring position. buf_count is mirror
4842          * copy of count and is not cleared by serial controller.
4843          * If DMA controller is active, that buffer is actively
4844          * being read so add to total.
4845          */
4846         do {
4847                 count = desc_count(info->tbufs[i]);
4848                 if (count)
4849                         total_count += count;
4850                 else if (!total_count)
4851                         active_buf_count = info->tbufs[i].buf_count;
4852                 if (++i == info->tbuf_count)
4853                         i = 0;
4854         } while (i != info->tbuf_current);
4855
4856         /* read tx DMA status register */
4857         reg_value = rd_reg32(info, TDCSR);
4858
4859         /* if tx DMA active, last zero count buffer is in use */
4860         if (reg_value & BIT0)
4861                 total_count += active_buf_count;
4862
4863         /* add tx FIFO count = reg_value[15..8] */
4864         total_count += (reg_value >> 8) & 0xff;
4865
4866         /* if transmitter active add one byte for shift register */
4867         if (info->tx_active)
4868                 total_count++;
4869
4870         return total_count;
4871 }
4872
4873 /*
4874  * load data into transmit DMA buffer ring and start transmitter if needed
4875  * return true if data accepted, otherwise false (buffers full)
4876  */
4877 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4878 {
4879         unsigned short count;
4880         unsigned int i;
4881         struct slgt_desc *d;
4882
4883         /* check required buffer space */
4884         if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4885                 return false;
4886
4887         DBGDATA(info, buf, size, "tx");
4888
4889         /*
4890          * copy data to one or more DMA buffers in circular ring
4891          * tbuf_start   = first buffer for this data
4892          * tbuf_current = next free buffer
4893          *
4894          * Copy all data before making data visible to DMA controller by
4895          * setting descriptor count of the first buffer.
4896          * This prevents an active DMA controller from reading the first DMA
4897          * buffers of a frame and stopping before the final buffers are filled.
4898          */
4899
4900         info->tbuf_start = i = info->tbuf_current;
4901
4902         while (size) {
4903                 d = &info->tbufs[i];
4904
4905                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4906                 memcpy(d->buf, buf, count);
4907
4908                 size -= count;
4909                 buf  += count;
4910
4911                 /*
4912                  * set EOF bit for last buffer of HDLC frame or
4913                  * for every buffer in raw mode
4914                  */
4915                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4916                     info->params.mode == MGSL_MODE_RAW)
4917                         set_desc_eof(*d, 1);
4918                 else
4919                         set_desc_eof(*d, 0);
4920
4921                 /* set descriptor count for all but first buffer */
4922                 if (i != info->tbuf_start)
4923                         set_desc_count(*d, count);
4924                 d->buf_count = count;
4925
4926                 if (++i == info->tbuf_count)
4927                         i = 0;
4928         }
4929
4930         info->tbuf_current = i;
4931
4932         /* set first buffer count to make new data visible to DMA controller */
4933         d = &info->tbufs[info->tbuf_start];
4934         set_desc_count(*d, d->buf_count);
4935
4936         /* start transmitter if needed and update transmit timeout */
4937         if (!info->tx_active)
4938                 tx_start(info);
4939         update_tx_timer(info);
4940
4941         return true;
4942 }
4943
4944 static int register_test(struct slgt_info *info)
4945 {
4946         static unsigned short patterns[] =
4947                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4948         static unsigned int count = ARRAY_SIZE(patterns);
4949         unsigned int i;
4950         int rc = 0;
4951
4952         for (i=0 ; i < count ; i++) {
4953                 wr_reg16(info, TIR, patterns[i]);
4954                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4955                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4956                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4957                         rc = -ENODEV;
4958                         break;
4959                 }
4960         }
4961         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4962         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4963         return rc;
4964 }
4965
4966 static int irq_test(struct slgt_info *info)
4967 {
4968         unsigned long timeout;
4969         unsigned long flags;
4970         struct tty_struct *oldtty = info->port.tty;
4971         u32 speed = info->params.data_rate;
4972
4973         info->params.data_rate = 921600;
4974         info->port.tty = NULL;
4975
4976         spin_lock_irqsave(&info->lock, flags);
4977         async_mode(info);
4978         slgt_irq_on(info, IRQ_TXIDLE);
4979
4980         /* enable transmitter */
4981         wr_reg16(info, TCR,
4982                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4983
4984         /* write one byte and wait for tx idle */
4985         wr_reg16(info, TDR, 0);
4986
4987         /* assume failure */
4988         info->init_error = DiagStatus_IrqFailure;
4989         info->irq_occurred = false;
4990
4991         spin_unlock_irqrestore(&info->lock, flags);
4992
4993         timeout=100;
4994         while(timeout-- && !info->irq_occurred)
4995                 msleep_interruptible(10);
4996
4997         spin_lock_irqsave(&info->lock,flags);
4998         reset_port(info);
4999         spin_unlock_irqrestore(&info->lock,flags);
5000
5001         info->params.data_rate = speed;
5002         info->port.tty = oldtty;
5003
5004         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5005         return info->irq_occurred ? 0 : -ENODEV;
5006 }
5007
5008 static int loopback_test_rx(struct slgt_info *info)
5009 {
5010         unsigned char *src, *dest;
5011         int count;
5012
5013         if (desc_complete(info->rbufs[0])) {
5014                 count = desc_count(info->rbufs[0]);
5015                 src   = info->rbufs[0].buf;
5016                 dest  = info->tmp_rbuf;
5017
5018                 for( ; count ; count-=2, src+=2) {
5019                         /* src=data byte (src+1)=status byte */
5020                         if (!(*(src+1) & (BIT9 + BIT8))) {
5021                                 *dest = *src;
5022                                 dest++;
5023                                 info->tmp_rbuf_count++;
5024                         }
5025                 }
5026                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5027                 return 1;
5028         }
5029         return 0;
5030 }
5031
5032 static int loopback_test(struct slgt_info *info)
5033 {
5034 #define TESTFRAMESIZE 20
5035
5036         unsigned long timeout;
5037         u16 count = TESTFRAMESIZE;
5038         unsigned char buf[TESTFRAMESIZE];
5039         int rc = -ENODEV;
5040         unsigned long flags;
5041
5042         struct tty_struct *oldtty = info->port.tty;
5043         MGSL_PARAMS params;
5044
5045         memcpy(&params, &info->params, sizeof(params));
5046
5047         info->params.mode = MGSL_MODE_ASYNC;
5048         info->params.data_rate = 921600;
5049         info->params.loopback = 1;
5050         info->port.tty = NULL;
5051
5052         /* build and send transmit frame */
5053         for (count = 0; count < TESTFRAMESIZE; ++count)
5054                 buf[count] = (unsigned char)count;
5055
5056         info->tmp_rbuf_count = 0;
5057         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5058
5059         /* program hardware for HDLC and enabled receiver */
5060         spin_lock_irqsave(&info->lock,flags);
5061         async_mode(info);
5062         rx_start(info);
5063         tx_load(info, buf, count);
5064         spin_unlock_irqrestore(&info->lock, flags);
5065
5066         /* wait for receive complete */
5067         for (timeout = 100; timeout; --timeout) {
5068                 msleep_interruptible(10);
5069                 if (loopback_test_rx(info)) {
5070                         rc = 0;
5071                         break;
5072                 }
5073         }
5074
5075         /* verify received frame length and contents */
5076         if (!rc && (info->tmp_rbuf_count != count ||
5077                   memcmp(buf, info->tmp_rbuf, count))) {
5078                 rc = -ENODEV;
5079         }
5080
5081         spin_lock_irqsave(&info->lock,flags);
5082         reset_adapter(info);
5083         spin_unlock_irqrestore(&info->lock,flags);
5084
5085         memcpy(&info->params, &params, sizeof(info->params));
5086         info->port.tty = oldtty;
5087
5088         info->init_error = rc ? DiagStatus_DmaFailure : 0;
5089         return rc;
5090 }
5091
5092 static int adapter_test(struct slgt_info *info)
5093 {
5094         DBGINFO(("testing %s\n", info->device_name));
5095         if (register_test(info) < 0) {
5096                 printk("register test failure %s addr=%08X\n",
5097                         info->device_name, info->phys_reg_addr);
5098         } else if (irq_test(info) < 0) {
5099                 printk("IRQ test failure %s IRQ=%d\n",
5100                         info->device_name, info->irq_level);
5101         } else if (loopback_test(info) < 0) {
5102                 printk("loopback test failure %s\n", info->device_name);
5103         }
5104         return info->init_error;
5105 }
5106
5107 /*
5108  * transmit timeout handler
5109  */
5110 static void tx_timeout(unsigned long context)
5111 {
5112         struct slgt_info *info = (struct slgt_info*)context;
5113         unsigned long flags;
5114
5115         DBGINFO(("%s tx_timeout\n", info->device_name));
5116         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5117                 info->icount.txtimeout++;
5118         }
5119         spin_lock_irqsave(&info->lock,flags);
5120         tx_stop(info);
5121         spin_unlock_irqrestore(&info->lock,flags);
5122
5123 #if SYNCLINK_GENERIC_HDLC
5124         if (info->netcount)
5125                 hdlcdev_tx_done(info);
5126         else
5127 #endif
5128                 bh_transmit(info);
5129 }
5130
5131 /*
5132  * receive buffer polling timer
5133  */
5134 static void rx_timeout(unsigned long context)
5135 {
5136         struct slgt_info *info = (struct slgt_info*)context;
5137         unsigned long flags;
5138
5139         DBGINFO(("%s rx_timeout\n", info->device_name));
5140         spin_lock_irqsave(&info->lock, flags);
5141         info->pending_bh |= BH_RECEIVE;
5142         spin_unlock_irqrestore(&info->lock, flags);
5143         bh_handler(&info->task);
5144 }
5145