2 * Cadence UART driver (found in Xilinx Zynq)
4 * 2011 - 2014 (C) Xilinx Inc.
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/iopoll.h>
36 #define CDNS_UART_TTY_NAME "ttyPS"
37 #define CDNS_UART_NAME "xuartps"
38 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
39 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
40 #define CDNS_UART_NR_PORTS 2
41 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
42 #define CDNS_UART_REGISTER_SPACE 0x1000
43 #define TX_TIMEOUT 500000
45 /* Rx Trigger level */
46 static int rx_trigger_level = 56;
47 module_param(rx_trigger_level, uint, S_IRUGO);
48 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
51 static int rx_timeout = 10;
52 module_param(rx_timeout, uint, S_IRUGO);
53 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
55 /* Register offsets for the UART. */
56 #define CDNS_UART_CR 0x00 /* Control Register */
57 #define CDNS_UART_MR 0x04 /* Mode Register */
58 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
59 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
60 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
61 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
62 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
63 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
64 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
65 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
66 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
67 #define CDNS_UART_SR 0x2C /* Channel Status */
68 #define CDNS_UART_FIFO 0x30 /* FIFO */
69 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
70 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
71 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
72 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
73 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
74 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
76 /* Control Register Bit Definitions */
77 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
78 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
79 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
80 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
81 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
82 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
83 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
84 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
85 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
86 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
87 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
88 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
92 * The mode register (MR) defines the mode of transfer as well as the data
93 * format. If this register is modified during transmission or reception,
94 * data validity cannot be guaranteed.
96 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
97 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
98 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
99 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
101 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
102 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
104 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
105 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
106 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
107 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
108 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
110 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
111 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
112 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
115 * Interrupt Registers:
116 * Interrupt control logic uses the interrupt enable register (IER) and the
117 * interrupt disable register (IDR) to set the value of the bits in the
118 * interrupt mask register (IMR). The IMR determines whether to pass an
119 * interrupt to the interrupt status register (ISR).
120 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
121 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
122 * Reading either IER or IDR returns 0x00.
123 * All four registers have the same bit definitions.
125 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
126 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
127 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
128 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
129 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
130 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
131 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
132 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
133 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
134 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
135 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
138 * Do not enable parity error interrupt for the following
139 * reason: When parity error interrupt is enabled, each Rx
140 * parity error always results in 2 events. The first one
141 * being parity error interrupt and the second one with a
142 * proper Rx interrupt with the incoming data. Disabling
143 * parity error interrupt ensures better handling of parity
144 * error events. With this change, for a parity error case, we
145 * get a Rx interrupt with parity error set in ISR register
146 * and we still handle parity errors in the desired way.
149 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
150 CDNS_UART_IXR_OVERRUN | \
151 CDNS_UART_IXR_RXTRIG | \
154 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
155 #define CDNS_UART_IXR_BRK 0x00002000
157 #define CDNS_UART_RXBS_SUPPORT BIT(1)
159 * Modem Control register:
160 * The read/write Modem Control register controls the interface with the modem
161 * or data set, or a peripheral device emulating a modem.
163 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
164 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
165 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
168 * Channel Status Register:
169 * The channel status register (CSR) is provided to enable the control logic
170 * to monitor the status of bits in the channel interrupt status register,
171 * even if these are masked out by the interrupt mask register.
173 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
174 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
175 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
176 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
178 /* baud dividers min/max values */
179 #define CDNS_UART_BDIV_MIN 4
180 #define CDNS_UART_BDIV_MAX 255
181 #define CDNS_UART_CD_MAX 65535
182 #define UART_AUTOSUSPEND_TIMEOUT 3000
185 * struct cdns_uart - device data
186 * @port: Pointer to the UART port
187 * @uartclk: Reference clock
189 * @baud: Current baud rate
190 * @clk_rate_change_nb: Notifier block for clock changes
191 * @quirks: Flags for RXBS support.
194 struct uart_port *port;
198 struct notifier_block clk_rate_change_nb;
201 struct cdns_platform_data {
204 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
208 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
209 * @dev_id: Id of the UART port
210 * @isrstatus: The interrupt status register value as read
213 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
215 struct uart_port *port = (struct uart_port *)dev_id;
216 struct cdns_uart *cdns_uart = port->private_data;
218 unsigned int rxbs_status = 0;
219 unsigned int status_mask;
220 unsigned int framerrprocessed = 0;
221 char status = TTY_NORMAL;
222 bool is_rxbs_support;
224 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
226 while ((readl(port->membase + CDNS_UART_SR) &
227 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
229 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
230 data = readl(port->membase + CDNS_UART_FIFO);
233 * There is no hardware break detection in Zynq, so we interpret
234 * framing error with all-zeros data as a break sequence.
235 * Most of the time, there's another non-zero byte at the
236 * end of the sequence.
238 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
240 port->read_status_mask |= CDNS_UART_IXR_BRK;
241 framerrprocessed = 1;
245 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
248 if (uart_handle_break(port))
252 isrstatus &= port->read_status_mask;
253 isrstatus &= ~port->ignore_status_mask;
254 status_mask = port->read_status_mask;
255 status_mask &= ~port->ignore_status_mask;
258 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
259 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
261 if (uart_handle_break(port))
265 if (uart_handle_sysrq_char(port, data))
268 if (is_rxbs_support) {
269 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
270 && (status_mask & CDNS_UART_IXR_PARITY)) {
271 port->icount.parity++;
274 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
275 && (status_mask & CDNS_UART_IXR_PARITY)) {
276 port->icount.frame++;
280 if (isrstatus & CDNS_UART_IXR_PARITY) {
281 port->icount.parity++;
284 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
286 port->icount.frame++;
290 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
291 port->icount.overrun++;
292 tty_insert_flip_char(&port->state->port, 0,
295 tty_insert_flip_char(&port->state->port, data, status);
298 spin_unlock(&port->lock);
299 tty_flip_buffer_push(&port->state->port);
300 spin_lock(&port->lock);
304 * cdns_uart_handle_tx - Handle the bytes to be Txed.
305 * @dev_id: Id of the UART port
308 static void cdns_uart_handle_tx(void *dev_id)
310 struct uart_port *port = (struct uart_port *)dev_id;
311 unsigned int numbytes;
313 if (uart_circ_empty(&port->state->xmit)) {
314 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
316 numbytes = port->fifosize;
317 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
318 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
320 * Get the data from the UART circular buffer
321 * and write it to the cdns_uart's TX_FIFO
325 port->state->xmit.buf[port->state->xmit.
326 tail], port->membase + CDNS_UART_FIFO);
331 * Adjust the tail of the UART buffer and wrap
332 * the buffer if it reaches limit.
334 port->state->xmit.tail =
335 (port->state->xmit.tail + 1) &
336 (UART_XMIT_SIZE - 1);
341 if (uart_circ_chars_pending(
342 &port->state->xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(port);
348 * cdns_uart_isr - Interrupt handler
350 * @dev_id: Id of the port
354 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
356 struct uart_port *port = (struct uart_port *)dev_id;
357 unsigned int isrstatus;
359 spin_lock(&port->lock);
361 /* Read the interrupt status register to determine which
362 * interrupt(s) is/are active and clear them.
364 isrstatus = readl(port->membase + CDNS_UART_ISR);
365 writel(isrstatus, port->membase + CDNS_UART_ISR);
367 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
368 cdns_uart_handle_tx(dev_id);
369 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
372 isrstatus &= port->read_status_mask;
373 isrstatus &= ~port->ignore_status_mask;
375 * Skip RX processing if RX is disabled as RXEMPTY will never be set
376 * as read bytes will not be removed from the FIFO.
378 if (isrstatus & CDNS_UART_IXR_RXMASK &&
379 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
380 cdns_uart_handle_rx(dev_id, isrstatus);
382 spin_unlock(&port->lock);
387 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
388 * @clk: UART module input clock
389 * @baud: Desired baud rate
390 * @rbdiv: BDIV value (return value)
391 * @rcd: CD value (return value)
392 * @div8: Value for clk_sel bit in mod (return value)
393 * Return: baud rate, requested baud when possible, or actual baud when there
394 * was too much error, zero if no valid divisors are found.
396 * Formula to obtain baud rate is
397 * baud_tx/rx rate = clk/CD * (BDIV + 1)
398 * input_clk = (Uart User Defined Clock or Apb Clock)
399 * depends on UCLKEN in MR Reg
400 * clk = input_clk or input_clk/8;
401 * depends on CLKS in MR reg
402 * CD and BDIV depends on values in
403 * baud rate generate register
404 * baud rate clock divisor register
406 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
407 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
410 unsigned int calc_baud;
411 unsigned int bestbaud = 0;
412 unsigned int bauderror;
413 unsigned int besterror = ~0;
415 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
422 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
423 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
424 if (cd < 1 || cd > CDNS_UART_CD_MAX)
427 calc_baud = clk / (cd * (bdiv + 1));
429 if (baud > calc_baud)
430 bauderror = baud - calc_baud;
432 bauderror = calc_baud - baud;
434 if (besterror > bauderror) {
437 bestbaud = calc_baud;
438 besterror = bauderror;
441 /* use the values when percent error is acceptable */
442 if (((besterror * 100) / baud) < 3)
449 * cdns_uart_set_baud_rate - Calculate and set the baud rate
450 * @port: Handle to the uart port structure
451 * @baud: Baud rate to set
452 * Return: baud rate, requested baud when possible, or actual baud when there
453 * was too much error, zero if no valid divisors are found.
455 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
458 unsigned int calc_baud;
459 u32 cd = 0, bdiv = 0;
462 struct cdns_uart *cdns_uart = port->private_data;
464 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
467 /* Write new divisors to hardware */
468 mreg = readl(port->membase + CDNS_UART_MR);
470 mreg |= CDNS_UART_MR_CLKSEL;
472 mreg &= ~CDNS_UART_MR_CLKSEL;
473 writel(mreg, port->membase + CDNS_UART_MR);
474 writel(cd, port->membase + CDNS_UART_BAUDGEN);
475 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
476 cdns_uart->baud = baud;
481 #ifdef CONFIG_COMMON_CLK
483 * cdns_uart_clk_notitifer_cb - Clock notifier callback
484 * @nb: Notifier block
485 * @event: Notify event
486 * @data: Notifier data
487 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
489 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
490 unsigned long event, void *data)
493 struct uart_port *port;
495 struct clk_notifier_data *ndata = data;
496 unsigned long flags = 0;
497 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
499 port = cdns_uart->port;
504 case PRE_RATE_CHANGE:
510 * Find out if current baud-rate can be achieved with new clock
513 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
514 &bdiv, &cd, &div8)) {
515 dev_warn(port->dev, "clock rate change rejected\n");
519 spin_lock_irqsave(&cdns_uart->port->lock, flags);
521 /* Disable the TX and RX to set baud rate */
522 ctrl_reg = readl(port->membase + CDNS_UART_CR);
523 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
524 writel(ctrl_reg, port->membase + CDNS_UART_CR);
526 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
530 case POST_RATE_CHANGE:
532 * Set clk dividers to generate correct baud with new clock
536 spin_lock_irqsave(&cdns_uart->port->lock, flags);
539 port->uartclk = ndata->new_rate;
541 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
544 case ABORT_RATE_CHANGE:
546 spin_lock_irqsave(&cdns_uart->port->lock, flags);
548 /* Set TX/RX Reset */
549 ctrl_reg = readl(port->membase + CDNS_UART_CR);
550 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
551 writel(ctrl_reg, port->membase + CDNS_UART_CR);
553 while (readl(port->membase + CDNS_UART_CR) &
554 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
558 * Clear the RX disable and TX disable bits and then set the TX
559 * enable bit and RX enable bit to enable the transmitter and
562 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
563 ctrl_reg = readl(port->membase + CDNS_UART_CR);
564 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
565 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
566 writel(ctrl_reg, port->membase + CDNS_UART_CR);
568 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
578 * cdns_uart_start_tx - Start transmitting bytes
579 * @port: Handle to the uart port structure
581 static void cdns_uart_start_tx(struct uart_port *port)
585 if (uart_tx_stopped(port))
589 * Set the TX enable bit and clear the TX disable bit to enable the
592 status = readl(port->membase + CDNS_UART_CR);
593 status &= ~CDNS_UART_CR_TX_DIS;
594 status |= CDNS_UART_CR_TX_EN;
595 writel(status, port->membase + CDNS_UART_CR);
597 if (uart_circ_empty(&port->state->xmit))
600 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
602 cdns_uart_handle_tx(port);
604 /* Enable the TX Empty interrupt */
605 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
609 * cdns_uart_stop_tx - Stop TX
610 * @port: Handle to the uart port structure
612 static void cdns_uart_stop_tx(struct uart_port *port)
616 regval = readl(port->membase + CDNS_UART_CR);
617 regval |= CDNS_UART_CR_TX_DIS;
618 /* Disable the transmitter */
619 writel(regval, port->membase + CDNS_UART_CR);
623 * cdns_uart_stop_rx - Stop RX
624 * @port: Handle to the uart port structure
626 static void cdns_uart_stop_rx(struct uart_port *port)
630 /* Disable RX IRQs */
631 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
633 /* Disable the receiver */
634 regval = readl(port->membase + CDNS_UART_CR);
635 regval |= CDNS_UART_CR_RX_DIS;
636 writel(regval, port->membase + CDNS_UART_CR);
640 * cdns_uart_tx_empty - Check whether TX is empty
641 * @port: Handle to the uart port structure
643 * Return: TIOCSER_TEMT on success, 0 otherwise
645 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
649 status = readl(port->membase + CDNS_UART_SR) &
650 CDNS_UART_SR_TXEMPTY;
651 return status ? TIOCSER_TEMT : 0;
655 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
656 * transmitting char breaks
657 * @port: Handle to the uart port structure
658 * @ctl: Value based on which start or stop decision is taken
660 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
665 spin_lock_irqsave(&port->lock, flags);
667 status = readl(port->membase + CDNS_UART_CR);
670 writel(CDNS_UART_CR_STARTBRK | status,
671 port->membase + CDNS_UART_CR);
673 if ((status & CDNS_UART_CR_STOPBRK) == 0)
674 writel(CDNS_UART_CR_STOPBRK | status,
675 port->membase + CDNS_UART_CR);
677 spin_unlock_irqrestore(&port->lock, flags);
681 * cdns_uart_set_termios - termios operations, handling data length, parity,
682 * stop bits, flow control, baud rate
683 * @port: Handle to the uart port structure
684 * @termios: Handle to the input termios structure
685 * @old: Values of the previously saved termios structure
687 static void cdns_uart_set_termios(struct uart_port *port,
688 struct ktermios *termios, struct ktermios *old)
690 unsigned int cval = 0;
691 unsigned int baud, minbaud, maxbaud;
693 unsigned int ctrl_reg, mode_reg, val;
696 /* Wait for the transmit FIFO to empty before making changes */
697 if (!(readl(port->membase + CDNS_UART_CR) &
698 CDNS_UART_CR_TX_DIS)) {
699 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
700 val, (val & CDNS_UART_SR_TXEMPTY),
703 dev_err(port->dev, "timed out waiting for tx empty");
707 spin_lock_irqsave(&port->lock, flags);
709 /* Disable the TX and RX to set baud rate */
710 ctrl_reg = readl(port->membase + CDNS_UART_CR);
711 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
712 writel(ctrl_reg, port->membase + CDNS_UART_CR);
715 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
716 * min and max baud should be calculated here based on port->uartclk.
717 * this way we get a valid baud and can safely call set_baud()
719 minbaud = port->uartclk /
720 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
721 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
722 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
723 baud = cdns_uart_set_baud_rate(port, baud);
724 if (tty_termios_baud_rate(termios))
725 tty_termios_encode_baud_rate(termios, baud, baud);
727 /* Update the per-port timeout. */
728 uart_update_timeout(port, termios->c_cflag, baud);
730 /* Set TX/RX Reset */
731 ctrl_reg = readl(port->membase + CDNS_UART_CR);
732 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
733 writel(ctrl_reg, port->membase + CDNS_UART_CR);
735 while (readl(port->membase + CDNS_UART_CR) &
736 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
740 * Clear the RX disable and TX disable bits and then set the TX enable
741 * bit and RX enable bit to enable the transmitter and receiver.
743 ctrl_reg = readl(port->membase + CDNS_UART_CR);
744 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
745 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
746 writel(ctrl_reg, port->membase + CDNS_UART_CR);
748 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
750 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
751 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
752 port->ignore_status_mask = 0;
754 if (termios->c_iflag & INPCK)
755 port->read_status_mask |= CDNS_UART_IXR_PARITY |
756 CDNS_UART_IXR_FRAMING;
758 if (termios->c_iflag & IGNPAR)
759 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
760 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
762 /* ignore all characters if CREAD is not set */
763 if ((termios->c_cflag & CREAD) == 0)
764 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
765 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
766 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
768 mode_reg = readl(port->membase + CDNS_UART_MR);
770 /* Handling Data Size */
771 switch (termios->c_cflag & CSIZE) {
773 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
776 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
780 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
781 termios->c_cflag &= ~CSIZE;
782 termios->c_cflag |= CS8;
786 /* Handling Parity and Stop Bits length */
787 if (termios->c_cflag & CSTOPB)
788 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
790 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
792 if (termios->c_cflag & PARENB) {
793 /* Mark or Space parity */
794 if (termios->c_cflag & CMSPAR) {
795 if (termios->c_cflag & PARODD)
796 cval |= CDNS_UART_MR_PARITY_MARK;
798 cval |= CDNS_UART_MR_PARITY_SPACE;
800 if (termios->c_cflag & PARODD)
801 cval |= CDNS_UART_MR_PARITY_ODD;
803 cval |= CDNS_UART_MR_PARITY_EVEN;
806 cval |= CDNS_UART_MR_PARITY_NONE;
808 cval |= mode_reg & 1;
809 writel(cval, port->membase + CDNS_UART_MR);
811 spin_unlock_irqrestore(&port->lock, flags);
815 * cdns_uart_startup - Called when an application opens a cdns_uart port
816 * @port: Handle to the uart port structure
818 * Return: 0 on success, negative errno otherwise
820 static int cdns_uart_startup(struct uart_port *port)
822 struct cdns_uart *cdns_uart = port->private_data;
826 unsigned int status = 0;
828 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
830 spin_lock_irqsave(&port->lock, flags);
832 /* Disable the TX and RX */
833 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
834 port->membase + CDNS_UART_CR);
836 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
839 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
840 port->membase + CDNS_UART_CR);
842 while (readl(port->membase + CDNS_UART_CR) &
843 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
847 * Clear the RX disable bit and then set the RX enable bit to enable
850 status = readl(port->membase + CDNS_UART_CR);
851 status &= CDNS_UART_CR_RX_DIS;
852 status |= CDNS_UART_CR_RX_EN;
853 writel(status, port->membase + CDNS_UART_CR);
855 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
858 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
859 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
860 port->membase + CDNS_UART_MR);
863 * Set the RX FIFO Trigger level to use most of the FIFO, but it
864 * can be tuned with a module parameter
866 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
869 * Receive Timeout register is enabled but it
870 * can be tuned with a module parameter
872 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
874 /* Clear out any pending interrupts before enabling them */
875 writel(readl(port->membase + CDNS_UART_ISR),
876 port->membase + CDNS_UART_ISR);
878 spin_unlock_irqrestore(&port->lock, flags);
880 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
882 dev_err(port->dev, "request_irq '%d' failed with %d\n",
887 /* Set the Interrupt Registers with desired interrupts */
889 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
890 port->membase + CDNS_UART_IER);
892 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
898 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
899 * @port: Handle to the uart port structure
901 static void cdns_uart_shutdown(struct uart_port *port)
906 spin_lock_irqsave(&port->lock, flags);
908 /* Disable interrupts */
909 status = readl(port->membase + CDNS_UART_IMR);
910 writel(status, port->membase + CDNS_UART_IDR);
911 writel(0xffffffff, port->membase + CDNS_UART_ISR);
913 /* Disable the TX and RX */
914 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
915 port->membase + CDNS_UART_CR);
917 spin_unlock_irqrestore(&port->lock, flags);
919 free_irq(port->irq, port);
923 * cdns_uart_type - Set UART type to cdns_uart port
924 * @port: Handle to the uart port structure
926 * Return: string on success, NULL otherwise
928 static const char *cdns_uart_type(struct uart_port *port)
930 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
934 * cdns_uart_verify_port - Verify the port params
935 * @port: Handle to the uart port structure
936 * @ser: Handle to the structure whose members are compared
938 * Return: 0 on success, negative errno otherwise.
940 static int cdns_uart_verify_port(struct uart_port *port,
941 struct serial_struct *ser)
943 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
945 if (port->irq != ser->irq)
947 if (ser->io_type != UPIO_MEM)
949 if (port->iobase != ser->port)
957 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
958 * called when the driver adds a cdns_uart port via
959 * uart_add_one_port()
960 * @port: Handle to the uart port structure
962 * Return: 0 on success, negative errno otherwise.
964 static int cdns_uart_request_port(struct uart_port *port)
966 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
971 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
972 if (!port->membase) {
973 dev_err(port->dev, "Unable to map registers\n");
974 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
981 * cdns_uart_release_port - Release UART port
982 * @port: Handle to the uart port structure
984 * Release the memory region attached to a cdns_uart port. Called when the
985 * driver removes a cdns_uart port via uart_remove_one_port().
987 static void cdns_uart_release_port(struct uart_port *port)
989 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
990 iounmap(port->membase);
991 port->membase = NULL;
995 * cdns_uart_config_port - Configure UART port
996 * @port: Handle to the uart port structure
999 static void cdns_uart_config_port(struct uart_port *port, int flags)
1001 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
1002 port->type = PORT_XUARTPS;
1006 * cdns_uart_get_mctrl - Get the modem control state
1007 * @port: Handle to the uart port structure
1009 * Return: the modem control state
1011 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1013 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1016 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1021 val = readl(port->membase + CDNS_UART_MODEMCR);
1022 mode_reg = readl(port->membase + CDNS_UART_MR);
1024 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1025 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1027 if (mctrl & TIOCM_RTS)
1028 val |= CDNS_UART_MODEMCR_RTS;
1029 if (mctrl & TIOCM_DTR)
1030 val |= CDNS_UART_MODEMCR_DTR;
1031 if (mctrl & TIOCM_LOOP)
1032 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1034 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1036 writel(val, port->membase + CDNS_UART_MODEMCR);
1037 writel(mode_reg, port->membase + CDNS_UART_MR);
1040 #ifdef CONFIG_CONSOLE_POLL
1041 static int cdns_uart_poll_get_char(struct uart_port *port)
1044 unsigned long flags;
1046 spin_lock_irqsave(&port->lock, flags);
1048 /* Check if FIFO is empty */
1049 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1051 else /* Read a character */
1052 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1054 spin_unlock_irqrestore(&port->lock, flags);
1059 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1061 unsigned long flags;
1063 spin_lock_irqsave(&port->lock, flags);
1065 /* Wait until FIFO is empty */
1066 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1069 /* Write a character */
1070 writel(c, port->membase + CDNS_UART_FIFO);
1072 /* Wait until FIFO is empty */
1073 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1076 spin_unlock_irqrestore(&port->lock, flags);
1082 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1083 unsigned int oldstate)
1086 case UART_PM_STATE_OFF:
1087 pm_runtime_mark_last_busy(port->dev);
1088 pm_runtime_put_autosuspend(port->dev);
1091 pm_runtime_get_sync(port->dev);
1096 static const struct uart_ops cdns_uart_ops = {
1097 .set_mctrl = cdns_uart_set_mctrl,
1098 .get_mctrl = cdns_uart_get_mctrl,
1099 .start_tx = cdns_uart_start_tx,
1100 .stop_tx = cdns_uart_stop_tx,
1101 .stop_rx = cdns_uart_stop_rx,
1102 .tx_empty = cdns_uart_tx_empty,
1103 .break_ctl = cdns_uart_break_ctl,
1104 .set_termios = cdns_uart_set_termios,
1105 .startup = cdns_uart_startup,
1106 .shutdown = cdns_uart_shutdown,
1108 .type = cdns_uart_type,
1109 .verify_port = cdns_uart_verify_port,
1110 .request_port = cdns_uart_request_port,
1111 .release_port = cdns_uart_release_port,
1112 .config_port = cdns_uart_config_port,
1113 #ifdef CONFIG_CONSOLE_POLL
1114 .poll_get_char = cdns_uart_poll_get_char,
1115 .poll_put_char = cdns_uart_poll_put_char,
1119 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1122 * cdns_uart_get_port - Configure the port from platform device resource info
1125 * Return: a pointer to a uart_port or NULL for failure
1127 static struct uart_port *cdns_uart_get_port(int id)
1129 struct uart_port *port;
1131 /* Try the given port id if failed use default method */
1132 if (id < CDNS_UART_NR_PORTS && cdns_uart_port[id].mapbase != 0) {
1133 /* Find the next unused port */
1134 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1135 if (cdns_uart_port[id].mapbase == 0)
1139 if (id >= CDNS_UART_NR_PORTS)
1142 port = &cdns_uart_port[id];
1144 /* At this point, we've got an empty uart_port struct, initialize it */
1145 spin_lock_init(&port->lock);
1146 port->membase = NULL;
1148 port->type = PORT_UNKNOWN;
1149 port->iotype = UPIO_MEM32;
1150 port->flags = UPF_BOOT_AUTOCONF;
1151 port->ops = &cdns_uart_ops;
1152 port->fifosize = CDNS_UART_FIFO_SIZE;
1158 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1160 * cdns_uart_console_wait_tx - Wait for the TX to be full
1161 * @port: Handle to the uart port structure
1163 static void cdns_uart_console_wait_tx(struct uart_port *port)
1165 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1170 * cdns_uart_console_putchar - write the character to the FIFO buffer
1171 * @port: Handle to the uart port structure
1172 * @ch: Character to be written
1174 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1176 cdns_uart_console_wait_tx(port);
1177 writel(ch, port->membase + CDNS_UART_FIFO);
1180 static void cdns_early_write(struct console *con, const char *s,
1183 struct earlycon_device *dev = con->data;
1185 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1188 static int __init cdns_early_console_setup(struct earlycon_device *device,
1191 struct uart_port *port = &device->port;
1196 /* initialise control register */
1197 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1198 port->membase + CDNS_UART_CR);
1200 /* only set baud if specified on command line - otherwise
1201 * assume it has been initialized by a boot loader.
1204 u32 cd = 0, bdiv = 0;
1208 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1210 mr = CDNS_UART_MR_PARITY_NONE;
1212 mr |= CDNS_UART_MR_CLKSEL;
1214 writel(mr, port->membase + CDNS_UART_MR);
1215 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1216 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1219 device->con->write = cdns_early_write;
1223 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1224 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1225 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1226 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1229 * cdns_uart_console_write - perform write operation
1230 * @co: Console handle
1231 * @s: Pointer to character array
1232 * @count: No of characters
1234 static void cdns_uart_console_write(struct console *co, const char *s,
1237 struct uart_port *port = &cdns_uart_port[co->index];
1238 unsigned long flags;
1239 unsigned int imr, ctrl;
1244 else if (oops_in_progress)
1245 locked = spin_trylock_irqsave(&port->lock, flags);
1247 spin_lock_irqsave(&port->lock, flags);
1249 /* save and disable interrupt */
1250 imr = readl(port->membase + CDNS_UART_IMR);
1251 writel(imr, port->membase + CDNS_UART_IDR);
1254 * Make sure that the tx part is enabled. Set the TX enable bit and
1255 * clear the TX disable bit to enable the transmitter.
1257 ctrl = readl(port->membase + CDNS_UART_CR);
1258 ctrl &= ~CDNS_UART_CR_TX_DIS;
1259 ctrl |= CDNS_UART_CR_TX_EN;
1260 writel(ctrl, port->membase + CDNS_UART_CR);
1262 uart_console_write(port, s, count, cdns_uart_console_putchar);
1263 cdns_uart_console_wait_tx(port);
1265 writel(ctrl, port->membase + CDNS_UART_CR);
1267 /* restore interrupt state */
1268 writel(imr, port->membase + CDNS_UART_IER);
1271 spin_unlock_irqrestore(&port->lock, flags);
1275 * cdns_uart_console_setup - Initialize the uart to default config
1276 * @co: Console handle
1277 * @options: Initial settings of uart
1279 * Return: 0 on success, negative errno otherwise.
1281 static int cdns_uart_console_setup(struct console *co, char *options)
1283 struct uart_port *port = &cdns_uart_port[co->index];
1288 unsigned long time_out;
1290 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1293 if (!port->membase) {
1294 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1300 uart_parse_options(options, &baud, &parity, &bits, &flow);
1302 /* Wait for tx_empty before setting up the console */
1303 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1305 while (time_before(jiffies, time_out) &&
1306 cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1309 return uart_set_options(port, co, baud, parity, bits, flow);
1312 static struct uart_driver cdns_uart_uart_driver;
1314 static struct console cdns_uart_console = {
1315 .name = CDNS_UART_TTY_NAME,
1316 .write = cdns_uart_console_write,
1317 .device = uart_console_device,
1318 .setup = cdns_uart_console_setup,
1319 .flags = CON_PRINTBUFFER,
1320 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1321 .data = &cdns_uart_uart_driver,
1325 * cdns_uart_console_init - Initialization call
1327 * Return: 0 on success, negative errno otherwise
1329 static int __init cdns_uart_console_init(void)
1331 register_console(&cdns_uart_console);
1335 console_initcall(cdns_uart_console_init);
1337 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1339 static struct uart_driver cdns_uart_uart_driver = {
1340 .owner = THIS_MODULE,
1341 .driver_name = CDNS_UART_NAME,
1342 .dev_name = CDNS_UART_TTY_NAME,
1343 .major = CDNS_UART_MAJOR,
1344 .minor = CDNS_UART_MINOR,
1345 .nr = CDNS_UART_NR_PORTS,
1346 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1347 .cons = &cdns_uart_console,
1351 #ifdef CONFIG_PM_SLEEP
1353 * cdns_uart_suspend - suspend event
1354 * @device: Pointer to the device structure
1358 static int cdns_uart_suspend(struct device *device)
1360 struct uart_port *port = dev_get_drvdata(device);
1363 may_wake = device_may_wakeup(device);
1365 if (console_suspend_enabled && may_wake) {
1366 unsigned long flags = 0;
1368 spin_lock_irqsave(&port->lock, flags);
1369 /* Empty the receive FIFO 1st before making changes */
1370 while (!(readl(port->membase + CDNS_UART_SR) &
1371 CDNS_UART_SR_RXEMPTY))
1372 readl(port->membase + CDNS_UART_FIFO);
1373 /* set RX trigger level to 1 */
1374 writel(1, port->membase + CDNS_UART_RXWM);
1375 /* disable RX timeout interrups */
1376 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1377 spin_unlock_irqrestore(&port->lock, flags);
1381 * Call the API provided in serial_core.c file which handles
1384 return uart_suspend_port(&cdns_uart_uart_driver, port);
1388 * cdns_uart_resume - Resume after a previous suspend
1389 * @device: Pointer to the device structure
1393 static int cdns_uart_resume(struct device *device)
1395 struct uart_port *port = dev_get_drvdata(device);
1396 unsigned long flags = 0;
1400 may_wake = device_may_wakeup(device);
1402 if (console_suspend_enabled && !may_wake) {
1403 struct cdns_uart *cdns_uart = port->private_data;
1405 clk_enable(cdns_uart->pclk);
1406 clk_enable(cdns_uart->uartclk);
1408 spin_lock_irqsave(&port->lock, flags);
1410 /* Set TX/RX Reset */
1411 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1412 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1413 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1414 while (readl(port->membase + CDNS_UART_CR) &
1415 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1418 /* restore rx timeout value */
1419 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1421 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1422 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1423 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1424 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1426 clk_disable(cdns_uart->uartclk);
1427 clk_disable(cdns_uart->pclk);
1428 spin_unlock_irqrestore(&port->lock, flags);
1430 spin_lock_irqsave(&port->lock, flags);
1431 /* restore original rx trigger level */
1432 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1433 /* enable RX timeout interrupt */
1434 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1435 spin_unlock_irqrestore(&port->lock, flags);
1438 return uart_resume_port(&cdns_uart_uart_driver, port);
1440 #endif /* ! CONFIG_PM_SLEEP */
1441 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1443 struct platform_device *pdev = to_platform_device(dev);
1444 struct uart_port *port = platform_get_drvdata(pdev);
1445 struct cdns_uart *cdns_uart = port->private_data;
1447 clk_disable(cdns_uart->uartclk);
1448 clk_disable(cdns_uart->pclk);
1452 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1454 struct platform_device *pdev = to_platform_device(dev);
1455 struct uart_port *port = platform_get_drvdata(pdev);
1456 struct cdns_uart *cdns_uart = port->private_data;
1458 clk_enable(cdns_uart->pclk);
1459 clk_enable(cdns_uart->uartclk);
1463 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1464 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1465 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1466 cdns_runtime_resume, NULL)
1469 static const struct cdns_platform_data zynqmp_uart_def = {
1470 .quirks = CDNS_UART_RXBS_SUPPORT, };
1472 /* Match table for of_platform binding */
1473 static const struct of_device_id cdns_uart_of_match[] = {
1474 { .compatible = "xlnx,xuartps", },
1475 { .compatible = "cdns,uart-r1p8", },
1476 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1477 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1480 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1483 * cdns_uart_probe - Platform driver probe
1484 * @pdev: Pointer to the platform device structure
1486 * Return: 0 on success, negative errno otherwise
1488 static int cdns_uart_probe(struct platform_device *pdev)
1491 struct uart_port *port;
1492 struct resource *res;
1493 struct cdns_uart *cdns_uart_data;
1494 const struct of_device_id *match;
1496 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1498 if (!cdns_uart_data)
1501 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1502 if (match && match->data) {
1503 const struct cdns_platform_data *data = match->data;
1505 cdns_uart_data->quirks = data->quirks;
1508 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1509 if (IS_ERR(cdns_uart_data->pclk)) {
1510 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1511 if (!IS_ERR(cdns_uart_data->pclk))
1512 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1514 if (IS_ERR(cdns_uart_data->pclk)) {
1515 dev_err(&pdev->dev, "pclk clock not found.\n");
1516 return PTR_ERR(cdns_uart_data->pclk);
1519 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1520 if (IS_ERR(cdns_uart_data->uartclk)) {
1521 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1522 if (!IS_ERR(cdns_uart_data->uartclk))
1523 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1525 if (IS_ERR(cdns_uart_data->uartclk)) {
1526 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1527 return PTR_ERR(cdns_uart_data->uartclk);
1530 rc = clk_prepare_enable(cdns_uart_data->pclk);
1532 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1535 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1537 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1538 goto err_out_clk_dis_pclk;
1541 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1544 goto err_out_clk_disable;
1547 irq = platform_get_irq(pdev, 0);
1550 goto err_out_clk_disable;
1553 #ifdef CONFIG_COMMON_CLK
1554 cdns_uart_data->clk_rate_change_nb.notifier_call =
1555 cdns_uart_clk_notifier_cb;
1556 if (clk_notifier_register(cdns_uart_data->uartclk,
1557 &cdns_uart_data->clk_rate_change_nb))
1558 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1560 /* Look for a serialN alias */
1561 id = of_alias_get_id(pdev->dev.of_node, "serial");
1565 /* Initialize the port structure */
1566 port = cdns_uart_get_port(id);
1569 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1571 goto err_out_notif_unreg;
1575 * Register the port.
1576 * This function also registers this device with the tty layer
1577 * and triggers invocation of the config_port() entry point.
1579 port->mapbase = res->start;
1581 port->dev = &pdev->dev;
1582 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1583 port->private_data = cdns_uart_data;
1584 cdns_uart_data->port = port;
1585 platform_set_drvdata(pdev, port);
1587 pm_runtime_use_autosuspend(&pdev->dev);
1588 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1589 pm_runtime_set_active(&pdev->dev);
1590 pm_runtime_enable(&pdev->dev);
1592 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1595 "uart_add_one_port() failed; err=%i\n", rc);
1596 goto err_out_pm_disable;
1602 pm_runtime_disable(&pdev->dev);
1603 pm_runtime_set_suspended(&pdev->dev);
1604 pm_runtime_dont_use_autosuspend(&pdev->dev);
1605 err_out_notif_unreg:
1606 #ifdef CONFIG_COMMON_CLK
1607 clk_notifier_unregister(cdns_uart_data->uartclk,
1608 &cdns_uart_data->clk_rate_change_nb);
1610 err_out_clk_disable:
1611 clk_disable_unprepare(cdns_uart_data->uartclk);
1612 err_out_clk_dis_pclk:
1613 clk_disable_unprepare(cdns_uart_data->pclk);
1619 * cdns_uart_remove - called when the platform driver is unregistered
1620 * @pdev: Pointer to the platform device structure
1622 * Return: 0 on success, negative errno otherwise
1624 static int cdns_uart_remove(struct platform_device *pdev)
1626 struct uart_port *port = platform_get_drvdata(pdev);
1627 struct cdns_uart *cdns_uart_data = port->private_data;
1630 /* Remove the cdns_uart port from the serial core */
1631 #ifdef CONFIG_COMMON_CLK
1632 clk_notifier_unregister(cdns_uart_data->uartclk,
1633 &cdns_uart_data->clk_rate_change_nb);
1635 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1637 clk_disable_unprepare(cdns_uart_data->uartclk);
1638 clk_disable_unprepare(cdns_uart_data->pclk);
1639 pm_runtime_disable(&pdev->dev);
1640 pm_runtime_set_suspended(&pdev->dev);
1641 pm_runtime_dont_use_autosuspend(&pdev->dev);
1645 static struct platform_driver cdns_uart_platform_driver = {
1646 .probe = cdns_uart_probe,
1647 .remove = cdns_uart_remove,
1649 .name = CDNS_UART_NAME,
1650 .of_match_table = cdns_uart_of_match,
1651 .pm = &cdns_uart_dev_pm_ops,
1652 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1656 static int __init cdns_uart_init(void)
1660 /* Register the cdns_uart driver with the serial core */
1661 retval = uart_register_driver(&cdns_uart_uart_driver);
1665 /* Register the platform driver */
1666 retval = platform_driver_register(&cdns_uart_platform_driver);
1668 uart_unregister_driver(&cdns_uart_uart_driver);
1673 static void __exit cdns_uart_exit(void)
1675 /* Unregister the platform driver */
1676 platform_driver_unregister(&cdns_uart_platform_driver);
1678 /* Unregister the cdns_uart driver */
1679 uart_unregister_driver(&cdns_uart_uart_driver);
1682 module_init(cdns_uart_init);
1683 module_exit(cdns_uart_exit);
1685 MODULE_DESCRIPTION("Driver for Cadence UART");
1686 MODULE_AUTHOR("Xilinx Inc.");
1687 MODULE_LICENSE("GPL");