2 * Cadence UART driver (found in Xilinx Zynq)
4 * 2011 - 2014 (C) Xilinx Inc.
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
32 #include <linux/module.h>
34 #define CDNS_UART_TTY_NAME "ttyPS"
35 #define CDNS_UART_NAME "xuartps"
36 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38 #define CDNS_UART_NR_PORTS 2
39 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40 #define CDNS_UART_REGISTER_SPACE 0x1000
42 /* Rx Trigger level */
43 static int rx_trigger_level = 56;
44 module_param(rx_trigger_level, uint, S_IRUGO);
45 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
48 static int rx_timeout = 10;
49 module_param(rx_timeout, uint, S_IRUGO);
50 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
52 /* Register offsets for the UART. */
53 #define CDNS_UART_CR 0x00 /* Control Register */
54 #define CDNS_UART_MR 0x04 /* Mode Register */
55 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
56 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
57 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
58 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
59 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
60 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
61 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
62 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
63 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
64 #define CDNS_UART_SR 0x2C /* Channel Status */
65 #define CDNS_UART_FIFO 0x30 /* FIFO */
66 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
67 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
68 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
69 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
70 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
71 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
73 /* Control Register Bit Definitions */
74 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
75 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
76 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
77 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
78 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
79 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
80 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
81 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
82 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
83 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
84 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
85 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
89 * The mode register (MR) defines the mode of transfer as well as the data
90 * format. If this register is modified during transmission or reception,
91 * data validity cannot be guaranteed.
93 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
94 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
95 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
97 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
98 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
100 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
101 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
102 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
103 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
104 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
106 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
107 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
108 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
111 * Interrupt Registers:
112 * Interrupt control logic uses the interrupt enable register (IER) and the
113 * interrupt disable register (IDR) to set the value of the bits in the
114 * interrupt mask register (IMR). The IMR determines whether to pass an
115 * interrupt to the interrupt status register (ISR).
116 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
117 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
118 * Reading either IER or IDR returns 0x00.
119 * All four registers have the same bit definitions.
121 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
122 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
123 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
124 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
125 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
126 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
127 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
128 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
129 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
130 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
131 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
134 * Do not enable parity error interrupt for the following
135 * reason: When parity error interrupt is enabled, each Rx
136 * parity error always results in 2 events. The first one
137 * being parity error interrupt and the second one with a
138 * proper Rx interrupt with the incoming data. Disabling
139 * parity error interrupt ensures better handling of parity
140 * error events. With this change, for a parity error case, we
141 * get a Rx interrupt with parity error set in ISR register
142 * and we still handle parity errors in the desired way.
145 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
146 CDNS_UART_IXR_OVERRUN | \
147 CDNS_UART_IXR_RXTRIG | \
150 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
151 #define CDNS_UART_IXR_BRK 0x00002000
153 #define CDNS_UART_RXBS_SUPPORT BIT(1)
155 * Modem Control register:
156 * The read/write Modem Control register controls the interface with the modem
157 * or data set, or a peripheral device emulating a modem.
159 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
160 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
161 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
164 * Channel Status Register:
165 * The channel status register (CSR) is provided to enable the control logic
166 * to monitor the status of bits in the channel interrupt status register,
167 * even if these are masked out by the interrupt mask register.
169 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
170 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
171 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
172 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
174 /* baud dividers min/max values */
175 #define CDNS_UART_BDIV_MIN 4
176 #define CDNS_UART_BDIV_MAX 255
177 #define CDNS_UART_CD_MAX 65535
180 * struct cdns_uart - device data
181 * @port: Pointer to the UART port
182 * @uartclk: Reference clock
184 * @baud: Current baud rate
185 * @clk_rate_change_nb: Notifier block for clock changes
188 struct uart_port *port;
192 struct notifier_block clk_rate_change_nb;
195 struct cdns_platform_data {
198 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
202 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
203 * @dev_id: Id of the UART port
204 * @isrstatus: The interrupt status register value as read
207 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
209 struct uart_port *port = (struct uart_port *)dev_id;
210 struct cdns_uart *cdns_uart = port->private_data;
212 unsigned int rxbs_status = 0;
213 unsigned int status_mask;
214 unsigned int framerrprocessed = 0;
215 char status = TTY_NORMAL;
216 bool is_rxbs_support;
218 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
220 while ((readl(port->membase + CDNS_UART_SR) &
221 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
223 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
224 data = readl(port->membase + CDNS_UART_FIFO);
227 * There is no hardware break detection in Zynq, so we interpret
228 * framing error with all-zeros data as a break sequence.
229 * Most of the time, there's another non-zero byte at the
230 * end of the sequence.
232 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
234 port->read_status_mask |= CDNS_UART_IXR_BRK;
235 framerrprocessed = 1;
239 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
242 if (uart_handle_break(port))
246 isrstatus &= port->read_status_mask;
247 isrstatus &= ~port->ignore_status_mask;
248 status_mask = port->read_status_mask;
249 status_mask &= ~port->ignore_status_mask;
252 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
253 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
255 if (uart_handle_break(port))
259 if (uart_handle_sysrq_char(port, data))
262 if (is_rxbs_support) {
263 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
264 && (status_mask & CDNS_UART_IXR_PARITY)) {
265 port->icount.parity++;
268 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
269 && (status_mask & CDNS_UART_IXR_PARITY)) {
270 port->icount.frame++;
274 if (isrstatus & CDNS_UART_IXR_PARITY) {
275 port->icount.parity++;
278 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
280 port->icount.frame++;
284 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
285 port->icount.overrun++;
286 tty_insert_flip_char(&port->state->port, 0,
289 tty_insert_flip_char(&port->state->port, data, status);
292 spin_unlock(&port->lock);
293 tty_flip_buffer_push(&port->state->port);
294 spin_lock(&port->lock);
298 * cdns_uart_handle_tx - Handle the bytes to be Txed.
299 * @dev_id: Id of the UART port
302 static void cdns_uart_handle_tx(void *dev_id)
304 struct uart_port *port = (struct uart_port *)dev_id;
305 unsigned int numbytes;
307 if (uart_circ_empty(&port->state->xmit)) {
308 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
310 numbytes = port->fifosize;
311 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
312 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
314 * Get the data from the UART circular buffer
315 * and write it to the cdns_uart's TX_FIFO
319 port->state->xmit.buf[port->state->xmit.
320 tail], port->membase + CDNS_UART_FIFO);
325 * Adjust the tail of the UART buffer and wrap
326 * the buffer if it reaches limit.
328 port->state->xmit.tail =
329 (port->state->xmit.tail + 1) &
330 (UART_XMIT_SIZE - 1);
335 if (uart_circ_chars_pending(
336 &port->state->xmit) < WAKEUP_CHARS)
337 uart_write_wakeup(port);
342 * cdns_uart_isr - Interrupt handler
344 * @dev_id: Id of the port
348 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
350 struct uart_port *port = (struct uart_port *)dev_id;
351 unsigned int isrstatus;
353 spin_lock(&port->lock);
355 /* Read the interrupt status register to determine which
356 * interrupt(s) is/are active and clear them.
358 isrstatus = readl(port->membase + CDNS_UART_ISR);
359 writel(isrstatus, port->membase + CDNS_UART_ISR);
361 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
362 cdns_uart_handle_tx(dev_id);
363 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
367 * Skip RX processing if RX is disabled as RXEMPTY will never be set
368 * as read bytes will not be removed from the FIFO.
370 if (isrstatus & CDNS_UART_IXR_RXMASK &&
371 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
372 cdns_uart_handle_rx(dev_id, isrstatus);
374 spin_unlock(&port->lock);
379 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
380 * @clk: UART module input clock
381 * @baud: Desired baud rate
382 * @rbdiv: BDIV value (return value)
383 * @rcd: CD value (return value)
384 * @div8: Value for clk_sel bit in mod (return value)
385 * Return: baud rate, requested baud when possible, or actual baud when there
386 * was too much error, zero if no valid divisors are found.
388 * Formula to obtain baud rate is
389 * baud_tx/rx rate = clk/CD * (BDIV + 1)
390 * input_clk = (Uart User Defined Clock or Apb Clock)
391 * depends on UCLKEN in MR Reg
392 * clk = input_clk or input_clk/8;
393 * depends on CLKS in MR reg
394 * CD and BDIV depends on values in
395 * baud rate generate register
396 * baud rate clock divisor register
398 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
399 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
402 unsigned int calc_baud;
403 unsigned int bestbaud = 0;
404 unsigned int bauderror;
405 unsigned int besterror = ~0;
407 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
414 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
415 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
416 if (cd < 1 || cd > CDNS_UART_CD_MAX)
419 calc_baud = clk / (cd * (bdiv + 1));
421 if (baud > calc_baud)
422 bauderror = baud - calc_baud;
424 bauderror = calc_baud - baud;
426 if (besterror > bauderror) {
429 bestbaud = calc_baud;
430 besterror = bauderror;
433 /* use the values when percent error is acceptable */
434 if (((besterror * 100) / baud) < 3)
441 * cdns_uart_set_baud_rate - Calculate and set the baud rate
442 * @port: Handle to the uart port structure
443 * @baud: Baud rate to set
444 * Return: baud rate, requested baud when possible, or actual baud when there
445 * was too much error, zero if no valid divisors are found.
447 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
450 unsigned int calc_baud;
451 u32 cd = 0, bdiv = 0;
454 struct cdns_uart *cdns_uart = port->private_data;
456 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
459 /* Write new divisors to hardware */
460 mreg = readl(port->membase + CDNS_UART_MR);
462 mreg |= CDNS_UART_MR_CLKSEL;
464 mreg &= ~CDNS_UART_MR_CLKSEL;
465 writel(mreg, port->membase + CDNS_UART_MR);
466 writel(cd, port->membase + CDNS_UART_BAUDGEN);
467 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
468 cdns_uart->baud = baud;
473 #ifdef CONFIG_COMMON_CLK
475 * cdns_uart_clk_notitifer_cb - Clock notifier callback
476 * @nb: Notifier block
477 * @event: Notify event
478 * @data: Notifier data
479 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
481 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
482 unsigned long event, void *data)
485 struct uart_port *port;
487 struct clk_notifier_data *ndata = data;
488 unsigned long flags = 0;
489 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
491 port = cdns_uart->port;
496 case PRE_RATE_CHANGE:
502 * Find out if current baud-rate can be achieved with new clock
505 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
506 &bdiv, &cd, &div8)) {
507 dev_warn(port->dev, "clock rate change rejected\n");
511 spin_lock_irqsave(&cdns_uart->port->lock, flags);
513 /* Disable the TX and RX to set baud rate */
514 ctrl_reg = readl(port->membase + CDNS_UART_CR);
515 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
516 writel(ctrl_reg, port->membase + CDNS_UART_CR);
518 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
522 case POST_RATE_CHANGE:
524 * Set clk dividers to generate correct baud with new clock
528 spin_lock_irqsave(&cdns_uart->port->lock, flags);
531 port->uartclk = ndata->new_rate;
533 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
536 case ABORT_RATE_CHANGE:
538 spin_lock_irqsave(&cdns_uart->port->lock, flags);
540 /* Set TX/RX Reset */
541 ctrl_reg = readl(port->membase + CDNS_UART_CR);
542 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
543 writel(ctrl_reg, port->membase + CDNS_UART_CR);
545 while (readl(port->membase + CDNS_UART_CR) &
546 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
550 * Clear the RX disable and TX disable bits and then set the TX
551 * enable bit and RX enable bit to enable the transmitter and
554 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
555 ctrl_reg = readl(port->membase + CDNS_UART_CR);
556 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
557 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
558 writel(ctrl_reg, port->membase + CDNS_UART_CR);
560 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
570 * cdns_uart_start_tx - Start transmitting bytes
571 * @port: Handle to the uart port structure
573 static void cdns_uart_start_tx(struct uart_port *port)
577 if (uart_tx_stopped(port))
581 * Set the TX enable bit and clear the TX disable bit to enable the
584 status = readl(port->membase + CDNS_UART_CR);
585 status &= ~CDNS_UART_CR_TX_DIS;
586 status |= CDNS_UART_CR_TX_EN;
587 writel(status, port->membase + CDNS_UART_CR);
589 if (uart_circ_empty(&port->state->xmit))
592 cdns_uart_handle_tx(port);
594 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
595 /* Enable the TX Empty interrupt */
596 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
600 * cdns_uart_stop_tx - Stop TX
601 * @port: Handle to the uart port structure
603 static void cdns_uart_stop_tx(struct uart_port *port)
607 regval = readl(port->membase + CDNS_UART_CR);
608 regval |= CDNS_UART_CR_TX_DIS;
609 /* Disable the transmitter */
610 writel(regval, port->membase + CDNS_UART_CR);
614 * cdns_uart_stop_rx - Stop RX
615 * @port: Handle to the uart port structure
617 static void cdns_uart_stop_rx(struct uart_port *port)
621 /* Disable RX IRQs */
622 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
624 /* Disable the receiver */
625 regval = readl(port->membase + CDNS_UART_CR);
626 regval |= CDNS_UART_CR_RX_DIS;
627 writel(regval, port->membase + CDNS_UART_CR);
631 * cdns_uart_tx_empty - Check whether TX is empty
632 * @port: Handle to the uart port structure
634 * Return: TIOCSER_TEMT on success, 0 otherwise
636 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
640 status = readl(port->membase + CDNS_UART_SR) &
641 CDNS_UART_SR_TXEMPTY;
642 return status ? TIOCSER_TEMT : 0;
646 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
647 * transmitting char breaks
648 * @port: Handle to the uart port structure
649 * @ctl: Value based on which start or stop decision is taken
651 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
656 spin_lock_irqsave(&port->lock, flags);
658 status = readl(port->membase + CDNS_UART_CR);
661 writel(CDNS_UART_CR_STARTBRK | status,
662 port->membase + CDNS_UART_CR);
664 if ((status & CDNS_UART_CR_STOPBRK) == 0)
665 writel(CDNS_UART_CR_STOPBRK | status,
666 port->membase + CDNS_UART_CR);
668 spin_unlock_irqrestore(&port->lock, flags);
672 * cdns_uart_set_termios - termios operations, handling data length, parity,
673 * stop bits, flow control, baud rate
674 * @port: Handle to the uart port structure
675 * @termios: Handle to the input termios structure
676 * @old: Values of the previously saved termios structure
678 static void cdns_uart_set_termios(struct uart_port *port,
679 struct ktermios *termios, struct ktermios *old)
681 unsigned int cval = 0;
682 unsigned int baud, minbaud, maxbaud;
684 unsigned int ctrl_reg, mode_reg;
686 spin_lock_irqsave(&port->lock, flags);
688 /* Wait for the transmit FIFO to empty before making changes */
689 if (!(readl(port->membase + CDNS_UART_CR) &
690 CDNS_UART_CR_TX_DIS)) {
691 while (!(readl(port->membase + CDNS_UART_SR) &
692 CDNS_UART_SR_TXEMPTY)) {
697 /* Disable the TX and RX to set baud rate */
698 ctrl_reg = readl(port->membase + CDNS_UART_CR);
699 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
700 writel(ctrl_reg, port->membase + CDNS_UART_CR);
703 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
704 * min and max baud should be calculated here based on port->uartclk.
705 * this way we get a valid baud and can safely call set_baud()
707 minbaud = port->uartclk /
708 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
709 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
710 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
711 baud = cdns_uart_set_baud_rate(port, baud);
712 if (tty_termios_baud_rate(termios))
713 tty_termios_encode_baud_rate(termios, baud, baud);
715 /* Update the per-port timeout. */
716 uart_update_timeout(port, termios->c_cflag, baud);
718 /* Set TX/RX Reset */
719 ctrl_reg = readl(port->membase + CDNS_UART_CR);
720 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
721 writel(ctrl_reg, port->membase + CDNS_UART_CR);
723 while (readl(port->membase + CDNS_UART_CR) &
724 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
728 * Clear the RX disable and TX disable bits and then set the TX enable
729 * bit and RX enable bit to enable the transmitter and receiver.
731 ctrl_reg = readl(port->membase + CDNS_UART_CR);
732 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
733 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
734 writel(ctrl_reg, port->membase + CDNS_UART_CR);
736 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
738 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
739 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
740 port->ignore_status_mask = 0;
742 if (termios->c_iflag & INPCK)
743 port->read_status_mask |= CDNS_UART_IXR_PARITY |
744 CDNS_UART_IXR_FRAMING;
746 if (termios->c_iflag & IGNPAR)
747 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
748 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
750 /* ignore all characters if CREAD is not set */
751 if ((termios->c_cflag & CREAD) == 0)
752 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
753 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
754 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
756 mode_reg = readl(port->membase + CDNS_UART_MR);
758 /* Handling Data Size */
759 switch (termios->c_cflag & CSIZE) {
761 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
764 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
768 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
769 termios->c_cflag &= ~CSIZE;
770 termios->c_cflag |= CS8;
774 /* Handling Parity and Stop Bits length */
775 if (termios->c_cflag & CSTOPB)
776 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
778 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
780 if (termios->c_cflag & PARENB) {
781 /* Mark or Space parity */
782 if (termios->c_cflag & CMSPAR) {
783 if (termios->c_cflag & PARODD)
784 cval |= CDNS_UART_MR_PARITY_MARK;
786 cval |= CDNS_UART_MR_PARITY_SPACE;
788 if (termios->c_cflag & PARODD)
789 cval |= CDNS_UART_MR_PARITY_ODD;
791 cval |= CDNS_UART_MR_PARITY_EVEN;
794 cval |= CDNS_UART_MR_PARITY_NONE;
796 cval |= mode_reg & 1;
797 writel(cval, port->membase + CDNS_UART_MR);
799 spin_unlock_irqrestore(&port->lock, flags);
803 * cdns_uart_startup - Called when an application opens a cdns_uart port
804 * @port: Handle to the uart port structure
806 * Return: 0 on success, negative errno otherwise
808 static int cdns_uart_startup(struct uart_port *port)
810 struct cdns_uart *cdns_uart = port->private_data;
814 unsigned int status = 0;
816 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
818 spin_lock_irqsave(&port->lock, flags);
820 /* Disable the TX and RX */
821 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
822 port->membase + CDNS_UART_CR);
824 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
827 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
828 port->membase + CDNS_UART_CR);
830 while (readl(port->membase + CDNS_UART_CR) &
831 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
835 * Clear the RX disable bit and then set the RX enable bit to enable
838 status = readl(port->membase + CDNS_UART_CR);
839 status &= CDNS_UART_CR_RX_DIS;
840 status |= CDNS_UART_CR_RX_EN;
841 writel(status, port->membase + CDNS_UART_CR);
843 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
846 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
847 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
848 port->membase + CDNS_UART_MR);
851 * Set the RX FIFO Trigger level to use most of the FIFO, but it
852 * can be tuned with a module parameter
854 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
857 * Receive Timeout register is enabled but it
858 * can be tuned with a module parameter
860 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
862 /* Clear out any pending interrupts before enabling them */
863 writel(readl(port->membase + CDNS_UART_ISR),
864 port->membase + CDNS_UART_ISR);
866 spin_unlock_irqrestore(&port->lock, flags);
868 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
870 dev_err(port->dev, "request_irq '%d' failed with %d\n",
875 /* Set the Interrupt Registers with desired interrupts */
877 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
878 port->membase + CDNS_UART_IER);
880 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
886 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
887 * @port: Handle to the uart port structure
889 static void cdns_uart_shutdown(struct uart_port *port)
894 spin_lock_irqsave(&port->lock, flags);
896 /* Disable interrupts */
897 status = readl(port->membase + CDNS_UART_IMR);
898 writel(status, port->membase + CDNS_UART_IDR);
899 writel(0xffffffff, port->membase + CDNS_UART_ISR);
901 /* Disable the TX and RX */
902 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
903 port->membase + CDNS_UART_CR);
905 spin_unlock_irqrestore(&port->lock, flags);
907 free_irq(port->irq, port);
911 * cdns_uart_type - Set UART type to cdns_uart port
912 * @port: Handle to the uart port structure
914 * Return: string on success, NULL otherwise
916 static const char *cdns_uart_type(struct uart_port *port)
918 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
922 * cdns_uart_verify_port - Verify the port params
923 * @port: Handle to the uart port structure
924 * @ser: Handle to the structure whose members are compared
926 * Return: 0 on success, negative errno otherwise.
928 static int cdns_uart_verify_port(struct uart_port *port,
929 struct serial_struct *ser)
931 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
933 if (port->irq != ser->irq)
935 if (ser->io_type != UPIO_MEM)
937 if (port->iobase != ser->port)
945 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
946 * called when the driver adds a cdns_uart port via
947 * uart_add_one_port()
948 * @port: Handle to the uart port structure
950 * Return: 0 on success, negative errno otherwise.
952 static int cdns_uart_request_port(struct uart_port *port)
954 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
959 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
960 if (!port->membase) {
961 dev_err(port->dev, "Unable to map registers\n");
962 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
969 * cdns_uart_release_port - Release UART port
970 * @port: Handle to the uart port structure
972 * Release the memory region attached to a cdns_uart port. Called when the
973 * driver removes a cdns_uart port via uart_remove_one_port().
975 static void cdns_uart_release_port(struct uart_port *port)
977 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
978 iounmap(port->membase);
979 port->membase = NULL;
983 * cdns_uart_config_port - Configure UART port
984 * @port: Handle to the uart port structure
987 static void cdns_uart_config_port(struct uart_port *port, int flags)
989 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
990 port->type = PORT_XUARTPS;
994 * cdns_uart_get_mctrl - Get the modem control state
995 * @port: Handle to the uart port structure
997 * Return: the modem control state
999 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1001 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1004 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1008 val = readl(port->membase + CDNS_UART_MODEMCR);
1010 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1012 if (mctrl & TIOCM_RTS)
1013 val |= CDNS_UART_MODEMCR_RTS;
1014 if (mctrl & TIOCM_DTR)
1015 val |= CDNS_UART_MODEMCR_DTR;
1017 writel(val, port->membase + CDNS_UART_MODEMCR);
1020 #ifdef CONFIG_CONSOLE_POLL
1021 static int cdns_uart_poll_get_char(struct uart_port *port)
1024 unsigned long flags;
1026 spin_lock_irqsave(&port->lock, flags);
1028 /* Check if FIFO is empty */
1029 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1031 else /* Read a character */
1032 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1034 spin_unlock_irqrestore(&port->lock, flags);
1039 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1041 unsigned long flags;
1043 spin_lock_irqsave(&port->lock, flags);
1045 /* Wait until FIFO is empty */
1046 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1049 /* Write a character */
1050 writel(c, port->membase + CDNS_UART_FIFO);
1052 /* Wait until FIFO is empty */
1053 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1056 spin_unlock_irqrestore(&port->lock, flags);
1062 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1063 unsigned int oldstate)
1065 struct cdns_uart *cdns_uart = port->private_data;
1068 case UART_PM_STATE_OFF:
1069 clk_disable(cdns_uart->uartclk);
1070 clk_disable(cdns_uart->pclk);
1073 clk_enable(cdns_uart->pclk);
1074 clk_enable(cdns_uart->uartclk);
1079 static const struct uart_ops cdns_uart_ops = {
1080 .set_mctrl = cdns_uart_set_mctrl,
1081 .get_mctrl = cdns_uart_get_mctrl,
1082 .start_tx = cdns_uart_start_tx,
1083 .stop_tx = cdns_uart_stop_tx,
1084 .stop_rx = cdns_uart_stop_rx,
1085 .tx_empty = cdns_uart_tx_empty,
1086 .break_ctl = cdns_uart_break_ctl,
1087 .set_termios = cdns_uart_set_termios,
1088 .startup = cdns_uart_startup,
1089 .shutdown = cdns_uart_shutdown,
1091 .type = cdns_uart_type,
1092 .verify_port = cdns_uart_verify_port,
1093 .request_port = cdns_uart_request_port,
1094 .release_port = cdns_uart_release_port,
1095 .config_port = cdns_uart_config_port,
1096 #ifdef CONFIG_CONSOLE_POLL
1097 .poll_get_char = cdns_uart_poll_get_char,
1098 .poll_put_char = cdns_uart_poll_put_char,
1102 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1105 * cdns_uart_get_port - Configure the port from platform device resource info
1108 * Return: a pointer to a uart_port or NULL for failure
1110 static struct uart_port *cdns_uart_get_port(int id)
1112 struct uart_port *port;
1114 /* Try the given port id if failed use default method */
1115 if (id < CDNS_UART_NR_PORTS && cdns_uart_port[id].mapbase != 0) {
1116 /* Find the next unused port */
1117 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1118 if (cdns_uart_port[id].mapbase == 0)
1122 if (id >= CDNS_UART_NR_PORTS)
1125 port = &cdns_uart_port[id];
1127 /* At this point, we've got an empty uart_port struct, initialize it */
1128 spin_lock_init(&port->lock);
1129 port->membase = NULL;
1131 port->type = PORT_UNKNOWN;
1132 port->iotype = UPIO_MEM32;
1133 port->flags = UPF_BOOT_AUTOCONF;
1134 port->ops = &cdns_uart_ops;
1135 port->fifosize = CDNS_UART_FIFO_SIZE;
1141 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1143 * cdns_uart_console_wait_tx - Wait for the TX to be full
1144 * @port: Handle to the uart port structure
1146 static void cdns_uart_console_wait_tx(struct uart_port *port)
1148 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1153 * cdns_uart_console_putchar - write the character to the FIFO buffer
1154 * @port: Handle to the uart port structure
1155 * @ch: Character to be written
1157 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1159 cdns_uart_console_wait_tx(port);
1160 writel(ch, port->membase + CDNS_UART_FIFO);
1163 static void __init cdns_early_write(struct console *con, const char *s,
1166 struct earlycon_device *dev = con->data;
1168 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1171 static int __init cdns_early_console_setup(struct earlycon_device *device,
1174 struct uart_port *port = &device->port;
1179 /* initialise control register */
1180 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1181 port->membase + CDNS_UART_CR);
1183 /* only set baud if specified on command line - otherwise
1184 * assume it has been initialized by a boot loader.
1187 u32 cd = 0, bdiv = 0;
1191 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1193 mr = CDNS_UART_MR_PARITY_NONE;
1195 mr |= CDNS_UART_MR_CLKSEL;
1197 writel(mr, port->membase + CDNS_UART_MR);
1198 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1199 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1202 device->con->write = cdns_early_write;
1206 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1207 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1208 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1209 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1212 * cdns_uart_console_write - perform write operation
1213 * @co: Console handle
1214 * @s: Pointer to character array
1215 * @count: No of characters
1217 static void cdns_uart_console_write(struct console *co, const char *s,
1220 struct uart_port *port = &cdns_uart_port[co->index];
1221 unsigned long flags;
1222 unsigned int imr, ctrl;
1227 else if (oops_in_progress)
1228 locked = spin_trylock_irqsave(&port->lock, flags);
1230 spin_lock_irqsave(&port->lock, flags);
1232 /* save and disable interrupt */
1233 imr = readl(port->membase + CDNS_UART_IMR);
1234 writel(imr, port->membase + CDNS_UART_IDR);
1237 * Make sure that the tx part is enabled. Set the TX enable bit and
1238 * clear the TX disable bit to enable the transmitter.
1240 ctrl = readl(port->membase + CDNS_UART_CR);
1241 ctrl &= ~CDNS_UART_CR_TX_DIS;
1242 ctrl |= CDNS_UART_CR_TX_EN;
1243 writel(ctrl, port->membase + CDNS_UART_CR);
1245 uart_console_write(port, s, count, cdns_uart_console_putchar);
1246 cdns_uart_console_wait_tx(port);
1248 writel(ctrl, port->membase + CDNS_UART_CR);
1250 /* restore interrupt state */
1251 writel(imr, port->membase + CDNS_UART_IER);
1254 spin_unlock_irqrestore(&port->lock, flags);
1258 * cdns_uart_console_setup - Initialize the uart to default config
1259 * @co: Console handle
1260 * @options: Initial settings of uart
1262 * Return: 0 on success, negative errno otherwise.
1264 static int cdns_uart_console_setup(struct console *co, char *options)
1266 struct uart_port *port = &cdns_uart_port[co->index];
1272 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1275 if (!port->membase) {
1276 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1282 uart_parse_options(options, &baud, &parity, &bits, &flow);
1284 return uart_set_options(port, co, baud, parity, bits, flow);
1287 static struct uart_driver cdns_uart_uart_driver;
1289 static struct console cdns_uart_console = {
1290 .name = CDNS_UART_TTY_NAME,
1291 .write = cdns_uart_console_write,
1292 .device = uart_console_device,
1293 .setup = cdns_uart_console_setup,
1294 .flags = CON_PRINTBUFFER,
1295 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1296 .data = &cdns_uart_uart_driver,
1300 * cdns_uart_console_init - Initialization call
1302 * Return: 0 on success, negative errno otherwise
1304 static int __init cdns_uart_console_init(void)
1306 register_console(&cdns_uart_console);
1310 console_initcall(cdns_uart_console_init);
1312 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1314 static struct uart_driver cdns_uart_uart_driver = {
1315 .owner = THIS_MODULE,
1316 .driver_name = CDNS_UART_NAME,
1317 .dev_name = CDNS_UART_TTY_NAME,
1318 .major = CDNS_UART_MAJOR,
1319 .minor = CDNS_UART_MINOR,
1320 .nr = CDNS_UART_NR_PORTS,
1321 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1322 .cons = &cdns_uart_console,
1326 #ifdef CONFIG_PM_SLEEP
1328 * cdns_uart_suspend - suspend event
1329 * @device: Pointer to the device structure
1333 static int cdns_uart_suspend(struct device *device)
1335 struct uart_port *port = dev_get_drvdata(device);
1336 struct tty_struct *tty;
1337 struct device *tty_dev;
1340 /* Get the tty which could be NULL so don't assume it's valid */
1341 tty = tty_port_tty_get(&port->state->port);
1344 may_wake = device_may_wakeup(tty_dev);
1349 * Call the API provided in serial_core.c file which handles
1352 uart_suspend_port(&cdns_uart_uart_driver, port);
1353 if (console_suspend_enabled && !may_wake) {
1354 struct cdns_uart *cdns_uart = port->private_data;
1356 clk_disable(cdns_uart->uartclk);
1357 clk_disable(cdns_uart->pclk);
1359 unsigned long flags = 0;
1361 spin_lock_irqsave(&port->lock, flags);
1362 /* Empty the receive FIFO 1st before making changes */
1363 while (!(readl(port->membase + CDNS_UART_SR) &
1364 CDNS_UART_SR_RXEMPTY))
1365 readl(port->membase + CDNS_UART_FIFO);
1366 /* set RX trigger level to 1 */
1367 writel(1, port->membase + CDNS_UART_RXWM);
1368 /* disable RX timeout interrups */
1369 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1370 spin_unlock_irqrestore(&port->lock, flags);
1377 * cdns_uart_resume - Resume after a previous suspend
1378 * @device: Pointer to the device structure
1382 static int cdns_uart_resume(struct device *device)
1384 struct uart_port *port = dev_get_drvdata(device);
1385 unsigned long flags = 0;
1387 struct tty_struct *tty;
1388 struct device *tty_dev;
1391 /* Get the tty which could be NULL so don't assume it's valid */
1392 tty = tty_port_tty_get(&port->state->port);
1395 may_wake = device_may_wakeup(tty_dev);
1399 if (console_suspend_enabled && !may_wake) {
1400 struct cdns_uart *cdns_uart = port->private_data;
1402 clk_enable(cdns_uart->pclk);
1403 clk_enable(cdns_uart->uartclk);
1405 spin_lock_irqsave(&port->lock, flags);
1407 /* Set TX/RX Reset */
1408 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1409 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1410 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1411 while (readl(port->membase + CDNS_UART_CR) &
1412 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1415 /* restore rx timeout value */
1416 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1418 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1419 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1420 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1421 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1423 spin_unlock_irqrestore(&port->lock, flags);
1425 spin_lock_irqsave(&port->lock, flags);
1426 /* restore original rx trigger level */
1427 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1428 /* enable RX timeout interrupt */
1429 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1430 spin_unlock_irqrestore(&port->lock, flags);
1433 return uart_resume_port(&cdns_uart_uart_driver, port);
1435 #endif /* ! CONFIG_PM_SLEEP */
1437 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1440 static const struct cdns_platform_data zynqmp_uart_def = {
1441 .quirks = CDNS_UART_RXBS_SUPPORT, };
1443 /* Match table for of_platform binding */
1444 static const struct of_device_id cdns_uart_of_match[] = {
1445 { .compatible = "xlnx,xuartps", },
1446 { .compatible = "cdns,uart-r1p8", },
1447 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1448 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1451 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1454 * cdns_uart_probe - Platform driver probe
1455 * @pdev: Pointer to the platform device structure
1457 * Return: 0 on success, negative errno otherwise
1459 static int cdns_uart_probe(struct platform_device *pdev)
1462 struct uart_port *port;
1463 struct resource *res;
1464 struct cdns_uart *cdns_uart_data;
1465 const struct of_device_id *match;
1467 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1469 if (!cdns_uart_data)
1472 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1473 if (match && match->data) {
1474 const struct cdns_platform_data *data = match->data;
1476 cdns_uart_data->quirks = data->quirks;
1479 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1480 if (IS_ERR(cdns_uart_data->pclk)) {
1481 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1482 if (!IS_ERR(cdns_uart_data->pclk))
1483 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1485 if (IS_ERR(cdns_uart_data->pclk)) {
1486 dev_err(&pdev->dev, "pclk clock not found.\n");
1487 return PTR_ERR(cdns_uart_data->pclk);
1490 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1491 if (IS_ERR(cdns_uart_data->uartclk)) {
1492 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1493 if (!IS_ERR(cdns_uart_data->uartclk))
1494 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1496 if (IS_ERR(cdns_uart_data->uartclk)) {
1497 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1498 return PTR_ERR(cdns_uart_data->uartclk);
1501 rc = clk_prepare(cdns_uart_data->pclk);
1503 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1506 rc = clk_prepare(cdns_uart_data->uartclk);
1508 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1509 goto err_out_clk_dis_pclk;
1512 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1515 goto err_out_clk_disable;
1518 irq = platform_get_irq(pdev, 0);
1521 goto err_out_clk_disable;
1524 #ifdef CONFIG_COMMON_CLK
1525 cdns_uart_data->clk_rate_change_nb.notifier_call =
1526 cdns_uart_clk_notifier_cb;
1527 if (clk_notifier_register(cdns_uart_data->uartclk,
1528 &cdns_uart_data->clk_rate_change_nb))
1529 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1531 /* Look for a serialN alias */
1532 id = of_alias_get_id(pdev->dev.of_node, "serial");
1536 /* Initialize the port structure */
1537 port = cdns_uart_get_port(id);
1540 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1542 goto err_out_notif_unreg;
1546 * Register the port.
1547 * This function also registers this device with the tty layer
1548 * and triggers invocation of the config_port() entry point.
1550 port->mapbase = res->start;
1552 port->dev = &pdev->dev;
1553 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1554 port->private_data = cdns_uart_data;
1555 cdns_uart_data->port = port;
1556 platform_set_drvdata(pdev, port);
1558 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1561 "uart_add_one_port() failed; err=%i\n", rc);
1562 goto err_out_notif_unreg;
1567 err_out_notif_unreg:
1568 #ifdef CONFIG_COMMON_CLK
1569 clk_notifier_unregister(cdns_uart_data->uartclk,
1570 &cdns_uart_data->clk_rate_change_nb);
1572 err_out_clk_disable:
1573 clk_unprepare(cdns_uart_data->uartclk);
1574 err_out_clk_dis_pclk:
1575 clk_unprepare(cdns_uart_data->pclk);
1581 * cdns_uart_remove - called when the platform driver is unregistered
1582 * @pdev: Pointer to the platform device structure
1584 * Return: 0 on success, negative errno otherwise
1586 static int cdns_uart_remove(struct platform_device *pdev)
1588 struct uart_port *port = platform_get_drvdata(pdev);
1589 struct cdns_uart *cdns_uart_data = port->private_data;
1592 /* Remove the cdns_uart port from the serial core */
1593 #ifdef CONFIG_COMMON_CLK
1594 clk_notifier_unregister(cdns_uart_data->uartclk,
1595 &cdns_uart_data->clk_rate_change_nb);
1597 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1599 clk_unprepare(cdns_uart_data->uartclk);
1600 clk_unprepare(cdns_uart_data->pclk);
1604 static struct platform_driver cdns_uart_platform_driver = {
1605 .probe = cdns_uart_probe,
1606 .remove = cdns_uart_remove,
1608 .name = CDNS_UART_NAME,
1609 .of_match_table = cdns_uart_of_match,
1610 .pm = &cdns_uart_dev_pm_ops,
1611 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1615 static int __init cdns_uart_init(void)
1619 /* Register the cdns_uart driver with the serial core */
1620 retval = uart_register_driver(&cdns_uart_uart_driver);
1624 /* Register the platform driver */
1625 retval = platform_driver_register(&cdns_uart_platform_driver);
1627 uart_unregister_driver(&cdns_uart_uart_driver);
1632 static void __exit cdns_uart_exit(void)
1634 /* Unregister the platform driver */
1635 platform_driver_unregister(&cdns_uart_platform_driver);
1637 /* Unregister the cdns_uart driver */
1638 uart_unregister_driver(&cdns_uart_uart_driver);
1641 module_init(cdns_uart_init);
1642 module_exit(cdns_uart_exit);
1644 MODULE_DESCRIPTION("Driver for Cadence UART");
1645 MODULE_AUTHOR("Xilinx Inc.");
1646 MODULE_LICENSE("GPL");