1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * 2011 - 2014 (C) Xilinx Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/platform_device.h>
17 #include <linux/serial.h>
18 #include <linux/console.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/clk.h>
24 #include <linux/irq.h>
27 #include <linux/module.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/iopoll.h>
31 #define CDNS_UART_TTY_NAME "ttyPS"
32 #define CDNS_UART_NAME "xuartps"
33 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
34 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
35 #define CDNS_UART_NR_PORTS 2
36 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
37 #define CDNS_UART_REGISTER_SPACE 0x1000
38 #define TX_TIMEOUT 500000
40 /* Rx Trigger level */
41 static int rx_trigger_level = 56;
42 module_param(rx_trigger_level, uint, S_IRUGO);
43 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46 static int rx_timeout = 10;
47 module_param(rx_timeout, uint, S_IRUGO);
48 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
50 /* Register offsets for the UART. */
51 #define CDNS_UART_CR 0x00 /* Control Register */
52 #define CDNS_UART_MR 0x04 /* Mode Register */
53 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
54 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
55 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
56 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
57 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
58 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
59 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
60 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
61 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
62 #define CDNS_UART_SR 0x2C /* Channel Status */
63 #define CDNS_UART_FIFO 0x30 /* FIFO */
64 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
65 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
66 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
67 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
68 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
69 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
71 /* Control Register Bit Definitions */
72 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
73 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
74 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
75 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
76 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
77 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
78 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
79 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
80 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
81 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
82 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
83 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
87 * The mode register (MR) defines the mode of transfer as well as the data
88 * format. If this register is modified during transmission or reception,
89 * data validity cannot be guaranteed.
91 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
92 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
93 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
94 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
96 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
97 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
99 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
100 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
101 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
102 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
103 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
105 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
106 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
107 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
110 * Interrupt Registers:
111 * Interrupt control logic uses the interrupt enable register (IER) and the
112 * interrupt disable register (IDR) to set the value of the bits in the
113 * interrupt mask register (IMR). The IMR determines whether to pass an
114 * interrupt to the interrupt status register (ISR).
115 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
116 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
117 * Reading either IER or IDR returns 0x00.
118 * All four registers have the same bit definitions.
120 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
121 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
122 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
123 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
124 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
125 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
126 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
127 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
128 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
129 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
130 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
133 * Do not enable parity error interrupt for the following
134 * reason: When parity error interrupt is enabled, each Rx
135 * parity error always results in 2 events. The first one
136 * being parity error interrupt and the second one with a
137 * proper Rx interrupt with the incoming data. Disabling
138 * parity error interrupt ensures better handling of parity
139 * error events. With this change, for a parity error case, we
140 * get a Rx interrupt with parity error set in ISR register
141 * and we still handle parity errors in the desired way.
144 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
145 CDNS_UART_IXR_OVERRUN | \
146 CDNS_UART_IXR_RXTRIG | \
149 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
150 #define CDNS_UART_IXR_BRK 0x00002000
152 #define CDNS_UART_RXBS_SUPPORT BIT(1)
154 * Modem Control register:
155 * The read/write Modem Control register controls the interface with the modem
156 * or data set, or a peripheral device emulating a modem.
158 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
159 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
160 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
163 * Channel Status Register:
164 * The channel status register (CSR) is provided to enable the control logic
165 * to monitor the status of bits in the channel interrupt status register,
166 * even if these are masked out by the interrupt mask register.
168 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
169 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
170 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
171 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
172 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
174 /* baud dividers min/max values */
175 #define CDNS_UART_BDIV_MIN 4
176 #define CDNS_UART_BDIV_MAX 255
177 #define CDNS_UART_CD_MAX 65535
178 #define UART_AUTOSUSPEND_TIMEOUT 3000
181 * struct cdns_uart - device data
182 * @port: Pointer to the UART port
183 * @uartclk: Reference clock
185 * @baud: Current baud rate
186 * @clk_rate_change_nb: Notifier block for clock changes
187 * @quirks: Flags for RXBS support.
190 struct uart_port *port;
194 struct notifier_block clk_rate_change_nb;
197 struct cdns_platform_data {
200 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
204 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
205 * @dev_id: Id of the UART port
206 * @isrstatus: The interrupt status register value as read
209 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
211 struct uart_port *port = (struct uart_port *)dev_id;
212 struct cdns_uart *cdns_uart = port->private_data;
214 unsigned int rxbs_status = 0;
215 unsigned int status_mask;
216 unsigned int framerrprocessed = 0;
217 char status = TTY_NORMAL;
218 bool is_rxbs_support;
220 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
222 while ((readl(port->membase + CDNS_UART_SR) &
223 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
225 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
226 data = readl(port->membase + CDNS_UART_FIFO);
229 * There is no hardware break detection in Zynq, so we interpret
230 * framing error with all-zeros data as a break sequence.
231 * Most of the time, there's another non-zero byte at the
232 * end of the sequence.
234 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
236 port->read_status_mask |= CDNS_UART_IXR_BRK;
237 framerrprocessed = 1;
241 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
244 if (uart_handle_break(port))
248 isrstatus &= port->read_status_mask;
249 isrstatus &= ~port->ignore_status_mask;
250 status_mask = port->read_status_mask;
251 status_mask &= ~port->ignore_status_mask;
254 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
255 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
257 if (uart_handle_break(port))
261 if (uart_handle_sysrq_char(port, data))
264 if (is_rxbs_support) {
265 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
266 && (status_mask & CDNS_UART_IXR_PARITY)) {
267 port->icount.parity++;
270 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
271 && (status_mask & CDNS_UART_IXR_PARITY)) {
272 port->icount.frame++;
276 if (isrstatus & CDNS_UART_IXR_PARITY) {
277 port->icount.parity++;
280 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
282 port->icount.frame++;
286 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
287 port->icount.overrun++;
288 tty_insert_flip_char(&port->state->port, 0,
291 tty_insert_flip_char(&port->state->port, data, status);
294 spin_unlock(&port->lock);
295 tty_flip_buffer_push(&port->state->port);
296 spin_lock(&port->lock);
300 * cdns_uart_handle_tx - Handle the bytes to be Txed.
301 * @dev_id: Id of the UART port
304 static void cdns_uart_handle_tx(void *dev_id)
306 struct uart_port *port = (struct uart_port *)dev_id;
307 unsigned int numbytes;
309 if (uart_circ_empty(&port->state->xmit)) {
310 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
312 numbytes = port->fifosize;
313 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
314 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
316 * Get the data from the UART circular buffer
317 * and write it to the cdns_uart's TX_FIFO
321 port->state->xmit.buf[port->state->xmit.
322 tail], port->membase + CDNS_UART_FIFO);
327 * Adjust the tail of the UART buffer and wrap
328 * the buffer if it reaches limit.
330 port->state->xmit.tail =
331 (port->state->xmit.tail + 1) &
332 (UART_XMIT_SIZE - 1);
337 if (uart_circ_chars_pending(
338 &port->state->xmit) < WAKEUP_CHARS)
339 uart_write_wakeup(port);
344 * cdns_uart_isr - Interrupt handler
346 * @dev_id: Id of the port
350 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
352 struct uart_port *port = (struct uart_port *)dev_id;
353 unsigned int isrstatus;
355 spin_lock(&port->lock);
357 /* Read the interrupt status register to determine which
358 * interrupt(s) is/are active and clear them.
360 isrstatus = readl(port->membase + CDNS_UART_ISR);
361 writel(isrstatus, port->membase + CDNS_UART_ISR);
363 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
364 cdns_uart_handle_tx(dev_id);
365 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
369 * Skip RX processing if RX is disabled as RXEMPTY will never be set
370 * as read bytes will not be removed from the FIFO.
372 if (isrstatus & CDNS_UART_IXR_RXMASK &&
373 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
374 cdns_uart_handle_rx(dev_id, isrstatus);
376 spin_unlock(&port->lock);
381 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
382 * @clk: UART module input clock
383 * @baud: Desired baud rate
384 * @rbdiv: BDIV value (return value)
385 * @rcd: CD value (return value)
386 * @div8: Value for clk_sel bit in mod (return value)
387 * Return: baud rate, requested baud when possible, or actual baud when there
388 * was too much error, zero if no valid divisors are found.
390 * Formula to obtain baud rate is
391 * baud_tx/rx rate = clk/CD * (BDIV + 1)
392 * input_clk = (Uart User Defined Clock or Apb Clock)
393 * depends on UCLKEN in MR Reg
394 * clk = input_clk or input_clk/8;
395 * depends on CLKS in MR reg
396 * CD and BDIV depends on values in
397 * baud rate generate register
398 * baud rate clock divisor register
400 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
401 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
404 unsigned int calc_baud;
405 unsigned int bestbaud = 0;
406 unsigned int bauderror;
407 unsigned int besterror = ~0;
409 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
416 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
417 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
418 if (cd < 1 || cd > CDNS_UART_CD_MAX)
421 calc_baud = clk / (cd * (bdiv + 1));
423 if (baud > calc_baud)
424 bauderror = baud - calc_baud;
426 bauderror = calc_baud - baud;
428 if (besterror > bauderror) {
431 bestbaud = calc_baud;
432 besterror = bauderror;
435 /* use the values when percent error is acceptable */
436 if (((besterror * 100) / baud) < 3)
443 * cdns_uart_set_baud_rate - Calculate and set the baud rate
444 * @port: Handle to the uart port structure
445 * @baud: Baud rate to set
446 * Return: baud rate, requested baud when possible, or actual baud when there
447 * was too much error, zero if no valid divisors are found.
449 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
452 unsigned int calc_baud;
453 u32 cd = 0, bdiv = 0;
456 struct cdns_uart *cdns_uart = port->private_data;
458 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
461 /* Write new divisors to hardware */
462 mreg = readl(port->membase + CDNS_UART_MR);
464 mreg |= CDNS_UART_MR_CLKSEL;
466 mreg &= ~CDNS_UART_MR_CLKSEL;
467 writel(mreg, port->membase + CDNS_UART_MR);
468 writel(cd, port->membase + CDNS_UART_BAUDGEN);
469 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
470 cdns_uart->baud = baud;
475 #ifdef CONFIG_COMMON_CLK
477 * cdns_uart_clk_notitifer_cb - Clock notifier callback
478 * @nb: Notifier block
479 * @event: Notify event
480 * @data: Notifier data
481 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
483 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
484 unsigned long event, void *data)
487 struct uart_port *port;
489 struct clk_notifier_data *ndata = data;
490 unsigned long flags = 0;
491 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
493 port = cdns_uart->port;
498 case PRE_RATE_CHANGE:
504 * Find out if current baud-rate can be achieved with new clock
507 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
508 &bdiv, &cd, &div8)) {
509 dev_warn(port->dev, "clock rate change rejected\n");
513 spin_lock_irqsave(&cdns_uart->port->lock, flags);
515 /* Disable the TX and RX to set baud rate */
516 ctrl_reg = readl(port->membase + CDNS_UART_CR);
517 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
518 writel(ctrl_reg, port->membase + CDNS_UART_CR);
520 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
524 case POST_RATE_CHANGE:
526 * Set clk dividers to generate correct baud with new clock
530 spin_lock_irqsave(&cdns_uart->port->lock, flags);
533 port->uartclk = ndata->new_rate;
535 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
538 case ABORT_RATE_CHANGE:
540 spin_lock_irqsave(&cdns_uart->port->lock, flags);
542 /* Set TX/RX Reset */
543 ctrl_reg = readl(port->membase + CDNS_UART_CR);
544 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
545 writel(ctrl_reg, port->membase + CDNS_UART_CR);
547 while (readl(port->membase + CDNS_UART_CR) &
548 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
552 * Clear the RX disable and TX disable bits and then set the TX
553 * enable bit and RX enable bit to enable the transmitter and
556 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
557 ctrl_reg = readl(port->membase + CDNS_UART_CR);
558 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
559 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
560 writel(ctrl_reg, port->membase + CDNS_UART_CR);
562 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
572 * cdns_uart_start_tx - Start transmitting bytes
573 * @port: Handle to the uart port structure
575 static void cdns_uart_start_tx(struct uart_port *port)
579 if (uart_tx_stopped(port))
583 * Set the TX enable bit and clear the TX disable bit to enable the
586 status = readl(port->membase + CDNS_UART_CR);
587 status &= ~CDNS_UART_CR_TX_DIS;
588 status |= CDNS_UART_CR_TX_EN;
589 writel(status, port->membase + CDNS_UART_CR);
591 if (uart_circ_empty(&port->state->xmit))
594 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
596 cdns_uart_handle_tx(port);
598 /* Enable the TX Empty interrupt */
599 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
603 * cdns_uart_stop_tx - Stop TX
604 * @port: Handle to the uart port structure
606 static void cdns_uart_stop_tx(struct uart_port *port)
610 regval = readl(port->membase + CDNS_UART_CR);
611 regval |= CDNS_UART_CR_TX_DIS;
612 /* Disable the transmitter */
613 writel(regval, port->membase + CDNS_UART_CR);
617 * cdns_uart_stop_rx - Stop RX
618 * @port: Handle to the uart port structure
620 static void cdns_uart_stop_rx(struct uart_port *port)
624 /* Disable RX IRQs */
625 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
627 /* Disable the receiver */
628 regval = readl(port->membase + CDNS_UART_CR);
629 regval |= CDNS_UART_CR_RX_DIS;
630 writel(regval, port->membase + CDNS_UART_CR);
634 * cdns_uart_tx_empty - Check whether TX is empty
635 * @port: Handle to the uart port structure
637 * Return: TIOCSER_TEMT on success, 0 otherwise
639 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
643 status = readl(port->membase + CDNS_UART_SR) &
644 CDNS_UART_SR_TXEMPTY;
645 return status ? TIOCSER_TEMT : 0;
649 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
650 * transmitting char breaks
651 * @port: Handle to the uart port structure
652 * @ctl: Value based on which start or stop decision is taken
654 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
659 spin_lock_irqsave(&port->lock, flags);
661 status = readl(port->membase + CDNS_UART_CR);
664 writel(CDNS_UART_CR_STARTBRK | status,
665 port->membase + CDNS_UART_CR);
667 if ((status & CDNS_UART_CR_STOPBRK) == 0)
668 writel(CDNS_UART_CR_STOPBRK | status,
669 port->membase + CDNS_UART_CR);
671 spin_unlock_irqrestore(&port->lock, flags);
675 * cdns_uart_set_termios - termios operations, handling data length, parity,
676 * stop bits, flow control, baud rate
677 * @port: Handle to the uart port structure
678 * @termios: Handle to the input termios structure
679 * @old: Values of the previously saved termios structure
681 static void cdns_uart_set_termios(struct uart_port *port,
682 struct ktermios *termios, struct ktermios *old)
684 unsigned int cval = 0;
685 unsigned int baud, minbaud, maxbaud;
687 unsigned int ctrl_reg, mode_reg, val;
690 /* Wait for the transmit FIFO to empty before making changes */
691 if (!(readl(port->membase + CDNS_UART_CR) &
692 CDNS_UART_CR_TX_DIS)) {
693 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
694 val, (val & CDNS_UART_SR_TXEMPTY),
697 dev_err(port->dev, "timed out waiting for tx empty");
701 spin_lock_irqsave(&port->lock, flags);
703 /* Disable the TX and RX to set baud rate */
704 ctrl_reg = readl(port->membase + CDNS_UART_CR);
705 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
706 writel(ctrl_reg, port->membase + CDNS_UART_CR);
709 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
710 * min and max baud should be calculated here based on port->uartclk.
711 * this way we get a valid baud and can safely call set_baud()
713 minbaud = port->uartclk /
714 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
715 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
716 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
717 baud = cdns_uart_set_baud_rate(port, baud);
718 if (tty_termios_baud_rate(termios))
719 tty_termios_encode_baud_rate(termios, baud, baud);
721 /* Update the per-port timeout. */
722 uart_update_timeout(port, termios->c_cflag, baud);
724 /* Set TX/RX Reset */
725 ctrl_reg = readl(port->membase + CDNS_UART_CR);
726 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
727 writel(ctrl_reg, port->membase + CDNS_UART_CR);
729 while (readl(port->membase + CDNS_UART_CR) &
730 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
734 * Clear the RX disable and TX disable bits and then set the TX enable
735 * bit and RX enable bit to enable the transmitter and receiver.
737 ctrl_reg = readl(port->membase + CDNS_UART_CR);
738 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
739 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
740 writel(ctrl_reg, port->membase + CDNS_UART_CR);
742 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
744 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
745 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
746 port->ignore_status_mask = 0;
748 if (termios->c_iflag & INPCK)
749 port->read_status_mask |= CDNS_UART_IXR_PARITY |
750 CDNS_UART_IXR_FRAMING;
752 if (termios->c_iflag & IGNPAR)
753 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
754 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
756 /* ignore all characters if CREAD is not set */
757 if ((termios->c_cflag & CREAD) == 0)
758 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
759 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
760 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
762 mode_reg = readl(port->membase + CDNS_UART_MR);
764 /* Handling Data Size */
765 switch (termios->c_cflag & CSIZE) {
767 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
770 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
774 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
775 termios->c_cflag &= ~CSIZE;
776 termios->c_cflag |= CS8;
780 /* Handling Parity and Stop Bits length */
781 if (termios->c_cflag & CSTOPB)
782 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
784 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
786 if (termios->c_cflag & PARENB) {
787 /* Mark or Space parity */
788 if (termios->c_cflag & CMSPAR) {
789 if (termios->c_cflag & PARODD)
790 cval |= CDNS_UART_MR_PARITY_MARK;
792 cval |= CDNS_UART_MR_PARITY_SPACE;
794 if (termios->c_cflag & PARODD)
795 cval |= CDNS_UART_MR_PARITY_ODD;
797 cval |= CDNS_UART_MR_PARITY_EVEN;
800 cval |= CDNS_UART_MR_PARITY_NONE;
802 cval |= mode_reg & 1;
803 writel(cval, port->membase + CDNS_UART_MR);
805 spin_unlock_irqrestore(&port->lock, flags);
809 * cdns_uart_startup - Called when an application opens a cdns_uart port
810 * @port: Handle to the uart port structure
812 * Return: 0 on success, negative errno otherwise
814 static int cdns_uart_startup(struct uart_port *port)
816 struct cdns_uart *cdns_uart = port->private_data;
820 unsigned int status = 0;
822 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
824 spin_lock_irqsave(&port->lock, flags);
826 /* Disable the TX and RX */
827 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
828 port->membase + CDNS_UART_CR);
830 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
833 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
834 port->membase + CDNS_UART_CR);
836 while (readl(port->membase + CDNS_UART_CR) &
837 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
841 * Clear the RX disable bit and then set the RX enable bit to enable
844 status = readl(port->membase + CDNS_UART_CR);
845 status &= ~CDNS_UART_CR_RX_DIS;
846 status |= CDNS_UART_CR_RX_EN;
847 writel(status, port->membase + CDNS_UART_CR);
849 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
852 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
853 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
854 port->membase + CDNS_UART_MR);
857 * Set the RX FIFO Trigger level to use most of the FIFO, but it
858 * can be tuned with a module parameter
860 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
863 * Receive Timeout register is enabled but it
864 * can be tuned with a module parameter
866 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
868 /* Clear out any pending interrupts before enabling them */
869 writel(readl(port->membase + CDNS_UART_ISR),
870 port->membase + CDNS_UART_ISR);
872 spin_unlock_irqrestore(&port->lock, flags);
874 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
876 dev_err(port->dev, "request_irq '%d' failed with %d\n",
881 /* Set the Interrupt Registers with desired interrupts */
883 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
884 port->membase + CDNS_UART_IER);
886 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
892 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
893 * @port: Handle to the uart port structure
895 static void cdns_uart_shutdown(struct uart_port *port)
900 spin_lock_irqsave(&port->lock, flags);
902 /* Disable interrupts */
903 status = readl(port->membase + CDNS_UART_IMR);
904 writel(status, port->membase + CDNS_UART_IDR);
905 writel(0xffffffff, port->membase + CDNS_UART_ISR);
907 /* Disable the TX and RX */
908 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
909 port->membase + CDNS_UART_CR);
911 spin_unlock_irqrestore(&port->lock, flags);
913 free_irq(port->irq, port);
917 * cdns_uart_type - Set UART type to cdns_uart port
918 * @port: Handle to the uart port structure
920 * Return: string on success, NULL otherwise
922 static const char *cdns_uart_type(struct uart_port *port)
924 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
928 * cdns_uart_verify_port - Verify the port params
929 * @port: Handle to the uart port structure
930 * @ser: Handle to the structure whose members are compared
932 * Return: 0 on success, negative errno otherwise.
934 static int cdns_uart_verify_port(struct uart_port *port,
935 struct serial_struct *ser)
937 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
939 if (port->irq != ser->irq)
941 if (ser->io_type != UPIO_MEM)
943 if (port->iobase != ser->port)
951 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
952 * called when the driver adds a cdns_uart port via
953 * uart_add_one_port()
954 * @port: Handle to the uart port structure
956 * Return: 0 on success, negative errno otherwise.
958 static int cdns_uart_request_port(struct uart_port *port)
960 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
965 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
966 if (!port->membase) {
967 dev_err(port->dev, "Unable to map registers\n");
968 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
975 * cdns_uart_release_port - Release UART port
976 * @port: Handle to the uart port structure
978 * Release the memory region attached to a cdns_uart port. Called when the
979 * driver removes a cdns_uart port via uart_remove_one_port().
981 static void cdns_uart_release_port(struct uart_port *port)
983 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
984 iounmap(port->membase);
985 port->membase = NULL;
989 * cdns_uart_config_port - Configure UART port
990 * @port: Handle to the uart port structure
993 static void cdns_uart_config_port(struct uart_port *port, int flags)
995 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
996 port->type = PORT_XUARTPS;
1000 * cdns_uart_get_mctrl - Get the modem control state
1001 * @port: Handle to the uart port structure
1003 * Return: the modem control state
1005 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1007 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1010 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1015 val = readl(port->membase + CDNS_UART_MODEMCR);
1016 mode_reg = readl(port->membase + CDNS_UART_MR);
1018 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1019 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1021 if (mctrl & TIOCM_RTS)
1022 val |= CDNS_UART_MODEMCR_RTS;
1023 if (mctrl & TIOCM_DTR)
1024 val |= CDNS_UART_MODEMCR_DTR;
1025 if (mctrl & TIOCM_LOOP)
1026 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1028 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1030 writel(val, port->membase + CDNS_UART_MODEMCR);
1031 writel(mode_reg, port->membase + CDNS_UART_MR);
1034 #ifdef CONFIG_CONSOLE_POLL
1035 static int cdns_uart_poll_get_char(struct uart_port *port)
1038 unsigned long flags;
1040 spin_lock_irqsave(&port->lock, flags);
1042 /* Check if FIFO is empty */
1043 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1045 else /* Read a character */
1046 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1048 spin_unlock_irqrestore(&port->lock, flags);
1053 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1055 unsigned long flags;
1057 spin_lock_irqsave(&port->lock, flags);
1059 /* Wait until FIFO is empty */
1060 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1063 /* Write a character */
1064 writel(c, port->membase + CDNS_UART_FIFO);
1066 /* Wait until FIFO is empty */
1067 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1070 spin_unlock_irqrestore(&port->lock, flags);
1076 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1077 unsigned int oldstate)
1080 case UART_PM_STATE_OFF:
1081 pm_runtime_mark_last_busy(port->dev);
1082 pm_runtime_put_autosuspend(port->dev);
1085 pm_runtime_get_sync(port->dev);
1090 static const struct uart_ops cdns_uart_ops = {
1091 .set_mctrl = cdns_uart_set_mctrl,
1092 .get_mctrl = cdns_uart_get_mctrl,
1093 .start_tx = cdns_uart_start_tx,
1094 .stop_tx = cdns_uart_stop_tx,
1095 .stop_rx = cdns_uart_stop_rx,
1096 .tx_empty = cdns_uart_tx_empty,
1097 .break_ctl = cdns_uart_break_ctl,
1098 .set_termios = cdns_uart_set_termios,
1099 .startup = cdns_uart_startup,
1100 .shutdown = cdns_uart_shutdown,
1102 .type = cdns_uart_type,
1103 .verify_port = cdns_uart_verify_port,
1104 .request_port = cdns_uart_request_port,
1105 .release_port = cdns_uart_release_port,
1106 .config_port = cdns_uart_config_port,
1107 #ifdef CONFIG_CONSOLE_POLL
1108 .poll_get_char = cdns_uart_poll_get_char,
1109 .poll_put_char = cdns_uart_poll_put_char,
1113 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1115 * cdns_uart_console_putchar - write the character to the FIFO buffer
1116 * @port: Handle to the uart port structure
1117 * @ch: Character to be written
1119 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1121 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1123 writel(ch, port->membase + CDNS_UART_FIFO);
1126 static void cdns_early_write(struct console *con, const char *s,
1129 struct earlycon_device *dev = con->data;
1131 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1134 static int __init cdns_early_console_setup(struct earlycon_device *device,
1137 struct uart_port *port = &device->port;
1142 /* initialise control register */
1143 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1144 port->membase + CDNS_UART_CR);
1146 /* only set baud if specified on command line - otherwise
1147 * assume it has been initialized by a boot loader.
1149 if (port->uartclk && device->baud) {
1150 u32 cd = 0, bdiv = 0;
1154 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1156 mr = CDNS_UART_MR_PARITY_NONE;
1158 mr |= CDNS_UART_MR_CLKSEL;
1160 writel(mr, port->membase + CDNS_UART_MR);
1161 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1162 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1165 device->con->write = cdns_early_write;
1169 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1170 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1171 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1172 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1175 /* Static pointer to console port */
1176 static struct uart_port *console_port;
1179 * cdns_uart_console_write - perform write operation
1180 * @co: Console handle
1181 * @s: Pointer to character array
1182 * @count: No of characters
1184 static void cdns_uart_console_write(struct console *co, const char *s,
1187 struct uart_port *port = console_port;
1188 unsigned long flags;
1189 unsigned int imr, ctrl;
1194 else if (oops_in_progress)
1195 locked = spin_trylock_irqsave(&port->lock, flags);
1197 spin_lock_irqsave(&port->lock, flags);
1199 /* save and disable interrupt */
1200 imr = readl(port->membase + CDNS_UART_IMR);
1201 writel(imr, port->membase + CDNS_UART_IDR);
1204 * Make sure that the tx part is enabled. Set the TX enable bit and
1205 * clear the TX disable bit to enable the transmitter.
1207 ctrl = readl(port->membase + CDNS_UART_CR);
1208 ctrl &= ~CDNS_UART_CR_TX_DIS;
1209 ctrl |= CDNS_UART_CR_TX_EN;
1210 writel(ctrl, port->membase + CDNS_UART_CR);
1212 uart_console_write(port, s, count, cdns_uart_console_putchar);
1213 while ((readl(port->membase + CDNS_UART_SR) &
1214 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1215 CDNS_UART_SR_TXEMPTY)
1218 /* restore interrupt state */
1219 writel(imr, port->membase + CDNS_UART_IER);
1222 spin_unlock_irqrestore(&port->lock, flags);
1226 * cdns_uart_console_setup - Initialize the uart to default config
1227 * @co: Console handle
1228 * @options: Initial settings of uart
1230 * Return: 0 on success, negative errno otherwise.
1232 static int cdns_uart_console_setup(struct console *co, char *options)
1234 struct uart_port *port = console_port;
1240 unsigned long time_out;
1242 if (!port->membase) {
1243 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1249 uart_parse_options(options, &baud, &parity, &bits, &flow);
1251 /* Wait for tx_empty before setting up the console */
1252 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1254 while (time_before(jiffies, time_out) &&
1255 cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1258 return uart_set_options(port, co, baud, parity, bits, flow);
1261 static struct uart_driver cdns_uart_uart_driver;
1263 static struct console cdns_uart_console = {
1264 .name = CDNS_UART_TTY_NAME,
1265 .write = cdns_uart_console_write,
1266 .device = uart_console_device,
1267 .setup = cdns_uart_console_setup,
1268 .flags = CON_PRINTBUFFER,
1269 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1270 .data = &cdns_uart_uart_driver,
1272 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1274 static struct uart_driver cdns_uart_uart_driver = {
1275 .owner = THIS_MODULE,
1276 .driver_name = CDNS_UART_NAME,
1277 .dev_name = CDNS_UART_TTY_NAME,
1278 .major = CDNS_UART_MAJOR,
1279 .minor = CDNS_UART_MINOR,
1280 .nr = CDNS_UART_NR_PORTS,
1281 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1282 .cons = &cdns_uart_console,
1286 #ifdef CONFIG_PM_SLEEP
1288 * cdns_uart_suspend - suspend event
1289 * @device: Pointer to the device structure
1293 static int cdns_uart_suspend(struct device *device)
1295 struct uart_port *port = dev_get_drvdata(device);
1298 may_wake = device_may_wakeup(device);
1300 if (console_suspend_enabled && may_wake) {
1301 unsigned long flags = 0;
1303 spin_lock_irqsave(&port->lock, flags);
1304 /* Empty the receive FIFO 1st before making changes */
1305 while (!(readl(port->membase + CDNS_UART_SR) &
1306 CDNS_UART_SR_RXEMPTY))
1307 readl(port->membase + CDNS_UART_FIFO);
1308 /* set RX trigger level to 1 */
1309 writel(1, port->membase + CDNS_UART_RXWM);
1310 /* disable RX timeout interrups */
1311 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1312 spin_unlock_irqrestore(&port->lock, flags);
1316 * Call the API provided in serial_core.c file which handles
1319 return uart_suspend_port(&cdns_uart_uart_driver, port);
1323 * cdns_uart_resume - Resume after a previous suspend
1324 * @device: Pointer to the device structure
1328 static int cdns_uart_resume(struct device *device)
1330 struct uart_port *port = dev_get_drvdata(device);
1331 unsigned long flags = 0;
1335 may_wake = device_may_wakeup(device);
1337 if (console_suspend_enabled && !may_wake) {
1338 struct cdns_uart *cdns_uart = port->private_data;
1340 clk_enable(cdns_uart->pclk);
1341 clk_enable(cdns_uart->uartclk);
1343 spin_lock_irqsave(&port->lock, flags);
1345 /* Set TX/RX Reset */
1346 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1347 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1348 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1349 while (readl(port->membase + CDNS_UART_CR) &
1350 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1353 /* restore rx timeout value */
1354 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1356 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1357 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1358 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1359 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1361 clk_disable(cdns_uart->uartclk);
1362 clk_disable(cdns_uart->pclk);
1363 spin_unlock_irqrestore(&port->lock, flags);
1365 spin_lock_irqsave(&port->lock, flags);
1366 /* restore original rx trigger level */
1367 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1368 /* enable RX timeout interrupt */
1369 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1370 spin_unlock_irqrestore(&port->lock, flags);
1373 return uart_resume_port(&cdns_uart_uart_driver, port);
1375 #endif /* ! CONFIG_PM_SLEEP */
1376 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1378 struct uart_port *port = dev_get_drvdata(dev);
1379 struct cdns_uart *cdns_uart = port->private_data;
1381 clk_disable(cdns_uart->uartclk);
1382 clk_disable(cdns_uart->pclk);
1386 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1388 struct uart_port *port = dev_get_drvdata(dev);
1389 struct cdns_uart *cdns_uart = port->private_data;
1391 clk_enable(cdns_uart->pclk);
1392 clk_enable(cdns_uart->uartclk);
1396 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1397 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1398 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1399 cdns_runtime_resume, NULL)
1402 static const struct cdns_platform_data zynqmp_uart_def = {
1403 .quirks = CDNS_UART_RXBS_SUPPORT, };
1405 /* Match table for of_platform binding */
1406 static const struct of_device_id cdns_uart_of_match[] = {
1407 { .compatible = "xlnx,xuartps", },
1408 { .compatible = "cdns,uart-r1p8", },
1409 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1410 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1413 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1416 * cdns_uart_probe - Platform driver probe
1417 * @pdev: Pointer to the platform device structure
1419 * Return: 0 on success, negative errno otherwise
1421 static int cdns_uart_probe(struct platform_device *pdev)
1424 struct uart_port *port;
1425 struct resource *res;
1426 struct cdns_uart *cdns_uart_data;
1427 const struct of_device_id *match;
1429 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1431 if (!cdns_uart_data)
1433 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1437 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1438 if (match && match->data) {
1439 const struct cdns_platform_data *data = match->data;
1441 cdns_uart_data->quirks = data->quirks;
1444 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1445 if (IS_ERR(cdns_uart_data->pclk)) {
1446 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1447 if (!IS_ERR(cdns_uart_data->pclk))
1448 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1450 if (IS_ERR(cdns_uart_data->pclk)) {
1451 dev_err(&pdev->dev, "pclk clock not found.\n");
1452 return PTR_ERR(cdns_uart_data->pclk);
1455 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1456 if (IS_ERR(cdns_uart_data->uartclk)) {
1457 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1458 if (!IS_ERR(cdns_uart_data->uartclk))
1459 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1461 if (IS_ERR(cdns_uart_data->uartclk)) {
1462 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1463 return PTR_ERR(cdns_uart_data->uartclk);
1466 rc = clk_prepare_enable(cdns_uart_data->pclk);
1468 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1471 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1473 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1474 goto err_out_clk_dis_pclk;
1477 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1480 goto err_out_clk_disable;
1483 irq = platform_get_irq(pdev, 0);
1486 goto err_out_clk_disable;
1489 #ifdef CONFIG_COMMON_CLK
1490 cdns_uart_data->clk_rate_change_nb.notifier_call =
1491 cdns_uart_clk_notifier_cb;
1492 if (clk_notifier_register(cdns_uart_data->uartclk,
1493 &cdns_uart_data->clk_rate_change_nb))
1494 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1496 /* Look for a serialN alias */
1497 id = of_alias_get_id(pdev->dev.of_node, "serial");
1501 if (id >= CDNS_UART_NR_PORTS) {
1502 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1504 goto err_out_notif_unreg;
1507 /* At this point, we've got an empty uart_port struct, initialize it */
1508 spin_lock_init(&port->lock);
1509 port->membase = NULL;
1511 port->type = PORT_UNKNOWN;
1512 port->iotype = UPIO_MEM32;
1513 port->flags = UPF_BOOT_AUTOCONF;
1514 port->ops = &cdns_uart_ops;
1515 port->fifosize = CDNS_UART_FIFO_SIZE;
1520 * Register the port.
1521 * This function also registers this device with the tty layer
1522 * and triggers invocation of the config_port() entry point.
1524 port->mapbase = res->start;
1526 port->dev = &pdev->dev;
1527 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1528 port->private_data = cdns_uart_data;
1529 cdns_uart_data->port = port;
1530 platform_set_drvdata(pdev, port);
1532 pm_runtime_use_autosuspend(&pdev->dev);
1533 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1534 pm_runtime_set_active(&pdev->dev);
1535 pm_runtime_enable(&pdev->dev);
1537 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1539 * If console hasn't been found yet try to assign this port
1540 * because it is required to be assigned for console setup function.
1541 * If register_console() don't assign value, then console_port pointer
1544 if (cdns_uart_uart_driver.cons->index == -1)
1545 console_port = port;
1548 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1551 "uart_add_one_port() failed; err=%i\n", rc);
1552 goto err_out_pm_disable;
1555 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1556 /* This is not port which is used for console that's why clean it up */
1557 if (cdns_uart_uart_driver.cons->index == -1)
1558 console_port = NULL;
1564 pm_runtime_disable(&pdev->dev);
1565 pm_runtime_set_suspended(&pdev->dev);
1566 pm_runtime_dont_use_autosuspend(&pdev->dev);
1567 err_out_notif_unreg:
1568 #ifdef CONFIG_COMMON_CLK
1569 clk_notifier_unregister(cdns_uart_data->uartclk,
1570 &cdns_uart_data->clk_rate_change_nb);
1572 err_out_clk_disable:
1573 clk_disable_unprepare(cdns_uart_data->uartclk);
1574 err_out_clk_dis_pclk:
1575 clk_disable_unprepare(cdns_uart_data->pclk);
1581 * cdns_uart_remove - called when the platform driver is unregistered
1582 * @pdev: Pointer to the platform device structure
1584 * Return: 0 on success, negative errno otherwise
1586 static int cdns_uart_remove(struct platform_device *pdev)
1588 struct uart_port *port = platform_get_drvdata(pdev);
1589 struct cdns_uart *cdns_uart_data = port->private_data;
1592 /* Remove the cdns_uart port from the serial core */
1593 #ifdef CONFIG_COMMON_CLK
1594 clk_notifier_unregister(cdns_uart_data->uartclk,
1595 &cdns_uart_data->clk_rate_change_nb);
1597 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1599 clk_disable_unprepare(cdns_uart_data->uartclk);
1600 clk_disable_unprepare(cdns_uart_data->pclk);
1601 pm_runtime_disable(&pdev->dev);
1602 pm_runtime_set_suspended(&pdev->dev);
1603 pm_runtime_dont_use_autosuspend(&pdev->dev);
1607 static struct platform_driver cdns_uart_platform_driver = {
1608 .probe = cdns_uart_probe,
1609 .remove = cdns_uart_remove,
1611 .name = CDNS_UART_NAME,
1612 .of_match_table = cdns_uart_of_match,
1613 .pm = &cdns_uart_dev_pm_ops,
1614 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1618 static int __init cdns_uart_init(void)
1622 /* Register the cdns_uart driver with the serial core */
1623 retval = uart_register_driver(&cdns_uart_uart_driver);
1627 /* Register the platform driver */
1628 retval = platform_driver_register(&cdns_uart_platform_driver);
1630 uart_unregister_driver(&cdns_uart_uart_driver);
1635 static void __exit cdns_uart_exit(void)
1637 /* Unregister the platform driver */
1638 platform_driver_unregister(&cdns_uart_platform_driver);
1640 /* Unregister the cdns_uart driver */
1641 uart_unregister_driver(&cdns_uart_uart_driver);
1644 arch_initcall(cdns_uart_init);
1645 module_exit(cdns_uart_exit);
1647 MODULE_DESCRIPTION("Driver for Cadence UART");
1648 MODULE_AUTHOR("Xilinx Inc.");
1649 MODULE_LICENSE("GPL");