1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * 2011 - 2014 (C) Xilinx Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/platform_device.h>
17 #include <linux/serial.h>
18 #include <linux/console.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/clk.h>
24 #include <linux/irq.h>
27 #include <linux/module.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/iopoll.h>
31 #define CDNS_UART_TTY_NAME "ttyPS"
32 #define CDNS_UART_NAME "xuartps"
33 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
34 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
35 #define CDNS_UART_NR_PORTS 2
36 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
37 #define CDNS_UART_REGISTER_SPACE 0x1000
38 #define TX_TIMEOUT 500000
40 /* Rx Trigger level */
41 static int rx_trigger_level = 56;
42 module_param(rx_trigger_level, uint, S_IRUGO);
43 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46 static int rx_timeout = 10;
47 module_param(rx_timeout, uint, S_IRUGO);
48 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
50 /* Register offsets for the UART. */
51 #define CDNS_UART_CR 0x00 /* Control Register */
52 #define CDNS_UART_MR 0x04 /* Mode Register */
53 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
54 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
55 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
56 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
57 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
58 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
59 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
60 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
61 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
62 #define CDNS_UART_SR 0x2C /* Channel Status */
63 #define CDNS_UART_FIFO 0x30 /* FIFO */
64 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
65 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
66 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
67 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
68 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
69 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
71 /* Control Register Bit Definitions */
72 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
73 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
74 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
75 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
76 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
77 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
78 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
79 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
80 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
81 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
82 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
83 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
87 * The mode register (MR) defines the mode of transfer as well as the data
88 * format. If this register is modified during transmission or reception,
89 * data validity cannot be guaranteed.
91 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
92 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
93 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
94 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
96 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
97 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
99 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
100 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
101 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
102 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
103 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
105 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
106 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
107 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
110 * Interrupt Registers:
111 * Interrupt control logic uses the interrupt enable register (IER) and the
112 * interrupt disable register (IDR) to set the value of the bits in the
113 * interrupt mask register (IMR). The IMR determines whether to pass an
114 * interrupt to the interrupt status register (ISR).
115 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
116 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
117 * Reading either IER or IDR returns 0x00.
118 * All four registers have the same bit definitions.
120 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
121 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
122 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
123 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
124 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
125 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
126 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
127 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
128 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
129 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
130 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
133 * Do not enable parity error interrupt for the following
134 * reason: When parity error interrupt is enabled, each Rx
135 * parity error always results in 2 events. The first one
136 * being parity error interrupt and the second one with a
137 * proper Rx interrupt with the incoming data. Disabling
138 * parity error interrupt ensures better handling of parity
139 * error events. With this change, for a parity error case, we
140 * get a Rx interrupt with parity error set in ISR register
141 * and we still handle parity errors in the desired way.
144 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
145 CDNS_UART_IXR_OVERRUN | \
146 CDNS_UART_IXR_RXTRIG | \
149 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
150 #define CDNS_UART_IXR_BRK 0x00002000
152 #define CDNS_UART_RXBS_SUPPORT BIT(1)
154 * Modem Control register:
155 * The read/write Modem Control register controls the interface with the modem
156 * or data set, or a peripheral device emulating a modem.
158 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
159 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
160 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
163 * Channel Status Register:
164 * The channel status register (CSR) is provided to enable the control logic
165 * to monitor the status of bits in the channel interrupt status register,
166 * even if these are masked out by the interrupt mask register.
168 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
169 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
170 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
171 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
172 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
174 /* baud dividers min/max values */
175 #define CDNS_UART_BDIV_MIN 4
176 #define CDNS_UART_BDIV_MAX 255
177 #define CDNS_UART_CD_MAX 65535
178 #define UART_AUTOSUSPEND_TIMEOUT 3000
181 * struct cdns_uart - device data
182 * @port: Pointer to the UART port
183 * @uartclk: Reference clock
185 * @baud: Current baud rate
186 * @clk_rate_change_nb: Notifier block for clock changes
187 * @quirks: Flags for RXBS support.
190 struct uart_port *port;
194 struct notifier_block clk_rate_change_nb;
197 struct cdns_platform_data {
200 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
204 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
205 * @dev_id: Id of the UART port
206 * @isrstatus: The interrupt status register value as read
209 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
211 struct uart_port *port = (struct uart_port *)dev_id;
212 struct cdns_uart *cdns_uart = port->private_data;
214 unsigned int rxbs_status = 0;
215 unsigned int status_mask;
216 unsigned int framerrprocessed = 0;
217 char status = TTY_NORMAL;
218 bool is_rxbs_support;
220 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
222 while ((readl(port->membase + CDNS_UART_SR) &
223 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
225 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
226 data = readl(port->membase + CDNS_UART_FIFO);
229 * There is no hardware break detection in Zynq, so we interpret
230 * framing error with all-zeros data as a break sequence.
231 * Most of the time, there's another non-zero byte at the
232 * end of the sequence.
234 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
236 port->read_status_mask |= CDNS_UART_IXR_BRK;
237 framerrprocessed = 1;
241 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
244 if (uart_handle_break(port))
248 isrstatus &= port->read_status_mask;
249 isrstatus &= ~port->ignore_status_mask;
250 status_mask = port->read_status_mask;
251 status_mask &= ~port->ignore_status_mask;
254 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
255 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
257 if (uart_handle_break(port))
261 if (uart_handle_sysrq_char(port, data))
264 if (is_rxbs_support) {
265 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
266 && (status_mask & CDNS_UART_IXR_PARITY)) {
267 port->icount.parity++;
270 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
271 && (status_mask & CDNS_UART_IXR_PARITY)) {
272 port->icount.frame++;
276 if (isrstatus & CDNS_UART_IXR_PARITY) {
277 port->icount.parity++;
280 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
282 port->icount.frame++;
286 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
287 port->icount.overrun++;
288 tty_insert_flip_char(&port->state->port, 0,
291 tty_insert_flip_char(&port->state->port, data, status);
294 spin_unlock(&port->lock);
295 tty_flip_buffer_push(&port->state->port);
296 spin_lock(&port->lock);
300 * cdns_uart_handle_tx - Handle the bytes to be Txed.
301 * @dev_id: Id of the UART port
304 static void cdns_uart_handle_tx(void *dev_id)
306 struct uart_port *port = (struct uart_port *)dev_id;
307 unsigned int numbytes;
309 if (uart_circ_empty(&port->state->xmit)) {
310 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
312 numbytes = port->fifosize;
313 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
314 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
316 * Get the data from the UART circular buffer
317 * and write it to the cdns_uart's TX_FIFO
321 port->state->xmit.buf[port->state->xmit.
322 tail], port->membase + CDNS_UART_FIFO);
327 * Adjust the tail of the UART buffer and wrap
328 * the buffer if it reaches limit.
330 port->state->xmit.tail =
331 (port->state->xmit.tail + 1) &
332 (UART_XMIT_SIZE - 1);
337 if (uart_circ_chars_pending(
338 &port->state->xmit) < WAKEUP_CHARS)
339 uart_write_wakeup(port);
344 * cdns_uart_isr - Interrupt handler
346 * @dev_id: Id of the port
350 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
352 struct uart_port *port = (struct uart_port *)dev_id;
353 unsigned int isrstatus;
355 spin_lock(&port->lock);
357 /* Read the interrupt status register to determine which
358 * interrupt(s) is/are active and clear them.
360 isrstatus = readl(port->membase + CDNS_UART_ISR);
361 writel(isrstatus, port->membase + CDNS_UART_ISR);
363 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
364 cdns_uart_handle_tx(dev_id);
365 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
369 * Skip RX processing if RX is disabled as RXEMPTY will never be set
370 * as read bytes will not be removed from the FIFO.
372 if (isrstatus & CDNS_UART_IXR_RXMASK &&
373 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
374 cdns_uart_handle_rx(dev_id, isrstatus);
376 spin_unlock(&port->lock);
381 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
382 * @clk: UART module input clock
383 * @baud: Desired baud rate
384 * @rbdiv: BDIV value (return value)
385 * @rcd: CD value (return value)
386 * @div8: Value for clk_sel bit in mod (return value)
387 * Return: baud rate, requested baud when possible, or actual baud when there
388 * was too much error, zero if no valid divisors are found.
390 * Formula to obtain baud rate is
391 * baud_tx/rx rate = clk/CD * (BDIV + 1)
392 * input_clk = (Uart User Defined Clock or Apb Clock)
393 * depends on UCLKEN in MR Reg
394 * clk = input_clk or input_clk/8;
395 * depends on CLKS in MR reg
396 * CD and BDIV depends on values in
397 * baud rate generate register
398 * baud rate clock divisor register
400 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
401 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
404 unsigned int calc_baud;
405 unsigned int bestbaud = 0;
406 unsigned int bauderror;
407 unsigned int besterror = ~0;
409 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
416 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
417 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
418 if (cd < 1 || cd > CDNS_UART_CD_MAX)
421 calc_baud = clk / (cd * (bdiv + 1));
423 if (baud > calc_baud)
424 bauderror = baud - calc_baud;
426 bauderror = calc_baud - baud;
428 if (besterror > bauderror) {
431 bestbaud = calc_baud;
432 besterror = bauderror;
435 /* use the values when percent error is acceptable */
436 if (((besterror * 100) / baud) < 3)
443 * cdns_uart_set_baud_rate - Calculate and set the baud rate
444 * @port: Handle to the uart port structure
445 * @baud: Baud rate to set
446 * Return: baud rate, requested baud when possible, or actual baud when there
447 * was too much error, zero if no valid divisors are found.
449 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
452 unsigned int calc_baud;
453 u32 cd = 0, bdiv = 0;
456 struct cdns_uart *cdns_uart = port->private_data;
458 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
461 /* Write new divisors to hardware */
462 mreg = readl(port->membase + CDNS_UART_MR);
464 mreg |= CDNS_UART_MR_CLKSEL;
466 mreg &= ~CDNS_UART_MR_CLKSEL;
467 writel(mreg, port->membase + CDNS_UART_MR);
468 writel(cd, port->membase + CDNS_UART_BAUDGEN);
469 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
470 cdns_uart->baud = baud;
475 #ifdef CONFIG_COMMON_CLK
477 * cdns_uart_clk_notitifer_cb - Clock notifier callback
478 * @nb: Notifier block
479 * @event: Notify event
480 * @data: Notifier data
481 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
483 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
484 unsigned long event, void *data)
487 struct uart_port *port;
489 struct clk_notifier_data *ndata = data;
490 unsigned long flags = 0;
491 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
493 port = cdns_uart->port;
498 case PRE_RATE_CHANGE:
504 * Find out if current baud-rate can be achieved with new clock
507 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
508 &bdiv, &cd, &div8)) {
509 dev_warn(port->dev, "clock rate change rejected\n");
513 spin_lock_irqsave(&cdns_uart->port->lock, flags);
515 /* Disable the TX and RX to set baud rate */
516 ctrl_reg = readl(port->membase + CDNS_UART_CR);
517 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
518 writel(ctrl_reg, port->membase + CDNS_UART_CR);
520 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
524 case POST_RATE_CHANGE:
526 * Set clk dividers to generate correct baud with new clock
530 spin_lock_irqsave(&cdns_uart->port->lock, flags);
533 port->uartclk = ndata->new_rate;
535 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
538 case ABORT_RATE_CHANGE:
540 spin_lock_irqsave(&cdns_uart->port->lock, flags);
542 /* Set TX/RX Reset */
543 ctrl_reg = readl(port->membase + CDNS_UART_CR);
544 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
545 writel(ctrl_reg, port->membase + CDNS_UART_CR);
547 while (readl(port->membase + CDNS_UART_CR) &
548 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
552 * Clear the RX disable and TX disable bits and then set the TX
553 * enable bit and RX enable bit to enable the transmitter and
556 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
557 ctrl_reg = readl(port->membase + CDNS_UART_CR);
558 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
559 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
560 writel(ctrl_reg, port->membase + CDNS_UART_CR);
562 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
572 * cdns_uart_start_tx - Start transmitting bytes
573 * @port: Handle to the uart port structure
575 static void cdns_uart_start_tx(struct uart_port *port)
579 if (uart_tx_stopped(port))
583 * Set the TX enable bit and clear the TX disable bit to enable the
586 status = readl(port->membase + CDNS_UART_CR);
587 status &= ~CDNS_UART_CR_TX_DIS;
588 status |= CDNS_UART_CR_TX_EN;
589 writel(status, port->membase + CDNS_UART_CR);
591 if (uart_circ_empty(&port->state->xmit))
594 cdns_uart_handle_tx(port);
596 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
597 /* Enable the TX Empty interrupt */
598 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
602 * cdns_uart_stop_tx - Stop TX
603 * @port: Handle to the uart port structure
605 static void cdns_uart_stop_tx(struct uart_port *port)
609 regval = readl(port->membase + CDNS_UART_CR);
610 regval |= CDNS_UART_CR_TX_DIS;
611 /* Disable the transmitter */
612 writel(regval, port->membase + CDNS_UART_CR);
616 * cdns_uart_stop_rx - Stop RX
617 * @port: Handle to the uart port structure
619 static void cdns_uart_stop_rx(struct uart_port *port)
623 /* Disable RX IRQs */
624 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
626 /* Disable the receiver */
627 regval = readl(port->membase + CDNS_UART_CR);
628 regval |= CDNS_UART_CR_RX_DIS;
629 writel(regval, port->membase + CDNS_UART_CR);
633 * cdns_uart_tx_empty - Check whether TX is empty
634 * @port: Handle to the uart port structure
636 * Return: TIOCSER_TEMT on success, 0 otherwise
638 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
642 status = readl(port->membase + CDNS_UART_SR) &
643 CDNS_UART_SR_TXEMPTY;
644 return status ? TIOCSER_TEMT : 0;
648 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
649 * transmitting char breaks
650 * @port: Handle to the uart port structure
651 * @ctl: Value based on which start or stop decision is taken
653 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
658 spin_lock_irqsave(&port->lock, flags);
660 status = readl(port->membase + CDNS_UART_CR);
663 writel(CDNS_UART_CR_STARTBRK | status,
664 port->membase + CDNS_UART_CR);
666 if ((status & CDNS_UART_CR_STOPBRK) == 0)
667 writel(CDNS_UART_CR_STOPBRK | status,
668 port->membase + CDNS_UART_CR);
670 spin_unlock_irqrestore(&port->lock, flags);
674 * cdns_uart_set_termios - termios operations, handling data length, parity,
675 * stop bits, flow control, baud rate
676 * @port: Handle to the uart port structure
677 * @termios: Handle to the input termios structure
678 * @old: Values of the previously saved termios structure
680 static void cdns_uart_set_termios(struct uart_port *port,
681 struct ktermios *termios, struct ktermios *old)
683 unsigned int cval = 0;
684 unsigned int baud, minbaud, maxbaud;
686 unsigned int ctrl_reg, mode_reg, val;
689 /* Wait for the transmit FIFO to empty before making changes */
690 if (!(readl(port->membase + CDNS_UART_CR) &
691 CDNS_UART_CR_TX_DIS)) {
692 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
693 val, (val & CDNS_UART_SR_TXEMPTY),
696 dev_err(port->dev, "timed out waiting for tx empty");
700 spin_lock_irqsave(&port->lock, flags);
702 /* Disable the TX and RX to set baud rate */
703 ctrl_reg = readl(port->membase + CDNS_UART_CR);
704 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
705 writel(ctrl_reg, port->membase + CDNS_UART_CR);
708 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
709 * min and max baud should be calculated here based on port->uartclk.
710 * this way we get a valid baud and can safely call set_baud()
712 minbaud = port->uartclk /
713 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
714 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
715 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
716 baud = cdns_uart_set_baud_rate(port, baud);
717 if (tty_termios_baud_rate(termios))
718 tty_termios_encode_baud_rate(termios, baud, baud);
720 /* Update the per-port timeout. */
721 uart_update_timeout(port, termios->c_cflag, baud);
723 /* Set TX/RX Reset */
724 ctrl_reg = readl(port->membase + CDNS_UART_CR);
725 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
726 writel(ctrl_reg, port->membase + CDNS_UART_CR);
728 while (readl(port->membase + CDNS_UART_CR) &
729 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
733 * Clear the RX disable and TX disable bits and then set the TX enable
734 * bit and RX enable bit to enable the transmitter and receiver.
736 ctrl_reg = readl(port->membase + CDNS_UART_CR);
737 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
738 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
739 writel(ctrl_reg, port->membase + CDNS_UART_CR);
741 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
743 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
744 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
745 port->ignore_status_mask = 0;
747 if (termios->c_iflag & INPCK)
748 port->read_status_mask |= CDNS_UART_IXR_PARITY |
749 CDNS_UART_IXR_FRAMING;
751 if (termios->c_iflag & IGNPAR)
752 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
753 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
755 /* ignore all characters if CREAD is not set */
756 if ((termios->c_cflag & CREAD) == 0)
757 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
758 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
759 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
761 mode_reg = readl(port->membase + CDNS_UART_MR);
763 /* Handling Data Size */
764 switch (termios->c_cflag & CSIZE) {
766 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
769 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
773 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
774 termios->c_cflag &= ~CSIZE;
775 termios->c_cflag |= CS8;
779 /* Handling Parity and Stop Bits length */
780 if (termios->c_cflag & CSTOPB)
781 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
783 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
785 if (termios->c_cflag & PARENB) {
786 /* Mark or Space parity */
787 if (termios->c_cflag & CMSPAR) {
788 if (termios->c_cflag & PARODD)
789 cval |= CDNS_UART_MR_PARITY_MARK;
791 cval |= CDNS_UART_MR_PARITY_SPACE;
793 if (termios->c_cflag & PARODD)
794 cval |= CDNS_UART_MR_PARITY_ODD;
796 cval |= CDNS_UART_MR_PARITY_EVEN;
799 cval |= CDNS_UART_MR_PARITY_NONE;
801 cval |= mode_reg & 1;
802 writel(cval, port->membase + CDNS_UART_MR);
804 spin_unlock_irqrestore(&port->lock, flags);
808 * cdns_uart_startup - Called when an application opens a cdns_uart port
809 * @port: Handle to the uart port structure
811 * Return: 0 on success, negative errno otherwise
813 static int cdns_uart_startup(struct uart_port *port)
815 struct cdns_uart *cdns_uart = port->private_data;
819 unsigned int status = 0;
821 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
823 spin_lock_irqsave(&port->lock, flags);
825 /* Disable the TX and RX */
826 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
827 port->membase + CDNS_UART_CR);
829 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
832 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
833 port->membase + CDNS_UART_CR);
835 while (readl(port->membase + CDNS_UART_CR) &
836 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
840 * Clear the RX disable bit and then set the RX enable bit to enable
843 status = readl(port->membase + CDNS_UART_CR);
844 status &= ~CDNS_UART_CR_RX_DIS;
845 status |= CDNS_UART_CR_RX_EN;
846 writel(status, port->membase + CDNS_UART_CR);
848 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
851 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
852 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
853 port->membase + CDNS_UART_MR);
856 * Set the RX FIFO Trigger level to use most of the FIFO, but it
857 * can be tuned with a module parameter
859 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
862 * Receive Timeout register is enabled but it
863 * can be tuned with a module parameter
865 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
867 /* Clear out any pending interrupts before enabling them */
868 writel(readl(port->membase + CDNS_UART_ISR),
869 port->membase + CDNS_UART_ISR);
871 spin_unlock_irqrestore(&port->lock, flags);
873 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
875 dev_err(port->dev, "request_irq '%d' failed with %d\n",
880 /* Set the Interrupt Registers with desired interrupts */
882 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
883 port->membase + CDNS_UART_IER);
885 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
891 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
892 * @port: Handle to the uart port structure
894 static void cdns_uart_shutdown(struct uart_port *port)
899 spin_lock_irqsave(&port->lock, flags);
901 /* Disable interrupts */
902 status = readl(port->membase + CDNS_UART_IMR);
903 writel(status, port->membase + CDNS_UART_IDR);
904 writel(0xffffffff, port->membase + CDNS_UART_ISR);
906 /* Disable the TX and RX */
907 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
908 port->membase + CDNS_UART_CR);
910 spin_unlock_irqrestore(&port->lock, flags);
912 free_irq(port->irq, port);
916 * cdns_uart_type - Set UART type to cdns_uart port
917 * @port: Handle to the uart port structure
919 * Return: string on success, NULL otherwise
921 static const char *cdns_uart_type(struct uart_port *port)
923 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
927 * cdns_uart_verify_port - Verify the port params
928 * @port: Handle to the uart port structure
929 * @ser: Handle to the structure whose members are compared
931 * Return: 0 on success, negative errno otherwise.
933 static int cdns_uart_verify_port(struct uart_port *port,
934 struct serial_struct *ser)
936 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
938 if (port->irq != ser->irq)
940 if (ser->io_type != UPIO_MEM)
942 if (port->iobase != ser->port)
950 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
951 * called when the driver adds a cdns_uart port via
952 * uart_add_one_port()
953 * @port: Handle to the uart port structure
955 * Return: 0 on success, negative errno otherwise.
957 static int cdns_uart_request_port(struct uart_port *port)
959 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
964 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
965 if (!port->membase) {
966 dev_err(port->dev, "Unable to map registers\n");
967 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
974 * cdns_uart_release_port - Release UART port
975 * @port: Handle to the uart port structure
977 * Release the memory region attached to a cdns_uart port. Called when the
978 * driver removes a cdns_uart port via uart_remove_one_port().
980 static void cdns_uart_release_port(struct uart_port *port)
982 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
983 iounmap(port->membase);
984 port->membase = NULL;
988 * cdns_uart_config_port - Configure UART port
989 * @port: Handle to the uart port structure
992 static void cdns_uart_config_port(struct uart_port *port, int flags)
994 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
995 port->type = PORT_XUARTPS;
999 * cdns_uart_get_mctrl - Get the modem control state
1000 * @port: Handle to the uart port structure
1002 * Return: the modem control state
1004 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1006 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1009 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1014 val = readl(port->membase + CDNS_UART_MODEMCR);
1015 mode_reg = readl(port->membase + CDNS_UART_MR);
1017 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1018 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1020 if (mctrl & TIOCM_RTS)
1021 val |= CDNS_UART_MODEMCR_RTS;
1022 if (mctrl & TIOCM_DTR)
1023 val |= CDNS_UART_MODEMCR_DTR;
1024 if (mctrl & TIOCM_LOOP)
1025 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1027 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1029 writel(val, port->membase + CDNS_UART_MODEMCR);
1030 writel(mode_reg, port->membase + CDNS_UART_MR);
1033 #ifdef CONFIG_CONSOLE_POLL
1034 static int cdns_uart_poll_get_char(struct uart_port *port)
1037 unsigned long flags;
1039 spin_lock_irqsave(&port->lock, flags);
1041 /* Check if FIFO is empty */
1042 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1044 else /* Read a character */
1045 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1047 spin_unlock_irqrestore(&port->lock, flags);
1052 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1054 unsigned long flags;
1056 spin_lock_irqsave(&port->lock, flags);
1058 /* Wait until FIFO is empty */
1059 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1062 /* Write a character */
1063 writel(c, port->membase + CDNS_UART_FIFO);
1065 /* Wait until FIFO is empty */
1066 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1069 spin_unlock_irqrestore(&port->lock, flags);
1075 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1076 unsigned int oldstate)
1079 case UART_PM_STATE_OFF:
1080 pm_runtime_mark_last_busy(port->dev);
1081 pm_runtime_put_autosuspend(port->dev);
1084 pm_runtime_get_sync(port->dev);
1089 static const struct uart_ops cdns_uart_ops = {
1090 .set_mctrl = cdns_uart_set_mctrl,
1091 .get_mctrl = cdns_uart_get_mctrl,
1092 .start_tx = cdns_uart_start_tx,
1093 .stop_tx = cdns_uart_stop_tx,
1094 .stop_rx = cdns_uart_stop_rx,
1095 .tx_empty = cdns_uart_tx_empty,
1096 .break_ctl = cdns_uart_break_ctl,
1097 .set_termios = cdns_uart_set_termios,
1098 .startup = cdns_uart_startup,
1099 .shutdown = cdns_uart_shutdown,
1101 .type = cdns_uart_type,
1102 .verify_port = cdns_uart_verify_port,
1103 .request_port = cdns_uart_request_port,
1104 .release_port = cdns_uart_release_port,
1105 .config_port = cdns_uart_config_port,
1106 #ifdef CONFIG_CONSOLE_POLL
1107 .poll_get_char = cdns_uart_poll_get_char,
1108 .poll_put_char = cdns_uart_poll_put_char,
1112 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1114 * cdns_uart_console_putchar - write the character to the FIFO buffer
1115 * @port: Handle to the uart port structure
1116 * @ch: Character to be written
1118 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1120 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1122 writel(ch, port->membase + CDNS_UART_FIFO);
1125 static void cdns_early_write(struct console *con, const char *s,
1128 struct earlycon_device *dev = con->data;
1130 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1133 static int __init cdns_early_console_setup(struct earlycon_device *device,
1136 struct uart_port *port = &device->port;
1141 /* initialise control register */
1142 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1143 port->membase + CDNS_UART_CR);
1145 /* only set baud if specified on command line - otherwise
1146 * assume it has been initialized by a boot loader.
1148 if (port->uartclk && device->baud) {
1149 u32 cd = 0, bdiv = 0;
1153 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1155 mr = CDNS_UART_MR_PARITY_NONE;
1157 mr |= CDNS_UART_MR_CLKSEL;
1159 writel(mr, port->membase + CDNS_UART_MR);
1160 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1161 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1164 device->con->write = cdns_early_write;
1168 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1169 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1170 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1171 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1174 /* Static pointer to console port */
1175 static struct uart_port *console_port;
1178 * cdns_uart_console_write - perform write operation
1179 * @co: Console handle
1180 * @s: Pointer to character array
1181 * @count: No of characters
1183 static void cdns_uart_console_write(struct console *co, const char *s,
1186 struct uart_port *port = console_port;
1187 unsigned long flags;
1188 unsigned int imr, ctrl;
1193 else if (oops_in_progress)
1194 locked = spin_trylock_irqsave(&port->lock, flags);
1196 spin_lock_irqsave(&port->lock, flags);
1198 /* save and disable interrupt */
1199 imr = readl(port->membase + CDNS_UART_IMR);
1200 writel(imr, port->membase + CDNS_UART_IDR);
1203 * Make sure that the tx part is enabled. Set the TX enable bit and
1204 * clear the TX disable bit to enable the transmitter.
1206 ctrl = readl(port->membase + CDNS_UART_CR);
1207 ctrl &= ~CDNS_UART_CR_TX_DIS;
1208 ctrl |= CDNS_UART_CR_TX_EN;
1209 writel(ctrl, port->membase + CDNS_UART_CR);
1211 uart_console_write(port, s, count, cdns_uart_console_putchar);
1212 while ((readl(port->membase + CDNS_UART_SR) &
1213 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1214 CDNS_UART_SR_TXEMPTY)
1217 /* restore interrupt state */
1218 writel(imr, port->membase + CDNS_UART_IER);
1221 spin_unlock_irqrestore(&port->lock, flags);
1225 * cdns_uart_console_setup - Initialize the uart to default config
1226 * @co: Console handle
1227 * @options: Initial settings of uart
1229 * Return: 0 on success, negative errno otherwise.
1231 static int cdns_uart_console_setup(struct console *co, char *options)
1233 struct uart_port *port = console_port;
1239 unsigned long time_out;
1241 if (!port->membase) {
1242 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1248 uart_parse_options(options, &baud, &parity, &bits, &flow);
1250 /* Wait for tx_empty before setting up the console */
1251 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1253 while (time_before(jiffies, time_out) &&
1254 cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1257 return uart_set_options(port, co, baud, parity, bits, flow);
1260 static struct uart_driver cdns_uart_uart_driver;
1262 static struct console cdns_uart_console = {
1263 .name = CDNS_UART_TTY_NAME,
1264 .write = cdns_uart_console_write,
1265 .device = uart_console_device,
1266 .setup = cdns_uart_console_setup,
1267 .flags = CON_PRINTBUFFER,
1268 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1269 .data = &cdns_uart_uart_driver,
1271 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1273 static struct uart_driver cdns_uart_uart_driver = {
1274 .owner = THIS_MODULE,
1275 .driver_name = CDNS_UART_NAME,
1276 .dev_name = CDNS_UART_TTY_NAME,
1277 .major = CDNS_UART_MAJOR,
1278 .minor = CDNS_UART_MINOR,
1279 .nr = CDNS_UART_NR_PORTS,
1280 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1281 .cons = &cdns_uart_console,
1285 #ifdef CONFIG_PM_SLEEP
1287 * cdns_uart_suspend - suspend event
1288 * @device: Pointer to the device structure
1292 static int cdns_uart_suspend(struct device *device)
1294 struct uart_port *port = dev_get_drvdata(device);
1297 may_wake = device_may_wakeup(device);
1299 if (console_suspend_enabled && may_wake) {
1300 unsigned long flags = 0;
1302 spin_lock_irqsave(&port->lock, flags);
1303 /* Empty the receive FIFO 1st before making changes */
1304 while (!(readl(port->membase + CDNS_UART_SR) &
1305 CDNS_UART_SR_RXEMPTY))
1306 readl(port->membase + CDNS_UART_FIFO);
1307 /* set RX trigger level to 1 */
1308 writel(1, port->membase + CDNS_UART_RXWM);
1309 /* disable RX timeout interrups */
1310 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1311 spin_unlock_irqrestore(&port->lock, flags);
1315 * Call the API provided in serial_core.c file which handles
1318 return uart_suspend_port(&cdns_uart_uart_driver, port);
1322 * cdns_uart_resume - Resume after a previous suspend
1323 * @device: Pointer to the device structure
1327 static int cdns_uart_resume(struct device *device)
1329 struct uart_port *port = dev_get_drvdata(device);
1330 unsigned long flags = 0;
1334 may_wake = device_may_wakeup(device);
1336 if (console_suspend_enabled && !may_wake) {
1337 struct cdns_uart *cdns_uart = port->private_data;
1339 clk_enable(cdns_uart->pclk);
1340 clk_enable(cdns_uart->uartclk);
1342 spin_lock_irqsave(&port->lock, flags);
1344 /* Set TX/RX Reset */
1345 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1346 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1347 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1348 while (readl(port->membase + CDNS_UART_CR) &
1349 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1352 /* restore rx timeout value */
1353 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1355 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1356 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1357 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1358 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1360 clk_disable(cdns_uart->uartclk);
1361 clk_disable(cdns_uart->pclk);
1362 spin_unlock_irqrestore(&port->lock, flags);
1364 spin_lock_irqsave(&port->lock, flags);
1365 /* restore original rx trigger level */
1366 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1367 /* enable RX timeout interrupt */
1368 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1369 spin_unlock_irqrestore(&port->lock, flags);
1372 return uart_resume_port(&cdns_uart_uart_driver, port);
1374 #endif /* ! CONFIG_PM_SLEEP */
1375 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1377 struct uart_port *port = dev_get_drvdata(dev);
1378 struct cdns_uart *cdns_uart = port->private_data;
1380 clk_disable(cdns_uart->uartclk);
1381 clk_disable(cdns_uart->pclk);
1385 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1387 struct uart_port *port = dev_get_drvdata(dev);
1388 struct cdns_uart *cdns_uart = port->private_data;
1390 clk_enable(cdns_uart->pclk);
1391 clk_enable(cdns_uart->uartclk);
1395 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1396 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1397 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1398 cdns_runtime_resume, NULL)
1401 static const struct cdns_platform_data zynqmp_uart_def = {
1402 .quirks = CDNS_UART_RXBS_SUPPORT, };
1404 /* Match table for of_platform binding */
1405 static const struct of_device_id cdns_uart_of_match[] = {
1406 { .compatible = "xlnx,xuartps", },
1407 { .compatible = "cdns,uart-r1p8", },
1408 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1409 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1412 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1415 * cdns_uart_probe - Platform driver probe
1416 * @pdev: Pointer to the platform device structure
1418 * Return: 0 on success, negative errno otherwise
1420 static int cdns_uart_probe(struct platform_device *pdev)
1423 struct uart_port *port;
1424 struct resource *res;
1425 struct cdns_uart *cdns_uart_data;
1426 const struct of_device_id *match;
1428 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1430 if (!cdns_uart_data)
1432 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1436 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1437 if (match && match->data) {
1438 const struct cdns_platform_data *data = match->data;
1440 cdns_uart_data->quirks = data->quirks;
1443 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1444 if (IS_ERR(cdns_uart_data->pclk)) {
1445 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1446 if (!IS_ERR(cdns_uart_data->pclk))
1447 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1449 if (IS_ERR(cdns_uart_data->pclk)) {
1450 dev_err(&pdev->dev, "pclk clock not found.\n");
1451 return PTR_ERR(cdns_uart_data->pclk);
1454 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1455 if (IS_ERR(cdns_uart_data->uartclk)) {
1456 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1457 if (!IS_ERR(cdns_uart_data->uartclk))
1458 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1460 if (IS_ERR(cdns_uart_data->uartclk)) {
1461 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1462 return PTR_ERR(cdns_uart_data->uartclk);
1465 rc = clk_prepare_enable(cdns_uart_data->pclk);
1467 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1470 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1472 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1473 goto err_out_clk_dis_pclk;
1476 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1479 goto err_out_clk_disable;
1482 irq = platform_get_irq(pdev, 0);
1485 goto err_out_clk_disable;
1488 #ifdef CONFIG_COMMON_CLK
1489 cdns_uart_data->clk_rate_change_nb.notifier_call =
1490 cdns_uart_clk_notifier_cb;
1491 if (clk_notifier_register(cdns_uart_data->uartclk,
1492 &cdns_uart_data->clk_rate_change_nb))
1493 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1495 /* Look for a serialN alias */
1496 id = of_alias_get_id(pdev->dev.of_node, "serial");
1500 if (id >= CDNS_UART_NR_PORTS) {
1501 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1503 goto err_out_notif_unreg;
1506 /* At this point, we've got an empty uart_port struct, initialize it */
1507 spin_lock_init(&port->lock);
1508 port->membase = NULL;
1510 port->type = PORT_UNKNOWN;
1511 port->iotype = UPIO_MEM32;
1512 port->flags = UPF_BOOT_AUTOCONF;
1513 port->ops = &cdns_uart_ops;
1514 port->fifosize = CDNS_UART_FIFO_SIZE;
1519 * Register the port.
1520 * This function also registers this device with the tty layer
1521 * and triggers invocation of the config_port() entry point.
1523 port->mapbase = res->start;
1525 port->dev = &pdev->dev;
1526 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1527 port->private_data = cdns_uart_data;
1528 cdns_uart_data->port = port;
1529 platform_set_drvdata(pdev, port);
1531 pm_runtime_use_autosuspend(&pdev->dev);
1532 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1533 pm_runtime_set_active(&pdev->dev);
1534 pm_runtime_enable(&pdev->dev);
1536 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1538 * If console hasn't been found yet try to assign this port
1539 * because it is required to be assigned for console setup function.
1540 * If register_console() don't assign value, then console_port pointer
1543 if (cdns_uart_uart_driver.cons->index == -1)
1544 console_port = port;
1547 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1550 "uart_add_one_port() failed; err=%i\n", rc);
1551 goto err_out_pm_disable;
1554 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1555 /* This is not port which is used for console that's why clean it up */
1556 if (cdns_uart_uart_driver.cons->index == -1)
1557 console_port = NULL;
1563 pm_runtime_disable(&pdev->dev);
1564 pm_runtime_set_suspended(&pdev->dev);
1565 pm_runtime_dont_use_autosuspend(&pdev->dev);
1566 err_out_notif_unreg:
1567 #ifdef CONFIG_COMMON_CLK
1568 clk_notifier_unregister(cdns_uart_data->uartclk,
1569 &cdns_uart_data->clk_rate_change_nb);
1571 err_out_clk_disable:
1572 clk_disable_unprepare(cdns_uart_data->uartclk);
1573 err_out_clk_dis_pclk:
1574 clk_disable_unprepare(cdns_uart_data->pclk);
1580 * cdns_uart_remove - called when the platform driver is unregistered
1581 * @pdev: Pointer to the platform device structure
1583 * Return: 0 on success, negative errno otherwise
1585 static int cdns_uart_remove(struct platform_device *pdev)
1587 struct uart_port *port = platform_get_drvdata(pdev);
1588 struct cdns_uart *cdns_uart_data = port->private_data;
1591 /* Remove the cdns_uart port from the serial core */
1592 #ifdef CONFIG_COMMON_CLK
1593 clk_notifier_unregister(cdns_uart_data->uartclk,
1594 &cdns_uart_data->clk_rate_change_nb);
1596 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1598 clk_disable_unprepare(cdns_uart_data->uartclk);
1599 clk_disable_unprepare(cdns_uart_data->pclk);
1600 pm_runtime_disable(&pdev->dev);
1601 pm_runtime_set_suspended(&pdev->dev);
1602 pm_runtime_dont_use_autosuspend(&pdev->dev);
1606 static struct platform_driver cdns_uart_platform_driver = {
1607 .probe = cdns_uart_probe,
1608 .remove = cdns_uart_remove,
1610 .name = CDNS_UART_NAME,
1611 .of_match_table = cdns_uart_of_match,
1612 .pm = &cdns_uart_dev_pm_ops,
1613 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1617 static int __init cdns_uart_init(void)
1621 /* Register the cdns_uart driver with the serial core */
1622 retval = uart_register_driver(&cdns_uart_uart_driver);
1626 /* Register the platform driver */
1627 retval = platform_driver_register(&cdns_uart_platform_driver);
1629 uart_unregister_driver(&cdns_uart_uart_driver);
1634 static void __exit cdns_uart_exit(void)
1636 /* Unregister the platform driver */
1637 platform_driver_unregister(&cdns_uart_platform_driver);
1639 /* Unregister the cdns_uart driver */
1640 uart_unregister_driver(&cdns_uart_uart_driver);
1643 arch_initcall(cdns_uart_init);
1644 module_exit(cdns_uart_exit);
1646 MODULE_DESCRIPTION("Driver for Cadence UART");
1647 MODULE_AUTHOR("Xilinx Inc.");
1648 MODULE_LICENSE("GPL");