1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
5 * Based on msm_serial.c, which is:
6 * Copyright (C) 2007 Google, Inc.
7 * Author: Robert Love <rlove@google.com>
10 #include <linux/hrtimer.h>
11 #include <linux/delay.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/init.h>
16 #include <linux/console.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/slab.h>
22 #include <linux/clk.h>
24 #include <linux/of_device.h>
25 #include <linux/err.h>
28 * UART Register offsets
31 #define VT8500_URTDR 0x0000 /* Transmit data */
32 #define VT8500_URRDR 0x0004 /* Receive data */
33 #define VT8500_URDIV 0x0008 /* Clock/Baud rate divisor */
34 #define VT8500_URLCR 0x000C /* Line control */
35 #define VT8500_URICR 0x0010 /* IrDA control */
36 #define VT8500_URIER 0x0014 /* Interrupt enable */
37 #define VT8500_URISR 0x0018 /* Interrupt status */
38 #define VT8500_URUSR 0x001c /* UART status */
39 #define VT8500_URFCR 0x0020 /* FIFO control */
40 #define VT8500_URFIDX 0x0024 /* FIFO index */
41 #define VT8500_URBKR 0x0028 /* Break signal count */
42 #define VT8500_URTOD 0x002c /* Time out divisor */
43 #define VT8500_TXFIFO 0x1000 /* Transmit FIFO (16x8) */
44 #define VT8500_RXFIFO 0x1020 /* Receive FIFO (16x10) */
47 * Interrupt enable and status bits
50 #define TXDE (1 << 0) /* Tx Data empty */
51 #define RXDF (1 << 1) /* Rx Data full */
52 #define TXFAE (1 << 2) /* Tx FIFO almost empty */
53 #define TXFE (1 << 3) /* Tx FIFO empty */
54 #define RXFAF (1 << 4) /* Rx FIFO almost full */
55 #define RXFF (1 << 5) /* Rx FIFO full */
56 #define TXUDR (1 << 6) /* Tx underrun */
57 #define RXOVER (1 << 7) /* Rx overrun */
58 #define PER (1 << 8) /* Parity error */
59 #define FER (1 << 9) /* Frame error */
60 #define TCTS (1 << 10) /* Toggle of CTS */
61 #define RXTOUT (1 << 11) /* Rx timeout */
62 #define BKDONE (1 << 12) /* Break signal done */
63 #define ERR (1 << 13) /* AHB error response */
65 #define RX_FIFO_INTS (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
66 #define TX_FIFO_INTS (TXFAE | TXFE | TXUDR)
72 #define VT8500_TXEN (1 << 0) /* Enable transmit logic */
73 #define VT8500_RXEN (1 << 1) /* Enable receive logic */
74 #define VT8500_CS8 (1 << 2) /* 8-bit data length (vs. 7-bit) */
75 #define VT8500_CSTOPB (1 << 3) /* 2 stop bits (vs. 1) */
76 #define VT8500_PARENB (1 << 4) /* Enable parity */
77 #define VT8500_PARODD (1 << 5) /* Odd parity (vs. even) */
78 #define VT8500_RTS (1 << 6) /* Ready to send */
79 #define VT8500_LOOPBK (1 << 7) /* Enable internal loopback */
80 #define VT8500_DMA (1 << 8) /* Enable DMA mode (needs FIFO) */
81 #define VT8500_BREAK (1 << 9) /* Initiate break signal */
82 #define VT8500_PSLVERR (1 << 10) /* APB error upon empty RX FIFO read */
83 #define VT8500_SWRTSCTS (1 << 11) /* Software-controlled RTS/CTS */
86 * Capability flags (driver-internal)
89 #define VT8500_HAS_SWRTSCTS_SWITCH (1 << 1)
91 #define VT8500_RECOMMENDED_CLK 12000000
92 #define VT8500_OVERSAMPLING_DIVISOR 13
93 #define VT8500_MAX_PORTS 6
96 struct uart_port uart;
99 unsigned int clk_predivisor;
101 unsigned int vt8500_uart_flags;
105 * we use this variable to keep track of which ports
106 * have been allocated as we can't use pdev->id in
109 static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
111 static inline void vt8500_write(struct uart_port *port, unsigned int val,
114 writel(val, port->membase + off);
117 static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
119 return readl(port->membase + off);
122 static void vt8500_stop_tx(struct uart_port *port)
124 struct vt8500_port *vt8500_port = container_of(port,
128 vt8500_port->ier &= ~TX_FIFO_INTS;
129 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
132 static void vt8500_stop_rx(struct uart_port *port)
134 struct vt8500_port *vt8500_port = container_of(port,
138 vt8500_port->ier &= ~RX_FIFO_INTS;
139 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
142 static void vt8500_enable_ms(struct uart_port *port)
144 struct vt8500_port *vt8500_port = container_of(port,
148 vt8500_port->ier |= TCTS;
149 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
152 static void handle_rx(struct uart_port *port)
154 struct tty_port *tport = &port->state->port;
159 if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
160 port->icount.overrun++;
161 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
164 /* and now the main RX loop */
165 while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
167 char flag = TTY_NORMAL;
169 c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
171 /* Mask conditions we're ignorning. */
172 c &= ~port->read_status_mask;
175 port->icount.frame++;
177 } else if (c & PER) {
178 port->icount.parity++;
183 if (!uart_handle_sysrq_char(port, c))
184 tty_insert_flip_char(tport, c, flag);
187 tty_flip_buffer_push(tport);
190 static void handle_tx(struct uart_port *port)
192 struct circ_buf *xmit = &port->state->xmit;
195 writeb(port->x_char, port->membase + VT8500_TXFIFO);
199 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
200 vt8500_stop_tx(port);
204 while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
205 if (uart_circ_empty(xmit))
208 writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
210 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
214 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
215 uart_write_wakeup(port);
217 if (uart_circ_empty(xmit))
218 vt8500_stop_tx(port);
221 static void vt8500_start_tx(struct uart_port *port)
223 struct vt8500_port *vt8500_port = container_of(port,
227 vt8500_port->ier &= ~TX_FIFO_INTS;
228 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
230 vt8500_port->ier |= TX_FIFO_INTS;
231 vt8500_write(port, vt8500_port->ier, VT8500_URIER);
234 static void handle_delta_cts(struct uart_port *port)
237 wake_up_interruptible(&port->state->port.delta_msr_wait);
240 static irqreturn_t vt8500_irq(int irq, void *dev_id)
242 struct uart_port *port = dev_id;
245 spin_lock(&port->lock);
246 isr = vt8500_read(port, VT8500_URISR);
248 /* Acknowledge active status bits */
249 vt8500_write(port, isr, VT8500_URISR);
251 if (isr & RX_FIFO_INTS)
253 if (isr & TX_FIFO_INTS)
256 handle_delta_cts(port);
258 spin_unlock(&port->lock);
263 static unsigned int vt8500_tx_empty(struct uart_port *port)
265 return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
269 static unsigned int vt8500_get_mctrl(struct uart_port *port)
273 usr = vt8500_read(port, VT8500_URUSR);
280 static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
282 unsigned int lcr = vt8500_read(port, VT8500_URLCR);
284 if (mctrl & TIOCM_RTS)
289 vt8500_write(port, lcr, VT8500_URLCR);
292 static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
296 vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
300 static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
302 struct vt8500_port *vt8500_port =
303 container_of(port, struct vt8500_port, uart);
305 unsigned int loops = 1000;
307 div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
308 div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
310 /* Effective baud rate */
311 baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
313 while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
316 vt8500_write(port, div, VT8500_URDIV);
318 /* Break signal timing depends on baud rate, update accordingly */
319 vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
324 static int vt8500_startup(struct uart_port *port)
326 struct vt8500_port *vt8500_port =
327 container_of(port, struct vt8500_port, uart);
330 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
331 "vt8500_serial%d", port->line);
333 ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
334 vt8500_port->name, port);
338 vt8500_write(port, 0x03, VT8500_URLCR); /* enable TX & RX */
343 static void vt8500_shutdown(struct uart_port *port)
345 struct vt8500_port *vt8500_port =
346 container_of(port, struct vt8500_port, uart);
348 vt8500_port->ier = 0;
350 /* disable interrupts and FIFOs */
351 vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
352 vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
353 free_irq(port->irq, port);
356 static void vt8500_set_termios(struct uart_port *port,
357 struct ktermios *termios,
358 struct ktermios *old)
360 struct vt8500_port *vt8500_port =
361 container_of(port, struct vt8500_port, uart);
363 unsigned int baud, lcr;
364 unsigned int loops = 1000;
366 spin_lock_irqsave(&port->lock, flags);
368 /* calculate and set baud rate */
369 baud = uart_get_baud_rate(port, termios, old, 900, 921600);
370 baud = vt8500_set_baud_rate(port, baud);
371 if (tty_termios_baud_rate(termios))
372 tty_termios_encode_baud_rate(termios, baud, baud);
374 /* calculate parity */
375 lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
376 lcr &= ~(VT8500_PARENB | VT8500_PARODD);
377 if (termios->c_cflag & PARENB) {
378 lcr |= VT8500_PARENB;
379 termios->c_cflag &= ~CMSPAR;
380 if (termios->c_cflag & PARODD)
381 lcr |= VT8500_PARODD;
384 /* calculate bits per char */
386 switch (termios->c_cflag & CSIZE) {
392 termios->c_cflag &= ~CSIZE;
393 termios->c_cflag |= CS8;
397 /* calculate stop bits */
398 lcr &= ~VT8500_CSTOPB;
399 if (termios->c_cflag & CSTOPB)
400 lcr |= VT8500_CSTOPB;
402 lcr &= ~VT8500_SWRTSCTS;
403 if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
404 lcr |= VT8500_SWRTSCTS;
406 /* set parity, bits per char, and stop bit */
407 vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
409 /* Configure status bits to ignore based on termio flags. */
410 port->read_status_mask = 0;
411 if (termios->c_iflag & IGNPAR)
412 port->read_status_mask = FER | PER;
414 uart_update_timeout(port, termios->c_cflag, baud);
417 vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
418 while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
422 /* Every possible FIFO-related interrupt */
423 vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
428 if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
429 vt8500_port->ier |= TCTS;
431 vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
432 vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
434 spin_unlock_irqrestore(&port->lock, flags);
437 static const char *vt8500_type(struct uart_port *port)
439 struct vt8500_port *vt8500_port =
440 container_of(port, struct vt8500_port, uart);
441 return vt8500_port->name;
444 static void vt8500_release_port(struct uart_port *port)
448 static int vt8500_request_port(struct uart_port *port)
453 static void vt8500_config_port(struct uart_port *port, int flags)
455 port->type = PORT_VT8500;
458 static int vt8500_verify_port(struct uart_port *port,
459 struct serial_struct *ser)
461 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
463 if (unlikely(port->irq != ser->irq))
468 static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
469 static struct uart_driver vt8500_uart_driver;
471 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
473 static void wait_for_xmitr(struct uart_port *port)
475 unsigned int status, tmout = 10000;
477 /* Wait up to 10ms for the character(s) to be sent. */
479 status = vt8500_read(port, VT8500_URFIDX);
484 } while (status & 0x10);
487 static void vt8500_console_putchar(struct uart_port *port, unsigned char c)
489 wait_for_xmitr(port);
490 writeb(c, port->membase + VT8500_TXFIFO);
493 static void vt8500_console_write(struct console *co, const char *s,
496 struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
499 BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
501 ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
502 vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
504 uart_console_write(&vt8500_port->uart, s, count,
505 vt8500_console_putchar);
508 * Finally, wait for transmitter to become empty
509 * and switch back to FIFO
511 wait_for_xmitr(&vt8500_port->uart);
512 vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
515 static int __init vt8500_console_setup(struct console *co, char *options)
517 struct vt8500_port *vt8500_port;
523 if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
526 vt8500_port = vt8500_uart_ports[co->index];
532 uart_parse_options(options, &baud, &parity, &bits, &flow);
534 return uart_set_options(&vt8500_port->uart,
535 co, baud, parity, bits, flow);
538 static struct console vt8500_console = {
540 .write = vt8500_console_write,
541 .device = uart_console_device,
542 .setup = vt8500_console_setup,
543 .flags = CON_PRINTBUFFER,
545 .data = &vt8500_uart_driver,
548 #define VT8500_CONSOLE (&vt8500_console)
551 #define VT8500_CONSOLE NULL
554 #ifdef CONFIG_CONSOLE_POLL
555 static int vt8500_get_poll_char(struct uart_port *port)
557 unsigned int status = vt8500_read(port, VT8500_URFIDX);
559 if (!(status & 0x1f00))
562 return vt8500_read(port, VT8500_RXFIFO) & 0xff;
565 static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
567 unsigned int status, tmout = 10000;
570 status = vt8500_read(port, VT8500_URFIDX);
575 } while (status & 0x10);
577 vt8500_write(port, c, VT8500_TXFIFO);
581 static const struct uart_ops vt8500_uart_pops = {
582 .tx_empty = vt8500_tx_empty,
583 .set_mctrl = vt8500_set_mctrl,
584 .get_mctrl = vt8500_get_mctrl,
585 .stop_tx = vt8500_stop_tx,
586 .start_tx = vt8500_start_tx,
587 .stop_rx = vt8500_stop_rx,
588 .enable_ms = vt8500_enable_ms,
589 .break_ctl = vt8500_break_ctl,
590 .startup = vt8500_startup,
591 .shutdown = vt8500_shutdown,
592 .set_termios = vt8500_set_termios,
594 .release_port = vt8500_release_port,
595 .request_port = vt8500_request_port,
596 .config_port = vt8500_config_port,
597 .verify_port = vt8500_verify_port,
598 #ifdef CONFIG_CONSOLE_POLL
599 .poll_get_char = vt8500_get_poll_char,
600 .poll_put_char = vt8500_put_poll_char,
604 static struct uart_driver vt8500_uart_driver = {
605 .owner = THIS_MODULE,
606 .driver_name = "vt8500_serial",
607 .dev_name = "ttyWMT",
609 .cons = VT8500_CONSOLE,
612 static unsigned int vt8500_flags; /* none required so far */
613 static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
615 static const struct of_device_id wmt_dt_ids[] = {
616 { .compatible = "via,vt8500-uart", .data = &vt8500_flags},
617 { .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
621 static int vt8500_serial_probe(struct platform_device *pdev)
623 struct vt8500_port *vt8500_port;
624 struct resource *mmres;
625 struct device_node *np = pdev->dev.of_node;
626 const unsigned int *flags;
631 flags = of_device_get_match_data(&pdev->dev);
635 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
639 irq = platform_get_irq(pdev, 0);
644 port = of_alias_get_id(np, "serial");
645 if (port >= VT8500_MAX_PORTS)
652 /* calculate the port id */
653 port = find_first_zero_bit(vt8500_ports_in_use,
657 if (port >= VT8500_MAX_PORTS)
660 /* reserve the port id */
661 if (test_and_set_bit(port, vt8500_ports_in_use)) {
662 /* port already in use - shouldn't really happen */
666 vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
671 vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
672 if (IS_ERR(vt8500_port->uart.membase))
673 return PTR_ERR(vt8500_port->uart.membase);
675 vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
676 if (IS_ERR(vt8500_port->clk)) {
677 dev_err(&pdev->dev, "failed to get clock\n");
681 ret = clk_prepare_enable(vt8500_port->clk);
683 dev_err(&pdev->dev, "failed to enable clock\n");
687 vt8500_port->vt8500_uart_flags = *flags;
688 vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
689 clk_get_rate(vt8500_port->clk),
690 VT8500_RECOMMENDED_CLK
692 vt8500_port->uart.type = PORT_VT8500;
693 vt8500_port->uart.iotype = UPIO_MEM;
694 vt8500_port->uart.mapbase = mmres->start;
695 vt8500_port->uart.irq = irq;
696 vt8500_port->uart.fifosize = 16;
697 vt8500_port->uart.ops = &vt8500_uart_pops;
698 vt8500_port->uart.line = port;
699 vt8500_port->uart.dev = &pdev->dev;
700 vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
701 vt8500_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_VT8500_CONSOLE);
703 /* Serial core uses the magic "16" everywhere - adjust for it */
704 vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
705 vt8500_port->clk_predivisor /
706 VT8500_OVERSAMPLING_DIVISOR;
708 snprintf(vt8500_port->name, sizeof(vt8500_port->name),
709 "VT8500 UART%d", pdev->id);
711 vt8500_uart_ports[port] = vt8500_port;
713 uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
715 platform_set_drvdata(pdev, vt8500_port);
720 static struct platform_driver vt8500_platform_driver = {
721 .probe = vt8500_serial_probe,
723 .name = "vt8500_serial",
724 .of_match_table = wmt_dt_ids,
725 .suppress_bind_attrs = true,
729 static int __init vt8500_serial_init(void)
733 ret = uart_register_driver(&vt8500_uart_driver);
737 ret = platform_driver_register(&vt8500_platform_driver);
740 uart_unregister_driver(&vt8500_uart_driver);
744 device_initcall(vt8500_serial_init);