1 // SPDX-License-Identifier: GPL-2.0
3 * uartlite.c: Serial driver for Xilinx uartlite serial controller
5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2007 Secret Lab Technologies Ltd.
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/console.h>
12 #include <linux/serial.h>
13 #include <linux/serial_core.h>
14 #include <linux/tty.h>
15 #include <linux/tty_flip.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_platform.h>
24 #include <linux/clk.h>
26 #define ULITE_NAME "ttyUL"
27 #define ULITE_MAJOR 204
28 #define ULITE_MINOR 187
29 #define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS
31 /* ---------------------------------------------------------------------
32 * Register definitions
34 * For register details see datasheet:
35 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
40 #define ULITE_STATUS 0x08
41 #define ULITE_CONTROL 0x0c
43 #define ULITE_REGION 16
45 #define ULITE_STATUS_RXVALID 0x01
46 #define ULITE_STATUS_RXFULL 0x02
47 #define ULITE_STATUS_TXEMPTY 0x04
48 #define ULITE_STATUS_TXFULL 0x08
49 #define ULITE_STATUS_IE 0x10
50 #define ULITE_STATUS_OVERRUN 0x20
51 #define ULITE_STATUS_FRAME 0x40
52 #define ULITE_STATUS_PARITY 0x80
54 #define ULITE_CONTROL_RST_TX 0x01
55 #define ULITE_CONTROL_RST_RX 0x02
56 #define ULITE_CONTROL_IE 0x10
58 /* Static pointer to console port */
59 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
60 static struct uart_port *console_port;
63 struct uartlite_data {
64 const struct uartlite_reg_ops *reg_ops;
68 struct uartlite_reg_ops {
69 u32 (*in)(void __iomem *addr);
70 void (*out)(u32 val, void __iomem *addr);
73 static u32 uartlite_inbe32(void __iomem *addr)
75 return ioread32be(addr);
78 static void uartlite_outbe32(u32 val, void __iomem *addr)
80 iowrite32be(val, addr);
83 static const struct uartlite_reg_ops uartlite_be = {
84 .in = uartlite_inbe32,
85 .out = uartlite_outbe32,
88 static u32 uartlite_inle32(void __iomem *addr)
90 return ioread32(addr);
93 static void uartlite_outle32(u32 val, void __iomem *addr)
98 static const struct uartlite_reg_ops uartlite_le = {
99 .in = uartlite_inle32,
100 .out = uartlite_outle32,
103 static inline u32 uart_in32(u32 offset, struct uart_port *port)
105 struct uartlite_data *pdata = port->private_data;
107 return pdata->reg_ops->in(port->membase + offset);
110 static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
112 struct uartlite_data *pdata = port->private_data;
114 pdata->reg_ops->out(val, port->membase + offset);
117 static struct uart_port ulite_ports[ULITE_NR_UARTS];
119 /* ---------------------------------------------------------------------
120 * Core UART driver operations
123 static int ulite_receive(struct uart_port *port, int stat)
125 struct tty_port *tport = &port->state->port;
126 unsigned char ch = 0;
127 char flag = TTY_NORMAL;
129 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
130 | ULITE_STATUS_FRAME)) == 0)
134 if (stat & ULITE_STATUS_RXVALID) {
136 ch = uart_in32(ULITE_RX, port);
138 if (stat & ULITE_STATUS_PARITY)
139 port->icount.parity++;
142 if (stat & ULITE_STATUS_OVERRUN)
143 port->icount.overrun++;
145 if (stat & ULITE_STATUS_FRAME)
146 port->icount.frame++;
149 /* drop byte with parity error if IGNPAR specificed */
150 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
151 stat &= ~ULITE_STATUS_RXVALID;
153 stat &= port->read_status_mask;
155 if (stat & ULITE_STATUS_PARITY)
159 stat &= ~port->ignore_status_mask;
161 if (stat & ULITE_STATUS_RXVALID)
162 tty_insert_flip_char(tport, ch, flag);
164 if (stat & ULITE_STATUS_FRAME)
165 tty_insert_flip_char(tport, 0, TTY_FRAME);
167 if (stat & ULITE_STATUS_OVERRUN)
168 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
173 static int ulite_transmit(struct uart_port *port, int stat)
175 struct circ_buf *xmit = &port->state->xmit;
177 if (stat & ULITE_STATUS_TXFULL)
181 uart_out32(port->x_char, ULITE_TX, port);
187 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
190 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
191 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
195 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
196 uart_write_wakeup(port);
201 static irqreturn_t ulite_isr(int irq, void *dev_id)
203 struct uart_port *port = dev_id;
204 int stat, busy, n = 0;
208 spin_lock_irqsave(&port->lock, flags);
209 stat = uart_in32(ULITE_STATUS, port);
210 busy = ulite_receive(port, stat);
211 busy |= ulite_transmit(port, stat);
212 spin_unlock_irqrestore(&port->lock, flags);
218 tty_flip_buffer_push(&port->state->port);
225 static unsigned int ulite_tx_empty(struct uart_port *port)
230 spin_lock_irqsave(&port->lock, flags);
231 ret = uart_in32(ULITE_STATUS, port);
232 spin_unlock_irqrestore(&port->lock, flags);
234 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
237 static unsigned int ulite_get_mctrl(struct uart_port *port)
239 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
242 static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
247 static void ulite_stop_tx(struct uart_port *port)
252 static void ulite_start_tx(struct uart_port *port)
254 ulite_transmit(port, uart_in32(ULITE_STATUS, port));
257 static void ulite_stop_rx(struct uart_port *port)
259 /* don't forward any more data (like !CREAD) */
260 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
261 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
264 static void ulite_break_ctl(struct uart_port *port, int ctl)
269 static int ulite_startup(struct uart_port *port)
271 struct uartlite_data *pdata = port->private_data;
274 ret = clk_enable(pdata->clk);
276 dev_err(port->dev, "Failed to enable clock\n");
280 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING,
285 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
286 ULITE_CONTROL, port);
287 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
292 static void ulite_shutdown(struct uart_port *port)
294 struct uartlite_data *pdata = port->private_data;
296 uart_out32(0, ULITE_CONTROL, port);
297 uart_in32(ULITE_CONTROL, port); /* dummy */
298 free_irq(port->irq, port);
299 clk_disable(pdata->clk);
302 static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
303 struct ktermios *old)
308 spin_lock_irqsave(&port->lock, flags);
310 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
311 | ULITE_STATUS_TXFULL;
313 if (termios->c_iflag & INPCK)
314 port->read_status_mask |=
315 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
317 port->ignore_status_mask = 0;
318 if (termios->c_iflag & IGNPAR)
319 port->ignore_status_mask |= ULITE_STATUS_PARITY
320 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
322 /* ignore all characters if CREAD is not set */
323 if ((termios->c_cflag & CREAD) == 0)
324 port->ignore_status_mask |=
325 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
326 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
329 baud = uart_get_baud_rate(port, termios, old, 0, 460800);
330 uart_update_timeout(port, termios->c_cflag, baud);
332 spin_unlock_irqrestore(&port->lock, flags);
335 static const char *ulite_type(struct uart_port *port)
337 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
340 static void ulite_release_port(struct uart_port *port)
342 release_mem_region(port->mapbase, ULITE_REGION);
343 iounmap(port->membase);
344 port->membase = NULL;
347 static int ulite_request_port(struct uart_port *port)
349 struct uartlite_data *pdata = port->private_data;
352 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
353 port, (unsigned long long) port->mapbase);
355 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
356 dev_err(port->dev, "Memory region busy\n");
360 port->membase = ioremap(port->mapbase, ULITE_REGION);
361 if (!port->membase) {
362 dev_err(port->dev, "Unable to map registers\n");
363 release_mem_region(port->mapbase, ULITE_REGION);
367 pdata->reg_ops = &uartlite_be;
368 ret = uart_in32(ULITE_CONTROL, port);
369 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
370 ret = uart_in32(ULITE_STATUS, port);
371 /* Endianess detection */
372 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
373 pdata->reg_ops = &uartlite_le;
378 static void ulite_config_port(struct uart_port *port, int flags)
380 if (!ulite_request_port(port))
381 port->type = PORT_UARTLITE;
384 static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
386 /* we don't want the core code to modify any port params */
390 static void ulite_pm(struct uart_port *port, unsigned int state,
391 unsigned int oldstate)
393 struct uartlite_data *pdata = port->private_data;
396 clk_enable(pdata->clk);
398 clk_disable(pdata->clk);
401 #ifdef CONFIG_CONSOLE_POLL
402 static int ulite_get_poll_char(struct uart_port *port)
404 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
407 return uart_in32(ULITE_RX, port);
410 static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
412 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
415 /* write char to device */
416 uart_out32(ch, ULITE_TX, port);
420 static const struct uart_ops ulite_ops = {
421 .tx_empty = ulite_tx_empty,
422 .set_mctrl = ulite_set_mctrl,
423 .get_mctrl = ulite_get_mctrl,
424 .stop_tx = ulite_stop_tx,
425 .start_tx = ulite_start_tx,
426 .stop_rx = ulite_stop_rx,
427 .break_ctl = ulite_break_ctl,
428 .startup = ulite_startup,
429 .shutdown = ulite_shutdown,
430 .set_termios = ulite_set_termios,
432 .release_port = ulite_release_port,
433 .request_port = ulite_request_port,
434 .config_port = ulite_config_port,
435 .verify_port = ulite_verify_port,
437 #ifdef CONFIG_CONSOLE_POLL
438 .poll_get_char = ulite_get_poll_char,
439 .poll_put_char = ulite_put_poll_char,
443 /* ---------------------------------------------------------------------
444 * Console driver operations
447 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
448 static void ulite_console_wait_tx(struct uart_port *port)
451 unsigned long timeout;
454 * Spin waiting for TX fifo to have space available.
455 * When using the Microblaze Debug Module this can take up to 1s
457 timeout = jiffies + msecs_to_jiffies(1000);
459 val = uart_in32(ULITE_STATUS, port);
460 if ((val & ULITE_STATUS_TXFULL) == 0)
462 if (time_after(jiffies, timeout)) {
464 "timeout waiting for TX buffer empty\n");
471 static void ulite_console_putchar(struct uart_port *port, int ch)
473 ulite_console_wait_tx(port);
474 uart_out32(ch, ULITE_TX, port);
477 static void ulite_console_write(struct console *co, const char *s,
480 struct uart_port *port = console_port;
485 if (oops_in_progress) {
486 locked = spin_trylock_irqsave(&port->lock, flags);
488 spin_lock_irqsave(&port->lock, flags);
490 /* save and disable interrupt */
491 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
492 uart_out32(0, ULITE_CONTROL, port);
494 uart_console_write(port, s, count, ulite_console_putchar);
496 ulite_console_wait_tx(port);
498 /* restore interrupt state */
500 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
503 spin_unlock_irqrestore(&port->lock, flags);
506 static int ulite_console_setup(struct console *co, char *options)
508 struct uart_port *port = NULL;
514 if (co->index >= 0 && co->index < ULITE_NR_UARTS)
515 port = ulite_ports + co->index;
517 /* Has the device been initialized yet? */
518 if (!port || !port->mapbase) {
519 pr_debug("console on ttyUL%i not present\n", co->index);
525 /* not initialized yet? */
526 if (!port->membase) {
527 if (ulite_request_port(port))
532 uart_parse_options(options, &baud, &parity, &bits, &flow);
534 return uart_set_options(port, co, baud, parity, bits, flow);
537 static struct uart_driver ulite_uart_driver;
539 static struct console ulite_console = {
541 .write = ulite_console_write,
542 .device = uart_console_device,
543 .setup = ulite_console_setup,
544 .flags = CON_PRINTBUFFER,
545 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
546 .data = &ulite_uart_driver,
549 static void early_uartlite_putc(struct uart_port *port, int c)
552 * Limit how many times we'll spin waiting for TX FIFO status.
553 * This will prevent lockups if the base address is incorrectly
554 * set, or any other issue on the UARTLITE.
555 * This limit is pretty arbitrary, unless we are at about 10 baud
556 * we'll never timeout on a working UART.
559 unsigned retries = 1000000;
560 /* read status bit - 0x8 offset */
561 while (--retries && (readl(port->membase + 8) & (1 << 3)))
564 /* Only attempt the iowrite if we didn't timeout */
565 /* write to TX_FIFO - 0x4 offset */
567 writel(c & 0xff, port->membase + 4);
570 static void early_uartlite_write(struct console *console,
571 const char *s, unsigned n)
573 struct earlycon_device *device = console->data;
574 uart_console_write(&device->port, s, n, early_uartlite_putc);
577 static int __init early_uartlite_setup(struct earlycon_device *device,
580 if (!device->port.membase)
583 device->con->write = early_uartlite_write;
586 EARLYCON_DECLARE(uartlite, early_uartlite_setup);
587 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
588 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
590 #endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
592 static struct uart_driver ulite_uart_driver = {
593 .owner = THIS_MODULE,
594 .driver_name = "uartlite",
595 .dev_name = ULITE_NAME,
596 .major = ULITE_MAJOR,
597 .minor = ULITE_MINOR,
598 .nr = ULITE_NR_UARTS,
599 #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
600 .cons = &ulite_console,
604 /* ---------------------------------------------------------------------
605 * Port assignment functions (mapping devices to uart_port structures)
608 /** ulite_assign: register a uartlite device with the driver
610 * @dev: pointer to device structure
611 * @id: requested id number. Pass -1 for automatic port assignment
612 * @base: base address of uartlite registers
613 * @irq: irq number for uartlite
614 * @pdata: private data for uartlite
616 * Returns: 0 on success, <0 otherwise
618 static int ulite_assign(struct device *dev, int id, phys_addr_t base, int irq,
619 struct uartlite_data *pdata)
621 struct uart_port *port;
624 /* if id = -1; then scan for a free id and use that */
626 for (id = 0; id < ULITE_NR_UARTS; id++)
627 if (ulite_ports[id].mapbase == 0)
630 if (id < 0 || id >= ULITE_NR_UARTS) {
631 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
635 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
636 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
641 port = &ulite_ports[id];
643 spin_lock_init(&port->lock);
646 port->iotype = UPIO_MEM;
647 port->iobase = 1; /* mark port in use */
648 port->mapbase = base;
649 port->membase = NULL;
650 port->ops = &ulite_ops;
652 port->flags = UPF_BOOT_AUTOCONF;
654 port->type = PORT_UNKNOWN;
656 port->private_data = pdata;
658 dev_set_drvdata(dev, port);
660 /* Register the port */
661 rc = uart_add_one_port(&ulite_uart_driver, port);
663 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
665 dev_set_drvdata(dev, NULL);
672 /** ulite_release: register a uartlite device with the driver
674 * @dev: pointer to device structure
676 static int ulite_release(struct device *dev)
678 struct uart_port *port = dev_get_drvdata(dev);
682 rc = uart_remove_one_port(&ulite_uart_driver, port);
683 dev_set_drvdata(dev, NULL);
691 * ulite_suspend - Stop the device.
693 * @dev: handle to the device structure.
696 static int __maybe_unused ulite_suspend(struct device *dev)
698 struct uart_port *port = dev_get_drvdata(dev);
701 uart_suspend_port(&ulite_uart_driver, port);
707 * ulite_resume - Resume the device.
709 * @dev: handle to the device structure.
710 * Return: 0 on success, errno otherwise.
712 static int __maybe_unused ulite_resume(struct device *dev)
714 struct uart_port *port = dev_get_drvdata(dev);
717 uart_resume_port(&ulite_uart_driver, port);
722 /* ---------------------------------------------------------------------
723 * Platform bus binding
726 static SIMPLE_DEV_PM_OPS(ulite_pm_ops, ulite_suspend, ulite_resume);
728 #if defined(CONFIG_OF)
729 /* Match table for of_platform binding */
730 static const struct of_device_id ulite_of_match[] = {
731 { .compatible = "xlnx,opb-uartlite-1.00.b", },
732 { .compatible = "xlnx,xps-uartlite-1.00.a", },
735 MODULE_DEVICE_TABLE(of, ulite_of_match);
736 #endif /* CONFIG_OF */
738 static int ulite_probe(struct platform_device *pdev)
740 struct resource *res;
741 struct uartlite_data *pdata;
747 prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
749 id = be32_to_cpup(prop);
751 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data),
756 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
760 irq = platform_get_irq(pdev, 0);
764 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
765 if (IS_ERR(pdata->clk)) {
766 if (PTR_ERR(pdata->clk) != -ENOENT)
767 return PTR_ERR(pdata->clk);
770 * Clock framework support is optional, continue on
771 * anyways if we don't find a matching clock.
776 ret = clk_prepare_enable(pdata->clk);
778 dev_err(&pdev->dev, "Failed to prepare clock\n");
782 if (!ulite_uart_driver.state) {
783 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n");
784 ret = uart_register_driver(&ulite_uart_driver);
786 dev_err(&pdev->dev, "Failed to register driver\n");
791 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);
793 clk_disable(pdata->clk);
798 static int ulite_remove(struct platform_device *pdev)
800 struct uart_port *port = dev_get_drvdata(&pdev->dev);
801 struct uartlite_data *pdata = port->private_data;
803 clk_disable_unprepare(pdata->clk);
804 return ulite_release(&pdev->dev);
807 /* work with hotplug and coldplug */
808 MODULE_ALIAS("platform:uartlite");
810 static struct platform_driver ulite_platform_driver = {
811 .probe = ulite_probe,
812 .remove = ulite_remove,
815 .of_match_table = of_match_ptr(ulite_of_match),
820 /* ---------------------------------------------------------------------
821 * Module setup/teardown
824 static int __init ulite_init(void)
827 pr_debug("uartlite: calling platform_driver_register()\n");
828 return platform_driver_register(&ulite_platform_driver);
831 static void __exit ulite_exit(void)
833 platform_driver_unregister(&ulite_platform_driver);
834 if (ulite_uart_driver.state)
835 uart_unregister_driver(&ulite_uart_driver);
838 module_init(ulite_init);
839 module_exit(ulite_exit);
841 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
842 MODULE_DESCRIPTION("Xilinx uartlite serial driver");
843 MODULE_LICENSE("GPL");