drivers/tty/serial/stm32-usart.c

   1 /*
   2  * Copyright (C) Maxime Coquelin 2015
   3  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4  *           Gerald Baeza <gerald.baeza@st.com>
   5  * License terms:  GNU General Public License (GPL), version 2
   6  *
   7  * Inspired by st-asc.c from STMicroelectronics (c)
   8  */
   9
  10 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  11 #define SUPPORT_SYSRQ
  12 #endif
  13
  14 #include <linux/clk.h>
  15 #include <linux/console.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-direction.h>
  18 #include <linux/dmaengine.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/io.h>
  21 #include <linux/iopoll.h>
  22 #include <linux/irq.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/serial_core.h>
  29 #include <linux/serial.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/sysrq.h>
  32 #include <linux/tty_flip.h>
  33 #include <linux/tty.h>
  34
  35 #include "stm32-usart.h"
  36
  37 static void stm32_stop_tx(struct uart_port *port);
  38 static void stm32_transmit_chars(struct uart_port *port);
  39
  40 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
  41 {
  42         return container_of(port, struct stm32_port, port);
  43 }
  44
  45 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
  46 {
  47         u32 val;
  48
  49         val = readl_relaxed(port->membase + reg);
  50         val |= bits;
  51         writel_relaxed(val, port->membase + reg);
  52 }
  53
  54 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
  55 {
  56         u32 val;
  57
  58         val = readl_relaxed(port->membase + reg);
  59         val &= ~bits;
  60         writel_relaxed(val, port->membase + reg);
  61 }
  62
  63 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
  64                             bool threaded)
  65 {
  66         struct stm32_port *stm32_port = to_stm32_port(port);
  67         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
  68         enum dma_status status;
  69         struct dma_tx_state state;
  70
  71         *sr = readl_relaxed(port->membase + ofs->isr);
  72
  73         if (threaded && stm32_port->rx_ch) {
  74                 status = dmaengine_tx_status(stm32_port->rx_ch,
  75                                              stm32_port->rx_ch->cookie,
  76                                              &state);
  77                 if ((status == DMA_IN_PROGRESS) &&
  78                     (*last_res != state.residue))
  79                         return 1;
  80                 else
  81                         return 0;
  82         } else if (*sr & USART_SR_RXNE) {
  83                 return 1;
  84         }
  85         return 0;
  86 }
  87
  88 static unsigned long
  89 stm32_get_char(struct uart_port *port, u32 *sr, int *last_res)
  90 {
  91         struct stm32_port *stm32_port = to_stm32_port(port);
  92         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
  93         unsigned long c;
  94
  95         if (stm32_port->rx_ch) {
  96                 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
  97                 if ((*last_res) == 0)
  98                         *last_res = RX_BUF_L;
  99                 return c;
 100         } else {
 101                 return readl_relaxed(port->membase + ofs->rdr);
 102         }
 103 }
 104
 105 static void stm32_receive_chars(struct uart_port *port, bool threaded)
 106 {
 107         struct tty_port *tport = &port->state->port;
 108         struct stm32_port *stm32_port = to_stm32_port(port);
 109         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 110         unsigned long c;
 111         u32 sr;
 112         char flag;
 113         static int last_res = RX_BUF_L;
 114
 115         if (port->irq_wake)
 116                 pm_wakeup_event(tport->tty->dev, 0);
 117
 118         while (stm32_pending_rx(port, &sr, &last_res, threaded)) {
 119                 sr |= USART_SR_DUMMY_RX;
 120                 c = stm32_get_char(port, &sr, &last_res);
 121                 flag = TTY_NORMAL;
 122                 port->icount.rx++;
 123
 124                 if (sr & USART_SR_ERR_MASK) {
 125                         if (sr & USART_SR_LBD) {
 126                                 port->icount.brk++;
 127                                 if (uart_handle_break(port))
 128                                         continue;
 129                         } else if (sr & USART_SR_ORE) {
 130                                 if (ofs->icr != UNDEF_REG)
 131                                         writel_relaxed(USART_ICR_ORECF,
 132                                                        port->membase +
 133                                                        ofs->icr);
 134                                 port->icount.overrun++;
 135                         } else if (sr & USART_SR_PE) {
 136                                 port->icount.parity++;
 137                         } else if (sr & USART_SR_FE) {
 138                                 port->icount.frame++;
 139                         }
 140
 141                         sr &= port->read_status_mask;
 142
 143                         if (sr & USART_SR_LBD)
 144                                 flag = TTY_BREAK;
 145                         else if (sr & USART_SR_PE)
 146                                 flag = TTY_PARITY;
 147                         else if (sr & USART_SR_FE)
 148                                 flag = TTY_FRAME;
 149                 }
 150
 151                 if (uart_handle_sysrq_char(port, c))
 152                         continue;
 153                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 154         }
 155
 156         spin_unlock(&port->lock);
 157         tty_flip_buffer_push(tport);
 158         spin_lock(&port->lock);
 159 }
 160
 161 static void stm32_tx_dma_complete(void *arg)
 162 {
 163         struct uart_port *port = arg;
 164         struct stm32_port *stm32port = to_stm32_port(port);
 165         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 166         unsigned int isr;
 167         int ret;
 168
 169         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 170                                                 isr,
 171                                                 (isr & USART_SR_TC),
 172                                                 10, 100000);
 173
 174         if (ret)
 175                 dev_err(port->dev, "terminal count not set\n");
 176
 177         if (ofs->icr == UNDEF_REG)
 178                 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 179         else
 180                 stm32_set_bits(port, ofs->icr, USART_CR_TC);
 181
 182         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 183         stm32port->tx_dma_busy = false;
 184
 185         /* Let's see if we have pending data to send */
 186         stm32_transmit_chars(port);
 187 }
 188
 189 static void stm32_transmit_chars_pio(struct uart_port *port)
 190 {
 191         struct stm32_port *stm32_port = to_stm32_port(port);
 192         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 193         struct circ_buf *xmit = &port->state->xmit;
 194         unsigned int isr;
 195         int ret;
 196
 197         if (stm32_port->tx_dma_busy) {
 198                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 199                 stm32_port->tx_dma_busy = false;
 200         }
 201
 202         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 203                                                 isr,
 204                                                 (isr & USART_SR_TXE),
 205                                                 10, 100);
 206
 207         if (ret)
 208                 dev_err(port->dev, "tx empty not set\n");
 209
 210         stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 211
 212         writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 213         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 214         port->icount.tx++;
 215 }
 216
 217 static void stm32_transmit_chars_dma(struct uart_port *port)
 218 {
 219         struct stm32_port *stm32port = to_stm32_port(port);
 220         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 221         struct circ_buf *xmit = &port->state->xmit;
 222         struct dma_async_tx_descriptor *desc = NULL;
 223         dma_cookie_t cookie;
 224         unsigned int count, i;
 225
 226         if (stm32port->tx_dma_busy)
 227                 return;
 228
 229         stm32port->tx_dma_busy = true;
 230
 231         count = uart_circ_chars_pending(xmit);
 232
 233         if (count > TX_BUF_L)
 234                 count = TX_BUF_L;
 235
 236         if (xmit->tail < xmit->head) {
 237                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 238         } else {
 239                 size_t one = UART_XMIT_SIZE - xmit->tail;
 240                 size_t two;
 241
 242                 if (one > count)
 243                         one = count;
 244                 two = count - one;
 245
 246                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 247                 if (two)
 248                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 249         }
 250
 251         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 252                                            stm32port->tx_dma_buf,
 253                                            count,
 254                                            DMA_MEM_TO_DEV,
 255                                            DMA_PREP_INTERRUPT);
 256
 257         if (!desc) {
 258                 for (i = count; i > 0; i--)
 259                         stm32_transmit_chars_pio(port);
 260                 return;
 261         }
 262
 263         desc->callback = stm32_tx_dma_complete;
 264         desc->callback_param = port;
 265
 266         /* Push current DMA TX transaction in the pending queue */
 267         cookie = dmaengine_submit(desc);
 268
 269         /* Issue pending DMA TX requests */
 270         dma_async_issue_pending(stm32port->tx_ch);
 271
 272         stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 273         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 274
 275         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 276         port->icount.tx += count;
 277 }
 278
 279 static void stm32_transmit_chars(struct uart_port *port)
 280 {
 281         struct stm32_port *stm32_port = to_stm32_port(port);
 282         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 283         struct circ_buf *xmit = &port->state->xmit;
 284
 285         if (port->x_char) {
 286                 if (stm32_port->tx_dma_busy)
 287                         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 288                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 289                 port->x_char = 0;
 290                 port->icount.tx++;
 291                 if (stm32_port->tx_dma_busy)
 292                         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 293                 return;
 294         }
 295
 296         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 297                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 298                 return;
 299         }
 300
 301         if (stm32_port->tx_ch)
 302                 stm32_transmit_chars_dma(port);
 303         else
 304                 stm32_transmit_chars_pio(port);
 305
 306         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 307                 uart_write_wakeup(port);
 308
 309         if (uart_circ_empty(xmit))
 310                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 311 }
 312
 313 static irqreturn_t stm32_interrupt(int irq, void *ptr)
 314 {
 315         struct uart_port *port = ptr;
 316         struct stm32_port *stm32_port = to_stm32_port(port);
 317         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 318         u32 sr;
 319
 320         spin_lock(&port->lock);
 321
 322         sr = readl_relaxed(port->membase + ofs->isr);
 323
 324         if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
 325                 stm32_receive_chars(port, false);
 326
 327         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
 328                 stm32_transmit_chars(port);
 329
 330         spin_unlock(&port->lock);
 331
 332         if (stm32_port->rx_ch)
 333                 return IRQ_WAKE_THREAD;
 334         else
 335                 return IRQ_HANDLED;
 336 }
 337
 338 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
 339 {
 340         struct uart_port *port = ptr;
 341         struct stm32_port *stm32_port = to_stm32_port(port);
 342
 343         spin_lock(&port->lock);
 344
 345         if (stm32_port->rx_ch)
 346                 stm32_receive_chars(port, true);
 347
 348         spin_unlock(&port->lock);
 349
 350         return IRQ_HANDLED;
 351 }
 352
 353 static unsigned int stm32_tx_empty(struct uart_port *port)
 354 {
 355         struct stm32_port *stm32_port = to_stm32_port(port);
 356         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 357
 358         return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
 359 }
 360
 361 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 362 {
 363         struct stm32_port *stm32_port = to_stm32_port(port);
 364         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 365
 366         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 367                 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 368         else
 369                 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 370 }
 371
 372 static unsigned int stm32_get_mctrl(struct uart_port *port)
 373 {
 374         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 375         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 376 }
 377
 378 /* Transmit stop */
 379 static void stm32_stop_tx(struct uart_port *port)
 380 {
 381         struct stm32_port *stm32_port = to_stm32_port(port);
 382         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 383
 384         stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 385 }
 386
 387 /* There are probably characters waiting to be transmitted. */
 388 static void stm32_start_tx(struct uart_port *port)
 389 {
 390         struct circ_buf *xmit = &port->state->xmit;
 391
 392         if (uart_circ_empty(xmit) && !port->x_char)
 393                 return;
 394
 395         stm32_transmit_chars(port);
 396 }
 397
 398 /* Throttle the remote when input buffer is about to overflow. */
 399 static void stm32_throttle(struct uart_port *port)
 400 {
 401         struct stm32_port *stm32_port = to_stm32_port(port);
 402         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&port->lock, flags);
 406         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 407         spin_unlock_irqrestore(&port->lock, flags);
 408 }
 409
 410 /* Unthrottle the remote, the input buffer can now accept data. */
 411 static void stm32_unthrottle(struct uart_port *port)
 412 {
 413         struct stm32_port *stm32_port = to_stm32_port(port);
 414         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 415         unsigned long flags;
 416
 417         spin_lock_irqsave(&port->lock, flags);
 418         stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 419         spin_unlock_irqrestore(&port->lock, flags);
 420 }
 421
 422 /* Receive stop */
 423 static void stm32_stop_rx(struct uart_port *port)
 424 {
 425         struct stm32_port *stm32_port = to_stm32_port(port);
 426         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 427
 428         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 429 }
 430
 431 /* Handle breaks - ignored by us */
 432 static void stm32_break_ctl(struct uart_port *port, int break_state)
 433 {
 434 }
 435
 436 static int stm32_startup(struct uart_port *port)
 437 {
 438         struct stm32_port *stm32_port = to_stm32_port(port);
 439         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 440         const char *name = to_platform_device(port->dev)->name;
 441         u32 val;
 442         int ret;
 443
 444         ret = request_threaded_irq(port->irq, stm32_interrupt,
 445                                    stm32_threaded_interrupt,
 446                                    IRQF_NO_SUSPEND, name, port);
 447         if (ret)
 448                 return ret;
 449
 450         val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 451         stm32_set_bits(port, ofs->cr1, val);
 452
 453         return 0;
 454 }
 455
 456 static void stm32_shutdown(struct uart_port *port)
 457 {
 458         struct stm32_port *stm32_port = to_stm32_port(port);
 459         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 460         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 461         u32 val;
 462
 463         val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 464         val |= BIT(cfg->uart_enable_bit);
 465         stm32_clr_bits(port, ofs->cr1, val);
 466
 467         free_irq(port->irq, port);
 468 }
 469
 470 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
 471                             struct ktermios *old)
 472 {
 473         struct stm32_port *stm32_port = to_stm32_port(port);
 474         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 475         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 476         unsigned int baud;
 477         u32 usartdiv, mantissa, fraction, oversampling;
 478         tcflag_t cflag = termios->c_cflag;
 479         u32 cr1, cr2, cr3, isr;
 480         unsigned long flags;
 481         int ret;
 482
 483         if (!stm32_port->hw_flow_control)
 484                 cflag &= ~CRTSCTS;
 485
 486         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 487
 488         spin_lock_irqsave(&port->lock, flags);
 489
 490         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 491                                                 isr,
 492                                                 (isr & USART_SR_TC),
 493                                                 10, 100000);
 494
 495         /* Send the TC error message only when ISR_TC is not set. */
 496         if (ret)
 497                 dev_err(port->dev, "Transmission is not complete\n");
 498
 499         /* Stop serial port and reset value */
 500         writel_relaxed(0, port->membase + ofs->cr1);
 501
 502         cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
 503         cr1 |= BIT(cfg->uart_enable_bit);
 504         cr2 = 0;
 505         cr3 = 0;
 506
 507         if (cflag & CSTOPB)
 508                 cr2 |= USART_CR2_STOP_2B;
 509
 510         if (cflag & PARENB) {
 511                 cr1 |= USART_CR1_PCE;
 512                 if ((cflag & CSIZE) == CS8) {
 513                         if (cfg->has_7bits_data)
 514                                 cr1 |= USART_CR1_M0;
 515                         else
 516                                 cr1 |= USART_CR1_M;
 517                 }
 518         }
 519
 520         if (cflag & PARODD)
 521                 cr1 |= USART_CR1_PS;
 522
 523         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
 524         if (cflag & CRTSCTS) {
 525                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 526                 cr3 |= USART_CR3_CTSE;
 527         }
 528
 529         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
 530
 531         /*
 532          * The USART supports 16 or 8 times oversampling.
 533          * By default we prefer 16 times oversampling, so that the receiver
 534          * has a better tolerance to clock deviations.
 535          * 8 times oversampling is only used to achieve higher speeds.
 536          */
 537         if (usartdiv < 16) {
 538                 oversampling = 8;
 539                 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
 540         } else {
 541                 oversampling = 16;
 542                 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
 543         }
 544
 545         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
 546         fraction = usartdiv % oversampling;
 547         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
 548
 549         uart_update_timeout(port, cflag, baud);
 550
 551         port->read_status_mask = USART_SR_ORE;
 552         if (termios->c_iflag & INPCK)
 553                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
 554         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 555                 port->read_status_mask |= USART_SR_LBD;
 556
 557         /* Characters to ignore */
 558         port->ignore_status_mask = 0;
 559         if (termios->c_iflag & IGNPAR)
 560                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
 561         if (termios->c_iflag & IGNBRK) {
 562                 port->ignore_status_mask |= USART_SR_LBD;
 563                 /*
 564                  * If we're ignoring parity and break indicators,
 565                  * ignore overruns too (for real raw support).
 566                  */
 567                 if (termios->c_iflag & IGNPAR)
 568                         port->ignore_status_mask |= USART_SR_ORE;
 569         }
 570
 571         /* Ignore all characters if CREAD is not set */
 572         if ((termios->c_cflag & CREAD) == 0)
 573                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
 574
 575         if (stm32_port->rx_ch)
 576                 cr3 |= USART_CR3_DMAR;
 577
 578         writel_relaxed(cr3, port->membase + ofs->cr3);
 579         writel_relaxed(cr2, port->membase + ofs->cr2);
 580         writel_relaxed(cr1, port->membase + ofs->cr1);
 581
 582         spin_unlock_irqrestore(&port->lock, flags);
 583 }
 584
 585 static const char *stm32_type(struct uart_port *port)
 586 {
 587         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
 588 }
 589
 590 static void stm32_release_port(struct uart_port *port)
 591 {
 592 }
 593
 594 static int stm32_request_port(struct uart_port *port)
 595 {
 596         return 0;
 597 }
 598
 599 static void stm32_config_port(struct uart_port *port, int flags)
 600 {
 601         if (flags & UART_CONFIG_TYPE)
 602                 port->type = PORT_STM32;
 603 }
 604
 605 static int
 606 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
 607 {
 608         /* No user changeable parameters */
 609         return -EINVAL;
 610 }
 611
 612 static void stm32_pm(struct uart_port *port, unsigned int state,
 613                 unsigned int oldstate)
 614 {
 615         struct stm32_port *stm32port = container_of(port,
 616                         struct stm32_port, port);
 617         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 618         struct stm32_usart_config *cfg = &stm32port->info->cfg;
 619         unsigned long flags = 0;
 620
 621         switch (state) {
 622         case UART_PM_STATE_ON:
 623                 clk_prepare_enable(stm32port->clk);
 624                 break;
 625         case UART_PM_STATE_OFF:
 626                 spin_lock_irqsave(&port->lock, flags);
 627                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 628                 spin_unlock_irqrestore(&port->lock, flags);
 629                 clk_disable_unprepare(stm32port->clk);
 630                 break;
 631         }
 632 }
 633
 634 static const struct uart_ops stm32_uart_ops = {
 635         .tx_empty       = stm32_tx_empty,
 636         .set_mctrl      = stm32_set_mctrl,
 637         .get_mctrl      = stm32_get_mctrl,
 638         .stop_tx        = stm32_stop_tx,
 639         .start_tx       = stm32_start_tx,
 640         .throttle       = stm32_throttle,
 641         .unthrottle     = stm32_unthrottle,
 642         .stop_rx        = stm32_stop_rx,
 643         .break_ctl      = stm32_break_ctl,
 644         .startup        = stm32_startup,
 645         .shutdown       = stm32_shutdown,
 646         .set_termios    = stm32_set_termios,
 647         .pm             = stm32_pm,
 648         .type           = stm32_type,
 649         .release_port   = stm32_release_port,
 650         .request_port   = stm32_request_port,
 651         .config_port    = stm32_config_port,
 652         .verify_port    = stm32_verify_port,
 653 };
 654
 655 static int stm32_init_port(struct stm32_port *stm32port,
 656                           struct platform_device *pdev)
 657 {
 658         struct uart_port *port = &stm32port->port;
 659         struct resource *res;
 660         int ret;
 661
 662         port->iotype    = UPIO_MEM;
 663         port->flags     = UPF_BOOT_AUTOCONF;
 664         port->ops       = &stm32_uart_ops;
 665         port->dev       = &pdev->dev;
 666         port->irq       = platform_get_irq(pdev, 0);
 667
 668         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 669         port->membase = devm_ioremap_resource(&pdev->dev, res);
 670         if (IS_ERR(port->membase))
 671                 return PTR_ERR(port->membase);
 672         port->mapbase = res->start;
 673
 674         spin_lock_init(&port->lock);
 675
 676         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
 677         if (IS_ERR(stm32port->clk))
 678                 return PTR_ERR(stm32port->clk);
 679
 680         /* Ensure that clk rate is correct by enabling the clk */
 681         ret = clk_prepare_enable(stm32port->clk);
 682         if (ret)
 683                 return ret;
 684
 685         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
 686         if (!stm32port->port.uartclk)
 687                 ret = -EINVAL;
 688
 689         return ret;
 690 }
 691
 692 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
 693 {
 694         struct device_node *np = pdev->dev.of_node;
 695         int id;
 696
 697         if (!np)
 698                 return NULL;
 699
 700         id = of_alias_get_id(np, "serial");
 701         if (id < 0)
 702                 id = 0;
 703
 704         if (WARN_ON(id >= STM32_MAX_PORTS))
 705                 return NULL;
 706
 707         stm32_ports[id].hw_flow_control = of_property_read_bool(np,
 708                                                         "st,hw-flow-ctrl");
 709         stm32_ports[id].port.line = id;
 710         return &stm32_ports[id];
 711 }
 712
 713 #ifdef CONFIG_OF
 714 static const struct of_device_id stm32_match[] = {
 715         { .compatible = "st,stm32-usart", .data = &stm32f4_info},
 716         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
 717         { .compatible = "st,stm32f7-usart", .data = &stm32f7_info},
 718         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
 719         {},
 720 };
 721
 722 MODULE_DEVICE_TABLE(of, stm32_match);
 723 #endif
 724
 725 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
 726                                  struct platform_device *pdev)
 727 {
 728         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 729         struct uart_port *port = &stm32port->port;
 730         struct device *dev = &pdev->dev;
 731         struct dma_slave_config config;
 732         struct dma_async_tx_descriptor *desc = NULL;
 733         dma_cookie_t cookie;
 734         int ret;
 735
 736         /* Request DMA RX channel */
 737         stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
 738         if (!stm32port->rx_ch) {
 739                 dev_info(dev, "rx dma alloc failed\n");
 740                 return -ENODEV;
 741         }
 742         stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
 743                                                  &stm32port->rx_dma_buf,
 744                                                  GFP_KERNEL);
 745         if (!stm32port->rx_buf) {
 746                 ret = -ENOMEM;
 747                 goto alloc_err;
 748         }
 749
 750         /* Configure DMA channel */
 751         memset(&config, 0, sizeof(config));
 752         config.src_addr = port->mapbase + ofs->rdr;
 753         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 754
 755         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
 756         if (ret < 0) {
 757                 dev_err(dev, "rx dma channel config failed\n");
 758                 ret = -ENODEV;
 759                 goto config_err;
 760         }
 761
 762         /* Prepare a DMA cyclic transaction */
 763         desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
 764                                          stm32port->rx_dma_buf,
 765                                          RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
 766                                          DMA_PREP_INTERRUPT);
 767         if (!desc) {
 768                 dev_err(dev, "rx dma prep cyclic failed\n");
 769                 ret = -ENODEV;
 770                 goto config_err;
 771         }
 772
 773         /* No callback as dma buffer is drained on usart interrupt */
 774         desc->callback = NULL;
 775         desc->callback_param = NULL;
 776
 777         /* Push current DMA transaction in the pending queue */
 778         cookie = dmaengine_submit(desc);
 779
 780         /* Issue pending DMA requests */
 781         dma_async_issue_pending(stm32port->rx_ch);
 782
 783         return 0;
 784
 785 config_err:
 786         dma_free_coherent(&pdev->dev,
 787                           RX_BUF_L, stm32port->rx_buf,
 788                           stm32port->rx_dma_buf);
 789
 790 alloc_err:
 791         dma_release_channel(stm32port->rx_ch);
 792         stm32port->rx_ch = NULL;
 793
 794         return ret;
 795 }
 796
 797 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
 798                                  struct platform_device *pdev)
 799 {
 800         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 801         struct uart_port *port = &stm32port->port;
 802         struct device *dev = &pdev->dev;
 803         struct dma_slave_config config;
 804         int ret;
 805
 806         stm32port->tx_dma_busy = false;
 807
 808         /* Request DMA TX channel */
 809         stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
 810         if (!stm32port->tx_ch) {
 811                 dev_info(dev, "tx dma alloc failed\n");
 812                 return -ENODEV;
 813         }
 814         stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
 815                                                  &stm32port->tx_dma_buf,
 816                                                  GFP_KERNEL);
 817         if (!stm32port->tx_buf) {
 818                 ret = -ENOMEM;
 819                 goto alloc_err;
 820         }
 821
 822         /* Configure DMA channel */
 823         memset(&config, 0, sizeof(config));
 824         config.dst_addr = port->mapbase + ofs->tdr;
 825         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 826
 827         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
 828         if (ret < 0) {
 829                 dev_err(dev, "tx dma channel config failed\n");
 830                 ret = -ENODEV;
 831                 goto config_err;
 832         }
 833
 834         return 0;
 835
 836 config_err:
 837         dma_free_coherent(&pdev->dev,
 838                           TX_BUF_L, stm32port->tx_buf,
 839                           stm32port->tx_dma_buf);
 840
 841 alloc_err:
 842         dma_release_channel(stm32port->tx_ch);
 843         stm32port->tx_ch = NULL;
 844
 845         return ret;
 846 }
 847
 848 static int stm32_serial_probe(struct platform_device *pdev)
 849 {
 850         const struct of_device_id *match;
 851         struct stm32_port *stm32port;
 852         int ret;
 853
 854         stm32port = stm32_of_get_stm32_port(pdev);
 855         if (!stm32port)
 856                 return -ENODEV;
 857
 858         match = of_match_device(stm32_match, &pdev->dev);
 859         if (match && match->data)
 860                 stm32port->info = (struct stm32_usart_info *)match->data;
 861         else
 862                 return -EINVAL;
 863
 864         ret = stm32_init_port(stm32port, pdev);
 865         if (ret)
 866                 return ret;
 867
 868         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
 869         if (ret)
 870                 return ret;
 871
 872         ret = stm32_of_dma_rx_probe(stm32port, pdev);
 873         if (ret)
 874                 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
 875
 876         ret = stm32_of_dma_tx_probe(stm32port, pdev);
 877         if (ret)
 878                 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
 879
 880         platform_set_drvdata(pdev, &stm32port->port);
 881
 882         return 0;
 883 }
 884
 885 static int stm32_serial_remove(struct platform_device *pdev)
 886 {
 887         struct uart_port *port = platform_get_drvdata(pdev);
 888         struct stm32_port *stm32_port = to_stm32_port(port);
 889         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 890
 891         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
 892
 893         if (stm32_port->rx_ch)
 894                 dma_release_channel(stm32_port->rx_ch);
 895
 896         if (stm32_port->rx_dma_buf)
 897                 dma_free_coherent(&pdev->dev,
 898                                   RX_BUF_L, stm32_port->rx_buf,
 899                                   stm32_port->rx_dma_buf);
 900
 901         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 902
 903         if (stm32_port->tx_ch)
 904                 dma_release_channel(stm32_port->tx_ch);
 905
 906         if (stm32_port->tx_dma_buf)
 907                 dma_free_coherent(&pdev->dev,
 908                                   TX_BUF_L, stm32_port->tx_buf,
 909                                   stm32_port->tx_dma_buf);
 910
 911         clk_disable_unprepare(stm32_port->clk);
 912
 913         return uart_remove_one_port(&stm32_usart_driver, port);
 914 }
 915
 916
 917 #ifdef CONFIG_SERIAL_STM32_CONSOLE
 918 static void stm32_console_putchar(struct uart_port *port, int ch)
 919 {
 920         struct stm32_port *stm32_port = to_stm32_port(port);
 921         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 922
 923         while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
 924                 cpu_relax();
 925
 926         writel_relaxed(ch, port->membase + ofs->tdr);
 927 }
 928
 929 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
 930 {
 931         struct uart_port *port = &stm32_ports[co->index].port;
 932         struct stm32_port *stm32_port = to_stm32_port(port);
 933         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 934         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 935         unsigned long flags;
 936         u32 old_cr1, new_cr1;
 937         int locked = 1;
 938
 939         local_irq_save(flags);
 940         if (port->sysrq)
 941                 locked = 0;
 942         else if (oops_in_progress)
 943                 locked = spin_trylock(&port->lock);
 944         else
 945                 spin_lock(&port->lock);
 946
 947         /* Save and disable interrupts, enable the transmitter */
 948         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
 949         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
 950         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
 951         writel_relaxed(new_cr1, port->membase + ofs->cr1);
 952
 953         uart_console_write(port, s, cnt, stm32_console_putchar);
 954
 955         /* Restore interrupt state */
 956         writel_relaxed(old_cr1, port->membase + ofs->cr1);
 957
 958         if (locked)
 959                 spin_unlock(&port->lock);
 960         local_irq_restore(flags);
 961 }
 962
 963 static int stm32_console_setup(struct console *co, char *options)
 964 {
 965         struct stm32_port *stm32port;
 966         int baud = 9600;
 967         int bits = 8;
 968         int parity = 'n';
 969         int flow = 'n';
 970
 971         if (co->index >= STM32_MAX_PORTS)
 972                 return -ENODEV;
 973
 974         stm32port = &stm32_ports[co->index];
 975
 976         /*
 977          * This driver does not support early console initialization
 978          * (use ARM early printk support instead), so we only expect
 979          * this to be called during the uart port registration when the
 980          * driver gets probed and the port should be mapped at that point.
 981          */
 982         if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
 983                 return -ENXIO;
 984
 985         if (options)
 986                 uart_parse_options(options, &baud, &parity, &bits, &flow);
 987
 988         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
 989 }
 990
 991 static struct console stm32_console = {
 992         .name           = STM32_SERIAL_NAME,
 993         .device         = uart_console_device,
 994         .write          = stm32_console_write,
 995         .setup          = stm32_console_setup,
 996         .flags          = CON_PRINTBUFFER,
 997         .index          = -1,
 998         .data           = &stm32_usart_driver,
 999 };
1000
1001 #define STM32_SERIAL_CONSOLE (&stm32_console)
1002
1003 #else
1004 #define STM32_SERIAL_CONSOLE NULL
1005 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1006
1007 static struct uart_driver stm32_usart_driver = {
1008         .driver_name    = DRIVER_NAME,
1009         .dev_name       = STM32_SERIAL_NAME,
1010         .major          = 0,
1011         .minor          = 0,
1012         .nr             = STM32_MAX_PORTS,
1013         .cons           = STM32_SERIAL_CONSOLE,
1014 };
1015
1016 static struct platform_driver stm32_serial_driver = {
1017         .probe          = stm32_serial_probe,
1018         .remove         = stm32_serial_remove,
1019         .driver = {
1020                 .name   = DRIVER_NAME,
1021                 .of_match_table = of_match_ptr(stm32_match),
1022         },
1023 };
1024
1025 static int __init usart_init(void)
1026 {
1027         static char banner[] __initdata = "STM32 USART driver initialized";
1028         int ret;
1029
1030         pr_info("%s\n", banner);
1031
1032         ret = uart_register_driver(&stm32_usart_driver);
1033         if (ret)
1034                 return ret;
1035
1036         ret = platform_driver_register(&stm32_serial_driver);
1037         if (ret)
1038                 uart_unregister_driver(&stm32_usart_driver);
1039
1040         return ret;
1041 }
1042
1043 static void __exit usart_exit(void)
1044 {
1045         platform_driver_unregister(&stm32_serial_driver);
1046         uart_unregister_driver(&stm32_usart_driver);
1047 }
1048
1049 module_init(usart_init);
1050 module_exit(usart_exit);
1051
1052 MODULE_ALIAS("platform:" DRIVER_NAME);
1053 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1054 MODULE_LICENSE("GPL v2");