drivers/tty/serial/stm32-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6  *           Gerald Baeza <gerald.baeza@st.com>
   7  *
   8  * Inspired by st-asc.c from STMicroelectronics (c)
   9  */
  10
  11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14
  15 #include <linux/clk.h>
  16 #include <linux/console.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-direction.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/irq.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pm_wakeirq.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/serial.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/sysrq.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/tty.h>
  36
  37 #include "stm32-usart.h"
  38
  39 static void stm32_stop_tx(struct uart_port *port);
  40 static void stm32_transmit_chars(struct uart_port *port);
  41
  42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
  43 {
  44         return container_of(port, struct stm32_port, port);
  45 }
  46
  47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
  48 {
  49         u32 val;
  50
  51         val = readl_relaxed(port->membase + reg);
  52         val |= bits;
  53         writel_relaxed(val, port->membase + reg);
  54 }
  55
  56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
  57 {
  58         u32 val;
  59
  60         val = readl_relaxed(port->membase + reg);
  61         val &= ~bits;
  62         writel_relaxed(val, port->membase + reg);
  63 }
  64
  65 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
  66                                    u32 delay_DDE, u32 baud)
  67 {
  68         u32 rs485_deat_dedt;
  69         u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
  70         bool over8;
  71
  72         *cr3 |= USART_CR3_DEM;
  73         over8 = *cr1 & USART_CR1_OVER8;
  74
  75         *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
  76
  77         if (over8)
  78                 rs485_deat_dedt = delay_ADE * baud * 8;
  79         else
  80                 rs485_deat_dedt = delay_ADE * baud * 16;
  81
  82         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  83         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  84                           rs485_deat_dedt_max : rs485_deat_dedt;
  85         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
  86                            USART_CR1_DEAT_MASK;
  87         *cr1 |= rs485_deat_dedt;
  88
  89         if (over8)
  90                 rs485_deat_dedt = delay_DDE * baud * 8;
  91         else
  92                 rs485_deat_dedt = delay_DDE * baud * 16;
  93
  94         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  95         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  96                           rs485_deat_dedt_max : rs485_deat_dedt;
  97         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
  98                            USART_CR1_DEDT_MASK;
  99         *cr1 |= rs485_deat_dedt;
 100 }
 101
 102 static int stm32_config_rs485(struct uart_port *port,
 103                               struct serial_rs485 *rs485conf)
 104 {
 105         struct stm32_port *stm32_port = to_stm32_port(port);
 106         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 107         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 108         u32 usartdiv, baud, cr1, cr3;
 109         bool over8;
 110
 111         stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 112
 113         port->rs485 = *rs485conf;
 114
 115         rs485conf->flags |= SER_RS485_RX_DURING_TX;
 116
 117         if (rs485conf->flags & SER_RS485_ENABLED) {
 118                 cr1 = readl_relaxed(port->membase + ofs->cr1);
 119                 cr3 = readl_relaxed(port->membase + ofs->cr3);
 120                 usartdiv = readl_relaxed(port->membase + ofs->brr);
 121                 usartdiv = usartdiv & GENMASK(15, 0);
 122                 over8 = cr1 & USART_CR1_OVER8;
 123
 124                 if (over8)
 125                         usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
 126                                    << USART_BRR_04_R_SHIFT;
 127
 128                 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
 129                 stm32_config_reg_rs485(&cr1, &cr3,
 130                                        rs485conf->delay_rts_before_send,
 131                                        rs485conf->delay_rts_after_send, baud);
 132
 133                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 134                         cr3 &= ~USART_CR3_DEP;
 135                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 136                 } else {
 137                         cr3 |= USART_CR3_DEP;
 138                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 139                 }
 140
 141                 writel_relaxed(cr3, port->membase + ofs->cr3);
 142                 writel_relaxed(cr1, port->membase + ofs->cr1);
 143         } else {
 144                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
 145                 stm32_clr_bits(port, ofs->cr1,
 146                                USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 147         }
 148
 149         stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 150
 151         return 0;
 152 }
 153
 154 static int stm32_init_rs485(struct uart_port *port,
 155                             struct platform_device *pdev)
 156 {
 157         struct serial_rs485 *rs485conf = &port->rs485;
 158
 159         rs485conf->flags = 0;
 160         rs485conf->delay_rts_before_send = 0;
 161         rs485conf->delay_rts_after_send = 0;
 162
 163         if (!pdev->dev.of_node)
 164                 return -ENODEV;
 165
 166         uart_get_rs485_mode(&pdev->dev, rs485conf);
 167
 168         return 0;
 169 }
 170
 171 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
 172                             bool threaded)
 173 {
 174         struct stm32_port *stm32_port = to_stm32_port(port);
 175         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 176         enum dma_status status;
 177         struct dma_tx_state state;
 178
 179         *sr = readl_relaxed(port->membase + ofs->isr);
 180
 181         if (threaded && stm32_port->rx_ch) {
 182                 status = dmaengine_tx_status(stm32_port->rx_ch,
 183                                              stm32_port->rx_ch->cookie,
 184                                              &state);
 185                 if ((status == DMA_IN_PROGRESS) &&
 186                     (*last_res != state.residue))
 187                         return 1;
 188                 else
 189                         return 0;
 190         } else if (*sr & USART_SR_RXNE) {
 191                 return 1;
 192         }
 193         return 0;
 194 }
 195
 196 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
 197                                     int *last_res)
 198 {
 199         struct stm32_port *stm32_port = to_stm32_port(port);
 200         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 201         unsigned long c;
 202
 203         if (stm32_port->rx_ch) {
 204                 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
 205                 if ((*last_res) == 0)
 206                         *last_res = RX_BUF_L;
 207         } else {
 208                 c = readl_relaxed(port->membase + ofs->rdr);
 209                 /* apply RDR data mask */
 210                 c &= stm32_port->rdr_mask;
 211         }
 212
 213         return c;
 214 }
 215
 216 static void stm32_receive_chars(struct uart_port *port, bool threaded)
 217 {
 218         struct tty_port *tport = &port->state->port;
 219         struct stm32_port *stm32_port = to_stm32_port(port);
 220         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 221         unsigned long c;
 222         u32 sr;
 223         char flag;
 224
 225         if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 226                 pm_wakeup_event(tport->tty->dev, 0);
 227
 228         while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
 229                 sr |= USART_SR_DUMMY_RX;
 230                 flag = TTY_NORMAL;
 231
 232                 /*
 233                  * Status bits has to be cleared before reading the RDR:
 234                  * In FIFO mode, reading the RDR will pop the next data
 235                  * (if any) along with its status bits into the SR.
 236                  * Not doing so leads to misalignement between RDR and SR,
 237                  * and clear status bits of the next rx data.
 238                  *
 239                  * Clear errors flags for stm32f7 and stm32h7 compatible
 240                  * devices. On stm32f4 compatible devices, the error bit is
 241                  * cleared by the sequence [read SR - read DR].
 242                  */
 243                 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
 244                         writel_relaxed(sr & USART_SR_ERR_MASK,
 245                                        port->membase + ofs->icr);
 246
 247                 c = stm32_get_char(port, &sr, &stm32_port->last_res);
 248                 port->icount.rx++;
 249                 if (sr & USART_SR_ERR_MASK) {
 250                         if (sr & USART_SR_ORE) {
 251                                 port->icount.overrun++;
 252                         } else if (sr & USART_SR_PE) {
 253                                 port->icount.parity++;
 254                         } else if (sr & USART_SR_FE) {
 255                                 /* Break detection if character is null */
 256                                 if (!c) {
 257                                         port->icount.brk++;
 258                                         if (uart_handle_break(port))
 259                                                 continue;
 260                                 } else {
 261                                         port->icount.frame++;
 262                                 }
 263                         }
 264
 265                         sr &= port->read_status_mask;
 266
 267                         if (sr & USART_SR_PE) {
 268                                 flag = TTY_PARITY;
 269                         } else if (sr & USART_SR_FE) {
 270                                 if (!c)
 271                                         flag = TTY_BREAK;
 272                                 else
 273                                         flag = TTY_FRAME;
 274                         }
 275                 }
 276
 277                 if (uart_handle_sysrq_char(port, c))
 278                         continue;
 279                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 280         }
 281
 282         spin_unlock(&port->lock);
 283         tty_flip_buffer_push(tport);
 284         spin_lock(&port->lock);
 285 }
 286
 287 static void stm32_tx_dma_complete(void *arg)
 288 {
 289         struct uart_port *port = arg;
 290         struct stm32_port *stm32port = to_stm32_port(port);
 291         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 292
 293         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 294         stm32port->tx_dma_busy = false;
 295
 296         /* Let's see if we have pending data to send */
 297         stm32_transmit_chars(port);
 298 }
 299
 300 static void stm32_transmit_chars_pio(struct uart_port *port)
 301 {
 302         struct stm32_port *stm32_port = to_stm32_port(port);
 303         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 304         struct circ_buf *xmit = &port->state->xmit;
 305         unsigned int isr;
 306         int ret;
 307
 308         if (stm32_port->tx_dma_busy) {
 309                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 310                 stm32_port->tx_dma_busy = false;
 311         }
 312
 313         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 314                                                 isr,
 315                                                 (isr & USART_SR_TXE),
 316                                                 10, 100000);
 317
 318         if (ret)
 319                 dev_err(port->dev, "tx empty not set\n");
 320
 321         stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 322
 323         writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 324         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 325         port->icount.tx++;
 326 }
 327
 328 static void stm32_transmit_chars_dma(struct uart_port *port)
 329 {
 330         struct stm32_port *stm32port = to_stm32_port(port);
 331         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 332         struct circ_buf *xmit = &port->state->xmit;
 333         struct dma_async_tx_descriptor *desc = NULL;
 334         dma_cookie_t cookie;
 335         unsigned int count, i;
 336
 337         if (stm32port->tx_dma_busy)
 338                 return;
 339
 340         stm32port->tx_dma_busy = true;
 341
 342         count = uart_circ_chars_pending(xmit);
 343
 344         if (count > TX_BUF_L)
 345                 count = TX_BUF_L;
 346
 347         if (xmit->tail < xmit->head) {
 348                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 349         } else {
 350                 size_t one = UART_XMIT_SIZE - xmit->tail;
 351                 size_t two;
 352
 353                 if (one > count)
 354                         one = count;
 355                 two = count - one;
 356
 357                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 358                 if (two)
 359                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 360         }
 361
 362         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 363                                            stm32port->tx_dma_buf,
 364                                            count,
 365                                            DMA_MEM_TO_DEV,
 366                                            DMA_PREP_INTERRUPT);
 367
 368         if (!desc) {
 369                 for (i = count; i > 0; i--)
 370                         stm32_transmit_chars_pio(port);
 371                 return;
 372         }
 373
 374         desc->callback = stm32_tx_dma_complete;
 375         desc->callback_param = port;
 376
 377         /* Push current DMA TX transaction in the pending queue */
 378         cookie = dmaengine_submit(desc);
 379
 380         /* Issue pending DMA TX requests */
 381         dma_async_issue_pending(stm32port->tx_ch);
 382
 383         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 384
 385         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 386         port->icount.tx += count;
 387 }
 388
 389 static void stm32_transmit_chars(struct uart_port *port)
 390 {
 391         struct stm32_port *stm32_port = to_stm32_port(port);
 392         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 393         struct circ_buf *xmit = &port->state->xmit;
 394
 395         if (port->x_char) {
 396                 if (stm32_port->tx_dma_busy)
 397                         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 398                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 399                 port->x_char = 0;
 400                 port->icount.tx++;
 401                 if (stm32_port->tx_dma_busy)
 402                         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 403                 return;
 404         }
 405
 406         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 407                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 408                 return;
 409         }
 410
 411         if (ofs->icr == UNDEF_REG)
 412                 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 413         else
 414                 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
 415
 416         if (stm32_port->tx_ch)
 417                 stm32_transmit_chars_dma(port);
 418         else
 419                 stm32_transmit_chars_pio(port);
 420
 421         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 422                 uart_write_wakeup(port);
 423
 424         if (uart_circ_empty(xmit))
 425                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 426 }
 427
 428 static irqreturn_t stm32_interrupt(int irq, void *ptr)
 429 {
 430         struct uart_port *port = ptr;
 431         struct stm32_port *stm32_port = to_stm32_port(port);
 432         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 433         u32 sr;
 434
 435         spin_lock(&port->lock);
 436
 437         sr = readl_relaxed(port->membase + ofs->isr);
 438
 439         if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
 440                 writel_relaxed(USART_ICR_WUCF,
 441                                port->membase + ofs->icr);
 442
 443         if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
 444                 stm32_receive_chars(port, false);
 445
 446         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
 447                 stm32_transmit_chars(port);
 448
 449         spin_unlock(&port->lock);
 450
 451         if (stm32_port->rx_ch)
 452                 return IRQ_WAKE_THREAD;
 453         else
 454                 return IRQ_HANDLED;
 455 }
 456
 457 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
 458 {
 459         struct uart_port *port = ptr;
 460         struct stm32_port *stm32_port = to_stm32_port(port);
 461
 462         spin_lock(&port->lock);
 463
 464         if (stm32_port->rx_ch)
 465                 stm32_receive_chars(port, true);
 466
 467         spin_unlock(&port->lock);
 468
 469         return IRQ_HANDLED;
 470 }
 471
 472 static unsigned int stm32_tx_empty(struct uart_port *port)
 473 {
 474         struct stm32_port *stm32_port = to_stm32_port(port);
 475         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 476
 477         if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
 478                 return TIOCSER_TEMT;
 479
 480         return 0;
 481 }
 482
 483 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 484 {
 485         struct stm32_port *stm32_port = to_stm32_port(port);
 486         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 487
 488         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 489                 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 490         else
 491                 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 492 }
 493
 494 static unsigned int stm32_get_mctrl(struct uart_port *port)
 495 {
 496         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 497         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 498 }
 499
 500 /* Transmit stop */
 501 static void stm32_stop_tx(struct uart_port *port)
 502 {
 503         struct stm32_port *stm32_port = to_stm32_port(port);
 504         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 505
 506         stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 507 }
 508
 509 /* There are probably characters waiting to be transmitted. */
 510 static void stm32_start_tx(struct uart_port *port)
 511 {
 512         struct circ_buf *xmit = &port->state->xmit;
 513
 514         if (uart_circ_empty(xmit) && !port->x_char)
 515                 return;
 516
 517         stm32_transmit_chars(port);
 518 }
 519
 520 /* Throttle the remote when input buffer is about to overflow. */
 521 static void stm32_throttle(struct uart_port *port)
 522 {
 523         struct stm32_port *stm32_port = to_stm32_port(port);
 524         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 525         unsigned long flags;
 526
 527         spin_lock_irqsave(&port->lock, flags);
 528         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 529         spin_unlock_irqrestore(&port->lock, flags);
 530 }
 531
 532 /* Unthrottle the remote, the input buffer can now accept data. */
 533 static void stm32_unthrottle(struct uart_port *port)
 534 {
 535         struct stm32_port *stm32_port = to_stm32_port(port);
 536         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 537         unsigned long flags;
 538
 539         spin_lock_irqsave(&port->lock, flags);
 540         stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 541         spin_unlock_irqrestore(&port->lock, flags);
 542 }
 543
 544 /* Receive stop */
 545 static void stm32_stop_rx(struct uart_port *port)
 546 {
 547         struct stm32_port *stm32_port = to_stm32_port(port);
 548         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 549
 550         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 551 }
 552
 553 /* Handle breaks - ignored by us */
 554 static void stm32_break_ctl(struct uart_port *port, int break_state)
 555 {
 556 }
 557
 558 static int stm32_startup(struct uart_port *port)
 559 {
 560         struct stm32_port *stm32_port = to_stm32_port(port);
 561         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 562         const char *name = to_platform_device(port->dev)->name;
 563         u32 val;
 564         int ret;
 565
 566         ret = request_threaded_irq(port->irq, stm32_interrupt,
 567                                    stm32_threaded_interrupt,
 568                                    IRQF_NO_SUSPEND, name, port);
 569         if (ret)
 570                 return ret;
 571
 572         val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 573         if (stm32_port->fifoen)
 574                 val |= USART_CR1_FIFOEN;
 575         stm32_set_bits(port, ofs->cr1, val);
 576
 577         return 0;
 578 }
 579
 580 static void stm32_shutdown(struct uart_port *port)
 581 {
 582         struct stm32_port *stm32_port = to_stm32_port(port);
 583         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 584         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 585         u32 val, isr;
 586         int ret;
 587
 588         val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 589         val |= BIT(cfg->uart_enable_bit);
 590         if (stm32_port->fifoen)
 591                 val |= USART_CR1_FIFOEN;
 592
 593         ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
 594                                          isr, (isr & USART_SR_TC),
 595                                          10, 100000);
 596
 597         if (ret)
 598                 dev_err(port->dev, "transmission complete not set\n");
 599
 600         stm32_clr_bits(port, ofs->cr1, val);
 601
 602         free_irq(port->irq, port);
 603 }
 604
 605 unsigned int stm32_get_databits(struct ktermios *termios)
 606 {
 607         unsigned int bits;
 608
 609         tcflag_t cflag = termios->c_cflag;
 610
 611         switch (cflag & CSIZE) {
 612         /*
 613          * CSIZE settings are not necessarily supported in hardware.
 614          * CSIZE unsupported configurations are handled here to set word length
 615          * to 8 bits word as default configuration and to print debug message.
 616          */
 617         case CS5:
 618                 bits = 5;
 619                 break;
 620         case CS6:
 621                 bits = 6;
 622                 break;
 623         case CS7:
 624                 bits = 7;
 625                 break;
 626         /* default including CS8 */
 627         default:
 628                 bits = 8;
 629                 break;
 630         }
 631
 632         return bits;
 633 }
 634
 635 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
 636                             struct ktermios *old)
 637 {
 638         struct stm32_port *stm32_port = to_stm32_port(port);
 639         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 640         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 641         struct serial_rs485 *rs485conf = &port->rs485;
 642         unsigned int baud, bits;
 643         u32 usartdiv, mantissa, fraction, oversampling;
 644         tcflag_t cflag = termios->c_cflag;
 645         u32 cr1, cr2, cr3, isr;
 646         unsigned long flags;
 647         int ret;
 648
 649         if (!stm32_port->hw_flow_control)
 650                 cflag &= ~CRTSCTS;
 651
 652         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 653
 654         spin_lock_irqsave(&port->lock, flags);
 655
 656         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 657                                                 isr,
 658                                                 (isr & USART_SR_TC),
 659                                                 10, 100000);
 660
 661         /* Send the TC error message only when ISR_TC is not set. */
 662         if (ret)
 663                 dev_err(port->dev, "Transmission is not complete\n");
 664
 665         /* Stop serial port and reset value */
 666         writel_relaxed(0, port->membase + ofs->cr1);
 667
 668         cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
 669
 670         if (stm32_port->fifoen)
 671                 cr1 |= USART_CR1_FIFOEN;
 672         cr2 = 0;
 673         cr3 = 0;
 674
 675         if (cflag & CSTOPB)
 676                 cr2 |= USART_CR2_STOP_2B;
 677
 678         bits = stm32_get_databits(termios);
 679         stm32_port->rdr_mask = (BIT(bits) - 1);
 680
 681         if (cflag & PARENB) {
 682                 bits++;
 683                 cr1 |= USART_CR1_PCE;
 684         }
 685
 686         /*
 687          * Word length configuration:
 688          * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
 689          * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
 690          * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
 691          * M0 and M1 already cleared by cr1 initialization.
 692          */
 693         if (bits == 9) {
 694                 cr1 |= USART_CR1_M0;
 695         } else if ((bits == 7) && cfg->has_7bits_data) {
 696                 cr1 |= USART_CR1_M1;
 697         } else if (bits != 8) {
 698                 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
 699                         , bits);
 700                 cflag &= ~CSIZE;
 701                 cflag |= CS8;
 702                 termios->c_cflag = cflag;
 703                 bits = 8;
 704                 if (cflag & PARENB) {
 705                         bits++;
 706                         cr1 |= USART_CR1_M0;
 707                 }
 708         }
 709
 710         if (cflag & PARODD)
 711                 cr1 |= USART_CR1_PS;
 712
 713         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
 714         if (cflag & CRTSCTS) {
 715                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 716                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
 717         }
 718
 719         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
 720
 721         /*
 722          * The USART supports 16 or 8 times oversampling.
 723          * By default we prefer 16 times oversampling, so that the receiver
 724          * has a better tolerance to clock deviations.
 725          * 8 times oversampling is only used to achieve higher speeds.
 726          */
 727         if (usartdiv < 16) {
 728                 oversampling = 8;
 729                 cr1 |= USART_CR1_OVER8;
 730                 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
 731         } else {
 732                 oversampling = 16;
 733                 cr1 &= ~USART_CR1_OVER8;
 734                 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
 735         }
 736
 737         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
 738         fraction = usartdiv % oversampling;
 739         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
 740
 741         uart_update_timeout(port, cflag, baud);
 742
 743         port->read_status_mask = USART_SR_ORE;
 744         if (termios->c_iflag & INPCK)
 745                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
 746         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 747                 port->read_status_mask |= USART_SR_FE;
 748
 749         /* Characters to ignore */
 750         port->ignore_status_mask = 0;
 751         if (termios->c_iflag & IGNPAR)
 752                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
 753         if (termios->c_iflag & IGNBRK) {
 754                 port->ignore_status_mask |= USART_SR_FE;
 755                 /*
 756                  * If we're ignoring parity and break indicators,
 757                  * ignore overruns too (for real raw support).
 758                  */
 759                 if (termios->c_iflag & IGNPAR)
 760                         port->ignore_status_mask |= USART_SR_ORE;
 761         }
 762
 763         /* Ignore all characters if CREAD is not set */
 764         if ((termios->c_cflag & CREAD) == 0)
 765                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
 766
 767         if (stm32_port->rx_ch)
 768                 cr3 |= USART_CR3_DMAR;
 769
 770         if (rs485conf->flags & SER_RS485_ENABLED) {
 771                 stm32_config_reg_rs485(&cr1, &cr3,
 772                                        rs485conf->delay_rts_before_send,
 773                                        rs485conf->delay_rts_after_send, baud);
 774                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 775                         cr3 &= ~USART_CR3_DEP;
 776                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 777                 } else {
 778                         cr3 |= USART_CR3_DEP;
 779                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 780                 }
 781
 782         } else {
 783                 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
 784                 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 785         }
 786
 787         writel_relaxed(cr3, port->membase + ofs->cr3);
 788         writel_relaxed(cr2, port->membase + ofs->cr2);
 789         writel_relaxed(cr1, port->membase + ofs->cr1);
 790
 791         stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 792         spin_unlock_irqrestore(&port->lock, flags);
 793 }
 794
 795 static const char *stm32_type(struct uart_port *port)
 796 {
 797         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
 798 }
 799
 800 static void stm32_release_port(struct uart_port *port)
 801 {
 802 }
 803
 804 static int stm32_request_port(struct uart_port *port)
 805 {
 806         return 0;
 807 }
 808
 809 static void stm32_config_port(struct uart_port *port, int flags)
 810 {
 811         if (flags & UART_CONFIG_TYPE)
 812                 port->type = PORT_STM32;
 813 }
 814
 815 static int
 816 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
 817 {
 818         /* No user changeable parameters */
 819         return -EINVAL;
 820 }
 821
 822 static void stm32_pm(struct uart_port *port, unsigned int state,
 823                 unsigned int oldstate)
 824 {
 825         struct stm32_port *stm32port = container_of(port,
 826                         struct stm32_port, port);
 827         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 828         struct stm32_usart_config *cfg = &stm32port->info->cfg;
 829         unsigned long flags = 0;
 830
 831         switch (state) {
 832         case UART_PM_STATE_ON:
 833                 clk_prepare_enable(stm32port->clk);
 834                 break;
 835         case UART_PM_STATE_OFF:
 836                 spin_lock_irqsave(&port->lock, flags);
 837                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 838                 spin_unlock_irqrestore(&port->lock, flags);
 839                 clk_disable_unprepare(stm32port->clk);
 840                 break;
 841         }
 842 }
 843
 844 static const struct uart_ops stm32_uart_ops = {
 845         .tx_empty       = stm32_tx_empty,
 846         .set_mctrl      = stm32_set_mctrl,
 847         .get_mctrl      = stm32_get_mctrl,
 848         .stop_tx        = stm32_stop_tx,
 849         .start_tx       = stm32_start_tx,
 850         .throttle       = stm32_throttle,
 851         .unthrottle     = stm32_unthrottle,
 852         .stop_rx        = stm32_stop_rx,
 853         .break_ctl      = stm32_break_ctl,
 854         .startup        = stm32_startup,
 855         .shutdown       = stm32_shutdown,
 856         .set_termios    = stm32_set_termios,
 857         .pm             = stm32_pm,
 858         .type           = stm32_type,
 859         .release_port   = stm32_release_port,
 860         .request_port   = stm32_request_port,
 861         .config_port    = stm32_config_port,
 862         .verify_port    = stm32_verify_port,
 863 };
 864
 865 static int stm32_init_port(struct stm32_port *stm32port,
 866                           struct platform_device *pdev)
 867 {
 868         struct uart_port *port = &stm32port->port;
 869         struct resource *res;
 870         int ret;
 871
 872         port->iotype    = UPIO_MEM;
 873         port->flags     = UPF_BOOT_AUTOCONF;
 874         port->ops       = &stm32_uart_ops;
 875         port->dev       = &pdev->dev;
 876         port->irq       = platform_get_irq(pdev, 0);
 877         port->rs485_config = stm32_config_rs485;
 878
 879         stm32_init_rs485(port, pdev);
 880
 881         stm32port->wakeirq = platform_get_irq(pdev, 1);
 882         stm32port->fifoen = stm32port->info->cfg.has_fifo;
 883
 884         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 885         port->membase = devm_ioremap_resource(&pdev->dev, res);
 886         if (IS_ERR(port->membase))
 887                 return PTR_ERR(port->membase);
 888         port->mapbase = res->start;
 889
 890         spin_lock_init(&port->lock);
 891
 892         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
 893         if (IS_ERR(stm32port->clk))
 894                 return PTR_ERR(stm32port->clk);
 895
 896         /* Ensure that clk rate is correct by enabling the clk */
 897         ret = clk_prepare_enable(stm32port->clk);
 898         if (ret)
 899                 return ret;
 900
 901         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
 902         if (!stm32port->port.uartclk) {
 903                 clk_disable_unprepare(stm32port->clk);
 904                 ret = -EINVAL;
 905         }
 906
 907         return ret;
 908 }
 909
 910 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
 911 {
 912         struct device_node *np = pdev->dev.of_node;
 913         int id;
 914
 915         if (!np)
 916                 return NULL;
 917
 918         id = of_alias_get_id(np, "serial");
 919         if (id < 0) {
 920                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
 921                 return NULL;
 922         }
 923
 924         if (WARN_ON(id >= STM32_MAX_PORTS))
 925                 return NULL;
 926
 927         stm32_ports[id].hw_flow_control = of_property_read_bool(np,
 928                                                         "st,hw-flow-ctrl");
 929         stm32_ports[id].port.line = id;
 930         stm32_ports[id].last_res = RX_BUF_L;
 931         return &stm32_ports[id];
 932 }
 933
 934 #ifdef CONFIG_OF
 935 static const struct of_device_id stm32_match[] = {
 936         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
 937         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
 938         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
 939         {},
 940 };
 941
 942 MODULE_DEVICE_TABLE(of, stm32_match);
 943 #endif
 944
 945 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
 946                                  struct platform_device *pdev)
 947 {
 948         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 949         struct uart_port *port = &stm32port->port;
 950         struct device *dev = &pdev->dev;
 951         struct dma_slave_config config;
 952         struct dma_async_tx_descriptor *desc = NULL;
 953         dma_cookie_t cookie;
 954         int ret;
 955
 956         /* Request DMA RX channel */
 957         stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
 958         if (!stm32port->rx_ch) {
 959                 dev_info(dev, "rx dma alloc failed\n");
 960                 return -ENODEV;
 961         }
 962         stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
 963                                                  &stm32port->rx_dma_buf,
 964                                                  GFP_KERNEL);
 965         if (!stm32port->rx_buf) {
 966                 ret = -ENOMEM;
 967                 goto alloc_err;
 968         }
 969
 970         /* Configure DMA channel */
 971         memset(&config, 0, sizeof(config));
 972         config.src_addr = port->mapbase + ofs->rdr;
 973         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 974
 975         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
 976         if (ret < 0) {
 977                 dev_err(dev, "rx dma channel config failed\n");
 978                 ret = -ENODEV;
 979                 goto config_err;
 980         }
 981
 982         /* Prepare a DMA cyclic transaction */
 983         desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
 984                                          stm32port->rx_dma_buf,
 985                                          RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
 986                                          DMA_PREP_INTERRUPT);
 987         if (!desc) {
 988                 dev_err(dev, "rx dma prep cyclic failed\n");
 989                 ret = -ENODEV;
 990                 goto config_err;
 991         }
 992
 993         /* No callback as dma buffer is drained on usart interrupt */
 994         desc->callback = NULL;
 995         desc->callback_param = NULL;
 996
 997         /* Push current DMA transaction in the pending queue */
 998         cookie = dmaengine_submit(desc);
 999
1000         /* Issue pending DMA requests */
1001         dma_async_issue_pending(stm32port->rx_ch);
1002
1003         return 0;
1004
1005 config_err:
1006         dma_free_coherent(&pdev->dev,
1007                           RX_BUF_L, stm32port->rx_buf,
1008                           stm32port->rx_dma_buf);
1009
1010 alloc_err:
1011         dma_release_channel(stm32port->rx_ch);
1012         stm32port->rx_ch = NULL;
1013
1014         return ret;
1015 }
1016
1017 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1018                                  struct platform_device *pdev)
1019 {
1020         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1021         struct uart_port *port = &stm32port->port;
1022         struct device *dev = &pdev->dev;
1023         struct dma_slave_config config;
1024         int ret;
1025
1026         stm32port->tx_dma_busy = false;
1027
1028         /* Request DMA TX channel */
1029         stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1030         if (!stm32port->tx_ch) {
1031                 dev_info(dev, "tx dma alloc failed\n");
1032                 return -ENODEV;
1033         }
1034         stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1035                                                  &stm32port->tx_dma_buf,
1036                                                  GFP_KERNEL);
1037         if (!stm32port->tx_buf) {
1038                 ret = -ENOMEM;
1039                 goto alloc_err;
1040         }
1041
1042         /* Configure DMA channel */
1043         memset(&config, 0, sizeof(config));
1044         config.dst_addr = port->mapbase + ofs->tdr;
1045         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1046
1047         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1048         if (ret < 0) {
1049                 dev_err(dev, "tx dma channel config failed\n");
1050                 ret = -ENODEV;
1051                 goto config_err;
1052         }
1053
1054         return 0;
1055
1056 config_err:
1057         dma_free_coherent(&pdev->dev,
1058                           TX_BUF_L, stm32port->tx_buf,
1059                           stm32port->tx_dma_buf);
1060
1061 alloc_err:
1062         dma_release_channel(stm32port->tx_ch);
1063         stm32port->tx_ch = NULL;
1064
1065         return ret;
1066 }
1067
1068 static int stm32_serial_probe(struct platform_device *pdev)
1069 {
1070         const struct of_device_id *match;
1071         struct stm32_port *stm32port;
1072         int ret;
1073
1074         stm32port = stm32_of_get_stm32_port(pdev);
1075         if (!stm32port)
1076                 return -ENODEV;
1077
1078         match = of_match_device(stm32_match, &pdev->dev);
1079         if (match && match->data)
1080                 stm32port->info = (struct stm32_usart_info *)match->data;
1081         else
1082                 return -EINVAL;
1083
1084         ret = stm32_init_port(stm32port, pdev);
1085         if (ret)
1086                 return ret;
1087
1088         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
1089                 ret = device_init_wakeup(&pdev->dev, true);
1090                 if (ret)
1091                         goto err_uninit;
1092
1093                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1094                                                     stm32port->wakeirq);
1095                 if (ret)
1096                         goto err_nowup;
1097
1098                 device_set_wakeup_enable(&pdev->dev, false);
1099         }
1100
1101         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1102         if (ret)
1103                 goto err_wirq;
1104
1105         ret = stm32_of_dma_rx_probe(stm32port, pdev);
1106         if (ret)
1107                 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1108
1109         ret = stm32_of_dma_tx_probe(stm32port, pdev);
1110         if (ret)
1111                 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1112
1113         platform_set_drvdata(pdev, &stm32port->port);
1114
1115         return 0;
1116
1117 err_wirq:
1118         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1119                 dev_pm_clear_wake_irq(&pdev->dev);
1120
1121 err_nowup:
1122         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1123                 device_init_wakeup(&pdev->dev, false);
1124
1125 err_uninit:
1126         clk_disable_unprepare(stm32port->clk);
1127
1128         return ret;
1129 }
1130
1131 static int stm32_serial_remove(struct platform_device *pdev)
1132 {
1133         struct uart_port *port = platform_get_drvdata(pdev);
1134         struct stm32_port *stm32_port = to_stm32_port(port);
1135         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1136         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1137
1138         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1139
1140         if (stm32_port->rx_ch)
1141                 dma_release_channel(stm32_port->rx_ch);
1142
1143         if (stm32_port->rx_dma_buf)
1144                 dma_free_coherent(&pdev->dev,
1145                                   RX_BUF_L, stm32_port->rx_buf,
1146                                   stm32_port->rx_dma_buf);
1147
1148         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1149
1150         if (stm32_port->tx_ch)
1151                 dma_release_channel(stm32_port->tx_ch);
1152
1153         if (stm32_port->tx_dma_buf)
1154                 dma_free_coherent(&pdev->dev,
1155                                   TX_BUF_L, stm32_port->tx_buf,
1156                                   stm32_port->tx_dma_buf);
1157
1158         if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
1159                 dev_pm_clear_wake_irq(&pdev->dev);
1160                 device_init_wakeup(&pdev->dev, false);
1161         }
1162
1163         clk_disable_unprepare(stm32_port->clk);
1164
1165         return uart_remove_one_port(&stm32_usart_driver, port);
1166 }
1167
1168
1169 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1170 static void stm32_console_putchar(struct uart_port *port, int ch)
1171 {
1172         struct stm32_port *stm32_port = to_stm32_port(port);
1173         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1174
1175         while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1176                 cpu_relax();
1177
1178         writel_relaxed(ch, port->membase + ofs->tdr);
1179 }
1180
1181 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1182 {
1183         struct uart_port *port = &stm32_ports[co->index].port;
1184         struct stm32_port *stm32_port = to_stm32_port(port);
1185         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1186         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1187         unsigned long flags;
1188         u32 old_cr1, new_cr1;
1189         int locked = 1;
1190
1191         local_irq_save(flags);
1192         if (port->sysrq)
1193                 locked = 0;
1194         else if (oops_in_progress)
1195                 locked = spin_trylock(&port->lock);
1196         else
1197                 spin_lock(&port->lock);
1198
1199         /* Save and disable interrupts, enable the transmitter */
1200         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1201         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1202         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1203         writel_relaxed(new_cr1, port->membase + ofs->cr1);
1204
1205         uart_console_write(port, s, cnt, stm32_console_putchar);
1206
1207         /* Restore interrupt state */
1208         writel_relaxed(old_cr1, port->membase + ofs->cr1);
1209
1210         if (locked)
1211                 spin_unlock(&port->lock);
1212         local_irq_restore(flags);
1213 }
1214
1215 static int stm32_console_setup(struct console *co, char *options)
1216 {
1217         struct stm32_port *stm32port;
1218         int baud = 9600;
1219         int bits = 8;
1220         int parity = 'n';
1221         int flow = 'n';
1222
1223         if (co->index >= STM32_MAX_PORTS)
1224                 return -ENODEV;
1225
1226         stm32port = &stm32_ports[co->index];
1227
1228         /*
1229          * This driver does not support early console initialization
1230          * (use ARM early printk support instead), so we only expect
1231          * this to be called during the uart port registration when the
1232          * driver gets probed and the port should be mapped at that point.
1233          */
1234         if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1235                 return -ENXIO;
1236
1237         if (options)
1238                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1239
1240         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1241 }
1242
1243 static struct console stm32_console = {
1244         .name           = STM32_SERIAL_NAME,
1245         .device         = uart_console_device,
1246         .write          = stm32_console_write,
1247         .setup          = stm32_console_setup,
1248         .flags          = CON_PRINTBUFFER,
1249         .index          = -1,
1250         .data           = &stm32_usart_driver,
1251 };
1252
1253 #define STM32_SERIAL_CONSOLE (&stm32_console)
1254
1255 #else
1256 #define STM32_SERIAL_CONSOLE NULL
1257 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1258
1259 static struct uart_driver stm32_usart_driver = {
1260         .driver_name    = DRIVER_NAME,
1261         .dev_name       = STM32_SERIAL_NAME,
1262         .major          = 0,
1263         .minor          = 0,
1264         .nr             = STM32_MAX_PORTS,
1265         .cons           = STM32_SERIAL_CONSOLE,
1266 };
1267
1268 #ifdef CONFIG_PM_SLEEP
1269 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1270 {
1271         struct stm32_port *stm32_port = to_stm32_port(port);
1272         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1273         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1274         u32 val;
1275
1276         if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1277                 return;
1278
1279         if (enable) {
1280                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1281                 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1282                 val = readl_relaxed(port->membase + ofs->cr3);
1283                 val &= ~USART_CR3_WUS_MASK;
1284                 /* Enable Wake up interrupt from low power on start bit */
1285                 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1286                 writel_relaxed(val, port->membase + ofs->cr3);
1287                 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1288         } else {
1289                 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1290         }
1291 }
1292
1293 static int stm32_serial_suspend(struct device *dev)
1294 {
1295         struct uart_port *port = dev_get_drvdata(dev);
1296
1297         uart_suspend_port(&stm32_usart_driver, port);
1298
1299         if (device_may_wakeup(dev))
1300                 stm32_serial_enable_wakeup(port, true);
1301         else
1302                 stm32_serial_enable_wakeup(port, false);
1303
1304         return 0;
1305 }
1306
1307 static int stm32_serial_resume(struct device *dev)
1308 {
1309         struct uart_port *port = dev_get_drvdata(dev);
1310
1311         if (device_may_wakeup(dev))
1312                 stm32_serial_enable_wakeup(port, false);
1313
1314         return uart_resume_port(&stm32_usart_driver, port);
1315 }
1316 #endif /* CONFIG_PM_SLEEP */
1317
1318 static const struct dev_pm_ops stm32_serial_pm_ops = {
1319         SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1320 };
1321
1322 static struct platform_driver stm32_serial_driver = {
1323         .probe          = stm32_serial_probe,
1324         .remove         = stm32_serial_remove,
1325         .driver = {
1326                 .name   = DRIVER_NAME,
1327                 .pm     = &stm32_serial_pm_ops,
1328                 .of_match_table = of_match_ptr(stm32_match),
1329         },
1330 };
1331
1332 static int __init usart_init(void)
1333 {
1334         static char banner[] __initdata = "STM32 USART driver initialized";
1335         int ret;
1336
1337         pr_info("%s\n", banner);
1338
1339         ret = uart_register_driver(&stm32_usart_driver);
1340         if (ret)
1341                 return ret;
1342
1343         ret = platform_driver_register(&stm32_serial_driver);
1344         if (ret)
1345                 uart_unregister_driver(&stm32_usart_driver);
1346
1347         return ret;
1348 }
1349
1350 static void __exit usart_exit(void)
1351 {
1352         platform_driver_unregister(&stm32_serial_driver);
1353         uart_unregister_driver(&stm32_usart_driver);
1354 }
1355
1356 module_init(usart_init);
1357 module_exit(usart_exit);
1358
1359 MODULE_ALIAS("platform:" DRIVER_NAME);
1360 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1361 MODULE_LICENSE("GPL v2");