drivers/tty/serial/stm32-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6  *           Gerald Baeza <gerald.baeza@foss.st.com>
   7  *           Erwan Le Ray <erwan.leray@foss.st.com>
   8  *
   9  * Inspired by st-asc.c from STMicroelectronics (c)
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/dma-direction.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/irq.h>
  21 #include <linux/module.h>
  22 #include <linux/of.h>
  23 #include <linux/of_platform.h>
  24 #include <linux/pinctrl/consumer.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/pm_wakeirq.h>
  28 #include <linux/serial_core.h>
  29 #include <linux/serial.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/sysrq.h>
  32 #include <linux/tty_flip.h>
  33 #include <linux/tty.h>
  34
  35 #include "serial_mctrl_gpio.h"
  36 #include "stm32-usart.h"
  37
  38
  39 /* Register offsets */
  40 static struct stm32_usart_info __maybe_unused stm32f4_info = {
  41         .ofs = {
  42                 .isr    = 0x00,
  43                 .rdr    = 0x04,
  44                 .tdr    = 0x04,
  45                 .brr    = 0x08,
  46                 .cr1    = 0x0c,
  47                 .cr2    = 0x10,
  48                 .cr3    = 0x14,
  49                 .gtpr   = 0x18,
  50                 .rtor   = UNDEF_REG,
  51                 .rqr    = UNDEF_REG,
  52                 .icr    = UNDEF_REG,
  53         },
  54         .cfg = {
  55                 .uart_enable_bit = 13,
  56                 .has_7bits_data = false,
  57                 .fifosize = 1,
  58         }
  59 };
  60
  61 static struct stm32_usart_info __maybe_unused stm32f7_info = {
  62         .ofs = {
  63                 .cr1    = 0x00,
  64                 .cr2    = 0x04,
  65                 .cr3    = 0x08,
  66                 .brr    = 0x0c,
  67                 .gtpr   = 0x10,
  68                 .rtor   = 0x14,
  69                 .rqr    = 0x18,
  70                 .isr    = 0x1c,
  71                 .icr    = 0x20,
  72                 .rdr    = 0x24,
  73                 .tdr    = 0x28,
  74         },
  75         .cfg = {
  76                 .uart_enable_bit = 0,
  77                 .has_7bits_data = true,
  78                 .has_swap = true,
  79                 .fifosize = 1,
  80         }
  81 };
  82
  83 static struct stm32_usart_info __maybe_unused stm32h7_info = {
  84         .ofs = {
  85                 .cr1    = 0x00,
  86                 .cr2    = 0x04,
  87                 .cr3    = 0x08,
  88                 .brr    = 0x0c,
  89                 .gtpr   = 0x10,
  90                 .rtor   = 0x14,
  91                 .rqr    = 0x18,
  92                 .isr    = 0x1c,
  93                 .icr    = 0x20,
  94                 .rdr    = 0x24,
  95                 .tdr    = 0x28,
  96         },
  97         .cfg = {
  98                 .uart_enable_bit = 0,
  99                 .has_7bits_data = true,
 100                 .has_swap = true,
 101                 .has_wakeup = true,
 102                 .has_fifo = true,
 103                 .fifosize = 16,
 104         }
 105 };
 106
 107 static void stm32_usart_stop_tx(struct uart_port *port);
 108 static void stm32_usart_transmit_chars(struct uart_port *port);
 109 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch);
 110
 111 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
 112 {
 113         return container_of(port, struct stm32_port, port);
 114 }
 115
 116 static void stm32_usart_set_bits(struct uart_port *port, u32 reg, u32 bits)
 117 {
 118         u32 val;
 119
 120         val = readl_relaxed(port->membase + reg);
 121         val |= bits;
 122         writel_relaxed(val, port->membase + reg);
 123 }
 124
 125 static void stm32_usart_clr_bits(struct uart_port *port, u32 reg, u32 bits)
 126 {
 127         u32 val;
 128
 129         val = readl_relaxed(port->membase + reg);
 130         val &= ~bits;
 131         writel_relaxed(val, port->membase + reg);
 132 }
 133
 134 static unsigned int stm32_usart_tx_empty(struct uart_port *port)
 135 {
 136         struct stm32_port *stm32_port = to_stm32_port(port);
 137         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 138
 139         if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
 140                 return TIOCSER_TEMT;
 141
 142         return 0;
 143 }
 144
 145 static void stm32_usart_rs485_rts_enable(struct uart_port *port)
 146 {
 147         struct stm32_port *stm32_port = to_stm32_port(port);
 148         struct serial_rs485 *rs485conf = &port->rs485;
 149
 150         if (stm32_port->hw_flow_control ||
 151             !(rs485conf->flags & SER_RS485_ENABLED))
 152                 return;
 153
 154         if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 155                 mctrl_gpio_set(stm32_port->gpios,
 156                                stm32_port->port.mctrl | TIOCM_RTS);
 157         } else {
 158                 mctrl_gpio_set(stm32_port->gpios,
 159                                stm32_port->port.mctrl & ~TIOCM_RTS);
 160         }
 161 }
 162
 163 static void stm32_usart_rs485_rts_disable(struct uart_port *port)
 164 {
 165         struct stm32_port *stm32_port = to_stm32_port(port);
 166         struct serial_rs485 *rs485conf = &port->rs485;
 167
 168         if (stm32_port->hw_flow_control ||
 169             !(rs485conf->flags & SER_RS485_ENABLED))
 170                 return;
 171
 172         if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 173                 mctrl_gpio_set(stm32_port->gpios,
 174                                stm32_port->port.mctrl & ~TIOCM_RTS);
 175         } else {
 176                 mctrl_gpio_set(stm32_port->gpios,
 177                                stm32_port->port.mctrl | TIOCM_RTS);
 178         }
 179 }
 180
 181 static void stm32_usart_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
 182                                          u32 delay_DDE, u32 baud)
 183 {
 184         u32 rs485_deat_dedt;
 185         u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
 186         bool over8;
 187
 188         *cr3 |= USART_CR3_DEM;
 189         over8 = *cr1 & USART_CR1_OVER8;
 190
 191         *cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 192
 193         if (over8)
 194                 rs485_deat_dedt = delay_ADE * baud * 8;
 195         else
 196                 rs485_deat_dedt = delay_ADE * baud * 16;
 197
 198         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
 199         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
 200                           rs485_deat_dedt_max : rs485_deat_dedt;
 201         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
 202                            USART_CR1_DEAT_MASK;
 203         *cr1 |= rs485_deat_dedt;
 204
 205         if (over8)
 206                 rs485_deat_dedt = delay_DDE * baud * 8;
 207         else
 208                 rs485_deat_dedt = delay_DDE * baud * 16;
 209
 210         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
 211         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
 212                           rs485_deat_dedt_max : rs485_deat_dedt;
 213         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
 214                            USART_CR1_DEDT_MASK;
 215         *cr1 |= rs485_deat_dedt;
 216 }
 217
 218 static int stm32_usart_config_rs485(struct uart_port *port, struct ktermios *termios,
 219                                     struct serial_rs485 *rs485conf)
 220 {
 221         struct stm32_port *stm32_port = to_stm32_port(port);
 222         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 223         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 224         u32 usartdiv, baud, cr1, cr3;
 225         bool over8;
 226
 227         stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 228
 229         if (rs485conf->flags & SER_RS485_ENABLED) {
 230                 cr1 = readl_relaxed(port->membase + ofs->cr1);
 231                 cr3 = readl_relaxed(port->membase + ofs->cr3);
 232                 usartdiv = readl_relaxed(port->membase + ofs->brr);
 233                 usartdiv = usartdiv & GENMASK(15, 0);
 234                 over8 = cr1 & USART_CR1_OVER8;
 235
 236                 if (over8)
 237                         usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
 238                                    << USART_BRR_04_R_SHIFT;
 239
 240                 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
 241                 stm32_usart_config_reg_rs485(&cr1, &cr3,
 242                                              rs485conf->delay_rts_before_send,
 243                                              rs485conf->delay_rts_after_send,
 244                                              baud);
 245
 246                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND)
 247                         cr3 &= ~USART_CR3_DEP;
 248                 else
 249                         cr3 |= USART_CR3_DEP;
 250
 251                 writel_relaxed(cr3, port->membase + ofs->cr3);
 252                 writel_relaxed(cr1, port->membase + ofs->cr1);
 253
 254                 if (!port->rs485_rx_during_tx_gpio)
 255                         rs485conf->flags |= SER_RS485_RX_DURING_TX;
 256
 257         } else {
 258                 stm32_usart_clr_bits(port, ofs->cr3,
 259                                      USART_CR3_DEM | USART_CR3_DEP);
 260                 stm32_usart_clr_bits(port, ofs->cr1,
 261                                      USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 262         }
 263
 264         stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 265
 266         /* Adjust RTS polarity in case it's driven in software */
 267         if (stm32_usart_tx_empty(port))
 268                 stm32_usart_rs485_rts_disable(port);
 269         else
 270                 stm32_usart_rs485_rts_enable(port);
 271
 272         return 0;
 273 }
 274
 275 static int stm32_usart_init_rs485(struct uart_port *port,
 276                                   struct platform_device *pdev)
 277 {
 278         struct serial_rs485 *rs485conf = &port->rs485;
 279
 280         rs485conf->flags = 0;
 281         rs485conf->delay_rts_before_send = 0;
 282         rs485conf->delay_rts_after_send = 0;
 283
 284         if (!pdev->dev.of_node)
 285                 return -ENODEV;
 286
 287         return uart_get_rs485_mode(port);
 288 }
 289
 290 static bool stm32_usart_rx_dma_started(struct stm32_port *stm32_port)
 291 {
 292         return stm32_port->rx_ch ? stm32_port->rx_dma_busy : false;
 293 }
 294
 295 static void stm32_usart_rx_dma_terminate(struct stm32_port *stm32_port)
 296 {
 297         dmaengine_terminate_async(stm32_port->rx_ch);
 298         stm32_port->rx_dma_busy = false;
 299 }
 300
 301 static int stm32_usart_dma_pause_resume(struct stm32_port *stm32_port,
 302                                         struct dma_chan *chan,
 303                                         enum dma_status expected_status,
 304                                         int dmaengine_pause_or_resume(struct dma_chan *),
 305                                         bool stm32_usart_xx_dma_started(struct stm32_port *),
 306                                         void stm32_usart_xx_dma_terminate(struct stm32_port *))
 307 {
 308         struct uart_port *port = &stm32_port->port;
 309         enum dma_status dma_status;
 310         int ret;
 311
 312         if (!stm32_usart_xx_dma_started(stm32_port))
 313                 return -EPERM;
 314
 315         dma_status = dmaengine_tx_status(chan, chan->cookie, NULL);
 316         if (dma_status != expected_status)
 317                 return -EAGAIN;
 318
 319         ret = dmaengine_pause_or_resume(chan);
 320         if (ret) {
 321                 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
 322                 stm32_usart_xx_dma_terminate(stm32_port);
 323         }
 324         return ret;
 325 }
 326
 327 static int stm32_usart_rx_dma_pause(struct stm32_port *stm32_port)
 328 {
 329         return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
 330                                             DMA_IN_PROGRESS, dmaengine_pause,
 331                                             stm32_usart_rx_dma_started,
 332                                             stm32_usart_rx_dma_terminate);
 333 }
 334
 335 static int stm32_usart_rx_dma_resume(struct stm32_port *stm32_port)
 336 {
 337         return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
 338                                             DMA_PAUSED, dmaengine_resume,
 339                                             stm32_usart_rx_dma_started,
 340                                             stm32_usart_rx_dma_terminate);
 341 }
 342
 343 /* Return true when data is pending (in pio mode), and false when no data is pending. */
 344 static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr)
 345 {
 346         struct stm32_port *stm32_port = to_stm32_port(port);
 347         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 348
 349         *sr = readl_relaxed(port->membase + ofs->isr);
 350         /* Get pending characters in RDR or FIFO */
 351         if (*sr & USART_SR_RXNE) {
 352                 /* Get all pending characters from the RDR or the FIFO when using interrupts */
 353                 if (!stm32_usart_rx_dma_started(stm32_port))
 354                         return true;
 355
 356                 /* Handle only RX data errors when using DMA */
 357                 if (*sr & USART_SR_ERR_MASK)
 358                         return true;
 359         }
 360
 361         return false;
 362 }
 363
 364 static u8 stm32_usart_get_char_pio(struct uart_port *port)
 365 {
 366         struct stm32_port *stm32_port = to_stm32_port(port);
 367         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 368         unsigned long c;
 369
 370         c = readl_relaxed(port->membase + ofs->rdr);
 371         /* Apply RDR data mask */
 372         c &= stm32_port->rdr_mask;
 373
 374         return c;
 375 }
 376
 377 static unsigned int stm32_usart_receive_chars_pio(struct uart_port *port)
 378 {
 379         struct stm32_port *stm32_port = to_stm32_port(port);
 380         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 381         unsigned int size = 0;
 382         u32 sr;
 383         u8 c, flag;
 384
 385         while (stm32_usart_pending_rx_pio(port, &sr)) {
 386                 sr |= USART_SR_DUMMY_RX;
 387                 flag = TTY_NORMAL;
 388
 389                 /*
 390                  * Status bits has to be cleared before reading the RDR:
 391                  * In FIFO mode, reading the RDR will pop the next data
 392                  * (if any) along with its status bits into the SR.
 393                  * Not doing so leads to misalignement between RDR and SR,
 394                  * and clear status bits of the next rx data.
 395                  *
 396                  * Clear errors flags for stm32f7 and stm32h7 compatible
 397                  * devices. On stm32f4 compatible devices, the error bit is
 398                  * cleared by the sequence [read SR - read DR].
 399                  */
 400                 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
 401                         writel_relaxed(sr & USART_SR_ERR_MASK,
 402                                        port->membase + ofs->icr);
 403
 404                 c = stm32_usart_get_char_pio(port);
 405                 port->icount.rx++;
 406                 size++;
 407                 if (sr & USART_SR_ERR_MASK) {
 408                         if (sr & USART_SR_ORE) {
 409                                 port->icount.overrun++;
 410                         } else if (sr & USART_SR_PE) {
 411                                 port->icount.parity++;
 412                         } else if (sr & USART_SR_FE) {
 413                                 /* Break detection if character is null */
 414                                 if (!c) {
 415                                         port->icount.brk++;
 416                                         if (uart_handle_break(port))
 417                                                 continue;
 418                                 } else {
 419                                         port->icount.frame++;
 420                                 }
 421                         }
 422
 423                         sr &= port->read_status_mask;
 424
 425                         if (sr & USART_SR_PE) {
 426                                 flag = TTY_PARITY;
 427                         } else if (sr & USART_SR_FE) {
 428                                 if (!c)
 429                                         flag = TTY_BREAK;
 430                                 else
 431                                         flag = TTY_FRAME;
 432                         }
 433                 }
 434
 435                 if (uart_prepare_sysrq_char(port, c))
 436                         continue;
 437                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 438         }
 439
 440         return size;
 441 }
 442
 443 static void stm32_usart_push_buffer_dma(struct uart_port *port, unsigned int dma_size)
 444 {
 445         struct stm32_port *stm32_port = to_stm32_port(port);
 446         struct tty_port *ttyport = &stm32_port->port.state->port;
 447         unsigned char *dma_start;
 448         int dma_count, i;
 449
 450         dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res);
 451
 452         /*
 453          * Apply rdr_mask on buffer in order to mask parity bit.
 454          * This loop is useless in cs8 mode because DMA copies only
 455          * 8 bits and already ignores parity bit.
 456          */
 457         if (!(stm32_port->rdr_mask == (BIT(8) - 1)))
 458                 for (i = 0; i < dma_size; i++)
 459                         *(dma_start + i) &= stm32_port->rdr_mask;
 460
 461         dma_count = tty_insert_flip_string(ttyport, dma_start, dma_size);
 462         port->icount.rx += dma_count;
 463         if (dma_count != dma_size)
 464                 port->icount.buf_overrun++;
 465         stm32_port->last_res -= dma_count;
 466         if (stm32_port->last_res == 0)
 467                 stm32_port->last_res = RX_BUF_L;
 468 }
 469
 470 static unsigned int stm32_usart_receive_chars_dma(struct uart_port *port)
 471 {
 472         struct stm32_port *stm32_port = to_stm32_port(port);
 473         unsigned int dma_size, size = 0;
 474
 475         /* DMA buffer is configured in cyclic mode and handles the rollback of the buffer. */
 476         if (stm32_port->rx_dma_state.residue > stm32_port->last_res) {
 477                 /* Conditional first part: from last_res to end of DMA buffer */
 478                 dma_size = stm32_port->last_res;
 479                 stm32_usart_push_buffer_dma(port, dma_size);
 480                 size = dma_size;
 481         }
 482
 483         dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue;
 484         stm32_usart_push_buffer_dma(port, dma_size);
 485         size += dma_size;
 486
 487         return size;
 488 }
 489
 490 static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force_dma_flush)
 491 {
 492         struct stm32_port *stm32_port = to_stm32_port(port);
 493         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 494         enum dma_status rx_dma_status;
 495         u32 sr;
 496         unsigned int size = 0;
 497
 498         if (stm32_usart_rx_dma_started(stm32_port) || force_dma_flush) {
 499                 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
 500                                                     stm32_port->rx_ch->cookie,
 501                                                     &stm32_port->rx_dma_state);
 502                 if (rx_dma_status == DMA_IN_PROGRESS ||
 503                     rx_dma_status == DMA_PAUSED) {
 504                         /* Empty DMA buffer */
 505                         size = stm32_usart_receive_chars_dma(port);
 506                         sr = readl_relaxed(port->membase + ofs->isr);
 507                         if (sr & USART_SR_ERR_MASK) {
 508                                 /* Disable DMA request line */
 509                                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
 510
 511                                 /* Switch to PIO mode to handle the errors */
 512                                 size += stm32_usart_receive_chars_pio(port);
 513
 514                                 /* Switch back to DMA mode */
 515                                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
 516                         }
 517                 } else {
 518                         /* Disable RX DMA */
 519                         stm32_usart_rx_dma_terminate(stm32_port);
 520                         /* Fall back to interrupt mode */
 521                         dev_dbg(port->dev, "DMA error, fallback to irq mode\n");
 522                         size = stm32_usart_receive_chars_pio(port);
 523                 }
 524         } else {
 525                 size = stm32_usart_receive_chars_pio(port);
 526         }
 527
 528         return size;
 529 }
 530
 531 static void stm32_usart_rx_dma_complete(void *arg)
 532 {
 533         struct uart_port *port = arg;
 534         struct tty_port *tport = &port->state->port;
 535         unsigned int size;
 536         unsigned long flags;
 537
 538         uart_port_lock_irqsave(port, &flags);
 539         size = stm32_usart_receive_chars(port, false);
 540         uart_unlock_and_check_sysrq_irqrestore(port, flags);
 541         if (size)
 542                 tty_flip_buffer_push(tport);
 543 }
 544
 545 static int stm32_usart_rx_dma_start_or_resume(struct uart_port *port)
 546 {
 547         struct stm32_port *stm32_port = to_stm32_port(port);
 548         struct dma_async_tx_descriptor *desc;
 549         enum dma_status rx_dma_status;
 550         int ret;
 551
 552         if (stm32_port->throttled)
 553                 return 0;
 554
 555         if (stm32_port->rx_dma_busy) {
 556                 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
 557                                                     stm32_port->rx_ch->cookie,
 558                                                     NULL);
 559                 if (rx_dma_status == DMA_IN_PROGRESS)
 560                         return 0;
 561
 562                 if (rx_dma_status == DMA_PAUSED && !stm32_usart_rx_dma_resume(stm32_port))
 563                         return 0;
 564
 565                 dev_err(port->dev, "DMA failed : status error.\n");
 566                 stm32_usart_rx_dma_terminate(stm32_port);
 567         }
 568
 569         stm32_port->rx_dma_busy = true;
 570
 571         stm32_port->last_res = RX_BUF_L;
 572         /* Prepare a DMA cyclic transaction */
 573         desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch,
 574                                          stm32_port->rx_dma_buf,
 575                                          RX_BUF_L, RX_BUF_P,
 576                                          DMA_DEV_TO_MEM,
 577                                          DMA_PREP_INTERRUPT);
 578         if (!desc) {
 579                 dev_err(port->dev, "rx dma prep cyclic failed\n");
 580                 stm32_port->rx_dma_busy = false;
 581                 return -ENODEV;
 582         }
 583
 584         desc->callback = stm32_usart_rx_dma_complete;
 585         desc->callback_param = port;
 586
 587         /* Push current DMA transaction in the pending queue */
 588         ret = dma_submit_error(dmaengine_submit(desc));
 589         if (ret) {
 590                 dmaengine_terminate_sync(stm32_port->rx_ch);
 591                 stm32_port->rx_dma_busy = false;
 592                 return ret;
 593         }
 594
 595         /* Issue pending DMA requests */
 596         dma_async_issue_pending(stm32_port->rx_ch);
 597
 598         return 0;
 599 }
 600
 601 static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port)
 602 {
 603         dmaengine_terminate_async(stm32_port->tx_ch);
 604         stm32_port->tx_dma_busy = false;
 605 }
 606
 607 static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port)
 608 {
 609         /*
 610          * We cannot use the function "dmaengine_tx_status" to know the
 611          * status of DMA. This function does not show if the "dma complete"
 612          * callback of the DMA transaction has been called. So we prefer
 613          * to use "tx_dma_busy" flag to prevent dual DMA transaction at the
 614          * same time.
 615          */
 616         return stm32_port->tx_dma_busy;
 617 }
 618
 619 static int stm32_usart_tx_dma_pause(struct stm32_port *stm32_port)
 620 {
 621         return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch,
 622                                             DMA_IN_PROGRESS, dmaengine_pause,
 623                                             stm32_usart_tx_dma_started,
 624                                             stm32_usart_tx_dma_terminate);
 625 }
 626
 627 static int stm32_usart_tx_dma_resume(struct stm32_port *stm32_port)
 628 {
 629         return stm32_usart_dma_pause_resume(stm32_port, stm32_port->tx_ch,
 630                                             DMA_PAUSED, dmaengine_resume,
 631                                             stm32_usart_tx_dma_started,
 632                                             stm32_usart_tx_dma_terminate);
 633 }
 634
 635 static void stm32_usart_tx_dma_complete(void *arg)
 636 {
 637         struct uart_port *port = arg;
 638         struct stm32_port *stm32port = to_stm32_port(port);
 639         unsigned long flags;
 640
 641         stm32_usart_tx_dma_terminate(stm32port);
 642
 643         /* Let's see if we have pending data to send */
 644         uart_port_lock_irqsave(port, &flags);
 645         stm32_usart_transmit_chars(port);
 646         uart_port_unlock_irqrestore(port, flags);
 647 }
 648
 649 static void stm32_usart_tx_interrupt_enable(struct uart_port *port)
 650 {
 651         struct stm32_port *stm32_port = to_stm32_port(port);
 652         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 653
 654         /*
 655          * Enables TX FIFO threashold irq when FIFO is enabled,
 656          * or TX empty irq when FIFO is disabled
 657          */
 658         if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
 659                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE);
 660         else
 661                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 662 }
 663
 664 static void stm32_usart_tc_interrupt_enable(struct uart_port *port)
 665 {
 666         struct stm32_port *stm32_port = to_stm32_port(port);
 667         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 668
 669         stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE);
 670 }
 671
 672 static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
 673 {
 674         struct stm32_port *stm32_port = to_stm32_port(port);
 675         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 676
 677         if (stm32_port->fifoen && stm32_port->txftcfg >= 0)
 678                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE);
 679         else
 680                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 681 }
 682
 683 static void stm32_usart_tc_interrupt_disable(struct uart_port *port)
 684 {
 685         struct stm32_port *stm32_port = to_stm32_port(port);
 686         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 687
 688         stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE);
 689 }
 690
 691 static void stm32_usart_transmit_chars_pio(struct uart_port *port)
 692 {
 693         struct stm32_port *stm32_port = to_stm32_port(port);
 694         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 695         struct circ_buf *xmit = &port->state->xmit;
 696
 697         while (!uart_circ_empty(xmit)) {
 698                 /* Check that TDR is empty before filling FIFO */
 699                 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
 700                         break;
 701                 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 702                 uart_xmit_advance(port, 1);
 703         }
 704
 705         /* rely on TXE irq (mask or unmask) for sending remaining data */
 706         if (uart_circ_empty(xmit))
 707                 stm32_usart_tx_interrupt_disable(port);
 708         else
 709                 stm32_usart_tx_interrupt_enable(port);
 710 }
 711
 712 static void stm32_usart_transmit_chars_dma(struct uart_port *port)
 713 {
 714         struct stm32_port *stm32port = to_stm32_port(port);
 715         struct circ_buf *xmit = &port->state->xmit;
 716         struct dma_async_tx_descriptor *desc = NULL;
 717         unsigned int count;
 718         int ret;
 719
 720         if (stm32_usart_tx_dma_started(stm32port)) {
 721                 ret = stm32_usart_tx_dma_resume(stm32port);
 722                 if (ret < 0 && ret != -EAGAIN)
 723                         goto fallback_err;
 724                 return;
 725         }
 726
 727         count = uart_circ_chars_pending(xmit);
 728
 729         if (count > TX_BUF_L)
 730                 count = TX_BUF_L;
 731
 732         if (xmit->tail < xmit->head) {
 733                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 734         } else {
 735                 size_t one = UART_XMIT_SIZE - xmit->tail;
 736                 size_t two;
 737
 738                 if (one > count)
 739                         one = count;
 740                 two = count - one;
 741
 742                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 743                 if (two)
 744                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 745         }
 746
 747         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 748                                            stm32port->tx_dma_buf,
 749                                            count,
 750                                            DMA_MEM_TO_DEV,
 751                                            DMA_PREP_INTERRUPT);
 752
 753         if (!desc)
 754                 goto fallback_err;
 755
 756         /*
 757          * Set "tx_dma_busy" flag. This flag will be released when
 758          * dmaengine_terminate_async will be called. This flag helps
 759          * transmit_chars_dma not to start another DMA transaction
 760          * if the callback of the previous is not yet called.
 761          */
 762         stm32port->tx_dma_busy = true;
 763
 764         desc->callback = stm32_usart_tx_dma_complete;
 765         desc->callback_param = port;
 766
 767         /* Push current DMA TX transaction in the pending queue */
 768         /* DMA no yet started, safe to free resources */
 769         ret = dma_submit_error(dmaengine_submit(desc));
 770         if (ret) {
 771                 dev_err(port->dev, "DMA failed with error code: %d\n", ret);
 772                 stm32_usart_tx_dma_terminate(stm32port);
 773                 goto fallback_err;
 774         }
 775
 776         /* Issue pending DMA TX requests */
 777         dma_async_issue_pending(stm32port->tx_ch);
 778
 779         uart_xmit_advance(port, count);
 780
 781         return;
 782
 783 fallback_err:
 784         stm32_usart_transmit_chars_pio(port);
 785 }
 786
 787 static void stm32_usart_transmit_chars(struct uart_port *port)
 788 {
 789         struct stm32_port *stm32_port = to_stm32_port(port);
 790         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 791         struct circ_buf *xmit = &port->state->xmit;
 792         u32 isr;
 793         int ret;
 794
 795         if (!stm32_port->hw_flow_control &&
 796             port->rs485.flags & SER_RS485_ENABLED &&
 797             (port->x_char ||
 798              !(uart_circ_empty(xmit) || uart_tx_stopped(port)))) {
 799                 stm32_usart_tc_interrupt_disable(port);
 800                 stm32_usart_rs485_rts_enable(port);
 801         }
 802
 803         if (port->x_char) {
 804                 /* dma terminate may have been called in case of dma pause failure */
 805                 stm32_usart_tx_dma_pause(stm32_port);
 806
 807                 /* Check that TDR is empty before filling FIFO */
 808                 ret =
 809                 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 810                                                   isr,
 811                                                   (isr & USART_SR_TXE),
 812                                                   10, 1000);
 813                 if (ret)
 814                         dev_warn(port->dev, "1 character may be erased\n");
 815
 816                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 817                 port->x_char = 0;
 818                 port->icount.tx++;
 819
 820                 /* dma terminate may have been called in case of dma resume failure */
 821                 stm32_usart_tx_dma_resume(stm32_port);
 822                 return;
 823         }
 824
 825         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 826                 stm32_usart_tx_interrupt_disable(port);
 827                 return;
 828         }
 829
 830         if (ofs->icr == UNDEF_REG)
 831                 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC);
 832         else
 833                 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
 834
 835         if (stm32_port->tx_ch)
 836                 stm32_usart_transmit_chars_dma(port);
 837         else
 838                 stm32_usart_transmit_chars_pio(port);
 839
 840         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 841                 uart_write_wakeup(port);
 842
 843         if (uart_circ_empty(xmit)) {
 844                 stm32_usart_tx_interrupt_disable(port);
 845                 if (!stm32_port->hw_flow_control &&
 846                     port->rs485.flags & SER_RS485_ENABLED) {
 847                         stm32_usart_tc_interrupt_enable(port);
 848                 }
 849         }
 850 }
 851
 852 static irqreturn_t stm32_usart_interrupt(int irq, void *ptr)
 853 {
 854         struct uart_port *port = ptr;
 855         struct tty_port *tport = &port->state->port;
 856         struct stm32_port *stm32_port = to_stm32_port(port);
 857         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 858         u32 sr;
 859         unsigned int size;
 860         irqreturn_t ret = IRQ_NONE;
 861
 862         sr = readl_relaxed(port->membase + ofs->isr);
 863
 864         if (!stm32_port->hw_flow_control &&
 865             port->rs485.flags & SER_RS485_ENABLED &&
 866             (sr & USART_SR_TC)) {
 867                 stm32_usart_tc_interrupt_disable(port);
 868                 stm32_usart_rs485_rts_disable(port);
 869                 ret = IRQ_HANDLED;
 870         }
 871
 872         if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) {
 873                 writel_relaxed(USART_ICR_RTOCF,
 874                                port->membase + ofs->icr);
 875                 ret = IRQ_HANDLED;
 876         }
 877
 878         if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) {
 879                 /* Clear wake up flag and disable wake up interrupt */
 880                 writel_relaxed(USART_ICR_WUCF,
 881                                port->membase + ofs->icr);
 882                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
 883                 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 884                         pm_wakeup_event(tport->tty->dev, 0);
 885                 ret = IRQ_HANDLED;
 886         }
 887
 888         /*
 889          * rx errors in dma mode has to be handled ASAP to avoid overrun as the DMA request
 890          * line has been masked by HW and rx data are stacking in FIFO.
 891          */
 892         if (!stm32_port->throttled) {
 893                 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_started(stm32_port)) ||
 894                     ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_started(stm32_port))) {
 895                         uart_port_lock(port);
 896                         size = stm32_usart_receive_chars(port, false);
 897                         uart_unlock_and_check_sysrq(port);
 898                         if (size)
 899                                 tty_flip_buffer_push(tport);
 900                         ret = IRQ_HANDLED;
 901                 }
 902         }
 903
 904         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) {
 905                 uart_port_lock(port);
 906                 stm32_usart_transmit_chars(port);
 907                 uart_port_unlock(port);
 908                 ret = IRQ_HANDLED;
 909         }
 910
 911         /* Receiver timeout irq for DMA RX */
 912         if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) {
 913                 uart_port_lock(port);
 914                 size = stm32_usart_receive_chars(port, false);
 915                 uart_unlock_and_check_sysrq(port);
 916                 if (size)
 917                         tty_flip_buffer_push(tport);
 918                 ret = IRQ_HANDLED;
 919         }
 920
 921         return ret;
 922 }
 923
 924 static void stm32_usart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 925 {
 926         struct stm32_port *stm32_port = to_stm32_port(port);
 927         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 928
 929         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 930                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 931         else
 932                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 933
 934         mctrl_gpio_set(stm32_port->gpios, mctrl);
 935 }
 936
 937 static unsigned int stm32_usart_get_mctrl(struct uart_port *port)
 938 {
 939         struct stm32_port *stm32_port = to_stm32_port(port);
 940         unsigned int ret;
 941
 942         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 943         ret = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 944
 945         return mctrl_gpio_get(stm32_port->gpios, &ret);
 946 }
 947
 948 static void stm32_usart_enable_ms(struct uart_port *port)
 949 {
 950         mctrl_gpio_enable_ms(to_stm32_port(port)->gpios);
 951 }
 952
 953 static void stm32_usart_disable_ms(struct uart_port *port)
 954 {
 955         mctrl_gpio_disable_ms(to_stm32_port(port)->gpios);
 956 }
 957
 958 /* Transmit stop */
 959 static void stm32_usart_stop_tx(struct uart_port *port)
 960 {
 961         struct stm32_port *stm32_port = to_stm32_port(port);
 962
 963         stm32_usart_tx_interrupt_disable(port);
 964
 965         /* dma terminate may have been called in case of dma pause failure */
 966         stm32_usart_tx_dma_pause(stm32_port);
 967
 968         stm32_usart_rs485_rts_disable(port);
 969 }
 970
 971 /* There are probably characters waiting to be transmitted. */
 972 static void stm32_usart_start_tx(struct uart_port *port)
 973 {
 974         struct circ_buf *xmit = &port->state->xmit;
 975
 976         if (uart_circ_empty(xmit) && !port->x_char) {
 977                 stm32_usart_rs485_rts_disable(port);
 978                 return;
 979         }
 980
 981         stm32_usart_rs485_rts_enable(port);
 982
 983         stm32_usart_transmit_chars(port);
 984 }
 985
 986 /* Flush the transmit buffer. */
 987 static void stm32_usart_flush_buffer(struct uart_port *port)
 988 {
 989         struct stm32_port *stm32_port = to_stm32_port(port);
 990
 991         if (stm32_port->tx_ch)
 992                 stm32_usart_tx_dma_terminate(stm32_port);
 993 }
 994
 995 /* Throttle the remote when input buffer is about to overflow. */
 996 static void stm32_usart_throttle(struct uart_port *port)
 997 {
 998         struct stm32_port *stm32_port = to_stm32_port(port);
 999         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1000         unsigned long flags;
1001
1002         uart_port_lock_irqsave(port, &flags);
1003
1004         /*
1005          * Pause DMA transfer, so the RX data gets queued into the FIFO.
1006          * Hardware flow control is triggered when RX FIFO is full.
1007          */
1008         stm32_usart_rx_dma_pause(stm32_port);
1009
1010         stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1011         if (stm32_port->cr3_irq)
1012                 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
1013
1014         stm32_port->throttled = true;
1015         uart_port_unlock_irqrestore(port, flags);
1016 }
1017
1018 /* Unthrottle the remote, the input buffer can now accept data. */
1019 static void stm32_usart_unthrottle(struct uart_port *port)
1020 {
1021         struct stm32_port *stm32_port = to_stm32_port(port);
1022         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1023         unsigned long flags;
1024
1025         uart_port_lock_irqsave(port, &flags);
1026         stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq);
1027         if (stm32_port->cr3_irq)
1028                 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
1029
1030         stm32_port->throttled = false;
1031
1032         /*
1033          * Switch back to DMA mode (resume DMA).
1034          * Hardware flow control is stopped when FIFO is not full any more.
1035          */
1036         if (stm32_port->rx_ch)
1037                 stm32_usart_rx_dma_start_or_resume(port);
1038
1039         uart_port_unlock_irqrestore(port, flags);
1040 }
1041
1042 /* Receive stop */
1043 static void stm32_usart_stop_rx(struct uart_port *port)
1044 {
1045         struct stm32_port *stm32_port = to_stm32_port(port);
1046         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1047
1048         /* Disable DMA request line. */
1049         stm32_usart_rx_dma_pause(stm32_port);
1050
1051         stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
1052         if (stm32_port->cr3_irq)
1053                 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq);
1054 }
1055
1056 static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
1057 {
1058         struct stm32_port *stm32_port = to_stm32_port(port);
1059         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1060         unsigned long flags;
1061
1062         spin_lock_irqsave(&port->lock, flags);
1063
1064         if (break_state)
1065                 stm32_usart_set_bits(port, ofs->rqr, USART_RQR_SBKRQ);
1066         else
1067                 stm32_usart_clr_bits(port, ofs->rqr, USART_RQR_SBKRQ);
1068
1069         spin_unlock_irqrestore(&port->lock, flags);
1070 }
1071
1072 static int stm32_usart_startup(struct uart_port *port)
1073 {
1074         struct stm32_port *stm32_port = to_stm32_port(port);
1075         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1076         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1077         const char *name = to_platform_device(port->dev)->name;
1078         u32 val;
1079         int ret;
1080
1081         ret = request_irq(port->irq, stm32_usart_interrupt,
1082                           IRQF_NO_SUSPEND, name, port);
1083         if (ret)
1084                 return ret;
1085
1086         if (stm32_port->swap) {
1087                 val = readl_relaxed(port->membase + ofs->cr2);
1088                 val |= USART_CR2_SWAP;
1089                 writel_relaxed(val, port->membase + ofs->cr2);
1090         }
1091         stm32_port->throttled = false;
1092
1093         /* RX FIFO Flush */
1094         if (ofs->rqr != UNDEF_REG)
1095                 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
1096
1097         if (stm32_port->rx_ch) {
1098                 ret = stm32_usart_rx_dma_start_or_resume(port);
1099                 if (ret) {
1100                         free_irq(port->irq, port);
1101                         return ret;
1102                 }
1103         }
1104
1105         /* RX enabling */
1106         val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit);
1107         stm32_usart_set_bits(port, ofs->cr1, val);
1108
1109         return 0;
1110 }
1111
1112 static void stm32_usart_shutdown(struct uart_port *port)
1113 {
1114         struct stm32_port *stm32_port = to_stm32_port(port);
1115         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1116         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1117         u32 val, isr;
1118         int ret;
1119
1120         if (stm32_usart_tx_dma_started(stm32_port))
1121                 stm32_usart_tx_dma_terminate(stm32_port);
1122
1123         if (stm32_port->tx_ch)
1124                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1125
1126         /* Disable modem control interrupts */
1127         stm32_usart_disable_ms(port);
1128
1129         val = USART_CR1_TXEIE | USART_CR1_TE;
1130         val |= stm32_port->cr1_irq | USART_CR1_RE;
1131         val |= BIT(cfg->uart_enable_bit);
1132         if (stm32_port->fifoen)
1133                 val |= USART_CR1_FIFOEN;
1134
1135         ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
1136                                          isr, (isr & USART_SR_TC),
1137                                          10, 100000);
1138
1139         /* Send the TC error message only when ISR_TC is not set */
1140         if (ret)
1141                 dev_err(port->dev, "Transmission is not complete\n");
1142
1143         /* Disable RX DMA. */
1144         if (stm32_port->rx_ch) {
1145                 stm32_usart_rx_dma_terminate(stm32_port);
1146                 dmaengine_synchronize(stm32_port->rx_ch);
1147         }
1148
1149         /* flush RX & TX FIFO */
1150         if (ofs->rqr != UNDEF_REG)
1151                 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
1152                                port->membase + ofs->rqr);
1153
1154         stm32_usart_clr_bits(port, ofs->cr1, val);
1155
1156         free_irq(port->irq, port);
1157 }
1158
1159 static void stm32_usart_set_termios(struct uart_port *port,
1160                                     struct ktermios *termios,
1161                                     const struct ktermios *old)
1162 {
1163         struct stm32_port *stm32_port = to_stm32_port(port);
1164         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1165         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1166         struct serial_rs485 *rs485conf = &port->rs485;
1167         unsigned int baud, bits;
1168         u32 usartdiv, mantissa, fraction, oversampling;
1169         tcflag_t cflag = termios->c_cflag;
1170         u32 cr1, cr2, cr3, isr;
1171         unsigned long flags;
1172         int ret;
1173
1174         if (!stm32_port->hw_flow_control)
1175                 cflag &= ~CRTSCTS;
1176
1177         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
1178
1179         uart_port_lock_irqsave(port, &flags);
1180
1181         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
1182                                                 isr,
1183                                                 (isr & USART_SR_TC),
1184                                                 10, 100000);
1185
1186         /* Send the TC error message only when ISR_TC is not set. */
1187         if (ret)
1188                 dev_err(port->dev, "Transmission is not complete\n");
1189
1190         /* Stop serial port and reset value */
1191         writel_relaxed(0, port->membase + ofs->cr1);
1192
1193         /* flush RX & TX FIFO */
1194         if (ofs->rqr != UNDEF_REG)
1195                 writel_relaxed(USART_RQR_TXFRQ | USART_RQR_RXFRQ,
1196                                port->membase + ofs->rqr);
1197
1198         cr1 = USART_CR1_TE | USART_CR1_RE;
1199         if (stm32_port->fifoen)
1200                 cr1 |= USART_CR1_FIFOEN;
1201         cr2 = stm32_port->swap ? USART_CR2_SWAP : 0;
1202
1203         /* Tx and RX FIFO configuration */
1204         cr3 = readl_relaxed(port->membase + ofs->cr3);
1205         cr3 &= USART_CR3_TXFTIE | USART_CR3_RXFTIE;
1206         if (stm32_port->fifoen) {
1207                 if (stm32_port->txftcfg >= 0)
1208                         cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT;
1209                 if (stm32_port->rxftcfg >= 0)
1210                         cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT;
1211         }
1212
1213         if (cflag & CSTOPB)
1214                 cr2 |= USART_CR2_STOP_2B;
1215
1216         bits = tty_get_char_size(cflag);
1217         stm32_port->rdr_mask = (BIT(bits) - 1);
1218
1219         if (cflag & PARENB) {
1220                 bits++;
1221                 cr1 |= USART_CR1_PCE;
1222         }
1223
1224         /*
1225          * Word length configuration:
1226          * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
1227          * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
1228          * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
1229          * M0 and M1 already cleared by cr1 initialization.
1230          */
1231         if (bits == 9) {
1232                 cr1 |= USART_CR1_M0;
1233         } else if ((bits == 7) && cfg->has_7bits_data) {
1234                 cr1 |= USART_CR1_M1;
1235         } else if (bits != 8) {
1236                 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
1237                         , bits);
1238                 cflag &= ~CSIZE;
1239                 cflag |= CS8;
1240                 termios->c_cflag = cflag;
1241                 bits = 8;
1242                 if (cflag & PARENB) {
1243                         bits++;
1244                         cr1 |= USART_CR1_M0;
1245                 }
1246         }
1247
1248         if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch ||
1249                                        (stm32_port->fifoen &&
1250                                         stm32_port->rxftcfg >= 0))) {
1251                 if (cflag & CSTOPB)
1252                         bits = bits + 3; /* 1 start bit + 2 stop bits */
1253                 else
1254                         bits = bits + 2; /* 1 start bit + 1 stop bit */
1255
1256                 /* RX timeout irq to occur after last stop bit + bits */
1257                 stm32_port->cr1_irq = USART_CR1_RTOIE;
1258                 writel_relaxed(bits, port->membase + ofs->rtor);
1259                 cr2 |= USART_CR2_RTOEN;
1260                 /*
1261                  * Enable fifo threshold irq in two cases, either when there is no DMA, or when
1262                  * wake up over usart, from low power until the DMA gets re-enabled by resume.
1263                  */
1264                 stm32_port->cr3_irq =  USART_CR3_RXFTIE;
1265         }
1266
1267         cr1 |= stm32_port->cr1_irq;
1268         cr3 |= stm32_port->cr3_irq;
1269
1270         if (cflag & PARODD)
1271                 cr1 |= USART_CR1_PS;
1272
1273         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1274         if (cflag & CRTSCTS) {
1275                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1276                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
1277         }
1278
1279         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
1280
1281         /*
1282          * The USART supports 16 or 8 times oversampling.
1283          * By default we prefer 16 times oversampling, so that the receiver
1284          * has a better tolerance to clock deviations.
1285          * 8 times oversampling is only used to achieve higher speeds.
1286          */
1287         if (usartdiv < 16) {
1288                 oversampling = 8;
1289                 cr1 |= USART_CR1_OVER8;
1290                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8);
1291         } else {
1292                 oversampling = 16;
1293                 cr1 &= ~USART_CR1_OVER8;
1294                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
1295         }
1296
1297         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
1298         fraction = usartdiv % oversampling;
1299         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
1300
1301         uart_update_timeout(port, cflag, baud);
1302
1303         port->read_status_mask = USART_SR_ORE;
1304         if (termios->c_iflag & INPCK)
1305                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
1306         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1307                 port->read_status_mask |= USART_SR_FE;
1308
1309         /* Characters to ignore */
1310         port->ignore_status_mask = 0;
1311         if (termios->c_iflag & IGNPAR)
1312                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
1313         if (termios->c_iflag & IGNBRK) {
1314                 port->ignore_status_mask |= USART_SR_FE;
1315                 /*
1316                  * If we're ignoring parity and break indicators,
1317                  * ignore overruns too (for real raw support).
1318                  */
1319                 if (termios->c_iflag & IGNPAR)
1320                         port->ignore_status_mask |= USART_SR_ORE;
1321         }
1322
1323         /* Ignore all characters if CREAD is not set */
1324         if ((termios->c_cflag & CREAD) == 0)
1325                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
1326
1327         if (stm32_port->rx_ch) {
1328                 /*
1329                  * Setup DMA to collect only valid data and enable error irqs.
1330                  * This also enables break reception when using DMA.
1331                  */
1332                 cr1 |= USART_CR1_PEIE;
1333                 cr3 |= USART_CR3_EIE;
1334                 cr3 |= USART_CR3_DMAR;
1335                 cr3 |= USART_CR3_DDRE;
1336         }
1337
1338         if (stm32_port->tx_ch)
1339                 cr3 |= USART_CR3_DMAT;
1340
1341         if (rs485conf->flags & SER_RS485_ENABLED) {
1342                 stm32_usart_config_reg_rs485(&cr1, &cr3,
1343                                              rs485conf->delay_rts_before_send,
1344                                              rs485conf->delay_rts_after_send,
1345                                              baud);
1346                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
1347                         cr3 &= ~USART_CR3_DEP;
1348                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1349                 } else {
1350                         cr3 |= USART_CR3_DEP;
1351                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1352                 }
1353
1354         } else {
1355                 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
1356                 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
1357         }
1358
1359         /* Configure wake up from low power on start bit detection */
1360         if (stm32_port->wakeup_src) {
1361                 cr3 &= ~USART_CR3_WUS_MASK;
1362                 cr3 |= USART_CR3_WUS_START_BIT;
1363         }
1364
1365         writel_relaxed(cr3, port->membase + ofs->cr3);
1366         writel_relaxed(cr2, port->membase + ofs->cr2);
1367         writel_relaxed(cr1, port->membase + ofs->cr1);
1368
1369         stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1370         uart_port_unlock_irqrestore(port, flags);
1371
1372         /* Handle modem control interrupts */
1373         if (UART_ENABLE_MS(port, termios->c_cflag))
1374                 stm32_usart_enable_ms(port);
1375         else
1376                 stm32_usart_disable_ms(port);
1377 }
1378
1379 static const char *stm32_usart_type(struct uart_port *port)
1380 {
1381         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
1382 }
1383
1384 static void stm32_usart_release_port(struct uart_port *port)
1385 {
1386 }
1387
1388 static int stm32_usart_request_port(struct uart_port *port)
1389 {
1390         return 0;
1391 }
1392
1393 static void stm32_usart_config_port(struct uart_port *port, int flags)
1394 {
1395         if (flags & UART_CONFIG_TYPE)
1396                 port->type = PORT_STM32;
1397 }
1398
1399 static int
1400 stm32_usart_verify_port(struct uart_port *port, struct serial_struct *ser)
1401 {
1402         /* No user changeable parameters */
1403         return -EINVAL;
1404 }
1405
1406 static void stm32_usart_pm(struct uart_port *port, unsigned int state,
1407                            unsigned int oldstate)
1408 {
1409         struct stm32_port *stm32port = container_of(port,
1410                         struct stm32_port, port);
1411         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1412         const struct stm32_usart_config *cfg = &stm32port->info->cfg;
1413         unsigned long flags;
1414
1415         switch (state) {
1416         case UART_PM_STATE_ON:
1417                 pm_runtime_get_sync(port->dev);
1418                 break;
1419         case UART_PM_STATE_OFF:
1420                 uart_port_lock_irqsave(port, &flags);
1421                 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1422                 uart_port_unlock_irqrestore(port, flags);
1423                 pm_runtime_put_sync(port->dev);
1424                 break;
1425         }
1426 }
1427
1428 #if defined(CONFIG_CONSOLE_POLL)
1429
1430  /* Callbacks for characters polling in debug context (i.e. KGDB). */
1431 static int stm32_usart_poll_init(struct uart_port *port)
1432 {
1433         struct stm32_port *stm32_port = to_stm32_port(port);
1434
1435         return clk_prepare_enable(stm32_port->clk);
1436 }
1437
1438 static int stm32_usart_poll_get_char(struct uart_port *port)
1439 {
1440         struct stm32_port *stm32_port = to_stm32_port(port);
1441         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1442
1443         if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE))
1444                 return NO_POLL_CHAR;
1445
1446         return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask;
1447 }
1448
1449 static void stm32_usart_poll_put_char(struct uart_port *port, unsigned char ch)
1450 {
1451         stm32_usart_console_putchar(port, ch);
1452 }
1453 #endif /* CONFIG_CONSOLE_POLL */
1454
1455 static const struct uart_ops stm32_uart_ops = {
1456         .tx_empty       = stm32_usart_tx_empty,
1457         .set_mctrl      = stm32_usart_set_mctrl,
1458         .get_mctrl      = stm32_usart_get_mctrl,
1459         .stop_tx        = stm32_usart_stop_tx,
1460         .start_tx       = stm32_usart_start_tx,
1461         .throttle       = stm32_usart_throttle,
1462         .unthrottle     = stm32_usart_unthrottle,
1463         .stop_rx        = stm32_usart_stop_rx,
1464         .enable_ms      = stm32_usart_enable_ms,
1465         .break_ctl      = stm32_usart_break_ctl,
1466         .startup        = stm32_usart_startup,
1467         .shutdown       = stm32_usart_shutdown,
1468         .flush_buffer   = stm32_usart_flush_buffer,
1469         .set_termios    = stm32_usart_set_termios,
1470         .pm             = stm32_usart_pm,
1471         .type           = stm32_usart_type,
1472         .release_port   = stm32_usart_release_port,
1473         .request_port   = stm32_usart_request_port,
1474         .config_port    = stm32_usart_config_port,
1475         .verify_port    = stm32_usart_verify_port,
1476 #if defined(CONFIG_CONSOLE_POLL)
1477         .poll_init      = stm32_usart_poll_init,
1478         .poll_get_char  = stm32_usart_poll_get_char,
1479         .poll_put_char  = stm32_usart_poll_put_char,
1480 #endif /* CONFIG_CONSOLE_POLL */
1481 };
1482
1483 /*
1484  * STM32H7 RX & TX FIFO threshold configuration (CR3 RXFTCFG / TXFTCFG)
1485  * Note: 1 isn't a valid value in RXFTCFG / TXFTCFG. In this case,
1486  * RXNEIE / TXEIE can be used instead of threshold irqs: RXFTIE / TXFTIE.
1487  * So, RXFTCFG / TXFTCFG bitfields values are encoded as array index + 1.
1488  */
1489 static const u32 stm32h7_usart_fifo_thresh_cfg[] = { 1, 2, 4, 8, 12, 14, 16 };
1490
1491 static void stm32_usart_get_ftcfg(struct platform_device *pdev, const char *p,
1492                                   int *ftcfg)
1493 {
1494         u32 bytes, i;
1495
1496         /* DT option to get RX & TX FIFO threshold (default to 8 bytes) */
1497         if (of_property_read_u32(pdev->dev.of_node, p, &bytes))
1498                 bytes = 8;
1499
1500         for (i = 0; i < ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg); i++)
1501                 if (stm32h7_usart_fifo_thresh_cfg[i] >= bytes)
1502                         break;
1503         if (i >= ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg))
1504                 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1;
1505
1506         dev_dbg(&pdev->dev, "%s set to %d bytes\n", p,
1507                 stm32h7_usart_fifo_thresh_cfg[i]);
1508
1509         /* Provide FIFO threshold ftcfg (1 is invalid: threshold irq unused) */
1510         if (i)
1511                 *ftcfg = i - 1;
1512         else
1513                 *ftcfg = -EINVAL;
1514 }
1515
1516 static void stm32_usart_deinit_port(struct stm32_port *stm32port)
1517 {
1518         clk_disable_unprepare(stm32port->clk);
1519 }
1520
1521 static const struct serial_rs485 stm32_rs485_supported = {
1522         .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
1523                  SER_RS485_RX_DURING_TX,
1524         .delay_rts_before_send = 1,
1525         .delay_rts_after_send = 1,
1526 };
1527
1528 static int stm32_usart_init_port(struct stm32_port *stm32port,
1529                                  struct platform_device *pdev)
1530 {
1531         struct uart_port *port = &stm32port->port;
1532         struct resource *res;
1533         int ret, irq;
1534
1535         irq = platform_get_irq(pdev, 0);
1536         if (irq < 0)
1537                 return irq;
1538
1539         port->iotype    = UPIO_MEM;
1540         port->flags     = UPF_BOOT_AUTOCONF;
1541         port->ops       = &stm32_uart_ops;
1542         port->dev       = &pdev->dev;
1543         port->fifosize  = stm32port->info->cfg.fifosize;
1544         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE);
1545         port->irq = irq;
1546         port->rs485_config = stm32_usart_config_rs485;
1547         port->rs485_supported = stm32_rs485_supported;
1548
1549         ret = stm32_usart_init_rs485(port, pdev);
1550         if (ret)
1551                 return ret;
1552
1553         stm32port->wakeup_src = stm32port->info->cfg.has_wakeup &&
1554                 of_property_read_bool(pdev->dev.of_node, "wakeup-source");
1555
1556         stm32port->swap = stm32port->info->cfg.has_swap &&
1557                 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap");
1558
1559         stm32port->fifoen = stm32port->info->cfg.has_fifo;
1560         if (stm32port->fifoen) {
1561                 stm32_usart_get_ftcfg(pdev, "rx-threshold",
1562                                       &stm32port->rxftcfg);
1563                 stm32_usart_get_ftcfg(pdev, "tx-threshold",
1564                                       &stm32port->txftcfg);
1565         }
1566
1567         port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1568         if (IS_ERR(port->membase))
1569                 return PTR_ERR(port->membase);
1570         port->mapbase = res->start;
1571
1572         spin_lock_init(&port->lock);
1573
1574         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
1575         if (IS_ERR(stm32port->clk))
1576                 return PTR_ERR(stm32port->clk);
1577
1578         /* Ensure that clk rate is correct by enabling the clk */
1579         ret = clk_prepare_enable(stm32port->clk);
1580         if (ret)
1581                 return ret;
1582
1583         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
1584         if (!stm32port->port.uartclk) {
1585                 ret = -EINVAL;
1586                 goto err_clk;
1587         }
1588
1589         stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0);
1590         if (IS_ERR(stm32port->gpios)) {
1591                 ret = PTR_ERR(stm32port->gpios);
1592                 goto err_clk;
1593         }
1594
1595         /*
1596          * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts"
1597          * properties should not be specified.
1598          */
1599         if (stm32port->hw_flow_control) {
1600                 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) ||
1601                     mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) {
1602                         dev_err(&pdev->dev, "Conflicting RTS/CTS config\n");
1603                         ret = -EINVAL;
1604                         goto err_clk;
1605                 }
1606         }
1607
1608         return ret;
1609
1610 err_clk:
1611         clk_disable_unprepare(stm32port->clk);
1612
1613         return ret;
1614 }
1615
1616 static struct stm32_port *stm32_usart_of_get_port(struct platform_device *pdev)
1617 {
1618         struct device_node *np = pdev->dev.of_node;
1619         int id;
1620
1621         if (!np)
1622                 return NULL;
1623
1624         id = of_alias_get_id(np, "serial");
1625         if (id < 0) {
1626                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
1627                 return NULL;
1628         }
1629
1630         if (WARN_ON(id >= STM32_MAX_PORTS))
1631                 return NULL;
1632
1633         stm32_ports[id].hw_flow_control =
1634                 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ ||
1635                 of_property_read_bool (np, "uart-has-rtscts");
1636         stm32_ports[id].port.line = id;
1637         stm32_ports[id].cr1_irq = USART_CR1_RXNEIE;
1638         stm32_ports[id].cr3_irq = 0;
1639         stm32_ports[id].last_res = RX_BUF_L;
1640         return &stm32_ports[id];
1641 }
1642
1643 #ifdef CONFIG_OF
1644 static const struct of_device_id stm32_match[] = {
1645         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1646         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1647         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1648         {},
1649 };
1650
1651 MODULE_DEVICE_TABLE(of, stm32_match);
1652 #endif
1653
1654 static void stm32_usart_of_dma_rx_remove(struct stm32_port *stm32port,
1655                                          struct platform_device *pdev)
1656 {
1657         if (stm32port->rx_buf)
1658                 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf,
1659                                   stm32port->rx_dma_buf);
1660 }
1661
1662 static int stm32_usart_of_dma_rx_probe(struct stm32_port *stm32port,
1663                                        struct platform_device *pdev)
1664 {
1665         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1666         struct uart_port *port = &stm32port->port;
1667         struct device *dev = &pdev->dev;
1668         struct dma_slave_config config;
1669         int ret;
1670
1671         stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L,
1672                                                &stm32port->rx_dma_buf,
1673                                                GFP_KERNEL);
1674         if (!stm32port->rx_buf)
1675                 return -ENOMEM;
1676
1677         /* Configure DMA channel */
1678         memset(&config, 0, sizeof(config));
1679         config.src_addr = port->mapbase + ofs->rdr;
1680         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1681
1682         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
1683         if (ret < 0) {
1684                 dev_err(dev, "rx dma channel config failed\n");
1685                 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1686                 return ret;
1687         }
1688
1689         return 0;
1690 }
1691
1692 static void stm32_usart_of_dma_tx_remove(struct stm32_port *stm32port,
1693                                          struct platform_device *pdev)
1694 {
1695         if (stm32port->tx_buf)
1696                 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf,
1697                                   stm32port->tx_dma_buf);
1698 }
1699
1700 static int stm32_usart_of_dma_tx_probe(struct stm32_port *stm32port,
1701                                        struct platform_device *pdev)
1702 {
1703         const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1704         struct uart_port *port = &stm32port->port;
1705         struct device *dev = &pdev->dev;
1706         struct dma_slave_config config;
1707         int ret;
1708
1709         stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L,
1710                                                &stm32port->tx_dma_buf,
1711                                                GFP_KERNEL);
1712         if (!stm32port->tx_buf)
1713                 return -ENOMEM;
1714
1715         /* Configure DMA channel */
1716         memset(&config, 0, sizeof(config));
1717         config.dst_addr = port->mapbase + ofs->tdr;
1718         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1719
1720         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1721         if (ret < 0) {
1722                 dev_err(dev, "tx dma channel config failed\n");
1723                 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1724                 return ret;
1725         }
1726
1727         return 0;
1728 }
1729
1730 static int stm32_usart_serial_probe(struct platform_device *pdev)
1731 {
1732         struct stm32_port *stm32port;
1733         int ret;
1734
1735         stm32port = stm32_usart_of_get_port(pdev);
1736         if (!stm32port)
1737                 return -ENODEV;
1738
1739         stm32port->info = of_device_get_match_data(&pdev->dev);
1740         if (!stm32port->info)
1741                 return -EINVAL;
1742
1743         stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx");
1744         if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER)
1745                 return -EPROBE_DEFER;
1746
1747         /* Fall back in interrupt mode for any non-deferral error */
1748         if (IS_ERR(stm32port->rx_ch))
1749                 stm32port->rx_ch = NULL;
1750
1751         stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx");
1752         if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) {
1753                 ret = -EPROBE_DEFER;
1754                 goto err_dma_rx;
1755         }
1756         /* Fall back in interrupt mode for any non-deferral error */
1757         if (IS_ERR(stm32port->tx_ch))
1758                 stm32port->tx_ch = NULL;
1759
1760         ret = stm32_usart_init_port(stm32port, pdev);
1761         if (ret)
1762                 goto err_dma_tx;
1763
1764         if (stm32port->wakeup_src) {
1765                 device_set_wakeup_capable(&pdev->dev, true);
1766                 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq);
1767                 if (ret)
1768                         goto err_deinit_port;
1769         }
1770
1771         if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) {
1772                 /* Fall back in interrupt mode */
1773                 dma_release_channel(stm32port->rx_ch);
1774                 stm32port->rx_ch = NULL;
1775         }
1776
1777         if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) {
1778                 /* Fall back in interrupt mode */
1779                 dma_release_channel(stm32port->tx_ch);
1780                 stm32port->tx_ch = NULL;
1781         }
1782
1783         if (!stm32port->rx_ch)
1784                 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n");
1785         if (!stm32port->tx_ch)
1786                 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n");
1787
1788         platform_set_drvdata(pdev, &stm32port->port);
1789
1790         pm_runtime_get_noresume(&pdev->dev);
1791         pm_runtime_set_active(&pdev->dev);
1792         pm_runtime_enable(&pdev->dev);
1793
1794         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1795         if (ret)
1796                 goto err_port;
1797
1798         pm_runtime_put_sync(&pdev->dev);
1799
1800         return 0;
1801
1802 err_port:
1803         pm_runtime_disable(&pdev->dev);
1804         pm_runtime_set_suspended(&pdev->dev);
1805         pm_runtime_put_noidle(&pdev->dev);
1806
1807         if (stm32port->tx_ch)
1808                 stm32_usart_of_dma_tx_remove(stm32port, pdev);
1809         if (stm32port->rx_ch)
1810                 stm32_usart_of_dma_rx_remove(stm32port, pdev);
1811
1812         if (stm32port->wakeup_src)
1813                 dev_pm_clear_wake_irq(&pdev->dev);
1814
1815 err_deinit_port:
1816         if (stm32port->wakeup_src)
1817                 device_set_wakeup_capable(&pdev->dev, false);
1818
1819         stm32_usart_deinit_port(stm32port);
1820
1821 err_dma_tx:
1822         if (stm32port->tx_ch)
1823                 dma_release_channel(stm32port->tx_ch);
1824
1825 err_dma_rx:
1826         if (stm32port->rx_ch)
1827                 dma_release_channel(stm32port->rx_ch);
1828
1829         return ret;
1830 }
1831
1832 static void stm32_usart_serial_remove(struct platform_device *pdev)
1833 {
1834         struct uart_port *port = platform_get_drvdata(pdev);
1835         struct stm32_port *stm32_port = to_stm32_port(port);
1836         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1837         u32 cr3;
1838
1839         pm_runtime_get_sync(&pdev->dev);
1840         uart_remove_one_port(&stm32_usart_driver, port);
1841
1842         pm_runtime_disable(&pdev->dev);
1843         pm_runtime_set_suspended(&pdev->dev);
1844         pm_runtime_put_noidle(&pdev->dev);
1845
1846         stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE);
1847
1848         if (stm32_port->tx_ch) {
1849                 stm32_usart_of_dma_tx_remove(stm32_port, pdev);
1850                 dma_release_channel(stm32_port->tx_ch);
1851         }
1852
1853         if (stm32_port->rx_ch) {
1854                 stm32_usart_of_dma_rx_remove(stm32_port, pdev);
1855                 dma_release_channel(stm32_port->rx_ch);
1856         }
1857
1858         cr3 = readl_relaxed(port->membase + ofs->cr3);
1859         cr3 &= ~USART_CR3_EIE;
1860         cr3 &= ~USART_CR3_DMAR;
1861         cr3 &= ~USART_CR3_DMAT;
1862         cr3 &= ~USART_CR3_DDRE;
1863         writel_relaxed(cr3, port->membase + ofs->cr3);
1864
1865         if (stm32_port->wakeup_src) {
1866                 dev_pm_clear_wake_irq(&pdev->dev);
1867                 device_init_wakeup(&pdev->dev, false);
1868         }
1869
1870         stm32_usart_deinit_port(stm32_port);
1871 }
1872
1873 static void __maybe_unused stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1874 {
1875         struct stm32_port *stm32_port = to_stm32_port(port);
1876         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1877         u32 isr;
1878         int ret;
1879
1880         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr,
1881                                                 (isr & USART_SR_TXE), 100,
1882                                                 STM32_USART_TIMEOUT_USEC);
1883         if (ret != 0) {
1884                 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret);
1885                 return;
1886         }
1887         writel_relaxed(ch, port->membase + ofs->tdr);
1888 }
1889
1890 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1891 static void stm32_usart_console_write(struct console *co, const char *s,
1892                                       unsigned int cnt)
1893 {
1894         struct uart_port *port = &stm32_ports[co->index].port;
1895         struct stm32_port *stm32_port = to_stm32_port(port);
1896         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1897         const struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1898         unsigned long flags;
1899         u32 old_cr1, new_cr1;
1900         int locked = 1;
1901
1902         if (oops_in_progress)
1903                 locked = uart_port_trylock_irqsave(port, &flags);
1904         else
1905                 uart_port_lock_irqsave(port, &flags);
1906
1907         /* Save and disable interrupts, enable the transmitter */
1908         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1909         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1910         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1911         writel_relaxed(new_cr1, port->membase + ofs->cr1);
1912
1913         uart_console_write(port, s, cnt, stm32_usart_console_putchar);
1914
1915         /* Restore interrupt state */
1916         writel_relaxed(old_cr1, port->membase + ofs->cr1);
1917
1918         if (locked)
1919                 uart_port_unlock_irqrestore(port, flags);
1920 }
1921
1922 static int stm32_usart_console_setup(struct console *co, char *options)
1923 {
1924         struct stm32_port *stm32port;
1925         int baud = 9600;
1926         int bits = 8;
1927         int parity = 'n';
1928         int flow = 'n';
1929
1930         if (co->index >= STM32_MAX_PORTS)
1931                 return -ENODEV;
1932
1933         stm32port = &stm32_ports[co->index];
1934
1935         /*
1936          * This driver does not support early console initialization
1937          * (use ARM early printk support instead), so we only expect
1938          * this to be called during the uart port registration when the
1939          * driver gets probed and the port should be mapped at that point.
1940          */
1941         if (stm32port->port.mapbase == 0 || !stm32port->port.membase)
1942                 return -ENXIO;
1943
1944         if (options)
1945                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1946
1947         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1948 }
1949
1950 static struct console stm32_console = {
1951         .name           = STM32_SERIAL_NAME,
1952         .device         = uart_console_device,
1953         .write          = stm32_usart_console_write,
1954         .setup          = stm32_usart_console_setup,
1955         .flags          = CON_PRINTBUFFER,
1956         .index          = -1,
1957         .data           = &stm32_usart_driver,
1958 };
1959
1960 #define STM32_SERIAL_CONSOLE (&stm32_console)
1961
1962 #else
1963 #define STM32_SERIAL_CONSOLE NULL
1964 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1965
1966 #ifdef CONFIG_SERIAL_EARLYCON
1967 static void early_stm32_usart_console_putchar(struct uart_port *port, unsigned char ch)
1968 {
1969         struct stm32_usart_info *info = port->private_data;
1970
1971         while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE))
1972                 cpu_relax();
1973
1974         writel_relaxed(ch, port->membase + info->ofs.tdr);
1975 }
1976
1977 static void early_stm32_serial_write(struct console *console, const char *s, unsigned int count)
1978 {
1979         struct earlycon_device *device = console->data;
1980         struct uart_port *port = &device->port;
1981
1982         uart_console_write(port, s, count, early_stm32_usart_console_putchar);
1983 }
1984
1985 static int __init early_stm32_h7_serial_setup(struct earlycon_device *device, const char *options)
1986 {
1987         if (!(device->port.membase || device->port.iobase))
1988                 return -ENODEV;
1989         device->port.private_data = &stm32h7_info;
1990         device->con->write = early_stm32_serial_write;
1991         return 0;
1992 }
1993
1994 static int __init early_stm32_f7_serial_setup(struct earlycon_device *device, const char *options)
1995 {
1996         if (!(device->port.membase || device->port.iobase))
1997                 return -ENODEV;
1998         device->port.private_data = &stm32f7_info;
1999         device->con->write = early_stm32_serial_write;
2000         return 0;
2001 }
2002
2003 static int __init early_stm32_f4_serial_setup(struct earlycon_device *device, const char *options)
2004 {
2005         if (!(device->port.membase || device->port.iobase))
2006                 return -ENODEV;
2007         device->port.private_data = &stm32f4_info;
2008         device->con->write = early_stm32_serial_write;
2009         return 0;
2010 }
2011
2012 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
2013 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
2014 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
2015 #endif /* CONFIG_SERIAL_EARLYCON */
2016
2017 static struct uart_driver stm32_usart_driver = {
2018         .driver_name    = DRIVER_NAME,
2019         .dev_name       = STM32_SERIAL_NAME,
2020         .major          = 0,
2021         .minor          = 0,
2022         .nr             = STM32_MAX_PORTS,
2023         .cons           = STM32_SERIAL_CONSOLE,
2024 };
2025
2026 static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
2027                                                        bool enable)
2028 {
2029         struct stm32_port *stm32_port = to_stm32_port(port);
2030         const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
2031         struct tty_port *tport = &port->state->port;
2032         int ret;
2033         unsigned int size = 0;
2034         unsigned long flags;
2035
2036         if (!stm32_port->wakeup_src || !tty_port_initialized(tport))
2037                 return 0;
2038
2039         /*
2040          * Enable low-power wake-up and wake-up irq if argument is set to
2041          * "enable", disable low-power wake-up and wake-up irq otherwise
2042          */
2043         if (enable) {
2044                 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM);
2045                 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE);
2046                 mctrl_gpio_enable_irq_wake(stm32_port->gpios);
2047
2048                 /*
2049                  * When DMA is used for reception, it must be disabled before
2050                  * entering low-power mode and re-enabled when exiting from
2051                  * low-power mode.
2052                  */
2053                 if (stm32_port->rx_ch) {
2054                         uart_port_lock_irqsave(port, &flags);
2055                         /* Poll data from DMA RX buffer if any */
2056                         if (!stm32_usart_rx_dma_pause(stm32_port))
2057                                 size += stm32_usart_receive_chars(port, true);
2058                         stm32_usart_rx_dma_terminate(stm32_port);
2059                         uart_unlock_and_check_sysrq_irqrestore(port, flags);
2060                         if (size)
2061                                 tty_flip_buffer_push(tport);
2062                 }
2063
2064                 /* Poll data from RX FIFO if any */
2065                 stm32_usart_receive_chars(port, false);
2066         } else {
2067                 if (stm32_port->rx_ch) {
2068                         ret = stm32_usart_rx_dma_start_or_resume(port);
2069                         if (ret)
2070                                 return ret;
2071                 }
2072                 mctrl_gpio_disable_irq_wake(stm32_port->gpios);
2073                 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM);
2074                 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE);
2075         }
2076
2077         return 0;
2078 }
2079
2080 static int __maybe_unused stm32_usart_serial_suspend(struct device *dev)
2081 {
2082         struct uart_port *port = dev_get_drvdata(dev);
2083         int ret;
2084
2085         uart_suspend_port(&stm32_usart_driver, port);
2086
2087         if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
2088                 ret = stm32_usart_serial_en_wakeup(port, true);
2089                 if (ret)
2090                         return ret;
2091         }
2092
2093         /*
2094          * When "no_console_suspend" is enabled, keep the pinctrl default state
2095          * and rely on bootloader stage to restore this state upon resume.
2096          * Otherwise, apply the idle or sleep states depending on wakeup
2097          * capabilities.
2098          */
2099         if (console_suspend_enabled || !uart_console(port)) {
2100                 if (device_may_wakeup(dev) || device_wakeup_path(dev))
2101                         pinctrl_pm_select_idle_state(dev);
2102                 else
2103                         pinctrl_pm_select_sleep_state(dev);
2104         }
2105
2106         return 0;
2107 }
2108
2109 static int __maybe_unused stm32_usart_serial_resume(struct device *dev)
2110 {
2111         struct uart_port *port = dev_get_drvdata(dev);
2112         int ret;
2113
2114         pinctrl_pm_select_default_state(dev);
2115
2116         if (device_may_wakeup(dev) || device_wakeup_path(dev)) {
2117                 ret = stm32_usart_serial_en_wakeup(port, false);
2118                 if (ret)
2119                         return ret;
2120         }
2121
2122         return uart_resume_port(&stm32_usart_driver, port);
2123 }
2124
2125 static int __maybe_unused stm32_usart_runtime_suspend(struct device *dev)
2126 {
2127         struct uart_port *port = dev_get_drvdata(dev);
2128         struct stm32_port *stm32port = container_of(port,
2129                         struct stm32_port, port);
2130
2131         clk_disable_unprepare(stm32port->clk);
2132
2133         return 0;
2134 }
2135
2136 static int __maybe_unused stm32_usart_runtime_resume(struct device *dev)
2137 {
2138         struct uart_port *port = dev_get_drvdata(dev);
2139         struct stm32_port *stm32port = container_of(port,
2140                         struct stm32_port, port);
2141
2142         return clk_prepare_enable(stm32port->clk);
2143 }
2144
2145 static const struct dev_pm_ops stm32_serial_pm_ops = {
2146         SET_RUNTIME_PM_OPS(stm32_usart_runtime_suspend,
2147                            stm32_usart_runtime_resume, NULL)
2148         SET_SYSTEM_SLEEP_PM_OPS(stm32_usart_serial_suspend,
2149                                 stm32_usart_serial_resume)
2150 };
2151
2152 static struct platform_driver stm32_serial_driver = {
2153         .probe          = stm32_usart_serial_probe,
2154         .remove_new     = stm32_usart_serial_remove,
2155         .driver = {
2156                 .name   = DRIVER_NAME,
2157                 .pm     = &stm32_serial_pm_ops,
2158                 .of_match_table = of_match_ptr(stm32_match),
2159         },
2160 };
2161
2162 static int __init stm32_usart_init(void)
2163 {
2164         static char banner[] __initdata = "STM32 USART driver initialized";
2165         int ret;
2166
2167         pr_info("%s\n", banner);
2168
2169         ret = uart_register_driver(&stm32_usart_driver);
2170         if (ret)
2171                 return ret;
2172
2173         ret = platform_driver_register(&stm32_serial_driver);
2174         if (ret)
2175                 uart_unregister_driver(&stm32_usart_driver);
2176
2177         return ret;
2178 }
2179
2180 static void __exit stm32_usart_exit(void)
2181 {
2182         platform_driver_unregister(&stm32_serial_driver);
2183         uart_unregister_driver(&stm32_usart_driver);
2184 }
2185
2186 module_init(stm32_usart_init);
2187 module_exit(stm32_usart_exit);
2188
2189 MODULE_ALIAS("platform:" DRIVER_NAME);
2190 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
2191 MODULE_LICENSE("GPL v2");