drivers/tty/serial/stm32-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Maxime Coquelin 2015
   4  * Copyright (C) STMicroelectronics SA 2017
   5  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   6  *           Gerald Baeza <gerald.baeza@st.com>
   7  *
   8  * Inspired by st-asc.c from STMicroelectronics (c)
   9  */
  10
  11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14
  15 #include <linux/clk.h>
  16 #include <linux/console.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-direction.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/irq.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pm_wakeirq.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/serial.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/sysrq.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/tty.h>
  36
  37 #include "stm32-usart.h"
  38
  39 static void stm32_stop_tx(struct uart_port *port);
  40 static void stm32_transmit_chars(struct uart_port *port);
  41
  42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
  43 {
  44         return container_of(port, struct stm32_port, port);
  45 }
  46
  47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
  48 {
  49         u32 val;
  50
  51         val = readl_relaxed(port->membase + reg);
  52         val |= bits;
  53         writel_relaxed(val, port->membase + reg);
  54 }
  55
  56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
  57 {
  58         u32 val;
  59
  60         val = readl_relaxed(port->membase + reg);
  61         val &= ~bits;
  62         writel_relaxed(val, port->membase + reg);
  63 }
  64
  65 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
  66                                    u32 delay_DDE, u32 baud)
  67 {
  68         u32 rs485_deat_dedt;
  69         u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
  70         bool over8;
  71
  72         *cr3 |= USART_CR3_DEM;
  73         over8 = *cr1 & USART_CR1_OVER8;
  74
  75         if (over8)
  76                 rs485_deat_dedt = delay_ADE * baud * 8;
  77         else
  78                 rs485_deat_dedt = delay_ADE * baud * 16;
  79
  80         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  81         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  82                           rs485_deat_dedt_max : rs485_deat_dedt;
  83         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
  84                            USART_CR1_DEAT_MASK;
  85         *cr1 |= rs485_deat_dedt;
  86
  87         if (over8)
  88                 rs485_deat_dedt = delay_DDE * baud * 8;
  89         else
  90                 rs485_deat_dedt = delay_DDE * baud * 16;
  91
  92         rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
  93         rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
  94                           rs485_deat_dedt_max : rs485_deat_dedt;
  95         rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
  96                            USART_CR1_DEDT_MASK;
  97         *cr1 |= rs485_deat_dedt;
  98 }
  99
 100 static int stm32_config_rs485(struct uart_port *port,
 101                               struct serial_rs485 *rs485conf)
 102 {
 103         struct stm32_port *stm32_port = to_stm32_port(port);
 104         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 105         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 106         u32 usartdiv, baud, cr1, cr3;
 107         bool over8;
 108
 109         stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 110
 111         port->rs485 = *rs485conf;
 112
 113         rs485conf->flags |= SER_RS485_RX_DURING_TX;
 114
 115         if (rs485conf->flags & SER_RS485_ENABLED) {
 116                 cr1 = readl_relaxed(port->membase + ofs->cr1);
 117                 cr3 = readl_relaxed(port->membase + ofs->cr3);
 118                 usartdiv = readl_relaxed(port->membase + ofs->brr);
 119                 usartdiv = usartdiv & GENMASK(15, 0);
 120                 over8 = cr1 & USART_CR1_OVER8;
 121
 122                 if (over8)
 123                         usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
 124                                    << USART_BRR_04_R_SHIFT;
 125
 126                 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
 127                 stm32_config_reg_rs485(&cr1, &cr3,
 128                                        rs485conf->delay_rts_before_send,
 129                                        rs485conf->delay_rts_after_send, baud);
 130
 131                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 132                         cr3 &= ~USART_CR3_DEP;
 133                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 134                 } else {
 135                         cr3 |= USART_CR3_DEP;
 136                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 137                 }
 138
 139                 writel_relaxed(cr3, port->membase + ofs->cr3);
 140                 writel_relaxed(cr1, port->membase + ofs->cr1);
 141         } else {
 142                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
 143                 stm32_clr_bits(port, ofs->cr1,
 144                                USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 145         }
 146
 147         stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 148
 149         return 0;
 150 }
 151
 152 static int stm32_init_rs485(struct uart_port *port,
 153                             struct platform_device *pdev)
 154 {
 155         struct serial_rs485 *rs485conf = &port->rs485;
 156
 157         rs485conf->flags = 0;
 158         rs485conf->delay_rts_before_send = 0;
 159         rs485conf->delay_rts_after_send = 0;
 160
 161         if (!pdev->dev.of_node)
 162                 return -ENODEV;
 163
 164         uart_get_rs485_mode(&pdev->dev, rs485conf);
 165
 166         return 0;
 167 }
 168
 169 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
 170                             bool threaded)
 171 {
 172         struct stm32_port *stm32_port = to_stm32_port(port);
 173         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 174         enum dma_status status;
 175         struct dma_tx_state state;
 176
 177         *sr = readl_relaxed(port->membase + ofs->isr);
 178
 179         if (threaded && stm32_port->rx_ch) {
 180                 status = dmaengine_tx_status(stm32_port->rx_ch,
 181                                              stm32_port->rx_ch->cookie,
 182                                              &state);
 183                 if ((status == DMA_IN_PROGRESS) &&
 184                     (*last_res != state.residue))
 185                         return 1;
 186                 else
 187                         return 0;
 188         } else if (*sr & USART_SR_RXNE) {
 189                 return 1;
 190         }
 191         return 0;
 192 }
 193
 194 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
 195                                     int *last_res)
 196 {
 197         struct stm32_port *stm32_port = to_stm32_port(port);
 198         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 199         unsigned long c;
 200
 201         if (stm32_port->rx_ch) {
 202                 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
 203                 if ((*last_res) == 0)
 204                         *last_res = RX_BUF_L;
 205         } else {
 206                 c = readl_relaxed(port->membase + ofs->rdr);
 207                 /* apply RDR data mask */
 208                 c &= stm32_port->rdr_mask;
 209         }
 210
 211         return c;
 212 }
 213
 214 static void stm32_receive_chars(struct uart_port *port, bool threaded)
 215 {
 216         struct tty_port *tport = &port->state->port;
 217         struct stm32_port *stm32_port = to_stm32_port(port);
 218         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 219         unsigned long c;
 220         u32 sr;
 221         char flag;
 222
 223         if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 224                 pm_wakeup_event(tport->tty->dev, 0);
 225
 226         while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
 227                 sr |= USART_SR_DUMMY_RX;
 228                 flag = TTY_NORMAL;
 229
 230                 /*
 231                  * Status bits has to be cleared before reading the RDR:
 232                  * In FIFO mode, reading the RDR will pop the next data
 233                  * (if any) along with its status bits into the SR.
 234                  * Not doing so leads to misalignement between RDR and SR,
 235                  * and clear status bits of the next rx data.
 236                  *
 237                  * Clear errors flags for stm32f7 and stm32h7 compatible
 238                  * devices. On stm32f4 compatible devices, the error bit is
 239                  * cleared by the sequence [read SR - read DR].
 240                  */
 241                 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
 242                         writel_relaxed(sr & USART_SR_ERR_MASK,
 243                                        port->membase + ofs->icr);
 244
 245                 c = stm32_get_char(port, &sr, &stm32_port->last_res);
 246                 port->icount.rx++;
 247                 if (sr & USART_SR_ERR_MASK) {
 248                         if (sr & USART_SR_ORE) {
 249                                 port->icount.overrun++;
 250                         } else if (sr & USART_SR_PE) {
 251                                 port->icount.parity++;
 252                         } else if (sr & USART_SR_FE) {
 253                                 /* Break detection if character is null */
 254                                 if (!c) {
 255                                         port->icount.brk++;
 256                                         if (uart_handle_break(port))
 257                                                 continue;
 258                                 } else {
 259                                         port->icount.frame++;
 260                                 }
 261                         }
 262
 263                         sr &= port->read_status_mask;
 264
 265                         if (sr & USART_SR_PE) {
 266                                 flag = TTY_PARITY;
 267                         } else if (sr & USART_SR_FE) {
 268                                 if (!c)
 269                                         flag = TTY_BREAK;
 270                                 else
 271                                         flag = TTY_FRAME;
 272                         }
 273                 }
 274
 275                 if (uart_handle_sysrq_char(port, c))
 276                         continue;
 277                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 278         }
 279
 280         spin_unlock(&port->lock);
 281         tty_flip_buffer_push(tport);
 282         spin_lock(&port->lock);
 283 }
 284
 285 static void stm32_tx_dma_complete(void *arg)
 286 {
 287         struct uart_port *port = arg;
 288         struct stm32_port *stm32port = to_stm32_port(port);
 289         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 290
 291         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 292         stm32port->tx_dma_busy = false;
 293
 294         /* Let's see if we have pending data to send */
 295         stm32_transmit_chars(port);
 296 }
 297
 298 static void stm32_transmit_chars_pio(struct uart_port *port)
 299 {
 300         struct stm32_port *stm32_port = to_stm32_port(port);
 301         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 302         struct circ_buf *xmit = &port->state->xmit;
 303         unsigned int isr;
 304         int ret;
 305
 306         if (stm32_port->tx_dma_busy) {
 307                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 308                 stm32_port->tx_dma_busy = false;
 309         }
 310
 311         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 312                                                 isr,
 313                                                 (isr & USART_SR_TXE),
 314                                                 10, 100000);
 315
 316         if (ret)
 317                 dev_err(port->dev, "tx empty not set\n");
 318
 319         stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 320
 321         writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 322         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 323         port->icount.tx++;
 324 }
 325
 326 static void stm32_transmit_chars_dma(struct uart_port *port)
 327 {
 328         struct stm32_port *stm32port = to_stm32_port(port);
 329         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 330         struct circ_buf *xmit = &port->state->xmit;
 331         struct dma_async_tx_descriptor *desc = NULL;
 332         dma_cookie_t cookie;
 333         unsigned int count, i;
 334
 335         if (stm32port->tx_dma_busy)
 336                 return;
 337
 338         stm32port->tx_dma_busy = true;
 339
 340         count = uart_circ_chars_pending(xmit);
 341
 342         if (count > TX_BUF_L)
 343                 count = TX_BUF_L;
 344
 345         if (xmit->tail < xmit->head) {
 346                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 347         } else {
 348                 size_t one = UART_XMIT_SIZE - xmit->tail;
 349                 size_t two;
 350
 351                 if (one > count)
 352                         one = count;
 353                 two = count - one;
 354
 355                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 356                 if (two)
 357                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 358         }
 359
 360         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 361                                            stm32port->tx_dma_buf,
 362                                            count,
 363                                            DMA_MEM_TO_DEV,
 364                                            DMA_PREP_INTERRUPT);
 365
 366         if (!desc) {
 367                 for (i = count; i > 0; i--)
 368                         stm32_transmit_chars_pio(port);
 369                 return;
 370         }
 371
 372         desc->callback = stm32_tx_dma_complete;
 373         desc->callback_param = port;
 374
 375         /* Push current DMA TX transaction in the pending queue */
 376         cookie = dmaengine_submit(desc);
 377
 378         /* Issue pending DMA TX requests */
 379         dma_async_issue_pending(stm32port->tx_ch);
 380
 381         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 382
 383         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 384         port->icount.tx += count;
 385 }
 386
 387 static void stm32_transmit_chars(struct uart_port *port)
 388 {
 389         struct stm32_port *stm32_port = to_stm32_port(port);
 390         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 391         struct circ_buf *xmit = &port->state->xmit;
 392
 393         if (port->x_char) {
 394                 if (stm32_port->tx_dma_busy)
 395                         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 396                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 397                 port->x_char = 0;
 398                 port->icount.tx++;
 399                 if (stm32_port->tx_dma_busy)
 400                         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 401                 return;
 402         }
 403
 404         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 405                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 406                 return;
 407         }
 408
 409         if (ofs->icr == UNDEF_REG)
 410                 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 411         else
 412                 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
 413
 414         if (stm32_port->tx_ch)
 415                 stm32_transmit_chars_dma(port);
 416         else
 417                 stm32_transmit_chars_pio(port);
 418
 419         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 420                 uart_write_wakeup(port);
 421
 422         if (uart_circ_empty(xmit))
 423                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 424 }
 425
 426 static irqreturn_t stm32_interrupt(int irq, void *ptr)
 427 {
 428         struct uart_port *port = ptr;
 429         struct stm32_port *stm32_port = to_stm32_port(port);
 430         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 431         u32 sr;
 432
 433         spin_lock(&port->lock);
 434
 435         sr = readl_relaxed(port->membase + ofs->isr);
 436
 437         if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
 438                 writel_relaxed(USART_ICR_WUCF,
 439                                port->membase + ofs->icr);
 440
 441         if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
 442                 stm32_receive_chars(port, false);
 443
 444         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
 445                 stm32_transmit_chars(port);
 446
 447         spin_unlock(&port->lock);
 448
 449         if (stm32_port->rx_ch)
 450                 return IRQ_WAKE_THREAD;
 451         else
 452                 return IRQ_HANDLED;
 453 }
 454
 455 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
 456 {
 457         struct uart_port *port = ptr;
 458         struct stm32_port *stm32_port = to_stm32_port(port);
 459
 460         spin_lock(&port->lock);
 461
 462         if (stm32_port->rx_ch)
 463                 stm32_receive_chars(port, true);
 464
 465         spin_unlock(&port->lock);
 466
 467         return IRQ_HANDLED;
 468 }
 469
 470 static unsigned int stm32_tx_empty(struct uart_port *port)
 471 {
 472         struct stm32_port *stm32_port = to_stm32_port(port);
 473         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 474
 475         if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
 476                 return TIOCSER_TEMT;
 477
 478         return 0;
 479 }
 480
 481 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 482 {
 483         struct stm32_port *stm32_port = to_stm32_port(port);
 484         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 485
 486         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 487                 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 488         else
 489                 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 490 }
 491
 492 static unsigned int stm32_get_mctrl(struct uart_port *port)
 493 {
 494         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 495         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 496 }
 497
 498 /* Transmit stop */
 499 static void stm32_stop_tx(struct uart_port *port)
 500 {
 501         struct stm32_port *stm32_port = to_stm32_port(port);
 502         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 503
 504         stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 505 }
 506
 507 /* There are probably characters waiting to be transmitted. */
 508 static void stm32_start_tx(struct uart_port *port)
 509 {
 510         struct circ_buf *xmit = &port->state->xmit;
 511
 512         if (uart_circ_empty(xmit) && !port->x_char)
 513                 return;
 514
 515         stm32_transmit_chars(port);
 516 }
 517
 518 /* Throttle the remote when input buffer is about to overflow. */
 519 static void stm32_throttle(struct uart_port *port)
 520 {
 521         struct stm32_port *stm32_port = to_stm32_port(port);
 522         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 523         unsigned long flags;
 524
 525         spin_lock_irqsave(&port->lock, flags);
 526         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 527         spin_unlock_irqrestore(&port->lock, flags);
 528 }
 529
 530 /* Unthrottle the remote, the input buffer can now accept data. */
 531 static void stm32_unthrottle(struct uart_port *port)
 532 {
 533         struct stm32_port *stm32_port = to_stm32_port(port);
 534         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 535         unsigned long flags;
 536
 537         spin_lock_irqsave(&port->lock, flags);
 538         stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 539         spin_unlock_irqrestore(&port->lock, flags);
 540 }
 541
 542 /* Receive stop */
 543 static void stm32_stop_rx(struct uart_port *port)
 544 {
 545         struct stm32_port *stm32_port = to_stm32_port(port);
 546         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 547
 548         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 549 }
 550
 551 /* Handle breaks - ignored by us */
 552 static void stm32_break_ctl(struct uart_port *port, int break_state)
 553 {
 554 }
 555
 556 static int stm32_startup(struct uart_port *port)
 557 {
 558         struct stm32_port *stm32_port = to_stm32_port(port);
 559         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 560         const char *name = to_platform_device(port->dev)->name;
 561         u32 val;
 562         int ret;
 563
 564         ret = request_threaded_irq(port->irq, stm32_interrupt,
 565                                    stm32_threaded_interrupt,
 566                                    IRQF_NO_SUSPEND, name, port);
 567         if (ret)
 568                 return ret;
 569
 570         val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 571         if (stm32_port->fifoen)
 572                 val |= USART_CR1_FIFOEN;
 573         stm32_set_bits(port, ofs->cr1, val);
 574
 575         return 0;
 576 }
 577
 578 static void stm32_shutdown(struct uart_port *port)
 579 {
 580         struct stm32_port *stm32_port = to_stm32_port(port);
 581         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 582         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 583         u32 val, isr;
 584         int ret;
 585
 586         val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 587         val |= BIT(cfg->uart_enable_bit);
 588         if (stm32_port->fifoen)
 589                 val |= USART_CR1_FIFOEN;
 590
 591         ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
 592                                          isr, (isr & USART_SR_TC),
 593                                          10, 100000);
 594
 595         if (ret)
 596                 dev_err(port->dev, "transmission complete not set\n");
 597
 598         stm32_clr_bits(port, ofs->cr1, val);
 599
 600         free_irq(port->irq, port);
 601 }
 602
 603 unsigned int stm32_get_databits(struct ktermios *termios)
 604 {
 605         unsigned int bits;
 606
 607         tcflag_t cflag = termios->c_cflag;
 608
 609         switch (cflag & CSIZE) {
 610         /*
 611          * CSIZE settings are not necessarily supported in hardware.
 612          * CSIZE unsupported configurations are handled here to set word length
 613          * to 8 bits word as default configuration and to print debug message.
 614          */
 615         case CS5:
 616                 bits = 5;
 617                 break;
 618         case CS6:
 619                 bits = 6;
 620                 break;
 621         case CS7:
 622                 bits = 7;
 623                 break;
 624         /* default including CS8 */
 625         default:
 626                 bits = 8;
 627                 break;
 628         }
 629
 630         return bits;
 631 }
 632
 633 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
 634                             struct ktermios *old)
 635 {
 636         struct stm32_port *stm32_port = to_stm32_port(port);
 637         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 638         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 639         struct serial_rs485 *rs485conf = &port->rs485;
 640         unsigned int baud, bits;
 641         u32 usartdiv, mantissa, fraction, oversampling;
 642         tcflag_t cflag = termios->c_cflag;
 643         u32 cr1, cr2, cr3, isr;
 644         unsigned long flags;
 645         int ret;
 646
 647         if (!stm32_port->hw_flow_control)
 648                 cflag &= ~CRTSCTS;
 649
 650         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 651
 652         spin_lock_irqsave(&port->lock, flags);
 653
 654         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 655                                                 isr,
 656                                                 (isr & USART_SR_TC),
 657                                                 10, 100000);
 658
 659         /* Send the TC error message only when ISR_TC is not set. */
 660         if (ret)
 661                 dev_err(port->dev, "Transmission is not complete\n");
 662
 663         /* Stop serial port and reset value */
 664         writel_relaxed(0, port->membase + ofs->cr1);
 665
 666         cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
 667
 668         if (stm32_port->fifoen)
 669                 cr1 |= USART_CR1_FIFOEN;
 670         cr2 = 0;
 671         cr3 = 0;
 672
 673         if (cflag & CSTOPB)
 674                 cr2 |= USART_CR2_STOP_2B;
 675
 676         bits = stm32_get_databits(termios);
 677         stm32_port->rdr_mask = (BIT(bits) - 1);
 678
 679         if (cflag & PARENB) {
 680                 bits++;
 681                 cr1 |= USART_CR1_PCE;
 682         }
 683
 684         /*
 685          * Word length configuration:
 686          * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
 687          * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
 688          * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
 689          * M0 and M1 already cleared by cr1 initialization.
 690          */
 691         if (bits == 9)
 692                 cr1 |= USART_CR1_M0;
 693         else if ((bits == 7) && cfg->has_7bits_data)
 694                 cr1 |= USART_CR1_M1;
 695         else if (bits != 8)
 696                 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
 697                         , bits);
 698
 699         if (cflag & PARODD)
 700                 cr1 |= USART_CR1_PS;
 701
 702         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
 703         if (cflag & CRTSCTS) {
 704                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 705                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
 706         }
 707
 708         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
 709
 710         /*
 711          * The USART supports 16 or 8 times oversampling.
 712          * By default we prefer 16 times oversampling, so that the receiver
 713          * has a better tolerance to clock deviations.
 714          * 8 times oversampling is only used to achieve higher speeds.
 715          */
 716         if (usartdiv < 16) {
 717                 oversampling = 8;
 718                 cr1 |= USART_CR1_OVER8;
 719                 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
 720         } else {
 721                 oversampling = 16;
 722                 cr1 &= ~USART_CR1_OVER8;
 723                 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
 724         }
 725
 726         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
 727         fraction = usartdiv % oversampling;
 728         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
 729
 730         uart_update_timeout(port, cflag, baud);
 731
 732         port->read_status_mask = USART_SR_ORE;
 733         if (termios->c_iflag & INPCK)
 734                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
 735         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 736                 port->read_status_mask |= USART_SR_FE;
 737
 738         /* Characters to ignore */
 739         port->ignore_status_mask = 0;
 740         if (termios->c_iflag & IGNPAR)
 741                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
 742         if (termios->c_iflag & IGNBRK) {
 743                 port->ignore_status_mask |= USART_SR_FE;
 744                 /*
 745                  * If we're ignoring parity and break indicators,
 746                  * ignore overruns too (for real raw support).
 747                  */
 748                 if (termios->c_iflag & IGNPAR)
 749                         port->ignore_status_mask |= USART_SR_ORE;
 750         }
 751
 752         /* Ignore all characters if CREAD is not set */
 753         if ((termios->c_cflag & CREAD) == 0)
 754                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
 755
 756         if (stm32_port->rx_ch)
 757                 cr3 |= USART_CR3_DMAR;
 758
 759         if (rs485conf->flags & SER_RS485_ENABLED) {
 760                 stm32_config_reg_rs485(&cr1, &cr3,
 761                                        rs485conf->delay_rts_before_send,
 762                                        rs485conf->delay_rts_after_send, baud);
 763                 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
 764                         cr3 &= ~USART_CR3_DEP;
 765                         rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
 766                 } else {
 767                         cr3 |= USART_CR3_DEP;
 768                         rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
 769                 }
 770
 771         } else {
 772                 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
 773                 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
 774         }
 775
 776         writel_relaxed(cr3, port->membase + ofs->cr3);
 777         writel_relaxed(cr2, port->membase + ofs->cr2);
 778         writel_relaxed(cr1, port->membase + ofs->cr1);
 779
 780         stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 781         spin_unlock_irqrestore(&port->lock, flags);
 782 }
 783
 784 static const char *stm32_type(struct uart_port *port)
 785 {
 786         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
 787 }
 788
 789 static void stm32_release_port(struct uart_port *port)
 790 {
 791 }
 792
 793 static int stm32_request_port(struct uart_port *port)
 794 {
 795         return 0;
 796 }
 797
 798 static void stm32_config_port(struct uart_port *port, int flags)
 799 {
 800         if (flags & UART_CONFIG_TYPE)
 801                 port->type = PORT_STM32;
 802 }
 803
 804 static int
 805 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
 806 {
 807         /* No user changeable parameters */
 808         return -EINVAL;
 809 }
 810
 811 static void stm32_pm(struct uart_port *port, unsigned int state,
 812                 unsigned int oldstate)
 813 {
 814         struct stm32_port *stm32port = container_of(port,
 815                         struct stm32_port, port);
 816         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 817         struct stm32_usart_config *cfg = &stm32port->info->cfg;
 818         unsigned long flags = 0;
 819
 820         switch (state) {
 821         case UART_PM_STATE_ON:
 822                 clk_prepare_enable(stm32port->clk);
 823                 break;
 824         case UART_PM_STATE_OFF:
 825                 spin_lock_irqsave(&port->lock, flags);
 826                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 827                 spin_unlock_irqrestore(&port->lock, flags);
 828                 clk_disable_unprepare(stm32port->clk);
 829                 break;
 830         }
 831 }
 832
 833 static const struct uart_ops stm32_uart_ops = {
 834         .tx_empty       = stm32_tx_empty,
 835         .set_mctrl      = stm32_set_mctrl,
 836         .get_mctrl      = stm32_get_mctrl,
 837         .stop_tx        = stm32_stop_tx,
 838         .start_tx       = stm32_start_tx,
 839         .throttle       = stm32_throttle,
 840         .unthrottle     = stm32_unthrottle,
 841         .stop_rx        = stm32_stop_rx,
 842         .break_ctl      = stm32_break_ctl,
 843         .startup        = stm32_startup,
 844         .shutdown       = stm32_shutdown,
 845         .set_termios    = stm32_set_termios,
 846         .pm             = stm32_pm,
 847         .type           = stm32_type,
 848         .release_port   = stm32_release_port,
 849         .request_port   = stm32_request_port,
 850         .config_port    = stm32_config_port,
 851         .verify_port    = stm32_verify_port,
 852 };
 853
 854 static int stm32_init_port(struct stm32_port *stm32port,
 855                           struct platform_device *pdev)
 856 {
 857         struct uart_port *port = &stm32port->port;
 858         struct resource *res;
 859         int ret;
 860
 861         port->iotype    = UPIO_MEM;
 862         port->flags     = UPF_BOOT_AUTOCONF;
 863         port->ops       = &stm32_uart_ops;
 864         port->dev       = &pdev->dev;
 865         port->irq       = platform_get_irq(pdev, 0);
 866         port->rs485_config = stm32_config_rs485;
 867
 868         stm32_init_rs485(port, pdev);
 869
 870         stm32port->wakeirq = platform_get_irq(pdev, 1);
 871         stm32port->fifoen = stm32port->info->cfg.has_fifo;
 872
 873         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 874         port->membase = devm_ioremap_resource(&pdev->dev, res);
 875         if (IS_ERR(port->membase))
 876                 return PTR_ERR(port->membase);
 877         port->mapbase = res->start;
 878
 879         spin_lock_init(&port->lock);
 880
 881         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
 882         if (IS_ERR(stm32port->clk))
 883                 return PTR_ERR(stm32port->clk);
 884
 885         /* Ensure that clk rate is correct by enabling the clk */
 886         ret = clk_prepare_enable(stm32port->clk);
 887         if (ret)
 888                 return ret;
 889
 890         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
 891         if (!stm32port->port.uartclk) {
 892                 clk_disable_unprepare(stm32port->clk);
 893                 ret = -EINVAL;
 894         }
 895
 896         return ret;
 897 }
 898
 899 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
 900 {
 901         struct device_node *np = pdev->dev.of_node;
 902         int id;
 903
 904         if (!np)
 905                 return NULL;
 906
 907         id = of_alias_get_id(np, "serial");
 908         if (id < 0) {
 909                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
 910                 return NULL;
 911         }
 912
 913         if (WARN_ON(id >= STM32_MAX_PORTS))
 914                 return NULL;
 915
 916         stm32_ports[id].hw_flow_control = of_property_read_bool(np,
 917                                                         "st,hw-flow-ctrl");
 918         stm32_ports[id].port.line = id;
 919         stm32_ports[id].last_res = RX_BUF_L;
 920         return &stm32_ports[id];
 921 }
 922
 923 #ifdef CONFIG_OF
 924 static const struct of_device_id stm32_match[] = {
 925         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
 926         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
 927         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
 928         {},
 929 };
 930
 931 MODULE_DEVICE_TABLE(of, stm32_match);
 932 #endif
 933
 934 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
 935                                  struct platform_device *pdev)
 936 {
 937         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 938         struct uart_port *port = &stm32port->port;
 939         struct device *dev = &pdev->dev;
 940         struct dma_slave_config config;
 941         struct dma_async_tx_descriptor *desc = NULL;
 942         dma_cookie_t cookie;
 943         int ret;
 944
 945         /* Request DMA RX channel */
 946         stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
 947         if (!stm32port->rx_ch) {
 948                 dev_info(dev, "rx dma alloc failed\n");
 949                 return -ENODEV;
 950         }
 951         stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
 952                                                  &stm32port->rx_dma_buf,
 953                                                  GFP_KERNEL);
 954         if (!stm32port->rx_buf) {
 955                 ret = -ENOMEM;
 956                 goto alloc_err;
 957         }
 958
 959         /* Configure DMA channel */
 960         memset(&config, 0, sizeof(config));
 961         config.src_addr = port->mapbase + ofs->rdr;
 962         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 963
 964         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
 965         if (ret < 0) {
 966                 dev_err(dev, "rx dma channel config failed\n");
 967                 ret = -ENODEV;
 968                 goto config_err;
 969         }
 970
 971         /* Prepare a DMA cyclic transaction */
 972         desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
 973                                          stm32port->rx_dma_buf,
 974                                          RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
 975                                          DMA_PREP_INTERRUPT);
 976         if (!desc) {
 977                 dev_err(dev, "rx dma prep cyclic failed\n");
 978                 ret = -ENODEV;
 979                 goto config_err;
 980         }
 981
 982         /* No callback as dma buffer is drained on usart interrupt */
 983         desc->callback = NULL;
 984         desc->callback_param = NULL;
 985
 986         /* Push current DMA transaction in the pending queue */
 987         cookie = dmaengine_submit(desc);
 988
 989         /* Issue pending DMA requests */
 990         dma_async_issue_pending(stm32port->rx_ch);
 991
 992         return 0;
 993
 994 config_err:
 995         dma_free_coherent(&pdev->dev,
 996                           RX_BUF_L, stm32port->rx_buf,
 997                           stm32port->rx_dma_buf);
 998
 999 alloc_err:
1000         dma_release_channel(stm32port->rx_ch);
1001         stm32port->rx_ch = NULL;
1002
1003         return ret;
1004 }
1005
1006 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1007                                  struct platform_device *pdev)
1008 {
1009         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1010         struct uart_port *port = &stm32port->port;
1011         struct device *dev = &pdev->dev;
1012         struct dma_slave_config config;
1013         int ret;
1014
1015         stm32port->tx_dma_busy = false;
1016
1017         /* Request DMA TX channel */
1018         stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1019         if (!stm32port->tx_ch) {
1020                 dev_info(dev, "tx dma alloc failed\n");
1021                 return -ENODEV;
1022         }
1023         stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1024                                                  &stm32port->tx_dma_buf,
1025                                                  GFP_KERNEL);
1026         if (!stm32port->tx_buf) {
1027                 ret = -ENOMEM;
1028                 goto alloc_err;
1029         }
1030
1031         /* Configure DMA channel */
1032         memset(&config, 0, sizeof(config));
1033         config.dst_addr = port->mapbase + ofs->tdr;
1034         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1035
1036         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1037         if (ret < 0) {
1038                 dev_err(dev, "tx dma channel config failed\n");
1039                 ret = -ENODEV;
1040                 goto config_err;
1041         }
1042
1043         return 0;
1044
1045 config_err:
1046         dma_free_coherent(&pdev->dev,
1047                           TX_BUF_L, stm32port->tx_buf,
1048                           stm32port->tx_dma_buf);
1049
1050 alloc_err:
1051         dma_release_channel(stm32port->tx_ch);
1052         stm32port->tx_ch = NULL;
1053
1054         return ret;
1055 }
1056
1057 static int stm32_serial_probe(struct platform_device *pdev)
1058 {
1059         const struct of_device_id *match;
1060         struct stm32_port *stm32port;
1061         int ret;
1062
1063         stm32port = stm32_of_get_stm32_port(pdev);
1064         if (!stm32port)
1065                 return -ENODEV;
1066
1067         match = of_match_device(stm32_match, &pdev->dev);
1068         if (match && match->data)
1069                 stm32port->info = (struct stm32_usart_info *)match->data;
1070         else
1071                 return -EINVAL;
1072
1073         ret = stm32_init_port(stm32port, pdev);
1074         if (ret)
1075                 return ret;
1076
1077         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
1078                 ret = device_init_wakeup(&pdev->dev, true);
1079                 if (ret)
1080                         goto err_uninit;
1081
1082                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1083                                                     stm32port->wakeirq);
1084                 if (ret)
1085                         goto err_nowup;
1086
1087                 device_set_wakeup_enable(&pdev->dev, false);
1088         }
1089
1090         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1091         if (ret)
1092                 goto err_wirq;
1093
1094         ret = stm32_of_dma_rx_probe(stm32port, pdev);
1095         if (ret)
1096                 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1097
1098         ret = stm32_of_dma_tx_probe(stm32port, pdev);
1099         if (ret)
1100                 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1101
1102         platform_set_drvdata(pdev, &stm32port->port);
1103
1104         return 0;
1105
1106 err_wirq:
1107         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1108                 dev_pm_clear_wake_irq(&pdev->dev);
1109
1110 err_nowup:
1111         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
1112                 device_init_wakeup(&pdev->dev, false);
1113
1114 err_uninit:
1115         clk_disable_unprepare(stm32port->clk);
1116
1117         return ret;
1118 }
1119
1120 static int stm32_serial_remove(struct platform_device *pdev)
1121 {
1122         struct uart_port *port = platform_get_drvdata(pdev);
1123         struct stm32_port *stm32_port = to_stm32_port(port);
1124         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1125         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1126
1127         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1128
1129         if (stm32_port->rx_ch)
1130                 dma_release_channel(stm32_port->rx_ch);
1131
1132         if (stm32_port->rx_dma_buf)
1133                 dma_free_coherent(&pdev->dev,
1134                                   RX_BUF_L, stm32_port->rx_buf,
1135                                   stm32_port->rx_dma_buf);
1136
1137         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1138
1139         if (stm32_port->tx_ch)
1140                 dma_release_channel(stm32_port->tx_ch);
1141
1142         if (stm32_port->tx_dma_buf)
1143                 dma_free_coherent(&pdev->dev,
1144                                   TX_BUF_L, stm32_port->tx_buf,
1145                                   stm32_port->tx_dma_buf);
1146
1147         if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
1148                 dev_pm_clear_wake_irq(&pdev->dev);
1149                 device_init_wakeup(&pdev->dev, false);
1150         }
1151
1152         clk_disable_unprepare(stm32_port->clk);
1153
1154         return uart_remove_one_port(&stm32_usart_driver, port);
1155 }
1156
1157
1158 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1159 static void stm32_console_putchar(struct uart_port *port, int ch)
1160 {
1161         struct stm32_port *stm32_port = to_stm32_port(port);
1162         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1163
1164         while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1165                 cpu_relax();
1166
1167         writel_relaxed(ch, port->membase + ofs->tdr);
1168 }
1169
1170 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1171 {
1172         struct uart_port *port = &stm32_ports[co->index].port;
1173         struct stm32_port *stm32_port = to_stm32_port(port);
1174         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1175         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1176         unsigned long flags;
1177         u32 old_cr1, new_cr1;
1178         int locked = 1;
1179
1180         local_irq_save(flags);
1181         if (port->sysrq)
1182                 locked = 0;
1183         else if (oops_in_progress)
1184                 locked = spin_trylock(&port->lock);
1185         else
1186                 spin_lock(&port->lock);
1187
1188         /* Save and disable interrupts, enable the transmitter */
1189         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1190         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1191         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1192         writel_relaxed(new_cr1, port->membase + ofs->cr1);
1193
1194         uart_console_write(port, s, cnt, stm32_console_putchar);
1195
1196         /* Restore interrupt state */
1197         writel_relaxed(old_cr1, port->membase + ofs->cr1);
1198
1199         if (locked)
1200                 spin_unlock(&port->lock);
1201         local_irq_restore(flags);
1202 }
1203
1204 static int stm32_console_setup(struct console *co, char *options)
1205 {
1206         struct stm32_port *stm32port;
1207         int baud = 9600;
1208         int bits = 8;
1209         int parity = 'n';
1210         int flow = 'n';
1211
1212         if (co->index >= STM32_MAX_PORTS)
1213                 return -ENODEV;
1214
1215         stm32port = &stm32_ports[co->index];
1216
1217         /*
1218          * This driver does not support early console initialization
1219          * (use ARM early printk support instead), so we only expect
1220          * this to be called during the uart port registration when the
1221          * driver gets probed and the port should be mapped at that point.
1222          */
1223         if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1224                 return -ENXIO;
1225
1226         if (options)
1227                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1228
1229         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1230 }
1231
1232 static struct console stm32_console = {
1233         .name           = STM32_SERIAL_NAME,
1234         .device         = uart_console_device,
1235         .write          = stm32_console_write,
1236         .setup          = stm32_console_setup,
1237         .flags          = CON_PRINTBUFFER,
1238         .index          = -1,
1239         .data           = &stm32_usart_driver,
1240 };
1241
1242 #define STM32_SERIAL_CONSOLE (&stm32_console)
1243
1244 #else
1245 #define STM32_SERIAL_CONSOLE NULL
1246 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1247
1248 static struct uart_driver stm32_usart_driver = {
1249         .driver_name    = DRIVER_NAME,
1250         .dev_name       = STM32_SERIAL_NAME,
1251         .major          = 0,
1252         .minor          = 0,
1253         .nr             = STM32_MAX_PORTS,
1254         .cons           = STM32_SERIAL_CONSOLE,
1255 };
1256
1257 #ifdef CONFIG_PM_SLEEP
1258 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1259 {
1260         struct stm32_port *stm32_port = to_stm32_port(port);
1261         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1262         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1263         u32 val;
1264
1265         if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1266                 return;
1267
1268         if (enable) {
1269                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1270                 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1271                 val = readl_relaxed(port->membase + ofs->cr3);
1272                 val &= ~USART_CR3_WUS_MASK;
1273                 /* Enable Wake up interrupt from low power on start bit */
1274                 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1275                 writel_relaxed(val, port->membase + ofs->cr3);
1276                 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1277         } else {
1278                 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1279         }
1280 }
1281
1282 static int stm32_serial_suspend(struct device *dev)
1283 {
1284         struct uart_port *port = dev_get_drvdata(dev);
1285
1286         uart_suspend_port(&stm32_usart_driver, port);
1287
1288         if (device_may_wakeup(dev))
1289                 stm32_serial_enable_wakeup(port, true);
1290         else
1291                 stm32_serial_enable_wakeup(port, false);
1292
1293         return 0;
1294 }
1295
1296 static int stm32_serial_resume(struct device *dev)
1297 {
1298         struct uart_port *port = dev_get_drvdata(dev);
1299
1300         if (device_may_wakeup(dev))
1301                 stm32_serial_enable_wakeup(port, false);
1302
1303         return uart_resume_port(&stm32_usart_driver, port);
1304 }
1305 #endif /* CONFIG_PM_SLEEP */
1306
1307 static const struct dev_pm_ops stm32_serial_pm_ops = {
1308         SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1309 };
1310
1311 static struct platform_driver stm32_serial_driver = {
1312         .probe          = stm32_serial_probe,
1313         .remove         = stm32_serial_remove,
1314         .driver = {
1315                 .name   = DRIVER_NAME,
1316                 .pm     = &stm32_serial_pm_ops,
1317                 .of_match_table = of_match_ptr(stm32_match),
1318         },
1319 };
1320
1321 static int __init usart_init(void)
1322 {
1323         static char banner[] __initdata = "STM32 USART driver initialized";
1324         int ret;
1325
1326         pr_info("%s\n", banner);
1327
1328         ret = uart_register_driver(&stm32_usart_driver);
1329         if (ret)
1330                 return ret;
1331
1332         ret = platform_driver_register(&stm32_serial_driver);
1333         if (ret)
1334                 uart_unregister_driver(&stm32_usart_driver);
1335
1336         return ret;
1337 }
1338
1339 static void __exit usart_exit(void)
1340 {
1341         platform_driver_unregister(&stm32_serial_driver);
1342         uart_unregister_driver(&stm32_usart_driver);
1343 }
1344
1345 module_init(usart_init);
1346 module_exit(usart_exit);
1347
1348 MODULE_ALIAS("platform:" DRIVER_NAME);
1349 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1350 MODULE_LICENSE("GPL v2");