2 * Copyright (C) Maxime Coquelin 2015
3 * Copyright (C) STMicroelectronics SA 2017
4 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
5 * Gerald Baeza <gerald.baeza@st.com>
6 * License terms: GNU General Public License (GPL), version 2
8 * Inspired by st-asc.c from STMicroelectronics (c)
11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15 #include <linux/clk.h>
16 #include <linux/console.h>
17 #include <linux/delay.h>
18 #include <linux/dma-direction.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/iopoll.h>
23 #include <linux/irq.h>
24 #include <linux/module.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pm_wakeirq.h>
30 #include <linux/serial_core.h>
31 #include <linux/serial.h>
32 #include <linux/spinlock.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/tty.h>
37 #include "stm32-usart.h"
39 static void stm32_stop_tx(struct uart_port *port);
40 static void stm32_transmit_chars(struct uart_port *port);
42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
44 return container_of(port, struct stm32_port, port);
47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
51 val = readl_relaxed(port->membase + reg);
53 writel_relaxed(val, port->membase + reg);
56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
60 val = readl_relaxed(port->membase + reg);
62 writel_relaxed(val, port->membase + reg);
65 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
68 struct stm32_port *stm32_port = to_stm32_port(port);
69 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
70 enum dma_status status;
71 struct dma_tx_state state;
73 *sr = readl_relaxed(port->membase + ofs->isr);
75 if (threaded && stm32_port->rx_ch) {
76 status = dmaengine_tx_status(stm32_port->rx_ch,
77 stm32_port->rx_ch->cookie,
79 if ((status == DMA_IN_PROGRESS) &&
80 (*last_res != state.residue))
84 } else if (*sr & USART_SR_RXNE) {
91 stm32_get_char(struct uart_port *port, u32 *sr, int *last_res)
93 struct stm32_port *stm32_port = to_stm32_port(port);
94 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
97 if (stm32_port->rx_ch) {
98 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
100 *last_res = RX_BUF_L;
103 return readl_relaxed(port->membase + ofs->rdr);
107 static void stm32_receive_chars(struct uart_port *port, bool threaded)
109 struct tty_port *tport = &port->state->port;
110 struct stm32_port *stm32_port = to_stm32_port(port);
111 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
116 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
117 pm_wakeup_event(tport->tty->dev, 0);
119 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
120 sr |= USART_SR_DUMMY_RX;
124 * Status bits has to be cleared before reading the RDR:
125 * In FIFO mode, reading the RDR will pop the next data
126 * (if any) along with its status bits into the SR.
127 * Not doing so leads to misalignement between RDR and SR,
128 * and clear status bits of the next rx data.
130 * Clear errors flags for stm32f7 and stm32h7 compatible
131 * devices. On stm32f4 compatible devices, the error bit is
132 * cleared by the sequence [read SR - read DR].
134 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
135 writel_relaxed(sr & USART_SR_ERR_MASK,
136 port->membase + ofs->icr);
138 c = stm32_get_char(port, &sr, &stm32_port->last_res);
140 if (sr & USART_SR_ERR_MASK) {
141 if (sr & USART_SR_ORE) {
142 port->icount.overrun++;
143 } else if (sr & USART_SR_PE) {
144 port->icount.parity++;
145 } else if (sr & USART_SR_FE) {
146 /* Break detection if character is null */
149 if (uart_handle_break(port))
152 port->icount.frame++;
156 sr &= port->read_status_mask;
158 if (sr & USART_SR_PE) {
160 } else if (sr & USART_SR_FE) {
168 if (uart_handle_sysrq_char(port, c))
170 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
173 spin_unlock(&port->lock);
174 tty_flip_buffer_push(tport);
175 spin_lock(&port->lock);
178 static void stm32_tx_dma_complete(void *arg)
180 struct uart_port *port = arg;
181 struct stm32_port *stm32port = to_stm32_port(port);
182 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
184 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
185 stm32port->tx_dma_busy = false;
187 /* Let's see if we have pending data to send */
188 stm32_transmit_chars(port);
191 static void stm32_transmit_chars_pio(struct uart_port *port)
193 struct stm32_port *stm32_port = to_stm32_port(port);
194 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
195 struct circ_buf *xmit = &port->state->xmit;
199 if (stm32_port->tx_dma_busy) {
200 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
201 stm32_port->tx_dma_busy = false;
204 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
206 (isr & USART_SR_TXE),
210 dev_err(port->dev, "tx empty not set\n");
212 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
214 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
215 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
219 static void stm32_transmit_chars_dma(struct uart_port *port)
221 struct stm32_port *stm32port = to_stm32_port(port);
222 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
223 struct circ_buf *xmit = &port->state->xmit;
224 struct dma_async_tx_descriptor *desc = NULL;
226 unsigned int count, i;
228 if (stm32port->tx_dma_busy)
231 stm32port->tx_dma_busy = true;
233 count = uart_circ_chars_pending(xmit);
235 if (count > TX_BUF_L)
238 if (xmit->tail < xmit->head) {
239 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
241 size_t one = UART_XMIT_SIZE - xmit->tail;
248 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
250 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
253 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
254 stm32port->tx_dma_buf,
260 for (i = count; i > 0; i--)
261 stm32_transmit_chars_pio(port);
265 desc->callback = stm32_tx_dma_complete;
266 desc->callback_param = port;
268 /* Push current DMA TX transaction in the pending queue */
269 cookie = dmaengine_submit(desc);
271 /* Issue pending DMA TX requests */
272 dma_async_issue_pending(stm32port->tx_ch);
274 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
276 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
277 port->icount.tx += count;
280 static void stm32_transmit_chars(struct uart_port *port)
282 struct stm32_port *stm32_port = to_stm32_port(port);
283 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
284 struct circ_buf *xmit = &port->state->xmit;
287 if (stm32_port->tx_dma_busy)
288 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
289 writel_relaxed(port->x_char, port->membase + ofs->tdr);
292 if (stm32_port->tx_dma_busy)
293 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
297 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
298 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
302 if (ofs->icr == UNDEF_REG)
303 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
305 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
307 if (stm32_port->tx_ch)
308 stm32_transmit_chars_dma(port);
310 stm32_transmit_chars_pio(port);
312 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
313 uart_write_wakeup(port);
315 if (uart_circ_empty(xmit))
316 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
319 static irqreturn_t stm32_interrupt(int irq, void *ptr)
321 struct uart_port *port = ptr;
322 struct stm32_port *stm32_port = to_stm32_port(port);
323 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
326 spin_lock(&port->lock);
328 sr = readl_relaxed(port->membase + ofs->isr);
330 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
331 writel_relaxed(USART_ICR_WUCF,
332 port->membase + ofs->icr);
334 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
335 stm32_receive_chars(port, false);
337 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
338 stm32_transmit_chars(port);
340 spin_unlock(&port->lock);
342 if (stm32_port->rx_ch)
343 return IRQ_WAKE_THREAD;
348 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
350 struct uart_port *port = ptr;
351 struct stm32_port *stm32_port = to_stm32_port(port);
353 spin_lock(&port->lock);
355 if (stm32_port->rx_ch)
356 stm32_receive_chars(port, true);
358 spin_unlock(&port->lock);
363 static unsigned int stm32_tx_empty(struct uart_port *port)
365 struct stm32_port *stm32_port = to_stm32_port(port);
366 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
368 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
374 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
376 struct stm32_port *stm32_port = to_stm32_port(port);
377 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
379 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
380 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
382 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
385 static unsigned int stm32_get_mctrl(struct uart_port *port)
387 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
388 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
392 static void stm32_stop_tx(struct uart_port *port)
394 struct stm32_port *stm32_port = to_stm32_port(port);
395 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
397 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
400 /* There are probably characters waiting to be transmitted. */
401 static void stm32_start_tx(struct uart_port *port)
403 struct circ_buf *xmit = &port->state->xmit;
405 if (uart_circ_empty(xmit))
408 stm32_transmit_chars(port);
411 /* Throttle the remote when input buffer is about to overflow. */
412 static void stm32_throttle(struct uart_port *port)
414 struct stm32_port *stm32_port = to_stm32_port(port);
415 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
418 spin_lock_irqsave(&port->lock, flags);
419 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
420 spin_unlock_irqrestore(&port->lock, flags);
423 /* Unthrottle the remote, the input buffer can now accept data. */
424 static void stm32_unthrottle(struct uart_port *port)
426 struct stm32_port *stm32_port = to_stm32_port(port);
427 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
430 spin_lock_irqsave(&port->lock, flags);
431 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
432 spin_unlock_irqrestore(&port->lock, flags);
436 static void stm32_stop_rx(struct uart_port *port)
438 struct stm32_port *stm32_port = to_stm32_port(port);
439 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
441 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
444 /* Handle breaks - ignored by us */
445 static void stm32_break_ctl(struct uart_port *port, int break_state)
449 static int stm32_startup(struct uart_port *port)
451 struct stm32_port *stm32_port = to_stm32_port(port);
452 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
453 const char *name = to_platform_device(port->dev)->name;
457 ret = request_threaded_irq(port->irq, stm32_interrupt,
458 stm32_threaded_interrupt,
459 IRQF_NO_SUSPEND, name, port);
463 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
464 if (stm32_port->fifoen)
465 val |= USART_CR1_FIFOEN;
466 stm32_set_bits(port, ofs->cr1, val);
471 static void stm32_shutdown(struct uart_port *port)
473 struct stm32_port *stm32_port = to_stm32_port(port);
474 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
475 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
479 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
480 val |= BIT(cfg->uart_enable_bit);
481 if (stm32_port->fifoen)
482 val |= USART_CR1_FIFOEN;
484 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
485 isr, (isr & USART_SR_TC),
489 dev_err(port->dev, "transmission complete not set\n");
491 stm32_clr_bits(port, ofs->cr1, val);
493 free_irq(port->irq, port);
496 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
497 struct ktermios *old)
499 struct stm32_port *stm32_port = to_stm32_port(port);
500 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
501 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
503 u32 usartdiv, mantissa, fraction, oversampling;
504 tcflag_t cflag = termios->c_cflag;
505 u32 cr1, cr2, cr3, isr;
509 if (!stm32_port->hw_flow_control)
512 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
514 spin_lock_irqsave(&port->lock, flags);
516 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
521 /* Send the TC error message only when ISR_TC is not set. */
523 dev_err(port->dev, "Transmission is not complete\n");
525 /* Stop serial port and reset value */
526 writel_relaxed(0, port->membase + ofs->cr1);
528 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
529 cr1 |= BIT(cfg->uart_enable_bit);
530 if (stm32_port->fifoen)
531 cr1 |= USART_CR1_FIFOEN;
536 cr2 |= USART_CR2_STOP_2B;
538 if (cflag & PARENB) {
539 cr1 |= USART_CR1_PCE;
540 if ((cflag & CSIZE) == CS8) {
541 if (cfg->has_7bits_data)
551 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
552 if (cflag & CRTSCTS) {
553 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
554 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
557 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
560 * The USART supports 16 or 8 times oversampling.
561 * By default we prefer 16 times oversampling, so that the receiver
562 * has a better tolerance to clock deviations.
563 * 8 times oversampling is only used to achieve higher speeds.
567 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
570 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
573 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
574 fraction = usartdiv % oversampling;
575 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
577 uart_update_timeout(port, cflag, baud);
579 port->read_status_mask = USART_SR_ORE;
580 if (termios->c_iflag & INPCK)
581 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
582 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
583 port->read_status_mask |= USART_SR_FE;
585 /* Characters to ignore */
586 port->ignore_status_mask = 0;
587 if (termios->c_iflag & IGNPAR)
588 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
589 if (termios->c_iflag & IGNBRK) {
590 port->ignore_status_mask |= USART_SR_FE;
592 * If we're ignoring parity and break indicators,
593 * ignore overruns too (for real raw support).
595 if (termios->c_iflag & IGNPAR)
596 port->ignore_status_mask |= USART_SR_ORE;
599 /* Ignore all characters if CREAD is not set */
600 if ((termios->c_cflag & CREAD) == 0)
601 port->ignore_status_mask |= USART_SR_DUMMY_RX;
603 if (stm32_port->rx_ch)
604 cr3 |= USART_CR3_DMAR;
606 writel_relaxed(cr3, port->membase + ofs->cr3);
607 writel_relaxed(cr2, port->membase + ofs->cr2);
608 writel_relaxed(cr1, port->membase + ofs->cr1);
610 spin_unlock_irqrestore(&port->lock, flags);
613 static const char *stm32_type(struct uart_port *port)
615 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
618 static void stm32_release_port(struct uart_port *port)
622 static int stm32_request_port(struct uart_port *port)
627 static void stm32_config_port(struct uart_port *port, int flags)
629 if (flags & UART_CONFIG_TYPE)
630 port->type = PORT_STM32;
634 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
636 /* No user changeable parameters */
640 static void stm32_pm(struct uart_port *port, unsigned int state,
641 unsigned int oldstate)
643 struct stm32_port *stm32port = container_of(port,
644 struct stm32_port, port);
645 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
646 struct stm32_usart_config *cfg = &stm32port->info->cfg;
647 unsigned long flags = 0;
650 case UART_PM_STATE_ON:
651 clk_prepare_enable(stm32port->clk);
653 case UART_PM_STATE_OFF:
654 spin_lock_irqsave(&port->lock, flags);
655 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
656 spin_unlock_irqrestore(&port->lock, flags);
657 clk_disable_unprepare(stm32port->clk);
662 static const struct uart_ops stm32_uart_ops = {
663 .tx_empty = stm32_tx_empty,
664 .set_mctrl = stm32_set_mctrl,
665 .get_mctrl = stm32_get_mctrl,
666 .stop_tx = stm32_stop_tx,
667 .start_tx = stm32_start_tx,
668 .throttle = stm32_throttle,
669 .unthrottle = stm32_unthrottle,
670 .stop_rx = stm32_stop_rx,
671 .break_ctl = stm32_break_ctl,
672 .startup = stm32_startup,
673 .shutdown = stm32_shutdown,
674 .set_termios = stm32_set_termios,
677 .release_port = stm32_release_port,
678 .request_port = stm32_request_port,
679 .config_port = stm32_config_port,
680 .verify_port = stm32_verify_port,
683 static int stm32_init_port(struct stm32_port *stm32port,
684 struct platform_device *pdev)
686 struct uart_port *port = &stm32port->port;
687 struct resource *res;
690 port->iotype = UPIO_MEM;
691 port->flags = UPF_BOOT_AUTOCONF;
692 port->ops = &stm32_uart_ops;
693 port->dev = &pdev->dev;
694 port->irq = platform_get_irq(pdev, 0);
695 stm32port->wakeirq = platform_get_irq(pdev, 1);
696 stm32port->fifoen = stm32port->info->cfg.has_fifo;
698 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
699 port->membase = devm_ioremap_resource(&pdev->dev, res);
700 if (IS_ERR(port->membase))
701 return PTR_ERR(port->membase);
702 port->mapbase = res->start;
704 spin_lock_init(&port->lock);
706 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
707 if (IS_ERR(stm32port->clk))
708 return PTR_ERR(stm32port->clk);
710 /* Ensure that clk rate is correct by enabling the clk */
711 ret = clk_prepare_enable(stm32port->clk);
715 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
716 if (!stm32port->port.uartclk) {
717 clk_disable_unprepare(stm32port->clk);
724 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
726 struct device_node *np = pdev->dev.of_node;
732 id = of_alias_get_id(np, "serial");
734 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
738 if (WARN_ON(id >= STM32_MAX_PORTS))
741 stm32_ports[id].hw_flow_control = of_property_read_bool(np,
743 stm32_ports[id].port.line = id;
744 stm32_ports[id].last_res = RX_BUF_L;
745 return &stm32_ports[id];
749 static const struct of_device_id stm32_match[] = {
750 { .compatible = "st,stm32-usart", .data = &stm32f4_info},
751 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
752 { .compatible = "st,stm32f7-usart", .data = &stm32f7_info},
753 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
754 { .compatible = "st,stm32h7-usart", .data = &stm32h7_info},
755 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
759 MODULE_DEVICE_TABLE(of, stm32_match);
762 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
763 struct platform_device *pdev)
765 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
766 struct uart_port *port = &stm32port->port;
767 struct device *dev = &pdev->dev;
768 struct dma_slave_config config;
769 struct dma_async_tx_descriptor *desc = NULL;
773 /* Request DMA RX channel */
774 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
775 if (!stm32port->rx_ch) {
776 dev_info(dev, "rx dma alloc failed\n");
779 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
780 &stm32port->rx_dma_buf,
782 if (!stm32port->rx_buf) {
787 /* Configure DMA channel */
788 memset(&config, 0, sizeof(config));
789 config.src_addr = port->mapbase + ofs->rdr;
790 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
792 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
794 dev_err(dev, "rx dma channel config failed\n");
799 /* Prepare a DMA cyclic transaction */
800 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
801 stm32port->rx_dma_buf,
802 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
805 dev_err(dev, "rx dma prep cyclic failed\n");
810 /* No callback as dma buffer is drained on usart interrupt */
811 desc->callback = NULL;
812 desc->callback_param = NULL;
814 /* Push current DMA transaction in the pending queue */
815 cookie = dmaengine_submit(desc);
817 /* Issue pending DMA requests */
818 dma_async_issue_pending(stm32port->rx_ch);
823 dma_free_coherent(&pdev->dev,
824 RX_BUF_L, stm32port->rx_buf,
825 stm32port->rx_dma_buf);
828 dma_release_channel(stm32port->rx_ch);
829 stm32port->rx_ch = NULL;
834 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
835 struct platform_device *pdev)
837 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
838 struct uart_port *port = &stm32port->port;
839 struct device *dev = &pdev->dev;
840 struct dma_slave_config config;
843 stm32port->tx_dma_busy = false;
845 /* Request DMA TX channel */
846 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
847 if (!stm32port->tx_ch) {
848 dev_info(dev, "tx dma alloc failed\n");
851 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
852 &stm32port->tx_dma_buf,
854 if (!stm32port->tx_buf) {
859 /* Configure DMA channel */
860 memset(&config, 0, sizeof(config));
861 config.dst_addr = port->mapbase + ofs->tdr;
862 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
864 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
866 dev_err(dev, "tx dma channel config failed\n");
874 dma_free_coherent(&pdev->dev,
875 TX_BUF_L, stm32port->tx_buf,
876 stm32port->tx_dma_buf);
879 dma_release_channel(stm32port->tx_ch);
880 stm32port->tx_ch = NULL;
885 static int stm32_serial_probe(struct platform_device *pdev)
887 const struct of_device_id *match;
888 struct stm32_port *stm32port;
891 stm32port = stm32_of_get_stm32_port(pdev);
895 match = of_match_device(stm32_match, &pdev->dev);
896 if (match && match->data)
897 stm32port->info = (struct stm32_usart_info *)match->data;
901 ret = stm32_init_port(stm32port, pdev);
905 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
906 ret = device_init_wakeup(&pdev->dev, true);
910 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
915 device_set_wakeup_enable(&pdev->dev, false);
918 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
922 ret = stm32_of_dma_rx_probe(stm32port, pdev);
924 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
926 ret = stm32_of_dma_tx_probe(stm32port, pdev);
928 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
930 platform_set_drvdata(pdev, &stm32port->port);
935 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
936 dev_pm_clear_wake_irq(&pdev->dev);
939 if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
940 device_init_wakeup(&pdev->dev, false);
943 clk_disable_unprepare(stm32port->clk);
948 static int stm32_serial_remove(struct platform_device *pdev)
950 struct uart_port *port = platform_get_drvdata(pdev);
951 struct stm32_port *stm32_port = to_stm32_port(port);
952 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
953 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
955 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
957 if (stm32_port->rx_ch)
958 dma_release_channel(stm32_port->rx_ch);
960 if (stm32_port->rx_dma_buf)
961 dma_free_coherent(&pdev->dev,
962 RX_BUF_L, stm32_port->rx_buf,
963 stm32_port->rx_dma_buf);
965 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
967 if (stm32_port->tx_ch)
968 dma_release_channel(stm32_port->tx_ch);
970 if (stm32_port->tx_dma_buf)
971 dma_free_coherent(&pdev->dev,
972 TX_BUF_L, stm32_port->tx_buf,
973 stm32_port->tx_dma_buf);
975 if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
976 dev_pm_clear_wake_irq(&pdev->dev);
977 device_init_wakeup(&pdev->dev, false);
980 clk_disable_unprepare(stm32_port->clk);
982 return uart_remove_one_port(&stm32_usart_driver, port);
986 #ifdef CONFIG_SERIAL_STM32_CONSOLE
987 static void stm32_console_putchar(struct uart_port *port, int ch)
989 struct stm32_port *stm32_port = to_stm32_port(port);
990 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
992 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
995 writel_relaxed(ch, port->membase + ofs->tdr);
998 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1000 struct uart_port *port = &stm32_ports[co->index].port;
1001 struct stm32_port *stm32_port = to_stm32_port(port);
1002 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1003 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1004 unsigned long flags;
1005 u32 old_cr1, new_cr1;
1008 local_irq_save(flags);
1011 else if (oops_in_progress)
1012 locked = spin_trylock(&port->lock);
1014 spin_lock(&port->lock);
1016 /* Save and disable interrupts, enable the transmitter */
1017 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1018 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1019 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1020 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1022 uart_console_write(port, s, cnt, stm32_console_putchar);
1024 /* Restore interrupt state */
1025 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1028 spin_unlock(&port->lock);
1029 local_irq_restore(flags);
1032 static int stm32_console_setup(struct console *co, char *options)
1034 struct stm32_port *stm32port;
1040 if (co->index >= STM32_MAX_PORTS)
1043 stm32port = &stm32_ports[co->index];
1046 * This driver does not support early console initialization
1047 * (use ARM early printk support instead), so we only expect
1048 * this to be called during the uart port registration when the
1049 * driver gets probed and the port should be mapped at that point.
1051 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1055 uart_parse_options(options, &baud, &parity, &bits, &flow);
1057 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1060 static struct console stm32_console = {
1061 .name = STM32_SERIAL_NAME,
1062 .device = uart_console_device,
1063 .write = stm32_console_write,
1064 .setup = stm32_console_setup,
1065 .flags = CON_PRINTBUFFER,
1067 .data = &stm32_usart_driver,
1070 #define STM32_SERIAL_CONSOLE (&stm32_console)
1073 #define STM32_SERIAL_CONSOLE NULL
1074 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1076 static struct uart_driver stm32_usart_driver = {
1077 .driver_name = DRIVER_NAME,
1078 .dev_name = STM32_SERIAL_NAME,
1081 .nr = STM32_MAX_PORTS,
1082 .cons = STM32_SERIAL_CONSOLE,
1085 #ifdef CONFIG_PM_SLEEP
1086 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1088 struct stm32_port *stm32_port = to_stm32_port(port);
1089 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1090 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1093 if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1097 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1098 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1099 val = readl_relaxed(port->membase + ofs->cr3);
1100 val &= ~USART_CR3_WUS_MASK;
1101 /* Enable Wake up interrupt from low power on start bit */
1102 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1103 writel_relaxed(val, port->membase + ofs->cr3);
1104 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1106 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1110 static int stm32_serial_suspend(struct device *dev)
1112 struct uart_port *port = dev_get_drvdata(dev);
1114 uart_suspend_port(&stm32_usart_driver, port);
1116 if (device_may_wakeup(dev))
1117 stm32_serial_enable_wakeup(port, true);
1119 stm32_serial_enable_wakeup(port, false);
1124 static int stm32_serial_resume(struct device *dev)
1126 struct uart_port *port = dev_get_drvdata(dev);
1128 if (device_may_wakeup(dev))
1129 stm32_serial_enable_wakeup(port, false);
1131 return uart_resume_port(&stm32_usart_driver, port);
1133 #endif /* CONFIG_PM_SLEEP */
1135 static const struct dev_pm_ops stm32_serial_pm_ops = {
1136 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1139 static struct platform_driver stm32_serial_driver = {
1140 .probe = stm32_serial_probe,
1141 .remove = stm32_serial_remove,
1143 .name = DRIVER_NAME,
1144 .pm = &stm32_serial_pm_ops,
1145 .of_match_table = of_match_ptr(stm32_match),
1149 static int __init usart_init(void)
1151 static char banner[] __initdata = "STM32 USART driver initialized";
1154 pr_info("%s\n", banner);
1156 ret = uart_register_driver(&stm32_usart_driver);
1160 ret = platform_driver_register(&stm32_serial_driver);
1162 uart_unregister_driver(&stm32_usart_driver);
1167 static void __exit usart_exit(void)
1169 platform_driver_unregister(&stm32_serial_driver);
1170 uart_unregister_driver(&stm32_usart_driver);
1173 module_init(usart_init);
1174 module_exit(usart_exit);
1176 MODULE_ALIAS("platform:" DRIVER_NAME);
1177 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1178 MODULE_LICENSE("GPL v2");