1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/module.h>
37 #include <linux/of_device.h>
38 #include <linux/platform_device.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/scatterlist.h>
41 #include <linux/serial.h>
42 #include <linux/serial_sci.h>
43 #include <linux/sh_dma.h>
44 #include <linux/slab.h>
45 #include <linux/string.h>
46 #include <linux/sysrq.h>
47 #include <linux/timer.h>
48 #include <linux/tty.h>
49 #include <linux/tty_flip.h>
52 #include <asm/sh_bios.h>
53 #include <asm/platform_early.h>
56 #include "serial_mctrl_gpio.h"
59 /* Offsets into the sci_port->irqs array */
69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72 #define SCIx_IRQ_IS_MUXED(port) \
73 ((port)->irqs[SCIx_ERI_IRQ] == \
74 (port)->irqs[SCIx_RXI_IRQ]) || \
75 ((port)->irqs[SCIx_ERI_IRQ] && \
76 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79 SCI_FCK, /* Functional Clock */
80 SCI_SCK, /* Optional External Clock */
81 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
82 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
86 /* Bit x set means sampling rate x + 1 is supported */
87 #define SCI_SR(x) BIT((x) - 1)
88 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
92 SCI_SR(19) | SCI_SR(27)
94 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
95 #define max_sr(_port) fls((_port)->sampling_rate_mask)
97 /* Iterate over all supported sampling rates, from high to low */
98 #define for_each_sr(_sr, _port) \
99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
100 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102 struct plat_sci_reg {
106 struct sci_port_params {
107 const struct plat_sci_reg regs[SCIx_NR_REGS];
108 unsigned int fifosize;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int sampling_rate_mask;
112 unsigned int error_mask;
113 unsigned int error_clear;
117 struct uart_port port;
119 /* Platform configuration */
120 const struct sci_port_params *params;
121 const struct plat_sci_port *cfg;
122 unsigned int sampling_rate_mask;
123 resource_size_t reg_size;
124 struct mctrl_gpios *gpios;
127 struct clk *clks[SCI_NUM_CLKS];
128 unsigned long clk_rates[SCI_NUM_CLKS];
130 int irqs[SCIx_NR_IRQS];
131 char *irqstr[SCIx_NR_IRQS];
133 struct dma_chan *chan_tx;
134 struct dma_chan *chan_rx;
136 #ifdef CONFIG_SERIAL_SH_SCI_DMA
137 struct dma_chan *chan_tx_saved;
138 struct dma_chan *chan_rx_saved;
139 dma_cookie_t cookie_tx;
140 dma_cookie_t cookie_rx[2];
141 dma_cookie_t active_rx;
142 dma_addr_t tx_dma_addr;
143 unsigned int tx_dma_len;
144 struct scatterlist sg_rx[2];
147 struct work_struct work_tx;
148 struct hrtimer rx_timer;
149 unsigned int rx_timeout; /* microseconds */
151 unsigned int rx_frame;
153 struct timer_list rx_fifo_timer;
161 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
163 static struct sci_port sci_ports[SCI_NPORTS];
164 static unsigned long sci_ports_in_use;
165 static struct uart_driver sci_uart_driver;
167 static inline struct sci_port *
168 to_sci_port(struct uart_port *uart)
170 return container_of(uart, struct sci_port, port);
173 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
175 * Common SCI definitions, dependent on the port's regshift
178 [SCIx_SCI_REGTYPE] = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
188 .overrun_reg = SCxSR,
189 .overrun_mask = SCI_ORER,
190 .sampling_rate_mask = SCI_SR(32),
191 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
192 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
196 * Common definitions for legacy IrDA ports.
198 [SCIx_IRDA_REGTYPE] = {
200 [SCSMR] = { 0x00, 8 },
201 [SCBRR] = { 0x02, 8 },
202 [SCSCR] = { 0x04, 8 },
203 [SCxTDR] = { 0x06, 8 },
204 [SCxSR] = { 0x08, 16 },
205 [SCxRDR] = { 0x0a, 8 },
206 [SCFCR] = { 0x0c, 8 },
207 [SCFDR] = { 0x0e, 16 },
210 .overrun_reg = SCxSR,
211 .overrun_mask = SCI_ORER,
212 .sampling_rate_mask = SCI_SR(32),
213 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
214 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
218 * Common SCIFA definitions.
220 [SCIx_SCIFA_REGTYPE] = {
222 [SCSMR] = { 0x00, 16 },
223 [SCBRR] = { 0x04, 8 },
224 [SCSCR] = { 0x08, 16 },
225 [SCxTDR] = { 0x20, 8 },
226 [SCxSR] = { 0x14, 16 },
227 [SCxRDR] = { 0x24, 8 },
228 [SCFCR] = { 0x18, 16 },
229 [SCFDR] = { 0x1c, 16 },
230 [SCPCR] = { 0x30, 16 },
231 [SCPDR] = { 0x34, 16 },
234 .overrun_reg = SCxSR,
235 .overrun_mask = SCIFA_ORER,
236 .sampling_rate_mask = SCI_SR_SCIFAB,
237 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
238 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
242 * Common SCIFB definitions.
244 [SCIx_SCIFB_REGTYPE] = {
246 [SCSMR] = { 0x00, 16 },
247 [SCBRR] = { 0x04, 8 },
248 [SCSCR] = { 0x08, 16 },
249 [SCxTDR] = { 0x40, 8 },
250 [SCxSR] = { 0x14, 16 },
251 [SCxRDR] = { 0x60, 8 },
252 [SCFCR] = { 0x18, 16 },
253 [SCTFDR] = { 0x38, 16 },
254 [SCRFDR] = { 0x3c, 16 },
255 [SCPCR] = { 0x30, 16 },
256 [SCPDR] = { 0x34, 16 },
259 .overrun_reg = SCxSR,
260 .overrun_mask = SCIFA_ORER,
261 .sampling_rate_mask = SCI_SR_SCIFAB,
262 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
263 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
267 * Common SH-2(A) SCIF definitions for ports with FIFO data
270 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
272 [SCSMR] = { 0x00, 16 },
273 [SCBRR] = { 0x04, 8 },
274 [SCSCR] = { 0x08, 16 },
275 [SCxTDR] = { 0x0c, 8 },
276 [SCxSR] = { 0x10, 16 },
277 [SCxRDR] = { 0x14, 8 },
278 [SCFCR] = { 0x18, 16 },
279 [SCFDR] = { 0x1c, 16 },
280 [SCSPTR] = { 0x20, 16 },
281 [SCLSR] = { 0x24, 16 },
284 .overrun_reg = SCLSR,
285 .overrun_mask = SCLSR_ORER,
286 .sampling_rate_mask = SCI_SR(32),
287 .error_mask = SCIF_DEFAULT_ERROR_MASK,
288 .error_clear = SCIF_ERROR_CLEAR,
292 * The "SCIFA" that is in RZ/T and RZ/A2.
293 * It looks like a normal SCIF with FIFO data, but with a
294 * compressed address space. Also, the break out of interrupts
295 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
297 [SCIx_RZ_SCIFA_REGTYPE] = {
299 [SCSMR] = { 0x00, 16 },
300 [SCBRR] = { 0x02, 8 },
301 [SCSCR] = { 0x04, 16 },
302 [SCxTDR] = { 0x06, 8 },
303 [SCxSR] = { 0x08, 16 },
304 [SCxRDR] = { 0x0A, 8 },
305 [SCFCR] = { 0x0C, 16 },
306 [SCFDR] = { 0x0E, 16 },
307 [SCSPTR] = { 0x10, 16 },
308 [SCLSR] = { 0x12, 16 },
311 .overrun_reg = SCLSR,
312 .overrun_mask = SCLSR_ORER,
313 .sampling_rate_mask = SCI_SR(32),
314 .error_mask = SCIF_DEFAULT_ERROR_MASK,
315 .error_clear = SCIF_ERROR_CLEAR,
319 * Common SH-3 SCIF definitions.
321 [SCIx_SH3_SCIF_REGTYPE] = {
323 [SCSMR] = { 0x00, 8 },
324 [SCBRR] = { 0x02, 8 },
325 [SCSCR] = { 0x04, 8 },
326 [SCxTDR] = { 0x06, 8 },
327 [SCxSR] = { 0x08, 16 },
328 [SCxRDR] = { 0x0a, 8 },
329 [SCFCR] = { 0x0c, 8 },
330 [SCFDR] = { 0x0e, 16 },
333 .overrun_reg = SCLSR,
334 .overrun_mask = SCLSR_ORER,
335 .sampling_rate_mask = SCI_SR(32),
336 .error_mask = SCIF_DEFAULT_ERROR_MASK,
337 .error_clear = SCIF_ERROR_CLEAR,
341 * Common SH-4(A) SCIF(B) definitions.
343 [SCIx_SH4_SCIF_REGTYPE] = {
345 [SCSMR] = { 0x00, 16 },
346 [SCBRR] = { 0x04, 8 },
347 [SCSCR] = { 0x08, 16 },
348 [SCxTDR] = { 0x0c, 8 },
349 [SCxSR] = { 0x10, 16 },
350 [SCxRDR] = { 0x14, 8 },
351 [SCFCR] = { 0x18, 16 },
352 [SCFDR] = { 0x1c, 16 },
353 [SCSPTR] = { 0x20, 16 },
354 [SCLSR] = { 0x24, 16 },
357 .overrun_reg = SCLSR,
358 .overrun_mask = SCLSR_ORER,
359 .sampling_rate_mask = SCI_SR(32),
360 .error_mask = SCIF_DEFAULT_ERROR_MASK,
361 .error_clear = SCIF_ERROR_CLEAR,
365 * Common SCIF definitions for ports with a Baud Rate Generator for
366 * External Clock (BRG).
368 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
370 [SCSMR] = { 0x00, 16 },
371 [SCBRR] = { 0x04, 8 },
372 [SCSCR] = { 0x08, 16 },
373 [SCxTDR] = { 0x0c, 8 },
374 [SCxSR] = { 0x10, 16 },
375 [SCxRDR] = { 0x14, 8 },
376 [SCFCR] = { 0x18, 16 },
377 [SCFDR] = { 0x1c, 16 },
378 [SCSPTR] = { 0x20, 16 },
379 [SCLSR] = { 0x24, 16 },
380 [SCDL] = { 0x30, 16 },
381 [SCCKS] = { 0x34, 16 },
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR(32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
392 * Common HSCIF definitions.
394 [SCIx_HSCIF_REGTYPE] = {
396 [SCSMR] = { 0x00, 16 },
397 [SCBRR] = { 0x04, 8 },
398 [SCSCR] = { 0x08, 16 },
399 [SCxTDR] = { 0x0c, 8 },
400 [SCxSR] = { 0x10, 16 },
401 [SCxRDR] = { 0x14, 8 },
402 [SCFCR] = { 0x18, 16 },
403 [SCFDR] = { 0x1c, 16 },
404 [SCSPTR] = { 0x20, 16 },
405 [SCLSR] = { 0x24, 16 },
406 [HSSRR] = { 0x40, 16 },
407 [SCDL] = { 0x30, 16 },
408 [SCCKS] = { 0x34, 16 },
409 [HSRTRGR] = { 0x54, 16 },
410 [HSTTRGR] = { 0x58, 16 },
413 .overrun_reg = SCLSR,
414 .overrun_mask = SCLSR_ORER,
415 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
416 .error_mask = SCIF_DEFAULT_ERROR_MASK,
417 .error_clear = SCIF_ERROR_CLEAR,
421 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
424 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
426 [SCSMR] = { 0x00, 16 },
427 [SCBRR] = { 0x04, 8 },
428 [SCSCR] = { 0x08, 16 },
429 [SCxTDR] = { 0x0c, 8 },
430 [SCxSR] = { 0x10, 16 },
431 [SCxRDR] = { 0x14, 8 },
432 [SCFCR] = { 0x18, 16 },
433 [SCFDR] = { 0x1c, 16 },
434 [SCLSR] = { 0x24, 16 },
437 .overrun_reg = SCLSR,
438 .overrun_mask = SCLSR_ORER,
439 .sampling_rate_mask = SCI_SR(32),
440 .error_mask = SCIF_DEFAULT_ERROR_MASK,
441 .error_clear = SCIF_ERROR_CLEAR,
445 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
448 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
450 [SCSMR] = { 0x00, 16 },
451 [SCBRR] = { 0x04, 8 },
452 [SCSCR] = { 0x08, 16 },
453 [SCxTDR] = { 0x0c, 8 },
454 [SCxSR] = { 0x10, 16 },
455 [SCxRDR] = { 0x14, 8 },
456 [SCFCR] = { 0x18, 16 },
457 [SCFDR] = { 0x1c, 16 },
458 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
459 [SCRFDR] = { 0x20, 16 },
460 [SCSPTR] = { 0x24, 16 },
461 [SCLSR] = { 0x28, 16 },
464 .overrun_reg = SCLSR,
465 .overrun_mask = SCLSR_ORER,
466 .sampling_rate_mask = SCI_SR(32),
467 .error_mask = SCIF_DEFAULT_ERROR_MASK,
468 .error_clear = SCIF_ERROR_CLEAR,
472 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
475 [SCIx_SH7705_SCIF_REGTYPE] = {
477 [SCSMR] = { 0x00, 16 },
478 [SCBRR] = { 0x04, 8 },
479 [SCSCR] = { 0x08, 16 },
480 [SCxTDR] = { 0x20, 8 },
481 [SCxSR] = { 0x14, 16 },
482 [SCxRDR] = { 0x24, 8 },
483 [SCFCR] = { 0x18, 16 },
484 [SCFDR] = { 0x1c, 16 },
487 .overrun_reg = SCxSR,
488 .overrun_mask = SCIFA_ORER,
489 .sampling_rate_mask = SCI_SR(16),
490 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
491 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
495 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
498 * The "offset" here is rather misleading, in that it refers to an enum
499 * value relative to the port mapping rather than the fixed offset
500 * itself, which needs to be manually retrieved from the platform's
501 * register map for the given port.
503 static unsigned int sci_serial_in(struct uart_port *p, int offset)
505 const struct plat_sci_reg *reg = sci_getreg(p, offset);
508 return ioread8(p->membase + (reg->offset << p->regshift));
509 else if (reg->size == 16)
510 return ioread16(p->membase + (reg->offset << p->regshift));
512 WARN(1, "Invalid register access\n");
517 static void sci_serial_out(struct uart_port *p, int offset, int value)
519 const struct plat_sci_reg *reg = sci_getreg(p, offset);
522 iowrite8(value, p->membase + (reg->offset << p->regshift));
523 else if (reg->size == 16)
524 iowrite16(value, p->membase + (reg->offset << p->regshift));
526 WARN(1, "Invalid register access\n");
529 static void sci_port_enable(struct sci_port *sci_port)
533 if (!sci_port->port.dev)
536 pm_runtime_get_sync(sci_port->port.dev);
538 for (i = 0; i < SCI_NUM_CLKS; i++) {
539 clk_prepare_enable(sci_port->clks[i]);
540 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
542 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
545 static void sci_port_disable(struct sci_port *sci_port)
549 if (!sci_port->port.dev)
552 for (i = SCI_NUM_CLKS; i-- > 0; )
553 clk_disable_unprepare(sci_port->clks[i]);
555 pm_runtime_put_sync(sci_port->port.dev);
558 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
561 * Not all ports (such as SCIFA) will support REIE. Rather than
562 * special-casing the port type, we check the port initialization
563 * IRQ enable mask to see whether the IRQ is desired at all. If
564 * it's unset, it's logically inferred that there's no point in
567 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
570 static void sci_start_tx(struct uart_port *port)
572 struct sci_port *s = to_sci_port(port);
575 #ifdef CONFIG_SERIAL_SH_SCI_DMA
576 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
577 u16 new, scr = serial_port_in(port, SCSCR);
579 new = scr | SCSCR_TDRQE;
581 new = scr & ~SCSCR_TDRQE;
583 serial_port_out(port, SCSCR, new);
586 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
587 dma_submit_error(s->cookie_tx)) {
589 schedule_work(&s->work_tx);
593 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
594 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
595 ctrl = serial_port_in(port, SCSCR);
596 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 static void sci_stop_tx(struct uart_port *port)
604 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
605 ctrl = serial_port_in(port, SCSCR);
607 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
608 ctrl &= ~SCSCR_TDRQE;
612 serial_port_out(port, SCSCR, ctrl);
614 #ifdef CONFIG_SERIAL_SH_SCI_DMA
615 if (to_sci_port(port)->chan_tx &&
616 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
617 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
618 to_sci_port(port)->cookie_tx = -EINVAL;
623 static void sci_start_rx(struct uart_port *port)
627 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
629 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
630 ctrl &= ~SCSCR_RDRQE;
632 serial_port_out(port, SCSCR, ctrl);
635 static void sci_stop_rx(struct uart_port *port)
639 ctrl = serial_port_in(port, SCSCR);
641 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
642 ctrl &= ~SCSCR_RDRQE;
644 ctrl &= ~port_rx_irq_mask(port);
646 serial_port_out(port, SCSCR, ctrl);
649 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
651 if (port->type == PORT_SCI) {
652 /* Just store the mask */
653 serial_port_out(port, SCxSR, mask);
654 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
655 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
656 /* Only clear the status bits we want to clear */
657 serial_port_out(port, SCxSR,
658 serial_port_in(port, SCxSR) & mask);
660 /* Store the mask, clear parity/framing errors */
661 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
665 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
666 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
668 #ifdef CONFIG_CONSOLE_POLL
669 static int sci_poll_get_char(struct uart_port *port)
671 unsigned short status;
675 status = serial_port_in(port, SCxSR);
676 if (status & SCxSR_ERRORS(port)) {
677 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
683 if (!(status & SCxSR_RDxF(port)))
686 c = serial_port_in(port, SCxRDR);
689 serial_port_in(port, SCxSR);
690 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
696 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
698 unsigned short status;
701 status = serial_port_in(port, SCxSR);
702 } while (!(status & SCxSR_TDxE(port)));
704 serial_port_out(port, SCxTDR, c);
705 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
707 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
708 CONFIG_SERIAL_SH_SCI_EARLYCON */
710 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
712 struct sci_port *s = to_sci_port(port);
715 * Use port-specific handler if provided.
717 if (s->cfg->ops && s->cfg->ops->init_pins) {
718 s->cfg->ops->init_pins(port, cflag);
722 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
723 u16 data = serial_port_in(port, SCPDR);
724 u16 ctrl = serial_port_in(port, SCPCR);
726 /* Enable RXD and TXD pin functions */
727 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
728 if (to_sci_port(port)->has_rtscts) {
729 /* RTS# is output, active low, unless autorts */
730 if (!(port->mctrl & TIOCM_RTS)) {
733 } else if (!s->autorts) {
737 /* Enable RTS# pin function */
740 /* Enable CTS# pin function */
743 serial_port_out(port, SCPDR, data);
744 serial_port_out(port, SCPCR, ctrl);
745 } else if (sci_getreg(port, SCSPTR)->size) {
746 u16 status = serial_port_in(port, SCSPTR);
748 /* RTS# is always output; and active low, unless autorts */
749 status |= SCSPTR_RTSIO;
750 if (!(port->mctrl & TIOCM_RTS))
751 status |= SCSPTR_RTSDT;
752 else if (!s->autorts)
753 status &= ~SCSPTR_RTSDT;
754 /* CTS# and SCK are inputs */
755 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
756 serial_port_out(port, SCSPTR, status);
760 static int sci_txfill(struct uart_port *port)
762 struct sci_port *s = to_sci_port(port);
763 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
764 const struct plat_sci_reg *reg;
766 reg = sci_getreg(port, SCTFDR);
768 return serial_port_in(port, SCTFDR) & fifo_mask;
770 reg = sci_getreg(port, SCFDR);
772 return serial_port_in(port, SCFDR) >> 8;
774 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
777 static int sci_txroom(struct uart_port *port)
779 return port->fifosize - sci_txfill(port);
782 static int sci_rxfill(struct uart_port *port)
784 struct sci_port *s = to_sci_port(port);
785 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
786 const struct plat_sci_reg *reg;
788 reg = sci_getreg(port, SCRFDR);
790 return serial_port_in(port, SCRFDR) & fifo_mask;
792 reg = sci_getreg(port, SCFDR);
794 return serial_port_in(port, SCFDR) & fifo_mask;
796 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
799 /* ********************************************************************** *
800 * the interrupt related routines *
801 * ********************************************************************** */
803 static void sci_transmit_chars(struct uart_port *port)
805 struct circ_buf *xmit = &port->state->xmit;
806 unsigned int stopped = uart_tx_stopped(port);
807 unsigned short status;
811 status = serial_port_in(port, SCxSR);
812 if (!(status & SCxSR_TDxE(port))) {
813 ctrl = serial_port_in(port, SCSCR);
814 if (uart_circ_empty(xmit))
818 serial_port_out(port, SCSCR, ctrl);
822 count = sci_txroom(port);
830 } else if (!uart_circ_empty(xmit) && !stopped) {
831 c = xmit->buf[xmit->tail];
832 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
837 serial_port_out(port, SCxTDR, c);
840 } while (--count > 0);
842 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
844 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
845 uart_write_wakeup(port);
846 if (uart_circ_empty(xmit))
851 /* On SH3, SCIF may read end-of-break as a space->mark char */
852 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
854 static void sci_receive_chars(struct uart_port *port)
856 struct tty_port *tport = &port->state->port;
857 int i, count, copied = 0;
858 unsigned short status;
861 status = serial_port_in(port, SCxSR);
862 if (!(status & SCxSR_RDxF(port)))
866 /* Don't copy more bytes than there is room for in the buffer */
867 count = tty_buffer_request_room(tport, sci_rxfill(port));
869 /* If for any reason we can't copy more data, we're done! */
873 if (port->type == PORT_SCI) {
874 char c = serial_port_in(port, SCxRDR);
875 if (uart_handle_sysrq_char(port, c))
878 tty_insert_flip_char(tport, c, TTY_NORMAL);
880 for (i = 0; i < count; i++) {
883 if (port->type == PORT_SCIF ||
884 port->type == PORT_HSCIF) {
885 status = serial_port_in(port, SCxSR);
886 c = serial_port_in(port, SCxRDR);
888 c = serial_port_in(port, SCxRDR);
889 status = serial_port_in(port, SCxSR);
891 if (uart_handle_sysrq_char(port, c)) {
896 /* Store data and status */
897 if (status & SCxSR_FER(port)) {
899 port->icount.frame++;
900 dev_notice(port->dev, "frame error\n");
901 } else if (status & SCxSR_PER(port)) {
903 port->icount.parity++;
904 dev_notice(port->dev, "parity error\n");
908 tty_insert_flip_char(tport, c, flag);
912 serial_port_in(port, SCxSR); /* dummy read */
913 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
916 port->icount.rx += count;
920 /* Tell the rest of the system the news. New characters! */
921 tty_flip_buffer_push(tport);
923 /* TTY buffers full; read from RX reg to prevent lockup */
924 serial_port_in(port, SCxRDR);
925 serial_port_in(port, SCxSR); /* dummy read */
926 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
930 static int sci_handle_errors(struct uart_port *port)
933 unsigned short status = serial_port_in(port, SCxSR);
934 struct tty_port *tport = &port->state->port;
935 struct sci_port *s = to_sci_port(port);
937 /* Handle overruns */
938 if (status & s->params->overrun_mask) {
939 port->icount.overrun++;
942 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
945 dev_notice(port->dev, "overrun error\n");
948 if (status & SCxSR_FER(port)) {
950 port->icount.frame++;
952 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
955 dev_notice(port->dev, "frame error\n");
958 if (status & SCxSR_PER(port)) {
960 port->icount.parity++;
962 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
965 dev_notice(port->dev, "parity error\n");
969 tty_flip_buffer_push(tport);
974 static int sci_handle_fifo_overrun(struct uart_port *port)
976 struct tty_port *tport = &port->state->port;
977 struct sci_port *s = to_sci_port(port);
978 const struct plat_sci_reg *reg;
982 reg = sci_getreg(port, s->params->overrun_reg);
986 status = serial_port_in(port, s->params->overrun_reg);
987 if (status & s->params->overrun_mask) {
988 status &= ~s->params->overrun_mask;
989 serial_port_out(port, s->params->overrun_reg, status);
991 port->icount.overrun++;
993 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
994 tty_flip_buffer_push(tport);
996 dev_dbg(port->dev, "overrun error\n");
1003 static int sci_handle_breaks(struct uart_port *port)
1006 unsigned short status = serial_port_in(port, SCxSR);
1007 struct tty_port *tport = &port->state->port;
1009 if (uart_handle_break(port))
1012 if (status & SCxSR_BRK(port)) {
1015 /* Notify of BREAK */
1016 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1019 dev_dbg(port->dev, "BREAK detected\n");
1023 tty_flip_buffer_push(tport);
1025 copied += sci_handle_fifo_overrun(port);
1030 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1034 if (rx_trig >= port->fifosize)
1035 rx_trig = port->fifosize - 1;
1039 /* HSCIF can be set to an arbitrary level. */
1040 if (sci_getreg(port, HSRTRGR)->size) {
1041 serial_port_out(port, HSRTRGR, rx_trig);
1045 switch (port->type) {
1050 } else if (rx_trig < 8) {
1053 } else if (rx_trig < 14) {
1057 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1066 } else if (rx_trig < 32) {
1069 } else if (rx_trig < 48) {
1073 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1078 WARN(1, "unknown FIFO configuration");
1082 serial_port_out(port, SCFCR,
1083 (serial_port_in(port, SCFCR) &
1084 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1089 static int scif_rtrg_enabled(struct uart_port *port)
1091 if (sci_getreg(port, HSRTRGR)->size)
1092 return serial_port_in(port, HSRTRGR) != 0;
1094 return (serial_port_in(port, SCFCR) &
1095 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1098 static void rx_fifo_timer_fn(struct timer_list *t)
1100 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1101 struct uart_port *port = &s->port;
1103 dev_dbg(port->dev, "Rx timed out\n");
1104 scif_set_rtrg(port, 1);
1107 static ssize_t rx_fifo_trigger_show(struct device *dev,
1108 struct device_attribute *attr, char *buf)
1110 struct uart_port *port = dev_get_drvdata(dev);
1111 struct sci_port *sci = to_sci_port(port);
1113 return sprintf(buf, "%d\n", sci->rx_trigger);
1116 static ssize_t rx_fifo_trigger_store(struct device *dev,
1117 struct device_attribute *attr,
1118 const char *buf, size_t count)
1120 struct uart_port *port = dev_get_drvdata(dev);
1121 struct sci_port *sci = to_sci_port(port);
1125 ret = kstrtol(buf, 0, &r);
1129 sci->rx_trigger = scif_set_rtrg(port, r);
1130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1131 scif_set_rtrg(port, 1);
1136 static DEVICE_ATTR_RW(rx_fifo_trigger);
1138 static ssize_t rx_fifo_timeout_show(struct device *dev,
1139 struct device_attribute *attr,
1142 struct uart_port *port = dev_get_drvdata(dev);
1143 struct sci_port *sci = to_sci_port(port);
1146 if (port->type == PORT_HSCIF)
1147 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1149 v = sci->rx_fifo_timeout;
1151 return sprintf(buf, "%d\n", v);
1154 static ssize_t rx_fifo_timeout_store(struct device *dev,
1155 struct device_attribute *attr,
1159 struct uart_port *port = dev_get_drvdata(dev);
1160 struct sci_port *sci = to_sci_port(port);
1164 ret = kstrtol(buf, 0, &r);
1168 if (port->type == PORT_HSCIF) {
1171 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1173 sci->rx_fifo_timeout = r;
1174 scif_set_rtrg(port, 1);
1176 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1182 static DEVICE_ATTR_RW(rx_fifo_timeout);
1185 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1186 static void sci_dma_tx_complete(void *arg)
1188 struct sci_port *s = arg;
1189 struct uart_port *port = &s->port;
1190 struct circ_buf *xmit = &port->state->xmit;
1191 unsigned long flags;
1193 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1195 spin_lock_irqsave(&port->lock, flags);
1197 xmit->tail += s->tx_dma_len;
1198 xmit->tail &= UART_XMIT_SIZE - 1;
1200 port->icount.tx += s->tx_dma_len;
1202 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1203 uart_write_wakeup(port);
1205 if (!uart_circ_empty(xmit)) {
1207 schedule_work(&s->work_tx);
1209 s->cookie_tx = -EINVAL;
1210 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1211 u16 ctrl = serial_port_in(port, SCSCR);
1212 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1216 spin_unlock_irqrestore(&port->lock, flags);
1219 /* Locking: called with port lock held */
1220 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1222 struct uart_port *port = &s->port;
1223 struct tty_port *tport = &port->state->port;
1226 copied = tty_insert_flip_string(tport, buf, count);
1228 port->icount.buf_overrun++;
1230 port->icount.rx += copied;
1235 static int sci_dma_rx_find_active(struct sci_port *s)
1239 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1240 if (s->active_rx == s->cookie_rx[i])
1246 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1251 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1252 s->cookie_rx[i] = -EINVAL;
1256 static void sci_dma_rx_release(struct sci_port *s)
1258 struct dma_chan *chan = s->chan_rx_saved;
1260 s->chan_rx_saved = NULL;
1261 sci_dma_rx_chan_invalidate(s);
1262 dmaengine_terminate_sync(chan);
1263 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1264 sg_dma_address(&s->sg_rx[0]));
1265 dma_release_channel(chan);
1268 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1270 long sec = usec / 1000000;
1271 long nsec = (usec % 1000000) * 1000;
1272 ktime_t t = ktime_set(sec, nsec);
1274 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1277 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1279 struct uart_port *port = &s->port;
1282 /* Direct new serial port interrupts back to CPU */
1283 scr = serial_port_in(port, SCSCR);
1284 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1285 scr &= ~SCSCR_RDRQE;
1286 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1288 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1291 static void sci_dma_rx_complete(void *arg)
1293 struct sci_port *s = arg;
1294 struct dma_chan *chan = s->chan_rx;
1295 struct uart_port *port = &s->port;
1296 struct dma_async_tx_descriptor *desc;
1297 unsigned long flags;
1298 int active, count = 0;
1300 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1303 spin_lock_irqsave(&port->lock, flags);
1305 active = sci_dma_rx_find_active(s);
1307 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1309 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1312 tty_flip_buffer_push(&port->state->port);
1314 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1320 desc->callback = sci_dma_rx_complete;
1321 desc->callback_param = s;
1322 s->cookie_rx[active] = dmaengine_submit(desc);
1323 if (dma_submit_error(s->cookie_rx[active]))
1326 s->active_rx = s->cookie_rx[!active];
1328 dma_async_issue_pending(chan);
1330 spin_unlock_irqrestore(&port->lock, flags);
1331 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1332 __func__, s->cookie_rx[active], active, s->active_rx);
1336 spin_unlock_irqrestore(&port->lock, flags);
1337 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1339 spin_lock_irqsave(&port->lock, flags);
1340 dmaengine_terminate_async(chan);
1341 sci_dma_rx_chan_invalidate(s);
1342 sci_dma_rx_reenable_irq(s);
1343 spin_unlock_irqrestore(&port->lock, flags);
1346 static void sci_dma_tx_release(struct sci_port *s)
1348 struct dma_chan *chan = s->chan_tx_saved;
1350 cancel_work_sync(&s->work_tx);
1351 s->chan_tx_saved = s->chan_tx = NULL;
1352 s->cookie_tx = -EINVAL;
1353 dmaengine_terminate_sync(chan);
1354 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1356 dma_release_channel(chan);
1359 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1361 struct dma_chan *chan = s->chan_rx;
1362 struct uart_port *port = &s->port;
1363 unsigned long flags;
1366 for (i = 0; i < 2; i++) {
1367 struct scatterlist *sg = &s->sg_rx[i];
1368 struct dma_async_tx_descriptor *desc;
1370 desc = dmaengine_prep_slave_sg(chan,
1371 sg, 1, DMA_DEV_TO_MEM,
1372 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1376 desc->callback = sci_dma_rx_complete;
1377 desc->callback_param = s;
1378 s->cookie_rx[i] = dmaengine_submit(desc);
1379 if (dma_submit_error(s->cookie_rx[i]))
1384 s->active_rx = s->cookie_rx[0];
1386 dma_async_issue_pending(chan);
1391 if (!port_lock_held)
1392 spin_lock_irqsave(&port->lock, flags);
1394 dmaengine_terminate_async(chan);
1395 sci_dma_rx_chan_invalidate(s);
1397 if (!port_lock_held)
1398 spin_unlock_irqrestore(&port->lock, flags);
1402 static void sci_dma_tx_work_fn(struct work_struct *work)
1404 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1405 struct dma_async_tx_descriptor *desc;
1406 struct dma_chan *chan = s->chan_tx;
1407 struct uart_port *port = &s->port;
1408 struct circ_buf *xmit = &port->state->xmit;
1409 unsigned long flags;
1415 * Port xmit buffer is already mapped, and it is one page... Just adjust
1416 * offsets and lengths. Since it is a circular buffer, we have to
1417 * transmit till the end, and then the rest. Take the port lock to get a
1418 * consistent xmit buffer state.
1420 spin_lock_irq(&port->lock);
1423 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1424 s->tx_dma_len = min_t(unsigned int,
1425 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1426 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1427 if (!s->tx_dma_len) {
1428 /* Transmit buffer has been flushed */
1429 spin_unlock_irq(&port->lock);
1433 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1435 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1437 spin_unlock_irq(&port->lock);
1438 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1442 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1445 desc->callback = sci_dma_tx_complete;
1446 desc->callback_param = s;
1447 s->cookie_tx = dmaengine_submit(desc);
1448 if (dma_submit_error(s->cookie_tx)) {
1449 spin_unlock_irq(&port->lock);
1450 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1454 spin_unlock_irq(&port->lock);
1455 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1456 __func__, xmit->buf, tail, head, s->cookie_tx);
1458 dma_async_issue_pending(chan);
1462 spin_lock_irqsave(&port->lock, flags);
1465 spin_unlock_irqrestore(&port->lock, flags);
1469 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1471 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1472 struct dma_chan *chan = s->chan_rx;
1473 struct uart_port *port = &s->port;
1474 struct dma_tx_state state;
1475 enum dma_status status;
1476 unsigned long flags;
1480 dev_dbg(port->dev, "DMA Rx timed out\n");
1482 spin_lock_irqsave(&port->lock, flags);
1484 active = sci_dma_rx_find_active(s);
1486 spin_unlock_irqrestore(&port->lock, flags);
1487 return HRTIMER_NORESTART;
1490 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1491 if (status == DMA_COMPLETE) {
1492 spin_unlock_irqrestore(&port->lock, flags);
1493 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1494 s->active_rx, active);
1496 /* Let packet complete handler take care of the packet */
1497 return HRTIMER_NORESTART;
1500 dmaengine_pause(chan);
1503 * sometimes DMA transfer doesn't stop even if it is stopped and
1504 * data keeps on coming until transaction is complete so check
1505 * for DMA_COMPLETE again
1506 * Let packet complete handler take care of the packet
1508 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1509 if (status == DMA_COMPLETE) {
1510 spin_unlock_irqrestore(&port->lock, flags);
1511 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1512 return HRTIMER_NORESTART;
1515 /* Handle incomplete DMA receive */
1516 dmaengine_terminate_async(s->chan_rx);
1517 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1520 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1522 tty_flip_buffer_push(&port->state->port);
1525 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1526 sci_dma_rx_submit(s, true);
1528 sci_dma_rx_reenable_irq(s);
1530 spin_unlock_irqrestore(&port->lock, flags);
1532 return HRTIMER_NORESTART;
1535 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1536 enum dma_transfer_direction dir)
1538 struct dma_chan *chan;
1539 struct dma_slave_config cfg;
1542 chan = dma_request_slave_channel(port->dev,
1543 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1545 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1549 memset(&cfg, 0, sizeof(cfg));
1550 cfg.direction = dir;
1551 if (dir == DMA_MEM_TO_DEV) {
1552 cfg.dst_addr = port->mapbase +
1553 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1554 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1556 cfg.src_addr = port->mapbase +
1557 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1558 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1561 ret = dmaengine_slave_config(chan, &cfg);
1563 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1564 dma_release_channel(chan);
1571 static void sci_request_dma(struct uart_port *port)
1573 struct sci_port *s = to_sci_port(port);
1574 struct dma_chan *chan;
1576 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1579 * DMA on console may interfere with Kernel log messages which use
1580 * plain putchar(). So, simply don't use it with a console.
1582 if (uart_console(port))
1585 if (!port->dev->of_node)
1588 s->cookie_tx = -EINVAL;
1591 * Don't request a dma channel if no channel was specified
1592 * in the device tree.
1594 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1597 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1598 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1600 /* UART circular tx buffer is an aligned page. */
1601 s->tx_dma_addr = dma_map_single(chan->device->dev,
1602 port->state->xmit.buf,
1605 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1606 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1607 dma_release_channel(chan);
1609 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1610 __func__, UART_XMIT_SIZE,
1611 port->state->xmit.buf, &s->tx_dma_addr);
1613 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1614 s->chan_tx_saved = s->chan_tx = chan;
1618 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1619 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1625 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1626 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1630 "Failed to allocate Rx dma buffer, using PIO\n");
1631 dma_release_channel(chan);
1635 for (i = 0; i < 2; i++) {
1636 struct scatterlist *sg = &s->sg_rx[i];
1638 sg_init_table(sg, 1);
1640 sg_dma_address(sg) = dma;
1641 sg_dma_len(sg) = s->buf_len_rx;
1643 buf += s->buf_len_rx;
1644 dma += s->buf_len_rx;
1647 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1648 s->rx_timer.function = sci_dma_rx_timer_fn;
1650 s->chan_rx_saved = s->chan_rx = chan;
1652 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1653 sci_dma_rx_submit(s, false);
1657 static void sci_free_dma(struct uart_port *port)
1659 struct sci_port *s = to_sci_port(port);
1661 if (s->chan_tx_saved)
1662 sci_dma_tx_release(s);
1663 if (s->chan_rx_saved)
1664 sci_dma_rx_release(s);
1667 static void sci_flush_buffer(struct uart_port *port)
1669 struct sci_port *s = to_sci_port(port);
1672 * In uart_flush_buffer(), the xmit circular buffer has just been
1673 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1678 dmaengine_terminate_async(s->chan_tx);
1679 s->cookie_tx = -EINVAL;
1682 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1683 static inline void sci_request_dma(struct uart_port *port)
1687 static inline void sci_free_dma(struct uart_port *port)
1691 #define sci_flush_buffer NULL
1692 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1694 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1696 struct uart_port *port = ptr;
1697 struct sci_port *s = to_sci_port(port);
1699 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1701 u16 scr = serial_port_in(port, SCSCR);
1702 u16 ssr = serial_port_in(port, SCxSR);
1704 /* Disable future Rx interrupts */
1705 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1706 disable_irq_nosync(irq);
1709 if (sci_dma_rx_submit(s, false) < 0)
1714 serial_port_out(port, SCSCR, scr);
1715 /* Clear current interrupt */
1716 serial_port_out(port, SCxSR,
1717 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1718 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1719 jiffies, s->rx_timeout);
1720 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1728 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1729 if (!scif_rtrg_enabled(port))
1730 scif_set_rtrg(port, s->rx_trigger);
1732 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1733 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1736 /* I think sci_receive_chars has to be called irrespective
1737 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1740 sci_receive_chars(port);
1745 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1747 struct uart_port *port = ptr;
1748 unsigned long flags;
1750 spin_lock_irqsave(&port->lock, flags);
1751 sci_transmit_chars(port);
1752 spin_unlock_irqrestore(&port->lock, flags);
1757 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1759 struct uart_port *port = ptr;
1762 sci_handle_breaks(port);
1764 /* drop invalid character received before break was detected */
1765 serial_port_in(port, SCxRDR);
1767 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1772 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1774 struct uart_port *port = ptr;
1775 struct sci_port *s = to_sci_port(port);
1777 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1778 /* Break and Error interrupts are muxed */
1779 unsigned short ssr_status = serial_port_in(port, SCxSR);
1781 /* Break Interrupt */
1782 if (ssr_status & SCxSR_BRK(port))
1783 sci_br_interrupt(irq, ptr);
1786 if (!(ssr_status & SCxSR_ERRORS(port)))
1791 if (port->type == PORT_SCI) {
1792 if (sci_handle_errors(port)) {
1793 /* discard character in rx buffer */
1794 serial_port_in(port, SCxSR);
1795 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1798 sci_handle_fifo_overrun(port);
1800 sci_receive_chars(port);
1803 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1805 /* Kick the transmission */
1807 sci_tx_interrupt(irq, ptr);
1812 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1814 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1815 struct uart_port *port = ptr;
1816 struct sci_port *s = to_sci_port(port);
1817 irqreturn_t ret = IRQ_NONE;
1819 ssr_status = serial_port_in(port, SCxSR);
1820 scr_status = serial_port_in(port, SCSCR);
1821 if (s->params->overrun_reg == SCxSR)
1822 orer_status = ssr_status;
1823 else if (sci_getreg(port, s->params->overrun_reg)->size)
1824 orer_status = serial_port_in(port, s->params->overrun_reg);
1826 err_enabled = scr_status & port_rx_irq_mask(port);
1829 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1831 ret = sci_tx_interrupt(irq, ptr);
1834 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1837 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1838 (scr_status & SCSCR_RIE))
1839 ret = sci_rx_interrupt(irq, ptr);
1841 /* Error Interrupt */
1842 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1843 ret = sci_er_interrupt(irq, ptr);
1845 /* Break Interrupt */
1846 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1847 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1848 ret = sci_br_interrupt(irq, ptr);
1850 /* Overrun Interrupt */
1851 if (orer_status & s->params->overrun_mask) {
1852 sci_handle_fifo_overrun(port);
1859 static const struct sci_irq_desc {
1861 irq_handler_t handler;
1862 } sci_irq_desc[] = {
1864 * Split out handlers, the default case.
1868 .handler = sci_er_interrupt,
1873 .handler = sci_rx_interrupt,
1878 .handler = sci_tx_interrupt,
1883 .handler = sci_br_interrupt,
1888 .handler = sci_rx_interrupt,
1893 .handler = sci_tx_interrupt,
1897 * Special muxed handler.
1901 .handler = sci_mpxed_interrupt,
1905 static int sci_request_irq(struct sci_port *port)
1907 struct uart_port *up = &port->port;
1908 int i, j, w, ret = 0;
1910 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1911 const struct sci_irq_desc *desc;
1914 /* Check if already registered (muxed) */
1915 for (w = 0; w < i; w++)
1916 if (port->irqs[w] == port->irqs[i])
1921 if (SCIx_IRQ_IS_MUXED(port)) {
1925 irq = port->irqs[i];
1928 * Certain port types won't support all of the
1929 * available interrupt sources.
1931 if (unlikely(irq < 0))
1935 desc = sci_irq_desc + i;
1936 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1937 dev_name(up->dev), desc->desc);
1938 if (!port->irqstr[j]) {
1943 ret = request_irq(irq, desc->handler, up->irqflags,
1944 port->irqstr[j], port);
1945 if (unlikely(ret)) {
1946 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1955 free_irq(port->irqs[i], port);
1959 kfree(port->irqstr[j]);
1964 static void sci_free_irq(struct sci_port *port)
1969 * Intentionally in reverse order so we iterate over the muxed
1972 for (i = 0; i < SCIx_NR_IRQS; i++) {
1973 int irq = port->irqs[i];
1976 * Certain port types won't support all of the available
1977 * interrupt sources.
1979 if (unlikely(irq < 0))
1982 /* Check if already freed (irq was muxed) */
1983 for (j = 0; j < i; j++)
1984 if (port->irqs[j] == irq)
1989 free_irq(port->irqs[i], port);
1990 kfree(port->irqstr[i]);
1992 if (SCIx_IRQ_IS_MUXED(port)) {
1993 /* If there's only one IRQ, we're done. */
1999 static unsigned int sci_tx_empty(struct uart_port *port)
2001 unsigned short status = serial_port_in(port, SCxSR);
2002 unsigned short in_tx_fifo = sci_txfill(port);
2004 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2007 static void sci_set_rts(struct uart_port *port, bool state)
2009 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2010 u16 data = serial_port_in(port, SCPDR);
2014 data &= ~SCPDR_RTSD;
2017 serial_port_out(port, SCPDR, data);
2019 /* RTS# is output */
2020 serial_port_out(port, SCPCR,
2021 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2022 } else if (sci_getreg(port, SCSPTR)->size) {
2023 u16 ctrl = serial_port_in(port, SCSPTR);
2027 ctrl &= ~SCSPTR_RTSDT;
2029 ctrl |= SCSPTR_RTSDT;
2030 serial_port_out(port, SCSPTR, ctrl);
2034 static bool sci_get_cts(struct uart_port *port)
2036 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2038 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2039 } else if (sci_getreg(port, SCSPTR)->size) {
2041 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2048 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2049 * CTS/RTS is supported in hardware by at least one port and controlled
2050 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2051 * handled via the ->init_pins() op, which is a bit of a one-way street,
2052 * lacking any ability to defer pin control -- this will later be
2053 * converted over to the GPIO framework).
2055 * Other modes (such as loopback) are supported generically on certain
2056 * port types, but not others. For these it's sufficient to test for the
2057 * existence of the support register and simply ignore the port type.
2059 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2061 struct sci_port *s = to_sci_port(port);
2063 if (mctrl & TIOCM_LOOP) {
2064 const struct plat_sci_reg *reg;
2067 * Standard loopback mode for SCFCR ports.
2069 reg = sci_getreg(port, SCFCR);
2071 serial_port_out(port, SCFCR,
2072 serial_port_in(port, SCFCR) |
2076 mctrl_gpio_set(s->gpios, mctrl);
2081 if (!(mctrl & TIOCM_RTS)) {
2082 /* Disable Auto RTS */
2083 serial_port_out(port, SCFCR,
2084 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2087 sci_set_rts(port, 0);
2088 } else if (s->autorts) {
2089 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2090 /* Enable RTS# pin function */
2091 serial_port_out(port, SCPCR,
2092 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2095 /* Enable Auto RTS */
2096 serial_port_out(port, SCFCR,
2097 serial_port_in(port, SCFCR) | SCFCR_MCE);
2100 sci_set_rts(port, 1);
2104 static unsigned int sci_get_mctrl(struct uart_port *port)
2106 struct sci_port *s = to_sci_port(port);
2107 struct mctrl_gpios *gpios = s->gpios;
2108 unsigned int mctrl = 0;
2110 mctrl_gpio_get(gpios, &mctrl);
2113 * CTS/RTS is handled in hardware when supported, while nothing
2117 if (sci_get_cts(port))
2119 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2122 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2124 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2130 static void sci_enable_ms(struct uart_port *port)
2132 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2135 static void sci_break_ctl(struct uart_port *port, int break_state)
2137 unsigned short scscr, scsptr;
2138 unsigned long flags;
2140 /* check wheter the port has SCSPTR */
2141 if (!sci_getreg(port, SCSPTR)->size) {
2143 * Not supported by hardware. Most parts couple break and rx
2144 * interrupts together, with break detection always enabled.
2149 spin_lock_irqsave(&port->lock, flags);
2150 scsptr = serial_port_in(port, SCSPTR);
2151 scscr = serial_port_in(port, SCSCR);
2153 if (break_state == -1) {
2154 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2157 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2161 serial_port_out(port, SCSPTR, scsptr);
2162 serial_port_out(port, SCSCR, scscr);
2163 spin_unlock_irqrestore(&port->lock, flags);
2166 static int sci_startup(struct uart_port *port)
2168 struct sci_port *s = to_sci_port(port);
2171 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2173 sci_request_dma(port);
2175 ret = sci_request_irq(s);
2176 if (unlikely(ret < 0)) {
2184 static void sci_shutdown(struct uart_port *port)
2186 struct sci_port *s = to_sci_port(port);
2187 unsigned long flags;
2190 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2193 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2195 spin_lock_irqsave(&port->lock, flags);
2199 * Stop RX and TX, disable related interrupts, keep clock source
2200 * and HSCIF TOT bits
2202 scr = serial_port_in(port, SCSCR);
2203 serial_port_out(port, SCSCR, scr &
2204 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2205 spin_unlock_irqrestore(&port->lock, flags);
2207 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2208 if (s->chan_rx_saved) {
2209 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2211 hrtimer_cancel(&s->rx_timer);
2215 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2216 del_timer_sync(&s->rx_fifo_timer);
2221 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2224 unsigned long freq = s->clk_rates[SCI_SCK];
2225 int err, min_err = INT_MAX;
2228 if (s->port.type != PORT_HSCIF)
2231 for_each_sr(sr, s) {
2232 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2233 if (abs(err) >= abs(min_err))
2243 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2248 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2249 unsigned long freq, unsigned int *dlr,
2252 int err, min_err = INT_MAX;
2253 unsigned int sr, dl;
2255 if (s->port.type != PORT_HSCIF)
2258 for_each_sr(sr, s) {
2259 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2260 dl = clamp(dl, 1U, 65535U);
2262 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2263 if (abs(err) >= abs(min_err))
2274 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2275 min_err, *dlr, *srr + 1);
2279 /* calculate sample rate, BRR, and clock select */
2280 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2281 unsigned int *brr, unsigned int *srr,
2284 unsigned long freq = s->clk_rates[SCI_FCK];
2285 unsigned int sr, br, prediv, scrate, c;
2286 int err, min_err = INT_MAX;
2288 if (s->port.type != PORT_HSCIF)
2292 * Find the combination of sample rate and clock select with the
2293 * smallest deviation from the desired baud rate.
2294 * Prefer high sample rates to maximise the receive margin.
2296 * M: Receive margin (%)
2297 * N: Ratio of bit rate to clock (N = sampling rate)
2298 * D: Clock duty (D = 0 to 1.0)
2299 * L: Frame length (L = 9 to 12)
2300 * F: Absolute value of clock frequency deviation
2302 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2303 * (|D - 0.5| / N * (1 + F))|
2304 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2306 for_each_sr(sr, s) {
2307 for (c = 0; c <= 3; c++) {
2308 /* integerized formulas from HSCIF documentation */
2309 prediv = sr * (1 << (2 * c + 1));
2312 * We need to calculate:
2314 * br = freq / (prediv * bps) clamped to [1..256]
2315 * err = freq / (br * prediv) - bps
2317 * Watch out for overflow when calculating the desired
2318 * sampling clock rate!
2320 if (bps > UINT_MAX / prediv)
2323 scrate = prediv * bps;
2324 br = DIV_ROUND_CLOSEST(freq, scrate);
2325 br = clamp(br, 1U, 256U);
2327 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2328 if (abs(err) >= abs(min_err))
2342 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2343 min_err, *brr, *srr + 1, *cks);
2347 static void sci_reset(struct uart_port *port)
2349 const struct plat_sci_reg *reg;
2350 unsigned int status;
2351 struct sci_port *s = to_sci_port(port);
2353 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2355 reg = sci_getreg(port, SCFCR);
2357 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2359 sci_clear_SCxSR(port,
2360 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2361 SCxSR_BREAK_CLEAR(port));
2362 if (sci_getreg(port, SCLSR)->size) {
2363 status = serial_port_in(port, SCLSR);
2364 status &= ~(SCLSR_TO | SCLSR_ORER);
2365 serial_port_out(port, SCLSR, status);
2368 if (s->rx_trigger > 1) {
2369 if (s->rx_fifo_timeout) {
2370 scif_set_rtrg(port, 1);
2371 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2373 if (port->type == PORT_SCIFA ||
2374 port->type == PORT_SCIFB)
2375 scif_set_rtrg(port, 1);
2377 scif_set_rtrg(port, s->rx_trigger);
2382 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2383 struct ktermios *old)
2385 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2386 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2387 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2388 struct sci_port *s = to_sci_port(port);
2389 const struct plat_sci_reg *reg;
2390 int min_err = INT_MAX, err;
2391 unsigned long max_freq = 0;
2393 unsigned long flags;
2395 if ((termios->c_cflag & CSIZE) == CS7) {
2396 smr_val |= SCSMR_CHR;
2398 termios->c_cflag &= ~CSIZE;
2399 termios->c_cflag |= CS8;
2401 if (termios->c_cflag & PARENB)
2402 smr_val |= SCSMR_PE;
2403 if (termios->c_cflag & PARODD)
2404 smr_val |= SCSMR_PE | SCSMR_ODD;
2405 if (termios->c_cflag & CSTOPB)
2406 smr_val |= SCSMR_STOP;
2409 * earlyprintk comes here early on with port->uartclk set to zero.
2410 * the clock framework is not up and running at this point so here
2411 * we assume that 115200 is the maximum baud rate. please note that
2412 * the baud rate is not programmed during earlyprintk - it is assumed
2413 * that the previous boot loader has enabled required clocks and
2414 * setup the baud rate generator hardware for us already.
2416 if (!port->uartclk) {
2417 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2421 for (i = 0; i < SCI_NUM_CLKS; i++)
2422 max_freq = max(max_freq, s->clk_rates[i]);
2424 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2429 * There can be multiple sources for the sampling clock. Find the one
2430 * that gives us the smallest deviation from the desired baud rate.
2433 /* Optional Undivided External Clock */
2434 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2435 port->type != PORT_SCIFB) {
2436 err = sci_sck_calc(s, baud, &srr1);
2437 if (abs(err) < abs(min_err)) {
2439 scr_val = SCSCR_CKE1;
2448 /* Optional BRG Frequency Divided External Clock */
2449 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2450 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2452 if (abs(err) < abs(min_err)) {
2453 best_clk = SCI_SCIF_CLK;
2454 scr_val = SCSCR_CKE1;
2464 /* Optional BRG Frequency Divided Internal Clock */
2465 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2466 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2468 if (abs(err) < abs(min_err)) {
2469 best_clk = SCI_BRG_INT;
2470 scr_val = SCSCR_CKE1;
2480 /* Divided Functional Clock using standard Bit Rate Register */
2481 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2482 if (abs(err) < abs(min_err)) {
2493 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2494 s->clks[best_clk], baud, min_err);
2499 * Program the optional External Baud Rate Generator (BRG) first.
2500 * It controls the mux to select (H)SCK or frequency divided clock.
2502 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2503 serial_port_out(port, SCDL, dl);
2504 serial_port_out(port, SCCKS, sccks);
2507 spin_lock_irqsave(&port->lock, flags);
2511 uart_update_timeout(port, termios->c_cflag, baud);
2513 /* byte size and parity */
2514 switch (termios->c_cflag & CSIZE) {
2529 if (termios->c_cflag & CSTOPB)
2531 if (termios->c_cflag & PARENB)
2534 if (best_clk >= 0) {
2535 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2537 case 5: smr_val |= SCSMR_SRC_5; break;
2538 case 7: smr_val |= SCSMR_SRC_7; break;
2539 case 11: smr_val |= SCSMR_SRC_11; break;
2540 case 13: smr_val |= SCSMR_SRC_13; break;
2541 case 16: smr_val |= SCSMR_SRC_16; break;
2542 case 17: smr_val |= SCSMR_SRC_17; break;
2543 case 19: smr_val |= SCSMR_SRC_19; break;
2544 case 27: smr_val |= SCSMR_SRC_27; break;
2547 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2548 serial_port_out(port, SCSMR, smr_val);
2549 serial_port_out(port, SCBRR, brr);
2550 if (sci_getreg(port, HSSRR)->size) {
2551 unsigned int hssrr = srr | HSCIF_SRE;
2552 /* Calculate deviation from intended rate at the
2553 * center of the last stop bit in sampling clocks.
2555 int last_stop = bits * 2 - 1;
2556 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2560 if (abs(deviation) >= 2) {
2561 /* At least two sampling clocks off at the
2562 * last stop bit; we can increase the error
2563 * margin by shifting the sampling point.
2565 int shift = clamp(deviation / 2, -8, 7);
2567 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2569 hssrr |= HSCIF_SRDE;
2571 serial_port_out(port, HSSRR, hssrr);
2574 /* Wait one bit interval */
2575 udelay((1000000 + (baud - 1)) / baud);
2577 /* Don't touch the bit rate configuration */
2578 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2579 smr_val |= serial_port_in(port, SCSMR) &
2580 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2581 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2582 serial_port_out(port, SCSMR, smr_val);
2585 sci_init_pins(port, termios->c_cflag);
2587 port->status &= ~UPSTAT_AUTOCTS;
2589 reg = sci_getreg(port, SCFCR);
2591 unsigned short ctrl = serial_port_in(port, SCFCR);
2593 if ((port->flags & UPF_HARD_FLOW) &&
2594 (termios->c_cflag & CRTSCTS)) {
2595 /* There is no CTS interrupt to restart the hardware */
2596 port->status |= UPSTAT_AUTOCTS;
2597 /* MCE is enabled when RTS is raised */
2602 * As we've done a sci_reset() above, ensure we don't
2603 * interfere with the FIFOs while toggling MCE. As the
2604 * reset values could still be set, simply mask them out.
2606 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2608 serial_port_out(port, SCFCR, ctrl);
2610 if (port->flags & UPF_HARD_FLOW) {
2611 /* Refresh (Auto) RTS */
2612 sci_set_mctrl(port, port->mctrl);
2615 scr_val |= SCSCR_RE | SCSCR_TE |
2616 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2617 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2618 if ((srr + 1 == 5) &&
2619 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2621 * In asynchronous mode, when the sampling rate is 1/5, first
2622 * received data may become invalid on some SCIFA and SCIFB.
2623 * To avoid this problem wait more than 1 serial data time (1
2624 * bit time x serial data number) after setting SCSCR.RE = 1.
2626 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2630 * Calculate delay for 2 DMA buffers (4 FIFO).
2631 * See serial_core.c::uart_update_timeout().
2632 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2633 * function calculates 1 jiffie for the data plus 5 jiffies for the
2634 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2635 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2636 * value obtained by this formula is too small. Therefore, if the value
2637 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2639 s->rx_frame = (10000 * bits) / (baud / 100);
2640 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2641 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2642 if (s->rx_timeout < 20)
2646 if ((termios->c_cflag & CREAD) != 0)
2649 spin_unlock_irqrestore(&port->lock, flags);
2651 sci_port_disable(s);
2653 if (UART_ENABLE_MS(port, termios->c_cflag))
2654 sci_enable_ms(port);
2657 static void sci_pm(struct uart_port *port, unsigned int state,
2658 unsigned int oldstate)
2660 struct sci_port *sci_port = to_sci_port(port);
2663 case UART_PM_STATE_OFF:
2664 sci_port_disable(sci_port);
2667 sci_port_enable(sci_port);
2672 static const char *sci_type(struct uart_port *port)
2674 switch (port->type) {
2692 static int sci_remap_port(struct uart_port *port)
2694 struct sci_port *sport = to_sci_port(port);
2697 * Nothing to do if there's already an established membase.
2702 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2703 port->membase = ioremap(port->mapbase, sport->reg_size);
2704 if (unlikely(!port->membase)) {
2705 dev_err(port->dev, "can't remap port#%d\n", port->line);
2710 * For the simple (and majority of) cases where we don't
2711 * need to do any remapping, just cast the cookie
2714 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2720 static void sci_release_port(struct uart_port *port)
2722 struct sci_port *sport = to_sci_port(port);
2724 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2725 iounmap(port->membase);
2726 port->membase = NULL;
2729 release_mem_region(port->mapbase, sport->reg_size);
2732 static int sci_request_port(struct uart_port *port)
2734 struct resource *res;
2735 struct sci_port *sport = to_sci_port(port);
2738 res = request_mem_region(port->mapbase, sport->reg_size,
2739 dev_name(port->dev));
2740 if (unlikely(res == NULL)) {
2741 dev_err(port->dev, "request_mem_region failed.");
2745 ret = sci_remap_port(port);
2746 if (unlikely(ret != 0)) {
2747 release_resource(res);
2754 static void sci_config_port(struct uart_port *port, int flags)
2756 if (flags & UART_CONFIG_TYPE) {
2757 struct sci_port *sport = to_sci_port(port);
2759 port->type = sport->cfg->type;
2760 sci_request_port(port);
2764 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2766 if (ser->baud_base < 2400)
2767 /* No paper tape reader for Mitch.. */
2773 static const struct uart_ops sci_uart_ops = {
2774 .tx_empty = sci_tx_empty,
2775 .set_mctrl = sci_set_mctrl,
2776 .get_mctrl = sci_get_mctrl,
2777 .start_tx = sci_start_tx,
2778 .stop_tx = sci_stop_tx,
2779 .stop_rx = sci_stop_rx,
2780 .enable_ms = sci_enable_ms,
2781 .break_ctl = sci_break_ctl,
2782 .startup = sci_startup,
2783 .shutdown = sci_shutdown,
2784 .flush_buffer = sci_flush_buffer,
2785 .set_termios = sci_set_termios,
2788 .release_port = sci_release_port,
2789 .request_port = sci_request_port,
2790 .config_port = sci_config_port,
2791 .verify_port = sci_verify_port,
2792 #ifdef CONFIG_CONSOLE_POLL
2793 .poll_get_char = sci_poll_get_char,
2794 .poll_put_char = sci_poll_put_char,
2798 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2800 const char *clk_names[] = {
2803 [SCI_BRG_INT] = "brg_int",
2804 [SCI_SCIF_CLK] = "scif_clk",
2809 if (sci_port->cfg->type == PORT_HSCIF)
2810 clk_names[SCI_SCK] = "hsck";
2812 for (i = 0; i < SCI_NUM_CLKS; i++) {
2813 clk = devm_clk_get(dev, clk_names[i]);
2814 if (PTR_ERR(clk) == -EPROBE_DEFER)
2815 return -EPROBE_DEFER;
2817 if (IS_ERR(clk) && i == SCI_FCK) {
2819 * "fck" used to be called "sci_ick", and we need to
2820 * maintain DT backward compatibility.
2822 clk = devm_clk_get(dev, "sci_ick");
2823 if (PTR_ERR(clk) == -EPROBE_DEFER)
2824 return -EPROBE_DEFER;
2830 * Not all SH platforms declare a clock lookup entry
2831 * for SCI devices, in which case we need to get the
2832 * global "peripheral_clk" clock.
2834 clk = devm_clk_get(dev, "peripheral_clk");
2838 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2840 return PTR_ERR(clk);
2845 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2848 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2849 clk, clk_get_rate(clk));
2850 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2855 static const struct sci_port_params *
2856 sci_probe_regmap(const struct plat_sci_port *cfg)
2858 unsigned int regtype;
2860 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2861 return &sci_port_params[cfg->regtype];
2863 switch (cfg->type) {
2865 regtype = SCIx_SCI_REGTYPE;
2868 regtype = SCIx_IRDA_REGTYPE;
2871 regtype = SCIx_SCIFA_REGTYPE;
2874 regtype = SCIx_SCIFB_REGTYPE;
2878 * The SH-4 is a bit of a misnomer here, although that's
2879 * where this particular port layout originated. This
2880 * configuration (or some slight variation thereof)
2881 * remains the dominant model for all SCIFs.
2883 regtype = SCIx_SH4_SCIF_REGTYPE;
2886 regtype = SCIx_HSCIF_REGTYPE;
2889 pr_err("Can't probe register map for given port\n");
2893 return &sci_port_params[regtype];
2896 static int sci_init_single(struct platform_device *dev,
2897 struct sci_port *sci_port, unsigned int index,
2898 const struct plat_sci_port *p, bool early)
2900 struct uart_port *port = &sci_port->port;
2901 const struct resource *res;
2907 port->ops = &sci_uart_ops;
2908 port->iotype = UPIO_MEM;
2910 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2912 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2916 port->mapbase = res->start;
2917 sci_port->reg_size = resource_size(res);
2919 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2921 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2923 sci_port->irqs[i] = platform_get_irq(dev, i);
2926 /* The SCI generates several interrupts. They can be muxed together or
2927 * connected to different interrupt lines. In the muxed case only one
2928 * interrupt resource is specified as there is only one interrupt ID.
2929 * In the non-muxed case, up to 6 interrupt signals might be generated
2930 * from the SCI, however those signals might have their own individual
2931 * interrupt ID numbers, or muxed together with another interrupt.
2933 if (sci_port->irqs[0] < 0)
2936 if (sci_port->irqs[1] < 0)
2937 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2938 sci_port->irqs[i] = sci_port->irqs[0];
2940 sci_port->params = sci_probe_regmap(p);
2941 if (unlikely(sci_port->params == NULL))
2946 sci_port->rx_trigger = 48;
2949 sci_port->rx_trigger = 64;
2952 sci_port->rx_trigger = 32;
2955 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2956 /* RX triggering not implemented for this IP */
2957 sci_port->rx_trigger = 1;
2959 sci_port->rx_trigger = 8;
2962 sci_port->rx_trigger = 1;
2966 sci_port->rx_fifo_timeout = 0;
2967 sci_port->hscif_tot = 0;
2969 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2970 * match the SoC datasheet, this should be investigated. Let platform
2971 * data override the sampling rate for now.
2973 sci_port->sampling_rate_mask = p->sampling_rate
2974 ? SCI_SR(p->sampling_rate)
2975 : sci_port->params->sampling_rate_mask;
2978 ret = sci_init_clocks(sci_port, &dev->dev);
2982 port->dev = &dev->dev;
2984 pm_runtime_enable(&dev->dev);
2987 port->type = p->type;
2988 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2989 port->fifosize = sci_port->params->fifosize;
2991 if (port->type == PORT_SCI) {
2992 if (sci_port->reg_size >= 0x20)
2999 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3000 * for the multi-IRQ ports, which is where we are primarily
3001 * concerned with the shutdown path synchronization.
3003 * For the muxed case there's nothing more to do.
3005 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3008 port->serial_in = sci_serial_in;
3009 port->serial_out = sci_serial_out;
3014 static void sci_cleanup_single(struct sci_port *port)
3016 pm_runtime_disable(port->port.dev);
3019 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3020 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3021 static void serial_console_putchar(struct uart_port *port, int ch)
3023 sci_poll_put_char(port, ch);
3027 * Print a string to the serial port trying not to disturb
3028 * any possible real use of the port...
3030 static void serial_console_write(struct console *co, const char *s,
3033 struct sci_port *sci_port = &sci_ports[co->index];
3034 struct uart_port *port = &sci_port->port;
3035 unsigned short bits, ctrl, ctrl_temp;
3036 unsigned long flags;
3041 else if (oops_in_progress)
3042 locked = spin_trylock_irqsave(&port->lock, flags);
3044 spin_lock_irqsave(&port->lock, flags);
3046 /* first save SCSCR then disable interrupts, keep clock source */
3047 ctrl = serial_port_in(port, SCSCR);
3048 ctrl_temp = SCSCR_RE | SCSCR_TE |
3049 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3050 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3051 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3053 uart_console_write(port, s, count, serial_console_putchar);
3055 /* wait until fifo is empty and last bit has been transmitted */
3056 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3057 while ((serial_port_in(port, SCxSR) & bits) != bits)
3060 /* restore the SCSCR */
3061 serial_port_out(port, SCSCR, ctrl);
3064 spin_unlock_irqrestore(&port->lock, flags);
3067 static int serial_console_setup(struct console *co, char *options)
3069 struct sci_port *sci_port;
3070 struct uart_port *port;
3078 * Refuse to handle any bogus ports.
3080 if (co->index < 0 || co->index >= SCI_NPORTS)
3083 sci_port = &sci_ports[co->index];
3084 port = &sci_port->port;
3087 * Refuse to handle uninitialized ports.
3092 ret = sci_remap_port(port);
3093 if (unlikely(ret != 0))
3097 uart_parse_options(options, &baud, &parity, &bits, &flow);
3099 return uart_set_options(port, co, baud, parity, bits, flow);
3102 static struct console serial_console = {
3104 .device = uart_console_device,
3105 .write = serial_console_write,
3106 .setup = serial_console_setup,
3107 .flags = CON_PRINTBUFFER,
3109 .data = &sci_uart_driver,
3112 #ifdef CONFIG_SUPERH
3113 static struct console early_serial_console = {
3114 .name = "early_ttySC",
3115 .write = serial_console_write,
3116 .flags = CON_PRINTBUFFER,
3120 static char early_serial_buf[32];
3122 static int sci_probe_earlyprintk(struct platform_device *pdev)
3124 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3126 if (early_serial_console.data)
3129 early_serial_console.index = pdev->id;
3131 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3133 serial_console_setup(&early_serial_console, early_serial_buf);
3135 if (!strstr(early_serial_buf, "keep"))
3136 early_serial_console.flags |= CON_BOOT;
3138 register_console(&early_serial_console);
3143 #define SCI_CONSOLE (&serial_console)
3146 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3151 #define SCI_CONSOLE NULL
3153 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3155 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3157 static DEFINE_MUTEX(sci_uart_registration_lock);
3158 static struct uart_driver sci_uart_driver = {
3159 .owner = THIS_MODULE,
3160 .driver_name = "sci",
3161 .dev_name = "ttySC",
3163 .minor = SCI_MINOR_START,
3165 .cons = SCI_CONSOLE,
3168 static int sci_remove(struct platform_device *dev)
3170 struct sci_port *port = platform_get_drvdata(dev);
3171 unsigned int type = port->port.type; /* uart_remove_... clears it */
3173 sci_ports_in_use &= ~BIT(port->port.line);
3174 uart_remove_one_port(&sci_uart_driver, &port->port);
3176 sci_cleanup_single(port);
3178 if (port->port.fifosize > 1)
3179 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3180 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3181 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3187 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3188 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3189 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3191 static const struct of_device_id of_sci_match[] = {
3192 /* SoC-specific types */
3194 .compatible = "renesas,scif-r7s72100",
3195 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3198 .compatible = "renesas,scif-r7s9210",
3199 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3201 /* Family-specific types */
3203 .compatible = "renesas,rcar-gen1-scif",
3204 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3206 .compatible = "renesas,rcar-gen2-scif",
3207 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3209 .compatible = "renesas,rcar-gen3-scif",
3210 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3214 .compatible = "renesas,scif",
3215 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3217 .compatible = "renesas,scifa",
3218 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3220 .compatible = "renesas,scifb",
3221 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3223 .compatible = "renesas,hscif",
3224 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3226 .compatible = "renesas,sci",
3227 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3232 MODULE_DEVICE_TABLE(of, of_sci_match);
3234 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3235 unsigned int *dev_id)
3237 struct device_node *np = pdev->dev.of_node;
3238 struct plat_sci_port *p;
3239 struct sci_port *sp;
3243 if (!IS_ENABLED(CONFIG_OF) || !np)
3246 data = of_device_get_match_data(&pdev->dev);
3248 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3252 /* Get the line number from the aliases node. */
3253 id = of_alias_get_id(np, "serial");
3254 if (id < 0 && ~sci_ports_in_use)
3255 id = ffz(sci_ports_in_use);
3257 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3260 if (id >= ARRAY_SIZE(sci_ports)) {
3261 dev_err(&pdev->dev, "serial%d out of range\n", id);
3265 sp = &sci_ports[id];
3268 p->type = SCI_OF_TYPE(data);
3269 p->regtype = SCI_OF_REGTYPE(data);
3271 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3276 static int sci_probe_single(struct platform_device *dev,
3278 struct plat_sci_port *p,
3279 struct sci_port *sciport)
3284 if (unlikely(index >= SCI_NPORTS)) {
3285 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3286 index+1, SCI_NPORTS);
3287 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3290 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3291 if (sci_ports_in_use & BIT(index))
3294 mutex_lock(&sci_uart_registration_lock);
3295 if (!sci_uart_driver.state) {
3296 ret = uart_register_driver(&sci_uart_driver);
3298 mutex_unlock(&sci_uart_registration_lock);
3302 mutex_unlock(&sci_uart_registration_lock);
3304 ret = sci_init_single(dev, sciport, index, p, false);
3308 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3309 if (IS_ERR(sciport->gpios))
3310 return PTR_ERR(sciport->gpios);
3312 if (sciport->has_rtscts) {
3313 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3314 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3315 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3318 sciport->port.flags |= UPF_HARD_FLOW;
3321 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3323 sci_cleanup_single(sciport);
3330 static int sci_probe(struct platform_device *dev)
3332 struct plat_sci_port *p;
3333 struct sci_port *sp;
3334 unsigned int dev_id;
3338 * If we've come here via earlyprintk initialization, head off to
3339 * the special early probe. We don't have sufficient device state
3340 * to make it beyond this yet.
3342 #ifdef CONFIG_SUPERH
3343 if (is_sh_early_platform_device(dev))
3344 return sci_probe_earlyprintk(dev);
3347 if (dev->dev.of_node) {
3348 p = sci_parse_dt(dev, &dev_id);
3352 p = dev->dev.platform_data;
3354 dev_err(&dev->dev, "no platform data supplied\n");
3361 sp = &sci_ports[dev_id];
3362 platform_set_drvdata(dev, sp);
3364 ret = sci_probe_single(dev, dev_id, p, sp);
3368 if (sp->port.fifosize > 1) {
3369 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3373 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3374 sp->port.type == PORT_HSCIF) {
3375 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3377 if (sp->port.fifosize > 1) {
3378 device_remove_file(&dev->dev,
3379 &dev_attr_rx_fifo_trigger);
3385 #ifdef CONFIG_SH_STANDARD_BIOS
3386 sh_bios_gdb_detach();
3389 sci_ports_in_use |= BIT(dev_id);
3393 static __maybe_unused int sci_suspend(struct device *dev)
3395 struct sci_port *sport = dev_get_drvdata(dev);
3398 uart_suspend_port(&sci_uart_driver, &sport->port);
3403 static __maybe_unused int sci_resume(struct device *dev)
3405 struct sci_port *sport = dev_get_drvdata(dev);
3408 uart_resume_port(&sci_uart_driver, &sport->port);
3413 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3415 static struct platform_driver sci_driver = {
3417 .remove = sci_remove,
3420 .pm = &sci_dev_pm_ops,
3421 .of_match_table = of_match_ptr(of_sci_match),
3425 static int __init sci_init(void)
3427 pr_info("%s\n", banner);
3429 return platform_driver_register(&sci_driver);
3432 static void __exit sci_exit(void)
3434 platform_driver_unregister(&sci_driver);
3436 if (sci_uart_driver.state)
3437 uart_unregister_driver(&sci_uart_driver);
3440 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3441 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3442 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3444 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3445 static struct plat_sci_port port_cfg __initdata;
3447 static int __init early_console_setup(struct earlycon_device *device,
3450 if (!device->port.membase)
3453 device->port.serial_in = sci_serial_in;
3454 device->port.serial_out = sci_serial_out;
3455 device->port.type = type;
3456 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3457 port_cfg.type = type;
3458 sci_ports[0].cfg = &port_cfg;
3459 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3460 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3461 sci_serial_out(&sci_ports[0].port, SCSCR,
3462 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3464 device->con->write = serial_console_write;
3467 static int __init sci_early_console_setup(struct earlycon_device *device,
3470 return early_console_setup(device, PORT_SCI);
3472 static int __init scif_early_console_setup(struct earlycon_device *device,
3475 return early_console_setup(device, PORT_SCIF);
3477 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3480 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3481 return early_console_setup(device, PORT_SCIF);
3483 static int __init scifa_early_console_setup(struct earlycon_device *device,
3486 return early_console_setup(device, PORT_SCIFA);
3488 static int __init scifb_early_console_setup(struct earlycon_device *device,
3491 return early_console_setup(device, PORT_SCIFB);
3493 static int __init hscif_early_console_setup(struct earlycon_device *device,
3496 return early_console_setup(device, PORT_HSCIF);
3499 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3500 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3501 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3502 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3503 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3504 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3505 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3507 module_init(sci_init);
3508 module_exit(sci_exit);
3510 MODULE_LICENSE("GPL");
3511 MODULE_ALIAS("platform:sh-sci");
3512 MODULE_AUTHOR("Paul Mundt");
3513 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");