2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Copyright (C) 2015 Glider bvba
6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 * based off of the old drivers/char/sh-sci.c by:
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 * Removed SH7300 support (Jul 2007).
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
21 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/clk.h>
28 #include <linux/console.h>
29 #include <linux/ctype.h>
30 #include <linux/cpufreq.h>
31 #include <linux/delay.h>
32 #include <linux/dmaengine.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/ioport.h>
39 #include <linux/major.h>
40 #include <linux/module.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
60 #include "serial_mctrl_gpio.h"
63 /* Offsets into the sci_port->irqs array */
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
74 #define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
81 SCI_FCK, /* Functional Clock */
82 SCI_SCK, /* Optional External Clock */
83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
88 /* Bit x set means sampling rate x + 1 is supported */
89 #define SCI_SR(x) BIT((x) - 1)
90 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
96 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
97 #define max_sr(_port) fls((_port)->sampling_rate_mask)
99 /* Iterate over all supported sampling rates, from high to low */
100 #define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104 struct plat_sci_reg {
108 struct sci_port_params {
109 const struct plat_sci_reg regs[SCIx_NR_REGS];
110 unsigned int fifosize;
111 unsigned int overrun_reg;
112 unsigned int overrun_mask;
113 unsigned int sampling_rate_mask;
114 unsigned int error_mask;
115 unsigned int error_clear;
119 struct uart_port port;
121 /* Platform configuration */
122 const struct sci_port_params *params;
123 const struct plat_sci_port *cfg;
124 unsigned int sampling_rate_mask;
125 resource_size_t reg_size;
126 struct mctrl_gpios *gpios;
129 struct clk *clks[SCI_NUM_CLKS];
130 unsigned long clk_rates[SCI_NUM_CLKS];
132 int irqs[SCIx_NR_IRQS];
133 char *irqstr[SCIx_NR_IRQS];
135 struct dma_chan *chan_tx;
136 struct dma_chan *chan_rx;
138 #ifdef CONFIG_SERIAL_SH_SCI_DMA
139 dma_cookie_t cookie_tx;
140 dma_cookie_t cookie_rx[2];
141 dma_cookie_t active_rx;
142 dma_addr_t tx_dma_addr;
143 unsigned int tx_dma_len;
144 struct scatterlist sg_rx[2];
147 struct work_struct work_tx;
148 struct timer_list rx_timer;
149 unsigned int rx_timeout;
151 unsigned int rx_frame;
153 struct timer_list rx_fifo_timer;
160 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
162 static struct sci_port sci_ports[SCI_NPORTS];
163 static struct uart_driver sci_uart_driver;
165 static inline struct sci_port *
166 to_sci_port(struct uart_port *uart)
168 return container_of(uart, struct sci_port, port);
171 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
173 * Common SCI definitions, dependent on the port's regshift
176 [SCIx_SCI_REGTYPE] = {
178 [SCSMR] = { 0x00, 8 },
179 [SCBRR] = { 0x01, 8 },
180 [SCSCR] = { 0x02, 8 },
181 [SCxTDR] = { 0x03, 8 },
182 [SCxSR] = { 0x04, 8 },
183 [SCxRDR] = { 0x05, 8 },
186 .overrun_reg = SCxSR,
187 .overrun_mask = SCI_ORER,
188 .sampling_rate_mask = SCI_SR(32),
189 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
190 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
194 * Common definitions for legacy IrDA ports.
196 [SCIx_IRDA_REGTYPE] = {
198 [SCSMR] = { 0x00, 8 },
199 [SCBRR] = { 0x02, 8 },
200 [SCSCR] = { 0x04, 8 },
201 [SCxTDR] = { 0x06, 8 },
202 [SCxSR] = { 0x08, 16 },
203 [SCxRDR] = { 0x0a, 8 },
204 [SCFCR] = { 0x0c, 8 },
205 [SCFDR] = { 0x0e, 16 },
208 .overrun_reg = SCxSR,
209 .overrun_mask = SCI_ORER,
210 .sampling_rate_mask = SCI_SR(32),
211 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
212 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
216 * Common SCIFA definitions.
218 [SCIx_SCIFA_REGTYPE] = {
220 [SCSMR] = { 0x00, 16 },
221 [SCBRR] = { 0x04, 8 },
222 [SCSCR] = { 0x08, 16 },
223 [SCxTDR] = { 0x20, 8 },
224 [SCxSR] = { 0x14, 16 },
225 [SCxRDR] = { 0x24, 8 },
226 [SCFCR] = { 0x18, 16 },
227 [SCFDR] = { 0x1c, 16 },
228 [SCPCR] = { 0x30, 16 },
229 [SCPDR] = { 0x34, 16 },
232 .overrun_reg = SCxSR,
233 .overrun_mask = SCIFA_ORER,
234 .sampling_rate_mask = SCI_SR_SCIFAB,
235 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
236 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
240 * Common SCIFB definitions.
242 [SCIx_SCIFB_REGTYPE] = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x40, 8 },
248 [SCxSR] = { 0x14, 16 },
249 [SCxRDR] = { 0x60, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCTFDR] = { 0x38, 16 },
252 [SCRFDR] = { 0x3c, 16 },
253 [SCPCR] = { 0x30, 16 },
254 [SCPDR] = { 0x34, 16 },
257 .overrun_reg = SCxSR,
258 .overrun_mask = SCIFA_ORER,
259 .sampling_rate_mask = SCI_SR_SCIFAB,
260 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
261 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
265 * Common SH-2(A) SCIF definitions for ports with FIFO data
268 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
270 [SCSMR] = { 0x00, 16 },
271 [SCBRR] = { 0x04, 8 },
272 [SCSCR] = { 0x08, 16 },
273 [SCxTDR] = { 0x0c, 8 },
274 [SCxSR] = { 0x10, 16 },
275 [SCxRDR] = { 0x14, 8 },
276 [SCFCR] = { 0x18, 16 },
277 [SCFDR] = { 0x1c, 16 },
278 [SCSPTR] = { 0x20, 16 },
279 [SCLSR] = { 0x24, 16 },
282 .overrun_reg = SCLSR,
283 .overrun_mask = SCLSR_ORER,
284 .sampling_rate_mask = SCI_SR(32),
285 .error_mask = SCIF_DEFAULT_ERROR_MASK,
286 .error_clear = SCIF_ERROR_CLEAR,
290 * Common SH-3 SCIF definitions.
292 [SCIx_SH3_SCIF_REGTYPE] = {
294 [SCSMR] = { 0x00, 8 },
295 [SCBRR] = { 0x02, 8 },
296 [SCSCR] = { 0x04, 8 },
297 [SCxTDR] = { 0x06, 8 },
298 [SCxSR] = { 0x08, 16 },
299 [SCxRDR] = { 0x0a, 8 },
300 [SCFCR] = { 0x0c, 8 },
301 [SCFDR] = { 0x0e, 16 },
304 .overrun_reg = SCLSR,
305 .overrun_mask = SCLSR_ORER,
306 .sampling_rate_mask = SCI_SR(32),
307 .error_mask = SCIF_DEFAULT_ERROR_MASK,
308 .error_clear = SCIF_ERROR_CLEAR,
312 * Common SH-4(A) SCIF(B) definitions.
314 [SCIx_SH4_SCIF_REGTYPE] = {
316 [SCSMR] = { 0x00, 16 },
317 [SCBRR] = { 0x04, 8 },
318 [SCSCR] = { 0x08, 16 },
319 [SCxTDR] = { 0x0c, 8 },
320 [SCxSR] = { 0x10, 16 },
321 [SCxRDR] = { 0x14, 8 },
322 [SCFCR] = { 0x18, 16 },
323 [SCFDR] = { 0x1c, 16 },
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
328 .overrun_reg = SCLSR,
329 .overrun_mask = SCLSR_ORER,
330 .sampling_rate_mask = SCI_SR(32),
331 .error_mask = SCIF_DEFAULT_ERROR_MASK,
332 .error_clear = SCIF_ERROR_CLEAR,
336 * Common SCIF definitions for ports with a Baud Rate Generator for
337 * External Clock (BRG).
339 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
341 [SCSMR] = { 0x00, 16 },
342 [SCBRR] = { 0x04, 8 },
343 [SCSCR] = { 0x08, 16 },
344 [SCxTDR] = { 0x0c, 8 },
345 [SCxSR] = { 0x10, 16 },
346 [SCxRDR] = { 0x14, 8 },
347 [SCFCR] = { 0x18, 16 },
348 [SCFDR] = { 0x1c, 16 },
349 [SCSPTR] = { 0x20, 16 },
350 [SCLSR] = { 0x24, 16 },
351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
355 .overrun_reg = SCLSR,
356 .overrun_mask = SCLSR_ORER,
357 .sampling_rate_mask = SCI_SR(32),
358 .error_mask = SCIF_DEFAULT_ERROR_MASK,
359 .error_clear = SCIF_ERROR_CLEAR,
363 * Common HSCIF definitions.
365 [SCIx_HSCIF_REGTYPE] = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCSPTR] = { 0x20, 16 },
376 [SCLSR] = { 0x24, 16 },
377 [HSSRR] = { 0x40, 16 },
378 [SCDL] = { 0x30, 16 },
379 [SCCKS] = { 0x34, 16 },
380 [HSRTRGR] = { 0x54, 16 },
381 [HSTTRGR] = { 0x58, 16 },
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
392 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
395 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
397 [SCSMR] = { 0x00, 16 },
398 [SCBRR] = { 0x04, 8 },
399 [SCSCR] = { 0x08, 16 },
400 [SCxTDR] = { 0x0c, 8 },
401 [SCxSR] = { 0x10, 16 },
402 [SCxRDR] = { 0x14, 8 },
403 [SCFCR] = { 0x18, 16 },
404 [SCFDR] = { 0x1c, 16 },
405 [SCLSR] = { 0x24, 16 },
408 .overrun_reg = SCLSR,
409 .overrun_mask = SCLSR_ORER,
410 .sampling_rate_mask = SCI_SR(32),
411 .error_mask = SCIF_DEFAULT_ERROR_MASK,
412 .error_clear = SCIF_ERROR_CLEAR,
416 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
419 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
421 [SCSMR] = { 0x00, 16 },
422 [SCBRR] = { 0x04, 8 },
423 [SCSCR] = { 0x08, 16 },
424 [SCxTDR] = { 0x0c, 8 },
425 [SCxSR] = { 0x10, 16 },
426 [SCxRDR] = { 0x14, 8 },
427 [SCFCR] = { 0x18, 16 },
428 [SCFDR] = { 0x1c, 16 },
429 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
430 [SCRFDR] = { 0x20, 16 },
431 [SCSPTR] = { 0x24, 16 },
432 [SCLSR] = { 0x28, 16 },
435 .overrun_reg = SCLSR,
436 .overrun_mask = SCLSR_ORER,
437 .sampling_rate_mask = SCI_SR(32),
438 .error_mask = SCIF_DEFAULT_ERROR_MASK,
439 .error_clear = SCIF_ERROR_CLEAR,
443 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
446 [SCIx_SH7705_SCIF_REGTYPE] = {
448 [SCSMR] = { 0x00, 16 },
449 [SCBRR] = { 0x04, 8 },
450 [SCSCR] = { 0x08, 16 },
451 [SCxTDR] = { 0x20, 8 },
452 [SCxSR] = { 0x14, 16 },
453 [SCxRDR] = { 0x24, 8 },
454 [SCFCR] = { 0x18, 16 },
455 [SCFDR] = { 0x1c, 16 },
458 .overrun_reg = SCxSR,
459 .overrun_mask = SCIFA_ORER,
460 .sampling_rate_mask = SCI_SR(16),
461 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
462 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
466 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
469 * The "offset" here is rather misleading, in that it refers to an enum
470 * value relative to the port mapping rather than the fixed offset
471 * itself, which needs to be manually retrieved from the platform's
472 * register map for the given port.
474 static unsigned int sci_serial_in(struct uart_port *p, int offset)
476 const struct plat_sci_reg *reg = sci_getreg(p, offset);
479 return ioread8(p->membase + (reg->offset << p->regshift));
480 else if (reg->size == 16)
481 return ioread16(p->membase + (reg->offset << p->regshift));
483 WARN(1, "Invalid register access\n");
488 static void sci_serial_out(struct uart_port *p, int offset, int value)
490 const struct plat_sci_reg *reg = sci_getreg(p, offset);
493 iowrite8(value, p->membase + (reg->offset << p->regshift));
494 else if (reg->size == 16)
495 iowrite16(value, p->membase + (reg->offset << p->regshift));
497 WARN(1, "Invalid register access\n");
500 static void sci_port_enable(struct sci_port *sci_port)
504 if (!sci_port->port.dev)
507 pm_runtime_get_sync(sci_port->port.dev);
509 for (i = 0; i < SCI_NUM_CLKS; i++) {
510 clk_prepare_enable(sci_port->clks[i]);
511 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
513 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
516 static void sci_port_disable(struct sci_port *sci_port)
520 if (!sci_port->port.dev)
523 for (i = SCI_NUM_CLKS; i-- > 0; )
524 clk_disable_unprepare(sci_port->clks[i]);
526 pm_runtime_put_sync(sci_port->port.dev);
529 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
532 * Not all ports (such as SCIFA) will support REIE. Rather than
533 * special-casing the port type, we check the port initialization
534 * IRQ enable mask to see whether the IRQ is desired at all. If
535 * it's unset, it's logically inferred that there's no point in
538 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
541 static void sci_start_tx(struct uart_port *port)
543 struct sci_port *s = to_sci_port(port);
546 #ifdef CONFIG_SERIAL_SH_SCI_DMA
547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
548 u16 new, scr = serial_port_in(port, SCSCR);
550 new = scr | SCSCR_TDRQE;
552 new = scr & ~SCSCR_TDRQE;
554 serial_port_out(port, SCSCR, new);
557 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
558 dma_submit_error(s->cookie_tx)) {
560 schedule_work(&s->work_tx);
564 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
565 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
566 ctrl = serial_port_in(port, SCSCR);
567 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
571 static void sci_stop_tx(struct uart_port *port)
575 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
576 ctrl = serial_port_in(port, SCSCR);
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
579 ctrl &= ~SCSCR_TDRQE;
583 serial_port_out(port, SCSCR, ctrl);
585 #ifdef CONFIG_SERIAL_SH_SCI_DMA
586 if (to_sci_port(port)->chan_tx &&
587 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
588 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
589 to_sci_port(port)->cookie_tx = -EINVAL;
594 static void sci_start_rx(struct uart_port *port)
598 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
600 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
601 ctrl &= ~SCSCR_RDRQE;
603 serial_port_out(port, SCSCR, ctrl);
606 static void sci_stop_rx(struct uart_port *port)
610 ctrl = serial_port_in(port, SCSCR);
612 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
613 ctrl &= ~SCSCR_RDRQE;
615 ctrl &= ~port_rx_irq_mask(port);
617 serial_port_out(port, SCSCR, ctrl);
620 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
622 if (port->type == PORT_SCI) {
623 /* Just store the mask */
624 serial_port_out(port, SCxSR, mask);
625 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
626 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
627 /* Only clear the status bits we want to clear */
628 serial_port_out(port, SCxSR,
629 serial_port_in(port, SCxSR) & mask);
631 /* Store the mask, clear parity/framing errors */
632 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
636 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
637 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
639 #ifdef CONFIG_CONSOLE_POLL
640 static int sci_poll_get_char(struct uart_port *port)
642 unsigned short status;
646 status = serial_port_in(port, SCxSR);
647 if (status & SCxSR_ERRORS(port)) {
648 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
654 if (!(status & SCxSR_RDxF(port)))
657 c = serial_port_in(port, SCxRDR);
660 serial_port_in(port, SCxSR);
661 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
667 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
669 unsigned short status;
672 status = serial_port_in(port, SCxSR);
673 } while (!(status & SCxSR_TDxE(port)));
675 serial_port_out(port, SCxTDR, c);
676 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
678 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
679 CONFIG_SERIAL_SH_SCI_EARLYCON */
681 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
683 struct sci_port *s = to_sci_port(port);
686 * Use port-specific handler if provided.
688 if (s->cfg->ops && s->cfg->ops->init_pins) {
689 s->cfg->ops->init_pins(port, cflag);
693 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
694 u16 data = serial_port_in(port, SCPDR);
695 u16 ctrl = serial_port_in(port, SCPCR);
697 /* Enable RXD and TXD pin functions */
698 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
699 if (to_sci_port(port)->has_rtscts) {
700 /* RTS# is output, active low, unless autorts */
701 if (!(port->mctrl & TIOCM_RTS)) {
704 } else if (!s->autorts) {
708 /* Enable RTS# pin function */
711 /* Enable CTS# pin function */
714 serial_port_out(port, SCPDR, data);
715 serial_port_out(port, SCPCR, ctrl);
716 } else if (sci_getreg(port, SCSPTR)->size) {
717 u16 status = serial_port_in(port, SCSPTR);
719 /* RTS# is always output; and active low, unless autorts */
720 status |= SCSPTR_RTSIO;
721 if (!(port->mctrl & TIOCM_RTS))
722 status |= SCSPTR_RTSDT;
723 else if (!s->autorts)
724 status &= ~SCSPTR_RTSDT;
725 /* CTS# and SCK are inputs */
726 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
727 serial_port_out(port, SCSPTR, status);
731 static int sci_txfill(struct uart_port *port)
733 struct sci_port *s = to_sci_port(port);
734 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
735 const struct plat_sci_reg *reg;
737 reg = sci_getreg(port, SCTFDR);
739 return serial_port_in(port, SCTFDR) & fifo_mask;
741 reg = sci_getreg(port, SCFDR);
743 return serial_port_in(port, SCFDR) >> 8;
745 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
748 static int sci_txroom(struct uart_port *port)
750 return port->fifosize - sci_txfill(port);
753 static int sci_rxfill(struct uart_port *port)
755 struct sci_port *s = to_sci_port(port);
756 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
757 const struct plat_sci_reg *reg;
759 reg = sci_getreg(port, SCRFDR);
761 return serial_port_in(port, SCRFDR) & fifo_mask;
763 reg = sci_getreg(port, SCFDR);
765 return serial_port_in(port, SCFDR) & fifo_mask;
767 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
770 /* ********************************************************************** *
771 * the interrupt related routines *
772 * ********************************************************************** */
774 static void sci_transmit_chars(struct uart_port *port)
776 struct circ_buf *xmit = &port->state->xmit;
777 unsigned int stopped = uart_tx_stopped(port);
778 unsigned short status;
782 status = serial_port_in(port, SCxSR);
783 if (!(status & SCxSR_TDxE(port))) {
784 ctrl = serial_port_in(port, SCSCR);
785 if (uart_circ_empty(xmit))
789 serial_port_out(port, SCSCR, ctrl);
793 count = sci_txroom(port);
801 } else if (!uart_circ_empty(xmit) && !stopped) {
802 c = xmit->buf[xmit->tail];
803 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
808 serial_port_out(port, SCxTDR, c);
811 } while (--count > 0);
813 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
815 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
816 uart_write_wakeup(port);
817 if (uart_circ_empty(xmit))
822 /* On SH3, SCIF may read end-of-break as a space->mark char */
823 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
825 static void sci_receive_chars(struct uart_port *port)
827 struct tty_port *tport = &port->state->port;
828 int i, count, copied = 0;
829 unsigned short status;
832 status = serial_port_in(port, SCxSR);
833 if (!(status & SCxSR_RDxF(port)))
837 /* Don't copy more bytes than there is room for in the buffer */
838 count = tty_buffer_request_room(tport, sci_rxfill(port));
840 /* If for any reason we can't copy more data, we're done! */
844 if (port->type == PORT_SCI) {
845 char c = serial_port_in(port, SCxRDR);
846 if (uart_handle_sysrq_char(port, c))
849 tty_insert_flip_char(tport, c, TTY_NORMAL);
851 for (i = 0; i < count; i++) {
854 if (port->type == PORT_SCIF ||
855 port->type == PORT_HSCIF) {
856 status = serial_port_in(port, SCxSR);
857 c = serial_port_in(port, SCxRDR);
859 c = serial_port_in(port, SCxRDR);
860 status = serial_port_in(port, SCxSR);
862 if (uart_handle_sysrq_char(port, c)) {
867 /* Store data and status */
868 if (status & SCxSR_FER(port)) {
870 port->icount.frame++;
871 dev_notice(port->dev, "frame error\n");
872 } else if (status & SCxSR_PER(port)) {
874 port->icount.parity++;
875 dev_notice(port->dev, "parity error\n");
879 tty_insert_flip_char(tport, c, flag);
883 serial_port_in(port, SCxSR); /* dummy read */
884 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
887 port->icount.rx += count;
891 /* Tell the rest of the system the news. New characters! */
892 tty_flip_buffer_push(tport);
894 /* TTY buffers full; read from RX reg to prevent lockup */
895 serial_port_in(port, SCxRDR);
896 serial_port_in(port, SCxSR); /* dummy read */
897 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
901 static int sci_handle_errors(struct uart_port *port)
904 unsigned short status = serial_port_in(port, SCxSR);
905 struct tty_port *tport = &port->state->port;
906 struct sci_port *s = to_sci_port(port);
908 /* Handle overruns */
909 if (status & s->params->overrun_mask) {
910 port->icount.overrun++;
913 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
916 dev_notice(port->dev, "overrun error\n");
919 if (status & SCxSR_FER(port)) {
921 port->icount.frame++;
923 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
926 dev_notice(port->dev, "frame error\n");
929 if (status & SCxSR_PER(port)) {
931 port->icount.parity++;
933 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
936 dev_notice(port->dev, "parity error\n");
940 tty_flip_buffer_push(tport);
945 static int sci_handle_fifo_overrun(struct uart_port *port)
947 struct tty_port *tport = &port->state->port;
948 struct sci_port *s = to_sci_port(port);
949 const struct plat_sci_reg *reg;
953 reg = sci_getreg(port, s->params->overrun_reg);
957 status = serial_port_in(port, s->params->overrun_reg);
958 if (status & s->params->overrun_mask) {
959 status &= ~s->params->overrun_mask;
960 serial_port_out(port, s->params->overrun_reg, status);
962 port->icount.overrun++;
964 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
965 tty_flip_buffer_push(tport);
967 dev_dbg(port->dev, "overrun error\n");
974 static int sci_handle_breaks(struct uart_port *port)
977 unsigned short status = serial_port_in(port, SCxSR);
978 struct tty_port *tport = &port->state->port;
980 if (uart_handle_break(port))
983 if (status & SCxSR_BRK(port)) {
986 /* Notify of BREAK */
987 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
990 dev_dbg(port->dev, "BREAK detected\n");
994 tty_flip_buffer_push(tport);
996 copied += sci_handle_fifo_overrun(port);
1001 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1005 if (rx_trig >= port->fifosize)
1006 rx_trig = port->fifosize - 1;
1010 /* HSCIF can be set to an arbitrary level. */
1011 if (sci_getreg(port, HSRTRGR)->size) {
1012 serial_port_out(port, HSRTRGR, rx_trig);
1016 switch (port->type) {
1021 } else if (rx_trig < 8) {
1024 } else if (rx_trig < 14) {
1028 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1037 } else if (rx_trig < 32) {
1040 } else if (rx_trig < 48) {
1044 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1049 WARN(1, "unknown FIFO configuration");
1053 serial_port_out(port, SCFCR,
1054 (serial_port_in(port, SCFCR) &
1055 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1060 static int scif_rtrg_enabled(struct uart_port *port)
1062 if (sci_getreg(port, HSRTRGR)->size)
1063 return serial_port_in(port, HSRTRGR) != 0;
1065 return (serial_port_in(port, SCFCR) &
1066 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1069 static void rx_fifo_timer_fn(unsigned long arg)
1071 struct sci_port *s = (struct sci_port *)arg;
1072 struct uart_port *port = &s->port;
1074 dev_dbg(port->dev, "Rx timed out\n");
1075 scif_set_rtrg(port, 1);
1078 static ssize_t rx_trigger_show(struct device *dev,
1079 struct device_attribute *attr,
1082 struct uart_port *port = dev_get_drvdata(dev);
1083 struct sci_port *sci = to_sci_port(port);
1085 return sprintf(buf, "%d\n", sci->rx_trigger);
1088 static ssize_t rx_trigger_store(struct device *dev,
1089 struct device_attribute *attr,
1093 struct uart_port *port = dev_get_drvdata(dev);
1094 struct sci_port *sci = to_sci_port(port);
1098 ret = kstrtol(buf, 0, &r);
1102 sci->rx_trigger = scif_set_rtrg(port, r);
1103 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1104 scif_set_rtrg(port, 1);
1109 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1111 static ssize_t rx_fifo_timeout_show(struct device *dev,
1112 struct device_attribute *attr,
1115 struct uart_port *port = dev_get_drvdata(dev);
1116 struct sci_port *sci = to_sci_port(port);
1118 return sprintf(buf, "%d\n", sci->rx_fifo_timeout);
1121 static ssize_t rx_fifo_timeout_store(struct device *dev,
1122 struct device_attribute *attr,
1126 struct uart_port *port = dev_get_drvdata(dev);
1127 struct sci_port *sci = to_sci_port(port);
1131 ret = kstrtol(buf, 0, &r);
1134 sci->rx_fifo_timeout = r;
1135 scif_set_rtrg(port, 1);
1137 setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
1138 (unsigned long)sci);
1142 static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store);
1145 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1146 static void sci_dma_tx_complete(void *arg)
1148 struct sci_port *s = arg;
1149 struct uart_port *port = &s->port;
1150 struct circ_buf *xmit = &port->state->xmit;
1151 unsigned long flags;
1153 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1155 spin_lock_irqsave(&port->lock, flags);
1157 xmit->tail += s->tx_dma_len;
1158 xmit->tail &= UART_XMIT_SIZE - 1;
1160 port->icount.tx += s->tx_dma_len;
1162 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1163 uart_write_wakeup(port);
1165 if (!uart_circ_empty(xmit)) {
1167 schedule_work(&s->work_tx);
1169 s->cookie_tx = -EINVAL;
1170 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1171 u16 ctrl = serial_port_in(port, SCSCR);
1172 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1176 spin_unlock_irqrestore(&port->lock, flags);
1179 /* Locking: called with port lock held */
1180 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1182 struct uart_port *port = &s->port;
1183 struct tty_port *tport = &port->state->port;
1186 copied = tty_insert_flip_string(tport, buf, count);
1188 port->icount.buf_overrun++;
1190 port->icount.rx += copied;
1195 static int sci_dma_rx_find_active(struct sci_port *s)
1199 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1200 if (s->active_rx == s->cookie_rx[i])
1206 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1208 struct dma_chan *chan = s->chan_rx;
1209 struct uart_port *port = &s->port;
1210 unsigned long flags;
1212 spin_lock_irqsave(&port->lock, flags);
1214 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1215 spin_unlock_irqrestore(&port->lock, flags);
1216 dmaengine_terminate_all(chan);
1217 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1218 sg_dma_address(&s->sg_rx[0]));
1219 dma_release_channel(chan);
1224 static void sci_dma_rx_complete(void *arg)
1226 struct sci_port *s = arg;
1227 struct dma_chan *chan = s->chan_rx;
1228 struct uart_port *port = &s->port;
1229 struct dma_async_tx_descriptor *desc;
1230 unsigned long flags;
1231 int active, count = 0;
1233 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1236 spin_lock_irqsave(&port->lock, flags);
1238 active = sci_dma_rx_find_active(s);
1240 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1242 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1245 tty_flip_buffer_push(&port->state->port);
1247 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1249 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1253 desc->callback = sci_dma_rx_complete;
1254 desc->callback_param = s;
1255 s->cookie_rx[active] = dmaengine_submit(desc);
1256 if (dma_submit_error(s->cookie_rx[active]))
1259 s->active_rx = s->cookie_rx[!active];
1261 dma_async_issue_pending(chan);
1263 spin_unlock_irqrestore(&port->lock, flags);
1264 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1265 __func__, s->cookie_rx[active], active, s->active_rx);
1269 spin_unlock_irqrestore(&port->lock, flags);
1270 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1271 sci_rx_dma_release(s, true);
1274 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1276 struct dma_chan *chan = s->chan_tx;
1277 struct uart_port *port = &s->port;
1278 unsigned long flags;
1280 spin_lock_irqsave(&port->lock, flags);
1282 s->cookie_tx = -EINVAL;
1283 spin_unlock_irqrestore(&port->lock, flags);
1284 dmaengine_terminate_all(chan);
1285 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1287 dma_release_channel(chan);
1292 static void sci_submit_rx(struct sci_port *s)
1294 struct dma_chan *chan = s->chan_rx;
1297 for (i = 0; i < 2; i++) {
1298 struct scatterlist *sg = &s->sg_rx[i];
1299 struct dma_async_tx_descriptor *desc;
1301 desc = dmaengine_prep_slave_sg(chan,
1302 sg, 1, DMA_DEV_TO_MEM,
1303 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1307 desc->callback = sci_dma_rx_complete;
1308 desc->callback_param = s;
1309 s->cookie_rx[i] = dmaengine_submit(desc);
1310 if (dma_submit_error(s->cookie_rx[i]))
1315 s->active_rx = s->cookie_rx[0];
1317 dma_async_issue_pending(chan);
1322 dmaengine_terminate_all(chan);
1323 for (i = 0; i < 2; i++)
1324 s->cookie_rx[i] = -EINVAL;
1325 s->active_rx = -EINVAL;
1326 sci_rx_dma_release(s, true);
1329 static void work_fn_tx(struct work_struct *work)
1331 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1332 struct dma_async_tx_descriptor *desc;
1333 struct dma_chan *chan = s->chan_tx;
1334 struct uart_port *port = &s->port;
1335 struct circ_buf *xmit = &port->state->xmit;
1341 * Port xmit buffer is already mapped, and it is one page... Just adjust
1342 * offsets and lengths. Since it is a circular buffer, we have to
1343 * transmit till the end, and then the rest. Take the port lock to get a
1344 * consistent xmit buffer state.
1346 spin_lock_irq(&port->lock);
1349 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1350 s->tx_dma_len = min_t(unsigned int,
1351 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1352 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1353 if (!s->tx_dma_len) {
1354 /* Transmit buffer has been flushed */
1355 spin_unlock_irq(&port->lock);
1359 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1361 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1363 spin_unlock_irq(&port->lock);
1364 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1366 sci_tx_dma_release(s, true);
1370 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1373 desc->callback = sci_dma_tx_complete;
1374 desc->callback_param = s;
1375 s->cookie_tx = dmaengine_submit(desc);
1376 if (dma_submit_error(s->cookie_tx)) {
1377 spin_unlock_irq(&port->lock);
1378 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1380 sci_tx_dma_release(s, true);
1384 spin_unlock_irq(&port->lock);
1385 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1386 __func__, xmit->buf, tail, head, s->cookie_tx);
1388 dma_async_issue_pending(chan);
1391 static void rx_timer_fn(unsigned long arg)
1393 struct sci_port *s = (struct sci_port *)arg;
1394 struct dma_chan *chan = s->chan_rx;
1395 struct uart_port *port = &s->port;
1396 struct dma_tx_state state;
1397 enum dma_status status;
1398 unsigned long flags;
1403 dev_dbg(port->dev, "DMA Rx timed out\n");
1405 spin_lock_irqsave(&port->lock, flags);
1407 active = sci_dma_rx_find_active(s);
1409 spin_unlock_irqrestore(&port->lock, flags);
1413 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1414 if (status == DMA_COMPLETE) {
1415 spin_unlock_irqrestore(&port->lock, flags);
1416 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1417 s->active_rx, active);
1419 /* Let packet complete handler take care of the packet */
1423 dmaengine_pause(chan);
1426 * sometimes DMA transfer doesn't stop even if it is stopped and
1427 * data keeps on coming until transaction is complete so check
1428 * for DMA_COMPLETE again
1429 * Let packet complete handler take care of the packet
1431 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1432 if (status == DMA_COMPLETE) {
1433 spin_unlock_irqrestore(&port->lock, flags);
1434 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1438 /* Handle incomplete DMA receive */
1439 dmaengine_terminate_all(s->chan_rx);
1440 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1443 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1445 tty_flip_buffer_push(&port->state->port);
1448 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1451 /* Direct new serial port interrupts back to CPU */
1452 scr = serial_port_in(port, SCSCR);
1453 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1454 scr &= ~SCSCR_RDRQE;
1455 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1457 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1459 spin_unlock_irqrestore(&port->lock, flags);
1462 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1463 enum dma_transfer_direction dir)
1465 struct dma_chan *chan;
1466 struct dma_slave_config cfg;
1469 chan = dma_request_slave_channel(port->dev,
1470 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1472 dev_warn(port->dev, "dma_request_slave_channel failed\n");
1476 memset(&cfg, 0, sizeof(cfg));
1477 cfg.direction = dir;
1478 if (dir == DMA_MEM_TO_DEV) {
1479 cfg.dst_addr = port->mapbase +
1480 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1481 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1483 cfg.src_addr = port->mapbase +
1484 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1485 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1488 ret = dmaengine_slave_config(chan, &cfg);
1490 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1491 dma_release_channel(chan);
1498 static void sci_request_dma(struct uart_port *port)
1500 struct sci_port *s = to_sci_port(port);
1501 struct dma_chan *chan;
1503 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1506 * DMA on console may interfere with Kernel log messages which use
1507 * plain putchar(). So, simply don't use it with a console.
1509 if (uart_console(port))
1512 if (!port->dev->of_node)
1515 s->cookie_tx = -EINVAL;
1518 * Don't request a dma channel if no channel was specified
1519 * in the device tree.
1521 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1524 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1525 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1528 /* UART circular tx buffer is an aligned page. */
1529 s->tx_dma_addr = dma_map_single(chan->device->dev,
1530 port->state->xmit.buf,
1533 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1534 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1535 dma_release_channel(chan);
1538 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1539 __func__, UART_XMIT_SIZE,
1540 port->state->xmit.buf, &s->tx_dma_addr);
1543 INIT_WORK(&s->work_tx, work_fn_tx);
1546 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1547 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1555 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1556 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1560 "Failed to allocate Rx dma buffer, using PIO\n");
1561 dma_release_channel(chan);
1566 for (i = 0; i < 2; i++) {
1567 struct scatterlist *sg = &s->sg_rx[i];
1569 sg_init_table(sg, 1);
1571 sg_dma_address(sg) = dma;
1572 sg_dma_len(sg) = s->buf_len_rx;
1574 buf += s->buf_len_rx;
1575 dma += s->buf_len_rx;
1578 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1580 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1585 static void sci_free_dma(struct uart_port *port)
1587 struct sci_port *s = to_sci_port(port);
1590 sci_tx_dma_release(s, false);
1592 sci_rx_dma_release(s, false);
1595 static void sci_flush_buffer(struct uart_port *port)
1597 struct sci_port *s = to_sci_port(port);
1600 * In uart_flush_buffer(), the xmit circular buffer has just been
1601 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1606 dmaengine_terminate_async(s->chan_tx);
1607 s->cookie_tx = -EINVAL;
1610 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1611 static inline void sci_request_dma(struct uart_port *port)
1615 static inline void sci_free_dma(struct uart_port *port)
1619 #define sci_flush_buffer NULL
1620 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1622 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1624 struct uart_port *port = ptr;
1625 struct sci_port *s = to_sci_port(port);
1627 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1629 u16 scr = serial_port_in(port, SCSCR);
1630 u16 ssr = serial_port_in(port, SCxSR);
1632 /* Disable future Rx interrupts */
1633 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1634 disable_irq_nosync(irq);
1640 serial_port_out(port, SCSCR, scr);
1641 /* Clear current interrupt */
1642 serial_port_out(port, SCxSR,
1643 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1644 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1645 jiffies, s->rx_timeout);
1646 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1652 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1653 if (!scif_rtrg_enabled(port))
1654 scif_set_rtrg(port, s->rx_trigger);
1656 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1657 s->rx_frame * s->rx_fifo_timeout, 1000));
1660 /* I think sci_receive_chars has to be called irrespective
1661 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1664 sci_receive_chars(ptr);
1669 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1671 struct uart_port *port = ptr;
1672 unsigned long flags;
1674 spin_lock_irqsave(&port->lock, flags);
1675 sci_transmit_chars(port);
1676 spin_unlock_irqrestore(&port->lock, flags);
1681 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1683 struct uart_port *port = ptr;
1684 struct sci_port *s = to_sci_port(port);
1687 if (port->type == PORT_SCI) {
1688 if (sci_handle_errors(port)) {
1689 /* discard character in rx buffer */
1690 serial_port_in(port, SCxSR);
1691 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1694 sci_handle_fifo_overrun(port);
1696 sci_receive_chars(ptr);
1699 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1701 /* Kick the transmission */
1703 sci_tx_interrupt(irq, ptr);
1708 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1710 struct uart_port *port = ptr;
1713 sci_handle_breaks(port);
1714 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1719 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1721 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1722 struct uart_port *port = ptr;
1723 struct sci_port *s = to_sci_port(port);
1724 irqreturn_t ret = IRQ_NONE;
1726 ssr_status = serial_port_in(port, SCxSR);
1727 scr_status = serial_port_in(port, SCSCR);
1728 if (s->params->overrun_reg == SCxSR)
1729 orer_status = ssr_status;
1730 else if (sci_getreg(port, s->params->overrun_reg)->size)
1731 orer_status = serial_port_in(port, s->params->overrun_reg);
1733 err_enabled = scr_status & port_rx_irq_mask(port);
1736 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1738 ret = sci_tx_interrupt(irq, ptr);
1741 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1744 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1745 (scr_status & SCSCR_RIE))
1746 ret = sci_rx_interrupt(irq, ptr);
1748 /* Error Interrupt */
1749 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1750 ret = sci_er_interrupt(irq, ptr);
1752 /* Break Interrupt */
1753 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1754 ret = sci_br_interrupt(irq, ptr);
1756 /* Overrun Interrupt */
1757 if (orer_status & s->params->overrun_mask) {
1758 sci_handle_fifo_overrun(port);
1765 static const struct sci_irq_desc {
1767 irq_handler_t handler;
1768 } sci_irq_desc[] = {
1770 * Split out handlers, the default case.
1774 .handler = sci_er_interrupt,
1779 .handler = sci_rx_interrupt,
1784 .handler = sci_tx_interrupt,
1789 .handler = sci_br_interrupt,
1793 * Special muxed handler.
1797 .handler = sci_mpxed_interrupt,
1801 static int sci_request_irq(struct sci_port *port)
1803 struct uart_port *up = &port->port;
1806 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1807 const struct sci_irq_desc *desc;
1810 if (SCIx_IRQ_IS_MUXED(port)) {
1814 irq = port->irqs[i];
1817 * Certain port types won't support all of the
1818 * available interrupt sources.
1820 if (unlikely(irq < 0))
1824 desc = sci_irq_desc + i;
1825 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1826 dev_name(up->dev), desc->desc);
1827 if (!port->irqstr[j]) {
1832 ret = request_irq(irq, desc->handler, up->irqflags,
1833 port->irqstr[j], port);
1834 if (unlikely(ret)) {
1835 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1844 free_irq(port->irqs[i], port);
1848 kfree(port->irqstr[j]);
1853 static void sci_free_irq(struct sci_port *port)
1858 * Intentionally in reverse order so we iterate over the muxed
1861 for (i = 0; i < SCIx_NR_IRQS; i++) {
1862 int irq = port->irqs[i];
1865 * Certain port types won't support all of the available
1866 * interrupt sources.
1868 if (unlikely(irq < 0))
1871 free_irq(port->irqs[i], port);
1872 kfree(port->irqstr[i]);
1874 if (SCIx_IRQ_IS_MUXED(port)) {
1875 /* If there's only one IRQ, we're done. */
1881 static unsigned int sci_tx_empty(struct uart_port *port)
1883 unsigned short status = serial_port_in(port, SCxSR);
1884 unsigned short in_tx_fifo = sci_txfill(port);
1886 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1889 static void sci_set_rts(struct uart_port *port, bool state)
1891 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1892 u16 data = serial_port_in(port, SCPDR);
1896 data &= ~SCPDR_RTSD;
1899 serial_port_out(port, SCPDR, data);
1901 /* RTS# is output */
1902 serial_port_out(port, SCPCR,
1903 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1904 } else if (sci_getreg(port, SCSPTR)->size) {
1905 u16 ctrl = serial_port_in(port, SCSPTR);
1909 ctrl &= ~SCSPTR_RTSDT;
1911 ctrl |= SCSPTR_RTSDT;
1912 serial_port_out(port, SCSPTR, ctrl);
1916 static bool sci_get_cts(struct uart_port *port)
1918 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1920 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1921 } else if (sci_getreg(port, SCSPTR)->size) {
1923 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1930 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1931 * CTS/RTS is supported in hardware by at least one port and controlled
1932 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1933 * handled via the ->init_pins() op, which is a bit of a one-way street,
1934 * lacking any ability to defer pin control -- this will later be
1935 * converted over to the GPIO framework).
1937 * Other modes (such as loopback) are supported generically on certain
1938 * port types, but not others. For these it's sufficient to test for the
1939 * existence of the support register and simply ignore the port type.
1941 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1943 struct sci_port *s = to_sci_port(port);
1945 if (mctrl & TIOCM_LOOP) {
1946 const struct plat_sci_reg *reg;
1949 * Standard loopback mode for SCFCR ports.
1951 reg = sci_getreg(port, SCFCR);
1953 serial_port_out(port, SCFCR,
1954 serial_port_in(port, SCFCR) |
1958 mctrl_gpio_set(s->gpios, mctrl);
1963 if (!(mctrl & TIOCM_RTS)) {
1964 /* Disable Auto RTS */
1965 serial_port_out(port, SCFCR,
1966 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1969 sci_set_rts(port, 0);
1970 } else if (s->autorts) {
1971 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1972 /* Enable RTS# pin function */
1973 serial_port_out(port, SCPCR,
1974 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1977 /* Enable Auto RTS */
1978 serial_port_out(port, SCFCR,
1979 serial_port_in(port, SCFCR) | SCFCR_MCE);
1982 sci_set_rts(port, 1);
1986 static unsigned int sci_get_mctrl(struct uart_port *port)
1988 struct sci_port *s = to_sci_port(port);
1989 struct mctrl_gpios *gpios = s->gpios;
1990 unsigned int mctrl = 0;
1992 mctrl_gpio_get(gpios, &mctrl);
1995 * CTS/RTS is handled in hardware when supported, while nothing
1999 if (sci_get_cts(port))
2001 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2004 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2006 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2012 static void sci_enable_ms(struct uart_port *port)
2014 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2017 static void sci_break_ctl(struct uart_port *port, int break_state)
2019 unsigned short scscr, scsptr;
2021 /* check wheter the port has SCSPTR */
2022 if (!sci_getreg(port, SCSPTR)->size) {
2024 * Not supported by hardware. Most parts couple break and rx
2025 * interrupts together, with break detection always enabled.
2030 scsptr = serial_port_in(port, SCSPTR);
2031 scscr = serial_port_in(port, SCSCR);
2033 if (break_state == -1) {
2034 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2037 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2041 serial_port_out(port, SCSPTR, scsptr);
2042 serial_port_out(port, SCSCR, scscr);
2045 static int sci_startup(struct uart_port *port)
2047 struct sci_port *s = to_sci_port(port);
2050 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2052 sci_request_dma(port);
2054 ret = sci_request_irq(s);
2055 if (unlikely(ret < 0)) {
2063 static void sci_shutdown(struct uart_port *port)
2065 struct sci_port *s = to_sci_port(port);
2066 unsigned long flags;
2069 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2072 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2074 spin_lock_irqsave(&port->lock, flags);
2077 /* Stop RX and TX, disable related interrupts, keep clock source */
2078 scr = serial_port_in(port, SCSCR);
2079 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
2080 spin_unlock_irqrestore(&port->lock, flags);
2082 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2084 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2086 del_timer_sync(&s->rx_timer);
2090 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2091 del_timer_sync(&s->rx_fifo_timer);
2096 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2099 unsigned long freq = s->clk_rates[SCI_SCK];
2100 int err, min_err = INT_MAX;
2103 if (s->port.type != PORT_HSCIF)
2106 for_each_sr(sr, s) {
2107 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2108 if (abs(err) >= abs(min_err))
2118 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2123 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2124 unsigned long freq, unsigned int *dlr,
2127 int err, min_err = INT_MAX;
2128 unsigned int sr, dl;
2130 if (s->port.type != PORT_HSCIF)
2133 for_each_sr(sr, s) {
2134 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2135 dl = clamp(dl, 1U, 65535U);
2137 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2138 if (abs(err) >= abs(min_err))
2149 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2150 min_err, *dlr, *srr + 1);
2154 /* calculate sample rate, BRR, and clock select */
2155 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2156 unsigned int *brr, unsigned int *srr,
2159 unsigned long freq = s->clk_rates[SCI_FCK];
2160 unsigned int sr, br, prediv, scrate, c;
2161 int err, min_err = INT_MAX;
2163 if (s->port.type != PORT_HSCIF)
2167 * Find the combination of sample rate and clock select with the
2168 * smallest deviation from the desired baud rate.
2169 * Prefer high sample rates to maximise the receive margin.
2171 * M: Receive margin (%)
2172 * N: Ratio of bit rate to clock (N = sampling rate)
2173 * D: Clock duty (D = 0 to 1.0)
2174 * L: Frame length (L = 9 to 12)
2175 * F: Absolute value of clock frequency deviation
2177 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2178 * (|D - 0.5| / N * (1 + F))|
2179 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2181 for_each_sr(sr, s) {
2182 for (c = 0; c <= 3; c++) {
2183 /* integerized formulas from HSCIF documentation */
2184 prediv = sr * (1 << (2 * c + 1));
2187 * We need to calculate:
2189 * br = freq / (prediv * bps) clamped to [1..256]
2190 * err = freq / (br * prediv) - bps
2192 * Watch out for overflow when calculating the desired
2193 * sampling clock rate!
2195 if (bps > UINT_MAX / prediv)
2198 scrate = prediv * bps;
2199 br = DIV_ROUND_CLOSEST(freq, scrate);
2200 br = clamp(br, 1U, 256U);
2202 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2203 if (abs(err) >= abs(min_err))
2217 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2218 min_err, *brr, *srr + 1, *cks);
2222 static void sci_reset(struct uart_port *port)
2224 const struct plat_sci_reg *reg;
2225 unsigned int status;
2226 struct sci_port *s = to_sci_port(port);
2228 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
2230 reg = sci_getreg(port, SCFCR);
2232 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2234 sci_clear_SCxSR(port,
2235 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2236 SCxSR_BREAK_CLEAR(port));
2237 if (sci_getreg(port, SCLSR)->size) {
2238 status = serial_port_in(port, SCLSR);
2239 status &= ~(SCLSR_TO | SCLSR_ORER);
2240 serial_port_out(port, SCLSR, status);
2243 if (s->rx_trigger > 1) {
2244 if (s->rx_fifo_timeout) {
2245 scif_set_rtrg(port, 1);
2246 setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn,
2249 if (port->type == PORT_SCIFA ||
2250 port->type == PORT_SCIFB)
2251 scif_set_rtrg(port, 1);
2253 scif_set_rtrg(port, s->rx_trigger);
2258 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2259 struct ktermios *old)
2261 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2262 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2263 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2264 struct sci_port *s = to_sci_port(port);
2265 const struct plat_sci_reg *reg;
2266 int min_err = INT_MAX, err;
2267 unsigned long max_freq = 0;
2270 if ((termios->c_cflag & CSIZE) == CS7) {
2271 smr_val |= SCSMR_CHR;
2273 termios->c_cflag &= ~CSIZE;
2274 termios->c_cflag |= CS8;
2276 if (termios->c_cflag & PARENB)
2277 smr_val |= SCSMR_PE;
2278 if (termios->c_cflag & PARODD)
2279 smr_val |= SCSMR_PE | SCSMR_ODD;
2280 if (termios->c_cflag & CSTOPB)
2281 smr_val |= SCSMR_STOP;
2284 * earlyprintk comes here early on with port->uartclk set to zero.
2285 * the clock framework is not up and running at this point so here
2286 * we assume that 115200 is the maximum baud rate. please note that
2287 * the baud rate is not programmed during earlyprintk - it is assumed
2288 * that the previous boot loader has enabled required clocks and
2289 * setup the baud rate generator hardware for us already.
2291 if (!port->uartclk) {
2292 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2296 for (i = 0; i < SCI_NUM_CLKS; i++)
2297 max_freq = max(max_freq, s->clk_rates[i]);
2299 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2304 * There can be multiple sources for the sampling clock. Find the one
2305 * that gives us the smallest deviation from the desired baud rate.
2308 /* Optional Undivided External Clock */
2309 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2310 port->type != PORT_SCIFB) {
2311 err = sci_sck_calc(s, baud, &srr1);
2312 if (abs(err) < abs(min_err)) {
2314 scr_val = SCSCR_CKE1;
2323 /* Optional BRG Frequency Divided External Clock */
2324 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2325 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2327 if (abs(err) < abs(min_err)) {
2328 best_clk = SCI_SCIF_CLK;
2329 scr_val = SCSCR_CKE1;
2339 /* Optional BRG Frequency Divided Internal Clock */
2340 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2341 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2343 if (abs(err) < abs(min_err)) {
2344 best_clk = SCI_BRG_INT;
2345 scr_val = SCSCR_CKE1;
2355 /* Divided Functional Clock using standard Bit Rate Register */
2356 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2357 if (abs(err) < abs(min_err)) {
2368 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2369 s->clks[best_clk], baud, min_err);
2374 * Program the optional External Baud Rate Generator (BRG) first.
2375 * It controls the mux to select (H)SCK or frequency divided clock.
2377 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2378 serial_port_out(port, SCDL, dl);
2379 serial_port_out(port, SCCKS, sccks);
2384 uart_update_timeout(port, termios->c_cflag, baud);
2386 if (best_clk >= 0) {
2387 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2389 case 5: smr_val |= SCSMR_SRC_5; break;
2390 case 7: smr_val |= SCSMR_SRC_7; break;
2391 case 11: smr_val |= SCSMR_SRC_11; break;
2392 case 13: smr_val |= SCSMR_SRC_13; break;
2393 case 16: smr_val |= SCSMR_SRC_16; break;
2394 case 17: smr_val |= SCSMR_SRC_17; break;
2395 case 19: smr_val |= SCSMR_SRC_19; break;
2396 case 27: smr_val |= SCSMR_SRC_27; break;
2400 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2401 scr_val, smr_val, brr, sccks, dl, srr);
2402 serial_port_out(port, SCSCR, scr_val);
2403 serial_port_out(port, SCSMR, smr_val);
2404 serial_port_out(port, SCBRR, brr);
2405 if (sci_getreg(port, HSSRR)->size)
2406 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2408 /* Wait one bit interval */
2409 udelay((1000000 + (baud - 1)) / baud);
2411 /* Don't touch the bit rate configuration */
2412 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2413 smr_val |= serial_port_in(port, SCSMR) &
2414 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2415 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2416 serial_port_out(port, SCSCR, scr_val);
2417 serial_port_out(port, SCSMR, smr_val);
2420 sci_init_pins(port, termios->c_cflag);
2422 port->status &= ~UPSTAT_AUTOCTS;
2424 reg = sci_getreg(port, SCFCR);
2426 unsigned short ctrl = serial_port_in(port, SCFCR);
2428 if ((port->flags & UPF_HARD_FLOW) &&
2429 (termios->c_cflag & CRTSCTS)) {
2430 /* There is no CTS interrupt to restart the hardware */
2431 port->status |= UPSTAT_AUTOCTS;
2432 /* MCE is enabled when RTS is raised */
2437 * As we've done a sci_reset() above, ensure we don't
2438 * interfere with the FIFOs while toggling MCE. As the
2439 * reset values could still be set, simply mask them out.
2441 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2443 serial_port_out(port, SCFCR, ctrl);
2445 if (port->flags & UPF_HARD_FLOW) {
2446 /* Refresh (Auto) RTS */
2447 sci_set_mctrl(port, port->mctrl);
2450 scr_val |= SCSCR_RE | SCSCR_TE |
2451 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2452 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2453 serial_port_out(port, SCSCR, scr_val);
2454 if ((srr + 1 == 5) &&
2455 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2457 * In asynchronous mode, when the sampling rate is 1/5, first
2458 * received data may become invalid on some SCIFA and SCIFB.
2459 * To avoid this problem wait more than 1 serial data time (1
2460 * bit time x serial data number) after setting SCSCR.RE = 1.
2462 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2466 * Calculate delay for 2 DMA buffers (4 FIFO).
2467 * See serial_core.c::uart_update_timeout().
2468 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2469 * function calculates 1 jiffie for the data plus 5 jiffies for the
2470 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2471 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2472 * value obtained by this formula is too small. Therefore, if the value
2473 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2475 /* byte size and parity */
2476 switch (termios->c_cflag & CSIZE) {
2491 if (termios->c_cflag & CSTOPB)
2493 if (termios->c_cflag & PARENB)
2496 s->rx_frame = (100 * bits * HZ) / (baud / 10);
2497 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2498 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
2499 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2500 s->rx_timeout * 1000 / HZ, port->timeout);
2501 if (s->rx_timeout < msecs_to_jiffies(20))
2502 s->rx_timeout = msecs_to_jiffies(20);
2505 if ((termios->c_cflag & CREAD) != 0)
2508 sci_port_disable(s);
2510 if (UART_ENABLE_MS(port, termios->c_cflag))
2511 sci_enable_ms(port);
2514 static void sci_pm(struct uart_port *port, unsigned int state,
2515 unsigned int oldstate)
2517 struct sci_port *sci_port = to_sci_port(port);
2520 case UART_PM_STATE_OFF:
2521 sci_port_disable(sci_port);
2524 sci_port_enable(sci_port);
2529 static const char *sci_type(struct uart_port *port)
2531 switch (port->type) {
2549 static int sci_remap_port(struct uart_port *port)
2551 struct sci_port *sport = to_sci_port(port);
2554 * Nothing to do if there's already an established membase.
2559 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2560 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2561 if (unlikely(!port->membase)) {
2562 dev_err(port->dev, "can't remap port#%d\n", port->line);
2567 * For the simple (and majority of) cases where we don't
2568 * need to do any remapping, just cast the cookie
2571 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2577 static void sci_release_port(struct uart_port *port)
2579 struct sci_port *sport = to_sci_port(port);
2581 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2582 iounmap(port->membase);
2583 port->membase = NULL;
2586 release_mem_region(port->mapbase, sport->reg_size);
2589 static int sci_request_port(struct uart_port *port)
2591 struct resource *res;
2592 struct sci_port *sport = to_sci_port(port);
2595 res = request_mem_region(port->mapbase, sport->reg_size,
2596 dev_name(port->dev));
2597 if (unlikely(res == NULL)) {
2598 dev_err(port->dev, "request_mem_region failed.");
2602 ret = sci_remap_port(port);
2603 if (unlikely(ret != 0)) {
2604 release_resource(res);
2611 static void sci_config_port(struct uart_port *port, int flags)
2613 if (flags & UART_CONFIG_TYPE) {
2614 struct sci_port *sport = to_sci_port(port);
2616 port->type = sport->cfg->type;
2617 sci_request_port(port);
2621 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2623 if (ser->baud_base < 2400)
2624 /* No paper tape reader for Mitch.. */
2630 static const struct uart_ops sci_uart_ops = {
2631 .tx_empty = sci_tx_empty,
2632 .set_mctrl = sci_set_mctrl,
2633 .get_mctrl = sci_get_mctrl,
2634 .start_tx = sci_start_tx,
2635 .stop_tx = sci_stop_tx,
2636 .stop_rx = sci_stop_rx,
2637 .enable_ms = sci_enable_ms,
2638 .break_ctl = sci_break_ctl,
2639 .startup = sci_startup,
2640 .shutdown = sci_shutdown,
2641 .flush_buffer = sci_flush_buffer,
2642 .set_termios = sci_set_termios,
2645 .release_port = sci_release_port,
2646 .request_port = sci_request_port,
2647 .config_port = sci_config_port,
2648 .verify_port = sci_verify_port,
2649 #ifdef CONFIG_CONSOLE_POLL
2650 .poll_get_char = sci_poll_get_char,
2651 .poll_put_char = sci_poll_put_char,
2655 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2657 const char *clk_names[] = {
2660 [SCI_BRG_INT] = "brg_int",
2661 [SCI_SCIF_CLK] = "scif_clk",
2666 if (sci_port->cfg->type == PORT_HSCIF)
2667 clk_names[SCI_SCK] = "hsck";
2669 for (i = 0; i < SCI_NUM_CLKS; i++) {
2670 clk = devm_clk_get(dev, clk_names[i]);
2671 if (PTR_ERR(clk) == -EPROBE_DEFER)
2672 return -EPROBE_DEFER;
2674 if (IS_ERR(clk) && i == SCI_FCK) {
2676 * "fck" used to be called "sci_ick", and we need to
2677 * maintain DT backward compatibility.
2679 clk = devm_clk_get(dev, "sci_ick");
2680 if (PTR_ERR(clk) == -EPROBE_DEFER)
2681 return -EPROBE_DEFER;
2687 * Not all SH platforms declare a clock lookup entry
2688 * for SCI devices, in which case we need to get the
2689 * global "peripheral_clk" clock.
2691 clk = devm_clk_get(dev, "peripheral_clk");
2695 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2697 return PTR_ERR(clk);
2702 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2705 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2706 clk, clk_get_rate(clk));
2707 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2712 static const struct sci_port_params *
2713 sci_probe_regmap(const struct plat_sci_port *cfg)
2715 unsigned int regtype;
2717 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2718 return &sci_port_params[cfg->regtype];
2720 switch (cfg->type) {
2722 regtype = SCIx_SCI_REGTYPE;
2725 regtype = SCIx_IRDA_REGTYPE;
2728 regtype = SCIx_SCIFA_REGTYPE;
2731 regtype = SCIx_SCIFB_REGTYPE;
2735 * The SH-4 is a bit of a misnomer here, although that's
2736 * where this particular port layout originated. This
2737 * configuration (or some slight variation thereof)
2738 * remains the dominant model for all SCIFs.
2740 regtype = SCIx_SH4_SCIF_REGTYPE;
2743 regtype = SCIx_HSCIF_REGTYPE;
2746 pr_err("Can't probe register map for given port\n");
2750 return &sci_port_params[regtype];
2753 static int sci_init_single(struct platform_device *dev,
2754 struct sci_port *sci_port, unsigned int index,
2755 const struct plat_sci_port *p, bool early)
2757 struct uart_port *port = &sci_port->port;
2758 const struct resource *res;
2764 port->ops = &sci_uart_ops;
2765 port->iotype = UPIO_MEM;
2768 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2772 port->mapbase = res->start;
2773 sci_port->reg_size = resource_size(res);
2775 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2776 sci_port->irqs[i] = platform_get_irq(dev, i);
2778 /* The SCI generates several interrupts. They can be muxed together or
2779 * connected to different interrupt lines. In the muxed case only one
2780 * interrupt resource is specified. In the non-muxed case three or four
2781 * interrupt resources are specified, as the BRI interrupt is optional.
2783 if (sci_port->irqs[0] < 0)
2786 if (sci_port->irqs[1] < 0) {
2787 sci_port->irqs[1] = sci_port->irqs[0];
2788 sci_port->irqs[2] = sci_port->irqs[0];
2789 sci_port->irqs[3] = sci_port->irqs[0];
2792 sci_port->params = sci_probe_regmap(p);
2793 if (unlikely(sci_port->params == NULL))
2798 sci_port->rx_trigger = 48;
2801 sci_port->rx_trigger = 64;
2804 sci_port->rx_trigger = 32;
2807 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2808 /* RX triggering not implemented for this IP */
2809 sci_port->rx_trigger = 1;
2811 sci_port->rx_trigger = 8;
2814 sci_port->rx_trigger = 1;
2818 sci_port->rx_fifo_timeout = 0;
2820 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2821 * match the SoC datasheet, this should be investigated. Let platform
2822 * data override the sampling rate for now.
2824 sci_port->sampling_rate_mask = p->sampling_rate
2825 ? SCI_SR(p->sampling_rate)
2826 : sci_port->params->sampling_rate_mask;
2829 ret = sci_init_clocks(sci_port, &dev->dev);
2833 port->dev = &dev->dev;
2835 pm_runtime_enable(&dev->dev);
2838 port->type = p->type;
2839 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2840 port->fifosize = sci_port->params->fifosize;
2842 if (port->type == PORT_SCI && !dev->dev.of_node) {
2843 if (sci_port->reg_size >= 0x20)
2850 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2851 * for the multi-IRQ ports, which is where we are primarily
2852 * concerned with the shutdown path synchronization.
2854 * For the muxed case there's nothing more to do.
2856 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2859 port->serial_in = sci_serial_in;
2860 port->serial_out = sci_serial_out;
2865 static void sci_cleanup_single(struct sci_port *port)
2867 pm_runtime_disable(port->port.dev);
2870 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2871 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2872 static void serial_console_putchar(struct uart_port *port, int ch)
2874 sci_poll_put_char(port, ch);
2878 * Print a string to the serial port trying not to disturb
2879 * any possible real use of the port...
2881 static void serial_console_write(struct console *co, const char *s,
2884 struct sci_port *sci_port = &sci_ports[co->index];
2885 struct uart_port *port = &sci_port->port;
2886 unsigned short bits, ctrl, ctrl_temp;
2887 unsigned long flags;
2890 #if defined(SUPPORT_SYSRQ)
2895 if (oops_in_progress)
2896 locked = spin_trylock_irqsave(&port->lock, flags);
2898 spin_lock_irqsave(&port->lock, flags);
2900 /* first save SCSCR then disable interrupts, keep clock source */
2901 ctrl = serial_port_in(port, SCSCR);
2902 ctrl_temp = SCSCR_RE | SCSCR_TE |
2903 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2904 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2905 serial_port_out(port, SCSCR, ctrl_temp);
2907 uart_console_write(port, s, count, serial_console_putchar);
2909 /* wait until fifo is empty and last bit has been transmitted */
2910 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2911 while ((serial_port_in(port, SCxSR) & bits) != bits)
2914 /* restore the SCSCR */
2915 serial_port_out(port, SCSCR, ctrl);
2918 spin_unlock_irqrestore(&port->lock, flags);
2921 static int serial_console_setup(struct console *co, char *options)
2923 struct sci_port *sci_port;
2924 struct uart_port *port;
2932 * Refuse to handle any bogus ports.
2934 if (co->index < 0 || co->index >= SCI_NPORTS)
2937 sci_port = &sci_ports[co->index];
2938 port = &sci_port->port;
2941 * Refuse to handle uninitialized ports.
2946 ret = sci_remap_port(port);
2947 if (unlikely(ret != 0))
2951 uart_parse_options(options, &baud, &parity, &bits, &flow);
2953 return uart_set_options(port, co, baud, parity, bits, flow);
2956 static struct console serial_console = {
2958 .device = uart_console_device,
2959 .write = serial_console_write,
2960 .setup = serial_console_setup,
2961 .flags = CON_PRINTBUFFER,
2963 .data = &sci_uart_driver,
2966 static struct console early_serial_console = {
2967 .name = "early_ttySC",
2968 .write = serial_console_write,
2969 .flags = CON_PRINTBUFFER,
2973 static char early_serial_buf[32];
2975 static int sci_probe_earlyprintk(struct platform_device *pdev)
2977 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2979 if (early_serial_console.data)
2982 early_serial_console.index = pdev->id;
2984 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2986 serial_console_setup(&early_serial_console, early_serial_buf);
2988 if (!strstr(early_serial_buf, "keep"))
2989 early_serial_console.flags |= CON_BOOT;
2991 register_console(&early_serial_console);
2995 #define SCI_CONSOLE (&serial_console)
2998 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3003 #define SCI_CONSOLE NULL
3005 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3007 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3009 static DEFINE_MUTEX(sci_uart_registration_lock);
3010 static struct uart_driver sci_uart_driver = {
3011 .owner = THIS_MODULE,
3012 .driver_name = "sci",
3013 .dev_name = "ttySC",
3015 .minor = SCI_MINOR_START,
3017 .cons = SCI_CONSOLE,
3020 static int sci_remove(struct platform_device *dev)
3022 struct sci_port *port = platform_get_drvdata(dev);
3024 uart_remove_one_port(&sci_uart_driver, &port->port);
3026 sci_cleanup_single(port);
3028 if (port->port.fifosize > 1) {
3029 sysfs_remove_file(&dev->dev.kobj,
3030 &dev_attr_rx_fifo_trigger.attr);
3032 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB) {
3033 sysfs_remove_file(&dev->dev.kobj,
3034 &dev_attr_rx_fifo_timeout.attr);
3041 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3042 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3043 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3045 static const struct of_device_id of_sci_match[] = {
3046 /* SoC-specific types */
3048 .compatible = "renesas,scif-r7s72100",
3049 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3051 /* Family-specific types */
3053 .compatible = "renesas,rcar-gen1-scif",
3054 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3056 .compatible = "renesas,rcar-gen2-scif",
3057 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3059 .compatible = "renesas,rcar-gen3-scif",
3060 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3064 .compatible = "renesas,scif",
3065 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3067 .compatible = "renesas,scifa",
3068 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3070 .compatible = "renesas,scifb",
3071 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3073 .compatible = "renesas,hscif",
3074 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3076 .compatible = "renesas,sci",
3077 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3082 MODULE_DEVICE_TABLE(of, of_sci_match);
3084 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3085 unsigned int *dev_id)
3087 struct device_node *np = pdev->dev.of_node;
3088 const struct of_device_id *match;
3089 struct plat_sci_port *p;
3090 struct sci_port *sp;
3093 if (!IS_ENABLED(CONFIG_OF) || !np)
3096 match = of_match_node(of_sci_match, np);
3100 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3104 /* Get the line number from the aliases node. */
3105 id = of_alias_get_id(np, "serial");
3107 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3110 if (id >= ARRAY_SIZE(sci_ports)) {
3111 dev_err(&pdev->dev, "serial%d out of range\n", id);
3115 sp = &sci_ports[id];
3118 p->type = SCI_OF_TYPE(match->data);
3119 p->regtype = SCI_OF_REGTYPE(match->data);
3121 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3126 static int sci_probe_single(struct platform_device *dev,
3128 struct plat_sci_port *p,
3129 struct sci_port *sciport)
3134 if (unlikely(index >= SCI_NPORTS)) {
3135 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3136 index+1, SCI_NPORTS);
3137 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3141 mutex_lock(&sci_uart_registration_lock);
3142 if (!sci_uart_driver.state) {
3143 ret = uart_register_driver(&sci_uart_driver);
3145 mutex_unlock(&sci_uart_registration_lock);
3149 mutex_unlock(&sci_uart_registration_lock);
3151 ret = sci_init_single(dev, sciport, index, p, false);
3155 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3156 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3157 return PTR_ERR(sciport->gpios);
3159 if (sciport->has_rtscts) {
3160 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3162 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3164 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3167 sciport->port.flags |= UPF_HARD_FLOW;
3170 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3172 sci_cleanup_single(sciport);
3179 static int sci_probe(struct platform_device *dev)
3181 struct plat_sci_port *p;
3182 struct sci_port *sp;
3183 unsigned int dev_id;
3187 * If we've come here via earlyprintk initialization, head off to
3188 * the special early probe. We don't have sufficient device state
3189 * to make it beyond this yet.
3191 if (is_early_platform_device(dev))
3192 return sci_probe_earlyprintk(dev);
3194 if (dev->dev.of_node) {
3195 p = sci_parse_dt(dev, &dev_id);
3199 p = dev->dev.platform_data;
3201 dev_err(&dev->dev, "no platform data supplied\n");
3208 sp = &sci_ports[dev_id];
3209 platform_set_drvdata(dev, sp);
3211 ret = sci_probe_single(dev, dev_id, p, sp);
3215 if (sp->port.fifosize > 1) {
3216 ret = sysfs_create_file(&dev->dev.kobj,
3217 &dev_attr_rx_fifo_trigger.attr);
3221 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB) {
3222 ret = sysfs_create_file(&dev->dev.kobj,
3223 &dev_attr_rx_fifo_timeout.attr);
3225 if (sp->port.fifosize > 1) {
3226 sysfs_remove_file(&dev->dev.kobj,
3227 &dev_attr_rx_fifo_trigger.attr);
3233 #ifdef CONFIG_SH_STANDARD_BIOS
3234 sh_bios_gdb_detach();
3240 static __maybe_unused int sci_suspend(struct device *dev)
3242 struct sci_port *sport = dev_get_drvdata(dev);
3245 uart_suspend_port(&sci_uart_driver, &sport->port);
3250 static __maybe_unused int sci_resume(struct device *dev)
3252 struct sci_port *sport = dev_get_drvdata(dev);
3255 uart_resume_port(&sci_uart_driver, &sport->port);
3260 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3262 static struct platform_driver sci_driver = {
3264 .remove = sci_remove,
3267 .pm = &sci_dev_pm_ops,
3268 .of_match_table = of_match_ptr(of_sci_match),
3272 static int __init sci_init(void)
3274 pr_info("%s\n", banner);
3276 return platform_driver_register(&sci_driver);
3279 static void __exit sci_exit(void)
3281 platform_driver_unregister(&sci_driver);
3283 if (sci_uart_driver.state)
3284 uart_unregister_driver(&sci_uart_driver);
3287 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3288 early_platform_init_buffer("earlyprintk", &sci_driver,
3289 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3291 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3292 static struct __init plat_sci_port port_cfg;
3294 static int __init early_console_setup(struct earlycon_device *device,
3297 if (!device->port.membase)
3300 device->port.serial_in = sci_serial_in;
3301 device->port.serial_out = sci_serial_out;
3302 device->port.type = type;
3303 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3304 port_cfg.type = type;
3305 sci_ports[0].cfg = &port_cfg;
3306 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3307 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3308 sci_serial_out(&sci_ports[0].port, SCSCR,
3309 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3311 device->con->write = serial_console_write;
3314 static int __init sci_early_console_setup(struct earlycon_device *device,
3317 return early_console_setup(device, PORT_SCI);
3319 static int __init scif_early_console_setup(struct earlycon_device *device,
3322 return early_console_setup(device, PORT_SCIF);
3324 static int __init scifa_early_console_setup(struct earlycon_device *device,
3327 return early_console_setup(device, PORT_SCIFA);
3329 static int __init scifb_early_console_setup(struct earlycon_device *device,
3332 return early_console_setup(device, PORT_SCIFB);
3334 static int __init hscif_early_console_setup(struct earlycon_device *device,
3337 return early_console_setup(device, PORT_HSCIF);
3340 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3341 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3342 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3343 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3344 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3345 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3347 module_init(sci_init);
3348 module_exit(sci_exit);
3350 MODULE_LICENSE("GPL");
3351 MODULE_ALIAS("platform:sh-sci");
3352 MODULE_AUTHOR("Paul Mundt");
3353 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");