2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
56 #include <asm/sh_bios.h>
61 /* Offsets into the sci_port->irqs array */
69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72 #define SCIx_IRQ_IS_MUXED(port) \
73 ((port)->irqs[SCIx_ERI_IRQ] == \
74 (port)->irqs[SCIx_RXI_IRQ]) || \
75 ((port)->irqs[SCIx_ERI_IRQ] && \
76 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79 struct uart_port port;
81 /* Platform configuration */
82 struct plat_sci_port *cfg;
83 unsigned int overrun_reg;
84 unsigned int overrun_mask;
85 unsigned int error_mask;
86 unsigned int error_clear;
87 unsigned int sampling_rate;
88 resource_size_t reg_size;
91 struct timer_list break_timer;
99 int irqs[SCIx_NR_IRQS];
100 char *irqstr[SCIx_NR_IRQS];
102 struct dma_chan *chan_tx;
103 struct dma_chan *chan_rx;
105 #ifdef CONFIG_SERIAL_SH_SCI_DMA
106 dma_cookie_t cookie_tx;
107 dma_cookie_t cookie_rx[2];
108 dma_cookie_t active_rx;
109 dma_addr_t tx_dma_addr;
110 unsigned int tx_dma_len;
111 struct scatterlist sg_rx[2];
114 struct work_struct work_tx;
115 struct timer_list rx_timer;
116 unsigned int rx_timeout;
120 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
122 static struct sci_port sci_ports[SCI_NPORTS];
123 static struct uart_driver sci_uart_driver;
125 static inline struct sci_port *
126 to_sci_port(struct uart_port *uart)
128 return container_of(uart, struct sci_port, port);
131 struct plat_sci_reg {
135 /* Helper for invalidating specific entries of an inherited map. */
136 #define sci_reg_invalid { .offset = 0, .size = 0 }
138 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
139 [SCIx_PROBE_REGTYPE] = {
140 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
144 * Common SCI definitions, dependent on the port's regshift
147 [SCIx_SCI_REGTYPE] = {
148 [SCSMR] = { 0x00, 8 },
149 [SCBRR] = { 0x01, 8 },
150 [SCSCR] = { 0x02, 8 },
151 [SCxTDR] = { 0x03, 8 },
152 [SCxSR] = { 0x04, 8 },
153 [SCxRDR] = { 0x05, 8 },
154 [SCFCR] = sci_reg_invalid,
155 [SCFDR] = sci_reg_invalid,
156 [SCTFDR] = sci_reg_invalid,
157 [SCRFDR] = sci_reg_invalid,
158 [SCSPTR] = sci_reg_invalid,
159 [SCLSR] = sci_reg_invalid,
160 [HSSRR] = sci_reg_invalid,
161 [SCPCR] = sci_reg_invalid,
162 [SCPDR] = sci_reg_invalid,
166 * Common definitions for legacy IrDA ports.
168 [SCIx_IRDA_REGTYPE] = {
169 [SCSMR] = { 0x00, 8 },
170 [SCBRR] = { 0x02, 8 },
171 [SCSCR] = { 0x04, 8 },
172 [SCxTDR] = { 0x06, 8 },
173 [SCxSR] = { 0x08, 16 },
174 [SCxRDR] = { 0x0a, 8 },
175 [SCFCR] = { 0x0c, 8 },
176 [SCFDR] = { 0x0e, 16 },
177 [SCTFDR] = sci_reg_invalid,
178 [SCRFDR] = sci_reg_invalid,
179 [SCSPTR] = sci_reg_invalid,
180 [SCLSR] = sci_reg_invalid,
181 [HSSRR] = sci_reg_invalid,
182 [SCPCR] = sci_reg_invalid,
183 [SCPDR] = sci_reg_invalid,
187 * Common SCIFA definitions.
189 [SCIx_SCIFA_REGTYPE] = {
190 [SCSMR] = { 0x00, 16 },
191 [SCBRR] = { 0x04, 8 },
192 [SCSCR] = { 0x08, 16 },
193 [SCxTDR] = { 0x20, 8 },
194 [SCxSR] = { 0x14, 16 },
195 [SCxRDR] = { 0x24, 8 },
196 [SCFCR] = { 0x18, 16 },
197 [SCFDR] = { 0x1c, 16 },
198 [SCTFDR] = sci_reg_invalid,
199 [SCRFDR] = sci_reg_invalid,
200 [SCSPTR] = sci_reg_invalid,
201 [SCLSR] = sci_reg_invalid,
202 [HSSRR] = sci_reg_invalid,
203 [SCPCR] = { 0x30, 16 },
204 [SCPDR] = { 0x34, 16 },
208 * Common SCIFB definitions.
210 [SCIx_SCIFB_REGTYPE] = {
211 [SCSMR] = { 0x00, 16 },
212 [SCBRR] = { 0x04, 8 },
213 [SCSCR] = { 0x08, 16 },
214 [SCxTDR] = { 0x40, 8 },
215 [SCxSR] = { 0x14, 16 },
216 [SCxRDR] = { 0x60, 8 },
217 [SCFCR] = { 0x18, 16 },
218 [SCFDR] = sci_reg_invalid,
219 [SCTFDR] = { 0x38, 16 },
220 [SCRFDR] = { 0x3c, 16 },
221 [SCSPTR] = sci_reg_invalid,
222 [SCLSR] = sci_reg_invalid,
223 [HSSRR] = sci_reg_invalid,
224 [SCPCR] = { 0x30, 16 },
225 [SCPDR] = { 0x34, 16 },
229 * Common SH-2(A) SCIF definitions for ports with FIFO data
232 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
233 [SCSMR] = { 0x00, 16 },
234 [SCBRR] = { 0x04, 8 },
235 [SCSCR] = { 0x08, 16 },
236 [SCxTDR] = { 0x0c, 8 },
237 [SCxSR] = { 0x10, 16 },
238 [SCxRDR] = { 0x14, 8 },
239 [SCFCR] = { 0x18, 16 },
240 [SCFDR] = { 0x1c, 16 },
241 [SCTFDR] = sci_reg_invalid,
242 [SCRFDR] = sci_reg_invalid,
243 [SCSPTR] = { 0x20, 16 },
244 [SCLSR] = { 0x24, 16 },
245 [HSSRR] = sci_reg_invalid,
246 [SCPCR] = sci_reg_invalid,
247 [SCPDR] = sci_reg_invalid,
251 * Common SH-3 SCIF definitions.
253 [SCIx_SH3_SCIF_REGTYPE] = {
254 [SCSMR] = { 0x00, 8 },
255 [SCBRR] = { 0x02, 8 },
256 [SCSCR] = { 0x04, 8 },
257 [SCxTDR] = { 0x06, 8 },
258 [SCxSR] = { 0x08, 16 },
259 [SCxRDR] = { 0x0a, 8 },
260 [SCFCR] = { 0x0c, 8 },
261 [SCFDR] = { 0x0e, 16 },
262 [SCTFDR] = sci_reg_invalid,
263 [SCRFDR] = sci_reg_invalid,
264 [SCSPTR] = sci_reg_invalid,
265 [SCLSR] = sci_reg_invalid,
266 [HSSRR] = sci_reg_invalid,
267 [SCPCR] = sci_reg_invalid,
268 [SCPDR] = sci_reg_invalid,
272 * Common SH-4(A) SCIF(B) definitions.
274 [SCIx_SH4_SCIF_REGTYPE] = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCTFDR] = sci_reg_invalid,
284 [SCRFDR] = sci_reg_invalid,
285 [SCSPTR] = { 0x20, 16 },
286 [SCLSR] = { 0x24, 16 },
287 [HSSRR] = sci_reg_invalid,
288 [SCPCR] = sci_reg_invalid,
289 [SCPDR] = sci_reg_invalid,
293 * Common HSCIF definitions.
295 [SCIx_HSCIF_REGTYPE] = {
296 [SCSMR] = { 0x00, 16 },
297 [SCBRR] = { 0x04, 8 },
298 [SCSCR] = { 0x08, 16 },
299 [SCxTDR] = { 0x0c, 8 },
300 [SCxSR] = { 0x10, 16 },
301 [SCxRDR] = { 0x14, 8 },
302 [SCFCR] = { 0x18, 16 },
303 [SCFDR] = { 0x1c, 16 },
304 [SCTFDR] = sci_reg_invalid,
305 [SCRFDR] = sci_reg_invalid,
306 [SCSPTR] = { 0x20, 16 },
307 [SCLSR] = { 0x24, 16 },
308 [HSSRR] = { 0x40, 16 },
309 [SCPCR] = sci_reg_invalid,
310 [SCPDR] = sci_reg_invalid,
314 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
317 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
318 [SCSMR] = { 0x00, 16 },
319 [SCBRR] = { 0x04, 8 },
320 [SCSCR] = { 0x08, 16 },
321 [SCxTDR] = { 0x0c, 8 },
322 [SCxSR] = { 0x10, 16 },
323 [SCxRDR] = { 0x14, 8 },
324 [SCFCR] = { 0x18, 16 },
325 [SCFDR] = { 0x1c, 16 },
326 [SCTFDR] = sci_reg_invalid,
327 [SCRFDR] = sci_reg_invalid,
328 [SCSPTR] = sci_reg_invalid,
329 [SCLSR] = { 0x24, 16 },
330 [HSSRR] = sci_reg_invalid,
331 [SCPCR] = sci_reg_invalid,
332 [SCPDR] = sci_reg_invalid,
336 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
339 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
340 [SCSMR] = { 0x00, 16 },
341 [SCBRR] = { 0x04, 8 },
342 [SCSCR] = { 0x08, 16 },
343 [SCxTDR] = { 0x0c, 8 },
344 [SCxSR] = { 0x10, 16 },
345 [SCxRDR] = { 0x14, 8 },
346 [SCFCR] = { 0x18, 16 },
347 [SCFDR] = { 0x1c, 16 },
348 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
349 [SCRFDR] = { 0x20, 16 },
350 [SCSPTR] = { 0x24, 16 },
351 [SCLSR] = { 0x28, 16 },
352 [HSSRR] = sci_reg_invalid,
353 [SCPCR] = sci_reg_invalid,
354 [SCPDR] = sci_reg_invalid,
358 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
361 [SCIx_SH7705_SCIF_REGTYPE] = {
362 [SCSMR] = { 0x00, 16 },
363 [SCBRR] = { 0x04, 8 },
364 [SCSCR] = { 0x08, 16 },
365 [SCxTDR] = { 0x20, 8 },
366 [SCxSR] = { 0x14, 16 },
367 [SCxRDR] = { 0x24, 8 },
368 [SCFCR] = { 0x18, 16 },
369 [SCFDR] = { 0x1c, 16 },
370 [SCTFDR] = sci_reg_invalid,
371 [SCRFDR] = sci_reg_invalid,
372 [SCSPTR] = sci_reg_invalid,
373 [SCLSR] = sci_reg_invalid,
374 [HSSRR] = sci_reg_invalid,
375 [SCPCR] = sci_reg_invalid,
376 [SCPDR] = sci_reg_invalid,
380 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
383 * The "offset" here is rather misleading, in that it refers to an enum
384 * value relative to the port mapping rather than the fixed offset
385 * itself, which needs to be manually retrieved from the platform's
386 * register map for the given port.
388 static unsigned int sci_serial_in(struct uart_port *p, int offset)
390 const struct plat_sci_reg *reg = sci_getreg(p, offset);
393 return ioread8(p->membase + (reg->offset << p->regshift));
394 else if (reg->size == 16)
395 return ioread16(p->membase + (reg->offset << p->regshift));
397 WARN(1, "Invalid register access\n");
402 static void sci_serial_out(struct uart_port *p, int offset, int value)
404 const struct plat_sci_reg *reg = sci_getreg(p, offset);
407 iowrite8(value, p->membase + (reg->offset << p->regshift));
408 else if (reg->size == 16)
409 iowrite16(value, p->membase + (reg->offset << p->regshift));
411 WARN(1, "Invalid register access\n");
414 static int sci_probe_regmap(struct plat_sci_port *cfg)
418 cfg->regtype = SCIx_SCI_REGTYPE;
421 cfg->regtype = SCIx_IRDA_REGTYPE;
424 cfg->regtype = SCIx_SCIFA_REGTYPE;
427 cfg->regtype = SCIx_SCIFB_REGTYPE;
431 * The SH-4 is a bit of a misnomer here, although that's
432 * where this particular port layout originated. This
433 * configuration (or some slight variation thereof)
434 * remains the dominant model for all SCIFs.
436 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
439 cfg->regtype = SCIx_HSCIF_REGTYPE;
442 pr_err("Can't probe register map for given port\n");
449 static void sci_port_enable(struct sci_port *sci_port)
451 if (!sci_port->port.dev)
454 pm_runtime_get_sync(sci_port->port.dev);
456 clk_prepare_enable(sci_port->iclk);
457 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
458 clk_prepare_enable(sci_port->fclk);
461 static void sci_port_disable(struct sci_port *sci_port)
463 if (!sci_port->port.dev)
466 /* Cancel the break timer to ensure that the timer handler will not try
467 * to access the hardware with clocks and power disabled. Reset the
468 * break flag to make the break debouncing state machine ready for the
471 del_timer_sync(&sci_port->break_timer);
472 sci_port->break_flag = 0;
474 clk_disable_unprepare(sci_port->fclk);
475 clk_disable_unprepare(sci_port->iclk);
477 pm_runtime_put_sync(sci_port->port.dev);
480 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
483 * Not all ports (such as SCIFA) will support REIE. Rather than
484 * special-casing the port type, we check the port initialization
485 * IRQ enable mask to see whether the IRQ is desired at all. If
486 * it's unset, it's logically inferred that there's no point in
489 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
492 static void sci_start_tx(struct uart_port *port)
494 struct sci_port *s = to_sci_port(port);
497 #ifdef CONFIG_SERIAL_SH_SCI_DMA
498 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
499 u16 new, scr = serial_port_in(port, SCSCR);
501 new = scr | SCSCR_TDRQE;
503 new = scr & ~SCSCR_TDRQE;
505 serial_port_out(port, SCSCR, new);
508 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
509 dma_submit_error(s->cookie_tx)) {
511 schedule_work(&s->work_tx);
515 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
516 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
517 ctrl = serial_port_in(port, SCSCR);
518 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
522 static void sci_stop_tx(struct uart_port *port)
526 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
527 ctrl = serial_port_in(port, SCSCR);
529 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
530 ctrl &= ~SCSCR_TDRQE;
534 serial_port_out(port, SCSCR, ctrl);
537 static void sci_start_rx(struct uart_port *port)
541 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
544 ctrl &= ~SCSCR_RDRQE;
546 serial_port_out(port, SCSCR, ctrl);
549 static void sci_stop_rx(struct uart_port *port)
553 ctrl = serial_port_in(port, SCSCR);
555 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
556 ctrl &= ~SCSCR_RDRQE;
558 ctrl &= ~port_rx_irq_mask(port);
560 serial_port_out(port, SCSCR, ctrl);
563 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
565 if (port->type == PORT_SCI) {
566 /* Just store the mask */
567 serial_port_out(port, SCxSR, mask);
568 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
569 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
570 /* Only clear the status bits we want to clear */
571 serial_port_out(port, SCxSR,
572 serial_port_in(port, SCxSR) & mask);
574 /* Store the mask, clear parity/framing errors */
575 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
579 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
581 #ifdef CONFIG_CONSOLE_POLL
582 static int sci_poll_get_char(struct uart_port *port)
584 unsigned short status;
588 status = serial_port_in(port, SCxSR);
589 if (status & SCxSR_ERRORS(port)) {
590 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
596 if (!(status & SCxSR_RDxF(port)))
599 c = serial_port_in(port, SCxRDR);
602 serial_port_in(port, SCxSR);
603 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
609 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
611 unsigned short status;
614 status = serial_port_in(port, SCxSR);
615 } while (!(status & SCxSR_TDxE(port)));
617 serial_port_out(port, SCxTDR, c);
618 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
620 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
622 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
624 struct sci_port *s = to_sci_port(port);
625 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
628 * Use port-specific handler if provided.
630 if (s->cfg->ops && s->cfg->ops->init_pins) {
631 s->cfg->ops->init_pins(port, cflag);
636 * For the generic path SCSPTR is necessary. Bail out if that's
642 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
643 ((!(cflag & CRTSCTS)))) {
644 unsigned short status;
646 status = serial_port_in(port, SCSPTR);
647 status &= ~SCSPTR_CTSIO;
648 status |= SCSPTR_RTSIO;
649 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
653 static int sci_txfill(struct uart_port *port)
655 const struct plat_sci_reg *reg;
657 reg = sci_getreg(port, SCTFDR);
659 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
661 reg = sci_getreg(port, SCFDR);
663 return serial_port_in(port, SCFDR) >> 8;
665 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
668 static int sci_txroom(struct uart_port *port)
670 return port->fifosize - sci_txfill(port);
673 static int sci_rxfill(struct uart_port *port)
675 const struct plat_sci_reg *reg;
677 reg = sci_getreg(port, SCRFDR);
679 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
681 reg = sci_getreg(port, SCFDR);
683 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
685 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
689 * SCI helper for checking the state of the muxed port/RXD pins.
691 static inline int sci_rxd_in(struct uart_port *port)
693 struct sci_port *s = to_sci_port(port);
695 if (s->cfg->port_reg <= 0)
698 /* Cast for ARM damage */
699 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
702 /* ********************************************************************** *
703 * the interrupt related routines *
704 * ********************************************************************** */
706 static void sci_transmit_chars(struct uart_port *port)
708 struct circ_buf *xmit = &port->state->xmit;
709 unsigned int stopped = uart_tx_stopped(port);
710 unsigned short status;
714 status = serial_port_in(port, SCxSR);
715 if (!(status & SCxSR_TDxE(port))) {
716 ctrl = serial_port_in(port, SCSCR);
717 if (uart_circ_empty(xmit))
721 serial_port_out(port, SCSCR, ctrl);
725 count = sci_txroom(port);
733 } else if (!uart_circ_empty(xmit) && !stopped) {
734 c = xmit->buf[xmit->tail];
735 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
740 serial_port_out(port, SCxTDR, c);
743 } while (--count > 0);
745 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
747 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
748 uart_write_wakeup(port);
749 if (uart_circ_empty(xmit))
754 /* On SH3, SCIF may read end-of-break as a space->mark char */
755 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
757 static void sci_receive_chars(struct uart_port *port)
759 struct sci_port *sci_port = to_sci_port(port);
760 struct tty_port *tport = &port->state->port;
761 int i, count, copied = 0;
762 unsigned short status;
765 status = serial_port_in(port, SCxSR);
766 if (!(status & SCxSR_RDxF(port)))
770 /* Don't copy more bytes than there is room for in the buffer */
771 count = tty_buffer_request_room(tport, sci_rxfill(port));
773 /* If for any reason we can't copy more data, we're done! */
777 if (port->type == PORT_SCI) {
778 char c = serial_port_in(port, SCxRDR);
779 if (uart_handle_sysrq_char(port, c) ||
780 sci_port->break_flag)
783 tty_insert_flip_char(tport, c, TTY_NORMAL);
785 for (i = 0; i < count; i++) {
786 char c = serial_port_in(port, SCxRDR);
788 status = serial_port_in(port, SCxSR);
789 #if defined(CONFIG_CPU_SH3)
790 /* Skip "chars" during break */
791 if (sci_port->break_flag) {
793 (status & SCxSR_FER(port))) {
798 /* Nonzero => end-of-break */
799 dev_dbg(port->dev, "debounce<%02x>\n", c);
800 sci_port->break_flag = 0;
807 #endif /* CONFIG_CPU_SH3 */
808 if (uart_handle_sysrq_char(port, c)) {
813 /* Store data and status */
814 if (status & SCxSR_FER(port)) {
816 port->icount.frame++;
817 dev_notice(port->dev, "frame error\n");
818 } else if (status & SCxSR_PER(port)) {
820 port->icount.parity++;
821 dev_notice(port->dev, "parity error\n");
825 tty_insert_flip_char(tport, c, flag);
829 serial_port_in(port, SCxSR); /* dummy read */
830 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
833 port->icount.rx += count;
837 /* Tell the rest of the system the news. New characters! */
838 tty_flip_buffer_push(tport);
840 /* TTY buffers full; read from RX reg to prevent lockup */
841 serial_port_in(port, SCxRDR);
842 serial_port_in(port, SCxSR); /* dummy read */
843 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
847 #define SCI_BREAK_JIFFIES (HZ/20)
850 * The sci generates interrupts during the break,
851 * 1 per millisecond or so during the break period, for 9600 baud.
852 * So dont bother disabling interrupts.
853 * But dont want more than 1 break event.
854 * Use a kernel timer to periodically poll the rx line until
855 * the break is finished.
857 static inline void sci_schedule_break_timer(struct sci_port *port)
859 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
862 /* Ensure that two consecutive samples find the break over. */
863 static void sci_break_timer(unsigned long data)
865 struct sci_port *port = (struct sci_port *)data;
867 if (sci_rxd_in(&port->port) == 0) {
868 port->break_flag = 1;
869 sci_schedule_break_timer(port);
870 } else if (port->break_flag == 1) {
872 port->break_flag = 2;
873 sci_schedule_break_timer(port);
875 port->break_flag = 0;
878 static int sci_handle_errors(struct uart_port *port)
881 unsigned short status = serial_port_in(port, SCxSR);
882 struct tty_port *tport = &port->state->port;
883 struct sci_port *s = to_sci_port(port);
885 /* Handle overruns */
886 if (status & s->overrun_mask) {
887 port->icount.overrun++;
890 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
893 dev_notice(port->dev, "overrun error\n");
896 if (status & SCxSR_FER(port)) {
897 if (sci_rxd_in(port) == 0) {
898 /* Notify of BREAK */
899 struct sci_port *sci_port = to_sci_port(port);
901 if (!sci_port->break_flag) {
904 sci_port->break_flag = 1;
905 sci_schedule_break_timer(sci_port);
907 /* Do sysrq handling. */
908 if (uart_handle_break(port))
911 dev_dbg(port->dev, "BREAK detected\n");
913 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
919 port->icount.frame++;
921 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
924 dev_notice(port->dev, "frame error\n");
928 if (status & SCxSR_PER(port)) {
930 port->icount.parity++;
932 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
935 dev_notice(port->dev, "parity error\n");
939 tty_flip_buffer_push(tport);
944 static int sci_handle_fifo_overrun(struct uart_port *port)
946 struct tty_port *tport = &port->state->port;
947 struct sci_port *s = to_sci_port(port);
948 const struct plat_sci_reg *reg;
952 reg = sci_getreg(port, s->overrun_reg);
956 status = serial_port_in(port, s->overrun_reg);
957 if (status & s->overrun_mask) {
958 status &= ~s->overrun_mask;
959 serial_port_out(port, s->overrun_reg, status);
961 port->icount.overrun++;
963 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
964 tty_flip_buffer_push(tport);
966 dev_dbg(port->dev, "overrun error\n");
973 static int sci_handle_breaks(struct uart_port *port)
976 unsigned short status = serial_port_in(port, SCxSR);
977 struct tty_port *tport = &port->state->port;
978 struct sci_port *s = to_sci_port(port);
980 if (uart_handle_break(port))
983 if (!s->break_flag && status & SCxSR_BRK(port)) {
984 #if defined(CONFIG_CPU_SH3)
991 /* Notify of BREAK */
992 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
995 dev_dbg(port->dev, "BREAK detected\n");
999 tty_flip_buffer_push(tport);
1001 copied += sci_handle_fifo_overrun(port);
1006 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1007 static void sci_dma_tx_complete(void *arg)
1009 struct sci_port *s = arg;
1010 struct uart_port *port = &s->port;
1011 struct circ_buf *xmit = &port->state->xmit;
1012 unsigned long flags;
1014 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1016 spin_lock_irqsave(&port->lock, flags);
1018 xmit->tail += s->tx_dma_len;
1019 xmit->tail &= UART_XMIT_SIZE - 1;
1021 port->icount.tx += s->tx_dma_len;
1023 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1024 uart_write_wakeup(port);
1026 if (!uart_circ_empty(xmit)) {
1028 schedule_work(&s->work_tx);
1030 s->cookie_tx = -EINVAL;
1031 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1032 u16 ctrl = serial_port_in(port, SCSCR);
1033 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1037 spin_unlock_irqrestore(&port->lock, flags);
1040 /* Locking: called with port lock held */
1041 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1043 struct uart_port *port = &s->port;
1044 struct tty_port *tport = &port->state->port;
1047 copied = tty_insert_flip_string(tport, buf, count);
1048 if (copied < count) {
1049 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1051 port->icount.buf_overrun++;
1054 port->icount.rx += copied;
1059 static int sci_dma_rx_find_active(struct sci_port *s)
1063 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1064 if (s->active_rx == s->cookie_rx[i])
1067 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1072 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1074 struct dma_chan *chan = s->chan_rx;
1075 struct uart_port *port = &s->port;
1076 unsigned long flags;
1078 spin_lock_irqsave(&port->lock, flags);
1080 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1081 spin_unlock_irqrestore(&port->lock, flags);
1082 dmaengine_terminate_all(chan);
1083 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1084 sg_dma_address(&s->sg_rx[0]));
1085 dma_release_channel(chan);
1090 static void sci_dma_rx_complete(void *arg)
1092 struct sci_port *s = arg;
1093 struct dma_chan *chan = s->chan_rx;
1094 struct uart_port *port = &s->port;
1095 struct dma_async_tx_descriptor *desc;
1096 unsigned long flags;
1097 int active, count = 0;
1099 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1102 spin_lock_irqsave(&port->lock, flags);
1104 active = sci_dma_rx_find_active(s);
1106 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1108 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1111 tty_flip_buffer_push(&port->state->port);
1113 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1115 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1119 desc->callback = sci_dma_rx_complete;
1120 desc->callback_param = s;
1121 s->cookie_rx[active] = dmaengine_submit(desc);
1122 if (dma_submit_error(s->cookie_rx[active]))
1125 s->active_rx = s->cookie_rx[!active];
1127 dma_async_issue_pending(chan);
1129 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1130 __func__, s->cookie_rx[active], active, s->active_rx);
1131 spin_unlock_irqrestore(&port->lock, flags);
1135 spin_unlock_irqrestore(&port->lock, flags);
1136 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1137 sci_rx_dma_release(s, true);
1140 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1142 struct dma_chan *chan = s->chan_tx;
1143 struct uart_port *port = &s->port;
1144 unsigned long flags;
1146 spin_lock_irqsave(&port->lock, flags);
1148 s->cookie_tx = -EINVAL;
1149 spin_unlock_irqrestore(&port->lock, flags);
1150 dmaengine_terminate_all(chan);
1151 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1153 dma_release_channel(chan);
1158 static void sci_submit_rx(struct sci_port *s)
1160 struct dma_chan *chan = s->chan_rx;
1163 for (i = 0; i < 2; i++) {
1164 struct scatterlist *sg = &s->sg_rx[i];
1165 struct dma_async_tx_descriptor *desc;
1167 desc = dmaengine_prep_slave_sg(chan,
1168 sg, 1, DMA_DEV_TO_MEM,
1169 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1173 desc->callback = sci_dma_rx_complete;
1174 desc->callback_param = s;
1175 s->cookie_rx[i] = dmaengine_submit(desc);
1176 if (dma_submit_error(s->cookie_rx[i]))
1179 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1180 s->cookie_rx[i], i);
1183 s->active_rx = s->cookie_rx[0];
1185 dma_async_issue_pending(chan);
1190 dmaengine_terminate_all(chan);
1191 for (i = 0; i < 2; i++)
1192 s->cookie_rx[i] = -EINVAL;
1193 s->active_rx = -EINVAL;
1194 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1195 sci_rx_dma_release(s, true);
1198 static void work_fn_tx(struct work_struct *work)
1200 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1201 struct dma_async_tx_descriptor *desc;
1202 struct dma_chan *chan = s->chan_tx;
1203 struct uart_port *port = &s->port;
1204 struct circ_buf *xmit = &port->state->xmit;
1210 * Port xmit buffer is already mapped, and it is one page... Just adjust
1211 * offsets and lengths. Since it is a circular buffer, we have to
1212 * transmit till the end, and then the rest. Take the port lock to get a
1213 * consistent xmit buffer state.
1215 spin_lock_irq(&port->lock);
1218 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1219 s->tx_dma_len = min_t(unsigned int,
1220 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1221 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1222 if (!s->tx_dma_len) {
1223 /* Transmit buffer has been flushed */
1224 spin_unlock_irq(&port->lock);
1228 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1230 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1232 spin_unlock_irq(&port->lock);
1233 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1235 sci_tx_dma_release(s, true);
1239 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1242 desc->callback = sci_dma_tx_complete;
1243 desc->callback_param = s;
1244 s->cookie_tx = dmaengine_submit(desc);
1245 if (dma_submit_error(s->cookie_tx)) {
1246 spin_unlock_irq(&port->lock);
1247 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1249 sci_tx_dma_release(s, true);
1253 spin_unlock_irq(&port->lock);
1254 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1255 __func__, xmit->buf, tail, head, s->cookie_tx);
1257 dma_async_issue_pending(chan);
1260 static void rx_timer_fn(unsigned long arg)
1262 struct sci_port *s = (struct sci_port *)arg;
1263 struct dma_chan *chan = s->chan_rx;
1264 struct uart_port *port = &s->port;
1265 struct dma_tx_state state;
1266 enum dma_status status;
1267 unsigned long flags;
1272 spin_lock_irqsave(&port->lock, flags);
1274 dev_dbg(port->dev, "DMA Rx timed out\n");
1276 active = sci_dma_rx_find_active(s);
1278 spin_unlock_irqrestore(&port->lock, flags);
1282 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1283 if (status == DMA_COMPLETE) {
1284 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1285 s->active_rx, active);
1286 spin_unlock_irqrestore(&port->lock, flags);
1288 /* Let packet complete handler take care of the packet */
1292 dmaengine_pause(chan);
1295 * sometimes DMA transfer doesn't stop even if it is stopped and
1296 * data keeps on coming until transaction is complete so check
1297 * for DMA_COMPLETE again
1298 * Let packet complete handler take care of the packet
1300 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1301 if (status == DMA_COMPLETE) {
1302 spin_unlock_irqrestore(&port->lock, flags);
1303 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1307 /* Handle incomplete DMA receive */
1308 dmaengine_terminate_all(s->chan_rx);
1309 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1310 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1314 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1316 tty_flip_buffer_push(&port->state->port);
1319 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1322 /* Direct new serial port interrupts back to CPU */
1323 scr = serial_port_in(port, SCSCR);
1324 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1325 scr &= ~SCSCR_RDRQE;
1326 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1328 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1330 spin_unlock_irqrestore(&port->lock, flags);
1333 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1334 enum dma_transfer_direction dir,
1337 dma_cap_mask_t mask;
1338 struct dma_chan *chan;
1339 struct dma_slave_config cfg;
1343 dma_cap_set(DMA_SLAVE, mask);
1345 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1346 (void *)(unsigned long)id, port->dev,
1347 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1350 "dma_request_slave_channel_compat failed\n");
1354 memset(&cfg, 0, sizeof(cfg));
1355 cfg.direction = dir;
1356 if (dir == DMA_MEM_TO_DEV) {
1357 cfg.dst_addr = port->mapbase +
1358 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1359 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1361 cfg.src_addr = port->mapbase +
1362 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1363 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1366 ret = dmaengine_slave_config(chan, &cfg);
1368 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1369 dma_release_channel(chan);
1376 static void sci_request_dma(struct uart_port *port)
1378 struct sci_port *s = to_sci_port(port);
1379 struct dma_chan *chan;
1381 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1383 if (!port->dev->of_node &&
1384 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
1387 s->cookie_tx = -EINVAL;
1388 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
1389 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1392 /* UART circular tx buffer is an aligned page. */
1393 s->tx_dma_addr = dma_map_single(chan->device->dev,
1394 port->state->xmit.buf,
1397 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1398 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1399 dma_release_channel(chan);
1402 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1403 __func__, UART_XMIT_SIZE,
1404 port->state->xmit.buf, &s->tx_dma_addr);
1407 INIT_WORK(&s->work_tx, work_fn_tx);
1410 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
1411 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1419 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1420 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1424 "Failed to allocate Rx dma buffer, using PIO\n");
1425 dma_release_channel(chan);
1430 for (i = 0; i < 2; i++) {
1431 struct scatterlist *sg = &s->sg_rx[i];
1433 sg_init_table(sg, 1);
1435 sg_dma_address(sg) = dma;
1436 sg_dma_len(sg) = s->buf_len_rx;
1438 buf += s->buf_len_rx;
1439 dma += s->buf_len_rx;
1442 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1444 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1449 static void sci_free_dma(struct uart_port *port)
1451 struct sci_port *s = to_sci_port(port);
1454 sci_tx_dma_release(s, false);
1456 sci_rx_dma_release(s, false);
1459 static void sci_flush_buffer(struct uart_port *port)
1462 * In uart_flush_buffer(), the xmit circular buffer has just been
1463 * cleared, so we have to reset tx_dma_len accordingly.
1465 to_sci_port(port)->tx_dma_len = 0;
1467 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1468 static inline void sci_request_dma(struct uart_port *port)
1472 static inline void sci_free_dma(struct uart_port *port)
1476 #define sci_flush_buffer NULL
1477 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1479 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1481 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1482 struct uart_port *port = ptr;
1483 struct sci_port *s = to_sci_port(port);
1486 u16 scr = serial_port_in(port, SCSCR);
1487 u16 ssr = serial_port_in(port, SCxSR);
1489 /* Disable future Rx interrupts */
1490 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1491 disable_irq_nosync(irq);
1497 serial_port_out(port, SCSCR, scr);
1498 /* Clear current interrupt */
1499 serial_port_out(port, SCxSR,
1500 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1501 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1502 jiffies, s->rx_timeout);
1503 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1509 /* I think sci_receive_chars has to be called irrespective
1510 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1513 sci_receive_chars(ptr);
1518 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1520 struct uart_port *port = ptr;
1521 unsigned long flags;
1523 spin_lock_irqsave(&port->lock, flags);
1524 sci_transmit_chars(port);
1525 spin_unlock_irqrestore(&port->lock, flags);
1530 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1532 struct uart_port *port = ptr;
1533 struct sci_port *s = to_sci_port(port);
1536 if (port->type == PORT_SCI) {
1537 if (sci_handle_errors(port)) {
1538 /* discard character in rx buffer */
1539 serial_port_in(port, SCxSR);
1540 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1543 sci_handle_fifo_overrun(port);
1545 sci_receive_chars(ptr);
1548 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1550 /* Kick the transmission */
1552 sci_tx_interrupt(irq, ptr);
1557 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1559 struct uart_port *port = ptr;
1562 sci_handle_breaks(port);
1563 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1568 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1570 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1571 struct uart_port *port = ptr;
1572 struct sci_port *s = to_sci_port(port);
1573 irqreturn_t ret = IRQ_NONE;
1575 ssr_status = serial_port_in(port, SCxSR);
1576 scr_status = serial_port_in(port, SCSCR);
1577 if (s->overrun_reg == SCxSR)
1578 orer_status = ssr_status;
1580 if (sci_getreg(port, s->overrun_reg)->size)
1581 orer_status = serial_port_in(port, s->overrun_reg);
1584 err_enabled = scr_status & port_rx_irq_mask(port);
1587 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1589 ret = sci_tx_interrupt(irq, ptr);
1592 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1595 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1596 (scr_status & SCSCR_RIE))
1597 ret = sci_rx_interrupt(irq, ptr);
1599 /* Error Interrupt */
1600 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1601 ret = sci_er_interrupt(irq, ptr);
1603 /* Break Interrupt */
1604 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1605 ret = sci_br_interrupt(irq, ptr);
1607 /* Overrun Interrupt */
1608 if (orer_status & s->overrun_mask) {
1609 sci_handle_fifo_overrun(port);
1616 static const struct sci_irq_desc {
1618 irq_handler_t handler;
1619 } sci_irq_desc[] = {
1621 * Split out handlers, the default case.
1625 .handler = sci_er_interrupt,
1630 .handler = sci_rx_interrupt,
1635 .handler = sci_tx_interrupt,
1640 .handler = sci_br_interrupt,
1644 * Special muxed handler.
1648 .handler = sci_mpxed_interrupt,
1652 static int sci_request_irq(struct sci_port *port)
1654 struct uart_port *up = &port->port;
1657 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1658 const struct sci_irq_desc *desc;
1661 if (SCIx_IRQ_IS_MUXED(port)) {
1665 irq = port->irqs[i];
1668 * Certain port types won't support all of the
1669 * available interrupt sources.
1671 if (unlikely(irq < 0))
1675 desc = sci_irq_desc + i;
1676 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1677 dev_name(up->dev), desc->desc);
1678 if (!port->irqstr[j])
1681 ret = request_irq(irq, desc->handler, up->irqflags,
1682 port->irqstr[j], port);
1683 if (unlikely(ret)) {
1684 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1693 free_irq(port->irqs[i], port);
1697 kfree(port->irqstr[j]);
1702 static void sci_free_irq(struct sci_port *port)
1707 * Intentionally in reverse order so we iterate over the muxed
1710 for (i = 0; i < SCIx_NR_IRQS; i++) {
1711 int irq = port->irqs[i];
1714 * Certain port types won't support all of the available
1715 * interrupt sources.
1717 if (unlikely(irq < 0))
1720 free_irq(port->irqs[i], port);
1721 kfree(port->irqstr[i]);
1723 if (SCIx_IRQ_IS_MUXED(port)) {
1724 /* If there's only one IRQ, we're done. */
1730 static unsigned int sci_tx_empty(struct uart_port *port)
1732 unsigned short status = serial_port_in(port, SCxSR);
1733 unsigned short in_tx_fifo = sci_txfill(port);
1735 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1739 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1740 * CTS/RTS is supported in hardware by at least one port and controlled
1741 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1742 * handled via the ->init_pins() op, which is a bit of a one-way street,
1743 * lacking any ability to defer pin control -- this will later be
1744 * converted over to the GPIO framework).
1746 * Other modes (such as loopback) are supported generically on certain
1747 * port types, but not others. For these it's sufficient to test for the
1748 * existence of the support register and simply ignore the port type.
1750 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1752 if (mctrl & TIOCM_LOOP) {
1753 const struct plat_sci_reg *reg;
1756 * Standard loopback mode for SCFCR ports.
1758 reg = sci_getreg(port, SCFCR);
1760 serial_port_out(port, SCFCR,
1761 serial_port_in(port, SCFCR) |
1766 static unsigned int sci_get_mctrl(struct uart_port *port)
1769 * CTS/RTS is handled in hardware when supported, while nothing
1770 * else is wired up. Keep it simple and simply assert DSR/CAR.
1772 return TIOCM_DSR | TIOCM_CAR;
1775 static void sci_break_ctl(struct uart_port *port, int break_state)
1777 struct sci_port *s = to_sci_port(port);
1778 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1779 unsigned short scscr, scsptr;
1781 /* check wheter the port has SCSPTR */
1784 * Not supported by hardware. Most parts couple break and rx
1785 * interrupts together, with break detection always enabled.
1790 scsptr = serial_port_in(port, SCSPTR);
1791 scscr = serial_port_in(port, SCSCR);
1793 if (break_state == -1) {
1794 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1797 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1801 serial_port_out(port, SCSPTR, scsptr);
1802 serial_port_out(port, SCSCR, scscr);
1805 static int sci_startup(struct uart_port *port)
1807 struct sci_port *s = to_sci_port(port);
1808 unsigned long flags;
1811 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1813 sci_request_dma(port);
1815 ret = sci_request_irq(s);
1816 if (unlikely(ret < 0)) {
1821 spin_lock_irqsave(&port->lock, flags);
1824 spin_unlock_irqrestore(&port->lock, flags);
1829 static void sci_shutdown(struct uart_port *port)
1831 struct sci_port *s = to_sci_port(port);
1832 unsigned long flags;
1834 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1836 spin_lock_irqsave(&port->lock, flags);
1839 spin_unlock_irqrestore(&port->lock, flags);
1841 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1843 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1845 del_timer_sync(&s->rx_timer);
1853 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1856 if (s->sampling_rate)
1857 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1859 /* Warn, but use a safe default */
1862 return ((freq + 16 * bps) / (32 * bps) - 1);
1865 /* calculate frame length from SMR */
1866 static int sci_baud_calc_frame_len(unsigned int smr_val)
1870 if (smr_val & SCSMR_CHR)
1872 if (smr_val & SCSMR_PE)
1874 if (smr_val & SCSMR_STOP)
1881 /* calculate sample rate, BRR, and clock select for HSCIF */
1882 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1883 int *brr, unsigned int *srr,
1884 unsigned int *cks, int frame_len)
1886 int sr, c, br, err, recv_margin;
1887 int min_err = 1000; /* 100% */
1888 int recv_max_margin = 0;
1890 /* Find the combination of sample rate and clock select with the
1891 smallest deviation from the desired baud rate. */
1892 for (sr = 8; sr <= 32; sr++) {
1893 for (c = 0; c <= 3; c++) {
1894 /* integerized formulas from HSCIF documentation */
1895 br = DIV_ROUND_CLOSEST(freq, (sr *
1896 (1 << (2 * c + 1)) * bps)) - 1;
1897 br = clamp(br, 0, 255);
1898 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1899 (1 << (2 * c + 1)) / 1000)) -
1902 * M: Receive margin (%)
1903 * N: Ratio of bit rate to clock (N = sampling rate)
1904 * D: Clock duty (D = 0 to 1.0)
1905 * L: Frame length (L = 9 to 12)
1906 * F: Absolute value of clock frequency deviation
1908 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1909 * (|D - 0.5| / N * (1 + F))|
1910 * NOTE: Usually, treat D for 0.5, F is 0 by this
1913 recv_margin = abs((500 -
1914 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1915 if (abs(min_err) > abs(err)) {
1917 recv_max_margin = recv_margin;
1918 } else if ((min_err == err) &&
1919 (recv_margin > recv_max_margin))
1920 recv_max_margin = recv_margin;
1930 if (min_err == 1000) {
1939 static void sci_reset(struct uart_port *port)
1941 const struct plat_sci_reg *reg;
1942 unsigned int status;
1945 status = serial_port_in(port, SCxSR);
1946 } while (!(status & SCxSR_TEND(port)));
1948 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1950 reg = sci_getreg(port, SCFCR);
1952 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1955 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1956 struct ktermios *old)
1958 struct sci_port *s = to_sci_port(port);
1959 const struct plat_sci_reg *reg;
1960 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1962 unsigned int srr = 15;
1964 if ((termios->c_cflag & CSIZE) == CS7)
1965 smr_val |= SCSMR_CHR;
1966 if (termios->c_cflag & PARENB)
1967 smr_val |= SCSMR_PE;
1968 if (termios->c_cflag & PARODD)
1969 smr_val |= SCSMR_PE | SCSMR_ODD;
1970 if (termios->c_cflag & CSTOPB)
1971 smr_val |= SCSMR_STOP;
1974 * earlyprintk comes here early on with port->uartclk set to zero.
1975 * the clock framework is not up and running at this point so here
1976 * we assume that 115200 is the maximum baud rate. please note that
1977 * the baud rate is not programmed during earlyprintk - it is assumed
1978 * that the previous boot loader has enabled required clocks and
1979 * setup the baud rate generator hardware for us already.
1981 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1983 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1984 if (likely(baud && port->uartclk)) {
1985 if (s->cfg->type == PORT_HSCIF) {
1986 int frame_len = sci_baud_calc_frame_len(smr_val);
1987 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1990 t = sci_scbrr_calc(s, baud, port->uartclk);
1991 for (cks = 0; t >= 256 && cks <= 3; cks++)
2000 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
2002 uart_update_timeout(port, termios->c_cflag, baud);
2004 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
2005 __func__, smr_val, cks, t, s->cfg->scscr);
2008 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
2009 serial_port_out(port, SCBRR, t);
2010 reg = sci_getreg(port, HSSRR);
2012 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2013 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
2015 serial_port_out(port, SCSMR, smr_val);
2017 sci_init_pins(port, termios->c_cflag);
2019 reg = sci_getreg(port, SCFCR);
2021 unsigned short ctrl = serial_port_in(port, SCFCR);
2023 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2024 if (termios->c_cflag & CRTSCTS)
2031 * As we've done a sci_reset() above, ensure we don't
2032 * interfere with the FIFOs while toggling MCE. As the
2033 * reset values could still be set, simply mask them out.
2035 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2037 serial_port_out(port, SCFCR, ctrl);
2040 serial_port_out(port, SCSCR, s->cfg->scscr);
2042 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2044 * Calculate delay for 2 DMA buffers (4 FIFO).
2045 * See serial_core.c::uart_update_timeout().
2046 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2047 * function calculates 1 jiffie for the data plus 5 jiffies for the
2048 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2049 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2050 * value obtained by this formula is too small. Therefore, if the value
2051 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2056 /* byte size and parity */
2057 switch (termios->c_cflag & CSIZE) {
2072 if (termios->c_cflag & CSTOPB)
2074 if (termios->c_cflag & PARENB)
2076 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2078 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2079 s->rx_timeout * 1000 / HZ, port->timeout);
2080 if (s->rx_timeout < msecs_to_jiffies(20))
2081 s->rx_timeout = msecs_to_jiffies(20);
2085 if ((termios->c_cflag & CREAD) != 0)
2088 sci_port_disable(s);
2091 static void sci_pm(struct uart_port *port, unsigned int state,
2092 unsigned int oldstate)
2094 struct sci_port *sci_port = to_sci_port(port);
2097 case UART_PM_STATE_OFF:
2098 sci_port_disable(sci_port);
2101 sci_port_enable(sci_port);
2106 static const char *sci_type(struct uart_port *port)
2108 switch (port->type) {
2126 static int sci_remap_port(struct uart_port *port)
2128 struct sci_port *sport = to_sci_port(port);
2131 * Nothing to do if there's already an established membase.
2136 if (port->flags & UPF_IOREMAP) {
2137 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2138 if (unlikely(!port->membase)) {
2139 dev_err(port->dev, "can't remap port#%d\n", port->line);
2144 * For the simple (and majority of) cases where we don't
2145 * need to do any remapping, just cast the cookie
2148 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2154 static void sci_release_port(struct uart_port *port)
2156 struct sci_port *sport = to_sci_port(port);
2158 if (port->flags & UPF_IOREMAP) {
2159 iounmap(port->membase);
2160 port->membase = NULL;
2163 release_mem_region(port->mapbase, sport->reg_size);
2166 static int sci_request_port(struct uart_port *port)
2168 struct resource *res;
2169 struct sci_port *sport = to_sci_port(port);
2172 res = request_mem_region(port->mapbase, sport->reg_size,
2173 dev_name(port->dev));
2174 if (unlikely(res == NULL)) {
2175 dev_err(port->dev, "request_mem_region failed.");
2179 ret = sci_remap_port(port);
2180 if (unlikely(ret != 0)) {
2181 release_resource(res);
2188 static void sci_config_port(struct uart_port *port, int flags)
2190 if (flags & UART_CONFIG_TYPE) {
2191 struct sci_port *sport = to_sci_port(port);
2193 port->type = sport->cfg->type;
2194 sci_request_port(port);
2198 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2200 if (ser->baud_base < 2400)
2201 /* No paper tape reader for Mitch.. */
2207 static struct uart_ops sci_uart_ops = {
2208 .tx_empty = sci_tx_empty,
2209 .set_mctrl = sci_set_mctrl,
2210 .get_mctrl = sci_get_mctrl,
2211 .start_tx = sci_start_tx,
2212 .stop_tx = sci_stop_tx,
2213 .stop_rx = sci_stop_rx,
2214 .break_ctl = sci_break_ctl,
2215 .startup = sci_startup,
2216 .shutdown = sci_shutdown,
2217 .flush_buffer = sci_flush_buffer,
2218 .set_termios = sci_set_termios,
2221 .release_port = sci_release_port,
2222 .request_port = sci_request_port,
2223 .config_port = sci_config_port,
2224 .verify_port = sci_verify_port,
2225 #ifdef CONFIG_CONSOLE_POLL
2226 .poll_get_char = sci_poll_get_char,
2227 .poll_put_char = sci_poll_put_char,
2231 static int sci_init_single(struct platform_device *dev,
2232 struct sci_port *sci_port, unsigned int index,
2233 struct plat_sci_port *p, bool early)
2235 struct uart_port *port = &sci_port->port;
2236 const struct resource *res;
2242 port->ops = &sci_uart_ops;
2243 port->iotype = UPIO_MEM;
2246 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2250 port->mapbase = res->start;
2251 sci_port->reg_size = resource_size(res);
2253 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2254 sci_port->irqs[i] = platform_get_irq(dev, i);
2256 /* The SCI generates several interrupts. They can be muxed together or
2257 * connected to different interrupt lines. In the muxed case only one
2258 * interrupt resource is specified. In the non-muxed case three or four
2259 * interrupt resources are specified, as the BRI interrupt is optional.
2261 if (sci_port->irqs[0] < 0)
2264 if (sci_port->irqs[1] < 0) {
2265 sci_port->irqs[1] = sci_port->irqs[0];
2266 sci_port->irqs[2] = sci_port->irqs[0];
2267 sci_port->irqs[3] = sci_port->irqs[0];
2270 if (p->regtype == SCIx_PROBE_REGTYPE) {
2271 ret = sci_probe_regmap(p);
2278 port->fifosize = 256;
2279 sci_port->overrun_reg = SCxSR;
2280 sci_port->overrun_mask = SCIFA_ORER;
2281 sci_port->sampling_rate = 16;
2284 port->fifosize = 128;
2285 sci_port->overrun_reg = SCLSR;
2286 sci_port->overrun_mask = SCLSR_ORER;
2287 sci_port->sampling_rate = 0;
2290 port->fifosize = 64;
2291 sci_port->overrun_reg = SCxSR;
2292 sci_port->overrun_mask = SCIFA_ORER;
2293 sci_port->sampling_rate = 16;
2296 port->fifosize = 16;
2297 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2298 sci_port->overrun_reg = SCxSR;
2299 sci_port->overrun_mask = SCIFA_ORER;
2300 sci_port->sampling_rate = 16;
2302 sci_port->overrun_reg = SCLSR;
2303 sci_port->overrun_mask = SCLSR_ORER;
2304 sci_port->sampling_rate = 32;
2309 sci_port->overrun_reg = SCxSR;
2310 sci_port->overrun_mask = SCI_ORER;
2311 sci_port->sampling_rate = 32;
2315 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2316 * match the SoC datasheet, this should be investigated. Let platform
2317 * data override the sampling rate for now.
2319 if (p->sampling_rate)
2320 sci_port->sampling_rate = p->sampling_rate;
2323 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2324 if (IS_ERR(sci_port->iclk)) {
2325 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2326 if (IS_ERR(sci_port->iclk)) {
2327 dev_err(&dev->dev, "can't get iclk\n");
2328 return PTR_ERR(sci_port->iclk);
2333 * The function clock is optional, ignore it if we can't
2336 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2337 if (IS_ERR(sci_port->fclk))
2338 sci_port->fclk = NULL;
2340 port->dev = &dev->dev;
2342 pm_runtime_enable(&dev->dev);
2345 sci_port->break_timer.data = (unsigned long)sci_port;
2346 sci_port->break_timer.function = sci_break_timer;
2347 init_timer(&sci_port->break_timer);
2350 * Establish some sensible defaults for the error detection.
2352 if (p->type == PORT_SCI) {
2353 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2354 sci_port->error_clear = SCI_ERROR_CLEAR;
2356 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2357 sci_port->error_clear = SCIF_ERROR_CLEAR;
2361 * Make the error mask inclusive of overrun detection, if
2364 if (sci_port->overrun_reg == SCxSR) {
2365 sci_port->error_mask |= sci_port->overrun_mask;
2366 sci_port->error_clear &= ~sci_port->overrun_mask;
2369 port->type = p->type;
2370 port->flags = UPF_FIXED_PORT | p->flags;
2371 port->regshift = p->regshift;
2374 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2375 * for the multi-IRQ ports, which is where we are primarily
2376 * concerned with the shutdown path synchronization.
2378 * For the muxed case there's nothing more to do.
2380 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2383 port->serial_in = sci_serial_in;
2384 port->serial_out = sci_serial_out;
2386 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2387 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2388 p->dma_slave_tx, p->dma_slave_rx);
2393 static void sci_cleanup_single(struct sci_port *port)
2395 clk_put(port->iclk);
2396 clk_put(port->fclk);
2398 pm_runtime_disable(port->port.dev);
2401 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2402 static void serial_console_putchar(struct uart_port *port, int ch)
2404 sci_poll_put_char(port, ch);
2408 * Print a string to the serial port trying not to disturb
2409 * any possible real use of the port...
2411 static void serial_console_write(struct console *co, const char *s,
2414 struct sci_port *sci_port = &sci_ports[co->index];
2415 struct uart_port *port = &sci_port->port;
2416 unsigned short bits, ctrl;
2417 unsigned long flags;
2422 else if (oops_in_progress)
2423 locked = spin_trylock_irqsave(&port->lock, flags);
2425 spin_lock_irqsave(&port->lock, flags);
2427 /* first save the SCSCR then disable the interrupts */
2428 ctrl = serial_port_in(port, SCSCR);
2429 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2431 uart_console_write(port, s, count, serial_console_putchar);
2433 /* wait until fifo is empty and last bit has been transmitted */
2434 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2435 while ((serial_port_in(port, SCxSR) & bits) != bits)
2438 /* restore the SCSCR */
2439 serial_port_out(port, SCSCR, ctrl);
2442 spin_unlock_irqrestore(&port->lock, flags);
2445 static int serial_console_setup(struct console *co, char *options)
2447 struct sci_port *sci_port;
2448 struct uart_port *port;
2456 * Refuse to handle any bogus ports.
2458 if (co->index < 0 || co->index >= SCI_NPORTS)
2461 sci_port = &sci_ports[co->index];
2462 port = &sci_port->port;
2465 * Refuse to handle uninitialized ports.
2470 ret = sci_remap_port(port);
2471 if (unlikely(ret != 0))
2475 uart_parse_options(options, &baud, &parity, &bits, &flow);
2477 return uart_set_options(port, co, baud, parity, bits, flow);
2480 static struct console serial_console = {
2482 .device = uart_console_device,
2483 .write = serial_console_write,
2484 .setup = serial_console_setup,
2485 .flags = CON_PRINTBUFFER,
2487 .data = &sci_uart_driver,
2490 static struct console early_serial_console = {
2491 .name = "early_ttySC",
2492 .write = serial_console_write,
2493 .flags = CON_PRINTBUFFER,
2497 static char early_serial_buf[32];
2499 static int sci_probe_earlyprintk(struct platform_device *pdev)
2501 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2503 if (early_serial_console.data)
2506 early_serial_console.index = pdev->id;
2508 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2510 serial_console_setup(&early_serial_console, early_serial_buf);
2512 if (!strstr(early_serial_buf, "keep"))
2513 early_serial_console.flags |= CON_BOOT;
2515 register_console(&early_serial_console);
2519 #define SCI_CONSOLE (&serial_console)
2522 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2527 #define SCI_CONSOLE NULL
2529 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2531 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2533 static struct uart_driver sci_uart_driver = {
2534 .owner = THIS_MODULE,
2535 .driver_name = "sci",
2536 .dev_name = "ttySC",
2538 .minor = SCI_MINOR_START,
2540 .cons = SCI_CONSOLE,
2543 static int sci_remove(struct platform_device *dev)
2545 struct sci_port *port = platform_get_drvdata(dev);
2547 uart_remove_one_port(&sci_uart_driver, &port->port);
2549 sci_cleanup_single(port);
2554 struct sci_port_info {
2556 unsigned int regtype;
2559 static const struct of_device_id of_sci_match[] = {
2561 .compatible = "renesas,scif",
2562 .data = &(const struct sci_port_info) {
2564 .regtype = SCIx_SH4_SCIF_REGTYPE,
2567 .compatible = "renesas,scifa",
2568 .data = &(const struct sci_port_info) {
2570 .regtype = SCIx_SCIFA_REGTYPE,
2573 .compatible = "renesas,scifb",
2574 .data = &(const struct sci_port_info) {
2576 .regtype = SCIx_SCIFB_REGTYPE,
2579 .compatible = "renesas,hscif",
2580 .data = &(const struct sci_port_info) {
2582 .regtype = SCIx_HSCIF_REGTYPE,
2585 .compatible = "renesas,sci",
2586 .data = &(const struct sci_port_info) {
2588 .regtype = SCIx_SCI_REGTYPE,
2594 MODULE_DEVICE_TABLE(of, of_sci_match);
2596 static struct plat_sci_port *
2597 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2599 struct device_node *np = pdev->dev.of_node;
2600 const struct of_device_id *match;
2601 const struct sci_port_info *info;
2602 struct plat_sci_port *p;
2605 if (!IS_ENABLED(CONFIG_OF) || !np)
2608 match = of_match_node(of_sci_match, pdev->dev.of_node);
2614 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2618 /* Get the line number for the aliases node. */
2619 id = of_alias_get_id(np, "serial");
2621 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2627 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2628 p->type = info->type;
2629 p->regtype = info->regtype;
2630 p->scscr = SCSCR_RE | SCSCR_TE;
2635 static int sci_probe_single(struct platform_device *dev,
2637 struct plat_sci_port *p,
2638 struct sci_port *sciport)
2643 if (unlikely(index >= SCI_NPORTS)) {
2644 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2645 index+1, SCI_NPORTS);
2646 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2650 ret = sci_init_single(dev, sciport, index, p, false);
2654 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2656 sci_cleanup_single(sciport);
2663 static int sci_probe(struct platform_device *dev)
2665 struct plat_sci_port *p;
2666 struct sci_port *sp;
2667 unsigned int dev_id;
2671 * If we've come here via earlyprintk initialization, head off to
2672 * the special early probe. We don't have sufficient device state
2673 * to make it beyond this yet.
2675 if (is_early_platform_device(dev))
2676 return sci_probe_earlyprintk(dev);
2678 if (dev->dev.of_node) {
2679 p = sci_parse_dt(dev, &dev_id);
2683 p = dev->dev.platform_data;
2685 dev_err(&dev->dev, "no platform data supplied\n");
2692 sp = &sci_ports[dev_id];
2693 platform_set_drvdata(dev, sp);
2695 ret = sci_probe_single(dev, dev_id, p, sp);
2699 #ifdef CONFIG_SH_STANDARD_BIOS
2700 sh_bios_gdb_detach();
2706 static __maybe_unused int sci_suspend(struct device *dev)
2708 struct sci_port *sport = dev_get_drvdata(dev);
2711 uart_suspend_port(&sci_uart_driver, &sport->port);
2716 static __maybe_unused int sci_resume(struct device *dev)
2718 struct sci_port *sport = dev_get_drvdata(dev);
2721 uart_resume_port(&sci_uart_driver, &sport->port);
2726 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2728 static struct platform_driver sci_driver = {
2730 .remove = sci_remove,
2733 .pm = &sci_dev_pm_ops,
2734 .of_match_table = of_match_ptr(of_sci_match),
2738 static int __init sci_init(void)
2742 pr_info("%s\n", banner);
2744 ret = uart_register_driver(&sci_uart_driver);
2745 if (likely(ret == 0)) {
2746 ret = platform_driver_register(&sci_driver);
2748 uart_unregister_driver(&sci_uart_driver);
2754 static void __exit sci_exit(void)
2756 platform_driver_unregister(&sci_driver);
2757 uart_unregister_driver(&sci_uart_driver);
2760 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2761 early_platform_init_buffer("earlyprintk", &sci_driver,
2762 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2764 module_init(sci_init);
2765 module_exit(sci_exit);
2767 MODULE_LICENSE("GPL");
2768 MODULE_ALIAS("platform:sh-sci");
2769 MODULE_AUTHOR("Paul Mundt");
2770 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");