1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/minmax.h>
35 #include <linux/module.h>
38 #include <linux/of_device.h>
39 #include <linux/platform_device.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/scatterlist.h>
42 #include <linux/serial.h>
43 #include <linux/serial_sci.h>
44 #include <linux/sh_dma.h>
45 #include <linux/slab.h>
46 #include <linux/string.h>
47 #include <linux/sysrq.h>
48 #include <linux/timer.h>
49 #include <linux/tty.h>
50 #include <linux/tty_flip.h>
53 #include <asm/sh_bios.h>
54 #include <asm/platform_early.h>
57 #include "serial_mctrl_gpio.h"
60 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
87 /* Bit x set means sampling rate x + 1 is supported */
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
95 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
96 #define max_sr(_port) fls((_port)->sampling_rate_mask)
98 /* Iterate over all supported sampling rates, from high to low */
99 #define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103 struct plat_sci_reg {
107 struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
118 struct uart_port port;
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
137 #ifdef CONFIG_SERIAL_SH_SCI_DMA
138 struct dma_chan *chan_tx_saved;
139 struct dma_chan *chan_rx_saved;
140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
145 struct scatterlist sg_rx[2];
148 struct work_struct work_tx;
149 struct hrtimer rx_timer;
150 unsigned int rx_timeout; /* microseconds */
152 unsigned int rx_frame;
154 struct timer_list rx_fifo_timer;
162 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
164 static struct sci_port sci_ports[SCI_NPORTS];
165 static unsigned long sci_ports_in_use;
166 static struct uart_driver sci_uart_driver;
168 static inline struct sci_port *
169 to_sci_port(struct uart_port *uart)
171 return container_of(uart, struct sci_port, port);
174 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
176 * Common SCI definitions, dependent on the port's regshift
179 [SCIx_SCI_REGTYPE] = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
189 .overrun_reg = SCxSR,
190 .overrun_mask = SCI_ORER,
191 .sampling_rate_mask = SCI_SR(32),
192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
197 * Common definitions for legacy IrDA ports.
199 [SCIx_IRDA_REGTYPE] = {
201 [SCSMR] = { 0x00, 8 },
202 [SCBRR] = { 0x02, 8 },
203 [SCSCR] = { 0x04, 8 },
204 [SCxTDR] = { 0x06, 8 },
205 [SCxSR] = { 0x08, 16 },
206 [SCxRDR] = { 0x0a, 8 },
207 [SCFCR] = { 0x0c, 8 },
208 [SCFDR] = { 0x0e, 16 },
211 .overrun_reg = SCxSR,
212 .overrun_mask = SCI_ORER,
213 .sampling_rate_mask = SCI_SR(32),
214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
219 * Common SCIFA definitions.
221 [SCIx_SCIFA_REGTYPE] = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x20, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x24, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = { 0x1c, 16 },
231 [SCPCR] = { 0x30, 16 },
232 [SCPDR] = { 0x34, 16 },
235 .overrun_reg = SCxSR,
236 .overrun_mask = SCIFA_ORER,
237 .sampling_rate_mask = SCI_SR_SCIFAB,
238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
243 * Common SCIFB definitions.
245 [SCIx_SCIFB_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x40, 8 },
251 [SCxSR] = { 0x14, 16 },
252 [SCxRDR] = { 0x60, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCTFDR] = { 0x38, 16 },
255 [SCRFDR] = { 0x3c, 16 },
256 [SCPCR] = { 0x30, 16 },
257 [SCPDR] = { 0x34, 16 },
260 .overrun_reg = SCxSR,
261 .overrun_mask = SCIFA_ORER,
262 .sampling_rate_mask = SCI_SR_SCIFAB,
263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
268 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCSPTR] = { 0x20, 16 },
282 [SCLSR] = { 0x24, 16 },
285 .overrun_reg = SCLSR,
286 .overrun_mask = SCLSR_ORER,
287 .sampling_rate_mask = SCI_SR(32),
288 .error_mask = SCIF_DEFAULT_ERROR_MASK,
289 .error_clear = SCIF_ERROR_CLEAR,
293 * The "SCIFA" that is in RZ/T and RZ/A2.
294 * It looks like a normal SCIF with FIFO data, but with a
295 * compressed address space. Also, the break out of interrupts
296 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
298 [SCIx_RZ_SCIFA_REGTYPE] = {
300 [SCSMR] = { 0x00, 16 },
301 [SCBRR] = { 0x02, 8 },
302 [SCSCR] = { 0x04, 16 },
303 [SCxTDR] = { 0x06, 8 },
304 [SCxSR] = { 0x08, 16 },
305 [SCxRDR] = { 0x0A, 8 },
306 [SCFCR] = { 0x0C, 16 },
307 [SCFDR] = { 0x0E, 16 },
308 [SCSPTR] = { 0x10, 16 },
309 [SCLSR] = { 0x12, 16 },
312 .overrun_reg = SCLSR,
313 .overrun_mask = SCLSR_ORER,
314 .sampling_rate_mask = SCI_SR(32),
315 .error_mask = SCIF_DEFAULT_ERROR_MASK,
316 .error_clear = SCIF_ERROR_CLEAR,
320 * Common SH-3 SCIF definitions.
322 [SCIx_SH3_SCIF_REGTYPE] = {
324 [SCSMR] = { 0x00, 8 },
325 [SCBRR] = { 0x02, 8 },
326 [SCSCR] = { 0x04, 8 },
327 [SCxTDR] = { 0x06, 8 },
328 [SCxSR] = { 0x08, 16 },
329 [SCxRDR] = { 0x0a, 8 },
330 [SCFCR] = { 0x0c, 8 },
331 [SCFDR] = { 0x0e, 16 },
334 .overrun_reg = SCLSR,
335 .overrun_mask = SCLSR_ORER,
336 .sampling_rate_mask = SCI_SR(32),
337 .error_mask = SCIF_DEFAULT_ERROR_MASK,
338 .error_clear = SCIF_ERROR_CLEAR,
342 * Common SH-4(A) SCIF(B) definitions.
344 [SCIx_SH4_SCIF_REGTYPE] = {
346 [SCSMR] = { 0x00, 16 },
347 [SCBRR] = { 0x04, 8 },
348 [SCSCR] = { 0x08, 16 },
349 [SCxTDR] = { 0x0c, 8 },
350 [SCxSR] = { 0x10, 16 },
351 [SCxRDR] = { 0x14, 8 },
352 [SCFCR] = { 0x18, 16 },
353 [SCFDR] = { 0x1c, 16 },
354 [SCSPTR] = { 0x20, 16 },
355 [SCLSR] = { 0x24, 16 },
358 .overrun_reg = SCLSR,
359 .overrun_mask = SCLSR_ORER,
360 .sampling_rate_mask = SCI_SR(32),
361 .error_mask = SCIF_DEFAULT_ERROR_MASK,
362 .error_clear = SCIF_ERROR_CLEAR,
366 * Common SCIF definitions for ports with a Baud Rate Generator for
367 * External Clock (BRG).
369 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
371 [SCSMR] = { 0x00, 16 },
372 [SCBRR] = { 0x04, 8 },
373 [SCSCR] = { 0x08, 16 },
374 [SCxTDR] = { 0x0c, 8 },
375 [SCxSR] = { 0x10, 16 },
376 [SCxRDR] = { 0x14, 8 },
377 [SCFCR] = { 0x18, 16 },
378 [SCFDR] = { 0x1c, 16 },
379 [SCSPTR] = { 0x20, 16 },
380 [SCLSR] = { 0x24, 16 },
381 [SCDL] = { 0x30, 16 },
382 [SCCKS] = { 0x34, 16 },
385 .overrun_reg = SCLSR,
386 .overrun_mask = SCLSR_ORER,
387 .sampling_rate_mask = SCI_SR(32),
388 .error_mask = SCIF_DEFAULT_ERROR_MASK,
389 .error_clear = SCIF_ERROR_CLEAR,
393 * Common HSCIF definitions.
395 [SCIx_HSCIF_REGTYPE] = {
397 [SCSMR] = { 0x00, 16 },
398 [SCBRR] = { 0x04, 8 },
399 [SCSCR] = { 0x08, 16 },
400 [SCxTDR] = { 0x0c, 8 },
401 [SCxSR] = { 0x10, 16 },
402 [SCxRDR] = { 0x14, 8 },
403 [SCFCR] = { 0x18, 16 },
404 [SCFDR] = { 0x1c, 16 },
405 [SCSPTR] = { 0x20, 16 },
406 [SCLSR] = { 0x24, 16 },
407 [HSSRR] = { 0x40, 16 },
408 [SCDL] = { 0x30, 16 },
409 [SCCKS] = { 0x34, 16 },
410 [HSRTRGR] = { 0x54, 16 },
411 [HSTTRGR] = { 0x58, 16 },
414 .overrun_reg = SCLSR,
415 .overrun_mask = SCLSR_ORER,
416 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
417 .error_mask = SCIF_DEFAULT_ERROR_MASK,
418 .error_clear = SCIF_ERROR_CLEAR,
422 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
425 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
427 [SCSMR] = { 0x00, 16 },
428 [SCBRR] = { 0x04, 8 },
429 [SCSCR] = { 0x08, 16 },
430 [SCxTDR] = { 0x0c, 8 },
431 [SCxSR] = { 0x10, 16 },
432 [SCxRDR] = { 0x14, 8 },
433 [SCFCR] = { 0x18, 16 },
434 [SCFDR] = { 0x1c, 16 },
435 [SCLSR] = { 0x24, 16 },
438 .overrun_reg = SCLSR,
439 .overrun_mask = SCLSR_ORER,
440 .sampling_rate_mask = SCI_SR(32),
441 .error_mask = SCIF_DEFAULT_ERROR_MASK,
442 .error_clear = SCIF_ERROR_CLEAR,
446 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
449 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
451 [SCSMR] = { 0x00, 16 },
452 [SCBRR] = { 0x04, 8 },
453 [SCSCR] = { 0x08, 16 },
454 [SCxTDR] = { 0x0c, 8 },
455 [SCxSR] = { 0x10, 16 },
456 [SCxRDR] = { 0x14, 8 },
457 [SCFCR] = { 0x18, 16 },
458 [SCFDR] = { 0x1c, 16 },
459 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
460 [SCRFDR] = { 0x20, 16 },
461 [SCSPTR] = { 0x24, 16 },
462 [SCLSR] = { 0x28, 16 },
465 .overrun_reg = SCLSR,
466 .overrun_mask = SCLSR_ORER,
467 .sampling_rate_mask = SCI_SR(32),
468 .error_mask = SCIF_DEFAULT_ERROR_MASK,
469 .error_clear = SCIF_ERROR_CLEAR,
473 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
476 [SCIx_SH7705_SCIF_REGTYPE] = {
478 [SCSMR] = { 0x00, 16 },
479 [SCBRR] = { 0x04, 8 },
480 [SCSCR] = { 0x08, 16 },
481 [SCxTDR] = { 0x20, 8 },
482 [SCxSR] = { 0x14, 16 },
483 [SCxRDR] = { 0x24, 8 },
484 [SCFCR] = { 0x18, 16 },
485 [SCFDR] = { 0x1c, 16 },
488 .overrun_reg = SCxSR,
489 .overrun_mask = SCIFA_ORER,
490 .sampling_rate_mask = SCI_SR(16),
491 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
492 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
496 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
499 * The "offset" here is rather misleading, in that it refers to an enum
500 * value relative to the port mapping rather than the fixed offset
501 * itself, which needs to be manually retrieved from the platform's
502 * register map for the given port.
504 static unsigned int sci_serial_in(struct uart_port *p, int offset)
506 const struct plat_sci_reg *reg = sci_getreg(p, offset);
509 return ioread8(p->membase + (reg->offset << p->regshift));
510 else if (reg->size == 16)
511 return ioread16(p->membase + (reg->offset << p->regshift));
513 WARN(1, "Invalid register access\n");
518 static void sci_serial_out(struct uart_port *p, int offset, int value)
520 const struct plat_sci_reg *reg = sci_getreg(p, offset);
523 iowrite8(value, p->membase + (reg->offset << p->regshift));
524 else if (reg->size == 16)
525 iowrite16(value, p->membase + (reg->offset << p->regshift));
527 WARN(1, "Invalid register access\n");
530 static void sci_port_enable(struct sci_port *sci_port)
534 if (!sci_port->port.dev)
537 pm_runtime_get_sync(sci_port->port.dev);
539 for (i = 0; i < SCI_NUM_CLKS; i++) {
540 clk_prepare_enable(sci_port->clks[i]);
541 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
543 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
546 static void sci_port_disable(struct sci_port *sci_port)
550 if (!sci_port->port.dev)
553 for (i = SCI_NUM_CLKS; i-- > 0; )
554 clk_disable_unprepare(sci_port->clks[i]);
556 pm_runtime_put_sync(sci_port->port.dev);
559 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562 * Not all ports (such as SCIFA) will support REIE. Rather than
563 * special-casing the port type, we check the port initialization
564 * IRQ enable mask to see whether the IRQ is desired at all. If
565 * it's unset, it's logically inferred that there's no point in
568 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571 static void sci_start_tx(struct uart_port *port)
573 struct sci_port *s = to_sci_port(port);
576 #ifdef CONFIG_SERIAL_SH_SCI_DMA
577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
578 u16 new, scr = serial_port_in(port, SCSCR);
580 new = scr | SCSCR_TDRQE;
582 new = scr & ~SCSCR_TDRQE;
584 serial_port_out(port, SCSCR, new);
587 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
588 dma_submit_error(s->cookie_tx)) {
590 schedule_work(&s->work_tx);
594 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
595 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
596 ctrl = serial_port_in(port, SCSCR);
597 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
601 static void sci_stop_tx(struct uart_port *port)
605 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
606 ctrl = serial_port_in(port, SCSCR);
608 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
609 ctrl &= ~SCSCR_TDRQE;
613 serial_port_out(port, SCSCR, ctrl);
615 #ifdef CONFIG_SERIAL_SH_SCI_DMA
616 if (to_sci_port(port)->chan_tx &&
617 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
618 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
619 to_sci_port(port)->cookie_tx = -EINVAL;
624 static void sci_start_rx(struct uart_port *port)
628 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
630 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
631 ctrl &= ~SCSCR_RDRQE;
633 serial_port_out(port, SCSCR, ctrl);
636 static void sci_stop_rx(struct uart_port *port)
640 ctrl = serial_port_in(port, SCSCR);
642 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
643 ctrl &= ~SCSCR_RDRQE;
645 ctrl &= ~port_rx_irq_mask(port);
647 serial_port_out(port, SCSCR, ctrl);
650 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
652 if (port->type == PORT_SCI) {
653 /* Just store the mask */
654 serial_port_out(port, SCxSR, mask);
655 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
656 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
657 /* Only clear the status bits we want to clear */
658 serial_port_out(port, SCxSR,
659 serial_port_in(port, SCxSR) & mask);
661 /* Store the mask, clear parity/framing errors */
662 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
666 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
667 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
669 #ifdef CONFIG_CONSOLE_POLL
670 static int sci_poll_get_char(struct uart_port *port)
672 unsigned short status;
676 status = serial_port_in(port, SCxSR);
677 if (status & SCxSR_ERRORS(port)) {
678 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
684 if (!(status & SCxSR_RDxF(port)))
687 c = serial_port_in(port, SCxRDR);
690 serial_port_in(port, SCxSR);
691 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
697 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
699 unsigned short status;
702 status = serial_port_in(port, SCxSR);
703 } while (!(status & SCxSR_TDxE(port)));
705 serial_port_out(port, SCxTDR, c);
706 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
708 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
709 CONFIG_SERIAL_SH_SCI_EARLYCON */
711 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
713 struct sci_port *s = to_sci_port(port);
716 * Use port-specific handler if provided.
718 if (s->cfg->ops && s->cfg->ops->init_pins) {
719 s->cfg->ops->init_pins(port, cflag);
723 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
724 u16 data = serial_port_in(port, SCPDR);
725 u16 ctrl = serial_port_in(port, SCPCR);
727 /* Enable RXD and TXD pin functions */
728 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
729 if (to_sci_port(port)->has_rtscts) {
730 /* RTS# is output, active low, unless autorts */
731 if (!(port->mctrl & TIOCM_RTS)) {
734 } else if (!s->autorts) {
738 /* Enable RTS# pin function */
741 /* Enable CTS# pin function */
744 serial_port_out(port, SCPDR, data);
745 serial_port_out(port, SCPCR, ctrl);
746 } else if (sci_getreg(port, SCSPTR)->size) {
747 u16 status = serial_port_in(port, SCSPTR);
749 /* RTS# is always output; and active low, unless autorts */
750 status |= SCSPTR_RTSIO;
751 if (!(port->mctrl & TIOCM_RTS))
752 status |= SCSPTR_RTSDT;
753 else if (!s->autorts)
754 status &= ~SCSPTR_RTSDT;
755 /* CTS# and SCK are inputs */
756 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
757 serial_port_out(port, SCSPTR, status);
761 static int sci_txfill(struct uart_port *port)
763 struct sci_port *s = to_sci_port(port);
764 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
765 const struct plat_sci_reg *reg;
767 reg = sci_getreg(port, SCTFDR);
769 return serial_port_in(port, SCTFDR) & fifo_mask;
771 reg = sci_getreg(port, SCFDR);
773 return serial_port_in(port, SCFDR) >> 8;
775 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
778 static int sci_txroom(struct uart_port *port)
780 return port->fifosize - sci_txfill(port);
783 static int sci_rxfill(struct uart_port *port)
785 struct sci_port *s = to_sci_port(port);
786 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
787 const struct plat_sci_reg *reg;
789 reg = sci_getreg(port, SCRFDR);
791 return serial_port_in(port, SCRFDR) & fifo_mask;
793 reg = sci_getreg(port, SCFDR);
795 return serial_port_in(port, SCFDR) & fifo_mask;
797 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
800 /* ********************************************************************** *
801 * the interrupt related routines *
802 * ********************************************************************** */
804 static void sci_transmit_chars(struct uart_port *port)
806 struct circ_buf *xmit = &port->state->xmit;
807 unsigned int stopped = uart_tx_stopped(port);
808 unsigned short status;
812 status = serial_port_in(port, SCxSR);
813 if (!(status & SCxSR_TDxE(port))) {
814 ctrl = serial_port_in(port, SCSCR);
815 if (uart_circ_empty(xmit))
819 serial_port_out(port, SCSCR, ctrl);
823 count = sci_txroom(port);
831 } else if (!uart_circ_empty(xmit) && !stopped) {
832 c = xmit->buf[xmit->tail];
833 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
838 serial_port_out(port, SCxTDR, c);
841 } while (--count > 0);
843 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
845 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
846 uart_write_wakeup(port);
847 if (uart_circ_empty(xmit))
852 /* On SH3, SCIF may read end-of-break as a space->mark char */
853 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
855 static void sci_receive_chars(struct uart_port *port)
857 struct tty_port *tport = &port->state->port;
858 int i, count, copied = 0;
859 unsigned short status;
862 status = serial_port_in(port, SCxSR);
863 if (!(status & SCxSR_RDxF(port)))
867 /* Don't copy more bytes than there is room for in the buffer */
868 count = tty_buffer_request_room(tport, sci_rxfill(port));
870 /* If for any reason we can't copy more data, we're done! */
874 if (port->type == PORT_SCI) {
875 char c = serial_port_in(port, SCxRDR);
876 if (uart_handle_sysrq_char(port, c))
879 tty_insert_flip_char(tport, c, TTY_NORMAL);
881 for (i = 0; i < count; i++) {
884 if (port->type == PORT_SCIF ||
885 port->type == PORT_HSCIF) {
886 status = serial_port_in(port, SCxSR);
887 c = serial_port_in(port, SCxRDR);
889 c = serial_port_in(port, SCxRDR);
890 status = serial_port_in(port, SCxSR);
892 if (uart_handle_sysrq_char(port, c)) {
897 /* Store data and status */
898 if (status & SCxSR_FER(port)) {
900 port->icount.frame++;
901 dev_notice(port->dev, "frame error\n");
902 } else if (status & SCxSR_PER(port)) {
904 port->icount.parity++;
905 dev_notice(port->dev, "parity error\n");
909 tty_insert_flip_char(tport, c, flag);
913 serial_port_in(port, SCxSR); /* dummy read */
914 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
917 port->icount.rx += count;
921 /* Tell the rest of the system the news. New characters! */
922 tty_flip_buffer_push(tport);
924 /* TTY buffers full; read from RX reg to prevent lockup */
925 serial_port_in(port, SCxRDR);
926 serial_port_in(port, SCxSR); /* dummy read */
927 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
931 static int sci_handle_errors(struct uart_port *port)
934 unsigned short status = serial_port_in(port, SCxSR);
935 struct tty_port *tport = &port->state->port;
936 struct sci_port *s = to_sci_port(port);
938 /* Handle overruns */
939 if (status & s->params->overrun_mask) {
940 port->icount.overrun++;
943 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
946 dev_notice(port->dev, "overrun error\n");
949 if (status & SCxSR_FER(port)) {
951 port->icount.frame++;
953 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
956 dev_notice(port->dev, "frame error\n");
959 if (status & SCxSR_PER(port)) {
961 port->icount.parity++;
963 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
966 dev_notice(port->dev, "parity error\n");
970 tty_flip_buffer_push(tport);
975 static int sci_handle_fifo_overrun(struct uart_port *port)
977 struct tty_port *tport = &port->state->port;
978 struct sci_port *s = to_sci_port(port);
979 const struct plat_sci_reg *reg;
983 reg = sci_getreg(port, s->params->overrun_reg);
987 status = serial_port_in(port, s->params->overrun_reg);
988 if (status & s->params->overrun_mask) {
989 status &= ~s->params->overrun_mask;
990 serial_port_out(port, s->params->overrun_reg, status);
992 port->icount.overrun++;
994 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
995 tty_flip_buffer_push(tport);
997 dev_dbg(port->dev, "overrun error\n");
1004 static int sci_handle_breaks(struct uart_port *port)
1007 unsigned short status = serial_port_in(port, SCxSR);
1008 struct tty_port *tport = &port->state->port;
1010 if (uart_handle_break(port))
1013 if (status & SCxSR_BRK(port)) {
1016 /* Notify of BREAK */
1017 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1020 dev_dbg(port->dev, "BREAK detected\n");
1024 tty_flip_buffer_push(tport);
1026 copied += sci_handle_fifo_overrun(port);
1031 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1035 if (rx_trig >= port->fifosize)
1036 rx_trig = port->fifosize - 1;
1040 /* HSCIF can be set to an arbitrary level. */
1041 if (sci_getreg(port, HSRTRGR)->size) {
1042 serial_port_out(port, HSRTRGR, rx_trig);
1046 switch (port->type) {
1051 } else if (rx_trig < 8) {
1054 } else if (rx_trig < 14) {
1058 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1067 } else if (rx_trig < 32) {
1070 } else if (rx_trig < 48) {
1074 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1079 WARN(1, "unknown FIFO configuration");
1083 serial_port_out(port, SCFCR,
1084 (serial_port_in(port, SCFCR) &
1085 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1090 static int scif_rtrg_enabled(struct uart_port *port)
1092 if (sci_getreg(port, HSRTRGR)->size)
1093 return serial_port_in(port, HSRTRGR) != 0;
1095 return (serial_port_in(port, SCFCR) &
1096 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1099 static void rx_fifo_timer_fn(struct timer_list *t)
1101 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1102 struct uart_port *port = &s->port;
1104 dev_dbg(port->dev, "Rx timed out\n");
1105 scif_set_rtrg(port, 1);
1108 static ssize_t rx_fifo_trigger_show(struct device *dev,
1109 struct device_attribute *attr, char *buf)
1111 struct uart_port *port = dev_get_drvdata(dev);
1112 struct sci_port *sci = to_sci_port(port);
1114 return sprintf(buf, "%d\n", sci->rx_trigger);
1117 static ssize_t rx_fifo_trigger_store(struct device *dev,
1118 struct device_attribute *attr,
1119 const char *buf, size_t count)
1121 struct uart_port *port = dev_get_drvdata(dev);
1122 struct sci_port *sci = to_sci_port(port);
1126 ret = kstrtol(buf, 0, &r);
1130 sci->rx_trigger = scif_set_rtrg(port, r);
1131 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1132 scif_set_rtrg(port, 1);
1137 static DEVICE_ATTR_RW(rx_fifo_trigger);
1139 static ssize_t rx_fifo_timeout_show(struct device *dev,
1140 struct device_attribute *attr,
1143 struct uart_port *port = dev_get_drvdata(dev);
1144 struct sci_port *sci = to_sci_port(port);
1147 if (port->type == PORT_HSCIF)
1148 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1150 v = sci->rx_fifo_timeout;
1152 return sprintf(buf, "%d\n", v);
1155 static ssize_t rx_fifo_timeout_store(struct device *dev,
1156 struct device_attribute *attr,
1160 struct uart_port *port = dev_get_drvdata(dev);
1161 struct sci_port *sci = to_sci_port(port);
1165 ret = kstrtol(buf, 0, &r);
1169 if (port->type == PORT_HSCIF) {
1172 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1174 sci->rx_fifo_timeout = r;
1175 scif_set_rtrg(port, 1);
1177 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1183 static DEVICE_ATTR_RW(rx_fifo_timeout);
1186 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1187 static void sci_dma_tx_complete(void *arg)
1189 struct sci_port *s = arg;
1190 struct uart_port *port = &s->port;
1191 struct circ_buf *xmit = &port->state->xmit;
1192 unsigned long flags;
1194 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1196 spin_lock_irqsave(&port->lock, flags);
1198 xmit->tail += s->tx_dma_len;
1199 xmit->tail &= UART_XMIT_SIZE - 1;
1201 port->icount.tx += s->tx_dma_len;
1203 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1204 uart_write_wakeup(port);
1206 if (!uart_circ_empty(xmit)) {
1208 schedule_work(&s->work_tx);
1210 s->cookie_tx = -EINVAL;
1211 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1212 u16 ctrl = serial_port_in(port, SCSCR);
1213 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1217 spin_unlock_irqrestore(&port->lock, flags);
1220 /* Locking: called with port lock held */
1221 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1223 struct uart_port *port = &s->port;
1224 struct tty_port *tport = &port->state->port;
1227 copied = tty_insert_flip_string(tport, buf, count);
1229 port->icount.buf_overrun++;
1231 port->icount.rx += copied;
1236 static int sci_dma_rx_find_active(struct sci_port *s)
1240 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1241 if (s->active_rx == s->cookie_rx[i])
1247 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1252 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1253 s->cookie_rx[i] = -EINVAL;
1257 static void sci_dma_rx_release(struct sci_port *s)
1259 struct dma_chan *chan = s->chan_rx_saved;
1260 struct uart_port *port = &s->port;
1261 unsigned long flags;
1263 uart_port_lock_irqsave(port, &flags);
1264 s->chan_rx_saved = NULL;
1265 sci_dma_rx_chan_invalidate(s);
1266 uart_port_unlock_irqrestore(port, flags);
1268 dmaengine_terminate_sync(chan);
1269 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1270 sg_dma_address(&s->sg_rx[0]));
1271 dma_release_channel(chan);
1274 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1276 long sec = usec / 1000000;
1277 long nsec = (usec % 1000000) * 1000;
1278 ktime_t t = ktime_set(sec, nsec);
1280 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1283 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1285 struct uart_port *port = &s->port;
1288 /* Direct new serial port interrupts back to CPU */
1289 scr = serial_port_in(port, SCSCR);
1290 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1291 scr &= ~SCSCR_RDRQE;
1292 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1294 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1297 static void sci_dma_rx_complete(void *arg)
1299 struct sci_port *s = arg;
1300 struct dma_chan *chan = s->chan_rx;
1301 struct uart_port *port = &s->port;
1302 struct dma_async_tx_descriptor *desc;
1303 unsigned long flags;
1304 int active, count = 0;
1306 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1309 spin_lock_irqsave(&port->lock, flags);
1311 active = sci_dma_rx_find_active(s);
1313 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1315 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1318 tty_flip_buffer_push(&port->state->port);
1320 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1322 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1326 desc->callback = sci_dma_rx_complete;
1327 desc->callback_param = s;
1328 s->cookie_rx[active] = dmaengine_submit(desc);
1329 if (dma_submit_error(s->cookie_rx[active]))
1332 s->active_rx = s->cookie_rx[!active];
1334 dma_async_issue_pending(chan);
1336 spin_unlock_irqrestore(&port->lock, flags);
1337 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1338 __func__, s->cookie_rx[active], active, s->active_rx);
1342 spin_unlock_irqrestore(&port->lock, flags);
1343 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1345 spin_lock_irqsave(&port->lock, flags);
1346 dmaengine_terminate_async(chan);
1347 sci_dma_rx_chan_invalidate(s);
1348 sci_dma_rx_reenable_irq(s);
1349 spin_unlock_irqrestore(&port->lock, flags);
1352 static void sci_dma_tx_release(struct sci_port *s)
1354 struct dma_chan *chan = s->chan_tx_saved;
1356 cancel_work_sync(&s->work_tx);
1357 s->chan_tx_saved = s->chan_tx = NULL;
1358 s->cookie_tx = -EINVAL;
1359 dmaengine_terminate_sync(chan);
1360 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1362 dma_release_channel(chan);
1365 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1367 struct dma_chan *chan = s->chan_rx;
1368 struct uart_port *port = &s->port;
1369 unsigned long flags;
1372 for (i = 0; i < 2; i++) {
1373 struct scatterlist *sg = &s->sg_rx[i];
1374 struct dma_async_tx_descriptor *desc;
1376 desc = dmaengine_prep_slave_sg(chan,
1377 sg, 1, DMA_DEV_TO_MEM,
1378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1382 desc->callback = sci_dma_rx_complete;
1383 desc->callback_param = s;
1384 s->cookie_rx[i] = dmaengine_submit(desc);
1385 if (dma_submit_error(s->cookie_rx[i]))
1390 s->active_rx = s->cookie_rx[0];
1392 dma_async_issue_pending(chan);
1397 if (!port_lock_held)
1398 spin_lock_irqsave(&port->lock, flags);
1400 dmaengine_terminate_async(chan);
1401 sci_dma_rx_chan_invalidate(s);
1403 if (!port_lock_held)
1404 spin_unlock_irqrestore(&port->lock, flags);
1408 static void sci_dma_tx_work_fn(struct work_struct *work)
1410 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1411 struct dma_async_tx_descriptor *desc;
1412 struct dma_chan *chan = s->chan_tx;
1413 struct uart_port *port = &s->port;
1414 struct circ_buf *xmit = &port->state->xmit;
1415 unsigned long flags;
1421 * Port xmit buffer is already mapped, and it is one page... Just adjust
1422 * offsets and lengths. Since it is a circular buffer, we have to
1423 * transmit till the end, and then the rest. Take the port lock to get a
1424 * consistent xmit buffer state.
1426 spin_lock_irq(&port->lock);
1429 buf = s->tx_dma_addr + (tail & (UART_XMIT_SIZE - 1));
1430 s->tx_dma_len = min_t(unsigned int,
1431 CIRC_CNT(head, tail, UART_XMIT_SIZE),
1432 CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE));
1433 if (!s->tx_dma_len) {
1434 /* Transmit buffer has been flushed */
1435 spin_unlock_irq(&port->lock);
1439 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1441 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1443 spin_unlock_irq(&port->lock);
1444 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1448 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1451 desc->callback = sci_dma_tx_complete;
1452 desc->callback_param = s;
1453 s->cookie_tx = dmaengine_submit(desc);
1454 if (dma_submit_error(s->cookie_tx)) {
1455 spin_unlock_irq(&port->lock);
1456 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1460 spin_unlock_irq(&port->lock);
1461 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1462 __func__, xmit->buf, tail, head, s->cookie_tx);
1464 dma_async_issue_pending(chan);
1468 spin_lock_irqsave(&port->lock, flags);
1471 spin_unlock_irqrestore(&port->lock, flags);
1475 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1477 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1478 struct dma_chan *chan = s->chan_rx;
1479 struct uart_port *port = &s->port;
1480 struct dma_tx_state state;
1481 enum dma_status status;
1482 unsigned long flags;
1486 dev_dbg(port->dev, "DMA Rx timed out\n");
1488 spin_lock_irqsave(&port->lock, flags);
1490 active = sci_dma_rx_find_active(s);
1492 spin_unlock_irqrestore(&port->lock, flags);
1493 return HRTIMER_NORESTART;
1496 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1497 if (status == DMA_COMPLETE) {
1498 spin_unlock_irqrestore(&port->lock, flags);
1499 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1500 s->active_rx, active);
1502 /* Let packet complete handler take care of the packet */
1503 return HRTIMER_NORESTART;
1506 dmaengine_pause(chan);
1509 * sometimes DMA transfer doesn't stop even if it is stopped and
1510 * data keeps on coming until transaction is complete so check
1511 * for DMA_COMPLETE again
1512 * Let packet complete handler take care of the packet
1514 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1515 if (status == DMA_COMPLETE) {
1516 spin_unlock_irqrestore(&port->lock, flags);
1517 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1518 return HRTIMER_NORESTART;
1521 /* Handle incomplete DMA receive */
1522 dmaengine_terminate_async(s->chan_rx);
1523 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1526 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1528 tty_flip_buffer_push(&port->state->port);
1531 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1532 sci_dma_rx_submit(s, true);
1534 sci_dma_rx_reenable_irq(s);
1536 spin_unlock_irqrestore(&port->lock, flags);
1538 return HRTIMER_NORESTART;
1541 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1542 enum dma_transfer_direction dir)
1544 struct dma_chan *chan;
1545 struct dma_slave_config cfg;
1548 chan = dma_request_slave_channel(port->dev,
1549 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1551 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1555 memset(&cfg, 0, sizeof(cfg));
1556 cfg.direction = dir;
1557 if (dir == DMA_MEM_TO_DEV) {
1558 cfg.dst_addr = port->mapbase +
1559 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1560 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1562 cfg.src_addr = port->mapbase +
1563 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1564 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1567 ret = dmaengine_slave_config(chan, &cfg);
1569 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1570 dma_release_channel(chan);
1577 static void sci_request_dma(struct uart_port *port)
1579 struct sci_port *s = to_sci_port(port);
1580 struct dma_chan *chan;
1582 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1585 * DMA on console may interfere with Kernel log messages which use
1586 * plain putchar(). So, simply don't use it with a console.
1588 if (uart_console(port))
1591 if (!port->dev->of_node)
1594 s->cookie_tx = -EINVAL;
1597 * Don't request a dma channel if no channel was specified
1598 * in the device tree.
1600 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1603 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1604 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1606 /* UART circular tx buffer is an aligned page. */
1607 s->tx_dma_addr = dma_map_single(chan->device->dev,
1608 port->state->xmit.buf,
1611 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1612 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1613 dma_release_channel(chan);
1615 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1616 __func__, UART_XMIT_SIZE,
1617 port->state->xmit.buf, &s->tx_dma_addr);
1619 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1620 s->chan_tx_saved = s->chan_tx = chan;
1624 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1625 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1631 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1632 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1636 "Failed to allocate Rx dma buffer, using PIO\n");
1637 dma_release_channel(chan);
1641 for (i = 0; i < 2; i++) {
1642 struct scatterlist *sg = &s->sg_rx[i];
1644 sg_init_table(sg, 1);
1646 sg_dma_address(sg) = dma;
1647 sg_dma_len(sg) = s->buf_len_rx;
1649 buf += s->buf_len_rx;
1650 dma += s->buf_len_rx;
1653 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1654 s->rx_timer.function = sci_dma_rx_timer_fn;
1656 s->chan_rx_saved = s->chan_rx = chan;
1658 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1659 sci_dma_rx_submit(s, false);
1663 static void sci_free_dma(struct uart_port *port)
1665 struct sci_port *s = to_sci_port(port);
1667 if (s->chan_tx_saved)
1668 sci_dma_tx_release(s);
1669 if (s->chan_rx_saved)
1670 sci_dma_rx_release(s);
1673 static void sci_flush_buffer(struct uart_port *port)
1675 struct sci_port *s = to_sci_port(port);
1678 * In uart_flush_buffer(), the xmit circular buffer has just been
1679 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1684 dmaengine_terminate_async(s->chan_tx);
1685 s->cookie_tx = -EINVAL;
1688 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1689 static inline void sci_request_dma(struct uart_port *port)
1693 static inline void sci_free_dma(struct uart_port *port)
1697 #define sci_flush_buffer NULL
1698 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1700 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1702 struct uart_port *port = ptr;
1703 struct sci_port *s = to_sci_port(port);
1705 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1707 u16 scr = serial_port_in(port, SCSCR);
1708 u16 ssr = serial_port_in(port, SCxSR);
1710 /* Disable future Rx interrupts */
1711 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1712 disable_irq_nosync(irq);
1715 if (sci_dma_rx_submit(s, false) < 0)
1720 serial_port_out(port, SCSCR, scr);
1721 /* Clear current interrupt */
1722 serial_port_out(port, SCxSR,
1723 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1724 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1725 jiffies, s->rx_timeout);
1726 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1734 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1735 if (!scif_rtrg_enabled(port))
1736 scif_set_rtrg(port, s->rx_trigger);
1738 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1739 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1742 /* I think sci_receive_chars has to be called irrespective
1743 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1746 sci_receive_chars(port);
1751 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1753 struct uart_port *port = ptr;
1754 unsigned long flags;
1756 spin_lock_irqsave(&port->lock, flags);
1757 sci_transmit_chars(port);
1758 spin_unlock_irqrestore(&port->lock, flags);
1763 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1765 struct uart_port *port = ptr;
1768 sci_handle_breaks(port);
1770 /* drop invalid character received before break was detected */
1771 serial_port_in(port, SCxRDR);
1773 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1778 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1780 struct uart_port *port = ptr;
1781 struct sci_port *s = to_sci_port(port);
1783 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1784 /* Break and Error interrupts are muxed */
1785 unsigned short ssr_status = serial_port_in(port, SCxSR);
1787 /* Break Interrupt */
1788 if (ssr_status & SCxSR_BRK(port))
1789 sci_br_interrupt(irq, ptr);
1792 if (!(ssr_status & SCxSR_ERRORS(port)))
1797 if (port->type == PORT_SCI) {
1798 if (sci_handle_errors(port)) {
1799 /* discard character in rx buffer */
1800 serial_port_in(port, SCxSR);
1801 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1804 sci_handle_fifo_overrun(port);
1806 sci_receive_chars(port);
1809 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1811 /* Kick the transmission */
1813 sci_tx_interrupt(irq, ptr);
1818 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1820 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1821 struct uart_port *port = ptr;
1822 struct sci_port *s = to_sci_port(port);
1823 irqreturn_t ret = IRQ_NONE;
1825 ssr_status = serial_port_in(port, SCxSR);
1826 scr_status = serial_port_in(port, SCSCR);
1827 if (s->params->overrun_reg == SCxSR)
1828 orer_status = ssr_status;
1829 else if (sci_getreg(port, s->params->overrun_reg)->size)
1830 orer_status = serial_port_in(port, s->params->overrun_reg);
1832 err_enabled = scr_status & port_rx_irq_mask(port);
1835 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1837 ret = sci_tx_interrupt(irq, ptr);
1840 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1843 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1844 (scr_status & SCSCR_RIE))
1845 ret = sci_rx_interrupt(irq, ptr);
1847 /* Error Interrupt */
1848 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1849 ret = sci_er_interrupt(irq, ptr);
1851 /* Break Interrupt */
1852 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1853 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1854 ret = sci_br_interrupt(irq, ptr);
1856 /* Overrun Interrupt */
1857 if (orer_status & s->params->overrun_mask) {
1858 sci_handle_fifo_overrun(port);
1865 static const struct sci_irq_desc {
1867 irq_handler_t handler;
1868 } sci_irq_desc[] = {
1870 * Split out handlers, the default case.
1874 .handler = sci_er_interrupt,
1879 .handler = sci_rx_interrupt,
1884 .handler = sci_tx_interrupt,
1889 .handler = sci_br_interrupt,
1894 .handler = sci_rx_interrupt,
1899 .handler = sci_tx_interrupt,
1903 * Special muxed handler.
1907 .handler = sci_mpxed_interrupt,
1911 static int sci_request_irq(struct sci_port *port)
1913 struct uart_port *up = &port->port;
1914 int i, j, w, ret = 0;
1916 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1917 const struct sci_irq_desc *desc;
1920 /* Check if already registered (muxed) */
1921 for (w = 0; w < i; w++)
1922 if (port->irqs[w] == port->irqs[i])
1927 if (SCIx_IRQ_IS_MUXED(port)) {
1931 irq = port->irqs[i];
1934 * Certain port types won't support all of the
1935 * available interrupt sources.
1937 if (unlikely(irq < 0))
1941 desc = sci_irq_desc + i;
1942 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1943 dev_name(up->dev), desc->desc);
1944 if (!port->irqstr[j]) {
1949 ret = request_irq(irq, desc->handler, up->irqflags,
1950 port->irqstr[j], port);
1951 if (unlikely(ret)) {
1952 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1961 free_irq(port->irqs[i], port);
1965 kfree(port->irqstr[j]);
1970 static void sci_free_irq(struct sci_port *port)
1975 * Intentionally in reverse order so we iterate over the muxed
1978 for (i = 0; i < SCIx_NR_IRQS; i++) {
1979 int irq = port->irqs[i];
1982 * Certain port types won't support all of the available
1983 * interrupt sources.
1985 if (unlikely(irq < 0))
1988 /* Check if already freed (irq was muxed) */
1989 for (j = 0; j < i; j++)
1990 if (port->irqs[j] == irq)
1995 free_irq(port->irqs[i], port);
1996 kfree(port->irqstr[i]);
1998 if (SCIx_IRQ_IS_MUXED(port)) {
1999 /* If there's only one IRQ, we're done. */
2005 static unsigned int sci_tx_empty(struct uart_port *port)
2007 unsigned short status = serial_port_in(port, SCxSR);
2008 unsigned short in_tx_fifo = sci_txfill(port);
2010 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2013 static void sci_set_rts(struct uart_port *port, bool state)
2015 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2016 u16 data = serial_port_in(port, SCPDR);
2020 data &= ~SCPDR_RTSD;
2023 serial_port_out(port, SCPDR, data);
2025 /* RTS# is output */
2026 serial_port_out(port, SCPCR,
2027 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2028 } else if (sci_getreg(port, SCSPTR)->size) {
2029 u16 ctrl = serial_port_in(port, SCSPTR);
2033 ctrl &= ~SCSPTR_RTSDT;
2035 ctrl |= SCSPTR_RTSDT;
2036 serial_port_out(port, SCSPTR, ctrl);
2040 static bool sci_get_cts(struct uart_port *port)
2042 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2044 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2045 } else if (sci_getreg(port, SCSPTR)->size) {
2047 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2054 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2055 * CTS/RTS is supported in hardware by at least one port and controlled
2056 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2057 * handled via the ->init_pins() op, which is a bit of a one-way street,
2058 * lacking any ability to defer pin control -- this will later be
2059 * converted over to the GPIO framework).
2061 * Other modes (such as loopback) are supported generically on certain
2062 * port types, but not others. For these it's sufficient to test for the
2063 * existence of the support register and simply ignore the port type.
2065 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2067 struct sci_port *s = to_sci_port(port);
2069 if (mctrl & TIOCM_LOOP) {
2070 const struct plat_sci_reg *reg;
2073 * Standard loopback mode for SCFCR ports.
2075 reg = sci_getreg(port, SCFCR);
2077 serial_port_out(port, SCFCR,
2078 serial_port_in(port, SCFCR) |
2082 mctrl_gpio_set(s->gpios, mctrl);
2087 if (!(mctrl & TIOCM_RTS)) {
2088 /* Disable Auto RTS */
2089 serial_port_out(port, SCFCR,
2090 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2093 sci_set_rts(port, 0);
2094 } else if (s->autorts) {
2095 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2096 /* Enable RTS# pin function */
2097 serial_port_out(port, SCPCR,
2098 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2101 /* Enable Auto RTS */
2102 serial_port_out(port, SCFCR,
2103 serial_port_in(port, SCFCR) | SCFCR_MCE);
2106 sci_set_rts(port, 1);
2110 static unsigned int sci_get_mctrl(struct uart_port *port)
2112 struct sci_port *s = to_sci_port(port);
2113 struct mctrl_gpios *gpios = s->gpios;
2114 unsigned int mctrl = 0;
2116 mctrl_gpio_get(gpios, &mctrl);
2119 * CTS/RTS is handled in hardware when supported, while nothing
2123 if (sci_get_cts(port))
2125 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2128 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2130 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2136 static void sci_enable_ms(struct uart_port *port)
2138 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2141 static void sci_break_ctl(struct uart_port *port, int break_state)
2143 unsigned short scscr, scsptr;
2144 unsigned long flags;
2146 /* check wheter the port has SCSPTR */
2147 if (!sci_getreg(port, SCSPTR)->size) {
2149 * Not supported by hardware. Most parts couple break and rx
2150 * interrupts together, with break detection always enabled.
2155 spin_lock_irqsave(&port->lock, flags);
2156 scsptr = serial_port_in(port, SCSPTR);
2157 scscr = serial_port_in(port, SCSCR);
2159 if (break_state == -1) {
2160 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2163 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2167 serial_port_out(port, SCSPTR, scsptr);
2168 serial_port_out(port, SCSCR, scscr);
2169 spin_unlock_irqrestore(&port->lock, flags);
2172 static int sci_startup(struct uart_port *port)
2174 struct sci_port *s = to_sci_port(port);
2177 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2179 sci_request_dma(port);
2181 ret = sci_request_irq(s);
2182 if (unlikely(ret < 0)) {
2190 static void sci_shutdown(struct uart_port *port)
2192 struct sci_port *s = to_sci_port(port);
2193 unsigned long flags;
2196 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2199 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2201 spin_lock_irqsave(&port->lock, flags);
2205 * Stop RX and TX, disable related interrupts, keep clock source
2206 * and HSCIF TOT bits
2208 scr = serial_port_in(port, SCSCR);
2209 serial_port_out(port, SCSCR, scr &
2210 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2211 spin_unlock_irqrestore(&port->lock, flags);
2213 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2214 if (s->chan_rx_saved) {
2215 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2217 hrtimer_cancel(&s->rx_timer);
2221 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2222 del_timer_sync(&s->rx_fifo_timer);
2227 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2230 unsigned long freq = s->clk_rates[SCI_SCK];
2231 int err, min_err = INT_MAX;
2234 if (s->port.type != PORT_HSCIF)
2237 for_each_sr(sr, s) {
2238 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2239 if (abs(err) >= abs(min_err))
2249 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2254 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2255 unsigned long freq, unsigned int *dlr,
2258 int err, min_err = INT_MAX;
2259 unsigned int sr, dl;
2261 if (s->port.type != PORT_HSCIF)
2264 for_each_sr(sr, s) {
2265 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2266 dl = clamp(dl, 1U, 65535U);
2268 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2269 if (abs(err) >= abs(min_err))
2280 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2281 min_err, *dlr, *srr + 1);
2285 /* calculate sample rate, BRR, and clock select */
2286 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2287 unsigned int *brr, unsigned int *srr,
2290 unsigned long freq = s->clk_rates[SCI_FCK];
2291 unsigned int sr, br, prediv, scrate, c;
2292 int err, min_err = INT_MAX;
2294 if (s->port.type != PORT_HSCIF)
2298 * Find the combination of sample rate and clock select with the
2299 * smallest deviation from the desired baud rate.
2300 * Prefer high sample rates to maximise the receive margin.
2302 * M: Receive margin (%)
2303 * N: Ratio of bit rate to clock (N = sampling rate)
2304 * D: Clock duty (D = 0 to 1.0)
2305 * L: Frame length (L = 9 to 12)
2306 * F: Absolute value of clock frequency deviation
2308 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2309 * (|D - 0.5| / N * (1 + F))|
2310 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2312 for_each_sr(sr, s) {
2313 for (c = 0; c <= 3; c++) {
2314 /* integerized formulas from HSCIF documentation */
2315 prediv = sr * (1 << (2 * c + 1));
2318 * We need to calculate:
2320 * br = freq / (prediv * bps) clamped to [1..256]
2321 * err = freq / (br * prediv) - bps
2323 * Watch out for overflow when calculating the desired
2324 * sampling clock rate!
2326 if (bps > UINT_MAX / prediv)
2329 scrate = prediv * bps;
2330 br = DIV_ROUND_CLOSEST(freq, scrate);
2331 br = clamp(br, 1U, 256U);
2333 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2334 if (abs(err) >= abs(min_err))
2348 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2349 min_err, *brr, *srr + 1, *cks);
2353 static void sci_reset(struct uart_port *port)
2355 const struct plat_sci_reg *reg;
2356 unsigned int status;
2357 struct sci_port *s = to_sci_port(port);
2359 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2361 reg = sci_getreg(port, SCFCR);
2363 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2365 sci_clear_SCxSR(port,
2366 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2367 SCxSR_BREAK_CLEAR(port));
2368 if (sci_getreg(port, SCLSR)->size) {
2369 status = serial_port_in(port, SCLSR);
2370 status &= ~(SCLSR_TO | SCLSR_ORER);
2371 serial_port_out(port, SCLSR, status);
2374 if (s->rx_trigger > 1) {
2375 if (s->rx_fifo_timeout) {
2376 scif_set_rtrg(port, 1);
2377 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2379 if (port->type == PORT_SCIFA ||
2380 port->type == PORT_SCIFB)
2381 scif_set_rtrg(port, 1);
2383 scif_set_rtrg(port, s->rx_trigger);
2388 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2389 struct ktermios *old)
2391 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2392 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2393 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2394 struct sci_port *s = to_sci_port(port);
2395 const struct plat_sci_reg *reg;
2396 int min_err = INT_MAX, err;
2397 unsigned long max_freq = 0;
2399 unsigned long flags;
2401 if ((termios->c_cflag & CSIZE) == CS7) {
2402 smr_val |= SCSMR_CHR;
2404 termios->c_cflag &= ~CSIZE;
2405 termios->c_cflag |= CS8;
2407 if (termios->c_cflag & PARENB)
2408 smr_val |= SCSMR_PE;
2409 if (termios->c_cflag & PARODD)
2410 smr_val |= SCSMR_PE | SCSMR_ODD;
2411 if (termios->c_cflag & CSTOPB)
2412 smr_val |= SCSMR_STOP;
2415 * earlyprintk comes here early on with port->uartclk set to zero.
2416 * the clock framework is not up and running at this point so here
2417 * we assume that 115200 is the maximum baud rate. please note that
2418 * the baud rate is not programmed during earlyprintk - it is assumed
2419 * that the previous boot loader has enabled required clocks and
2420 * setup the baud rate generator hardware for us already.
2422 if (!port->uartclk) {
2423 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2427 for (i = 0; i < SCI_NUM_CLKS; i++)
2428 max_freq = max(max_freq, s->clk_rates[i]);
2430 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2435 * There can be multiple sources for the sampling clock. Find the one
2436 * that gives us the smallest deviation from the desired baud rate.
2439 /* Optional Undivided External Clock */
2440 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2441 port->type != PORT_SCIFB) {
2442 err = sci_sck_calc(s, baud, &srr1);
2443 if (abs(err) < abs(min_err)) {
2445 scr_val = SCSCR_CKE1;
2454 /* Optional BRG Frequency Divided External Clock */
2455 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2456 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2458 if (abs(err) < abs(min_err)) {
2459 best_clk = SCI_SCIF_CLK;
2460 scr_val = SCSCR_CKE1;
2470 /* Optional BRG Frequency Divided Internal Clock */
2471 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2472 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2474 if (abs(err) < abs(min_err)) {
2475 best_clk = SCI_BRG_INT;
2476 scr_val = SCSCR_CKE1;
2486 /* Divided Functional Clock using standard Bit Rate Register */
2487 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2488 if (abs(err) < abs(min_err)) {
2499 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2500 s->clks[best_clk], baud, min_err);
2505 * Program the optional External Baud Rate Generator (BRG) first.
2506 * It controls the mux to select (H)SCK or frequency divided clock.
2508 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2509 serial_port_out(port, SCDL, dl);
2510 serial_port_out(port, SCCKS, sccks);
2513 spin_lock_irqsave(&port->lock, flags);
2517 uart_update_timeout(port, termios->c_cflag, baud);
2519 /* byte size and parity */
2520 switch (termios->c_cflag & CSIZE) {
2535 if (termios->c_cflag & CSTOPB)
2537 if (termios->c_cflag & PARENB)
2540 if (best_clk >= 0) {
2541 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2543 case 5: smr_val |= SCSMR_SRC_5; break;
2544 case 7: smr_val |= SCSMR_SRC_7; break;
2545 case 11: smr_val |= SCSMR_SRC_11; break;
2546 case 13: smr_val |= SCSMR_SRC_13; break;
2547 case 16: smr_val |= SCSMR_SRC_16; break;
2548 case 17: smr_val |= SCSMR_SRC_17; break;
2549 case 19: smr_val |= SCSMR_SRC_19; break;
2550 case 27: smr_val |= SCSMR_SRC_27; break;
2553 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2554 serial_port_out(port, SCSMR, smr_val);
2555 serial_port_out(port, SCBRR, brr);
2556 if (sci_getreg(port, HSSRR)->size) {
2557 unsigned int hssrr = srr | HSCIF_SRE;
2558 /* Calculate deviation from intended rate at the
2559 * center of the last stop bit in sampling clocks.
2561 int last_stop = bits * 2 - 1;
2562 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2566 if (abs(deviation) >= 2) {
2567 /* At least two sampling clocks off at the
2568 * last stop bit; we can increase the error
2569 * margin by shifting the sampling point.
2571 int shift = clamp(deviation / 2, -8, 7);
2573 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2575 hssrr |= HSCIF_SRDE;
2577 serial_port_out(port, HSSRR, hssrr);
2580 /* Wait one bit interval */
2581 udelay((1000000 + (baud - 1)) / baud);
2583 /* Don't touch the bit rate configuration */
2584 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2585 smr_val |= serial_port_in(port, SCSMR) &
2586 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2587 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2588 serial_port_out(port, SCSMR, smr_val);
2591 sci_init_pins(port, termios->c_cflag);
2593 port->status &= ~UPSTAT_AUTOCTS;
2595 reg = sci_getreg(port, SCFCR);
2597 unsigned short ctrl = serial_port_in(port, SCFCR);
2599 if ((port->flags & UPF_HARD_FLOW) &&
2600 (termios->c_cflag & CRTSCTS)) {
2601 /* There is no CTS interrupt to restart the hardware */
2602 port->status |= UPSTAT_AUTOCTS;
2603 /* MCE is enabled when RTS is raised */
2608 * As we've done a sci_reset() above, ensure we don't
2609 * interfere with the FIFOs while toggling MCE. As the
2610 * reset values could still be set, simply mask them out.
2612 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2614 serial_port_out(port, SCFCR, ctrl);
2616 if (port->flags & UPF_HARD_FLOW) {
2617 /* Refresh (Auto) RTS */
2618 sci_set_mctrl(port, port->mctrl);
2621 scr_val |= SCSCR_RE | SCSCR_TE |
2622 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2623 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2624 if ((srr + 1 == 5) &&
2625 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2627 * In asynchronous mode, when the sampling rate is 1/5, first
2628 * received data may become invalid on some SCIFA and SCIFB.
2629 * To avoid this problem wait more than 1 serial data time (1
2630 * bit time x serial data number) after setting SCSCR.RE = 1.
2632 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2636 * Calculate delay for 2 DMA buffers (4 FIFO).
2637 * See serial_core.c::uart_update_timeout().
2638 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2639 * function calculates 1 jiffie for the data plus 5 jiffies for the
2640 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2641 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2642 * value obtained by this formula is too small. Therefore, if the value
2643 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2645 s->rx_frame = (10000 * bits) / (baud / 100);
2646 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2647 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2648 if (s->rx_timeout < 20)
2652 if ((termios->c_cflag & CREAD) != 0)
2655 spin_unlock_irqrestore(&port->lock, flags);
2657 sci_port_disable(s);
2659 if (UART_ENABLE_MS(port, termios->c_cflag))
2660 sci_enable_ms(port);
2663 static void sci_pm(struct uart_port *port, unsigned int state,
2664 unsigned int oldstate)
2666 struct sci_port *sci_port = to_sci_port(port);
2669 case UART_PM_STATE_OFF:
2670 sci_port_disable(sci_port);
2673 sci_port_enable(sci_port);
2678 static const char *sci_type(struct uart_port *port)
2680 switch (port->type) {
2698 static int sci_remap_port(struct uart_port *port)
2700 struct sci_port *sport = to_sci_port(port);
2703 * Nothing to do if there's already an established membase.
2708 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2709 port->membase = ioremap(port->mapbase, sport->reg_size);
2710 if (unlikely(!port->membase)) {
2711 dev_err(port->dev, "can't remap port#%d\n", port->line);
2716 * For the simple (and majority of) cases where we don't
2717 * need to do any remapping, just cast the cookie
2720 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2726 static void sci_release_port(struct uart_port *port)
2728 struct sci_port *sport = to_sci_port(port);
2730 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2731 iounmap(port->membase);
2732 port->membase = NULL;
2735 release_mem_region(port->mapbase, sport->reg_size);
2738 static int sci_request_port(struct uart_port *port)
2740 struct resource *res;
2741 struct sci_port *sport = to_sci_port(port);
2744 res = request_mem_region(port->mapbase, sport->reg_size,
2745 dev_name(port->dev));
2746 if (unlikely(res == NULL)) {
2747 dev_err(port->dev, "request_mem_region failed.");
2751 ret = sci_remap_port(port);
2752 if (unlikely(ret != 0)) {
2753 release_resource(res);
2760 static void sci_config_port(struct uart_port *port, int flags)
2762 if (flags & UART_CONFIG_TYPE) {
2763 struct sci_port *sport = to_sci_port(port);
2765 port->type = sport->cfg->type;
2766 sci_request_port(port);
2770 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2772 if (ser->baud_base < 2400)
2773 /* No paper tape reader for Mitch.. */
2779 static const struct uart_ops sci_uart_ops = {
2780 .tx_empty = sci_tx_empty,
2781 .set_mctrl = sci_set_mctrl,
2782 .get_mctrl = sci_get_mctrl,
2783 .start_tx = sci_start_tx,
2784 .stop_tx = sci_stop_tx,
2785 .stop_rx = sci_stop_rx,
2786 .enable_ms = sci_enable_ms,
2787 .break_ctl = sci_break_ctl,
2788 .startup = sci_startup,
2789 .shutdown = sci_shutdown,
2790 .flush_buffer = sci_flush_buffer,
2791 .set_termios = sci_set_termios,
2794 .release_port = sci_release_port,
2795 .request_port = sci_request_port,
2796 .config_port = sci_config_port,
2797 .verify_port = sci_verify_port,
2798 #ifdef CONFIG_CONSOLE_POLL
2799 .poll_get_char = sci_poll_get_char,
2800 .poll_put_char = sci_poll_put_char,
2804 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2806 const char *clk_names[] = {
2809 [SCI_BRG_INT] = "brg_int",
2810 [SCI_SCIF_CLK] = "scif_clk",
2815 if (sci_port->cfg->type == PORT_HSCIF)
2816 clk_names[SCI_SCK] = "hsck";
2818 for (i = 0; i < SCI_NUM_CLKS; i++) {
2819 clk = devm_clk_get(dev, clk_names[i]);
2820 if (PTR_ERR(clk) == -EPROBE_DEFER)
2821 return -EPROBE_DEFER;
2823 if (IS_ERR(clk) && i == SCI_FCK) {
2825 * "fck" used to be called "sci_ick", and we need to
2826 * maintain DT backward compatibility.
2828 clk = devm_clk_get(dev, "sci_ick");
2829 if (PTR_ERR(clk) == -EPROBE_DEFER)
2830 return -EPROBE_DEFER;
2836 * Not all SH platforms declare a clock lookup entry
2837 * for SCI devices, in which case we need to get the
2838 * global "peripheral_clk" clock.
2840 clk = devm_clk_get(dev, "peripheral_clk");
2844 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2846 return PTR_ERR(clk);
2851 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2854 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2855 clk, clk_get_rate(clk));
2856 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2861 static const struct sci_port_params *
2862 sci_probe_regmap(const struct plat_sci_port *cfg)
2864 unsigned int regtype;
2866 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2867 return &sci_port_params[cfg->regtype];
2869 switch (cfg->type) {
2871 regtype = SCIx_SCI_REGTYPE;
2874 regtype = SCIx_IRDA_REGTYPE;
2877 regtype = SCIx_SCIFA_REGTYPE;
2880 regtype = SCIx_SCIFB_REGTYPE;
2884 * The SH-4 is a bit of a misnomer here, although that's
2885 * where this particular port layout originated. This
2886 * configuration (or some slight variation thereof)
2887 * remains the dominant model for all SCIFs.
2889 regtype = SCIx_SH4_SCIF_REGTYPE;
2892 regtype = SCIx_HSCIF_REGTYPE;
2895 pr_err("Can't probe register map for given port\n");
2899 return &sci_port_params[regtype];
2902 static int sci_init_single(struct platform_device *dev,
2903 struct sci_port *sci_port, unsigned int index,
2904 const struct plat_sci_port *p, bool early)
2906 struct uart_port *port = &sci_port->port;
2907 const struct resource *res;
2913 port->ops = &sci_uart_ops;
2914 port->iotype = UPIO_MEM;
2916 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2918 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2922 port->mapbase = res->start;
2923 sci_port->reg_size = resource_size(res);
2925 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2927 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2929 sci_port->irqs[i] = platform_get_irq(dev, i);
2933 * The fourth interrupt on SCI port is transmit end interrupt, so
2934 * shuffle the interrupts.
2936 if (p->type == PORT_SCI)
2937 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
2939 /* The SCI generates several interrupts. They can be muxed together or
2940 * connected to different interrupt lines. In the muxed case only one
2941 * interrupt resource is specified as there is only one interrupt ID.
2942 * In the non-muxed case, up to 6 interrupt signals might be generated
2943 * from the SCI, however those signals might have their own individual
2944 * interrupt ID numbers, or muxed together with another interrupt.
2946 if (sci_port->irqs[0] < 0)
2949 if (sci_port->irqs[1] < 0)
2950 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2951 sci_port->irqs[i] = sci_port->irqs[0];
2953 sci_port->params = sci_probe_regmap(p);
2954 if (unlikely(sci_port->params == NULL))
2959 sci_port->rx_trigger = 48;
2962 sci_port->rx_trigger = 64;
2965 sci_port->rx_trigger = 32;
2968 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2969 /* RX triggering not implemented for this IP */
2970 sci_port->rx_trigger = 1;
2972 sci_port->rx_trigger = 8;
2975 sci_port->rx_trigger = 1;
2979 sci_port->rx_fifo_timeout = 0;
2980 sci_port->hscif_tot = 0;
2982 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2983 * match the SoC datasheet, this should be investigated. Let platform
2984 * data override the sampling rate for now.
2986 sci_port->sampling_rate_mask = p->sampling_rate
2987 ? SCI_SR(p->sampling_rate)
2988 : sci_port->params->sampling_rate_mask;
2991 ret = sci_init_clocks(sci_port, &dev->dev);
2995 port->dev = &dev->dev;
2997 pm_runtime_enable(&dev->dev);
3000 port->type = p->type;
3001 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3002 port->fifosize = sci_port->params->fifosize;
3004 if (port->type == PORT_SCI && !dev->dev.of_node) {
3005 if (sci_port->reg_size >= 0x20)
3012 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3013 * for the multi-IRQ ports, which is where we are primarily
3014 * concerned with the shutdown path synchronization.
3016 * For the muxed case there's nothing more to do.
3018 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3021 port->serial_in = sci_serial_in;
3022 port->serial_out = sci_serial_out;
3027 static void sci_cleanup_single(struct sci_port *port)
3029 pm_runtime_disable(port->port.dev);
3032 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3033 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3034 static void serial_console_putchar(struct uart_port *port, int ch)
3036 sci_poll_put_char(port, ch);
3040 * Print a string to the serial port trying not to disturb
3041 * any possible real use of the port...
3043 static void serial_console_write(struct console *co, const char *s,
3046 struct sci_port *sci_port = &sci_ports[co->index];
3047 struct uart_port *port = &sci_port->port;
3048 unsigned short bits, ctrl, ctrl_temp;
3049 unsigned long flags;
3054 else if (oops_in_progress)
3055 locked = spin_trylock_irqsave(&port->lock, flags);
3057 spin_lock_irqsave(&port->lock, flags);
3059 /* first save SCSCR then disable interrupts, keep clock source */
3060 ctrl = serial_port_in(port, SCSCR);
3061 ctrl_temp = SCSCR_RE | SCSCR_TE |
3062 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3063 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3064 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3066 uart_console_write(port, s, count, serial_console_putchar);
3068 /* wait until fifo is empty and last bit has been transmitted */
3069 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3070 while ((serial_port_in(port, SCxSR) & bits) != bits)
3073 /* restore the SCSCR */
3074 serial_port_out(port, SCSCR, ctrl);
3077 spin_unlock_irqrestore(&port->lock, flags);
3080 static int serial_console_setup(struct console *co, char *options)
3082 struct sci_port *sci_port;
3083 struct uart_port *port;
3091 * Refuse to handle any bogus ports.
3093 if (co->index < 0 || co->index >= SCI_NPORTS)
3096 sci_port = &sci_ports[co->index];
3097 port = &sci_port->port;
3100 * Refuse to handle uninitialized ports.
3105 ret = sci_remap_port(port);
3106 if (unlikely(ret != 0))
3110 uart_parse_options(options, &baud, &parity, &bits, &flow);
3112 return uart_set_options(port, co, baud, parity, bits, flow);
3115 static struct console serial_console = {
3117 .device = uart_console_device,
3118 .write = serial_console_write,
3119 .setup = serial_console_setup,
3120 .flags = CON_PRINTBUFFER,
3122 .data = &sci_uart_driver,
3125 #ifdef CONFIG_SUPERH
3126 static struct console early_serial_console = {
3127 .name = "early_ttySC",
3128 .write = serial_console_write,
3129 .flags = CON_PRINTBUFFER,
3133 static char early_serial_buf[32];
3135 static int sci_probe_earlyprintk(struct platform_device *pdev)
3137 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3139 if (early_serial_console.data)
3142 early_serial_console.index = pdev->id;
3144 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3146 serial_console_setup(&early_serial_console, early_serial_buf);
3148 if (!strstr(early_serial_buf, "keep"))
3149 early_serial_console.flags |= CON_BOOT;
3151 register_console(&early_serial_console);
3156 #define SCI_CONSOLE (&serial_console)
3159 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3164 #define SCI_CONSOLE NULL
3166 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3168 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3170 static DEFINE_MUTEX(sci_uart_registration_lock);
3171 static struct uart_driver sci_uart_driver = {
3172 .owner = THIS_MODULE,
3173 .driver_name = "sci",
3174 .dev_name = "ttySC",
3176 .minor = SCI_MINOR_START,
3178 .cons = SCI_CONSOLE,
3181 static int sci_remove(struct platform_device *dev)
3183 struct sci_port *port = platform_get_drvdata(dev);
3184 unsigned int type = port->port.type; /* uart_remove_... clears it */
3186 sci_ports_in_use &= ~BIT(port->port.line);
3187 uart_remove_one_port(&sci_uart_driver, &port->port);
3189 sci_cleanup_single(port);
3191 if (port->port.fifosize > 1)
3192 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3193 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3194 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3200 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3201 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3202 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3204 static const struct of_device_id of_sci_match[] = {
3205 /* SoC-specific types */
3207 .compatible = "renesas,scif-r7s72100",
3208 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3211 .compatible = "renesas,scif-r7s9210",
3212 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3214 /* Family-specific types */
3216 .compatible = "renesas,rcar-gen1-scif",
3217 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3219 .compatible = "renesas,rcar-gen2-scif",
3220 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3222 .compatible = "renesas,rcar-gen3-scif",
3223 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3227 .compatible = "renesas,scif",
3228 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3230 .compatible = "renesas,scifa",
3231 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3233 .compatible = "renesas,scifb",
3234 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3236 .compatible = "renesas,hscif",
3237 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3239 .compatible = "renesas,sci",
3240 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3245 MODULE_DEVICE_TABLE(of, of_sci_match);
3247 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3248 unsigned int *dev_id)
3250 struct device_node *np = pdev->dev.of_node;
3251 struct plat_sci_port *p;
3252 struct sci_port *sp;
3256 if (!IS_ENABLED(CONFIG_OF) || !np)
3259 data = of_device_get_match_data(&pdev->dev);
3261 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3265 /* Get the line number from the aliases node. */
3266 id = of_alias_get_id(np, "serial");
3267 if (id < 0 && ~sci_ports_in_use)
3268 id = ffz(sci_ports_in_use);
3270 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3273 if (id >= ARRAY_SIZE(sci_ports)) {
3274 dev_err(&pdev->dev, "serial%d out of range\n", id);
3278 sp = &sci_ports[id];
3281 p->type = SCI_OF_TYPE(data);
3282 p->regtype = SCI_OF_REGTYPE(data);
3284 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3289 static int sci_probe_single(struct platform_device *dev,
3291 struct plat_sci_port *p,
3292 struct sci_port *sciport)
3297 if (unlikely(index >= SCI_NPORTS)) {
3298 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3299 index+1, SCI_NPORTS);
3300 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3303 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3304 if (sci_ports_in_use & BIT(index))
3307 mutex_lock(&sci_uart_registration_lock);
3308 if (!sci_uart_driver.state) {
3309 ret = uart_register_driver(&sci_uart_driver);
3311 mutex_unlock(&sci_uart_registration_lock);
3315 mutex_unlock(&sci_uart_registration_lock);
3317 ret = sci_init_single(dev, sciport, index, p, false);
3321 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3322 if (IS_ERR(sciport->gpios))
3323 return PTR_ERR(sciport->gpios);
3325 if (sciport->has_rtscts) {
3326 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3327 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3328 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3331 sciport->port.flags |= UPF_HARD_FLOW;
3334 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3336 sci_cleanup_single(sciport);
3343 static int sci_probe(struct platform_device *dev)
3345 struct plat_sci_port *p;
3346 struct sci_port *sp;
3347 unsigned int dev_id;
3351 * If we've come here via earlyprintk initialization, head off to
3352 * the special early probe. We don't have sufficient device state
3353 * to make it beyond this yet.
3355 #ifdef CONFIG_SUPERH
3356 if (is_sh_early_platform_device(dev))
3357 return sci_probe_earlyprintk(dev);
3360 if (dev->dev.of_node) {
3361 p = sci_parse_dt(dev, &dev_id);
3365 p = dev->dev.platform_data;
3367 dev_err(&dev->dev, "no platform data supplied\n");
3374 sp = &sci_ports[dev_id];
3375 platform_set_drvdata(dev, sp);
3377 ret = sci_probe_single(dev, dev_id, p, sp);
3381 if (sp->port.fifosize > 1) {
3382 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3386 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3387 sp->port.type == PORT_HSCIF) {
3388 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3390 if (sp->port.fifosize > 1) {
3391 device_remove_file(&dev->dev,
3392 &dev_attr_rx_fifo_trigger);
3398 #ifdef CONFIG_SH_STANDARD_BIOS
3399 sh_bios_gdb_detach();
3402 sci_ports_in_use |= BIT(dev_id);
3406 static __maybe_unused int sci_suspend(struct device *dev)
3408 struct sci_port *sport = dev_get_drvdata(dev);
3411 uart_suspend_port(&sci_uart_driver, &sport->port);
3416 static __maybe_unused int sci_resume(struct device *dev)
3418 struct sci_port *sport = dev_get_drvdata(dev);
3421 uart_resume_port(&sci_uart_driver, &sport->port);
3426 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3428 static struct platform_driver sci_driver = {
3430 .remove = sci_remove,
3433 .pm = &sci_dev_pm_ops,
3434 .of_match_table = of_match_ptr(of_sci_match),
3438 static int __init sci_init(void)
3440 pr_info("%s\n", banner);
3442 return platform_driver_register(&sci_driver);
3445 static void __exit sci_exit(void)
3447 platform_driver_unregister(&sci_driver);
3449 if (sci_uart_driver.state)
3450 uart_unregister_driver(&sci_uart_driver);
3453 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3454 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3455 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3457 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3458 static struct plat_sci_port port_cfg __initdata;
3460 static int __init early_console_setup(struct earlycon_device *device,
3463 if (!device->port.membase)
3466 device->port.serial_in = sci_serial_in;
3467 device->port.serial_out = sci_serial_out;
3468 device->port.type = type;
3469 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3470 port_cfg.type = type;
3471 sci_ports[0].cfg = &port_cfg;
3472 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3473 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3474 sci_serial_out(&sci_ports[0].port, SCSCR,
3475 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3477 device->con->write = serial_console_write;
3480 static int __init sci_early_console_setup(struct earlycon_device *device,
3483 return early_console_setup(device, PORT_SCI);
3485 static int __init scif_early_console_setup(struct earlycon_device *device,
3488 return early_console_setup(device, PORT_SCIF);
3490 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3493 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3494 return early_console_setup(device, PORT_SCIF);
3496 static int __init scifa_early_console_setup(struct earlycon_device *device,
3499 return early_console_setup(device, PORT_SCIFA);
3501 static int __init scifb_early_console_setup(struct earlycon_device *device,
3504 return early_console_setup(device, PORT_SCIFB);
3506 static int __init hscif_early_console_setup(struct earlycon_device *device,
3509 return early_console_setup(device, PORT_HSCIF);
3512 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3513 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3514 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3515 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3516 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3517 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3518 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3520 module_init(sci_init);
3521 module_exit(sci_exit);
3523 MODULE_LICENSE("GPL");
3524 MODULE_ALIAS("platform:sh-sci");
3525 MODULE_AUTHOR("Paul Mundt");
3526 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");