4 * High-speed serial driver for NVIDIA Tegra SoCs
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 #include <linux/clk.h>
24 #include <linux/debugfs.h>
25 #include <linux/delay.h>
26 #include <linux/dmaengine.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmapool.h>
29 #include <linux/err.h>
31 #include <linux/irq.h>
32 #include <linux/module.h>
34 #include <linux/of_device.h>
35 #include <linux/pagemap.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/serial.h>
39 #include <linux/serial_8250.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial_reg.h>
42 #include <linux/slab.h>
43 #include <linux/string.h>
44 #include <linux/termios.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
48 #define TEGRA_UART_TYPE "TEGRA_UART"
49 #define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
50 #define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
52 #define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
53 #define TEGRA_UART_LSR_TXFIFO_FULL 0x100
54 #define TEGRA_UART_IER_EORD 0x20
55 #define TEGRA_UART_MCR_RTS_EN 0x40
56 #define TEGRA_UART_MCR_CTS_EN 0x20
57 #define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
58 UART_LSR_PE | UART_LSR_FE)
59 #define TEGRA_UART_IRDA_CSR 0x08
60 #define TEGRA_UART_SIR_ENABLED 0x80
62 #define TEGRA_UART_TX_PIO 1
63 #define TEGRA_UART_TX_DMA 2
64 #define TEGRA_UART_MIN_DMA 16
65 #define TEGRA_UART_FIFO_SIZE 32
68 * Tx fifo trigger level setting in tegra uart is in
69 * reverse way then conventional uart.
71 #define TEGRA_UART_TX_TRIG_16B 0x00
72 #define TEGRA_UART_TX_TRIG_8B 0x10
73 #define TEGRA_UART_TX_TRIG_4B 0x20
74 #define TEGRA_UART_TX_TRIG_1B 0x30
76 #define TEGRA_UART_MAXIMUM 5
78 /* Default UART setting when started: 115200 no parity, stop, 8 data bits */
79 #define TEGRA_UART_DEFAULT_BAUD 115200
80 #define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
82 /* Tx transfer mode */
83 #define TEGRA_TX_PIO 1
84 #define TEGRA_TX_DMA 2
87 * tegra_uart_chip_data: SOC specific data.
89 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
90 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
91 * Tegra30 does not allow this.
92 * @support_clk_src_div: Clock source support the clock divider.
94 struct tegra_uart_chip_data {
95 bool tx_fifo_full_status;
96 bool allow_txfifo_reset_fifo_mode;
97 bool support_clk_src_div;
100 struct tegra_uart_port {
101 struct uart_port uport;
102 const struct tegra_uart_chip_data *cdata;
104 struct clk *uart_clk;
105 struct reset_control *rst;
106 unsigned int current_baud;
108 /* Register shadow */
109 unsigned long fcr_shadow;
110 unsigned long mcr_shadow;
111 unsigned long lcr_shadow;
112 unsigned long ier_shadow;
116 unsigned int tx_bytes;
118 bool enable_modem_interrupt;
124 struct dma_chan *rx_dma_chan;
125 struct dma_chan *tx_dma_chan;
126 dma_addr_t rx_dma_buf_phys;
127 dma_addr_t tx_dma_buf_phys;
128 unsigned char *rx_dma_buf_virt;
129 unsigned char *tx_dma_buf_virt;
130 struct dma_async_tx_descriptor *tx_dma_desc;
131 struct dma_async_tx_descriptor *rx_dma_desc;
132 dma_cookie_t tx_cookie;
133 dma_cookie_t rx_cookie;
134 unsigned int tx_bytes_requested;
135 unsigned int rx_bytes_requested;
138 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
139 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
141 static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
144 return readl(tup->uport.membase + (reg << tup->uport.regshift));
147 static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
150 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
153 static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
155 return container_of(u, struct tegra_uart_port, uport);
158 static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
160 struct tegra_uart_port *tup = to_tegra_uport(u);
163 * RI - Ring detector is active
164 * CD/DCD/CAR - Carrier detect is always active. For some reason
165 * linux has different names for carrier detect.
166 * DSR - Data Set ready is active as the hardware doesn't support it.
167 * Don't know if the linux support this yet?
168 * CTS - Clear to send. Always set to active, as the hardware handles
171 if (tup->enable_modem_interrupt)
172 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
176 static void set_rts(struct tegra_uart_port *tup, bool active)
180 mcr = tup->mcr_shadow;
182 mcr |= TEGRA_UART_MCR_RTS_EN;
184 mcr &= ~TEGRA_UART_MCR_RTS_EN;
185 if (mcr != tup->mcr_shadow) {
186 tegra_uart_write(tup, mcr, UART_MCR);
187 tup->mcr_shadow = mcr;
191 static void set_dtr(struct tegra_uart_port *tup, bool active)
195 mcr = tup->mcr_shadow;
199 mcr &= ~UART_MCR_DTR;
200 if (mcr != tup->mcr_shadow) {
201 tegra_uart_write(tup, mcr, UART_MCR);
202 tup->mcr_shadow = mcr;
206 static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
208 struct tegra_uart_port *tup = to_tegra_uport(u);
211 tup->rts_active = !!(mctrl & TIOCM_RTS);
212 set_rts(tup, tup->rts_active);
214 dtr_enable = !!(mctrl & TIOCM_DTR);
215 set_dtr(tup, dtr_enable);
218 static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
220 struct tegra_uart_port *tup = to_tegra_uport(u);
223 lcr = tup->lcr_shadow;
227 lcr &= ~UART_LCR_SBC;
228 tegra_uart_write(tup, lcr, UART_LCR);
229 tup->lcr_shadow = lcr;
233 * tegra_uart_wait_cycle_time: Wait for N UART clock periods
235 * @tup: Tegra serial port data structure.
236 * @cycles: Number of clock periods to wait.
238 * Tegra UARTs are clocked at 16X the baud/bit rate and hence the UART
239 * clock speed is 16X the current baud rate.
241 static void tegra_uart_wait_cycle_time(struct tegra_uart_port *tup,
244 if (tup->current_baud)
245 udelay(DIV_ROUND_UP(cycles * 1000000, tup->current_baud * 16));
248 /* Wait for a symbol-time. */
249 static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
252 if (tup->current_baud)
253 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
257 static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
259 unsigned long fcr = tup->fcr_shadow;
261 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
262 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
263 tegra_uart_write(tup, fcr, UART_FCR);
265 fcr &= ~UART_FCR_ENABLE_FIFO;
266 tegra_uart_write(tup, fcr, UART_FCR);
268 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
269 tegra_uart_write(tup, fcr, UART_FCR);
270 fcr |= UART_FCR_ENABLE_FIFO;
271 tegra_uart_write(tup, fcr, UART_FCR);
274 /* Dummy read to ensure the write is posted */
275 tegra_uart_read(tup, UART_SCR);
278 * For all tegra devices (up to t210), there is a hardware issue that
279 * requires software to wait for 32 UART clock periods for the flush
280 * to propagate, otherwise data could be lost.
282 tegra_uart_wait_cycle_time(tup, 32);
285 static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
288 unsigned int divisor;
292 if (tup->current_baud == baud)
295 if (tup->cdata->support_clk_src_div) {
297 ret = clk_set_rate(tup->uart_clk, rate);
299 dev_err(tup->uport.dev,
300 "clk_set_rate() failed for rate %lu\n", rate);
305 rate = clk_get_rate(tup->uart_clk);
306 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
309 lcr = tup->lcr_shadow;
310 lcr |= UART_LCR_DLAB;
311 tegra_uart_write(tup, lcr, UART_LCR);
313 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
314 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
316 lcr &= ~UART_LCR_DLAB;
317 tegra_uart_write(tup, lcr, UART_LCR);
319 /* Dummy read to ensure the write is posted */
320 tegra_uart_read(tup, UART_SCR);
322 tup->current_baud = baud;
324 /* wait two character intervals at new rate */
325 tegra_uart_wait_sym_time(tup, 2);
329 static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
332 char flag = TTY_NORMAL;
334 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
335 if (lsr & UART_LSR_OE) {
338 tup->uport.icount.overrun++;
339 dev_err(tup->uport.dev, "Got overrun errors\n");
340 } else if (lsr & UART_LSR_PE) {
343 tup->uport.icount.parity++;
344 dev_err(tup->uport.dev, "Got Parity errors\n");
345 } else if (lsr & UART_LSR_FE) {
347 tup->uport.icount.frame++;
348 dev_err(tup->uport.dev, "Got frame errors\n");
349 } else if (lsr & UART_LSR_BI) {
350 dev_err(tup->uport.dev, "Got Break\n");
351 tup->uport.icount.brk++;
352 /* If FIFO read error without any data, reset Rx FIFO */
353 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
354 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
360 static int tegra_uart_request_port(struct uart_port *u)
365 static void tegra_uart_release_port(struct uart_port *u)
367 /* Nothing to do here */
370 static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
372 struct circ_buf *xmit = &tup->uport.state->xmit;
375 for (i = 0; i < max_bytes; i++) {
376 BUG_ON(uart_circ_empty(xmit));
377 if (tup->cdata->tx_fifo_full_status) {
378 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
379 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
382 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
383 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
384 tup->uport.icount.tx++;
388 static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
391 if (bytes > TEGRA_UART_MIN_DMA)
392 bytes = TEGRA_UART_MIN_DMA;
394 tup->tx_in_progress = TEGRA_UART_TX_PIO;
395 tup->tx_bytes = bytes;
396 tup->ier_shadow |= UART_IER_THRI;
397 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
400 static void tegra_uart_tx_dma_complete(void *args)
402 struct tegra_uart_port *tup = args;
403 struct circ_buf *xmit = &tup->uport.state->xmit;
404 struct dma_tx_state state;
408 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
409 count = tup->tx_bytes_requested - state.residue;
410 async_tx_ack(tup->tx_dma_desc);
411 spin_lock_irqsave(&tup->uport.lock, flags);
412 uart_xmit_advance(&tup->uport, count);
413 tup->tx_in_progress = 0;
414 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
415 uart_write_wakeup(&tup->uport);
416 tegra_uart_start_next_tx(tup);
417 spin_unlock_irqrestore(&tup->uport.lock, flags);
420 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
423 struct circ_buf *xmit = &tup->uport.state->xmit;
424 dma_addr_t tx_phys_addr;
426 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
427 UART_XMIT_SIZE, DMA_TO_DEVICE);
429 tup->tx_bytes = count & ~(0xF);
430 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
431 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
432 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
434 if (!tup->tx_dma_desc) {
435 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
439 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
440 tup->tx_dma_desc->callback_param = tup;
441 tup->tx_in_progress = TEGRA_UART_TX_DMA;
442 tup->tx_bytes_requested = tup->tx_bytes;
443 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
444 dma_async_issue_pending(tup->tx_dma_chan);
448 static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
452 struct circ_buf *xmit = &tup->uport.state->xmit;
454 tail = (unsigned long)&xmit->buf[xmit->tail];
455 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
459 if (count < TEGRA_UART_MIN_DMA)
460 tegra_uart_start_pio_tx(tup, count);
461 else if (BYTES_TO_ALIGN(tail) > 0)
462 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
464 tegra_uart_start_tx_dma(tup, count);
467 /* Called by serial core driver with u->lock taken. */
468 static void tegra_uart_start_tx(struct uart_port *u)
470 struct tegra_uart_port *tup = to_tegra_uport(u);
471 struct circ_buf *xmit = &u->state->xmit;
473 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
474 tegra_uart_start_next_tx(tup);
477 static unsigned int tegra_uart_tx_empty(struct uart_port *u)
479 struct tegra_uart_port *tup = to_tegra_uport(u);
480 unsigned int ret = 0;
483 spin_lock_irqsave(&u->lock, flags);
484 if (!tup->tx_in_progress) {
485 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
486 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
489 spin_unlock_irqrestore(&u->lock, flags);
493 static void tegra_uart_stop_tx(struct uart_port *u)
495 struct tegra_uart_port *tup = to_tegra_uport(u);
496 struct dma_tx_state state;
499 if (tup->tx_in_progress != TEGRA_UART_TX_DMA)
502 dmaengine_terminate_all(tup->tx_dma_chan);
503 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
504 count = tup->tx_bytes_requested - state.residue;
505 async_tx_ack(tup->tx_dma_desc);
506 uart_xmit_advance(&tup->uport, count);
507 tup->tx_in_progress = 0;
510 static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
512 struct circ_buf *xmit = &tup->uport.state->xmit;
514 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
515 tup->tx_in_progress = 0;
516 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
517 uart_write_wakeup(&tup->uport);
518 tegra_uart_start_next_tx(tup);
521 static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
522 struct tty_port *tty)
525 char flag = TTY_NORMAL;
526 unsigned long lsr = 0;
529 lsr = tegra_uart_read(tup, UART_LSR);
530 if (!(lsr & UART_LSR_DR))
533 flag = tegra_uart_decode_rx_error(tup, lsr);
534 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
535 tup->uport.icount.rx++;
537 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
538 tty_insert_flip_char(tty, ch, flag);
542 static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
543 struct tty_port *tty,
548 /* If count is zero, then there is no data to be copied */
552 tup->uport.icount.rx += count;
554 dev_err(tup->uport.dev, "No tty port\n");
557 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
558 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
559 copied = tty_insert_flip_string(tty,
560 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
561 if (copied != count) {
563 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
565 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
566 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
569 static void tegra_uart_rx_buffer_push(struct tegra_uart_port *tup,
570 unsigned int residue)
572 struct tty_port *port = &tup->uport.state->port;
573 struct tty_struct *tty = tty_port_tty_get(port);
576 async_tx_ack(tup->rx_dma_desc);
577 count = tup->rx_bytes_requested - residue;
579 /* If we are here, DMA is stopped */
580 tegra_uart_copy_rx_to_tty(tup, port, count);
582 tegra_uart_handle_rx_pio(tup, port);
584 tty_flip_buffer_push(port);
589 static void tegra_uart_rx_dma_complete(void *args)
591 struct tegra_uart_port *tup = args;
592 struct uart_port *u = &tup->uport;
594 struct dma_tx_state state;
595 enum dma_status status;
597 spin_lock_irqsave(&u->lock, flags);
599 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
601 if (status == DMA_IN_PROGRESS) {
602 dev_dbg(tup->uport.dev, "RX DMA is in progress\n");
606 /* Deactivate flow control to stop sender */
610 tegra_uart_rx_buffer_push(tup, 0);
611 tegra_uart_start_rx_dma(tup);
613 /* Activate flow control to start transfer */
618 spin_unlock_irqrestore(&u->lock, flags);
621 static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
623 struct dma_tx_state state;
625 /* Deactivate flow control to stop sender */
629 dmaengine_terminate_all(tup->rx_dma_chan);
630 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
631 tegra_uart_rx_buffer_push(tup, state.residue);
632 tegra_uart_start_rx_dma(tup);
638 static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
640 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
642 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
643 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
645 if (!tup->rx_dma_desc) {
646 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
650 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
651 tup->rx_dma_desc->callback_param = tup;
652 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
653 count, DMA_TO_DEVICE);
654 tup->rx_bytes_requested = count;
655 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
656 dma_async_issue_pending(tup->rx_dma_chan);
660 static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
662 struct tegra_uart_port *tup = to_tegra_uport(u);
665 msr = tegra_uart_read(tup, UART_MSR);
666 if (!(msr & UART_MSR_ANY_DELTA))
669 if (msr & UART_MSR_TERI)
670 tup->uport.icount.rng++;
671 if (msr & UART_MSR_DDSR)
672 tup->uport.icount.dsr++;
673 /* We may only get DDCD when HW init and reset */
674 if (msr & UART_MSR_DDCD)
675 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
676 /* Will start/stop_tx accordingly */
677 if (msr & UART_MSR_DCTS)
678 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
681 static irqreturn_t tegra_uart_isr(int irq, void *data)
683 struct tegra_uart_port *tup = data;
684 struct uart_port *u = &tup->uport;
687 bool is_rx_int = false;
690 spin_lock_irqsave(&u->lock, flags);
692 iir = tegra_uart_read(tup, UART_IIR);
693 if (iir & UART_IIR_NO_INT) {
695 tegra_uart_handle_rx_dma(tup);
696 if (tup->rx_in_progress) {
697 ier = tup->ier_shadow;
698 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
699 TEGRA_UART_IER_EORD);
700 tup->ier_shadow = ier;
701 tegra_uart_write(tup, ier, UART_IER);
704 spin_unlock_irqrestore(&u->lock, flags);
708 switch ((iir >> 1) & 0x7) {
709 case 0: /* Modem signal change interrupt */
710 tegra_uart_handle_modem_signal_change(u);
713 case 1: /* Transmit interrupt only triggered when using PIO */
714 tup->ier_shadow &= ~UART_IER_THRI;
715 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
716 tegra_uart_handle_tx_pio(tup);
719 case 4: /* End of data */
720 case 6: /* Rx timeout */
721 case 2: /* Receive */
724 /* Disable Rx interrupts */
725 ier = tup->ier_shadow;
727 tegra_uart_write(tup, ier, UART_IER);
728 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
729 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
730 tup->ier_shadow = ier;
731 tegra_uart_write(tup, ier, UART_IER);
735 case 3: /* Receive error */
736 tegra_uart_decode_rx_error(tup,
737 tegra_uart_read(tup, UART_LSR));
740 case 5: /* break nothing to handle */
741 case 7: /* break nothing to handle */
747 static void tegra_uart_stop_rx(struct uart_port *u)
749 struct tegra_uart_port *tup = to_tegra_uport(u);
750 struct dma_tx_state state;
756 if (!tup->rx_in_progress)
759 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
761 ier = tup->ier_shadow;
762 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
763 TEGRA_UART_IER_EORD);
764 tup->ier_shadow = ier;
765 tegra_uart_write(tup, ier, UART_IER);
766 tup->rx_in_progress = 0;
767 dmaengine_terminate_all(tup->rx_dma_chan);
768 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
769 tegra_uart_rx_buffer_push(tup, state.residue);
772 static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
775 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
776 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
777 unsigned long wait_time;
782 /* Disable interrupts */
783 tegra_uart_write(tup, 0, UART_IER);
785 lsr = tegra_uart_read(tup, UART_LSR);
786 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
787 msr = tegra_uart_read(tup, UART_MSR);
788 mcr = tegra_uart_read(tup, UART_MCR);
789 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
790 dev_err(tup->uport.dev,
791 "Tx Fifo not empty, CTS disabled, waiting\n");
793 /* Wait for Tx fifo to be empty */
794 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
795 wait_time = min(fifo_empty_time, 100lu);
797 fifo_empty_time -= wait_time;
798 if (!fifo_empty_time) {
799 msr = tegra_uart_read(tup, UART_MSR);
800 mcr = tegra_uart_read(tup, UART_MCR);
801 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
802 (msr & UART_MSR_CTS))
803 dev_err(tup->uport.dev,
804 "Slave not ready\n");
807 lsr = tegra_uart_read(tup, UART_LSR);
811 spin_lock_irqsave(&tup->uport.lock, flags);
812 /* Reset the Rx and Tx FIFOs */
813 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
814 tup->current_baud = 0;
815 spin_unlock_irqrestore(&tup->uport.lock, flags);
817 clk_disable_unprepare(tup->uart_clk);
820 static int tegra_uart_hw_init(struct tegra_uart_port *tup)
828 tup->current_baud = 0;
830 clk_prepare_enable(tup->uart_clk);
832 /* Reset the UART controller to clear all previous status.*/
833 reset_control_assert(tup->rst);
835 reset_control_deassert(tup->rst);
837 tup->rx_in_progress = 0;
838 tup->tx_in_progress = 0;
841 * Set the trigger level
845 * For receive, this will interrupt the CPU after that many number of
846 * bytes are received, for the remaining bytes the receive timeout
847 * interrupt is received. Rx high watermark is set to 4.
849 * For transmit, if the trasnmit interrupt is enabled, this will
850 * interrupt the CPU when the number of entries in the FIFO reaches the
851 * low watermark. Tx low watermark is set to 16 bytes.
855 * Set the Tx trigger to 16. This should match the DMA burst size that
856 * programmed in the DMA registers.
858 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
859 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
860 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
861 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
863 /* Dummy read to ensure the write is posted */
864 tegra_uart_read(tup, UART_SCR);
867 * For all tegra devices (up to t210), there is a hardware issue that
868 * requires software to wait for 3 UART clock periods after enabling
869 * the TX fifo, otherwise data could be lost.
871 tegra_uart_wait_cycle_time(tup, 3);
874 * Initialize the UART with default configuration
875 * (115200, N, 8, 1) so that the receive DMA buffer may be
878 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
879 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
880 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
881 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
883 ret = tegra_uart_start_rx_dma(tup);
885 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
888 tup->rx_in_progress = 1;
891 * Enable IE_RXS for the receive status interrupts like line errros.
892 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
894 * If using DMA mode, enable EORD instead of receive interrupt which
895 * will interrupt after the UART is done with the receive instead of
896 * the interrupt when the FIFO "threshold" is reached.
898 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
899 * the DATA is sitting in the FIFO and couldn't be transferred to the
900 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
901 * triggered when there is a pause of the incomming data stream for 4
904 * For pauses in the data which is not aligned to 4 bytes, we get
905 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
908 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
909 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
913 static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
917 dmaengine_terminate_all(tup->rx_dma_chan);
918 dma_release_channel(tup->rx_dma_chan);
919 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
920 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
921 tup->rx_dma_chan = NULL;
922 tup->rx_dma_buf_phys = 0;
923 tup->rx_dma_buf_virt = NULL;
925 dmaengine_terminate_all(tup->tx_dma_chan);
926 dma_release_channel(tup->tx_dma_chan);
927 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
928 UART_XMIT_SIZE, DMA_TO_DEVICE);
929 tup->tx_dma_chan = NULL;
930 tup->tx_dma_buf_phys = 0;
931 tup->tx_dma_buf_virt = NULL;
935 static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
938 struct dma_chan *dma_chan;
939 unsigned char *dma_buf;
942 struct dma_slave_config dma_sconfig;
944 dma_chan = dma_request_slave_channel_reason(tup->uport.dev,
945 dma_to_memory ? "rx" : "tx");
946 if (IS_ERR(dma_chan)) {
947 ret = PTR_ERR(dma_chan);
948 dev_err(tup->uport.dev,
949 "DMA channel alloc failed: %d\n", ret);
954 dma_buf = dma_alloc_coherent(tup->uport.dev,
955 TEGRA_UART_RX_DMA_BUFFER_SIZE,
956 &dma_phys, GFP_KERNEL);
958 dev_err(tup->uport.dev,
959 "Not able to allocate the dma buffer\n");
960 dma_release_channel(dma_chan);
963 dma_sconfig.src_addr = tup->uport.mapbase;
964 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
965 dma_sconfig.src_maxburst = 4;
966 tup->rx_dma_chan = dma_chan;
967 tup->rx_dma_buf_virt = dma_buf;
968 tup->rx_dma_buf_phys = dma_phys;
970 dma_phys = dma_map_single(tup->uport.dev,
971 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
973 if (dma_mapping_error(tup->uport.dev, dma_phys)) {
974 dev_err(tup->uport.dev, "dma_map_single tx failed\n");
975 dma_release_channel(dma_chan);
978 dma_buf = tup->uport.state->xmit.buf;
979 dma_sconfig.dst_addr = tup->uport.mapbase;
980 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
981 dma_sconfig.dst_maxburst = 16;
982 tup->tx_dma_chan = dma_chan;
983 tup->tx_dma_buf_virt = dma_buf;
984 tup->tx_dma_buf_phys = dma_phys;
987 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
989 dev_err(tup->uport.dev,
990 "Dma slave config failed, err = %d\n", ret);
991 tegra_uart_dma_channel_free(tup, dma_to_memory);
998 static int tegra_uart_startup(struct uart_port *u)
1000 struct tegra_uart_port *tup = to_tegra_uport(u);
1003 ret = tegra_uart_dma_channel_allocate(tup, false);
1005 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
1009 ret = tegra_uart_dma_channel_allocate(tup, true);
1011 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1015 ret = tegra_uart_hw_init(tup);
1017 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1021 ret = request_irq(u->irq, tegra_uart_isr, 0,
1022 dev_name(u->dev), tup);
1024 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1030 tegra_uart_dma_channel_free(tup, true);
1032 tegra_uart_dma_channel_free(tup, false);
1037 * Flush any TX data submitted for DMA and PIO. Called when the
1038 * TX circular buffer is reset.
1040 static void tegra_uart_flush_buffer(struct uart_port *u)
1042 struct tegra_uart_port *tup = to_tegra_uport(u);
1045 if (tup->tx_dma_chan)
1046 dmaengine_terminate_all(tup->tx_dma_chan);
1049 static void tegra_uart_shutdown(struct uart_port *u)
1051 struct tegra_uart_port *tup = to_tegra_uport(u);
1053 tegra_uart_hw_deinit(tup);
1055 tup->rx_in_progress = 0;
1056 tup->tx_in_progress = 0;
1058 tegra_uart_dma_channel_free(tup, true);
1059 tegra_uart_dma_channel_free(tup, false);
1060 free_irq(u->irq, tup);
1063 static void tegra_uart_enable_ms(struct uart_port *u)
1065 struct tegra_uart_port *tup = to_tegra_uport(u);
1067 if (tup->enable_modem_interrupt) {
1068 tup->ier_shadow |= UART_IER_MSI;
1069 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1073 static void tegra_uart_set_termios(struct uart_port *u,
1074 struct ktermios *termios, struct ktermios *oldtermios)
1076 struct tegra_uart_port *tup = to_tegra_uport(u);
1078 unsigned long flags;
1081 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1082 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1083 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1086 spin_lock_irqsave(&u->lock, flags);
1088 /* Changing configuration, it is safe to stop any rx now */
1089 if (tup->rts_active)
1090 set_rts(tup, false);
1092 /* Clear all interrupts as configuration is going to be change */
1093 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1094 tegra_uart_read(tup, UART_IER);
1095 tegra_uart_write(tup, 0, UART_IER);
1096 tegra_uart_read(tup, UART_IER);
1099 lcr = tup->lcr_shadow;
1100 lcr &= ~UART_LCR_PARITY;
1102 /* CMSPAR isn't supported by this driver */
1103 termios->c_cflag &= ~CMSPAR;
1105 if ((termios->c_cflag & PARENB) == PARENB) {
1107 if (termios->c_cflag & PARODD) {
1108 lcr |= UART_LCR_PARITY;
1109 lcr &= ~UART_LCR_EPAR;
1110 lcr &= ~UART_LCR_SPAR;
1112 lcr |= UART_LCR_PARITY;
1113 lcr |= UART_LCR_EPAR;
1114 lcr &= ~UART_LCR_SPAR;
1118 lcr &= ~UART_LCR_WLEN8;
1119 switch (termios->c_cflag & CSIZE) {
1121 lcr |= UART_LCR_WLEN5;
1125 lcr |= UART_LCR_WLEN6;
1129 lcr |= UART_LCR_WLEN7;
1133 lcr |= UART_LCR_WLEN8;
1139 if (termios->c_cflag & CSTOPB) {
1140 lcr |= UART_LCR_STOP;
1143 lcr &= ~UART_LCR_STOP;
1147 tegra_uart_write(tup, lcr, UART_LCR);
1148 tup->lcr_shadow = lcr;
1149 tup->symb_bit = symb_bit;
1152 baud = uart_get_baud_rate(u, termios, oldtermios,
1153 parent_clk_rate/max_divider,
1154 parent_clk_rate/16);
1155 spin_unlock_irqrestore(&u->lock, flags);
1156 tegra_set_baudrate(tup, baud);
1157 if (tty_termios_baud_rate(termios))
1158 tty_termios_encode_baud_rate(termios, baud, baud);
1159 spin_lock_irqsave(&u->lock, flags);
1162 if (termios->c_cflag & CRTSCTS) {
1163 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1164 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1165 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1166 /* if top layer has asked to set rts active then do so here */
1167 if (tup->rts_active)
1170 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1171 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1172 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1175 /* update the port timeout based on new settings */
1176 uart_update_timeout(u, termios->c_cflag, baud);
1178 /* Make sure all write has completed */
1179 tegra_uart_read(tup, UART_IER);
1181 /* Reenable interrupt */
1182 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1183 tegra_uart_read(tup, UART_IER);
1185 spin_unlock_irqrestore(&u->lock, flags);
1188 static const char *tegra_uart_type(struct uart_port *u)
1190 return TEGRA_UART_TYPE;
1193 static struct uart_ops tegra_uart_ops = {
1194 .tx_empty = tegra_uart_tx_empty,
1195 .set_mctrl = tegra_uart_set_mctrl,
1196 .get_mctrl = tegra_uart_get_mctrl,
1197 .stop_tx = tegra_uart_stop_tx,
1198 .start_tx = tegra_uart_start_tx,
1199 .stop_rx = tegra_uart_stop_rx,
1200 .flush_buffer = tegra_uart_flush_buffer,
1201 .enable_ms = tegra_uart_enable_ms,
1202 .break_ctl = tegra_uart_break_ctl,
1203 .startup = tegra_uart_startup,
1204 .shutdown = tegra_uart_shutdown,
1205 .set_termios = tegra_uart_set_termios,
1206 .type = tegra_uart_type,
1207 .request_port = tegra_uart_request_port,
1208 .release_port = tegra_uart_release_port,
1211 static struct uart_driver tegra_uart_driver = {
1212 .owner = THIS_MODULE,
1213 .driver_name = "tegra_hsuart",
1214 .dev_name = "ttyTHS",
1216 .nr = TEGRA_UART_MAXIMUM,
1219 static int tegra_uart_parse_dt(struct platform_device *pdev,
1220 struct tegra_uart_port *tup)
1222 struct device_node *np = pdev->dev.of_node;
1225 port = of_alias_get_id(np, "serial");
1227 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1230 tup->uport.line = port;
1232 tup->enable_modem_interrupt = of_property_read_bool(np,
1233 "nvidia,enable-modem-interrupt");
1237 static struct tegra_uart_chip_data tegra20_uart_chip_data = {
1238 .tx_fifo_full_status = false,
1239 .allow_txfifo_reset_fifo_mode = true,
1240 .support_clk_src_div = false,
1243 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
1244 .tx_fifo_full_status = true,
1245 .allow_txfifo_reset_fifo_mode = false,
1246 .support_clk_src_div = true,
1249 static const struct of_device_id tegra_uart_of_match[] = {
1251 .compatible = "nvidia,tegra30-hsuart",
1252 .data = &tegra30_uart_chip_data,
1254 .compatible = "nvidia,tegra20-hsuart",
1255 .data = &tegra20_uart_chip_data,
1259 MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1261 static int tegra_uart_probe(struct platform_device *pdev)
1263 struct tegra_uart_port *tup;
1264 struct uart_port *u;
1265 struct resource *resource;
1267 const struct tegra_uart_chip_data *cdata;
1268 const struct of_device_id *match;
1270 match = of_match_device(tegra_uart_of_match, &pdev->dev);
1272 dev_err(&pdev->dev, "Error: No device match found\n");
1275 cdata = match->data;
1277 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1279 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1283 ret = tegra_uart_parse_dt(pdev, tup);
1288 u->dev = &pdev->dev;
1289 u->ops = &tegra_uart_ops;
1290 u->type = PORT_TEGRA;
1294 platform_set_drvdata(pdev, tup);
1295 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 dev_err(&pdev->dev, "No IO memory resource\n");
1301 u->mapbase = resource->start;
1302 u->membase = devm_ioremap_resource(&pdev->dev, resource);
1303 if (IS_ERR(u->membase))
1304 return PTR_ERR(u->membase);
1306 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1307 if (IS_ERR(tup->uart_clk)) {
1308 dev_err(&pdev->dev, "Couldn't get the clock\n");
1309 return PTR_ERR(tup->uart_clk);
1312 tup->rst = devm_reset_control_get(&pdev->dev, "serial");
1313 if (IS_ERR(tup->rst)) {
1314 dev_err(&pdev->dev, "Couldn't get the reset\n");
1315 return PTR_ERR(tup->rst);
1318 u->iotype = UPIO_MEM32;
1319 ret = platform_get_irq(pdev, 0);
1321 dev_err(&pdev->dev, "Couldn't get IRQ\n");
1326 ret = uart_add_one_port(&tegra_uart_driver, u);
1328 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1334 static int tegra_uart_remove(struct platform_device *pdev)
1336 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1337 struct uart_port *u = &tup->uport;
1339 uart_remove_one_port(&tegra_uart_driver, u);
1343 #ifdef CONFIG_PM_SLEEP
1344 static int tegra_uart_suspend(struct device *dev)
1346 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1347 struct uart_port *u = &tup->uport;
1349 return uart_suspend_port(&tegra_uart_driver, u);
1352 static int tegra_uart_resume(struct device *dev)
1354 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1355 struct uart_port *u = &tup->uport;
1357 return uart_resume_port(&tegra_uart_driver, u);
1361 static const struct dev_pm_ops tegra_uart_pm_ops = {
1362 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1365 static struct platform_driver tegra_uart_platform_driver = {
1366 .probe = tegra_uart_probe,
1367 .remove = tegra_uart_remove,
1369 .name = "serial-tegra",
1370 .of_match_table = tegra_uart_of_match,
1371 .pm = &tegra_uart_pm_ops,
1375 static int __init tegra_uart_init(void)
1379 ret = uart_register_driver(&tegra_uart_driver);
1381 pr_err("Could not register %s driver\n",
1382 tegra_uart_driver.driver_name);
1386 ret = platform_driver_register(&tegra_uart_platform_driver);
1388 pr_err("Uart platform driver register failed, e = %d\n", ret);
1389 uart_unregister_driver(&tegra_uart_driver);
1395 static void __exit tegra_uart_exit(void)
1397 pr_info("Unloading tegra uart driver\n");
1398 platform_driver_unregister(&tegra_uart_platform_driver);
1399 uart_unregister_driver(&tegra_uart_driver);
1402 module_init(tegra_uart_init);
1403 module_exit(tegra_uart_exit);
1405 MODULE_ALIAS("platform:serial-tegra");
1406 MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1407 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1408 MODULE_LICENSE("GPL v2");