drivers/tty/serial/samsung_tty.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7  */
   8
   9 /* Note on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22  */
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/ioport.h>
  29 #include <linux/io.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/init.h>
  32 #include <linux/sysrq.h>
  33 #include <linux/console.h>
  34 #include <linux/tty.h>
  35 #include <linux/tty_flip.h>
  36 #include <linux/serial_core.h>
  37 #include <linux/serial.h>
  38 #include <linux/serial_s3c.h>
  39 #include <linux/delay.h>
  40 #include <linux/clk.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/of.h>
  43 #include <asm/irq.h>
  44
  45 /* UART name and device definitions */
  46
  47 #define S3C24XX_SERIAL_NAME     "ttySAC"
  48 #define S3C24XX_SERIAL_MAJOR    204
  49 #define S3C24XX_SERIAL_MINOR    64
  50
  51 #define S3C24XX_TX_PIO                  1
  52 #define S3C24XX_TX_DMA                  2
  53 #define S3C24XX_RX_PIO                  1
  54 #define S3C24XX_RX_DMA                  2
  55
  56 /* flag to ignore all characters coming in */
  57 #define RXSTAT_DUMMY_READ (0x10000000)
  58
  59 enum s3c24xx_port_type {
  60         TYPE_S3C24XX,
  61         TYPE_S3C6400,
  62         TYPE_APPLE_S5L,
  63 };
  64
  65 struct s3c24xx_uart_info {
  66         const char              *name;
  67         enum s3c24xx_port_type  type;
  68         unsigned int            port_type;
  69         unsigned int            fifosize;
  70         unsigned long           rx_fifomask;
  71         unsigned long           rx_fifoshift;
  72         unsigned long           rx_fifofull;
  73         unsigned long           tx_fifomask;
  74         unsigned long           tx_fifoshift;
  75         unsigned long           tx_fifofull;
  76         unsigned int            def_clk_sel;
  77         unsigned long           num_clks;
  78         unsigned long           clksel_mask;
  79         unsigned long           clksel_shift;
  80         unsigned long           ucon_mask;
  81
  82         /* uart port features */
  83
  84         unsigned int            has_divslot:1;
  85 };
  86
  87 struct s3c24xx_serial_drv_data {
  88         const struct s3c24xx_uart_info  info;
  89         const struct s3c2410_uartcfg    def_cfg;
  90         const unsigned int              fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
  91 };
  92
  93 struct s3c24xx_uart_dma {
  94         unsigned int                    rx_chan_id;
  95         unsigned int                    tx_chan_id;
  96
  97         struct dma_slave_config         rx_conf;
  98         struct dma_slave_config         tx_conf;
  99
 100         struct dma_chan                 *rx_chan;
 101         struct dma_chan                 *tx_chan;
 102
 103         dma_addr_t                      rx_addr;
 104         dma_addr_t                      tx_addr;
 105
 106         dma_cookie_t                    rx_cookie;
 107         dma_cookie_t                    tx_cookie;
 108
 109         char                            *rx_buf;
 110
 111         dma_addr_t                      tx_transfer_addr;
 112
 113         size_t                          rx_size;
 114         size_t                          tx_size;
 115
 116         struct dma_async_tx_descriptor  *tx_desc;
 117         struct dma_async_tx_descriptor  *rx_desc;
 118
 119         int                             tx_bytes_requested;
 120         int                             rx_bytes_requested;
 121 };
 122
 123 struct s3c24xx_uart_port {
 124         unsigned char                   rx_claimed;
 125         unsigned char                   tx_claimed;
 126         unsigned char                   rx_enabled;
 127         unsigned char                   tx_enabled;
 128         unsigned int                    pm_level;
 129         unsigned long                   baudclk_rate;
 130         unsigned int                    min_dma_size;
 131
 132         unsigned int                    rx_irq;
 133         unsigned int                    tx_irq;
 134
 135         unsigned int                    tx_in_progress;
 136         unsigned int                    tx_mode;
 137         unsigned int                    rx_mode;
 138
 139         const struct s3c24xx_uart_info  *info;
 140         struct clk                      *clk;
 141         struct clk                      *baudclk;
 142         struct uart_port                port;
 143         const struct s3c24xx_serial_drv_data    *drv_data;
 144
 145         /* reference to platform data */
 146         const struct s3c2410_uartcfg    *cfg;
 147
 148         struct s3c24xx_uart_dma         *dma;
 149
 150 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 151         struct notifier_block           freq_transition;
 152 #endif
 153 };
 154
 155 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
 156
 157 /* conversion functions */
 158
 159 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 160
 161 /* register access controls */
 162
 163 #define portaddr(port, reg) ((port)->membase + (reg))
 164 #define portaddrl(port, reg) \
 165         ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 166
 167 static u32 rd_reg(const struct uart_port *port, u32 reg)
 168 {
 169         switch (port->iotype) {
 170         case UPIO_MEM:
 171                 return readb_relaxed(portaddr(port, reg));
 172         case UPIO_MEM32:
 173                 return readl_relaxed(portaddr(port, reg));
 174         default:
 175                 return 0;
 176         }
 177         return 0;
 178 }
 179
 180 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 181
 182 static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
 183 {
 184         switch (port->iotype) {
 185         case UPIO_MEM:
 186                 writeb_relaxed(val, portaddr(port, reg));
 187                 break;
 188         case UPIO_MEM32:
 189                 writel_relaxed(val, portaddr(port, reg));
 190                 break;
 191         }
 192 }
 193
 194 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 195
 196 /* Byte-order aware bit setting/clearing functions. */
 197
 198 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
 199                                    unsigned int reg)
 200 {
 201         unsigned long flags;
 202         u32 val;
 203
 204         local_irq_save(flags);
 205         val = rd_regl(port, reg);
 206         val |= (1 << idx);
 207         wr_regl(port, reg, val);
 208         local_irq_restore(flags);
 209 }
 210
 211 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
 212                                      unsigned int reg)
 213 {
 214         unsigned long flags;
 215         u32 val;
 216
 217         local_irq_save(flags);
 218         val = rd_regl(port, reg);
 219         val &= ~(1 << idx);
 220         wr_regl(port, reg, val);
 221         local_irq_restore(flags);
 222 }
 223
 224 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 225 {
 226         return container_of(port, struct s3c24xx_uart_port, port);
 227 }
 228
 229 /* translate a port to the device name */
 230
 231 static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
 232 {
 233         return to_platform_device(port->dev)->name;
 234 }
 235
 236 static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
 237 {
 238         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 239 }
 240
 241 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 242 {
 243         struct s3c24xx_uart_port *ourport = to_ourport(port);
 244         unsigned long flags;
 245         unsigned int ucon, ufcon;
 246         int count = 10000;
 247
 248         spin_lock_irqsave(&port->lock, flags);
 249
 250         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 251                 udelay(100);
 252
 253         ufcon = rd_regl(port, S3C2410_UFCON);
 254         ufcon |= S3C2410_UFCON_RESETRX;
 255         wr_regl(port, S3C2410_UFCON, ufcon);
 256
 257         ucon = rd_regl(port, S3C2410_UCON);
 258         ucon |= S3C2410_UCON_RXIRQMODE;
 259         wr_regl(port, S3C2410_UCON, ucon);
 260
 261         ourport->rx_enabled = 1;
 262         spin_unlock_irqrestore(&port->lock, flags);
 263 }
 264
 265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 266 {
 267         struct s3c24xx_uart_port *ourport = to_ourport(port);
 268         unsigned long flags;
 269         unsigned int ucon;
 270
 271         spin_lock_irqsave(&port->lock, flags);
 272
 273         ucon = rd_regl(port, S3C2410_UCON);
 274         ucon &= ~S3C2410_UCON_RXIRQMODE;
 275         wr_regl(port, S3C2410_UCON, ucon);
 276
 277         ourport->rx_enabled = 0;
 278         spin_unlock_irqrestore(&port->lock, flags);
 279 }
 280
 281 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 282 {
 283         struct s3c24xx_uart_port *ourport = to_ourport(port);
 284         struct s3c24xx_uart_dma *dma = ourport->dma;
 285         struct circ_buf *xmit = &port->state->xmit;
 286         struct dma_tx_state state;
 287         int count;
 288
 289         if (!ourport->tx_enabled)
 290                 return;
 291
 292         switch (ourport->info->type) {
 293         case TYPE_S3C6400:
 294                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 295                 break;
 296         case TYPE_APPLE_S5L:
 297                 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
 298                 break;
 299         default:
 300                 disable_irq_nosync(ourport->tx_irq);
 301                 break;
 302         }
 303
 304         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 305                 dmaengine_pause(dma->tx_chan);
 306                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 307                 dmaengine_terminate_all(dma->tx_chan);
 308                 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 309                                         dma->tx_transfer_addr, dma->tx_size,
 310                                         DMA_TO_DEVICE);
 311                 async_tx_ack(dma->tx_desc);
 312                 count = dma->tx_bytes_requested - state.residue;
 313                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 314                 port->icount.tx += count;
 315         }
 316
 317         ourport->tx_enabled = 0;
 318         ourport->tx_in_progress = 0;
 319
 320         if (port->flags & UPF_CONS_FLOW)
 321                 s3c24xx_serial_rx_enable(port);
 322
 323         ourport->tx_mode = 0;
 324 }
 325
 326 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 327
 328 static void s3c24xx_serial_tx_dma_complete(void *args)
 329 {
 330         struct s3c24xx_uart_port *ourport = args;
 331         struct uart_port *port = &ourport->port;
 332         struct circ_buf *xmit = &port->state->xmit;
 333         struct s3c24xx_uart_dma *dma = ourport->dma;
 334         struct dma_tx_state state;
 335         unsigned long flags;
 336         int count;
 337
 338         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 339         count = dma->tx_bytes_requested - state.residue;
 340         async_tx_ack(dma->tx_desc);
 341
 342         dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 343                                 dma->tx_transfer_addr, dma->tx_size,
 344                                 DMA_TO_DEVICE);
 345
 346         spin_lock_irqsave(&port->lock, flags);
 347
 348         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 349         port->icount.tx += count;
 350         ourport->tx_in_progress = 0;
 351
 352         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 353                 uart_write_wakeup(port);
 354
 355         s3c24xx_serial_start_next_tx(ourport);
 356         spin_unlock_irqrestore(&port->lock, flags);
 357 }
 358
 359 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 360 {
 361         const struct uart_port *port = &ourport->port;
 362         u32 ucon;
 363
 364         /* Mask Tx interrupt */
 365         switch (ourport->info->type) {
 366         case TYPE_S3C6400:
 367                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 368                 break;
 369         case TYPE_APPLE_S5L:
 370                 WARN_ON(1); // No DMA
 371                 break;
 372         default:
 373                 disable_irq_nosync(ourport->tx_irq);
 374                 break;
 375         }
 376
 377         /* Enable tx dma mode */
 378         ucon = rd_regl(port, S3C2410_UCON);
 379         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 380         ucon |= (dma_get_cache_alignment() >= 16) ?
 381                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 382         ucon |= S3C64XX_UCON_TXMODE_DMA;
 383         wr_regl(port,  S3C2410_UCON, ucon);
 384
 385         ourport->tx_mode = S3C24XX_TX_DMA;
 386 }
 387
 388 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 389 {
 390         const struct uart_port *port = &ourport->port;
 391         u32 ucon, ufcon;
 392
 393         /* Set ufcon txtrig */
 394         ourport->tx_in_progress = S3C24XX_TX_PIO;
 395         ufcon = rd_regl(port, S3C2410_UFCON);
 396         wr_regl(port,  S3C2410_UFCON, ufcon);
 397
 398         /* Enable tx pio mode */
 399         ucon = rd_regl(port, S3C2410_UCON);
 400         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 401         ucon |= S3C64XX_UCON_TXMODE_CPU;
 402         wr_regl(port,  S3C2410_UCON, ucon);
 403
 404         /* Unmask Tx interrupt */
 405         switch (ourport->info->type) {
 406         case TYPE_S3C6400:
 407                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 408                                   S3C64XX_UINTM);
 409                 break;
 410         case TYPE_APPLE_S5L:
 411                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
 412                 wr_regl(port, S3C2410_UCON, ucon);
 413                 break;
 414         default:
 415                 enable_irq(ourport->tx_irq);
 416                 break;
 417         }
 418
 419         ourport->tx_mode = S3C24XX_TX_PIO;
 420
 421         /*
 422          * The Apple version only has edge triggered TX IRQs, so we need
 423          * to kick off the process by sending some characters here.
 424          */
 425         if (ourport->info->type == TYPE_APPLE_S5L)
 426                 s3c24xx_serial_tx_chars(ourport);
 427 }
 428
 429 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 430 {
 431         if (ourport->tx_mode != S3C24XX_TX_PIO)
 432                 enable_tx_pio(ourport);
 433 }
 434
 435 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 436                                       unsigned int count)
 437 {
 438         struct uart_port *port = &ourport->port;
 439         struct circ_buf *xmit = &port->state->xmit;
 440         struct s3c24xx_uart_dma *dma = ourport->dma;
 441
 442         if (ourport->tx_mode != S3C24XX_TX_DMA)
 443                 enable_tx_dma(ourport);
 444
 445         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 446         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 447
 448         dma_sync_single_for_device(dma->tx_chan->device->dev,
 449                                    dma->tx_transfer_addr, dma->tx_size,
 450                                    DMA_TO_DEVICE);
 451
 452         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 453                                 dma->tx_transfer_addr, dma->tx_size,
 454                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 455         if (!dma->tx_desc) {
 456                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 457                 return -EIO;
 458         }
 459
 460         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 461         dma->tx_desc->callback_param = ourport;
 462         dma->tx_bytes_requested = dma->tx_size;
 463
 464         ourport->tx_in_progress = S3C24XX_TX_DMA;
 465         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 466         dma_async_issue_pending(dma->tx_chan);
 467         return 0;
 468 }
 469
 470 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 471 {
 472         struct uart_port *port = &ourport->port;
 473         struct circ_buf *xmit = &port->state->xmit;
 474         unsigned long count;
 475
 476         /* Get data size up to the end of buffer */
 477         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 478
 479         if (!count) {
 480                 s3c24xx_serial_stop_tx(port);
 481                 return;
 482         }
 483
 484         if (!ourport->dma || !ourport->dma->tx_chan ||
 485             count < ourport->min_dma_size ||
 486             xmit->tail & (dma_get_cache_alignment() - 1))
 487                 s3c24xx_serial_start_tx_pio(ourport);
 488         else
 489                 s3c24xx_serial_start_tx_dma(ourport, count);
 490 }
 491
 492 static void s3c24xx_serial_start_tx(struct uart_port *port)
 493 {
 494         struct s3c24xx_uart_port *ourport = to_ourport(port);
 495         struct circ_buf *xmit = &port->state->xmit;
 496
 497         if (!ourport->tx_enabled) {
 498                 if (port->flags & UPF_CONS_FLOW)
 499                         s3c24xx_serial_rx_disable(port);
 500
 501                 ourport->tx_enabled = 1;
 502                 if (!ourport->dma || !ourport->dma->tx_chan)
 503                         s3c24xx_serial_start_tx_pio(ourport);
 504         }
 505
 506         if (ourport->dma && ourport->dma->tx_chan) {
 507                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 508                         s3c24xx_serial_start_next_tx(ourport);
 509         }
 510 }
 511
 512 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 513                 struct tty_port *tty, int count)
 514 {
 515         struct s3c24xx_uart_dma *dma = ourport->dma;
 516         int copied;
 517
 518         if (!count)
 519                 return;
 520
 521         dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
 522                                 dma->rx_size, DMA_FROM_DEVICE);
 523
 524         ourport->port.icount.rx += count;
 525         if (!tty) {
 526                 dev_err(ourport->port.dev, "No tty port\n");
 527                 return;
 528         }
 529         copied = tty_insert_flip_string(tty,
 530                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 531         if (copied != count) {
 532                 WARN_ON(1);
 533                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 534         }
 535 }
 536
 537 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 538 {
 539         struct s3c24xx_uart_port *ourport = to_ourport(port);
 540         struct s3c24xx_uart_dma *dma = ourport->dma;
 541         struct tty_port *t = &port->state->port;
 542         struct dma_tx_state state;
 543         enum dma_status dma_status;
 544         unsigned int received;
 545
 546         if (ourport->rx_enabled) {
 547                 dev_dbg(port->dev, "stopping rx\n");
 548                 switch (ourport->info->type) {
 549                 case TYPE_S3C6400:
 550                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 551                                         S3C64XX_UINTM);
 552                         break;
 553                 case TYPE_APPLE_S5L:
 554                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
 555                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
 556                         break;
 557                 default:
 558                         disable_irq_nosync(ourport->rx_irq);
 559                         break;
 560                 }
 561                 ourport->rx_enabled = 0;
 562         }
 563         if (dma && dma->rx_chan) {
 564                 dmaengine_pause(dma->tx_chan);
 565                 dma_status = dmaengine_tx_status(dma->rx_chan,
 566                                 dma->rx_cookie, &state);
 567                 if (dma_status == DMA_IN_PROGRESS ||
 568                         dma_status == DMA_PAUSED) {
 569                         received = dma->rx_bytes_requested - state.residue;
 570                         dmaengine_terminate_all(dma->rx_chan);
 571                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 572                 }
 573         }
 574 }
 575
 576 static inline const struct s3c24xx_uart_info
 577         *s3c24xx_port_to_info(struct uart_port *port)
 578 {
 579         return to_ourport(port)->info;
 580 }
 581
 582 static inline const struct s3c2410_uartcfg
 583         *s3c24xx_port_to_cfg(const struct uart_port *port)
 584 {
 585         const struct s3c24xx_uart_port *ourport;
 586
 587         if (port->dev == NULL)
 588                 return NULL;
 589
 590         ourport = container_of(port, struct s3c24xx_uart_port, port);
 591         return ourport->cfg;
 592 }
 593
 594 static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport,
 595                                      unsigned long ufstat)
 596 {
 597         const struct s3c24xx_uart_info *info = ourport->info;
 598
 599         if (ufstat & info->rx_fifofull)
 600                 return ourport->port.fifosize;
 601
 602         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 603 }
 604
 605 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 606 static void s3c24xx_serial_rx_dma_complete(void *args)
 607 {
 608         struct s3c24xx_uart_port *ourport = args;
 609         struct uart_port *port = &ourport->port;
 610
 611         struct s3c24xx_uart_dma *dma = ourport->dma;
 612         struct tty_port *t = &port->state->port;
 613         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 614
 615         struct dma_tx_state state;
 616         unsigned long flags;
 617         int received;
 618
 619         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 620         received  = dma->rx_bytes_requested - state.residue;
 621         async_tx_ack(dma->rx_desc);
 622
 623         spin_lock_irqsave(&port->lock, flags);
 624
 625         if (received)
 626                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 627
 628         if (tty) {
 629                 tty_flip_buffer_push(t);
 630                 tty_kref_put(tty);
 631         }
 632
 633         s3c64xx_start_rx_dma(ourport);
 634
 635         spin_unlock_irqrestore(&port->lock, flags);
 636 }
 637
 638 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 639 {
 640         struct s3c24xx_uart_dma *dma = ourport->dma;
 641
 642         dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
 643                                    dma->rx_size, DMA_FROM_DEVICE);
 644
 645         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 646                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 647                                 DMA_PREP_INTERRUPT);
 648         if (!dma->rx_desc) {
 649                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 650                 return;
 651         }
 652
 653         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 654         dma->rx_desc->callback_param = ourport;
 655         dma->rx_bytes_requested = dma->rx_size;
 656
 657         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 658         dma_async_issue_pending(dma->rx_chan);
 659 }
 660
 661 /* ? - where has parity gone?? */
 662 #define S3C2410_UERSTAT_PARITY (0x1000)
 663
 664 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 665 {
 666         struct uart_port *port = &ourport->port;
 667         unsigned int ucon;
 668
 669         /* set Rx mode to DMA mode */
 670         ucon = rd_regl(port, S3C2410_UCON);
 671         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 672                         S3C64XX_UCON_TIMEOUT_MASK |
 673                         S3C64XX_UCON_EMPTYINT_EN |
 674                         S3C64XX_UCON_DMASUS_EN |
 675                         S3C64XX_UCON_TIMEOUT_EN |
 676                         S3C64XX_UCON_RXMODE_MASK);
 677         ucon |= S3C64XX_UCON_RXBURST_16 |
 678                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 679                         S3C64XX_UCON_EMPTYINT_EN |
 680                         S3C64XX_UCON_TIMEOUT_EN |
 681                         S3C64XX_UCON_RXMODE_DMA;
 682         wr_regl(port, S3C2410_UCON, ucon);
 683
 684         ourport->rx_mode = S3C24XX_RX_DMA;
 685 }
 686
 687 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 688 {
 689         struct uart_port *port = &ourport->port;
 690         unsigned int ucon;
 691
 692         /* set Rx mode to DMA mode */
 693         ucon = rd_regl(port, S3C2410_UCON);
 694         ucon &= ~S3C64XX_UCON_RXMODE_MASK;
 695         ucon |= S3C64XX_UCON_RXMODE_CPU;
 696
 697         /* Apple types use these bits for IRQ masks */
 698         if (ourport->info->type != TYPE_APPLE_S5L) {
 699                 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 700                                 S3C64XX_UCON_EMPTYINT_EN |
 701                                 S3C64XX_UCON_DMASUS_EN |
 702                                 S3C64XX_UCON_TIMEOUT_EN);
 703                 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 704                                 S3C64XX_UCON_TIMEOUT_EN;
 705         }
 706         wr_regl(port, S3C2410_UCON, ucon);
 707
 708         ourport->rx_mode = S3C24XX_RX_PIO;
 709 }
 710
 711 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 712
 713 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 714 {
 715         unsigned int utrstat, received;
 716         struct s3c24xx_uart_port *ourport = dev_id;
 717         struct uart_port *port = &ourport->port;
 718         struct s3c24xx_uart_dma *dma = ourport->dma;
 719         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 720         struct tty_port *t = &port->state->port;
 721         struct dma_tx_state state;
 722
 723         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 724         rd_regl(port, S3C2410_UFSTAT);
 725
 726         spin_lock(&port->lock);
 727
 728         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 729                 s3c64xx_start_rx_dma(ourport);
 730                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 731                         enable_rx_dma(ourport);
 732                 goto finish;
 733         }
 734
 735         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 736                 dmaengine_pause(dma->rx_chan);
 737                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 738                 dmaengine_terminate_all(dma->rx_chan);
 739                 received = dma->rx_bytes_requested - state.residue;
 740                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 741
 742                 enable_rx_pio(ourport);
 743         }
 744
 745         s3c24xx_serial_rx_drain_fifo(ourport);
 746
 747         if (tty) {
 748                 tty_flip_buffer_push(t);
 749                 tty_kref_put(tty);
 750         }
 751
 752         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 753
 754 finish:
 755         spin_unlock(&port->lock);
 756
 757         return IRQ_HANDLED;
 758 }
 759
 760 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 761 {
 762         struct uart_port *port = &ourport->port;
 763         unsigned int ufcon, ch, flag, ufstat, uerstat;
 764         unsigned int fifocnt = 0;
 765         int max_count = port->fifosize;
 766
 767         while (max_count-- > 0) {
 768                 /*
 769                  * Receive all characters known to be in FIFO
 770                  * before reading FIFO level again
 771                  */
 772                 if (fifocnt == 0) {
 773                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 774                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 775                         if (fifocnt == 0)
 776                                 break;
 777                 }
 778                 fifocnt--;
 779
 780                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 781                 ch = rd_reg(port, S3C2410_URXH);
 782
 783                 if (port->flags & UPF_CONS_FLOW) {
 784                         int txe = s3c24xx_serial_txempty_nofifo(port);
 785
 786                         if (ourport->rx_enabled) {
 787                                 if (!txe) {
 788                                         ourport->rx_enabled = 0;
 789                                         continue;
 790                                 }
 791                         } else {
 792                                 if (txe) {
 793                                         ufcon = rd_regl(port, S3C2410_UFCON);
 794                                         ufcon |= S3C2410_UFCON_RESETRX;
 795                                         wr_regl(port, S3C2410_UFCON, ufcon);
 796                                         ourport->rx_enabled = 1;
 797                                         return;
 798                                 }
 799                                 continue;
 800                         }
 801                 }
 802
 803                 /* insert the character into the buffer */
 804
 805                 flag = TTY_NORMAL;
 806                 port->icount.rx++;
 807
 808                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 809                         dev_dbg(port->dev,
 810                                 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
 811                                 ch, uerstat);
 812
 813                         /* check for break */
 814                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 815                                 dev_dbg(port->dev, "break!\n");
 816                                 port->icount.brk++;
 817                                 if (uart_handle_break(port))
 818                                         continue; /* Ignore character */
 819                         }
 820
 821                         if (uerstat & S3C2410_UERSTAT_FRAME)
 822                                 port->icount.frame++;
 823                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 824                                 port->icount.overrun++;
 825
 826                         uerstat &= port->read_status_mask;
 827
 828                         if (uerstat & S3C2410_UERSTAT_BREAK)
 829                                 flag = TTY_BREAK;
 830                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 831                                 flag = TTY_PARITY;
 832                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 833                                             S3C2410_UERSTAT_OVERRUN))
 834                                 flag = TTY_FRAME;
 835                 }
 836
 837                 if (uart_handle_sysrq_char(port, ch))
 838                         continue; /* Ignore character */
 839
 840                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 841                                  ch, flag);
 842         }
 843
 844         tty_flip_buffer_push(&port->state->port);
 845 }
 846
 847 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 848 {
 849         struct s3c24xx_uart_port *ourport = dev_id;
 850         struct uart_port *port = &ourport->port;
 851
 852         spin_lock(&port->lock);
 853         s3c24xx_serial_rx_drain_fifo(ourport);
 854         spin_unlock(&port->lock);
 855
 856         return IRQ_HANDLED;
 857 }
 858
 859 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
 860 {
 861         struct s3c24xx_uart_port *ourport = dev_id;
 862
 863         if (ourport->dma && ourport->dma->rx_chan)
 864                 return s3c24xx_serial_rx_chars_dma(dev_id);
 865         return s3c24xx_serial_rx_chars_pio(dev_id);
 866 }
 867
 868 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
 869 {
 870         struct uart_port *port = &ourport->port;
 871         struct circ_buf *xmit = &port->state->xmit;
 872         int count, dma_count = 0;
 873
 874         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 875
 876         if (ourport->dma && ourport->dma->tx_chan &&
 877             count >= ourport->min_dma_size) {
 878                 int align = dma_get_cache_alignment() -
 879                         (xmit->tail & (dma_get_cache_alignment() - 1));
 880                 if (count - align >= ourport->min_dma_size) {
 881                         dma_count = count - align;
 882                         count = align;
 883                 }
 884         }
 885
 886         if (port->x_char) {
 887                 wr_reg(port, S3C2410_UTXH, port->x_char);
 888                 port->icount.tx++;
 889                 port->x_char = 0;
 890                 return;
 891         }
 892
 893         /* if there isn't anything more to transmit, or the uart is now
 894          * stopped, disable the uart and exit
 895          */
 896
 897         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 898                 s3c24xx_serial_stop_tx(port);
 899                 return;
 900         }
 901
 902         /* try and drain the buffer... */
 903
 904         if (count > port->fifosize) {
 905                 count = port->fifosize;
 906                 dma_count = 0;
 907         }
 908
 909         while (!uart_circ_empty(xmit) && count > 0) {
 910                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 911                         break;
 912
 913                 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 914                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 915                 port->icount.tx++;
 916                 count--;
 917         }
 918
 919         if (!count && dma_count) {
 920                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 921                 return;
 922         }
 923
 924         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 925                 uart_write_wakeup(port);
 926
 927         if (uart_circ_empty(xmit))
 928                 s3c24xx_serial_stop_tx(port);
 929 }
 930
 931 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
 932 {
 933         struct s3c24xx_uart_port *ourport = id;
 934         struct uart_port *port = &ourport->port;
 935
 936         spin_lock(&port->lock);
 937
 938         s3c24xx_serial_tx_chars(ourport);
 939
 940         spin_unlock(&port->lock);
 941         return IRQ_HANDLED;
 942 }
 943
 944 /* interrupt handler for s3c64xx and later SoC's.*/
 945 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 946 {
 947         const struct s3c24xx_uart_port *ourport = id;
 948         const struct uart_port *port = &ourport->port;
 949         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 950         irqreturn_t ret = IRQ_HANDLED;
 951
 952         if (pend & S3C64XX_UINTM_RXD_MSK) {
 953                 ret = s3c24xx_serial_rx_irq(irq, id);
 954                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 955         }
 956         if (pend & S3C64XX_UINTM_TXD_MSK) {
 957                 ret = s3c24xx_serial_tx_irq(irq, id);
 958                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 959         }
 960         return ret;
 961 }
 962
 963 /* interrupt handler for Apple SoC's.*/
 964 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
 965 {
 966         const struct s3c24xx_uart_port *ourport = id;
 967         const struct uart_port *port = &ourport->port;
 968         unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
 969         irqreturn_t ret = IRQ_NONE;
 970
 971         if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
 972                 wr_regl(port, S3C2410_UTRSTAT,
 973                         APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
 974                 ret = s3c24xx_serial_rx_irq(irq, id);
 975         }
 976         if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
 977                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
 978                 ret = s3c24xx_serial_tx_irq(irq, id);
 979         }
 980
 981         return ret;
 982 }
 983
 984 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 985 {
 986         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 987         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 988         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 989
 990         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 991                 if ((ufstat & info->tx_fifomask) != 0 ||
 992                     (ufstat & info->tx_fifofull))
 993                         return 0;
 994
 995                 return 1;
 996         }
 997
 998         return s3c24xx_serial_txempty_nofifo(port);
 999 }
1000
1001 /* no modem control lines */
1002 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
1003 {
1004         unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1005
1006         if (umstat & S3C2410_UMSTAT_CTS)
1007                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1008         else
1009                 return TIOCM_CAR | TIOCM_DSR;
1010 }
1011
1012 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1013 {
1014         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1015
1016         if (mctrl & TIOCM_RTS)
1017                 umcon |= S3C2410_UMCOM_RTS_LOW;
1018         else
1019                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1020
1021         wr_regl(port, S3C2410_UMCON, umcon);
1022 }
1023
1024 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1025 {
1026         unsigned long flags;
1027         unsigned int ucon;
1028
1029         spin_lock_irqsave(&port->lock, flags);
1030
1031         ucon = rd_regl(port, S3C2410_UCON);
1032
1033         if (break_state)
1034                 ucon |= S3C2410_UCON_SBREAK;
1035         else
1036                 ucon &= ~S3C2410_UCON_SBREAK;
1037
1038         wr_regl(port, S3C2410_UCON, ucon);
1039
1040         spin_unlock_irqrestore(&port->lock, flags);
1041 }
1042
1043 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1044 {
1045         struct s3c24xx_uart_dma *dma = p->dma;
1046         struct dma_slave_caps dma_caps;
1047         const char *reason = NULL;
1048         int ret;
1049
1050         /* Default slave configuration parameters */
1051         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
1052         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1053         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
1054         dma->rx_conf.src_maxburst       = 1;
1055
1056         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
1057         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1058         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
1059         dma->tx_conf.dst_maxburst       = 1;
1060
1061         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1062
1063         if (IS_ERR(dma->rx_chan)) {
1064                 reason = "DMA RX channel request failed";
1065                 ret = PTR_ERR(dma->rx_chan);
1066                 goto err_warn;
1067         }
1068
1069         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1070         if (ret < 0 ||
1071             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1072                 reason = "insufficient DMA RX engine capabilities";
1073                 ret = -EOPNOTSUPP;
1074                 goto err_release_rx;
1075         }
1076
1077         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1078
1079         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1080         if (IS_ERR(dma->tx_chan)) {
1081                 reason = "DMA TX channel request failed";
1082                 ret = PTR_ERR(dma->tx_chan);
1083                 goto err_release_rx;
1084         }
1085
1086         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1087         if (ret < 0 ||
1088             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1089                 reason = "insufficient DMA TX engine capabilities";
1090                 ret = -EOPNOTSUPP;
1091                 goto err_release_tx;
1092         }
1093
1094         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1095
1096         /* RX buffer */
1097         dma->rx_size = PAGE_SIZE;
1098
1099         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1100         if (!dma->rx_buf) {
1101                 ret = -ENOMEM;
1102                 goto err_release_tx;
1103         }
1104
1105         dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1106                                       dma->rx_size, DMA_FROM_DEVICE);
1107         if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1108                 reason = "DMA mapping error for RX buffer";
1109                 ret = -EIO;
1110                 goto err_free_rx;
1111         }
1112
1113         /* TX buffer */
1114         dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1115                                       p->port.state->xmit.buf, UART_XMIT_SIZE,
1116                                       DMA_TO_DEVICE);
1117         if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1118                 reason = "DMA mapping error for TX buffer";
1119                 ret = -EIO;
1120                 goto err_unmap_rx;
1121         }
1122
1123         return 0;
1124
1125 err_unmap_rx:
1126         dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1127                          dma->rx_size, DMA_FROM_DEVICE);
1128 err_free_rx:
1129         kfree(dma->rx_buf);
1130 err_release_tx:
1131         dma_release_channel(dma->tx_chan);
1132 err_release_rx:
1133         dma_release_channel(dma->rx_chan);
1134 err_warn:
1135         if (reason)
1136                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1137         return ret;
1138 }
1139
1140 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1141 {
1142         struct s3c24xx_uart_dma *dma = p->dma;
1143
1144         if (dma->rx_chan) {
1145                 dmaengine_terminate_all(dma->rx_chan);
1146                 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1147                                  dma->rx_size, DMA_FROM_DEVICE);
1148                 kfree(dma->rx_buf);
1149                 dma_release_channel(dma->rx_chan);
1150                 dma->rx_chan = NULL;
1151         }
1152
1153         if (dma->tx_chan) {
1154                 dmaengine_terminate_all(dma->tx_chan);
1155                 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1156                                  UART_XMIT_SIZE, DMA_TO_DEVICE);
1157                 dma_release_channel(dma->tx_chan);
1158                 dma->tx_chan = NULL;
1159         }
1160 }
1161
1162 static void s3c24xx_serial_shutdown(struct uart_port *port)
1163 {
1164         struct s3c24xx_uart_port *ourport = to_ourport(port);
1165
1166         if (ourport->tx_claimed) {
1167                 free_irq(ourport->tx_irq, ourport);
1168                 ourport->tx_enabled = 0;
1169                 ourport->tx_claimed = 0;
1170                 ourport->tx_mode = 0;
1171         }
1172
1173         if (ourport->rx_claimed) {
1174                 free_irq(ourport->rx_irq, ourport);
1175                 ourport->rx_claimed = 0;
1176                 ourport->rx_enabled = 0;
1177         }
1178
1179         if (ourport->dma)
1180                 s3c24xx_serial_release_dma(ourport);
1181
1182         ourport->tx_in_progress = 0;
1183 }
1184
1185 static void s3c64xx_serial_shutdown(struct uart_port *port)
1186 {
1187         struct s3c24xx_uart_port *ourport = to_ourport(port);
1188
1189         ourport->tx_enabled = 0;
1190         ourport->tx_mode = 0;
1191         ourport->rx_enabled = 0;
1192
1193         free_irq(port->irq, ourport);
1194
1195         wr_regl(port, S3C64XX_UINTP, 0xf);
1196         wr_regl(port, S3C64XX_UINTM, 0xf);
1197
1198         if (ourport->dma)
1199                 s3c24xx_serial_release_dma(ourport);
1200
1201         ourport->tx_in_progress = 0;
1202 }
1203
1204 static void apple_s5l_serial_shutdown(struct uart_port *port)
1205 {
1206         struct s3c24xx_uart_port *ourport = to_ourport(port);
1207
1208         unsigned int ucon;
1209
1210         ucon = rd_regl(port, S3C2410_UCON);
1211         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1212                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1213                   APPLE_S5L_UCON_RXTO_ENA_MSK);
1214         wr_regl(port, S3C2410_UCON, ucon);
1215
1216         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1217
1218         free_irq(port->irq, ourport);
1219
1220         ourport->tx_enabled = 0;
1221         ourport->tx_mode = 0;
1222         ourport->rx_enabled = 0;
1223
1224         if (ourport->dma)
1225                 s3c24xx_serial_release_dma(ourport);
1226
1227         ourport->tx_in_progress = 0;
1228 }
1229
1230 static int s3c24xx_serial_startup(struct uart_port *port)
1231 {
1232         struct s3c24xx_uart_port *ourport = to_ourport(port);
1233         int ret;
1234
1235         ourport->rx_enabled = 1;
1236
1237         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0,
1238                           s3c24xx_serial_portname(port), ourport);
1239
1240         if (ret != 0) {
1241                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1242                 return ret;
1243         }
1244
1245         ourport->rx_claimed = 1;
1246
1247         dev_dbg(port->dev, "requesting tx irq...\n");
1248
1249         ourport->tx_enabled = 1;
1250
1251         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0,
1252                           s3c24xx_serial_portname(port), ourport);
1253
1254         if (ret) {
1255                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1256                 goto err;
1257         }
1258
1259         ourport->tx_claimed = 1;
1260
1261         /* the port reset code should have done the correct
1262          * register setup for the port controls
1263          */
1264
1265         return ret;
1266
1267 err:
1268         s3c24xx_serial_shutdown(port);
1269         return ret;
1270 }
1271
1272 static int s3c64xx_serial_startup(struct uart_port *port)
1273 {
1274         struct s3c24xx_uart_port *ourport = to_ourport(port);
1275         unsigned long flags;
1276         unsigned int ufcon;
1277         int ret;
1278
1279         wr_regl(port, S3C64XX_UINTM, 0xf);
1280         if (ourport->dma) {
1281                 ret = s3c24xx_serial_request_dma(ourport);
1282                 if (ret < 0) {
1283                         devm_kfree(port->dev, ourport->dma);
1284                         ourport->dma = NULL;
1285                 }
1286         }
1287
1288         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1289                           s3c24xx_serial_portname(port), ourport);
1290         if (ret) {
1291                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1292                 return ret;
1293         }
1294
1295         /* For compatibility with s3c24xx Soc's */
1296         ourport->rx_enabled = 1;
1297         ourport->tx_enabled = 0;
1298
1299         spin_lock_irqsave(&port->lock, flags);
1300
1301         ufcon = rd_regl(port, S3C2410_UFCON);
1302         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1303         if (!uart_console(port))
1304                 ufcon |= S3C2410_UFCON_RESETTX;
1305         wr_regl(port, S3C2410_UFCON, ufcon);
1306
1307         enable_rx_pio(ourport);
1308
1309         spin_unlock_irqrestore(&port->lock, flags);
1310
1311         /* Enable Rx Interrupt */
1312         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1313
1314         return ret;
1315 }
1316
1317 static int apple_s5l_serial_startup(struct uart_port *port)
1318 {
1319         struct s3c24xx_uart_port *ourport = to_ourport(port);
1320         unsigned long flags;
1321         unsigned int ufcon;
1322         int ret;
1323
1324         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1325
1326         ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1327                           s3c24xx_serial_portname(port), ourport);
1328         if (ret) {
1329                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1330                 return ret;
1331         }
1332
1333         /* For compatibility with s3c24xx Soc's */
1334         ourport->rx_enabled = 1;
1335         ourport->tx_enabled = 0;
1336
1337         spin_lock_irqsave(&port->lock, flags);
1338
1339         ufcon = rd_regl(port, S3C2410_UFCON);
1340         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1341         if (!uart_console(port))
1342                 ufcon |= S3C2410_UFCON_RESETTX;
1343         wr_regl(port, S3C2410_UFCON, ufcon);
1344
1345         enable_rx_pio(ourport);
1346
1347         spin_unlock_irqrestore(&port->lock, flags);
1348
1349         /* Enable Rx Interrupt */
1350         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1351         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1352
1353         return ret;
1354 }
1355
1356 /* power power management control */
1357
1358 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1359                               unsigned int old)
1360 {
1361         struct s3c24xx_uart_port *ourport = to_ourport(port);
1362         int timeout = 10000;
1363
1364         ourport->pm_level = level;
1365
1366         switch (level) {
1367         case 3:
1368                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1369                         udelay(100);
1370
1371                 if (!IS_ERR(ourport->baudclk))
1372                         clk_disable_unprepare(ourport->baudclk);
1373
1374                 clk_disable_unprepare(ourport->clk);
1375                 break;
1376
1377         case 0:
1378                 clk_prepare_enable(ourport->clk);
1379
1380                 if (!IS_ERR(ourport->baudclk))
1381                         clk_prepare_enable(ourport->baudclk);
1382                 break;
1383         default:
1384                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1385         }
1386 }
1387
1388 /* baud rate calculation
1389  *
1390  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1391  * of different sources, including the peripheral clock ("pclk") and an
1392  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1393  * with a programmable extra divisor.
1394  *
1395  * The following code goes through the clock sources, and calculates the
1396  * baud clocks (and the resultant actual baud rates) and then tries to
1397  * pick the closest one and select that.
1398  *
1399  */
1400
1401 #define MAX_CLK_NAME_LENGTH 15
1402
1403 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1404 {
1405         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1406         unsigned int ucon;
1407
1408         if (info->num_clks == 1)
1409                 return 0;
1410
1411         ucon = rd_regl(port, S3C2410_UCON);
1412         ucon &= info->clksel_mask;
1413         return ucon >> info->clksel_shift;
1414 }
1415
1416 static void s3c24xx_serial_setsource(struct uart_port *port,
1417                         unsigned int clk_sel)
1418 {
1419         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1420         unsigned int ucon;
1421
1422         if (info->num_clks == 1)
1423                 return;
1424
1425         ucon = rd_regl(port, S3C2410_UCON);
1426         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1427                 return;
1428
1429         ucon &= ~info->clksel_mask;
1430         ucon |= clk_sel << info->clksel_shift;
1431         wr_regl(port, S3C2410_UCON, ucon);
1432 }
1433
1434 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1435                         unsigned int req_baud, struct clk **best_clk,
1436                         unsigned int *clk_num)
1437 {
1438         const struct s3c24xx_uart_info *info = ourport->info;
1439         struct clk *clk;
1440         unsigned long rate;
1441         unsigned int cnt, baud, quot, best_quot = 0;
1442         char clkname[MAX_CLK_NAME_LENGTH];
1443         int calc_deviation, deviation = (1 << 30) - 1;
1444
1445         for (cnt = 0; cnt < info->num_clks; cnt++) {
1446                 /* Keep selected clock if provided */
1447                 if (ourport->cfg->clk_sel &&
1448                         !(ourport->cfg->clk_sel & (1 << cnt)))
1449                         continue;
1450
1451                 sprintf(clkname, "clk_uart_baud%d", cnt);
1452                 clk = clk_get(ourport->port.dev, clkname);
1453                 if (IS_ERR(clk))
1454                         continue;
1455
1456                 rate = clk_get_rate(clk);
1457                 if (!rate)
1458                         continue;
1459
1460                 if (ourport->info->has_divslot) {
1461                         unsigned long div = rate / req_baud;
1462
1463                         /* The UDIVSLOT register on the newer UARTs allows us to
1464                          * get a divisor adjustment of 1/16th on the baud clock.
1465                          *
1466                          * We don't keep the UDIVSLOT value (the 16ths we
1467                          * calculated by not multiplying the baud by 16) as it
1468                          * is easy enough to recalculate.
1469                          */
1470
1471                         quot = div / 16;
1472                         baud = rate / div;
1473                 } else {
1474                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1475                         baud = rate / (quot * 16);
1476                 }
1477                 quot--;
1478
1479                 calc_deviation = req_baud - baud;
1480                 if (calc_deviation < 0)
1481                         calc_deviation = -calc_deviation;
1482
1483                 if (calc_deviation < deviation) {
1484                         *best_clk = clk;
1485                         best_quot = quot;
1486                         *clk_num = cnt;
1487                         deviation = calc_deviation;
1488                 }
1489         }
1490
1491         return best_quot;
1492 }
1493
1494 /* udivslot_table[]
1495  *
1496  * This table takes the fractional value of the baud divisor and gives
1497  * the recommended setting for the UDIVSLOT register.
1498  */
1499 static const u16 udivslot_table[16] = {
1500         [0] = 0x0000,
1501         [1] = 0x0080,
1502         [2] = 0x0808,
1503         [3] = 0x0888,
1504         [4] = 0x2222,
1505         [5] = 0x4924,
1506         [6] = 0x4A52,
1507         [7] = 0x54AA,
1508         [8] = 0x5555,
1509         [9] = 0xD555,
1510         [10] = 0xD5D5,
1511         [11] = 0xDDD5,
1512         [12] = 0xDDDD,
1513         [13] = 0xDFDD,
1514         [14] = 0xDFDF,
1515         [15] = 0xFFDF,
1516 };
1517
1518 static void s3c24xx_serial_set_termios(struct uart_port *port,
1519                                        struct ktermios *termios,
1520                                        struct ktermios *old)
1521 {
1522         const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1523         struct s3c24xx_uart_port *ourport = to_ourport(port);
1524         struct clk *clk = ERR_PTR(-EINVAL);
1525         unsigned long flags;
1526         unsigned int baud, quot, clk_sel = 0;
1527         unsigned int ulcon;
1528         unsigned int umcon;
1529         unsigned int udivslot = 0;
1530
1531         /*
1532          * We don't support modem control lines.
1533          */
1534         termios->c_cflag &= ~(HUPCL | CMSPAR);
1535         termios->c_cflag |= CLOCAL;
1536
1537         /*
1538          * Ask the core to calculate the divisor for us.
1539          */
1540
1541         baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1542         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1543         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1544                 quot = port->custom_divisor;
1545         if (IS_ERR(clk))
1546                 return;
1547
1548         /* check to see if we need  to change clock source */
1549
1550         if (ourport->baudclk != clk) {
1551                 clk_prepare_enable(clk);
1552
1553                 s3c24xx_serial_setsource(port, clk_sel);
1554
1555                 if (!IS_ERR(ourport->baudclk)) {
1556                         clk_disable_unprepare(ourport->baudclk);
1557                         ourport->baudclk = ERR_PTR(-EINVAL);
1558                 }
1559
1560                 ourport->baudclk = clk;
1561                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1562         }
1563
1564         if (ourport->info->has_divslot) {
1565                 unsigned int div = ourport->baudclk_rate / baud;
1566
1567                 if (cfg->has_fracval) {
1568                         udivslot = (div & 15);
1569                         dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1570                 } else {
1571                         udivslot = udivslot_table[div & 15];
1572                         dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1573                                 udivslot, div & 15);
1574                 }
1575         }
1576
1577         switch (termios->c_cflag & CSIZE) {
1578         case CS5:
1579                 dev_dbg(port->dev, "config: 5bits/char\n");
1580                 ulcon = S3C2410_LCON_CS5;
1581                 break;
1582         case CS6:
1583                 dev_dbg(port->dev, "config: 6bits/char\n");
1584                 ulcon = S3C2410_LCON_CS6;
1585                 break;
1586         case CS7:
1587                 dev_dbg(port->dev, "config: 7bits/char\n");
1588                 ulcon = S3C2410_LCON_CS7;
1589                 break;
1590         case CS8:
1591         default:
1592                 dev_dbg(port->dev, "config: 8bits/char\n");
1593                 ulcon = S3C2410_LCON_CS8;
1594                 break;
1595         }
1596
1597         /* preserve original lcon IR settings */
1598         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1599
1600         if (termios->c_cflag & CSTOPB)
1601                 ulcon |= S3C2410_LCON_STOPB;
1602
1603         if (termios->c_cflag & PARENB) {
1604                 if (termios->c_cflag & PARODD)
1605                         ulcon |= S3C2410_LCON_PODD;
1606                 else
1607                         ulcon |= S3C2410_LCON_PEVEN;
1608         } else {
1609                 ulcon |= S3C2410_LCON_PNONE;
1610         }
1611
1612         spin_lock_irqsave(&port->lock, flags);
1613
1614         dev_dbg(port->dev,
1615                 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1616                 ulcon, quot, udivslot);
1617
1618         wr_regl(port, S3C2410_ULCON, ulcon);
1619         wr_regl(port, S3C2410_UBRDIV, quot);
1620
1621         port->status &= ~UPSTAT_AUTOCTS;
1622
1623         umcon = rd_regl(port, S3C2410_UMCON);
1624         if (termios->c_cflag & CRTSCTS) {
1625                 umcon |= S3C2410_UMCOM_AFC;
1626                 /* Disable RTS when RX FIFO contains 63 bytes */
1627                 umcon &= ~S3C2412_UMCON_AFC_8;
1628                 port->status = UPSTAT_AUTOCTS;
1629         } else {
1630                 umcon &= ~S3C2410_UMCOM_AFC;
1631         }
1632         wr_regl(port, S3C2410_UMCON, umcon);
1633
1634         if (ourport->info->has_divslot)
1635                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1636
1637         dev_dbg(port->dev,
1638                 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1639                 rd_regl(port, S3C2410_ULCON),
1640                 rd_regl(port, S3C2410_UCON),
1641                 rd_regl(port, S3C2410_UFCON));
1642
1643         /*
1644          * Update the per-port timeout.
1645          */
1646         uart_update_timeout(port, termios->c_cflag, baud);
1647
1648         /*
1649          * Which character status flags are we interested in?
1650          */
1651         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1652         if (termios->c_iflag & INPCK)
1653                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1654                         S3C2410_UERSTAT_PARITY;
1655         /*
1656          * Which character status flags should we ignore?
1657          */
1658         port->ignore_status_mask = 0;
1659         if (termios->c_iflag & IGNPAR)
1660                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1661         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1662                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1663
1664         /*
1665          * Ignore all characters if CREAD is not set.
1666          */
1667         if ((termios->c_cflag & CREAD) == 0)
1668                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1669
1670         spin_unlock_irqrestore(&port->lock, flags);
1671 }
1672
1673 static const char *s3c24xx_serial_type(struct uart_port *port)
1674 {
1675         const struct s3c24xx_uart_port *ourport = to_ourport(port);
1676
1677         switch (ourport->info->type) {
1678         case TYPE_S3C24XX:
1679                 return "S3C24XX";
1680         case TYPE_S3C6400:
1681                 return "S3C6400/10";
1682         case TYPE_APPLE_S5L:
1683                 return "APPLE S5L";
1684         default:
1685                 return NULL;
1686         }
1687 }
1688
1689 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1690 {
1691         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1692
1693         if (flags & UART_CONFIG_TYPE)
1694                 port->type = info->port_type;
1695 }
1696
1697 /*
1698  * verify the new serial_struct (for TIOCSSERIAL).
1699  */
1700 static int
1701 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1702 {
1703         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1704
1705         if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1706                 return -EINVAL;
1707
1708         return 0;
1709 }
1710
1711 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1712
1713 static struct console s3c24xx_serial_console;
1714
1715 static void __init s3c24xx_serial_register_console(void)
1716 {
1717         register_console(&s3c24xx_serial_console);
1718 }
1719
1720 static void s3c24xx_serial_unregister_console(void)
1721 {
1722         if (s3c24xx_serial_console.flags & CON_ENABLED)
1723                 unregister_console(&s3c24xx_serial_console);
1724 }
1725
1726 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1727 #else
1728 static inline void s3c24xx_serial_register_console(void) { }
1729 static inline void s3c24xx_serial_unregister_console(void) { }
1730 #define S3C24XX_SERIAL_CONSOLE NULL
1731 #endif
1732
1733 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1734 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1735 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1736                          unsigned char c);
1737 #endif
1738
1739 static const struct uart_ops s3c24xx_serial_ops = {
1740         .pm             = s3c24xx_serial_pm,
1741         .tx_empty       = s3c24xx_serial_tx_empty,
1742         .get_mctrl      = s3c24xx_serial_get_mctrl,
1743         .set_mctrl      = s3c24xx_serial_set_mctrl,
1744         .stop_tx        = s3c24xx_serial_stop_tx,
1745         .start_tx       = s3c24xx_serial_start_tx,
1746         .stop_rx        = s3c24xx_serial_stop_rx,
1747         .break_ctl      = s3c24xx_serial_break_ctl,
1748         .startup        = s3c24xx_serial_startup,
1749         .shutdown       = s3c24xx_serial_shutdown,
1750         .set_termios    = s3c24xx_serial_set_termios,
1751         .type           = s3c24xx_serial_type,
1752         .config_port    = s3c24xx_serial_config_port,
1753         .verify_port    = s3c24xx_serial_verify_port,
1754 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1755         .poll_get_char = s3c24xx_serial_get_poll_char,
1756         .poll_put_char = s3c24xx_serial_put_poll_char,
1757 #endif
1758 };
1759
1760 static const struct uart_ops s3c64xx_serial_ops = {
1761         .pm             = s3c24xx_serial_pm,
1762         .tx_empty       = s3c24xx_serial_tx_empty,
1763         .get_mctrl      = s3c24xx_serial_get_mctrl,
1764         .set_mctrl      = s3c24xx_serial_set_mctrl,
1765         .stop_tx        = s3c24xx_serial_stop_tx,
1766         .start_tx       = s3c24xx_serial_start_tx,
1767         .stop_rx        = s3c24xx_serial_stop_rx,
1768         .break_ctl      = s3c24xx_serial_break_ctl,
1769         .startup        = s3c64xx_serial_startup,
1770         .shutdown       = s3c64xx_serial_shutdown,
1771         .set_termios    = s3c24xx_serial_set_termios,
1772         .type           = s3c24xx_serial_type,
1773         .config_port    = s3c24xx_serial_config_port,
1774         .verify_port    = s3c24xx_serial_verify_port,
1775 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1776         .poll_get_char = s3c24xx_serial_get_poll_char,
1777         .poll_put_char = s3c24xx_serial_put_poll_char,
1778 #endif
1779 };
1780
1781 static const struct uart_ops apple_s5l_serial_ops = {
1782         .pm             = s3c24xx_serial_pm,
1783         .tx_empty       = s3c24xx_serial_tx_empty,
1784         .get_mctrl      = s3c24xx_serial_get_mctrl,
1785         .set_mctrl      = s3c24xx_serial_set_mctrl,
1786         .stop_tx        = s3c24xx_serial_stop_tx,
1787         .start_tx       = s3c24xx_serial_start_tx,
1788         .stop_rx        = s3c24xx_serial_stop_rx,
1789         .break_ctl      = s3c24xx_serial_break_ctl,
1790         .startup        = apple_s5l_serial_startup,
1791         .shutdown       = apple_s5l_serial_shutdown,
1792         .set_termios    = s3c24xx_serial_set_termios,
1793         .type           = s3c24xx_serial_type,
1794         .config_port    = s3c24xx_serial_config_port,
1795         .verify_port    = s3c24xx_serial_verify_port,
1796 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1797         .poll_get_char = s3c24xx_serial_get_poll_char,
1798         .poll_put_char = s3c24xx_serial_put_poll_char,
1799 #endif
1800 };
1801
1802 static struct uart_driver s3c24xx_uart_drv = {
1803         .owner          = THIS_MODULE,
1804         .driver_name    = "s3c2410_serial",
1805         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1806         .cons           = S3C24XX_SERIAL_CONSOLE,
1807         .dev_name       = S3C24XX_SERIAL_NAME,
1808         .major          = S3C24XX_SERIAL_MAJOR,
1809         .minor          = S3C24XX_SERIAL_MINOR,
1810 };
1811
1812 #define __PORT_LOCK_UNLOCKED(i) \
1813         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1814 static struct s3c24xx_uart_port
1815 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1816         [0] = {
1817                 .port = {
1818                         .lock           = __PORT_LOCK_UNLOCKED(0),
1819                         .iotype         = UPIO_MEM,
1820                         .uartclk        = 0,
1821                         .fifosize       = 16,
1822                         .ops            = &s3c24xx_serial_ops,
1823                         .flags          = UPF_BOOT_AUTOCONF,
1824                         .line           = 0,
1825                 }
1826         },
1827         [1] = {
1828                 .port = {
1829                         .lock           = __PORT_LOCK_UNLOCKED(1),
1830                         .iotype         = UPIO_MEM,
1831                         .uartclk        = 0,
1832                         .fifosize       = 16,
1833                         .ops            = &s3c24xx_serial_ops,
1834                         .flags          = UPF_BOOT_AUTOCONF,
1835                         .line           = 1,
1836                 }
1837         },
1838 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1839         [2] = {
1840                 .port = {
1841                         .lock           = __PORT_LOCK_UNLOCKED(2),
1842                         .iotype         = UPIO_MEM,
1843                         .uartclk        = 0,
1844                         .fifosize       = 16,
1845                         .ops            = &s3c24xx_serial_ops,
1846                         .flags          = UPF_BOOT_AUTOCONF,
1847                         .line           = 2,
1848                 }
1849         },
1850 #endif
1851 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1852         [3] = {
1853                 .port = {
1854                         .lock           = __PORT_LOCK_UNLOCKED(3),
1855                         .iotype         = UPIO_MEM,
1856                         .uartclk        = 0,
1857                         .fifosize       = 16,
1858                         .ops            = &s3c24xx_serial_ops,
1859                         .flags          = UPF_BOOT_AUTOCONF,
1860                         .line           = 3,
1861                 }
1862         }
1863 #endif
1864 };
1865 #undef __PORT_LOCK_UNLOCKED
1866
1867 /* s3c24xx_serial_resetport
1868  *
1869  * reset the fifos and other the settings.
1870  */
1871
1872 static void s3c24xx_serial_resetport(struct uart_port *port,
1873                                      const struct s3c2410_uartcfg *cfg)
1874 {
1875         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1876         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1877
1878         ucon &= (info->clksel_mask | info->ucon_mask);
1879         wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1880
1881         /* reset both fifos */
1882         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1883         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1884
1885         /* some delay is required after fifo reset */
1886         udelay(1);
1887 }
1888
1889 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1890
1891 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1892                                              unsigned long val, void *data)
1893 {
1894         struct s3c24xx_uart_port *port;
1895         struct uart_port *uport;
1896
1897         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1898         uport = &port->port;
1899
1900         /* check to see if port is enabled */
1901
1902         if (port->pm_level != 0)
1903                 return 0;
1904
1905         /* try and work out if the baudrate is changing, we can detect
1906          * a change in rate, but we do not have support for detecting
1907          * a disturbance in the clock-rate over the change.
1908          */
1909
1910         if (IS_ERR(port->baudclk))
1911                 goto exit;
1912
1913         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1914                 goto exit;
1915
1916         if (val == CPUFREQ_PRECHANGE) {
1917                 /* we should really shut the port down whilst the
1918                  * frequency change is in progress.
1919                  */
1920
1921         } else if (val == CPUFREQ_POSTCHANGE) {
1922                 struct ktermios *termios;
1923                 struct tty_struct *tty;
1924
1925                 if (uport->state == NULL)
1926                         goto exit;
1927
1928                 tty = uport->state->port.tty;
1929
1930                 if (tty == NULL)
1931                         goto exit;
1932
1933                 termios = &tty->termios;
1934
1935                 if (termios == NULL) {
1936                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1937                         goto exit;
1938                 }
1939
1940                 s3c24xx_serial_set_termios(uport, termios, NULL);
1941         }
1942
1943 exit:
1944         return 0;
1945 }
1946
1947 static inline int
1948 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1949 {
1950         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1951
1952         return cpufreq_register_notifier(&port->freq_transition,
1953                                          CPUFREQ_TRANSITION_NOTIFIER);
1954 }
1955
1956 static inline void
1957 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1958 {
1959         cpufreq_unregister_notifier(&port->freq_transition,
1960                                     CPUFREQ_TRANSITION_NOTIFIER);
1961 }
1962
1963 #else
1964 static inline int
1965 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1966 {
1967         return 0;
1968 }
1969
1970 static inline void
1971 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1972 {
1973 }
1974 #endif
1975
1976 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1977 {
1978         struct device *dev = ourport->port.dev;
1979         const struct s3c24xx_uart_info *info = ourport->info;
1980         char clk_name[MAX_CLK_NAME_LENGTH];
1981         unsigned int clk_sel;
1982         struct clk *clk;
1983         int clk_num;
1984         int ret;
1985
1986         clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1987         for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1988                 if (!(clk_sel & (1 << clk_num)))
1989                         continue;
1990
1991                 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1992                 clk = clk_get(dev, clk_name);
1993                 if (IS_ERR(clk))
1994                         continue;
1995
1996                 ret = clk_prepare_enable(clk);
1997                 if (ret) {
1998                         clk_put(clk);
1999                         continue;
2000                 }
2001
2002                 ourport->baudclk = clk;
2003                 ourport->baudclk_rate = clk_get_rate(clk);
2004                 s3c24xx_serial_setsource(&ourport->port, clk_num);
2005
2006                 return 0;
2007         }
2008
2009         return -EINVAL;
2010 }
2011
2012 /* s3c24xx_serial_init_port
2013  *
2014  * initialise a single serial port from the platform device given
2015  */
2016
2017 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
2018                                     struct platform_device *platdev)
2019 {
2020         struct uart_port *port = &ourport->port;
2021         const struct s3c2410_uartcfg *cfg = ourport->cfg;
2022         struct resource *res;
2023         int ret;
2024
2025         if (platdev == NULL)
2026                 return -ENODEV;
2027
2028         if (port->mapbase != 0)
2029                 return -EINVAL;
2030
2031         /* setup info for port */
2032         port->dev       = &platdev->dev;
2033
2034         port->uartclk = 1;
2035
2036         if (cfg->uart_flags & UPF_CONS_FLOW) {
2037                 dev_dbg(port->dev, "enabling flow control\n");
2038                 port->flags |= UPF_CONS_FLOW;
2039         }
2040
2041         /* sort our the physical and virtual addresses for each UART */
2042
2043         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
2044         if (res == NULL) {
2045                 dev_err(port->dev, "failed to find memory resource for uart\n");
2046                 return -EINVAL;
2047         }
2048
2049         dev_dbg(port->dev, "resource %pR)\n", res);
2050
2051         port->membase = devm_ioremap_resource(port->dev, res);
2052         if (IS_ERR(port->membase)) {
2053                 dev_err(port->dev, "failed to remap controller address\n");
2054                 return -EBUSY;
2055         }
2056
2057         port->mapbase = res->start;
2058         ret = platform_get_irq(platdev, 0);
2059         if (ret < 0) {
2060                 port->irq = 0;
2061         } else {
2062                 port->irq = ret;
2063                 ourport->rx_irq = ret;
2064                 ourport->tx_irq = ret + 1;
2065         }
2066
2067         switch (ourport->info->type) {
2068         case TYPE_S3C24XX:
2069                 ret = platform_get_irq(platdev, 1);
2070                 if (ret > 0)
2071                         ourport->tx_irq = ret;
2072                 break;
2073         default:
2074                 break;
2075         }
2076
2077         /*
2078          * DMA is currently supported only on DT platforms, if DMA properties
2079          * are specified.
2080          */
2081         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
2082                                                      "dmas", NULL)) {
2083                 ourport->dma = devm_kzalloc(port->dev,
2084                                             sizeof(*ourport->dma),
2085                                             GFP_KERNEL);
2086                 if (!ourport->dma) {
2087                         ret = -ENOMEM;
2088                         goto err;
2089                 }
2090         }
2091
2092         ourport->clk    = clk_get(&platdev->dev, "uart");
2093         if (IS_ERR(ourport->clk)) {
2094                 pr_err("%s: Controller clock not found\n",
2095                                 dev_name(&platdev->dev));
2096                 ret = PTR_ERR(ourport->clk);
2097                 goto err;
2098         }
2099
2100         ret = clk_prepare_enable(ourport->clk);
2101         if (ret) {
2102                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
2103                 clk_put(ourport->clk);
2104                 goto err;
2105         }
2106
2107         ret = s3c24xx_serial_enable_baudclk(ourport);
2108         if (ret)
2109                 pr_warn("uart: failed to enable baudclk\n");
2110
2111         /* Keep all interrupts masked and cleared */
2112         switch (ourport->info->type) {
2113         case TYPE_S3C6400:
2114                 wr_regl(port, S3C64XX_UINTM, 0xf);
2115                 wr_regl(port, S3C64XX_UINTP, 0xf);
2116                 wr_regl(port, S3C64XX_UINTSP, 0xf);
2117                 break;
2118         case TYPE_APPLE_S5L: {
2119                 unsigned int ucon;
2120
2121                 ucon = rd_regl(port, S3C2410_UCON);
2122                 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2123                         APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2124                         APPLE_S5L_UCON_RXTO_ENA_MSK);
2125                 wr_regl(port, S3C2410_UCON, ucon);
2126
2127                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
2128                 break;
2129         }
2130         default:
2131                 break;
2132         }
2133
2134         dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
2135                 &port->mapbase, port->membase, port->irq,
2136                 ourport->rx_irq, ourport->tx_irq, port->uartclk);
2137
2138         /* reset the fifos (and setup the uart) */
2139         s3c24xx_serial_resetport(port, cfg);
2140
2141         return 0;
2142
2143 err:
2144         port->mapbase = 0;
2145         return ret;
2146 }
2147
2148 /* Device driver serial port probe */
2149
2150 static int probe_index;
2151
2152 static inline const struct s3c24xx_serial_drv_data *
2153 s3c24xx_get_driver_data(struct platform_device *pdev)
2154 {
2155         if (dev_of_node(&pdev->dev))
2156                 return of_device_get_match_data(&pdev->dev);
2157
2158         return (struct s3c24xx_serial_drv_data *)
2159                         platform_get_device_id(pdev)->driver_data;
2160 }
2161
2162 static int s3c24xx_serial_probe(struct platform_device *pdev)
2163 {
2164         struct device_node *np = pdev->dev.of_node;
2165         struct s3c24xx_uart_port *ourport;
2166         int index = probe_index;
2167         int ret, prop = 0;
2168
2169         if (np) {
2170                 ret = of_alias_get_id(np, "serial");
2171                 if (ret >= 0)
2172                         index = ret;
2173         }
2174
2175         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2176                 dev_err(&pdev->dev, "serial%d out of range\n", index);
2177                 return -EINVAL;
2178         }
2179         ourport = &s3c24xx_serial_ports[index];
2180
2181         ourport->drv_data = s3c24xx_get_driver_data(pdev);
2182         if (!ourport->drv_data) {
2183                 dev_err(&pdev->dev, "could not find driver data\n");
2184                 return -ENODEV;
2185         }
2186
2187         ourport->baudclk = ERR_PTR(-EINVAL);
2188         ourport->info = &ourport->drv_data->info;
2189         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2190                         dev_get_platdata(&pdev->dev) :
2191                         &ourport->drv_data->def_cfg;
2192
2193         switch (ourport->info->type) {
2194         case TYPE_S3C24XX:
2195                 ourport->port.ops = &s3c24xx_serial_ops;
2196                 break;
2197         case TYPE_S3C6400:
2198                 ourport->port.ops = &s3c64xx_serial_ops;
2199                 break;
2200         case TYPE_APPLE_S5L:
2201                 ourport->port.ops = &apple_s5l_serial_ops;
2202                 break;
2203         }
2204
2205         if (np) {
2206                 of_property_read_u32(np,
2207                         "samsung,uart-fifosize", &ourport->port.fifosize);
2208
2209                 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2210                         switch (prop) {
2211                         case 1:
2212                                 ourport->port.iotype = UPIO_MEM;
2213                                 break;
2214                         case 4:
2215                                 ourport->port.iotype = UPIO_MEM32;
2216                                 break;
2217                         default:
2218                                 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2219                                                 prop);
2220                                 return -EINVAL;
2221                         }
2222                 }
2223         }
2224
2225         if (ourport->drv_data->fifosize[index])
2226                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2227         else if (ourport->info->fifosize)
2228                 ourport->port.fifosize = ourport->info->fifosize;
2229         ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2230
2231         /*
2232          * DMA transfers must be aligned at least to cache line size,
2233          * so find minimal transfer size suitable for DMA mode
2234          */
2235         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2236                                     dma_get_cache_alignment());
2237
2238         dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2239
2240         ret = s3c24xx_serial_init_port(ourport, pdev);
2241         if (ret < 0)
2242                 return ret;
2243
2244         if (!s3c24xx_uart_drv.state) {
2245                 ret = uart_register_driver(&s3c24xx_uart_drv);
2246                 if (ret < 0) {
2247                         pr_err("Failed to register Samsung UART driver\n");
2248                         return ret;
2249                 }
2250         }
2251
2252         dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2253         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2254         platform_set_drvdata(pdev, &ourport->port);
2255
2256         /*
2257          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2258          * so that a potential re-enablement through the pm-callback overlaps
2259          * and keeps the clock enabled in this case.
2260          */
2261         clk_disable_unprepare(ourport->clk);
2262         if (!IS_ERR(ourport->baudclk))
2263                 clk_disable_unprepare(ourport->baudclk);
2264
2265         ret = s3c24xx_serial_cpufreq_register(ourport);
2266         if (ret < 0)
2267                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2268
2269         probe_index++;
2270
2271         return 0;
2272 }
2273
2274 static int s3c24xx_serial_remove(struct platform_device *dev)
2275 {
2276         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2277
2278         if (port) {
2279                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2280                 uart_remove_one_port(&s3c24xx_uart_drv, port);
2281         }
2282
2283         uart_unregister_driver(&s3c24xx_uart_drv);
2284
2285         return 0;
2286 }
2287
2288 /* UART power management code */
2289 #ifdef CONFIG_PM_SLEEP
2290 static int s3c24xx_serial_suspend(struct device *dev)
2291 {
2292         struct uart_port *port = s3c24xx_dev_to_port(dev);
2293
2294         if (port)
2295                 uart_suspend_port(&s3c24xx_uart_drv, port);
2296
2297         return 0;
2298 }
2299
2300 static int s3c24xx_serial_resume(struct device *dev)
2301 {
2302         struct uart_port *port = s3c24xx_dev_to_port(dev);
2303         struct s3c24xx_uart_port *ourport = to_ourport(port);
2304
2305         if (port) {
2306                 clk_prepare_enable(ourport->clk);
2307                 if (!IS_ERR(ourport->baudclk))
2308                         clk_prepare_enable(ourport->baudclk);
2309                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2310                 if (!IS_ERR(ourport->baudclk))
2311                         clk_disable_unprepare(ourport->baudclk);
2312                 clk_disable_unprepare(ourport->clk);
2313
2314                 uart_resume_port(&s3c24xx_uart_drv, port);
2315         }
2316
2317         return 0;
2318 }
2319
2320 static int s3c24xx_serial_resume_noirq(struct device *dev)
2321 {
2322         struct uart_port *port = s3c24xx_dev_to_port(dev);
2323         struct s3c24xx_uart_port *ourport = to_ourport(port);
2324
2325         if (port) {
2326                 /* restore IRQ mask */
2327                 switch (ourport->info->type) {
2328                 case TYPE_S3C6400: {
2329                         unsigned int uintm = 0xf;
2330
2331                         if (ourport->tx_enabled)
2332                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2333                         if (ourport->rx_enabled)
2334                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2335                         clk_prepare_enable(ourport->clk);
2336                         if (!IS_ERR(ourport->baudclk))
2337                                 clk_prepare_enable(ourport->baudclk);
2338                         wr_regl(port, S3C64XX_UINTM, uintm);
2339                         if (!IS_ERR(ourport->baudclk))
2340                                 clk_disable_unprepare(ourport->baudclk);
2341                         clk_disable_unprepare(ourport->clk);
2342                         break;
2343                 }
2344                 case TYPE_APPLE_S5L: {
2345                         unsigned int ucon;
2346                         int ret;
2347
2348                         ret = clk_prepare_enable(ourport->clk);
2349                         if (ret) {
2350                                 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2351                                 return ret;
2352                         }
2353                         if (!IS_ERR(ourport->baudclk)) {
2354                                 ret = clk_prepare_enable(ourport->baudclk);
2355                                 if (ret) {
2356                                         dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2357                                         clk_disable_unprepare(ourport->clk);
2358                                         return ret;
2359                                 }
2360                         }
2361
2362                         ucon = rd_regl(port, S3C2410_UCON);
2363
2364                         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2365                                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2366                                   APPLE_S5L_UCON_RXTO_ENA_MSK);
2367
2368                         if (ourport->tx_enabled)
2369                                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2370                         if (ourport->rx_enabled)
2371                                 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2372                                         APPLE_S5L_UCON_RXTO_ENA_MSK;
2373
2374                         wr_regl(port, S3C2410_UCON, ucon);
2375
2376                         if (!IS_ERR(ourport->baudclk))
2377                                 clk_disable_unprepare(ourport->baudclk);
2378                         clk_disable_unprepare(ourport->clk);
2379                         break;
2380                 }
2381                 default:
2382                         break;
2383                 }
2384         }
2385
2386         return 0;
2387 }
2388
2389 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2390         .suspend = s3c24xx_serial_suspend,
2391         .resume = s3c24xx_serial_resume,
2392         .resume_noirq = s3c24xx_serial_resume_noirq,
2393 };
2394 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
2395
2396 #else /* !CONFIG_PM_SLEEP */
2397
2398 #define SERIAL_SAMSUNG_PM_OPS   NULL
2399 #endif /* CONFIG_PM_SLEEP */
2400
2401 /* Console code */
2402
2403 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2404
2405 static struct uart_port *cons_uart;
2406
2407 static int
2408 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2409 {
2410         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2411         unsigned long ufstat, utrstat;
2412
2413         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2414                 /* fifo mode - check amount of data in fifo registers... */
2415
2416                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2417                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2418         }
2419
2420         /* in non-fifo mode, we go and use the tx buffer empty */
2421
2422         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2423         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2424 }
2425
2426 static bool
2427 s3c24xx_port_configured(unsigned int ucon)
2428 {
2429         /* consider the serial port configured if the tx/rx mode set */
2430         return (ucon & 0xf) != 0;
2431 }
2432
2433 #ifdef CONFIG_CONSOLE_POLL
2434 /*
2435  * Console polling routines for writing and reading from the uart while
2436  * in an interrupt or debug context.
2437  */
2438
2439 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2440 {
2441         const struct s3c24xx_uart_port *ourport = to_ourport(port);
2442         unsigned int ufstat;
2443
2444         ufstat = rd_regl(port, S3C2410_UFSTAT);
2445         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2446                 return NO_POLL_CHAR;
2447
2448         return rd_reg(port, S3C2410_URXH);
2449 }
2450
2451 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2452                 unsigned char c)
2453 {
2454         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2455         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2456
2457         /* not possible to xmit on unconfigured port */
2458         if (!s3c24xx_port_configured(ucon))
2459                 return;
2460
2461         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2462                 cpu_relax();
2463         wr_reg(port, S3C2410_UTXH, c);
2464 }
2465
2466 #endif /* CONFIG_CONSOLE_POLL */
2467
2468 static void
2469 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2470 {
2471         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2472
2473         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2474                 cpu_relax();
2475         wr_reg(port, S3C2410_UTXH, ch);
2476 }
2477
2478 static void
2479 s3c24xx_serial_console_write(struct console *co, const char *s,
2480                              unsigned int count)
2481 {
2482         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2483         unsigned long flags;
2484         bool locked = true;
2485
2486         /* not possible to xmit on unconfigured port */
2487         if (!s3c24xx_port_configured(ucon))
2488                 return;
2489
2490         if (cons_uart->sysrq)
2491                 locked = false;
2492         else if (oops_in_progress)
2493                 locked = spin_trylock_irqsave(&cons_uart->lock, flags);
2494         else
2495                 spin_lock_irqsave(&cons_uart->lock, flags);
2496
2497         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2498
2499         if (locked)
2500                 spin_unlock_irqrestore(&cons_uart->lock, flags);
2501 }
2502
2503 /* Shouldn't be __init, as it can be instantiated from other module */
2504 static void
2505 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2506                            int *parity, int *bits)
2507 {
2508         struct clk *clk;
2509         unsigned int ulcon;
2510         unsigned int ucon;
2511         unsigned int ubrdiv;
2512         unsigned long rate;
2513         unsigned int clk_sel;
2514         char clk_name[MAX_CLK_NAME_LENGTH];
2515
2516         ulcon  = rd_regl(port, S3C2410_ULCON);
2517         ucon   = rd_regl(port, S3C2410_UCON);
2518         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2519
2520         if (s3c24xx_port_configured(ucon)) {
2521                 switch (ulcon & S3C2410_LCON_CSMASK) {
2522                 case S3C2410_LCON_CS5:
2523                         *bits = 5;
2524                         break;
2525                 case S3C2410_LCON_CS6:
2526                         *bits = 6;
2527                         break;
2528                 case S3C2410_LCON_CS7:
2529                         *bits = 7;
2530                         break;
2531                 case S3C2410_LCON_CS8:
2532                 default:
2533                         *bits = 8;
2534                         break;
2535                 }
2536
2537                 switch (ulcon & S3C2410_LCON_PMASK) {
2538                 case S3C2410_LCON_PEVEN:
2539                         *parity = 'e';
2540                         break;
2541
2542                 case S3C2410_LCON_PODD:
2543                         *parity = 'o';
2544                         break;
2545
2546                 case S3C2410_LCON_PNONE:
2547                 default:
2548                         *parity = 'n';
2549                 }
2550
2551                 /* now calculate the baud rate */
2552
2553                 clk_sel = s3c24xx_serial_getsource(port);
2554                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2555
2556                 clk = clk_get(port->dev, clk_name);
2557                 if (!IS_ERR(clk))
2558                         rate = clk_get_rate(clk);
2559                 else
2560                         rate = 1;
2561
2562                 *baud = rate / (16 * (ubrdiv + 1));
2563                 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2564         }
2565 }
2566
2567 /* Shouldn't be __init, as it can be instantiated from other module */
2568 static int
2569 s3c24xx_serial_console_setup(struct console *co, char *options)
2570 {
2571         struct uart_port *port;
2572         int baud = 9600;
2573         int bits = 8;
2574         int parity = 'n';
2575         int flow = 'n';
2576
2577         /* is this a valid port */
2578
2579         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2580                 co->index = 0;
2581
2582         port = &s3c24xx_serial_ports[co->index].port;
2583
2584         /* is the port configured? */
2585
2586         if (port->mapbase == 0x0)
2587                 return -ENODEV;
2588
2589         cons_uart = port;
2590
2591         /*
2592          * Check whether an invalid uart number has been specified, and
2593          * if so, search for the first available port that does have
2594          * console support.
2595          */
2596         if (options)
2597                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2598         else
2599                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2600
2601         dev_dbg(port->dev, "baud %d\n", baud);
2602
2603         return uart_set_options(port, co, baud, parity, bits, flow);
2604 }
2605
2606 static struct console s3c24xx_serial_console = {
2607         .name           = S3C24XX_SERIAL_NAME,
2608         .device         = uart_console_device,
2609         .flags          = CON_PRINTBUFFER,
2610         .index          = -1,
2611         .write          = s3c24xx_serial_console_write,
2612         .setup          = s3c24xx_serial_console_setup,
2613         .data           = &s3c24xx_uart_drv,
2614 };
2615 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2616
2617 #ifdef CONFIG_CPU_S3C2410
2618 static const struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2619         .info = {
2620                 .name           = "Samsung S3C2410 UART",
2621                 .type           = TYPE_S3C24XX,
2622                 .port_type      = PORT_S3C2410,
2623                 .fifosize       = 16,
2624                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2625                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2626                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2627                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2628                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2629                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2630                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2631                 .num_clks       = 2,
2632                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2633                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2634         },
2635         .def_cfg = {
2636                 .ucon           = S3C2410_UCON_DEFAULT,
2637                 .ufcon          = S3C2410_UFCON_DEFAULT,
2638         },
2639 };
2640 #define S3C2410_SERIAL_DRV_DATA (&s3c2410_serial_drv_data)
2641 #else
2642 #define S3C2410_SERIAL_DRV_DATA NULL
2643 #endif
2644
2645 #ifdef CONFIG_CPU_S3C2412
2646 static const struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2647         .info = {
2648                 .name           = "Samsung S3C2412 UART",
2649                 .type           = TYPE_S3C24XX,
2650                 .port_type      = PORT_S3C2412,
2651                 .fifosize       = 64,
2652                 .has_divslot    = 1,
2653                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2654                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2655                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2656                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2657                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2658                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2659                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2660                 .num_clks       = 4,
2661                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2662                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2663         },
2664         .def_cfg = {
2665                 .ucon           = S3C2410_UCON_DEFAULT,
2666                 .ufcon          = S3C2410_UFCON_DEFAULT,
2667         },
2668 };
2669 #define S3C2412_SERIAL_DRV_DATA (&s3c2412_serial_drv_data)
2670 #else
2671 #define S3C2412_SERIAL_DRV_DATA NULL
2672 #endif
2673
2674 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2675         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2676 static const struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2677         .info = {
2678                 .name           = "Samsung S3C2440 UART",
2679                 .type           = TYPE_S3C24XX,
2680                 .port_type      = PORT_S3C2440,
2681                 .fifosize       = 64,
2682                 .has_divslot    = 1,
2683                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2684                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2685                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2686                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2687                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2688                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2689                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2690                 .num_clks       = 4,
2691                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2692                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2693                 .ucon_mask      = S3C2440_UCON0_DIVMASK,
2694         },
2695         .def_cfg = {
2696                 .ucon           = S3C2410_UCON_DEFAULT,
2697                 .ufcon          = S3C2410_UFCON_DEFAULT,
2698         },
2699 };
2700 #define S3C2440_SERIAL_DRV_DATA (&s3c2440_serial_drv_data)
2701 #else
2702 #define S3C2440_SERIAL_DRV_DATA NULL
2703 #endif
2704
2705 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2706 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2707         .info = {
2708                 .name           = "Samsung S3C6400 UART",
2709                 .type           = TYPE_S3C6400,
2710                 .port_type      = PORT_S3C6400,
2711                 .fifosize       = 64,
2712                 .has_divslot    = 1,
2713                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2714                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2715                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2716                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2717                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2718                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2719                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2720                 .num_clks       = 4,
2721                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2722                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2723         },
2724         .def_cfg = {
2725                 .ucon           = S3C2410_UCON_DEFAULT,
2726                 .ufcon          = S3C2410_UFCON_DEFAULT,
2727         },
2728 };
2729 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2730 #else
2731 #define S3C6400_SERIAL_DRV_DATA NULL
2732 #endif
2733
2734 #ifdef CONFIG_CPU_S5PV210
2735 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2736         .info = {
2737                 .name           = "Samsung S5PV210 UART",
2738                 .type           = TYPE_S3C6400,
2739                 .port_type      = PORT_S3C6400,
2740                 .has_divslot    = 1,
2741                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2742                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2743                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2744                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2745                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2746                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2747                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2748                 .num_clks       = 2,
2749                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2750                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2751         },
2752         .def_cfg = {
2753                 .ucon           = S5PV210_UCON_DEFAULT,
2754                 .ufcon          = S5PV210_UFCON_DEFAULT,
2755         },
2756         .fifosize = { 256, 64, 16, 16 },
2757 };
2758 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2759 #else
2760 #define S5PV210_SERIAL_DRV_DATA NULL
2761 #endif
2762
2763 #if defined(CONFIG_ARCH_EXYNOS)
2764 #define EXYNOS_COMMON_SERIAL_DRV_DATA()                         \
2765         .info = {                                               \
2766                 .name           = "Samsung Exynos UART",        \
2767                 .type           = TYPE_S3C6400,                 \
2768                 .port_type      = PORT_S3C6400,                 \
2769                 .has_divslot    = 1,                            \
2770                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2771                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2772                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2773                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2774                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2775                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2776                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2777                 .num_clks       = 1,                            \
2778                 .clksel_mask    = 0,                            \
2779                 .clksel_shift   = 0,                            \
2780         },                                                      \
2781         .def_cfg = {                                            \
2782                 .ucon           = S5PV210_UCON_DEFAULT,         \
2783                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2784                 .has_fracval    = 1,                            \
2785         }                                                       \
2786
2787 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2788         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2789         .fifosize = { 256, 64, 16, 16 },
2790 };
2791
2792 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2793         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2794         .fifosize = { 64, 256, 16, 256 },
2795 };
2796
2797 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2798         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2799         .fifosize = { 256, 64, 64, 64 },
2800 };
2801
2802 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2803 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2804 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2805
2806 #else
2807 #define EXYNOS4210_SERIAL_DRV_DATA NULL
2808 #define EXYNOS5433_SERIAL_DRV_DATA NULL
2809 #define EXYNOS850_SERIAL_DRV_DATA NULL
2810 #endif
2811
2812 #ifdef CONFIG_ARCH_APPLE
2813 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2814         .info = {
2815                 .name           = "Apple S5L UART",
2816                 .type           = TYPE_APPLE_S5L,
2817                 .port_type      = PORT_8250,
2818                 .fifosize       = 16,
2819                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2820                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2821                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2822                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2823                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2824                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2825                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2826                 .num_clks       = 1,
2827                 .clksel_mask    = 0,
2828                 .clksel_shift   = 0,
2829                 .ucon_mask      = APPLE_S5L_UCON_MASK,
2830         },
2831         .def_cfg = {
2832                 .ucon           = APPLE_S5L_UCON_DEFAULT,
2833                 .ufcon          = S3C2410_UFCON_DEFAULT,
2834         },
2835 };
2836 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2837 #else
2838 #define S5L_SERIAL_DRV_DATA NULL
2839 #endif
2840
2841 #if defined(CONFIG_ARCH_ARTPEC)
2842 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2843         .info = {
2844                 .name           = "Axis ARTPEC-8 UART",
2845                 .type           = TYPE_S3C6400,
2846                 .port_type      = PORT_S3C6400,
2847                 .fifosize       = 64,
2848                 .has_divslot    = 1,
2849                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2850                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2851                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2852                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2853                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2854                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2855                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2856                 .num_clks       = 1,
2857                 .clksel_mask    = 0,
2858                 .clksel_shift   = 0,
2859         },
2860         .def_cfg = {
2861                 .ucon           = S5PV210_UCON_DEFAULT,
2862                 .ufcon          = S5PV210_UFCON_DEFAULT,
2863                 .has_fracval    = 1,
2864         }
2865 };
2866 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2867 #else
2868 #define ARTPEC8_SERIAL_DRV_DATA (NULL)
2869 #endif
2870
2871 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2872         {
2873                 .name           = "s3c2410-uart",
2874                 .driver_data    = (kernel_ulong_t)S3C2410_SERIAL_DRV_DATA,
2875         }, {
2876                 .name           = "s3c2412-uart",
2877                 .driver_data    = (kernel_ulong_t)S3C2412_SERIAL_DRV_DATA,
2878         }, {
2879                 .name           = "s3c2440-uart",
2880                 .driver_data    = (kernel_ulong_t)S3C2440_SERIAL_DRV_DATA,
2881         }, {
2882                 .name           = "s3c6400-uart",
2883                 .driver_data    = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2884         }, {
2885                 .name           = "s5pv210-uart",
2886                 .driver_data    = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2887         }, {
2888                 .name           = "exynos4210-uart",
2889                 .driver_data    = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2890         }, {
2891                 .name           = "exynos5433-uart",
2892                 .driver_data    = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2893         }, {
2894                 .name           = "s5l-uart",
2895                 .driver_data    = (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2896         }, {
2897                 .name           = "exynos850-uart",
2898                 .driver_data    = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2899         }, {
2900                 .name           = "artpec8-uart",
2901                 .driver_data    = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2902         },
2903         { },
2904 };
2905 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2906
2907 #ifdef CONFIG_OF
2908 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2909         { .compatible = "samsung,s3c2410-uart",
2910                 .data = S3C2410_SERIAL_DRV_DATA },
2911         { .compatible = "samsung,s3c2412-uart",
2912                 .data = S3C2412_SERIAL_DRV_DATA },
2913         { .compatible = "samsung,s3c2440-uart",
2914                 .data = S3C2440_SERIAL_DRV_DATA },
2915         { .compatible = "samsung,s3c6400-uart",
2916                 .data = S3C6400_SERIAL_DRV_DATA },
2917         { .compatible = "samsung,s5pv210-uart",
2918                 .data = S5PV210_SERIAL_DRV_DATA },
2919         { .compatible = "samsung,exynos4210-uart",
2920                 .data = EXYNOS4210_SERIAL_DRV_DATA },
2921         { .compatible = "samsung,exynos5433-uart",
2922                 .data = EXYNOS5433_SERIAL_DRV_DATA },
2923         { .compatible = "apple,s5l-uart",
2924                 .data = S5L_SERIAL_DRV_DATA },
2925         { .compatible = "samsung,exynos850-uart",
2926                 .data = EXYNOS850_SERIAL_DRV_DATA },
2927         { .compatible = "axis,artpec8-uart",
2928                 .data = ARTPEC8_SERIAL_DRV_DATA },
2929         {},
2930 };
2931 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2932 #endif
2933
2934 static struct platform_driver samsung_serial_driver = {
2935         .probe          = s3c24xx_serial_probe,
2936         .remove         = s3c24xx_serial_remove,
2937         .id_table       = s3c24xx_serial_driver_ids,
2938         .driver         = {
2939                 .name   = "samsung-uart",
2940                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2941                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2942         },
2943 };
2944
2945 static int __init samsung_serial_init(void)
2946 {
2947         int ret;
2948
2949         s3c24xx_serial_register_console();
2950
2951         ret = platform_driver_register(&samsung_serial_driver);
2952         if (ret) {
2953                 s3c24xx_serial_unregister_console();
2954                 return ret;
2955         }
2956
2957         return 0;
2958 }
2959
2960 static void __exit samsung_serial_exit(void)
2961 {
2962         platform_driver_unregister(&samsung_serial_driver);
2963         s3c24xx_serial_unregister_console();
2964 }
2965
2966 module_init(samsung_serial_init);
2967 module_exit(samsung_serial_exit);
2968
2969 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2970 /*
2971  * Early console.
2972  */
2973
2974 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2975 {
2976         switch (port->iotype) {
2977         case UPIO_MEM:
2978                 writeb(val, portaddr(port, reg));
2979                 break;
2980         case UPIO_MEM32:
2981                 writel(val, portaddr(port, reg));
2982                 break;
2983         }
2984 }
2985
2986 struct samsung_early_console_data {
2987         u32 txfull_mask;
2988         u32 rxfifo_mask;
2989 };
2990
2991 static void samsung_early_busyuart(const struct uart_port *port)
2992 {
2993         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2994                 ;
2995 }
2996
2997 static void samsung_early_busyuart_fifo(const struct uart_port *port)
2998 {
2999         const struct samsung_early_console_data *data = port->private_data;
3000
3001         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
3002                 ;
3003 }
3004
3005 static void samsung_early_putc(struct uart_port *port, unsigned char c)
3006 {
3007         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
3008                 samsung_early_busyuart_fifo(port);
3009         else
3010                 samsung_early_busyuart(port);
3011
3012         wr_reg_barrier(port, S3C2410_UTXH, c);
3013 }
3014
3015 static void samsung_early_write(struct console *con, const char *s,
3016                                 unsigned int n)
3017 {
3018         struct earlycon_device *dev = con->data;
3019
3020         uart_console_write(&dev->port, s, n, samsung_early_putc);
3021 }
3022
3023 static int samsung_early_read(struct console *con, char *s, unsigned int n)
3024 {
3025         struct earlycon_device *dev = con->data;
3026         const struct samsung_early_console_data *data = dev->port.private_data;
3027         int ch, ufstat, num_read = 0;
3028
3029         while (num_read < n) {
3030                 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
3031                 if (!(ufstat & data->rxfifo_mask))
3032                         break;
3033                 ch = rd_reg(&dev->port, S3C2410_URXH);
3034                 if (ch == NO_POLL_CHAR)
3035                         break;
3036
3037                 s[num_read++] = ch;
3038         }
3039
3040         return num_read;
3041 }
3042
3043 static int __init samsung_early_console_setup(struct earlycon_device *device,
3044                                               const char *opt)
3045 {
3046         if (!device->port.membase)
3047                 return -ENODEV;
3048
3049         device->con->write = samsung_early_write;
3050         device->con->read = samsung_early_read;
3051         return 0;
3052 }
3053
3054 /* S3C2410 */
3055 static struct samsung_early_console_data s3c2410_early_console_data = {
3056         .txfull_mask = S3C2410_UFSTAT_TXFULL,
3057         .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
3058 };
3059
3060 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
3061                                               const char *opt)
3062 {
3063         device->port.private_data = &s3c2410_early_console_data;
3064         return samsung_early_console_setup(device, opt);
3065 }
3066
3067 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
3068                         s3c2410_early_console_setup);
3069
3070 /* S3C2412, S3C2440, S3C64xx */
3071 static struct samsung_early_console_data s3c2440_early_console_data = {
3072         .txfull_mask = S3C2440_UFSTAT_TXFULL,
3073         .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
3074 };
3075
3076 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
3077                                               const char *opt)
3078 {
3079         device->port.private_data = &s3c2440_early_console_data;
3080         return samsung_early_console_setup(device, opt);
3081 }
3082
3083 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
3084                         s3c2440_early_console_setup);
3085 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
3086                         s3c2440_early_console_setup);
3087 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
3088                         s3c2440_early_console_setup);
3089
3090 /* S5PV210, Exynos */
3091 static struct samsung_early_console_data s5pv210_early_console_data = {
3092         .txfull_mask = S5PV210_UFSTAT_TXFULL,
3093         .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
3094 };
3095
3096 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
3097                                               const char *opt)
3098 {
3099         device->port.private_data = &s5pv210_early_console_data;
3100         return samsung_early_console_setup(device, opt);
3101 }
3102
3103 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
3104                         s5pv210_early_console_setup);
3105 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
3106                         s5pv210_early_console_setup);
3107 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
3108                         s5pv210_early_console_setup);
3109
3110 /* Apple S5L */
3111 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
3112                                                 const char *opt)
3113 {
3114         /* Close enough to S3C2410 for earlycon... */
3115         device->port.private_data = &s3c2410_early_console_data;
3116
3117 #ifdef CONFIG_ARM64
3118         /* ... but we need to override the existing fixmap entry as nGnRnE */
3119         __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
3120                      __pgprot(PROT_DEVICE_nGnRnE));
3121 #endif
3122         return samsung_early_console_setup(device, opt);
3123 }
3124
3125 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
3126 #endif
3127
3128 MODULE_ALIAS("platform:samsung-uart");
3129 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
3130 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3131 MODULE_LICENSE("GPL v2");