drivers/tty/serial/samsung_tty.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7  */
   8
   9 /* Note on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22  */
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/math.h>
  28 #include <linux/module.h>
  29 #include <linux/ioport.h>
  30 #include <linux/io.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/init.h>
  33 #include <linux/sysrq.h>
  34 #include <linux/console.h>
  35 #include <linux/tty.h>
  36 #include <linux/tty_flip.h>
  37 #include <linux/serial_core.h>
  38 #include <linux/serial.h>
  39 #include <linux/serial_s3c.h>
  40 #include <linux/delay.h>
  41 #include <linux/clk.h>
  42 #include <linux/cpufreq.h>
  43 #include <linux/of.h>
  44 #include <asm/irq.h>
  45
  46 /* UART name and device definitions */
  47
  48 #define S3C24XX_SERIAL_NAME     "ttySAC"
  49 #define S3C24XX_SERIAL_MAJOR    204
  50 #define S3C24XX_SERIAL_MINOR    64
  51
  52 #ifdef CONFIG_ARM64
  53 #define UART_NR                 12
  54 #else
  55 #define UART_NR                 CONFIG_SERIAL_SAMSUNG_UARTS
  56 #endif
  57
  58 #define S3C24XX_TX_PIO                  1
  59 #define S3C24XX_TX_DMA                  2
  60 #define S3C24XX_RX_PIO                  1
  61 #define S3C24XX_RX_DMA                  2
  62
  63 /* flag to ignore all characters coming in */
  64 #define RXSTAT_DUMMY_READ (0x10000000)
  65
  66 enum s3c24xx_port_type {
  67         TYPE_S3C6400,
  68         TYPE_APPLE_S5L,
  69 };
  70
  71 struct s3c24xx_uart_info {
  72         const char              *name;
  73         enum s3c24xx_port_type  type;
  74         unsigned int            port_type;
  75         unsigned int            fifosize;
  76         unsigned long           rx_fifomask;
  77         unsigned long           rx_fifoshift;
  78         unsigned long           rx_fifofull;
  79         unsigned long           tx_fifomask;
  80         unsigned long           tx_fifoshift;
  81         unsigned long           tx_fifofull;
  82         unsigned int            def_clk_sel;
  83         unsigned long           num_clks;
  84         unsigned long           clksel_mask;
  85         unsigned long           clksel_shift;
  86         unsigned long           ucon_mask;
  87
  88         /* uart port features */
  89
  90         unsigned int            has_divslot:1;
  91 };
  92
  93 struct s3c24xx_serial_drv_data {
  94         const struct s3c24xx_uart_info  info;
  95         const struct s3c2410_uartcfg    def_cfg;
  96         const unsigned int              fifosize[UART_NR];
  97 };
  98
  99 struct s3c24xx_uart_dma {
 100         unsigned int                    rx_chan_id;
 101         unsigned int                    tx_chan_id;
 102
 103         struct dma_slave_config         rx_conf;
 104         struct dma_slave_config         tx_conf;
 105
 106         struct dma_chan                 *rx_chan;
 107         struct dma_chan                 *tx_chan;
 108
 109         dma_addr_t                      rx_addr;
 110         dma_addr_t                      tx_addr;
 111
 112         dma_cookie_t                    rx_cookie;
 113         dma_cookie_t                    tx_cookie;
 114
 115         char                            *rx_buf;
 116
 117         dma_addr_t                      tx_transfer_addr;
 118
 119         size_t                          rx_size;
 120         size_t                          tx_size;
 121
 122         struct dma_async_tx_descriptor  *tx_desc;
 123         struct dma_async_tx_descriptor  *rx_desc;
 124
 125         int                             tx_bytes_requested;
 126         int                             rx_bytes_requested;
 127 };
 128
 129 struct s3c24xx_uart_port {
 130         unsigned char                   rx_enabled;
 131         unsigned char                   tx_enabled;
 132         unsigned int                    pm_level;
 133         unsigned long                   baudclk_rate;
 134         unsigned int                    min_dma_size;
 135
 136         unsigned int                    rx_irq;
 137         unsigned int                    tx_irq;
 138
 139         unsigned int                    tx_in_progress;
 140         unsigned int                    tx_mode;
 141         unsigned int                    rx_mode;
 142
 143         const struct s3c24xx_uart_info  *info;
 144         struct clk                      *clk;
 145         struct clk                      *baudclk;
 146         struct uart_port                port;
 147         const struct s3c24xx_serial_drv_data    *drv_data;
 148
 149         /* reference to platform data */
 150         const struct s3c2410_uartcfg    *cfg;
 151
 152         struct s3c24xx_uart_dma         *dma;
 153 };
 154
 155 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport);
 156
 157 /* conversion functions */
 158
 159 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 160
 161 /* register access controls */
 162
 163 #define portaddr(port, reg) ((port)->membase + (reg))
 164 #define portaddrl(port, reg) \
 165         ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 166
 167 static u32 rd_reg(const struct uart_port *port, u32 reg)
 168 {
 169         switch (port->iotype) {
 170         case UPIO_MEM:
 171                 return readb_relaxed(portaddr(port, reg));
 172         case UPIO_MEM32:
 173                 return readl_relaxed(portaddr(port, reg));
 174         default:
 175                 return 0;
 176         }
 177         return 0;
 178 }
 179
 180 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 181
 182 static void wr_reg(const struct uart_port *port, u32 reg, u32 val)
 183 {
 184         switch (port->iotype) {
 185         case UPIO_MEM:
 186                 writeb_relaxed(val, portaddr(port, reg));
 187                 break;
 188         case UPIO_MEM32:
 189                 writel_relaxed(val, portaddr(port, reg));
 190                 break;
 191         }
 192 }
 193
 194 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 195
 196 /* Byte-order aware bit setting/clearing functions. */
 197
 198 static inline void s3c24xx_set_bit(const struct uart_port *port, int idx,
 199                                    unsigned int reg)
 200 {
 201         unsigned long flags;
 202         u32 val;
 203
 204         local_irq_save(flags);
 205         val = rd_regl(port, reg);
 206         val |= (1 << idx);
 207         wr_regl(port, reg, val);
 208         local_irq_restore(flags);
 209 }
 210
 211 static inline void s3c24xx_clear_bit(const struct uart_port *port, int idx,
 212                                      unsigned int reg)
 213 {
 214         unsigned long flags;
 215         u32 val;
 216
 217         local_irq_save(flags);
 218         val = rd_regl(port, reg);
 219         val &= ~(1 << idx);
 220         wr_regl(port, reg, val);
 221         local_irq_restore(flags);
 222 }
 223
 224 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 225 {
 226         return container_of(port, struct s3c24xx_uart_port, port);
 227 }
 228
 229 /* translate a port to the device name */
 230
 231 static inline const char *s3c24xx_serial_portname(const struct uart_port *port)
 232 {
 233         return to_platform_device(port->dev)->name;
 234 }
 235
 236 static int s3c24xx_serial_txempty_nofifo(const struct uart_port *port)
 237 {
 238         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 239 }
 240
 241 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 242 {
 243         struct s3c24xx_uart_port *ourport = to_ourport(port);
 244         unsigned long flags;
 245         unsigned int ucon, ufcon;
 246         int count = 10000;
 247
 248         uart_port_lock_irqsave(port, &flags);
 249
 250         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 251                 udelay(100);
 252
 253         ufcon = rd_regl(port, S3C2410_UFCON);
 254         ufcon |= S3C2410_UFCON_RESETRX;
 255         wr_regl(port, S3C2410_UFCON, ufcon);
 256
 257         ucon = rd_regl(port, S3C2410_UCON);
 258         ucon |= S3C2410_UCON_RXIRQMODE;
 259         wr_regl(port, S3C2410_UCON, ucon);
 260
 261         ourport->rx_enabled = 1;
 262         uart_port_unlock_irqrestore(port, flags);
 263 }
 264
 265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 266 {
 267         struct s3c24xx_uart_port *ourport = to_ourport(port);
 268         unsigned long flags;
 269         unsigned int ucon;
 270
 271         uart_port_lock_irqsave(port, &flags);
 272
 273         ucon = rd_regl(port, S3C2410_UCON);
 274         ucon &= ~S3C2410_UCON_RXIRQMODE;
 275         wr_regl(port, S3C2410_UCON, ucon);
 276
 277         ourport->rx_enabled = 0;
 278         uart_port_unlock_irqrestore(port, flags);
 279 }
 280
 281 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 282 {
 283         struct s3c24xx_uart_port *ourport = to_ourport(port);
 284         struct s3c24xx_uart_dma *dma = ourport->dma;
 285         struct dma_tx_state state;
 286         int count;
 287
 288         if (!ourport->tx_enabled)
 289                 return;
 290
 291         switch (ourport->info->type) {
 292         case TYPE_S3C6400:
 293                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 294                 break;
 295         case TYPE_APPLE_S5L:
 296                 s3c24xx_clear_bit(port, APPLE_S5L_UCON_TXTHRESH_ENA, S3C2410_UCON);
 297                 break;
 298         default:
 299                 disable_irq_nosync(ourport->tx_irq);
 300                 break;
 301         }
 302
 303         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 304                 dmaengine_pause(dma->tx_chan);
 305                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 306                 dmaengine_terminate_all(dma->tx_chan);
 307                 dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 308                                         dma->tx_transfer_addr, dma->tx_size,
 309                                         DMA_TO_DEVICE);
 310                 async_tx_ack(dma->tx_desc);
 311                 count = dma->tx_bytes_requested - state.residue;
 312                 uart_xmit_advance(port, count);
 313         }
 314
 315         ourport->tx_enabled = 0;
 316         ourport->tx_in_progress = 0;
 317
 318         if (port->flags & UPF_CONS_FLOW)
 319                 s3c24xx_serial_rx_enable(port);
 320
 321         ourport->tx_mode = 0;
 322 }
 323
 324 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 325
 326 static void s3c24xx_serial_tx_dma_complete(void *args)
 327 {
 328         struct s3c24xx_uart_port *ourport = args;
 329         struct uart_port *port = &ourport->port;
 330         struct circ_buf *xmit = &port->state->xmit;
 331         struct s3c24xx_uart_dma *dma = ourport->dma;
 332         struct dma_tx_state state;
 333         unsigned long flags;
 334         int count;
 335
 336         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 337         count = dma->tx_bytes_requested - state.residue;
 338         async_tx_ack(dma->tx_desc);
 339
 340         dma_sync_single_for_cpu(dma->tx_chan->device->dev,
 341                                 dma->tx_transfer_addr, dma->tx_size,
 342                                 DMA_TO_DEVICE);
 343
 344         uart_port_lock_irqsave(port, &flags);
 345
 346         uart_xmit_advance(port, count);
 347         ourport->tx_in_progress = 0;
 348
 349         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 350                 uart_write_wakeup(port);
 351
 352         s3c24xx_serial_start_next_tx(ourport);
 353         uart_port_unlock_irqrestore(port, flags);
 354 }
 355
 356 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 357 {
 358         const struct uart_port *port = &ourport->port;
 359         u32 ucon;
 360
 361         /* Mask Tx interrupt */
 362         switch (ourport->info->type) {
 363         case TYPE_S3C6400:
 364                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 365                 break;
 366         case TYPE_APPLE_S5L:
 367                 WARN_ON(1); // No DMA
 368                 break;
 369         default:
 370                 disable_irq_nosync(ourport->tx_irq);
 371                 break;
 372         }
 373
 374         /* Enable tx dma mode */
 375         ucon = rd_regl(port, S3C2410_UCON);
 376         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 377         ucon |= S3C64XX_UCON_TXBURST_1;
 378         ucon |= S3C64XX_UCON_TXMODE_DMA;
 379         wr_regl(port,  S3C2410_UCON, ucon);
 380
 381         ourport->tx_mode = S3C24XX_TX_DMA;
 382 }
 383
 384 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 385 {
 386         const struct uart_port *port = &ourport->port;
 387         u32 ucon, ufcon;
 388
 389         /* Set ufcon txtrig */
 390         ourport->tx_in_progress = S3C24XX_TX_PIO;
 391         ufcon = rd_regl(port, S3C2410_UFCON);
 392         wr_regl(port,  S3C2410_UFCON, ufcon);
 393
 394         /* Enable tx pio mode */
 395         ucon = rd_regl(port, S3C2410_UCON);
 396         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 397         ucon |= S3C64XX_UCON_TXMODE_CPU;
 398         wr_regl(port,  S3C2410_UCON, ucon);
 399
 400         /* Unmask Tx interrupt */
 401         switch (ourport->info->type) {
 402         case TYPE_S3C6400:
 403                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 404                                   S3C64XX_UINTM);
 405                 break;
 406         case TYPE_APPLE_S5L:
 407                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
 408                 wr_regl(port, S3C2410_UCON, ucon);
 409                 break;
 410         default:
 411                 enable_irq(ourport->tx_irq);
 412                 break;
 413         }
 414
 415         ourport->tx_mode = S3C24XX_TX_PIO;
 416
 417         /*
 418          * The Apple version only has edge triggered TX IRQs, so we need
 419          * to kick off the process by sending some characters here.
 420          */
 421         if (ourport->info->type == TYPE_APPLE_S5L)
 422                 s3c24xx_serial_tx_chars(ourport);
 423 }
 424
 425 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 426 {
 427         if (ourport->tx_mode != S3C24XX_TX_PIO)
 428                 enable_tx_pio(ourport);
 429 }
 430
 431 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 432                                       unsigned int count)
 433 {
 434         struct uart_port *port = &ourport->port;
 435         struct circ_buf *xmit = &port->state->xmit;
 436         struct s3c24xx_uart_dma *dma = ourport->dma;
 437
 438         if (ourport->tx_mode != S3C24XX_TX_DMA)
 439                 enable_tx_dma(ourport);
 440
 441         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 442         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 443
 444         dma_sync_single_for_device(dma->tx_chan->device->dev,
 445                                    dma->tx_transfer_addr, dma->tx_size,
 446                                    DMA_TO_DEVICE);
 447
 448         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 449                                 dma->tx_transfer_addr, dma->tx_size,
 450                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 451         if (!dma->tx_desc) {
 452                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 453                 return -EIO;
 454         }
 455
 456         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 457         dma->tx_desc->callback_param = ourport;
 458         dma->tx_bytes_requested = dma->tx_size;
 459
 460         ourport->tx_in_progress = S3C24XX_TX_DMA;
 461         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 462         dma_async_issue_pending(dma->tx_chan);
 463         return 0;
 464 }
 465
 466 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 467 {
 468         struct uart_port *port = &ourport->port;
 469         struct circ_buf *xmit = &port->state->xmit;
 470         unsigned long count;
 471
 472         /* Get data size up to the end of buffer */
 473         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 474
 475         if (!count) {
 476                 s3c24xx_serial_stop_tx(port);
 477                 return;
 478         }
 479
 480         if (!ourport->dma || !ourport->dma->tx_chan ||
 481             count < ourport->min_dma_size ||
 482             xmit->tail & (dma_get_cache_alignment() - 1))
 483                 s3c24xx_serial_start_tx_pio(ourport);
 484         else
 485                 s3c24xx_serial_start_tx_dma(ourport, count);
 486 }
 487
 488 static void s3c24xx_serial_start_tx(struct uart_port *port)
 489 {
 490         struct s3c24xx_uart_port *ourport = to_ourport(port);
 491         struct circ_buf *xmit = &port->state->xmit;
 492
 493         if (!ourport->tx_enabled) {
 494                 if (port->flags & UPF_CONS_FLOW)
 495                         s3c24xx_serial_rx_disable(port);
 496
 497                 ourport->tx_enabled = 1;
 498                 if (!ourport->dma || !ourport->dma->tx_chan)
 499                         s3c24xx_serial_start_tx_pio(ourport);
 500         }
 501
 502         if (ourport->dma && ourport->dma->tx_chan) {
 503                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 504                         s3c24xx_serial_start_next_tx(ourport);
 505         }
 506 }
 507
 508 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 509                 struct tty_port *tty, int count)
 510 {
 511         struct s3c24xx_uart_dma *dma = ourport->dma;
 512         int copied;
 513
 514         if (!count)
 515                 return;
 516
 517         dma_sync_single_for_cpu(dma->rx_chan->device->dev, dma->rx_addr,
 518                                 dma->rx_size, DMA_FROM_DEVICE);
 519
 520         ourport->port.icount.rx += count;
 521         if (!tty) {
 522                 dev_err(ourport->port.dev, "No tty port\n");
 523                 return;
 524         }
 525         copied = tty_insert_flip_string(tty,
 526                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 527         if (copied != count) {
 528                 WARN_ON(1);
 529                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 530         }
 531 }
 532
 533 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 534 {
 535         struct s3c24xx_uart_port *ourport = to_ourport(port);
 536         struct s3c24xx_uart_dma *dma = ourport->dma;
 537         struct tty_port *t = &port->state->port;
 538         struct dma_tx_state state;
 539         enum dma_status dma_status;
 540         unsigned int received;
 541
 542         if (ourport->rx_enabled) {
 543                 dev_dbg(port->dev, "stopping rx\n");
 544                 switch (ourport->info->type) {
 545                 case TYPE_S3C6400:
 546                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 547                                         S3C64XX_UINTM);
 548                         break;
 549                 case TYPE_APPLE_S5L:
 550                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
 551                         s3c24xx_clear_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
 552                         break;
 553                 default:
 554                         disable_irq_nosync(ourport->rx_irq);
 555                         break;
 556                 }
 557                 ourport->rx_enabled = 0;
 558         }
 559         if (dma && dma->rx_chan) {
 560                 dmaengine_pause(dma->tx_chan);
 561                 dma_status = dmaengine_tx_status(dma->rx_chan,
 562                                 dma->rx_cookie, &state);
 563                 if (dma_status == DMA_IN_PROGRESS ||
 564                         dma_status == DMA_PAUSED) {
 565                         received = dma->rx_bytes_requested - state.residue;
 566                         dmaengine_terminate_all(dma->rx_chan);
 567                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 568                 }
 569         }
 570 }
 571
 572 static inline const struct s3c24xx_uart_info
 573         *s3c24xx_port_to_info(struct uart_port *port)
 574 {
 575         return to_ourport(port)->info;
 576 }
 577
 578 static inline const struct s3c2410_uartcfg
 579         *s3c24xx_port_to_cfg(const struct uart_port *port)
 580 {
 581         const struct s3c24xx_uart_port *ourport;
 582
 583         if (port->dev == NULL)
 584                 return NULL;
 585
 586         ourport = container_of(port, struct s3c24xx_uart_port, port);
 587         return ourport->cfg;
 588 }
 589
 590 static int s3c24xx_serial_rx_fifocnt(const struct s3c24xx_uart_port *ourport,
 591                                      unsigned long ufstat)
 592 {
 593         const struct s3c24xx_uart_info *info = ourport->info;
 594
 595         if (ufstat & info->rx_fifofull)
 596                 return ourport->port.fifosize;
 597
 598         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 599 }
 600
 601 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 602 static void s3c24xx_serial_rx_dma_complete(void *args)
 603 {
 604         struct s3c24xx_uart_port *ourport = args;
 605         struct uart_port *port = &ourport->port;
 606
 607         struct s3c24xx_uart_dma *dma = ourport->dma;
 608         struct tty_port *t = &port->state->port;
 609         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 610
 611         struct dma_tx_state state;
 612         unsigned long flags;
 613         int received;
 614
 615         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 616         received  = dma->rx_bytes_requested - state.residue;
 617         async_tx_ack(dma->rx_desc);
 618
 619         uart_port_lock_irqsave(port, &flags);
 620
 621         if (received)
 622                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 623
 624         if (tty) {
 625                 tty_flip_buffer_push(t);
 626                 tty_kref_put(tty);
 627         }
 628
 629         s3c64xx_start_rx_dma(ourport);
 630
 631         uart_port_unlock_irqrestore(port, flags);
 632 }
 633
 634 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 635 {
 636         struct s3c24xx_uart_dma *dma = ourport->dma;
 637
 638         dma_sync_single_for_device(dma->rx_chan->device->dev, dma->rx_addr,
 639                                    dma->rx_size, DMA_FROM_DEVICE);
 640
 641         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 642                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 643                                 DMA_PREP_INTERRUPT);
 644         if (!dma->rx_desc) {
 645                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 646                 return;
 647         }
 648
 649         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 650         dma->rx_desc->callback_param = ourport;
 651         dma->rx_bytes_requested = dma->rx_size;
 652
 653         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 654         dma_async_issue_pending(dma->rx_chan);
 655 }
 656
 657 /* ? - where has parity gone?? */
 658 #define S3C2410_UERSTAT_PARITY (0x1000)
 659
 660 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 661 {
 662         struct uart_port *port = &ourport->port;
 663         unsigned int ucon;
 664
 665         /* set Rx mode to DMA mode */
 666         ucon = rd_regl(port, S3C2410_UCON);
 667         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 668                         S3C64XX_UCON_TIMEOUT_MASK |
 669                         S3C64XX_UCON_EMPTYINT_EN |
 670                         S3C64XX_UCON_DMASUS_EN |
 671                         S3C64XX_UCON_TIMEOUT_EN |
 672                         S3C64XX_UCON_RXMODE_MASK);
 673         ucon |= S3C64XX_UCON_RXBURST_1 |
 674                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 675                         S3C64XX_UCON_EMPTYINT_EN |
 676                         S3C64XX_UCON_TIMEOUT_EN |
 677                         S3C64XX_UCON_RXMODE_DMA;
 678         wr_regl(port, S3C2410_UCON, ucon);
 679
 680         ourport->rx_mode = S3C24XX_RX_DMA;
 681 }
 682
 683 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 684 {
 685         struct uart_port *port = &ourport->port;
 686         unsigned int ucon;
 687
 688         /* set Rx mode to DMA mode */
 689         ucon = rd_regl(port, S3C2410_UCON);
 690         ucon &= ~S3C64XX_UCON_RXMODE_MASK;
 691         ucon |= S3C64XX_UCON_RXMODE_CPU;
 692
 693         /* Apple types use these bits for IRQ masks */
 694         if (ourport->info->type != TYPE_APPLE_S5L) {
 695                 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 696                                 S3C64XX_UCON_EMPTYINT_EN |
 697                                 S3C64XX_UCON_DMASUS_EN |
 698                                 S3C64XX_UCON_TIMEOUT_EN);
 699                 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 700                                 S3C64XX_UCON_TIMEOUT_EN;
 701         }
 702         wr_regl(port, S3C2410_UCON, ucon);
 703
 704         ourport->rx_mode = S3C24XX_RX_PIO;
 705 }
 706
 707 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 708
 709 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 710 {
 711         unsigned int utrstat, received;
 712         struct s3c24xx_uart_port *ourport = dev_id;
 713         struct uart_port *port = &ourport->port;
 714         struct s3c24xx_uart_dma *dma = ourport->dma;
 715         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 716         struct tty_port *t = &port->state->port;
 717         struct dma_tx_state state;
 718
 719         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 720         rd_regl(port, S3C2410_UFSTAT);
 721
 722         uart_port_lock(port);
 723
 724         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 725                 s3c64xx_start_rx_dma(ourport);
 726                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 727                         enable_rx_dma(ourport);
 728                 goto finish;
 729         }
 730
 731         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 732                 dmaengine_pause(dma->rx_chan);
 733                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 734                 dmaengine_terminate_all(dma->rx_chan);
 735                 received = dma->rx_bytes_requested - state.residue;
 736                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 737
 738                 enable_rx_pio(ourport);
 739         }
 740
 741         s3c24xx_serial_rx_drain_fifo(ourport);
 742
 743         if (tty) {
 744                 tty_flip_buffer_push(t);
 745                 tty_kref_put(tty);
 746         }
 747
 748         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 749
 750 finish:
 751         uart_port_unlock(port);
 752
 753         return IRQ_HANDLED;
 754 }
 755
 756 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 757 {
 758         struct uart_port *port = &ourport->port;
 759         unsigned int ufcon, ufstat, uerstat;
 760         unsigned int fifocnt = 0;
 761         int max_count = port->fifosize;
 762         u8 ch, flag;
 763
 764         while (max_count-- > 0) {
 765                 /*
 766                  * Receive all characters known to be in FIFO
 767                  * before reading FIFO level again
 768                  */
 769                 if (fifocnt == 0) {
 770                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 771                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 772                         if (fifocnt == 0)
 773                                 break;
 774                 }
 775                 fifocnt--;
 776
 777                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 778                 ch = rd_reg(port, S3C2410_URXH);
 779
 780                 if (port->flags & UPF_CONS_FLOW) {
 781                         int txe = s3c24xx_serial_txempty_nofifo(port);
 782
 783                         if (ourport->rx_enabled) {
 784                                 if (!txe) {
 785                                         ourport->rx_enabled = 0;
 786                                         continue;
 787                                 }
 788                         } else {
 789                                 if (txe) {
 790                                         ufcon = rd_regl(port, S3C2410_UFCON);
 791                                         ufcon |= S3C2410_UFCON_RESETRX;
 792                                         wr_regl(port, S3C2410_UFCON, ufcon);
 793                                         ourport->rx_enabled = 1;
 794                                         return;
 795                                 }
 796                                 continue;
 797                         }
 798                 }
 799
 800                 /* insert the character into the buffer */
 801
 802                 flag = TTY_NORMAL;
 803                 port->icount.rx++;
 804
 805                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 806                         dev_dbg(port->dev,
 807                                 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
 808                                 ch, uerstat);
 809
 810                         /* check for break */
 811                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 812                                 dev_dbg(port->dev, "break!\n");
 813                                 port->icount.brk++;
 814                                 if (uart_handle_break(port))
 815                                         continue; /* Ignore character */
 816                         }
 817
 818                         if (uerstat & S3C2410_UERSTAT_FRAME)
 819                                 port->icount.frame++;
 820                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 821                                 port->icount.overrun++;
 822
 823                         uerstat &= port->read_status_mask;
 824
 825                         if (uerstat & S3C2410_UERSTAT_BREAK)
 826                                 flag = TTY_BREAK;
 827                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 828                                 flag = TTY_PARITY;
 829                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 830                                             S3C2410_UERSTAT_OVERRUN))
 831                                 flag = TTY_FRAME;
 832                 }
 833
 834                 if (uart_handle_sysrq_char(port, ch))
 835                         continue; /* Ignore character */
 836
 837                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 838                                  ch, flag);
 839         }
 840
 841         tty_flip_buffer_push(&port->state->port);
 842 }
 843
 844 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 845 {
 846         struct s3c24xx_uart_port *ourport = dev_id;
 847         struct uart_port *port = &ourport->port;
 848
 849         uart_port_lock(port);
 850         s3c24xx_serial_rx_drain_fifo(ourport);
 851         uart_port_unlock(port);
 852
 853         return IRQ_HANDLED;
 854 }
 855
 856 static irqreturn_t s3c24xx_serial_rx_irq(int irq, void *dev_id)
 857 {
 858         struct s3c24xx_uart_port *ourport = dev_id;
 859
 860         if (ourport->dma && ourport->dma->rx_chan)
 861                 return s3c24xx_serial_rx_chars_dma(dev_id);
 862         return s3c24xx_serial_rx_chars_pio(dev_id);
 863 }
 864
 865 static void s3c24xx_serial_tx_chars(struct s3c24xx_uart_port *ourport)
 866 {
 867         struct uart_port *port = &ourport->port;
 868         struct circ_buf *xmit = &port->state->xmit;
 869         int count, dma_count = 0;
 870
 871         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 872
 873         if (ourport->dma && ourport->dma->tx_chan &&
 874             count >= ourport->min_dma_size) {
 875                 int align = dma_get_cache_alignment() -
 876                         (xmit->tail & (dma_get_cache_alignment() - 1));
 877                 if (count - align >= ourport->min_dma_size) {
 878                         dma_count = count - align;
 879                         count = align;
 880                 }
 881         }
 882
 883         if (port->x_char) {
 884                 wr_reg(port, S3C2410_UTXH, port->x_char);
 885                 port->icount.tx++;
 886                 port->x_char = 0;
 887                 return;
 888         }
 889
 890         /* if there isn't anything more to transmit, or the uart is now
 891          * stopped, disable the uart and exit
 892          */
 893
 894         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 895                 s3c24xx_serial_stop_tx(port);
 896                 return;
 897         }
 898
 899         /* try and drain the buffer... */
 900
 901         if (count > port->fifosize) {
 902                 count = port->fifosize;
 903                 dma_count = 0;
 904         }
 905
 906         while (!uart_circ_empty(xmit) && count > 0) {
 907                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 908                         break;
 909
 910                 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 911                 uart_xmit_advance(port, 1);
 912                 count--;
 913         }
 914
 915         if (!count && dma_count) {
 916                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 917                 return;
 918         }
 919
 920         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 921                 uart_write_wakeup(port);
 922
 923         if (uart_circ_empty(xmit))
 924                 s3c24xx_serial_stop_tx(port);
 925 }
 926
 927 static irqreturn_t s3c24xx_serial_tx_irq(int irq, void *id)
 928 {
 929         struct s3c24xx_uart_port *ourport = id;
 930         struct uart_port *port = &ourport->port;
 931
 932         uart_port_lock(port);
 933
 934         s3c24xx_serial_tx_chars(ourport);
 935
 936         uart_port_unlock(port);
 937         return IRQ_HANDLED;
 938 }
 939
 940 /* interrupt handler for s3c64xx and later SoC's.*/
 941 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 942 {
 943         const struct s3c24xx_uart_port *ourport = id;
 944         const struct uart_port *port = &ourport->port;
 945         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 946         irqreturn_t ret = IRQ_HANDLED;
 947
 948         if (pend & S3C64XX_UINTM_RXD_MSK) {
 949                 ret = s3c24xx_serial_rx_irq(irq, id);
 950                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 951         }
 952         if (pend & S3C64XX_UINTM_TXD_MSK) {
 953                 ret = s3c24xx_serial_tx_irq(irq, id);
 954                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 955         }
 956         return ret;
 957 }
 958
 959 /* interrupt handler for Apple SoC's.*/
 960 static irqreturn_t apple_serial_handle_irq(int irq, void *id)
 961 {
 962         const struct s3c24xx_uart_port *ourport = id;
 963         const struct uart_port *port = &ourport->port;
 964         unsigned int pend = rd_regl(port, S3C2410_UTRSTAT);
 965         irqreturn_t ret = IRQ_NONE;
 966
 967         if (pend & (APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO)) {
 968                 wr_regl(port, S3C2410_UTRSTAT,
 969                         APPLE_S5L_UTRSTAT_RXTHRESH | APPLE_S5L_UTRSTAT_RXTO);
 970                 ret = s3c24xx_serial_rx_irq(irq, id);
 971         }
 972         if (pend & APPLE_S5L_UTRSTAT_TXTHRESH) {
 973                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_TXTHRESH);
 974                 ret = s3c24xx_serial_tx_irq(irq, id);
 975         }
 976
 977         return ret;
 978 }
 979
 980 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 981 {
 982         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 983         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 984         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 985
 986         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 987                 if ((ufstat & info->tx_fifomask) != 0 ||
 988                     (ufstat & info->tx_fifofull))
 989                         return 0;
 990                 return TIOCSER_TEMT;
 991         }
 992
 993         return s3c24xx_serial_txempty_nofifo(port) ? TIOCSER_TEMT : 0;
 994 }
 995
 996 /* no modem control lines */
 997 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 998 {
 999         unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
1000
1001         if (umstat & S3C2410_UMSTAT_CTS)
1002                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1003         else
1004                 return TIOCM_CAR | TIOCM_DSR;
1005 }
1006
1007 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
1008 {
1009         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
1010         unsigned int ucon = rd_regl(port, S3C2410_UCON);
1011
1012         if (mctrl & TIOCM_RTS)
1013                 umcon |= S3C2410_UMCOM_RTS_LOW;
1014         else
1015                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
1016
1017         wr_regl(port, S3C2410_UMCON, umcon);
1018
1019         if (mctrl & TIOCM_LOOP)
1020                 ucon |= S3C2410_UCON_LOOPBACK;
1021         else
1022                 ucon &= ~S3C2410_UCON_LOOPBACK;
1023
1024         wr_regl(port, S3C2410_UCON, ucon);
1025 }
1026
1027 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
1028 {
1029         unsigned long flags;
1030         unsigned int ucon;
1031
1032         uart_port_lock_irqsave(port, &flags);
1033
1034         ucon = rd_regl(port, S3C2410_UCON);
1035
1036         if (break_state)
1037                 ucon |= S3C2410_UCON_SBREAK;
1038         else
1039                 ucon &= ~S3C2410_UCON_SBREAK;
1040
1041         wr_regl(port, S3C2410_UCON, ucon);
1042
1043         uart_port_unlock_irqrestore(port, flags);
1044 }
1045
1046 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
1047 {
1048         struct s3c24xx_uart_dma *dma = p->dma;
1049         struct dma_slave_caps dma_caps;
1050         const char *reason = NULL;
1051         int ret;
1052
1053         /* Default slave configuration parameters */
1054         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
1055         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1056         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
1057         dma->rx_conf.src_maxburst       = 1;
1058
1059         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
1060         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
1061         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
1062         dma->tx_conf.dst_maxburst       = 1;
1063
1064         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
1065
1066         if (IS_ERR(dma->rx_chan)) {
1067                 reason = "DMA RX channel request failed";
1068                 ret = PTR_ERR(dma->rx_chan);
1069                 goto err_warn;
1070         }
1071
1072         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1073         if (ret < 0 ||
1074             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1075                 reason = "insufficient DMA RX engine capabilities";
1076                 ret = -EOPNOTSUPP;
1077                 goto err_release_rx;
1078         }
1079
1080         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1081
1082         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1083         if (IS_ERR(dma->tx_chan)) {
1084                 reason = "DMA TX channel request failed";
1085                 ret = PTR_ERR(dma->tx_chan);
1086                 goto err_release_rx;
1087         }
1088
1089         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1090         if (ret < 0 ||
1091             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1092                 reason = "insufficient DMA TX engine capabilities";
1093                 ret = -EOPNOTSUPP;
1094                 goto err_release_tx;
1095         }
1096
1097         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1098
1099         /* RX buffer */
1100         dma->rx_size = PAGE_SIZE;
1101
1102         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1103         if (!dma->rx_buf) {
1104                 ret = -ENOMEM;
1105                 goto err_release_tx;
1106         }
1107
1108         dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
1109                                       dma->rx_size, DMA_FROM_DEVICE);
1110         if (dma_mapping_error(dma->rx_chan->device->dev, dma->rx_addr)) {
1111                 reason = "DMA mapping error for RX buffer";
1112                 ret = -EIO;
1113                 goto err_free_rx;
1114         }
1115
1116         /* TX buffer */
1117         dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
1118                                       p->port.state->xmit.buf, UART_XMIT_SIZE,
1119                                       DMA_TO_DEVICE);
1120         if (dma_mapping_error(dma->tx_chan->device->dev, dma->tx_addr)) {
1121                 reason = "DMA mapping error for TX buffer";
1122                 ret = -EIO;
1123                 goto err_unmap_rx;
1124         }
1125
1126         return 0;
1127
1128 err_unmap_rx:
1129         dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1130                          dma->rx_size, DMA_FROM_DEVICE);
1131 err_free_rx:
1132         kfree(dma->rx_buf);
1133 err_release_tx:
1134         dma_release_channel(dma->tx_chan);
1135 err_release_rx:
1136         dma_release_channel(dma->rx_chan);
1137 err_warn:
1138         if (reason)
1139                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1140         return ret;
1141 }
1142
1143 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1144 {
1145         struct s3c24xx_uart_dma *dma = p->dma;
1146
1147         if (dma->rx_chan) {
1148                 dmaengine_terminate_all(dma->rx_chan);
1149                 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
1150                                  dma->rx_size, DMA_FROM_DEVICE);
1151                 kfree(dma->rx_buf);
1152                 dma_release_channel(dma->rx_chan);
1153                 dma->rx_chan = NULL;
1154         }
1155
1156         if (dma->tx_chan) {
1157                 dmaengine_terminate_all(dma->tx_chan);
1158                 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
1159                                  UART_XMIT_SIZE, DMA_TO_DEVICE);
1160                 dma_release_channel(dma->tx_chan);
1161                 dma->tx_chan = NULL;
1162         }
1163 }
1164
1165 static void s3c64xx_serial_shutdown(struct uart_port *port)
1166 {
1167         struct s3c24xx_uart_port *ourport = to_ourport(port);
1168
1169         ourport->tx_enabled = 0;
1170         ourport->tx_mode = 0;
1171         ourport->rx_enabled = 0;
1172
1173         free_irq(port->irq, ourport);
1174
1175         wr_regl(port, S3C64XX_UINTP, 0xf);
1176         wr_regl(port, S3C64XX_UINTM, 0xf);
1177
1178         if (ourport->dma)
1179                 s3c24xx_serial_release_dma(ourport);
1180
1181         ourport->tx_in_progress = 0;
1182 }
1183
1184 static void apple_s5l_serial_shutdown(struct uart_port *port)
1185 {
1186         struct s3c24xx_uart_port *ourport = to_ourport(port);
1187
1188         unsigned int ucon;
1189
1190         ucon = rd_regl(port, S3C2410_UCON);
1191         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1192                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1193                   APPLE_S5L_UCON_RXTO_ENA_MSK);
1194         wr_regl(port, S3C2410_UCON, ucon);
1195
1196         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1197
1198         free_irq(port->irq, ourport);
1199
1200         ourport->tx_enabled = 0;
1201         ourport->tx_mode = 0;
1202         ourport->rx_enabled = 0;
1203
1204         if (ourport->dma)
1205                 s3c24xx_serial_release_dma(ourport);
1206
1207         ourport->tx_in_progress = 0;
1208 }
1209
1210 static int s3c64xx_serial_startup(struct uart_port *port)
1211 {
1212         struct s3c24xx_uart_port *ourport = to_ourport(port);
1213         unsigned long flags;
1214         unsigned int ufcon;
1215         int ret;
1216
1217         wr_regl(port, S3C64XX_UINTM, 0xf);
1218         if (ourport->dma) {
1219                 ret = s3c24xx_serial_request_dma(ourport);
1220                 if (ret < 0) {
1221                         devm_kfree(port->dev, ourport->dma);
1222                         ourport->dma = NULL;
1223                 }
1224         }
1225
1226         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1227                           s3c24xx_serial_portname(port), ourport);
1228         if (ret) {
1229                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1230                 return ret;
1231         }
1232
1233         /* For compatibility with s3c24xx Soc's */
1234         ourport->rx_enabled = 1;
1235         ourport->tx_enabled = 0;
1236
1237         uart_port_lock_irqsave(port, &flags);
1238
1239         ufcon = rd_regl(port, S3C2410_UFCON);
1240         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1241         if (!uart_console(port))
1242                 ufcon |= S3C2410_UFCON_RESETTX;
1243         wr_regl(port, S3C2410_UFCON, ufcon);
1244
1245         enable_rx_pio(ourport);
1246
1247         uart_port_unlock_irqrestore(port, flags);
1248
1249         /* Enable Rx Interrupt */
1250         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1251
1252         return ret;
1253 }
1254
1255 static int apple_s5l_serial_startup(struct uart_port *port)
1256 {
1257         struct s3c24xx_uart_port *ourport = to_ourport(port);
1258         unsigned long flags;
1259         unsigned int ufcon;
1260         int ret;
1261
1262         wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1263
1264         ret = request_irq(port->irq, apple_serial_handle_irq, 0,
1265                           s3c24xx_serial_portname(port), ourport);
1266         if (ret) {
1267                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1268                 return ret;
1269         }
1270
1271         /* For compatibility with s3c24xx Soc's */
1272         ourport->rx_enabled = 1;
1273         ourport->tx_enabled = 0;
1274
1275         uart_port_lock_irqsave(port, &flags);
1276
1277         ufcon = rd_regl(port, S3C2410_UFCON);
1278         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1279         if (!uart_console(port))
1280                 ufcon |= S3C2410_UFCON_RESETTX;
1281         wr_regl(port, S3C2410_UFCON, ufcon);
1282
1283         enable_rx_pio(ourport);
1284
1285         uart_port_unlock_irqrestore(port, flags);
1286
1287         /* Enable Rx Interrupt */
1288         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON);
1289         s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTO_ENA, S3C2410_UCON);
1290
1291         return ret;
1292 }
1293
1294 /* power power management control */
1295
1296 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1297                               unsigned int old)
1298 {
1299         struct s3c24xx_uart_port *ourport = to_ourport(port);
1300         int timeout = 10000;
1301
1302         ourport->pm_level = level;
1303
1304         switch (level) {
1305         case 3:
1306                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1307                         udelay(100);
1308
1309                 if (!IS_ERR(ourport->baudclk))
1310                         clk_disable_unprepare(ourport->baudclk);
1311
1312                 clk_disable_unprepare(ourport->clk);
1313                 break;
1314
1315         case 0:
1316                 clk_prepare_enable(ourport->clk);
1317
1318                 if (!IS_ERR(ourport->baudclk))
1319                         clk_prepare_enable(ourport->baudclk);
1320                 break;
1321         default:
1322                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1323         }
1324 }
1325
1326 /* baud rate calculation
1327  *
1328  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1329  * of different sources, including the peripheral clock ("pclk") and an
1330  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1331  * with a programmable extra divisor.
1332  *
1333  * The following code goes through the clock sources, and calculates the
1334  * baud clocks (and the resultant actual baud rates) and then tries to
1335  * pick the closest one and select that.
1336  *
1337  */
1338
1339 #define MAX_CLK_NAME_LENGTH 15
1340
1341 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1342 {
1343         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1344         unsigned int ucon;
1345
1346         if (info->num_clks == 1)
1347                 return 0;
1348
1349         ucon = rd_regl(port, S3C2410_UCON);
1350         ucon &= info->clksel_mask;
1351         return ucon >> info->clksel_shift;
1352 }
1353
1354 static void s3c24xx_serial_setsource(struct uart_port *port,
1355                         unsigned int clk_sel)
1356 {
1357         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1358         unsigned int ucon;
1359
1360         if (info->num_clks == 1)
1361                 return;
1362
1363         ucon = rd_regl(port, S3C2410_UCON);
1364         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1365                 return;
1366
1367         ucon &= ~info->clksel_mask;
1368         ucon |= clk_sel << info->clksel_shift;
1369         wr_regl(port, S3C2410_UCON, ucon);
1370 }
1371
1372 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1373                         unsigned int req_baud, struct clk **best_clk,
1374                         unsigned int *clk_num)
1375 {
1376         const struct s3c24xx_uart_info *info = ourport->info;
1377         struct clk *clk;
1378         unsigned long rate;
1379         unsigned int cnt, baud, quot, best_quot = 0;
1380         char clkname[MAX_CLK_NAME_LENGTH];
1381         int calc_deviation, deviation = (1 << 30) - 1;
1382
1383         for (cnt = 0; cnt < info->num_clks; cnt++) {
1384                 /* Keep selected clock if provided */
1385                 if (ourport->cfg->clk_sel &&
1386                         !(ourport->cfg->clk_sel & (1 << cnt)))
1387                         continue;
1388
1389                 sprintf(clkname, "clk_uart_baud%d", cnt);
1390                 clk = clk_get(ourport->port.dev, clkname);
1391                 if (IS_ERR(clk))
1392                         continue;
1393
1394                 rate = clk_get_rate(clk);
1395                 if (!rate) {
1396                         dev_err(ourport->port.dev,
1397                                 "Failed to get clock rate for %s.\n", clkname);
1398                         clk_put(clk);
1399                         continue;
1400                 }
1401
1402                 if (ourport->info->has_divslot) {
1403                         unsigned long div = rate / req_baud;
1404
1405                         /* The UDIVSLOT register on the newer UARTs allows us to
1406                          * get a divisor adjustment of 1/16th on the baud clock.
1407                          *
1408                          * We don't keep the UDIVSLOT value (the 16ths we
1409                          * calculated by not multiplying the baud by 16) as it
1410                          * is easy enough to recalculate.
1411                          */
1412
1413                         quot = div / 16;
1414                         baud = rate / div;
1415                 } else {
1416                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1417                         baud = rate / (quot * 16);
1418                 }
1419                 quot--;
1420
1421                 calc_deviation = abs(req_baud - baud);
1422
1423                 if (calc_deviation < deviation) {
1424                         /*
1425                          * If we find a better clk, release the previous one, if
1426                          * any.
1427                          */
1428                         if (!IS_ERR(*best_clk))
1429                                 clk_put(*best_clk);
1430                         *best_clk = clk;
1431                         best_quot = quot;
1432                         *clk_num = cnt;
1433                         deviation = calc_deviation;
1434                 } else {
1435                         clk_put(clk);
1436                 }
1437         }
1438
1439         return best_quot;
1440 }
1441
1442 /* udivslot_table[]
1443  *
1444  * This table takes the fractional value of the baud divisor and gives
1445  * the recommended setting for the UDIVSLOT register.
1446  */
1447 static const u16 udivslot_table[16] = {
1448         [0] = 0x0000,
1449         [1] = 0x0080,
1450         [2] = 0x0808,
1451         [3] = 0x0888,
1452         [4] = 0x2222,
1453         [5] = 0x4924,
1454         [6] = 0x4A52,
1455         [7] = 0x54AA,
1456         [8] = 0x5555,
1457         [9] = 0xD555,
1458         [10] = 0xD5D5,
1459         [11] = 0xDDD5,
1460         [12] = 0xDDDD,
1461         [13] = 0xDFDD,
1462         [14] = 0xDFDF,
1463         [15] = 0xFFDF,
1464 };
1465
1466 static void s3c24xx_serial_set_termios(struct uart_port *port,
1467                                        struct ktermios *termios,
1468                                        const struct ktermios *old)
1469 {
1470         const struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1471         struct s3c24xx_uart_port *ourport = to_ourport(port);
1472         struct clk *clk = ERR_PTR(-EINVAL);
1473         unsigned long flags;
1474         unsigned int baud, quot, clk_sel = 0;
1475         unsigned int ulcon;
1476         unsigned int umcon;
1477         unsigned int udivslot = 0;
1478
1479         /*
1480          * We don't support modem control lines.
1481          */
1482         termios->c_cflag &= ~(HUPCL | CMSPAR);
1483         termios->c_cflag |= CLOCAL;
1484
1485         /*
1486          * Ask the core to calculate the divisor for us.
1487          */
1488
1489         baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1490         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1491         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1492                 quot = port->custom_divisor;
1493         if (IS_ERR(clk))
1494                 return;
1495
1496         /* check to see if we need  to change clock source */
1497
1498         if (ourport->baudclk != clk) {
1499                 clk_prepare_enable(clk);
1500
1501                 s3c24xx_serial_setsource(port, clk_sel);
1502
1503                 if (!IS_ERR(ourport->baudclk)) {
1504                         clk_disable_unprepare(ourport->baudclk);
1505                         ourport->baudclk = ERR_PTR(-EINVAL);
1506                 }
1507
1508                 ourport->baudclk = clk;
1509                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1510         }
1511
1512         if (ourport->info->has_divslot) {
1513                 unsigned int div = ourport->baudclk_rate / baud;
1514
1515                 if (cfg->has_fracval) {
1516                         udivslot = (div & 15);
1517                         dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1518                 } else {
1519                         udivslot = udivslot_table[div & 15];
1520                         dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1521                                 udivslot, div & 15);
1522                 }
1523         }
1524
1525         switch (termios->c_cflag & CSIZE) {
1526         case CS5:
1527                 dev_dbg(port->dev, "config: 5bits/char\n");
1528                 ulcon = S3C2410_LCON_CS5;
1529                 break;
1530         case CS6:
1531                 dev_dbg(port->dev, "config: 6bits/char\n");
1532                 ulcon = S3C2410_LCON_CS6;
1533                 break;
1534         case CS7:
1535                 dev_dbg(port->dev, "config: 7bits/char\n");
1536                 ulcon = S3C2410_LCON_CS7;
1537                 break;
1538         case CS8:
1539         default:
1540                 dev_dbg(port->dev, "config: 8bits/char\n");
1541                 ulcon = S3C2410_LCON_CS8;
1542                 break;
1543         }
1544
1545         /* preserve original lcon IR settings */
1546         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1547
1548         if (termios->c_cflag & CSTOPB)
1549                 ulcon |= S3C2410_LCON_STOPB;
1550
1551         if (termios->c_cflag & PARENB) {
1552                 if (termios->c_cflag & PARODD)
1553                         ulcon |= S3C2410_LCON_PODD;
1554                 else
1555                         ulcon |= S3C2410_LCON_PEVEN;
1556         } else {
1557                 ulcon |= S3C2410_LCON_PNONE;
1558         }
1559
1560         uart_port_lock_irqsave(port, &flags);
1561
1562         dev_dbg(port->dev,
1563                 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1564                 ulcon, quot, udivslot);
1565
1566         wr_regl(port, S3C2410_ULCON, ulcon);
1567         wr_regl(port, S3C2410_UBRDIV, quot);
1568
1569         port->status &= ~UPSTAT_AUTOCTS;
1570
1571         umcon = rd_regl(port, S3C2410_UMCON);
1572         if (termios->c_cflag & CRTSCTS) {
1573                 umcon |= S3C2410_UMCOM_AFC;
1574                 /* Disable RTS when RX FIFO contains 63 bytes */
1575                 umcon &= ~S3C2412_UMCON_AFC_8;
1576                 port->status = UPSTAT_AUTOCTS;
1577         } else {
1578                 umcon &= ~S3C2410_UMCOM_AFC;
1579         }
1580         wr_regl(port, S3C2410_UMCON, umcon);
1581
1582         if (ourport->info->has_divslot)
1583                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1584
1585         dev_dbg(port->dev,
1586                 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1587                 rd_regl(port, S3C2410_ULCON),
1588                 rd_regl(port, S3C2410_UCON),
1589                 rd_regl(port, S3C2410_UFCON));
1590
1591         /*
1592          * Update the per-port timeout.
1593          */
1594         uart_update_timeout(port, termios->c_cflag, baud);
1595
1596         /*
1597          * Which character status flags are we interested in?
1598          */
1599         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1600         if (termios->c_iflag & INPCK)
1601                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1602                         S3C2410_UERSTAT_PARITY;
1603         /*
1604          * Which character status flags should we ignore?
1605          */
1606         port->ignore_status_mask = 0;
1607         if (termios->c_iflag & IGNPAR)
1608                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1609         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1610                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1611
1612         /*
1613          * Ignore all characters if CREAD is not set.
1614          */
1615         if ((termios->c_cflag & CREAD) == 0)
1616                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1617
1618         uart_port_unlock_irqrestore(port, flags);
1619 }
1620
1621 static const char *s3c24xx_serial_type(struct uart_port *port)
1622 {
1623         const struct s3c24xx_uart_port *ourport = to_ourport(port);
1624
1625         switch (ourport->info->type) {
1626         case TYPE_S3C6400:
1627                 return "S3C6400/10";
1628         case TYPE_APPLE_S5L:
1629                 return "APPLE S5L";
1630         default:
1631                 return NULL;
1632         }
1633 }
1634
1635 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1636 {
1637         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1638
1639         if (flags & UART_CONFIG_TYPE)
1640                 port->type = info->port_type;
1641 }
1642
1643 /*
1644  * verify the new serial_struct (for TIOCSSERIAL).
1645  */
1646 static int
1647 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1648 {
1649         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1650
1651         if (ser->type != PORT_UNKNOWN && ser->type != info->port_type)
1652                 return -EINVAL;
1653
1654         return 0;
1655 }
1656
1657 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1658
1659 static struct console s3c24xx_serial_console;
1660
1661 static void __init s3c24xx_serial_register_console(void)
1662 {
1663         register_console(&s3c24xx_serial_console);
1664 }
1665
1666 static void s3c24xx_serial_unregister_console(void)
1667 {
1668         if (console_is_registered(&s3c24xx_serial_console))
1669                 unregister_console(&s3c24xx_serial_console);
1670 }
1671
1672 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1673 #else
1674 static inline void s3c24xx_serial_register_console(void) { }
1675 static inline void s3c24xx_serial_unregister_console(void) { }
1676 #define S3C24XX_SERIAL_CONSOLE NULL
1677 #endif
1678
1679 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1680 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1681 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1682                          unsigned char c);
1683 #endif
1684
1685 static const struct uart_ops s3c64xx_serial_ops = {
1686         .pm             = s3c24xx_serial_pm,
1687         .tx_empty       = s3c24xx_serial_tx_empty,
1688         .get_mctrl      = s3c24xx_serial_get_mctrl,
1689         .set_mctrl      = s3c24xx_serial_set_mctrl,
1690         .stop_tx        = s3c24xx_serial_stop_tx,
1691         .start_tx       = s3c24xx_serial_start_tx,
1692         .stop_rx        = s3c24xx_serial_stop_rx,
1693         .break_ctl      = s3c24xx_serial_break_ctl,
1694         .startup        = s3c64xx_serial_startup,
1695         .shutdown       = s3c64xx_serial_shutdown,
1696         .set_termios    = s3c24xx_serial_set_termios,
1697         .type           = s3c24xx_serial_type,
1698         .config_port    = s3c24xx_serial_config_port,
1699         .verify_port    = s3c24xx_serial_verify_port,
1700 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1701         .poll_get_char = s3c24xx_serial_get_poll_char,
1702         .poll_put_char = s3c24xx_serial_put_poll_char,
1703 #endif
1704 };
1705
1706 static const struct uart_ops apple_s5l_serial_ops = {
1707         .pm             = s3c24xx_serial_pm,
1708         .tx_empty       = s3c24xx_serial_tx_empty,
1709         .get_mctrl      = s3c24xx_serial_get_mctrl,
1710         .set_mctrl      = s3c24xx_serial_set_mctrl,
1711         .stop_tx        = s3c24xx_serial_stop_tx,
1712         .start_tx       = s3c24xx_serial_start_tx,
1713         .stop_rx        = s3c24xx_serial_stop_rx,
1714         .break_ctl      = s3c24xx_serial_break_ctl,
1715         .startup        = apple_s5l_serial_startup,
1716         .shutdown       = apple_s5l_serial_shutdown,
1717         .set_termios    = s3c24xx_serial_set_termios,
1718         .type           = s3c24xx_serial_type,
1719         .config_port    = s3c24xx_serial_config_port,
1720         .verify_port    = s3c24xx_serial_verify_port,
1721 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1722         .poll_get_char = s3c24xx_serial_get_poll_char,
1723         .poll_put_char = s3c24xx_serial_put_poll_char,
1724 #endif
1725 };
1726
1727 static struct uart_driver s3c24xx_uart_drv = {
1728         .owner          = THIS_MODULE,
1729         .driver_name    = "s3c2410_serial",
1730         .nr             = UART_NR,
1731         .cons           = S3C24XX_SERIAL_CONSOLE,
1732         .dev_name       = S3C24XX_SERIAL_NAME,
1733         .major          = S3C24XX_SERIAL_MAJOR,
1734         .minor          = S3C24XX_SERIAL_MINOR,
1735 };
1736
1737 static struct s3c24xx_uart_port s3c24xx_serial_ports[UART_NR];
1738
1739 static void s3c24xx_serial_init_port_default(int index) {
1740         struct uart_port *port = &s3c24xx_serial_ports[index].port;
1741
1742         spin_lock_init(&port->lock);
1743
1744         port->iotype = UPIO_MEM;
1745         port->uartclk = 0;
1746         port->fifosize = 16;
1747         port->flags = UPF_BOOT_AUTOCONF;
1748         port->line = index;
1749 }
1750
1751 /* s3c24xx_serial_resetport
1752  *
1753  * reset the fifos and other the settings.
1754  */
1755
1756 static void s3c24xx_serial_resetport(struct uart_port *port,
1757                                      const struct s3c2410_uartcfg *cfg)
1758 {
1759         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1760         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1761
1762         ucon &= (info->clksel_mask | info->ucon_mask);
1763         wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1764
1765         /* reset both fifos */
1766         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1767         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1768
1769         /* some delay is required after fifo reset */
1770         udelay(1);
1771 }
1772
1773 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1774 {
1775         struct device *dev = ourport->port.dev;
1776         const struct s3c24xx_uart_info *info = ourport->info;
1777         char clk_name[MAX_CLK_NAME_LENGTH];
1778         unsigned int clk_sel;
1779         struct clk *clk;
1780         int clk_num;
1781         int ret;
1782
1783         clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1784         for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1785                 if (!(clk_sel & (1 << clk_num)))
1786                         continue;
1787
1788                 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1789                 clk = clk_get(dev, clk_name);
1790                 if (IS_ERR(clk))
1791                         continue;
1792
1793                 ret = clk_prepare_enable(clk);
1794                 if (ret) {
1795                         clk_put(clk);
1796                         continue;
1797                 }
1798
1799                 ourport->baudclk = clk;
1800                 ourport->baudclk_rate = clk_get_rate(clk);
1801                 s3c24xx_serial_setsource(&ourport->port, clk_num);
1802
1803                 return 0;
1804         }
1805
1806         return -EINVAL;
1807 }
1808
1809 /* s3c24xx_serial_init_port
1810  *
1811  * initialise a single serial port from the platform device given
1812  */
1813
1814 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1815                                     struct platform_device *platdev)
1816 {
1817         struct uart_port *port = &ourport->port;
1818         const struct s3c2410_uartcfg *cfg = ourport->cfg;
1819         struct resource *res;
1820         int ret;
1821
1822         if (platdev == NULL)
1823                 return -ENODEV;
1824
1825         if (port->mapbase != 0)
1826                 return -EINVAL;
1827
1828         /* setup info for port */
1829         port->dev       = &platdev->dev;
1830
1831         port->uartclk = 1;
1832
1833         if (cfg->uart_flags & UPF_CONS_FLOW) {
1834                 dev_dbg(port->dev, "enabling flow control\n");
1835                 port->flags |= UPF_CONS_FLOW;
1836         }
1837
1838         /* sort our the physical and virtual addresses for each UART */
1839
1840         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1841         if (res == NULL) {
1842                 dev_err(port->dev, "failed to find memory resource for uart\n");
1843                 return -EINVAL;
1844         }
1845
1846         dev_dbg(port->dev, "resource %pR)\n", res);
1847
1848         port->membase = devm_ioremap_resource(port->dev, res);
1849         if (IS_ERR(port->membase)) {
1850                 dev_err(port->dev, "failed to remap controller address\n");
1851                 return -EBUSY;
1852         }
1853
1854         port->mapbase = res->start;
1855         ret = platform_get_irq(platdev, 0);
1856         if (ret < 0) {
1857                 port->irq = 0;
1858         } else {
1859                 port->irq = ret;
1860                 ourport->rx_irq = ret;
1861                 ourport->tx_irq = ret + 1;
1862         }
1863
1864         /*
1865          * DMA is currently supported only on DT platforms, if DMA properties
1866          * are specified.
1867          */
1868         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1869                                                      "dmas", NULL)) {
1870                 ourport->dma = devm_kzalloc(port->dev,
1871                                             sizeof(*ourport->dma),
1872                                             GFP_KERNEL);
1873                 if (!ourport->dma) {
1874                         ret = -ENOMEM;
1875                         goto err;
1876                 }
1877         }
1878
1879         ourport->clk    = clk_get(&platdev->dev, "uart");
1880         if (IS_ERR(ourport->clk)) {
1881                 pr_err("%s: Controller clock not found\n",
1882                                 dev_name(&platdev->dev));
1883                 ret = PTR_ERR(ourport->clk);
1884                 goto err;
1885         }
1886
1887         ret = clk_prepare_enable(ourport->clk);
1888         if (ret) {
1889                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1890                 clk_put(ourport->clk);
1891                 goto err;
1892         }
1893
1894         ret = s3c24xx_serial_enable_baudclk(ourport);
1895         if (ret)
1896                 pr_warn("uart: failed to enable baudclk\n");
1897
1898         /* Keep all interrupts masked and cleared */
1899         switch (ourport->info->type) {
1900         case TYPE_S3C6400:
1901                 wr_regl(port, S3C64XX_UINTM, 0xf);
1902                 wr_regl(port, S3C64XX_UINTP, 0xf);
1903                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1904                 break;
1905         case TYPE_APPLE_S5L: {
1906                 unsigned int ucon;
1907
1908                 ucon = rd_regl(port, S3C2410_UCON);
1909                 ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
1910                         APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
1911                         APPLE_S5L_UCON_RXTO_ENA_MSK);
1912                 wr_regl(port, S3C2410_UCON, ucon);
1913
1914                 wr_regl(port, S3C2410_UTRSTAT, APPLE_S5L_UTRSTAT_ALL_FLAGS);
1915                 break;
1916         }
1917         default:
1918                 break;
1919         }
1920
1921         dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1922                 &port->mapbase, port->membase, port->irq,
1923                 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1924
1925         /* reset the fifos (and setup the uart) */
1926         s3c24xx_serial_resetport(port, cfg);
1927
1928         return 0;
1929
1930 err:
1931         port->mapbase = 0;
1932         return ret;
1933 }
1934
1935 /* Device driver serial port probe */
1936
1937 static int probe_index;
1938
1939 static inline const struct s3c24xx_serial_drv_data *
1940 s3c24xx_get_driver_data(struct platform_device *pdev)
1941 {
1942         if (dev_of_node(&pdev->dev))
1943                 return of_device_get_match_data(&pdev->dev);
1944
1945         return (struct s3c24xx_serial_drv_data *)
1946                         platform_get_device_id(pdev)->driver_data;
1947 }
1948
1949 static int s3c24xx_serial_probe(struct platform_device *pdev)
1950 {
1951         struct device_node *np = pdev->dev.of_node;
1952         struct s3c24xx_uart_port *ourport;
1953         int index = probe_index;
1954         int ret, prop = 0;
1955
1956         if (np) {
1957                 ret = of_alias_get_id(np, "serial");
1958                 if (ret >= 0)
1959                         index = ret;
1960         }
1961
1962         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1963                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1964                 return -EINVAL;
1965         }
1966         ourport = &s3c24xx_serial_ports[index];
1967
1968         s3c24xx_serial_init_port_default(index);
1969
1970         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1971         if (!ourport->drv_data) {
1972                 dev_err(&pdev->dev, "could not find driver data\n");
1973                 return -ENODEV;
1974         }
1975
1976         ourport->baudclk = ERR_PTR(-EINVAL);
1977         ourport->info = &ourport->drv_data->info;
1978         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1979                         dev_get_platdata(&pdev->dev) :
1980                         &ourport->drv_data->def_cfg;
1981
1982         switch (ourport->info->type) {
1983         case TYPE_S3C6400:
1984                 ourport->port.ops = &s3c64xx_serial_ops;
1985                 break;
1986         case TYPE_APPLE_S5L:
1987                 ourport->port.ops = &apple_s5l_serial_ops;
1988                 break;
1989         }
1990
1991         if (np) {
1992                 of_property_read_u32(np,
1993                         "samsung,uart-fifosize", &ourport->port.fifosize);
1994
1995                 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
1996                         switch (prop) {
1997                         case 1:
1998                                 ourport->port.iotype = UPIO_MEM;
1999                                 break;
2000                         case 4:
2001                                 ourport->port.iotype = UPIO_MEM32;
2002                                 break;
2003                         default:
2004                                 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2005                                                 prop);
2006                                 return -EINVAL;
2007                         }
2008                 }
2009         }
2010
2011         if (ourport->drv_data->fifosize[index])
2012                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2013         else if (ourport->info->fifosize)
2014                 ourport->port.fifosize = ourport->info->fifosize;
2015         ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2016
2017         /*
2018          * DMA transfers must be aligned at least to cache line size,
2019          * so find minimal transfer size suitable for DMA mode
2020          */
2021         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2022                                     dma_get_cache_alignment());
2023
2024         dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2025
2026         ret = s3c24xx_serial_init_port(ourport, pdev);
2027         if (ret < 0)
2028                 return ret;
2029
2030         if (!s3c24xx_uart_drv.state) {
2031                 ret = uart_register_driver(&s3c24xx_uart_drv);
2032                 if (ret < 0) {
2033                         pr_err("Failed to register Samsung UART driver\n");
2034                         return ret;
2035                 }
2036         }
2037
2038         dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2039         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2040         platform_set_drvdata(pdev, &ourport->port);
2041
2042         /*
2043          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2044          * so that a potential re-enablement through the pm-callback overlaps
2045          * and keeps the clock enabled in this case.
2046          */
2047         clk_disable_unprepare(ourport->clk);
2048         if (!IS_ERR(ourport->baudclk))
2049                 clk_disable_unprepare(ourport->baudclk);
2050
2051         probe_index++;
2052
2053         return 0;
2054 }
2055
2056 static void s3c24xx_serial_remove(struct platform_device *dev)
2057 {
2058         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2059
2060         if (port) {
2061                 uart_remove_one_port(&s3c24xx_uart_drv, port);
2062         }
2063
2064         uart_unregister_driver(&s3c24xx_uart_drv);
2065 }
2066
2067 /* UART power management code */
2068 #ifdef CONFIG_PM_SLEEP
2069 static int s3c24xx_serial_suspend(struct device *dev)
2070 {
2071         struct uart_port *port = s3c24xx_dev_to_port(dev);
2072
2073         if (port)
2074                 uart_suspend_port(&s3c24xx_uart_drv, port);
2075
2076         return 0;
2077 }
2078
2079 static int s3c24xx_serial_resume(struct device *dev)
2080 {
2081         struct uart_port *port = s3c24xx_dev_to_port(dev);
2082         struct s3c24xx_uart_port *ourport = to_ourport(port);
2083
2084         if (port) {
2085                 clk_prepare_enable(ourport->clk);
2086                 if (!IS_ERR(ourport->baudclk))
2087                         clk_prepare_enable(ourport->baudclk);
2088                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2089                 if (!IS_ERR(ourport->baudclk))
2090                         clk_disable_unprepare(ourport->baudclk);
2091                 clk_disable_unprepare(ourport->clk);
2092
2093                 uart_resume_port(&s3c24xx_uart_drv, port);
2094         }
2095
2096         return 0;
2097 }
2098
2099 static int s3c24xx_serial_resume_noirq(struct device *dev)
2100 {
2101         struct uart_port *port = s3c24xx_dev_to_port(dev);
2102         struct s3c24xx_uart_port *ourport = to_ourport(port);
2103
2104         if (port) {
2105                 /* restore IRQ mask */
2106                 switch (ourport->info->type) {
2107                 case TYPE_S3C6400: {
2108                         unsigned int uintm = 0xf;
2109
2110                         if (ourport->tx_enabled)
2111                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2112                         if (ourport->rx_enabled)
2113                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2114                         clk_prepare_enable(ourport->clk);
2115                         if (!IS_ERR(ourport->baudclk))
2116                                 clk_prepare_enable(ourport->baudclk);
2117                         wr_regl(port, S3C64XX_UINTM, uintm);
2118                         if (!IS_ERR(ourport->baudclk))
2119                                 clk_disable_unprepare(ourport->baudclk);
2120                         clk_disable_unprepare(ourport->clk);
2121                         break;
2122                 }
2123                 case TYPE_APPLE_S5L: {
2124                         unsigned int ucon;
2125                         int ret;
2126
2127                         ret = clk_prepare_enable(ourport->clk);
2128                         if (ret) {
2129                                 dev_err(dev, "clk_enable clk failed: %d\n", ret);
2130                                 return ret;
2131                         }
2132                         if (!IS_ERR(ourport->baudclk)) {
2133                                 ret = clk_prepare_enable(ourport->baudclk);
2134                                 if (ret) {
2135                                         dev_err(dev, "clk_enable baudclk failed: %d\n", ret);
2136                                         clk_disable_unprepare(ourport->clk);
2137                                         return ret;
2138                                 }
2139                         }
2140
2141                         ucon = rd_regl(port, S3C2410_UCON);
2142
2143                         ucon &= ~(APPLE_S5L_UCON_TXTHRESH_ENA_MSK |
2144                                   APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2145                                   APPLE_S5L_UCON_RXTO_ENA_MSK);
2146
2147                         if (ourport->tx_enabled)
2148                                 ucon |= APPLE_S5L_UCON_TXTHRESH_ENA_MSK;
2149                         if (ourport->rx_enabled)
2150                                 ucon |= APPLE_S5L_UCON_RXTHRESH_ENA_MSK |
2151                                         APPLE_S5L_UCON_RXTO_ENA_MSK;
2152
2153                         wr_regl(port, S3C2410_UCON, ucon);
2154
2155                         if (!IS_ERR(ourport->baudclk))
2156                                 clk_disable_unprepare(ourport->baudclk);
2157                         clk_disable_unprepare(ourport->clk);
2158                         break;
2159                 }
2160                 default:
2161                         break;
2162                 }
2163         }
2164
2165         return 0;
2166 }
2167
2168 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2169         SET_SYSTEM_SLEEP_PM_OPS(s3c24xx_serial_suspend, s3c24xx_serial_resume)
2170         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, s3c24xx_serial_resume_noirq)
2171 };
2172 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
2173
2174 #else /* !CONFIG_PM_SLEEP */
2175
2176 #define SERIAL_SAMSUNG_PM_OPS   NULL
2177 #endif /* CONFIG_PM_SLEEP */
2178
2179 /* Console code */
2180
2181 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2182
2183 static struct uart_port *cons_uart;
2184
2185 static int
2186 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2187 {
2188         const struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2189         unsigned long ufstat, utrstat;
2190
2191         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2192                 /* fifo mode - check amount of data in fifo registers... */
2193
2194                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2195                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2196         }
2197
2198         /* in non-fifo mode, we go and use the tx buffer empty */
2199
2200         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2201         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2202 }
2203
2204 static bool
2205 s3c24xx_port_configured(unsigned int ucon)
2206 {
2207         /* consider the serial port configured if the tx/rx mode set */
2208         return (ucon & 0xf) != 0;
2209 }
2210
2211 #ifdef CONFIG_CONSOLE_POLL
2212 /*
2213  * Console polling routines for writing and reading from the uart while
2214  * in an interrupt or debug context.
2215  */
2216
2217 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2218 {
2219         const struct s3c24xx_uart_port *ourport = to_ourport(port);
2220         unsigned int ufstat;
2221
2222         ufstat = rd_regl(port, S3C2410_UFSTAT);
2223         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2224                 return NO_POLL_CHAR;
2225
2226         return rd_reg(port, S3C2410_URXH);
2227 }
2228
2229 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2230                 unsigned char c)
2231 {
2232         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2233         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2234
2235         /* not possible to xmit on unconfigured port */
2236         if (!s3c24xx_port_configured(ucon))
2237                 return;
2238
2239         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2240                 cpu_relax();
2241         wr_reg(port, S3C2410_UTXH, c);
2242 }
2243
2244 #endif /* CONFIG_CONSOLE_POLL */
2245
2246 static void
2247 s3c24xx_serial_console_putchar(struct uart_port *port, unsigned char ch)
2248 {
2249         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2250
2251         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2252                 cpu_relax();
2253         wr_reg(port, S3C2410_UTXH, ch);
2254 }
2255
2256 static void
2257 s3c24xx_serial_console_write(struct console *co, const char *s,
2258                              unsigned int count)
2259 {
2260         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2261         unsigned long flags;
2262         bool locked = true;
2263
2264         /* not possible to xmit on unconfigured port */
2265         if (!s3c24xx_port_configured(ucon))
2266                 return;
2267
2268         if (cons_uart->sysrq)
2269                 locked = false;
2270         else if (oops_in_progress)
2271                 locked = uart_port_trylock_irqsave(cons_uart, &flags);
2272         else
2273                 uart_port_lock_irqsave(cons_uart, &flags);
2274
2275         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2276
2277         if (locked)
2278                 uart_port_unlock_irqrestore(cons_uart, flags);
2279 }
2280
2281 /* Shouldn't be __init, as it can be instantiated from other module */
2282 static void
2283 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2284                            int *parity, int *bits)
2285 {
2286         struct clk *clk;
2287         unsigned int ulcon;
2288         unsigned int ucon;
2289         unsigned int ubrdiv;
2290         unsigned long rate;
2291         unsigned int clk_sel;
2292         char clk_name[MAX_CLK_NAME_LENGTH];
2293
2294         ulcon  = rd_regl(port, S3C2410_ULCON);
2295         ucon   = rd_regl(port, S3C2410_UCON);
2296         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2297
2298         if (s3c24xx_port_configured(ucon)) {
2299                 switch (ulcon & S3C2410_LCON_CSMASK) {
2300                 case S3C2410_LCON_CS5:
2301                         *bits = 5;
2302                         break;
2303                 case S3C2410_LCON_CS6:
2304                         *bits = 6;
2305                         break;
2306                 case S3C2410_LCON_CS7:
2307                         *bits = 7;
2308                         break;
2309                 case S3C2410_LCON_CS8:
2310                 default:
2311                         *bits = 8;
2312                         break;
2313                 }
2314
2315                 switch (ulcon & S3C2410_LCON_PMASK) {
2316                 case S3C2410_LCON_PEVEN:
2317                         *parity = 'e';
2318                         break;
2319
2320                 case S3C2410_LCON_PODD:
2321                         *parity = 'o';
2322                         break;
2323
2324                 case S3C2410_LCON_PNONE:
2325                 default:
2326                         *parity = 'n';
2327                 }
2328
2329                 /* now calculate the baud rate */
2330
2331                 clk_sel = s3c24xx_serial_getsource(port);
2332                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2333
2334                 clk = clk_get(port->dev, clk_name);
2335                 if (!IS_ERR(clk))
2336                         rate = clk_get_rate(clk);
2337                 else
2338                         rate = 1;
2339
2340                 *baud = rate / (16 * (ubrdiv + 1));
2341                 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2342         }
2343 }
2344
2345 /* Shouldn't be __init, as it can be instantiated from other module */
2346 static int
2347 s3c24xx_serial_console_setup(struct console *co, char *options)
2348 {
2349         struct uart_port *port;
2350         int baud = 9600;
2351         int bits = 8;
2352         int parity = 'n';
2353         int flow = 'n';
2354
2355         /* is this a valid port */
2356
2357         if (co->index == -1 || co->index >= UART_NR)
2358                 co->index = 0;
2359
2360         port = &s3c24xx_serial_ports[co->index].port;
2361
2362         /* is the port configured? */
2363
2364         if (port->mapbase == 0x0)
2365                 return -ENODEV;
2366
2367         cons_uart = port;
2368
2369         /*
2370          * Check whether an invalid uart number has been specified, and
2371          * if so, search for the first available port that does have
2372          * console support.
2373          */
2374         if (options)
2375                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2376         else
2377                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2378
2379         dev_dbg(port->dev, "baud %d\n", baud);
2380
2381         return uart_set_options(port, co, baud, parity, bits, flow);
2382 }
2383
2384 static struct console s3c24xx_serial_console = {
2385         .name           = S3C24XX_SERIAL_NAME,
2386         .device         = uart_console_device,
2387         .flags          = CON_PRINTBUFFER,
2388         .index          = -1,
2389         .write          = s3c24xx_serial_console_write,
2390         .setup          = s3c24xx_serial_console_setup,
2391         .data           = &s3c24xx_uart_drv,
2392 };
2393 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2394
2395 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2396 static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2397         .info = {
2398                 .name           = "Samsung S3C6400 UART",
2399                 .type           = TYPE_S3C6400,
2400                 .port_type      = PORT_S3C6400,
2401                 .fifosize       = 64,
2402                 .has_divslot    = 1,
2403                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2404                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2405                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2406                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2407                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2408                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2409                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2410                 .num_clks       = 4,
2411                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2412                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2413         },
2414         .def_cfg = {
2415                 .ucon           = S3C2410_UCON_DEFAULT,
2416                 .ufcon          = S3C2410_UFCON_DEFAULT,
2417         },
2418 };
2419 #define S3C6400_SERIAL_DRV_DATA (&s3c6400_serial_drv_data)
2420 #else
2421 #define S3C6400_SERIAL_DRV_DATA NULL
2422 #endif
2423
2424 #ifdef CONFIG_CPU_S5PV210
2425 static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2426         .info = {
2427                 .name           = "Samsung S5PV210 UART",
2428                 .type           = TYPE_S3C6400,
2429                 .port_type      = PORT_S3C6400,
2430                 .has_divslot    = 1,
2431                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2432                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2433                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2434                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2435                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2436                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2437                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2438                 .num_clks       = 2,
2439                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2440                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2441         },
2442         .def_cfg = {
2443                 .ucon           = S5PV210_UCON_DEFAULT,
2444                 .ufcon          = S5PV210_UFCON_DEFAULT,
2445         },
2446         .fifosize = { 256, 64, 16, 16 },
2447 };
2448 #define S5PV210_SERIAL_DRV_DATA (&s5pv210_serial_drv_data)
2449 #else
2450 #define S5PV210_SERIAL_DRV_DATA NULL
2451 #endif
2452
2453 #if defined(CONFIG_ARCH_EXYNOS)
2454 #define EXYNOS_COMMON_SERIAL_DRV_DATA()                         \
2455         .info = {                                               \
2456                 .name           = "Samsung Exynos UART",        \
2457                 .type           = TYPE_S3C6400,                 \
2458                 .port_type      = PORT_S3C6400,                 \
2459                 .has_divslot    = 1,                            \
2460                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2461                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2462                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2463                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2464                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2465                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2466                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2467                 .num_clks       = 1,                            \
2468                 .clksel_mask    = 0,                            \
2469                 .clksel_shift   = 0,                            \
2470         },                                                      \
2471         .def_cfg = {                                            \
2472                 .ucon           = S5PV210_UCON_DEFAULT,         \
2473                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2474                 .has_fracval    = 1,                            \
2475         }                                                       \
2476
2477 static const struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2478         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2479         .fifosize = { 256, 64, 16, 16 },
2480 };
2481
2482 static const struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2483         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2484         .fifosize = { 64, 256, 16, 256 },
2485 };
2486
2487 static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
2488         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2489         .fifosize = { 256, 64, 64, 64 },
2490 };
2491
2492 /*
2493  * Common drv_data struct for platforms that specify samsung,uart-fifosize in
2494  * device tree.
2495  */
2496 static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = {
2497         EXYNOS_COMMON_SERIAL_DRV_DATA(),
2498         .fifosize = { 0 },
2499 };
2500
2501 #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
2502 #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
2503 #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
2504 #define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data)
2505
2506 #else
2507 #define EXYNOS4210_SERIAL_DRV_DATA NULL
2508 #define EXYNOS5433_SERIAL_DRV_DATA NULL
2509 #define EXYNOS850_SERIAL_DRV_DATA NULL
2510 #define EXYNOS_FIFOSZDT_DRV_DATA NULL
2511 #endif
2512
2513 #ifdef CONFIG_ARCH_APPLE
2514 static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
2515         .info = {
2516                 .name           = "Apple S5L UART",
2517                 .type           = TYPE_APPLE_S5L,
2518                 .port_type      = PORT_8250,
2519                 .fifosize       = 16,
2520                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2521                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2522                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2523                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2524                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2525                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2526                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2527                 .num_clks       = 1,
2528                 .clksel_mask    = 0,
2529                 .clksel_shift   = 0,
2530                 .ucon_mask      = APPLE_S5L_UCON_MASK,
2531         },
2532         .def_cfg = {
2533                 .ucon           = APPLE_S5L_UCON_DEFAULT,
2534                 .ufcon          = S3C2410_UFCON_DEFAULT,
2535         },
2536 };
2537 #define S5L_SERIAL_DRV_DATA (&s5l_serial_drv_data)
2538 #else
2539 #define S5L_SERIAL_DRV_DATA NULL
2540 #endif
2541
2542 #if defined(CONFIG_ARCH_ARTPEC)
2543 static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
2544         .info = {
2545                 .name           = "Axis ARTPEC-8 UART",
2546                 .type           = TYPE_S3C6400,
2547                 .port_type      = PORT_S3C6400,
2548                 .fifosize       = 64,
2549                 .has_divslot    = 1,
2550                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2551                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2552                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2553                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2554                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2555                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2556                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2557                 .num_clks       = 1,
2558                 .clksel_mask    = 0,
2559                 .clksel_shift   = 0,
2560         },
2561         .def_cfg = {
2562                 .ucon           = S5PV210_UCON_DEFAULT,
2563                 .ufcon          = S5PV210_UFCON_DEFAULT,
2564                 .has_fracval    = 1,
2565         }
2566 };
2567 #define ARTPEC8_SERIAL_DRV_DATA (&artpec8_serial_drv_data)
2568 #else
2569 #define ARTPEC8_SERIAL_DRV_DATA (NULL)
2570 #endif
2571
2572 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2573         {
2574                 .name           = "s3c6400-uart",
2575                 .driver_data    = (kernel_ulong_t)S3C6400_SERIAL_DRV_DATA,
2576         }, {
2577                 .name           = "s5pv210-uart",
2578                 .driver_data    = (kernel_ulong_t)S5PV210_SERIAL_DRV_DATA,
2579         }, {
2580                 .name           = "exynos4210-uart",
2581                 .driver_data    = (kernel_ulong_t)EXYNOS4210_SERIAL_DRV_DATA,
2582         }, {
2583                 .name           = "exynos5433-uart",
2584                 .driver_data    = (kernel_ulong_t)EXYNOS5433_SERIAL_DRV_DATA,
2585         }, {
2586                 .name           = "s5l-uart",
2587                 .driver_data    = (kernel_ulong_t)S5L_SERIAL_DRV_DATA,
2588         }, {
2589                 .name           = "exynos850-uart",
2590                 .driver_data    = (kernel_ulong_t)EXYNOS850_SERIAL_DRV_DATA,
2591         }, {
2592                 .name           = "artpec8-uart",
2593                 .driver_data    = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
2594         }, {
2595                 .name           = "gs101-uart",
2596                 .driver_data    = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA,
2597         },
2598         { },
2599 };
2600 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2601
2602 #ifdef CONFIG_OF
2603 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2604         { .compatible = "samsung,s3c6400-uart",
2605                 .data = S3C6400_SERIAL_DRV_DATA },
2606         { .compatible = "samsung,s5pv210-uart",
2607                 .data = S5PV210_SERIAL_DRV_DATA },
2608         { .compatible = "samsung,exynos4210-uart",
2609                 .data = EXYNOS4210_SERIAL_DRV_DATA },
2610         { .compatible = "samsung,exynos5433-uart",
2611                 .data = EXYNOS5433_SERIAL_DRV_DATA },
2612         { .compatible = "apple,s5l-uart",
2613                 .data = S5L_SERIAL_DRV_DATA },
2614         { .compatible = "samsung,exynos850-uart",
2615                 .data = EXYNOS850_SERIAL_DRV_DATA },
2616         { .compatible = "axis,artpec8-uart",
2617                 .data = ARTPEC8_SERIAL_DRV_DATA },
2618         { .compatible = "google,gs101-uart",
2619                 .data = EXYNOS_FIFOSZDT_DRV_DATA },
2620         {},
2621 };
2622 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2623 #endif
2624
2625 static struct platform_driver samsung_serial_driver = {
2626         .probe          = s3c24xx_serial_probe,
2627         .remove_new     = s3c24xx_serial_remove,
2628         .id_table       = s3c24xx_serial_driver_ids,
2629         .driver         = {
2630                 .name   = "samsung-uart",
2631                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2632                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2633         },
2634 };
2635
2636 static int __init samsung_serial_init(void)
2637 {
2638         int ret;
2639
2640         s3c24xx_serial_register_console();
2641
2642         ret = platform_driver_register(&samsung_serial_driver);
2643         if (ret) {
2644                 s3c24xx_serial_unregister_console();
2645                 return ret;
2646         }
2647
2648         return 0;
2649 }
2650
2651 static void __exit samsung_serial_exit(void)
2652 {
2653         platform_driver_unregister(&samsung_serial_driver);
2654         s3c24xx_serial_unregister_console();
2655 }
2656
2657 module_init(samsung_serial_init);
2658 module_exit(samsung_serial_exit);
2659
2660 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2661 /*
2662  * Early console.
2663  */
2664
2665 static void wr_reg_barrier(const struct uart_port *port, u32 reg, u32 val)
2666 {
2667         switch (port->iotype) {
2668         case UPIO_MEM:
2669                 writeb(val, portaddr(port, reg));
2670                 break;
2671         case UPIO_MEM32:
2672                 writel(val, portaddr(port, reg));
2673                 break;
2674         }
2675 }
2676
2677 struct samsung_early_console_data {
2678         u32 txfull_mask;
2679         u32 rxfifo_mask;
2680 };
2681
2682 static void samsung_early_busyuart(const struct uart_port *port)
2683 {
2684         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2685                 ;
2686 }
2687
2688 static void samsung_early_busyuart_fifo(const struct uart_port *port)
2689 {
2690         const struct samsung_early_console_data *data = port->private_data;
2691
2692         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2693                 ;
2694 }
2695
2696 static void samsung_early_putc(struct uart_port *port, unsigned char c)
2697 {
2698         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2699                 samsung_early_busyuart_fifo(port);
2700         else
2701                 samsung_early_busyuart(port);
2702
2703         wr_reg_barrier(port, S3C2410_UTXH, c);
2704 }
2705
2706 static void samsung_early_write(struct console *con, const char *s,
2707                                 unsigned int n)
2708 {
2709         struct earlycon_device *dev = con->data;
2710
2711         uart_console_write(&dev->port, s, n, samsung_early_putc);
2712 }
2713
2714 static int samsung_early_read(struct console *con, char *s, unsigned int n)
2715 {
2716         struct earlycon_device *dev = con->data;
2717         const struct samsung_early_console_data *data = dev->port.private_data;
2718         int ch, ufstat, num_read = 0;
2719
2720         while (num_read < n) {
2721                 ufstat = rd_regl(&dev->port, S3C2410_UFSTAT);
2722                 if (!(ufstat & data->rxfifo_mask))
2723                         break;
2724                 ch = rd_reg(&dev->port, S3C2410_URXH);
2725                 if (ch == NO_POLL_CHAR)
2726                         break;
2727
2728                 s[num_read++] = ch;
2729         }
2730
2731         return num_read;
2732 }
2733
2734 static int __init samsung_early_console_setup(struct earlycon_device *device,
2735                                               const char *opt)
2736 {
2737         if (!device->port.membase)
2738                 return -ENODEV;
2739
2740         device->con->write = samsung_early_write;
2741         device->con->read = samsung_early_read;
2742         return 0;
2743 }
2744
2745 /* S3C2410 */
2746 static struct samsung_early_console_data s3c2410_early_console_data = {
2747         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2748         .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK,
2749 };
2750
2751 /* S3C64xx */
2752 static struct samsung_early_console_data s3c2440_early_console_data = {
2753         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2754         .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK,
2755 };
2756
2757 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2758                                               const char *opt)
2759 {
2760         device->port.private_data = &s3c2440_early_console_data;
2761         return samsung_early_console_setup(device, opt);
2762 }
2763
2764 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2765                         s3c2440_early_console_setup);
2766
2767 /* S5PV210, Exynos */
2768 static struct samsung_early_console_data s5pv210_early_console_data = {
2769         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2770         .rxfifo_mask = S5PV210_UFSTAT_RXFULL | S5PV210_UFSTAT_RXMASK,
2771 };
2772
2773 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2774                                               const char *opt)
2775 {
2776         device->port.private_data = &s5pv210_early_console_data;
2777         return samsung_early_console_setup(device, opt);
2778 }
2779
2780 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2781                         s5pv210_early_console_setup);
2782 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2783                         s5pv210_early_console_setup);
2784 OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
2785                         s5pv210_early_console_setup);
2786
2787 /* Apple S5L */
2788 static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
2789                                                 const char *opt)
2790 {
2791         /* Close enough to S3C2410 for earlycon... */
2792         device->port.private_data = &s3c2410_early_console_data;
2793
2794 #ifdef CONFIG_ARM64
2795         /* ... but we need to override the existing fixmap entry as nGnRnE */
2796         __set_fixmap(FIX_EARLYCON_MEM_BASE, device->port.mapbase,
2797                      __pgprot(PROT_DEVICE_nGnRnE));
2798 #endif
2799         return samsung_early_console_setup(device, opt);
2800 }
2801
2802 OF_EARLYCON_DECLARE(s5l, "apple,s5l-uart", apple_s5l_early_console_setup);
2803 #endif
2804
2805 MODULE_ALIAS("platform:samsung-uart");
2806 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2807 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2808 MODULE_LICENSE("GPL v2");