drivers/tty/serial/samsung_tty.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7  */
   8
   9 /* Note on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22  */
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/ioport.h>
  29 #include <linux/io.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/init.h>
  32 #include <linux/sysrq.h>
  33 #include <linux/console.h>
  34 #include <linux/tty.h>
  35 #include <linux/tty_flip.h>
  36 #include <linux/serial_core.h>
  37 #include <linux/serial.h>
  38 #include <linux/serial_s3c.h>
  39 #include <linux/delay.h>
  40 #include <linux/clk.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/of.h>
  43 #include <asm/irq.h>
  44
  45 /* UART name and device definitions */
  46
  47 #define S3C24XX_SERIAL_NAME     "ttySAC"
  48 #define S3C24XX_SERIAL_MAJOR    204
  49 #define S3C24XX_SERIAL_MINOR    64
  50
  51 #define S3C24XX_TX_PIO                  1
  52 #define S3C24XX_TX_DMA                  2
  53 #define S3C24XX_RX_PIO                  1
  54 #define S3C24XX_RX_DMA                  2
  55
  56 /* flag to ignore all characters coming in */
  57 #define RXSTAT_DUMMY_READ (0x10000000)
  58
  59 struct s3c24xx_uart_info {
  60         char                    *name;
  61         unsigned int            type;
  62         unsigned int            fifosize;
  63         unsigned long           rx_fifomask;
  64         unsigned long           rx_fifoshift;
  65         unsigned long           rx_fifofull;
  66         unsigned long           tx_fifomask;
  67         unsigned long           tx_fifoshift;
  68         unsigned long           tx_fifofull;
  69         unsigned int            def_clk_sel;
  70         unsigned long           num_clks;
  71         unsigned long           clksel_mask;
  72         unsigned long           clksel_shift;
  73
  74         /* uart port features */
  75
  76         unsigned int            has_divslot:1;
  77 };
  78
  79 struct s3c24xx_serial_drv_data {
  80         struct s3c24xx_uart_info        *info;
  81         struct s3c2410_uartcfg          *def_cfg;
  82         unsigned int                    fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
  83 };
  84
  85 struct s3c24xx_uart_dma {
  86         unsigned int                    rx_chan_id;
  87         unsigned int                    tx_chan_id;
  88
  89         struct dma_slave_config         rx_conf;
  90         struct dma_slave_config         tx_conf;
  91
  92         struct dma_chan                 *rx_chan;
  93         struct dma_chan                 *tx_chan;
  94
  95         dma_addr_t                      rx_addr;
  96         dma_addr_t                      tx_addr;
  97
  98         dma_cookie_t                    rx_cookie;
  99         dma_cookie_t                    tx_cookie;
 100
 101         char                            *rx_buf;
 102
 103         dma_addr_t                      tx_transfer_addr;
 104
 105         size_t                          rx_size;
 106         size_t                          tx_size;
 107
 108         struct dma_async_tx_descriptor  *tx_desc;
 109         struct dma_async_tx_descriptor  *rx_desc;
 110
 111         int                             tx_bytes_requested;
 112         int                             rx_bytes_requested;
 113 };
 114
 115 struct s3c24xx_uart_port {
 116         unsigned char                   rx_claimed;
 117         unsigned char                   tx_claimed;
 118         unsigned char                   rx_enabled;
 119         unsigned char                   tx_enabled;
 120         unsigned int                    pm_level;
 121         unsigned long                   baudclk_rate;
 122         unsigned int                    min_dma_size;
 123
 124         unsigned int                    rx_irq;
 125         unsigned int                    tx_irq;
 126
 127         unsigned int                    tx_in_progress;
 128         unsigned int                    tx_mode;
 129         unsigned int                    rx_mode;
 130
 131         struct s3c24xx_uart_info        *info;
 132         struct clk                      *clk;
 133         struct clk                      *baudclk;
 134         struct uart_port                port;
 135         struct s3c24xx_serial_drv_data  *drv_data;
 136
 137         /* reference to platform data */
 138         struct s3c2410_uartcfg          *cfg;
 139
 140         struct s3c24xx_uart_dma         *dma;
 141
 142 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 143         struct notifier_block           freq_transition;
 144 #endif
 145 };
 146
 147 /* conversion functions */
 148
 149 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 150
 151 /* register access controls */
 152
 153 #define portaddr(port, reg) ((port)->membase + (reg))
 154 #define portaddrl(port, reg) \
 155         ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 156
 157 static u32 rd_reg(struct uart_port *port, u32 reg)
 158 {
 159         switch (port->iotype) {
 160         case UPIO_MEM:
 161                 return readb_relaxed(portaddr(port, reg));
 162         case UPIO_MEM32:
 163                 return readl_relaxed(portaddr(port, reg));
 164         default:
 165                 return 0;
 166         }
 167         return 0;
 168 }
 169
 170 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 171
 172 static void wr_reg(struct uart_port *port, u32 reg, u32 val)
 173 {
 174         switch (port->iotype) {
 175         case UPIO_MEM:
 176                 writeb_relaxed(val, portaddr(port, reg));
 177                 break;
 178         case UPIO_MEM32:
 179                 writel_relaxed(val, portaddr(port, reg));
 180                 break;
 181         }
 182 }
 183
 184 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 185
 186 /* Byte-order aware bit setting/clearing functions. */
 187
 188 static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
 189                                    unsigned int reg)
 190 {
 191         unsigned long flags;
 192         u32 val;
 193
 194         local_irq_save(flags);
 195         val = rd_regl(port, reg);
 196         val |= (1 << idx);
 197         wr_regl(port, reg, val);
 198         local_irq_restore(flags);
 199 }
 200
 201 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
 202                                      unsigned int reg)
 203 {
 204         unsigned long flags;
 205         u32 val;
 206
 207         local_irq_save(flags);
 208         val = rd_regl(port, reg);
 209         val &= ~(1 << idx);
 210         wr_regl(port, reg, val);
 211         local_irq_restore(flags);
 212 }
 213
 214 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 215 {
 216         return container_of(port, struct s3c24xx_uart_port, port);
 217 }
 218
 219 /* translate a port to the device name */
 220
 221 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 222 {
 223         return to_platform_device(port->dev)->name;
 224 }
 225
 226 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 227 {
 228         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 229 }
 230
 231 /*
 232  * s3c64xx and later SoC's include the interrupt mask and status registers in
 233  * the controller itself, unlike the s3c24xx SoC's which have these registers
 234  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 235  */
 236 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 237 {
 238         return to_ourport(port)->info->type == PORT_S3C6400;
 239 }
 240
 241 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 242 {
 243         struct s3c24xx_uart_port *ourport = to_ourport(port);
 244         unsigned long flags;
 245         unsigned int ucon, ufcon;
 246         int count = 10000;
 247
 248         spin_lock_irqsave(&port->lock, flags);
 249
 250         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 251                 udelay(100);
 252
 253         ufcon = rd_regl(port, S3C2410_UFCON);
 254         ufcon |= S3C2410_UFCON_RESETRX;
 255         wr_regl(port, S3C2410_UFCON, ufcon);
 256
 257         ucon = rd_regl(port, S3C2410_UCON);
 258         ucon |= S3C2410_UCON_RXIRQMODE;
 259         wr_regl(port, S3C2410_UCON, ucon);
 260
 261         ourport->rx_enabled = 1;
 262         spin_unlock_irqrestore(&port->lock, flags);
 263 }
 264
 265 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 266 {
 267         struct s3c24xx_uart_port *ourport = to_ourport(port);
 268         unsigned long flags;
 269         unsigned int ucon;
 270
 271         spin_lock_irqsave(&port->lock, flags);
 272
 273         ucon = rd_regl(port, S3C2410_UCON);
 274         ucon &= ~S3C2410_UCON_RXIRQMODE;
 275         wr_regl(port, S3C2410_UCON, ucon);
 276
 277         ourport->rx_enabled = 0;
 278         spin_unlock_irqrestore(&port->lock, flags);
 279 }
 280
 281 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 282 {
 283         struct s3c24xx_uart_port *ourport = to_ourport(port);
 284         struct s3c24xx_uart_dma *dma = ourport->dma;
 285         struct circ_buf *xmit = &port->state->xmit;
 286         struct dma_tx_state state;
 287         int count;
 288
 289         if (!ourport->tx_enabled)
 290                 return;
 291
 292         if (s3c24xx_serial_has_interrupt_mask(port))
 293                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 294         else
 295                 disable_irq_nosync(ourport->tx_irq);
 296
 297         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 298                 dmaengine_pause(dma->tx_chan);
 299                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 300                 dmaengine_terminate_all(dma->tx_chan);
 301                 dma_sync_single_for_cpu(ourport->port.dev,
 302                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 303                 async_tx_ack(dma->tx_desc);
 304                 count = dma->tx_bytes_requested - state.residue;
 305                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 306                 port->icount.tx += count;
 307         }
 308
 309         ourport->tx_enabled = 0;
 310         ourport->tx_in_progress = 0;
 311
 312         if (port->flags & UPF_CONS_FLOW)
 313                 s3c24xx_serial_rx_enable(port);
 314
 315         ourport->tx_mode = 0;
 316 }
 317
 318 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 319
 320 static void s3c24xx_serial_tx_dma_complete(void *args)
 321 {
 322         struct s3c24xx_uart_port *ourport = args;
 323         struct uart_port *port = &ourport->port;
 324         struct circ_buf *xmit = &port->state->xmit;
 325         struct s3c24xx_uart_dma *dma = ourport->dma;
 326         struct dma_tx_state state;
 327         unsigned long flags;
 328         int count;
 329
 330         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 331         count = dma->tx_bytes_requested - state.residue;
 332         async_tx_ack(dma->tx_desc);
 333
 334         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 335                                 dma->tx_size, DMA_TO_DEVICE);
 336
 337         spin_lock_irqsave(&port->lock, flags);
 338
 339         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 340         port->icount.tx += count;
 341         ourport->tx_in_progress = 0;
 342
 343         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 344                 uart_write_wakeup(port);
 345
 346         s3c24xx_serial_start_next_tx(ourport);
 347         spin_unlock_irqrestore(&port->lock, flags);
 348 }
 349
 350 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 351 {
 352         struct uart_port *port = &ourport->port;
 353         u32 ucon;
 354
 355         /* Mask Tx interrupt */
 356         if (s3c24xx_serial_has_interrupt_mask(port))
 357                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 358         else
 359                 disable_irq_nosync(ourport->tx_irq);
 360
 361         /* Enable tx dma mode */
 362         ucon = rd_regl(port, S3C2410_UCON);
 363         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 364         ucon |= S3C64XX_UCON_TXBURST_1;
 365         ucon |= S3C64XX_UCON_TXMODE_DMA;
 366         wr_regl(port,  S3C2410_UCON, ucon);
 367
 368         ourport->tx_mode = S3C24XX_TX_DMA;
 369 }
 370
 371 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 372 {
 373         struct uart_port *port = &ourport->port;
 374         u32 ucon, ufcon;
 375
 376         /* Set ufcon txtrig */
 377         ourport->tx_in_progress = S3C24XX_TX_PIO;
 378         ufcon = rd_regl(port, S3C2410_UFCON);
 379         wr_regl(port,  S3C2410_UFCON, ufcon);
 380
 381         /* Enable tx pio mode */
 382         ucon = rd_regl(port, S3C2410_UCON);
 383         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 384         ucon |= S3C64XX_UCON_TXMODE_CPU;
 385         wr_regl(port,  S3C2410_UCON, ucon);
 386
 387         /* Unmask Tx interrupt */
 388         if (s3c24xx_serial_has_interrupt_mask(port))
 389                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 390                                   S3C64XX_UINTM);
 391         else
 392                 enable_irq(ourport->tx_irq);
 393
 394         ourport->tx_mode = S3C24XX_TX_PIO;
 395 }
 396
 397 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 398 {
 399         if (ourport->tx_mode != S3C24XX_TX_PIO)
 400                 enable_tx_pio(ourport);
 401 }
 402
 403 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 404                                       unsigned int count)
 405 {
 406         struct uart_port *port = &ourport->port;
 407         struct circ_buf *xmit = &port->state->xmit;
 408         struct s3c24xx_uart_dma *dma = ourport->dma;
 409
 410         if (ourport->tx_mode != S3C24XX_TX_DMA)
 411                 enable_tx_dma(ourport);
 412
 413         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 414         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 415
 416         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 417                                 dma->tx_size, DMA_TO_DEVICE);
 418
 419         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 420                                 dma->tx_transfer_addr, dma->tx_size,
 421                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 422         if (!dma->tx_desc) {
 423                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 424                 return -EIO;
 425         }
 426
 427         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 428         dma->tx_desc->callback_param = ourport;
 429         dma->tx_bytes_requested = dma->tx_size;
 430
 431         ourport->tx_in_progress = S3C24XX_TX_DMA;
 432         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 433         dma_async_issue_pending(dma->tx_chan);
 434         return 0;
 435 }
 436
 437 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 438 {
 439         struct uart_port *port = &ourport->port;
 440         struct circ_buf *xmit = &port->state->xmit;
 441         unsigned long count;
 442
 443         /* Get data size up to the end of buffer */
 444         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 445
 446         if (!count) {
 447                 s3c24xx_serial_stop_tx(port);
 448                 return;
 449         }
 450
 451         if (!ourport->dma || !ourport->dma->tx_chan ||
 452             count < ourport->min_dma_size ||
 453             xmit->tail & (dma_get_cache_alignment() - 1))
 454                 s3c24xx_serial_start_tx_pio(ourport);
 455         else
 456                 s3c24xx_serial_start_tx_dma(ourport, count);
 457 }
 458
 459 static void s3c24xx_serial_start_tx(struct uart_port *port)
 460 {
 461         struct s3c24xx_uart_port *ourport = to_ourport(port);
 462         struct circ_buf *xmit = &port->state->xmit;
 463
 464         if (!ourport->tx_enabled) {
 465                 if (port->flags & UPF_CONS_FLOW)
 466                         s3c24xx_serial_rx_disable(port);
 467
 468                 ourport->tx_enabled = 1;
 469                 if (!ourport->dma || !ourport->dma->tx_chan)
 470                         s3c24xx_serial_start_tx_pio(ourport);
 471         }
 472
 473         if (ourport->dma && ourport->dma->tx_chan) {
 474                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 475                         s3c24xx_serial_start_next_tx(ourport);
 476         }
 477 }
 478
 479 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 480                 struct tty_port *tty, int count)
 481 {
 482         struct s3c24xx_uart_dma *dma = ourport->dma;
 483         int copied;
 484
 485         if (!count)
 486                 return;
 487
 488         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 489                                 dma->rx_size, DMA_FROM_DEVICE);
 490
 491         ourport->port.icount.rx += count;
 492         if (!tty) {
 493                 dev_err(ourport->port.dev, "No tty port\n");
 494                 return;
 495         }
 496         copied = tty_insert_flip_string(tty,
 497                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 498         if (copied != count) {
 499                 WARN_ON(1);
 500                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 501         }
 502 }
 503
 504 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 505 {
 506         struct s3c24xx_uart_port *ourport = to_ourport(port);
 507         struct s3c24xx_uart_dma *dma = ourport->dma;
 508         struct tty_port *t = &port->state->port;
 509         struct dma_tx_state state;
 510         enum dma_status dma_status;
 511         unsigned int received;
 512
 513         if (ourport->rx_enabled) {
 514                 dev_dbg(port->dev, "stopping rx\n");
 515                 if (s3c24xx_serial_has_interrupt_mask(port))
 516                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 517                                         S3C64XX_UINTM);
 518                 else
 519                         disable_irq_nosync(ourport->rx_irq);
 520                 ourport->rx_enabled = 0;
 521         }
 522         if (dma && dma->rx_chan) {
 523                 dmaengine_pause(dma->tx_chan);
 524                 dma_status = dmaengine_tx_status(dma->rx_chan,
 525                                 dma->rx_cookie, &state);
 526                 if (dma_status == DMA_IN_PROGRESS ||
 527                         dma_status == DMA_PAUSED) {
 528                         received = dma->rx_bytes_requested - state.residue;
 529                         dmaengine_terminate_all(dma->rx_chan);
 530                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 531                 }
 532         }
 533 }
 534
 535 static inline struct s3c24xx_uart_info
 536         *s3c24xx_port_to_info(struct uart_port *port)
 537 {
 538         return to_ourport(port)->info;
 539 }
 540
 541 static inline struct s3c2410_uartcfg
 542         *s3c24xx_port_to_cfg(struct uart_port *port)
 543 {
 544         struct s3c24xx_uart_port *ourport;
 545
 546         if (port->dev == NULL)
 547                 return NULL;
 548
 549         ourport = container_of(port, struct s3c24xx_uart_port, port);
 550         return ourport->cfg;
 551 }
 552
 553 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 554                                      unsigned long ufstat)
 555 {
 556         struct s3c24xx_uart_info *info = ourport->info;
 557
 558         if (ufstat & info->rx_fifofull)
 559                 return ourport->port.fifosize;
 560
 561         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 562 }
 563
 564 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 565 static void s3c24xx_serial_rx_dma_complete(void *args)
 566 {
 567         struct s3c24xx_uart_port *ourport = args;
 568         struct uart_port *port = &ourport->port;
 569
 570         struct s3c24xx_uart_dma *dma = ourport->dma;
 571         struct tty_port *t = &port->state->port;
 572         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 573
 574         struct dma_tx_state state;
 575         unsigned long flags;
 576         int received;
 577
 578         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 579         received  = dma->rx_bytes_requested - state.residue;
 580         async_tx_ack(dma->rx_desc);
 581
 582         spin_lock_irqsave(&port->lock, flags);
 583
 584         if (received)
 585                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 586
 587         if (tty) {
 588                 tty_flip_buffer_push(t);
 589                 tty_kref_put(tty);
 590         }
 591
 592         s3c64xx_start_rx_dma(ourport);
 593
 594         spin_unlock_irqrestore(&port->lock, flags);
 595 }
 596
 597 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 598 {
 599         struct s3c24xx_uart_dma *dma = ourport->dma;
 600
 601         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 602                                 dma->rx_size, DMA_FROM_DEVICE);
 603
 604         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 605                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 606                                 DMA_PREP_INTERRUPT);
 607         if (!dma->rx_desc) {
 608                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 609                 return;
 610         }
 611
 612         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 613         dma->rx_desc->callback_param = ourport;
 614         dma->rx_bytes_requested = dma->rx_size;
 615
 616         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 617         dma_async_issue_pending(dma->rx_chan);
 618 }
 619
 620 /* ? - where has parity gone?? */
 621 #define S3C2410_UERSTAT_PARITY (0x1000)
 622
 623 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 624 {
 625         struct uart_port *port = &ourport->port;
 626         unsigned int ucon;
 627
 628         /* set Rx mode to DMA mode */
 629         ucon = rd_regl(port, S3C2410_UCON);
 630         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 631                         S3C64XX_UCON_TIMEOUT_MASK |
 632                         S3C64XX_UCON_EMPTYINT_EN |
 633                         S3C64XX_UCON_DMASUS_EN |
 634                         S3C64XX_UCON_TIMEOUT_EN |
 635                         S3C64XX_UCON_RXMODE_MASK);
 636         ucon |= S3C64XX_UCON_RXBURST_1 |
 637                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 638                         S3C64XX_UCON_EMPTYINT_EN |
 639                         S3C64XX_UCON_TIMEOUT_EN |
 640                         S3C64XX_UCON_RXMODE_DMA;
 641         wr_regl(port, S3C2410_UCON, ucon);
 642
 643         ourport->rx_mode = S3C24XX_RX_DMA;
 644 }
 645
 646 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 647 {
 648         struct uart_port *port = &ourport->port;
 649         unsigned int ucon;
 650
 651         /* set Rx mode to DMA mode */
 652         ucon = rd_regl(port, S3C2410_UCON);
 653         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 654                         S3C64XX_UCON_EMPTYINT_EN |
 655                         S3C64XX_UCON_DMASUS_EN |
 656                         S3C64XX_UCON_TIMEOUT_EN |
 657                         S3C64XX_UCON_RXMODE_MASK);
 658         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 659                         S3C64XX_UCON_TIMEOUT_EN |
 660                         S3C64XX_UCON_RXMODE_CPU;
 661         wr_regl(port, S3C2410_UCON, ucon);
 662
 663         ourport->rx_mode = S3C24XX_RX_PIO;
 664 }
 665
 666 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 667
 668 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 669 {
 670         unsigned int utrstat, received;
 671         struct s3c24xx_uart_port *ourport = dev_id;
 672         struct uart_port *port = &ourport->port;
 673         struct s3c24xx_uart_dma *dma = ourport->dma;
 674         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 675         struct tty_port *t = &port->state->port;
 676         unsigned long flags;
 677         struct dma_tx_state state;
 678
 679         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 680         rd_regl(port, S3C2410_UFSTAT);
 681
 682         spin_lock_irqsave(&port->lock, flags);
 683
 684         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 685                 s3c64xx_start_rx_dma(ourport);
 686                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 687                         enable_rx_dma(ourport);
 688                 goto finish;
 689         }
 690
 691         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 692                 dmaengine_pause(dma->rx_chan);
 693                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 694                 dmaengine_terminate_all(dma->rx_chan);
 695                 received = dma->rx_bytes_requested - state.residue;
 696                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 697
 698                 enable_rx_pio(ourport);
 699         }
 700
 701         s3c24xx_serial_rx_drain_fifo(ourport);
 702
 703         if (tty) {
 704                 tty_flip_buffer_push(t);
 705                 tty_kref_put(tty);
 706         }
 707
 708         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 709
 710 finish:
 711         spin_unlock_irqrestore(&port->lock, flags);
 712
 713         return IRQ_HANDLED;
 714 }
 715
 716 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 717 {
 718         struct uart_port *port = &ourport->port;
 719         unsigned int ufcon, ch, flag, ufstat, uerstat;
 720         unsigned int fifocnt = 0;
 721         int max_count = port->fifosize;
 722
 723         while (max_count-- > 0) {
 724                 /*
 725                  * Receive all characters known to be in FIFO
 726                  * before reading FIFO level again
 727                  */
 728                 if (fifocnt == 0) {
 729                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 730                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 731                         if (fifocnt == 0)
 732                                 break;
 733                 }
 734                 fifocnt--;
 735
 736                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 737                 ch = rd_reg(port, S3C2410_URXH);
 738
 739                 if (port->flags & UPF_CONS_FLOW) {
 740                         int txe = s3c24xx_serial_txempty_nofifo(port);
 741
 742                         if (ourport->rx_enabled) {
 743                                 if (!txe) {
 744                                         ourport->rx_enabled = 0;
 745                                         continue;
 746                                 }
 747                         } else {
 748                                 if (txe) {
 749                                         ufcon = rd_regl(port, S3C2410_UFCON);
 750                                         ufcon |= S3C2410_UFCON_RESETRX;
 751                                         wr_regl(port, S3C2410_UFCON, ufcon);
 752                                         ourport->rx_enabled = 1;
 753                                         return;
 754                                 }
 755                                 continue;
 756                         }
 757                 }
 758
 759                 /* insert the character into the buffer */
 760
 761                 flag = TTY_NORMAL;
 762                 port->icount.rx++;
 763
 764                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 765                         dev_dbg(port->dev,
 766                                 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
 767                                 ch, uerstat);
 768
 769                         /* check for break */
 770                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 771                                 dev_dbg(port->dev, "break!\n");
 772                                 port->icount.brk++;
 773                                 if (uart_handle_break(port))
 774                                         continue; /* Ignore character */
 775                         }
 776
 777                         if (uerstat & S3C2410_UERSTAT_FRAME)
 778                                 port->icount.frame++;
 779                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 780                                 port->icount.overrun++;
 781
 782                         uerstat &= port->read_status_mask;
 783
 784                         if (uerstat & S3C2410_UERSTAT_BREAK)
 785                                 flag = TTY_BREAK;
 786                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 787                                 flag = TTY_PARITY;
 788                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 789                                             S3C2410_UERSTAT_OVERRUN))
 790                                 flag = TTY_FRAME;
 791                 }
 792
 793                 if (uart_handle_sysrq_char(port, ch))
 794                         continue; /* Ignore character */
 795
 796                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 797                                  ch, flag);
 798         }
 799
 800         tty_flip_buffer_push(&port->state->port);
 801 }
 802
 803 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 804 {
 805         struct s3c24xx_uart_port *ourport = dev_id;
 806         struct uart_port *port = &ourport->port;
 807         unsigned long flags;
 808
 809         spin_lock_irqsave(&port->lock, flags);
 810         s3c24xx_serial_rx_drain_fifo(ourport);
 811         spin_unlock_irqrestore(&port->lock, flags);
 812
 813         return IRQ_HANDLED;
 814 }
 815
 816 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 817 {
 818         struct s3c24xx_uart_port *ourport = dev_id;
 819
 820         if (ourport->dma && ourport->dma->rx_chan)
 821                 return s3c24xx_serial_rx_chars_dma(dev_id);
 822         return s3c24xx_serial_rx_chars_pio(dev_id);
 823 }
 824
 825 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 826 {
 827         struct s3c24xx_uart_port *ourport = id;
 828         struct uart_port *port = &ourport->port;
 829         struct circ_buf *xmit = &port->state->xmit;
 830         unsigned long flags;
 831         int count, dma_count = 0;
 832
 833         spin_lock_irqsave(&port->lock, flags);
 834
 835         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 836
 837         if (ourport->dma && ourport->dma->tx_chan &&
 838             count >= ourport->min_dma_size) {
 839                 int align = dma_get_cache_alignment() -
 840                         (xmit->tail & (dma_get_cache_alignment() - 1));
 841                 if (count - align >= ourport->min_dma_size) {
 842                         dma_count = count - align;
 843                         count = align;
 844                 }
 845         }
 846
 847         if (port->x_char) {
 848                 wr_reg(port, S3C2410_UTXH, port->x_char);
 849                 port->icount.tx++;
 850                 port->x_char = 0;
 851                 goto out;
 852         }
 853
 854         /* if there isn't anything more to transmit, or the uart is now
 855          * stopped, disable the uart and exit
 856          */
 857
 858         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 859                 s3c24xx_serial_stop_tx(port);
 860                 goto out;
 861         }
 862
 863         /* try and drain the buffer... */
 864
 865         if (count > port->fifosize) {
 866                 count = port->fifosize;
 867                 dma_count = 0;
 868         }
 869
 870         while (!uart_circ_empty(xmit) && count > 0) {
 871                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 872                         break;
 873
 874                 wr_reg(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 875                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 876                 port->icount.tx++;
 877                 count--;
 878         }
 879
 880         if (!count && dma_count) {
 881                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 882                 goto out;
 883         }
 884
 885         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 886                 uart_write_wakeup(port);
 887
 888         if (uart_circ_empty(xmit))
 889                 s3c24xx_serial_stop_tx(port);
 890
 891 out:
 892         spin_unlock_irqrestore(&port->lock, flags);
 893         return IRQ_HANDLED;
 894 }
 895
 896 /* interrupt handler for s3c64xx and later SoC's.*/
 897 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 898 {
 899         struct s3c24xx_uart_port *ourport = id;
 900         struct uart_port *port = &ourport->port;
 901         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 902         irqreturn_t ret = IRQ_HANDLED;
 903
 904         if (pend & S3C64XX_UINTM_RXD_MSK) {
 905                 ret = s3c24xx_serial_rx_chars(irq, id);
 906                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 907         }
 908         if (pend & S3C64XX_UINTM_TXD_MSK) {
 909                 ret = s3c24xx_serial_tx_chars(irq, id);
 910                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 911         }
 912         return ret;
 913 }
 914
 915 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 916 {
 917         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 918         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 919         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 920
 921         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 922                 if ((ufstat & info->tx_fifomask) != 0 ||
 923                     (ufstat & info->tx_fifofull))
 924                         return 0;
 925
 926                 return 1;
 927         }
 928
 929         return s3c24xx_serial_txempty_nofifo(port);
 930 }
 931
 932 /* no modem control lines */
 933 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 934 {
 935         unsigned int umstat = rd_reg(port, S3C2410_UMSTAT);
 936
 937         if (umstat & S3C2410_UMSTAT_CTS)
 938                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 939         else
 940                 return TIOCM_CAR | TIOCM_DSR;
 941 }
 942
 943 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 944 {
 945         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 946
 947         if (mctrl & TIOCM_RTS)
 948                 umcon |= S3C2410_UMCOM_RTS_LOW;
 949         else
 950                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 951
 952         wr_regl(port, S3C2410_UMCON, umcon);
 953 }
 954
 955 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 956 {
 957         unsigned long flags;
 958         unsigned int ucon;
 959
 960         spin_lock_irqsave(&port->lock, flags);
 961
 962         ucon = rd_regl(port, S3C2410_UCON);
 963
 964         if (break_state)
 965                 ucon |= S3C2410_UCON_SBREAK;
 966         else
 967                 ucon &= ~S3C2410_UCON_SBREAK;
 968
 969         wr_regl(port, S3C2410_UCON, ucon);
 970
 971         spin_unlock_irqrestore(&port->lock, flags);
 972 }
 973
 974 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 975 {
 976         struct s3c24xx_uart_dma *dma = p->dma;
 977         struct dma_slave_caps dma_caps;
 978         const char *reason = NULL;
 979         int ret;
 980
 981         /* Default slave configuration parameters */
 982         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 983         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 984         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 985         dma->rx_conf.src_maxburst       = 1;
 986
 987         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 988         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 989         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 990         dma->tx_conf.dst_maxburst       = 1;
 991
 992         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 993
 994         if (IS_ERR(dma->rx_chan)) {
 995                 reason = "DMA RX channel request failed";
 996                 ret = PTR_ERR(dma->rx_chan);
 997                 goto err_warn;
 998         }
 999
1000         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
1001         if (ret < 0 ||
1002             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1003                 reason = "insufficient DMA RX engine capabilities";
1004                 ret = -EOPNOTSUPP;
1005                 goto err_release_rx;
1006         }
1007
1008         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
1009
1010         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
1011         if (IS_ERR(dma->tx_chan)) {
1012                 reason = "DMA TX channel request failed";
1013                 ret = PTR_ERR(dma->tx_chan);
1014                 goto err_release_rx;
1015         }
1016
1017         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1018         if (ret < 0 ||
1019             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1020                 reason = "insufficient DMA TX engine capabilities";
1021                 ret = -EOPNOTSUPP;
1022                 goto err_release_tx;
1023         }
1024
1025         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1026
1027         /* RX buffer */
1028         dma->rx_size = PAGE_SIZE;
1029
1030         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1031         if (!dma->rx_buf) {
1032                 ret = -ENOMEM;
1033                 goto err_release_tx;
1034         }
1035
1036         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
1037                                 dma->rx_size, DMA_FROM_DEVICE);
1038         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
1039                 reason = "DMA mapping error for RX buffer";
1040                 ret = -EIO;
1041                 goto err_free_rx;
1042         }
1043
1044         /* TX buffer */
1045         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
1046                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1047         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
1048                 reason = "DMA mapping error for TX buffer";
1049                 ret = -EIO;
1050                 goto err_unmap_rx;
1051         }
1052
1053         return 0;
1054
1055 err_unmap_rx:
1056         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
1057                          DMA_FROM_DEVICE);
1058 err_free_rx:
1059         kfree(dma->rx_buf);
1060 err_release_tx:
1061         dma_release_channel(dma->tx_chan);
1062 err_release_rx:
1063         dma_release_channel(dma->rx_chan);
1064 err_warn:
1065         if (reason)
1066                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1067         return ret;
1068 }
1069
1070 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1071 {
1072         struct s3c24xx_uart_dma *dma = p->dma;
1073
1074         if (dma->rx_chan) {
1075                 dmaengine_terminate_all(dma->rx_chan);
1076                 dma_unmap_single(p->port.dev, dma->rx_addr,
1077                                 dma->rx_size, DMA_FROM_DEVICE);
1078                 kfree(dma->rx_buf);
1079                 dma_release_channel(dma->rx_chan);
1080                 dma->rx_chan = NULL;
1081         }
1082
1083         if (dma->tx_chan) {
1084                 dmaengine_terminate_all(dma->tx_chan);
1085                 dma_unmap_single(p->port.dev, dma->tx_addr,
1086                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1087                 dma_release_channel(dma->tx_chan);
1088                 dma->tx_chan = NULL;
1089         }
1090 }
1091
1092 static void s3c24xx_serial_shutdown(struct uart_port *port)
1093 {
1094         struct s3c24xx_uart_port *ourport = to_ourport(port);
1095
1096         if (ourport->tx_claimed) {
1097                 if (!s3c24xx_serial_has_interrupt_mask(port))
1098                         free_irq(ourport->tx_irq, ourport);
1099                 ourport->tx_enabled = 0;
1100                 ourport->tx_claimed = 0;
1101                 ourport->tx_mode = 0;
1102         }
1103
1104         if (ourport->rx_claimed) {
1105                 if (!s3c24xx_serial_has_interrupt_mask(port))
1106                         free_irq(ourport->rx_irq, ourport);
1107                 ourport->rx_claimed = 0;
1108                 ourport->rx_enabled = 0;
1109         }
1110
1111         /* Clear pending interrupts and mask all interrupts */
1112         if (s3c24xx_serial_has_interrupt_mask(port)) {
1113                 free_irq(port->irq, ourport);
1114
1115                 wr_regl(port, S3C64XX_UINTP, 0xf);
1116                 wr_regl(port, S3C64XX_UINTM, 0xf);
1117         }
1118
1119         if (ourport->dma)
1120                 s3c24xx_serial_release_dma(ourport);
1121
1122         ourport->tx_in_progress = 0;
1123 }
1124
1125 static int s3c24xx_serial_startup(struct uart_port *port)
1126 {
1127         struct s3c24xx_uart_port *ourport = to_ourport(port);
1128         int ret;
1129
1130         ourport->rx_enabled = 1;
1131
1132         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1133                           s3c24xx_serial_portname(port), ourport);
1134
1135         if (ret != 0) {
1136                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1137                 return ret;
1138         }
1139
1140         ourport->rx_claimed = 1;
1141
1142         dev_dbg(port->dev, "requesting tx irq...\n");
1143
1144         ourport->tx_enabled = 1;
1145
1146         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1147                           s3c24xx_serial_portname(port), ourport);
1148
1149         if (ret) {
1150                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1151                 goto err;
1152         }
1153
1154         ourport->tx_claimed = 1;
1155
1156         /* the port reset code should have done the correct
1157          * register setup for the port controls
1158          */
1159
1160         return ret;
1161
1162 err:
1163         s3c24xx_serial_shutdown(port);
1164         return ret;
1165 }
1166
1167 static int s3c64xx_serial_startup(struct uart_port *port)
1168 {
1169         struct s3c24xx_uart_port *ourport = to_ourport(port);
1170         unsigned long flags;
1171         unsigned int ufcon;
1172         int ret;
1173
1174         wr_regl(port, S3C64XX_UINTM, 0xf);
1175         if (ourport->dma) {
1176                 ret = s3c24xx_serial_request_dma(ourport);
1177                 if (ret < 0) {
1178                         devm_kfree(port->dev, ourport->dma);
1179                         ourport->dma = NULL;
1180                 }
1181         }
1182
1183         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1184                           s3c24xx_serial_portname(port), ourport);
1185         if (ret) {
1186                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1187                 return ret;
1188         }
1189
1190         /* For compatibility with s3c24xx Soc's */
1191         ourport->rx_enabled = 1;
1192         ourport->rx_claimed = 1;
1193         ourport->tx_enabled = 0;
1194         ourport->tx_claimed = 1;
1195
1196         spin_lock_irqsave(&port->lock, flags);
1197
1198         ufcon = rd_regl(port, S3C2410_UFCON);
1199         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1200         if (!uart_console(port))
1201                 ufcon |= S3C2410_UFCON_RESETTX;
1202         wr_regl(port, S3C2410_UFCON, ufcon);
1203
1204         enable_rx_pio(ourport);
1205
1206         spin_unlock_irqrestore(&port->lock, flags);
1207
1208         /* Enable Rx Interrupt */
1209         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1210
1211         return ret;
1212 }
1213
1214 /* power power management control */
1215
1216 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1217                               unsigned int old)
1218 {
1219         struct s3c24xx_uart_port *ourport = to_ourport(port);
1220         int timeout = 10000;
1221
1222         ourport->pm_level = level;
1223
1224         switch (level) {
1225         case 3:
1226                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1227                         udelay(100);
1228
1229                 if (!IS_ERR(ourport->baudclk))
1230                         clk_disable_unprepare(ourport->baudclk);
1231
1232                 clk_disable_unprepare(ourport->clk);
1233                 break;
1234
1235         case 0:
1236                 clk_prepare_enable(ourport->clk);
1237
1238                 if (!IS_ERR(ourport->baudclk))
1239                         clk_prepare_enable(ourport->baudclk);
1240
1241                 break;
1242         default:
1243                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1244         }
1245 }
1246
1247 /* baud rate calculation
1248  *
1249  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1250  * of different sources, including the peripheral clock ("pclk") and an
1251  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1252  * with a programmable extra divisor.
1253  *
1254  * The following code goes through the clock sources, and calculates the
1255  * baud clocks (and the resultant actual baud rates) and then tries to
1256  * pick the closest one and select that.
1257  *
1258  */
1259
1260 #define MAX_CLK_NAME_LENGTH 15
1261
1262 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1263 {
1264         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1265         unsigned int ucon;
1266
1267         if (info->num_clks == 1)
1268                 return 0;
1269
1270         ucon = rd_regl(port, S3C2410_UCON);
1271         ucon &= info->clksel_mask;
1272         return ucon >> info->clksel_shift;
1273 }
1274
1275 static void s3c24xx_serial_setsource(struct uart_port *port,
1276                         unsigned int clk_sel)
1277 {
1278         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1279         unsigned int ucon;
1280
1281         if (info->num_clks == 1)
1282                 return;
1283
1284         ucon = rd_regl(port, S3C2410_UCON);
1285         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1286                 return;
1287
1288         ucon &= ~info->clksel_mask;
1289         ucon |= clk_sel << info->clksel_shift;
1290         wr_regl(port, S3C2410_UCON, ucon);
1291 }
1292
1293 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1294                         unsigned int req_baud, struct clk **best_clk,
1295                         unsigned int *clk_num)
1296 {
1297         struct s3c24xx_uart_info *info = ourport->info;
1298         struct clk *clk;
1299         unsigned long rate;
1300         unsigned int cnt, baud, quot, best_quot = 0;
1301         char clkname[MAX_CLK_NAME_LENGTH];
1302         int calc_deviation, deviation = (1 << 30) - 1;
1303
1304         for (cnt = 0; cnt < info->num_clks; cnt++) {
1305                 /* Keep selected clock if provided */
1306                 if (ourport->cfg->clk_sel &&
1307                         !(ourport->cfg->clk_sel & (1 << cnt)))
1308                         continue;
1309
1310                 sprintf(clkname, "clk_uart_baud%d", cnt);
1311                 clk = clk_get(ourport->port.dev, clkname);
1312                 if (IS_ERR(clk))
1313                         continue;
1314
1315                 rate = clk_get_rate(clk);
1316                 if (!rate)
1317                         continue;
1318
1319                 if (ourport->info->has_divslot) {
1320                         unsigned long div = rate / req_baud;
1321
1322                         /* The UDIVSLOT register on the newer UARTs allows us to
1323                          * get a divisor adjustment of 1/16th on the baud clock.
1324                          *
1325                          * We don't keep the UDIVSLOT value (the 16ths we
1326                          * calculated by not multiplying the baud by 16) as it
1327                          * is easy enough to recalculate.
1328                          */
1329
1330                         quot = div / 16;
1331                         baud = rate / div;
1332                 } else {
1333                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1334                         baud = rate / (quot * 16);
1335                 }
1336                 quot--;
1337
1338                 calc_deviation = req_baud - baud;
1339                 if (calc_deviation < 0)
1340                         calc_deviation = -calc_deviation;
1341
1342                 if (calc_deviation < deviation) {
1343                         *best_clk = clk;
1344                         best_quot = quot;
1345                         *clk_num = cnt;
1346                         deviation = calc_deviation;
1347                 }
1348         }
1349
1350         return best_quot;
1351 }
1352
1353 /* udivslot_table[]
1354  *
1355  * This table takes the fractional value of the baud divisor and gives
1356  * the recommended setting for the UDIVSLOT register.
1357  */
1358 static u16 udivslot_table[16] = {
1359         [0] = 0x0000,
1360         [1] = 0x0080,
1361         [2] = 0x0808,
1362         [3] = 0x0888,
1363         [4] = 0x2222,
1364         [5] = 0x4924,
1365         [6] = 0x4A52,
1366         [7] = 0x54AA,
1367         [8] = 0x5555,
1368         [9] = 0xD555,
1369         [10] = 0xD5D5,
1370         [11] = 0xDDD5,
1371         [12] = 0xDDDD,
1372         [13] = 0xDFDD,
1373         [14] = 0xDFDF,
1374         [15] = 0xFFDF,
1375 };
1376
1377 static void s3c24xx_serial_set_termios(struct uart_port *port,
1378                                        struct ktermios *termios,
1379                                        struct ktermios *old)
1380 {
1381         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1382         struct s3c24xx_uart_port *ourport = to_ourport(port);
1383         struct clk *clk = ERR_PTR(-EINVAL);
1384         unsigned long flags;
1385         unsigned int baud, quot, clk_sel = 0;
1386         unsigned int ulcon;
1387         unsigned int umcon;
1388         unsigned int udivslot = 0;
1389
1390         /*
1391          * We don't support modem control lines.
1392          */
1393         termios->c_cflag &= ~(HUPCL | CMSPAR);
1394         termios->c_cflag |= CLOCAL;
1395
1396         /*
1397          * Ask the core to calculate the divisor for us.
1398          */
1399
1400         baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1401         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1402         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1403                 quot = port->custom_divisor;
1404         if (IS_ERR(clk))
1405                 return;
1406
1407         /* check to see if we need  to change clock source */
1408
1409         if (ourport->baudclk != clk) {
1410                 clk_prepare_enable(clk);
1411
1412                 s3c24xx_serial_setsource(port, clk_sel);
1413
1414                 if (!IS_ERR(ourport->baudclk)) {
1415                         clk_disable_unprepare(ourport->baudclk);
1416                         ourport->baudclk = ERR_PTR(-EINVAL);
1417                 }
1418
1419                 ourport->baudclk = clk;
1420                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1421         }
1422
1423         if (ourport->info->has_divslot) {
1424                 unsigned int div = ourport->baudclk_rate / baud;
1425
1426                 if (cfg->has_fracval) {
1427                         udivslot = (div & 15);
1428                         dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1429                 } else {
1430                         udivslot = udivslot_table[div & 15];
1431                         dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1432                                 udivslot, div & 15);
1433                 }
1434         }
1435
1436         switch (termios->c_cflag & CSIZE) {
1437         case CS5:
1438                 dev_dbg(port->dev, "config: 5bits/char\n");
1439                 ulcon = S3C2410_LCON_CS5;
1440                 break;
1441         case CS6:
1442                 dev_dbg(port->dev, "config: 6bits/char\n");
1443                 ulcon = S3C2410_LCON_CS6;
1444                 break;
1445         case CS7:
1446                 dev_dbg(port->dev, "config: 7bits/char\n");
1447                 ulcon = S3C2410_LCON_CS7;
1448                 break;
1449         case CS8:
1450         default:
1451                 dev_dbg(port->dev, "config: 8bits/char\n");
1452                 ulcon = S3C2410_LCON_CS8;
1453                 break;
1454         }
1455
1456         /* preserve original lcon IR settings */
1457         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1458
1459         if (termios->c_cflag & CSTOPB)
1460                 ulcon |= S3C2410_LCON_STOPB;
1461
1462         if (termios->c_cflag & PARENB) {
1463                 if (termios->c_cflag & PARODD)
1464                         ulcon |= S3C2410_LCON_PODD;
1465                 else
1466                         ulcon |= S3C2410_LCON_PEVEN;
1467         } else {
1468                 ulcon |= S3C2410_LCON_PNONE;
1469         }
1470
1471         spin_lock_irqsave(&port->lock, flags);
1472
1473         dev_dbg(port->dev,
1474                 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1475                 ulcon, quot, udivslot);
1476
1477         wr_regl(port, S3C2410_ULCON, ulcon);
1478         wr_regl(port, S3C2410_UBRDIV, quot);
1479
1480         port->status &= ~UPSTAT_AUTOCTS;
1481
1482         umcon = rd_regl(port, S3C2410_UMCON);
1483         if (termios->c_cflag & CRTSCTS) {
1484                 umcon |= S3C2410_UMCOM_AFC;
1485                 /* Disable RTS when RX FIFO contains 63 bytes */
1486                 umcon &= ~S3C2412_UMCON_AFC_8;
1487                 port->status = UPSTAT_AUTOCTS;
1488         } else {
1489                 umcon &= ~S3C2410_UMCOM_AFC;
1490         }
1491         wr_regl(port, S3C2410_UMCON, umcon);
1492
1493         if (ourport->info->has_divslot)
1494                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1495
1496         dev_dbg(port->dev,
1497                 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1498                 rd_regl(port, S3C2410_ULCON),
1499                 rd_regl(port, S3C2410_UCON),
1500                 rd_regl(port, S3C2410_UFCON));
1501
1502         /*
1503          * Update the per-port timeout.
1504          */
1505         uart_update_timeout(port, termios->c_cflag, baud);
1506
1507         /*
1508          * Which character status flags are we interested in?
1509          */
1510         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1511         if (termios->c_iflag & INPCK)
1512                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1513                         S3C2410_UERSTAT_PARITY;
1514         /*
1515          * Which character status flags should we ignore?
1516          */
1517         port->ignore_status_mask = 0;
1518         if (termios->c_iflag & IGNPAR)
1519                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1520         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1521                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1522
1523         /*
1524          * Ignore all characters if CREAD is not set.
1525          */
1526         if ((termios->c_cflag & CREAD) == 0)
1527                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1528
1529         spin_unlock_irqrestore(&port->lock, flags);
1530 }
1531
1532 static const char *s3c24xx_serial_type(struct uart_port *port)
1533 {
1534         switch (port->type) {
1535         case PORT_S3C2410:
1536                 return "S3C2410";
1537         case PORT_S3C2440:
1538                 return "S3C2440";
1539         case PORT_S3C2412:
1540                 return "S3C2412";
1541         case PORT_S3C6400:
1542                 return "S3C6400/10";
1543         default:
1544                 return NULL;
1545         }
1546 }
1547
1548 #define MAP_SIZE (0x100)
1549
1550 static void s3c24xx_serial_release_port(struct uart_port *port)
1551 {
1552         release_mem_region(port->mapbase, MAP_SIZE);
1553 }
1554
1555 static int s3c24xx_serial_request_port(struct uart_port *port)
1556 {
1557         const char *name = s3c24xx_serial_portname(port);
1558
1559         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1560 }
1561
1562 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1563 {
1564         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1565
1566         if (flags & UART_CONFIG_TYPE &&
1567             s3c24xx_serial_request_port(port) == 0)
1568                 port->type = info->type;
1569 }
1570
1571 /*
1572  * verify the new serial_struct (for TIOCSSERIAL).
1573  */
1574 static int
1575 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1576 {
1577         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1578
1579         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1580                 return -EINVAL;
1581
1582         return 0;
1583 }
1584
1585 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1586
1587 static struct console s3c24xx_serial_console;
1588
1589 static int __init s3c24xx_serial_console_init(void)
1590 {
1591         register_console(&s3c24xx_serial_console);
1592         return 0;
1593 }
1594 console_initcall(s3c24xx_serial_console_init);
1595
1596 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1597 #else
1598 #define S3C24XX_SERIAL_CONSOLE NULL
1599 #endif
1600
1601 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1602 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1603 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1604                          unsigned char c);
1605 #endif
1606
1607 static struct uart_ops s3c24xx_serial_ops = {
1608         .pm             = s3c24xx_serial_pm,
1609         .tx_empty       = s3c24xx_serial_tx_empty,
1610         .get_mctrl      = s3c24xx_serial_get_mctrl,
1611         .set_mctrl      = s3c24xx_serial_set_mctrl,
1612         .stop_tx        = s3c24xx_serial_stop_tx,
1613         .start_tx       = s3c24xx_serial_start_tx,
1614         .stop_rx        = s3c24xx_serial_stop_rx,
1615         .break_ctl      = s3c24xx_serial_break_ctl,
1616         .startup        = s3c24xx_serial_startup,
1617         .shutdown       = s3c24xx_serial_shutdown,
1618         .set_termios    = s3c24xx_serial_set_termios,
1619         .type           = s3c24xx_serial_type,
1620         .release_port   = s3c24xx_serial_release_port,
1621         .request_port   = s3c24xx_serial_request_port,
1622         .config_port    = s3c24xx_serial_config_port,
1623         .verify_port    = s3c24xx_serial_verify_port,
1624 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1625         .poll_get_char = s3c24xx_serial_get_poll_char,
1626         .poll_put_char = s3c24xx_serial_put_poll_char,
1627 #endif
1628 };
1629
1630 static struct uart_driver s3c24xx_uart_drv = {
1631         .owner          = THIS_MODULE,
1632         .driver_name    = "s3c2410_serial",
1633         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1634         .cons           = S3C24XX_SERIAL_CONSOLE,
1635         .dev_name       = S3C24XX_SERIAL_NAME,
1636         .major          = S3C24XX_SERIAL_MAJOR,
1637         .minor          = S3C24XX_SERIAL_MINOR,
1638 };
1639
1640 #define __PORT_LOCK_UNLOCKED(i) \
1641         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1642 static struct s3c24xx_uart_port
1643 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1644         [0] = {
1645                 .port = {
1646                         .lock           = __PORT_LOCK_UNLOCKED(0),
1647                         .iotype         = UPIO_MEM,
1648                         .uartclk        = 0,
1649                         .fifosize       = 16,
1650                         .ops            = &s3c24xx_serial_ops,
1651                         .flags          = UPF_BOOT_AUTOCONF,
1652                         .line           = 0,
1653                 }
1654         },
1655         [1] = {
1656                 .port = {
1657                         .lock           = __PORT_LOCK_UNLOCKED(1),
1658                         .iotype         = UPIO_MEM,
1659                         .uartclk        = 0,
1660                         .fifosize       = 16,
1661                         .ops            = &s3c24xx_serial_ops,
1662                         .flags          = UPF_BOOT_AUTOCONF,
1663                         .line           = 1,
1664                 }
1665         },
1666 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1667         [2] = {
1668                 .port = {
1669                         .lock           = __PORT_LOCK_UNLOCKED(2),
1670                         .iotype         = UPIO_MEM,
1671                         .uartclk        = 0,
1672                         .fifosize       = 16,
1673                         .ops            = &s3c24xx_serial_ops,
1674                         .flags          = UPF_BOOT_AUTOCONF,
1675                         .line           = 2,
1676                 }
1677         },
1678 #endif
1679 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1680         [3] = {
1681                 .port = {
1682                         .lock           = __PORT_LOCK_UNLOCKED(3),
1683                         .iotype         = UPIO_MEM,
1684                         .uartclk        = 0,
1685                         .fifosize       = 16,
1686                         .ops            = &s3c24xx_serial_ops,
1687                         .flags          = UPF_BOOT_AUTOCONF,
1688                         .line           = 3,
1689                 }
1690         }
1691 #endif
1692 };
1693 #undef __PORT_LOCK_UNLOCKED
1694
1695 /* s3c24xx_serial_resetport
1696  *
1697  * reset the fifos and other the settings.
1698  */
1699
1700 static void s3c24xx_serial_resetport(struct uart_port *port,
1701                                    struct s3c2410_uartcfg *cfg)
1702 {
1703         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1704         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1705         unsigned int ucon_mask;
1706
1707         ucon_mask = info->clksel_mask;
1708         if (info->type == PORT_S3C2440)
1709                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1710
1711         ucon &= ucon_mask;
1712         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1713
1714         /* reset both fifos */
1715         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1716         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1717
1718         /* some delay is required after fifo reset */
1719         udelay(1);
1720 }
1721
1722 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1723
1724 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1725                                              unsigned long val, void *data)
1726 {
1727         struct s3c24xx_uart_port *port;
1728         struct uart_port *uport;
1729
1730         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1731         uport = &port->port;
1732
1733         /* check to see if port is enabled */
1734
1735         if (port->pm_level != 0)
1736                 return 0;
1737
1738         /* try and work out if the baudrate is changing, we can detect
1739          * a change in rate, but we do not have support for detecting
1740          * a disturbance in the clock-rate over the change.
1741          */
1742
1743         if (IS_ERR(port->baudclk))
1744                 goto exit;
1745
1746         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1747                 goto exit;
1748
1749         if (val == CPUFREQ_PRECHANGE) {
1750                 /* we should really shut the port down whilst the
1751                  * frequency change is in progress.
1752                  */
1753
1754         } else if (val == CPUFREQ_POSTCHANGE) {
1755                 struct ktermios *termios;
1756                 struct tty_struct *tty;
1757
1758                 if (uport->state == NULL)
1759                         goto exit;
1760
1761                 tty = uport->state->port.tty;
1762
1763                 if (tty == NULL)
1764                         goto exit;
1765
1766                 termios = &tty->termios;
1767
1768                 if (termios == NULL) {
1769                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1770                         goto exit;
1771                 }
1772
1773                 s3c24xx_serial_set_termios(uport, termios, NULL);
1774         }
1775
1776 exit:
1777         return 0;
1778 }
1779
1780 static inline int
1781 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1782 {
1783         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1784
1785         return cpufreq_register_notifier(&port->freq_transition,
1786                                          CPUFREQ_TRANSITION_NOTIFIER);
1787 }
1788
1789 static inline void
1790 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1791 {
1792         cpufreq_unregister_notifier(&port->freq_transition,
1793                                     CPUFREQ_TRANSITION_NOTIFIER);
1794 }
1795
1796 #else
1797 static inline int
1798 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1799 {
1800         return 0;
1801 }
1802
1803 static inline void
1804 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1805 {
1806 }
1807 #endif
1808
1809 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1810 {
1811         struct device *dev = ourport->port.dev;
1812         struct s3c24xx_uart_info *info = ourport->info;
1813         char clk_name[MAX_CLK_NAME_LENGTH];
1814         unsigned int clk_sel;
1815         struct clk *clk;
1816         int clk_num;
1817         int ret;
1818
1819         clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1820         for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1821                 if (!(clk_sel & (1 << clk_num)))
1822                         continue;
1823
1824                 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1825                 clk = clk_get(dev, clk_name);
1826                 if (IS_ERR(clk))
1827                         continue;
1828
1829                 ret = clk_prepare_enable(clk);
1830                 if (ret) {
1831                         clk_put(clk);
1832                         continue;
1833                 }
1834
1835                 ourport->baudclk = clk;
1836                 ourport->baudclk_rate = clk_get_rate(clk);
1837                 s3c24xx_serial_setsource(&ourport->port, clk_num);
1838
1839                 return 0;
1840         }
1841
1842         return -EINVAL;
1843 }
1844
1845 /* s3c24xx_serial_init_port
1846  *
1847  * initialise a single serial port from the platform device given
1848  */
1849
1850 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1851                                     struct platform_device *platdev)
1852 {
1853         struct uart_port *port = &ourport->port;
1854         struct s3c2410_uartcfg *cfg = ourport->cfg;
1855         struct resource *res;
1856         int ret;
1857
1858         if (platdev == NULL)
1859                 return -ENODEV;
1860
1861         if (port->mapbase != 0)
1862                 return -EINVAL;
1863
1864         /* setup info for port */
1865         port->dev       = &platdev->dev;
1866
1867         /* Startup sequence is different for s3c64xx and higher SoC's */
1868         if (s3c24xx_serial_has_interrupt_mask(port))
1869                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1870
1871         port->uartclk = 1;
1872
1873         if (cfg->uart_flags & UPF_CONS_FLOW) {
1874                 dev_dbg(port->dev, "enabling flow control\n");
1875                 port->flags |= UPF_CONS_FLOW;
1876         }
1877
1878         /* sort our the physical and virtual addresses for each UART */
1879
1880         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1881         if (res == NULL) {
1882                 dev_err(port->dev, "failed to find memory resource for uart\n");
1883                 return -EINVAL;
1884         }
1885
1886         dev_dbg(port->dev, "resource %pR)\n", res);
1887
1888         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1889         if (!port->membase) {
1890                 dev_err(port->dev, "failed to remap controller address\n");
1891                 return -EBUSY;
1892         }
1893
1894         port->mapbase = res->start;
1895         ret = platform_get_irq(platdev, 0);
1896         if (ret < 0) {
1897                 port->irq = 0;
1898         } else {
1899                 port->irq = ret;
1900                 ourport->rx_irq = ret;
1901                 ourport->tx_irq = ret + 1;
1902         }
1903
1904         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1905                 ret = platform_get_irq(platdev, 1);
1906                 if (ret > 0)
1907                         ourport->tx_irq = ret;
1908         }
1909         /*
1910          * DMA is currently supported only on DT platforms, if DMA properties
1911          * are specified.
1912          */
1913         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1914                                                      "dmas", NULL)) {
1915                 ourport->dma = devm_kzalloc(port->dev,
1916                                             sizeof(*ourport->dma),
1917                                             GFP_KERNEL);
1918                 if (!ourport->dma) {
1919                         ret = -ENOMEM;
1920                         goto err;
1921                 }
1922         }
1923
1924         ourport->clk    = clk_get(&platdev->dev, "uart");
1925         if (IS_ERR(ourport->clk)) {
1926                 pr_err("%s: Controller clock not found\n",
1927                                 dev_name(&platdev->dev));
1928                 ret = PTR_ERR(ourport->clk);
1929                 goto err;
1930         }
1931
1932         ret = clk_prepare_enable(ourport->clk);
1933         if (ret) {
1934                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1935                 clk_put(ourport->clk);
1936                 goto err;
1937         }
1938
1939         ret = s3c24xx_serial_enable_baudclk(ourport);
1940         if (ret)
1941                 pr_warn("uart: failed to enable baudclk\n");
1942
1943         /* Keep all interrupts masked and cleared */
1944         if (s3c24xx_serial_has_interrupt_mask(port)) {
1945                 wr_regl(port, S3C64XX_UINTM, 0xf);
1946                 wr_regl(port, S3C64XX_UINTP, 0xf);
1947                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1948         }
1949
1950         dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1951                 &port->mapbase, port->membase, port->irq,
1952                 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1953
1954         /* reset the fifos (and setup the uart) */
1955         s3c24xx_serial_resetport(port, cfg);
1956
1957         return 0;
1958
1959 err:
1960         port->mapbase = 0;
1961         return ret;
1962 }
1963
1964 /* Device driver serial port probe */
1965
1966 #ifdef CONFIG_OF
1967 static const struct of_device_id s3c24xx_uart_dt_match[];
1968 #endif
1969
1970 static int probe_index;
1971
1972 static inline struct s3c24xx_serial_drv_data *
1973 s3c24xx_get_driver_data(struct platform_device *pdev)
1974 {
1975 #ifdef CONFIG_OF
1976         if (pdev->dev.of_node) {
1977                 const struct of_device_id *match;
1978
1979                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1980                 return (struct s3c24xx_serial_drv_data *)match->data;
1981         }
1982 #endif
1983         return (struct s3c24xx_serial_drv_data *)
1984                         platform_get_device_id(pdev)->driver_data;
1985 }
1986
1987 static int s3c24xx_serial_probe(struct platform_device *pdev)
1988 {
1989         struct device_node *np = pdev->dev.of_node;
1990         struct s3c24xx_uart_port *ourport;
1991         int index = probe_index;
1992         int ret, prop = 0;
1993
1994         if (np) {
1995                 ret = of_alias_get_id(np, "serial");
1996                 if (ret >= 0)
1997                         index = ret;
1998         }
1999
2000         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
2001                 dev_err(&pdev->dev, "serial%d out of range\n", index);
2002                 return -EINVAL;
2003         }
2004         ourport = &s3c24xx_serial_ports[index];
2005
2006         ourport->drv_data = s3c24xx_get_driver_data(pdev);
2007         if (!ourport->drv_data) {
2008                 dev_err(&pdev->dev, "could not find driver data\n");
2009                 return -ENODEV;
2010         }
2011
2012         ourport->baudclk = ERR_PTR(-EINVAL);
2013         ourport->info = ourport->drv_data->info;
2014         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2015                         dev_get_platdata(&pdev->dev) :
2016                         ourport->drv_data->def_cfg;
2017
2018         if (np) {
2019                 of_property_read_u32(np,
2020                         "samsung,uart-fifosize", &ourport->port.fifosize);
2021
2022                 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
2023                         switch (prop) {
2024                         case 1:
2025                                 ourport->port.iotype = UPIO_MEM;
2026                                 break;
2027                         case 4:
2028                                 ourport->port.iotype = UPIO_MEM32;
2029                                 break;
2030                         default:
2031                                 dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
2032                                                 prop);
2033                                 ret = -EINVAL;
2034                                 break;
2035                         }
2036                 }
2037         }
2038
2039         if (ourport->drv_data->fifosize[index])
2040                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2041         else if (ourport->info->fifosize)
2042                 ourport->port.fifosize = ourport->info->fifosize;
2043         ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2044
2045         /*
2046          * DMA transfers must be aligned at least to cache line size,
2047          * so find minimal transfer size suitable for DMA mode
2048          */
2049         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2050                                     dma_get_cache_alignment());
2051
2052         dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2053
2054         ret = s3c24xx_serial_init_port(ourport, pdev);
2055         if (ret < 0)
2056                 return ret;
2057
2058         if (!s3c24xx_uart_drv.state) {
2059                 ret = uart_register_driver(&s3c24xx_uart_drv);
2060                 if (ret < 0) {
2061                         pr_err("Failed to register Samsung UART driver\n");
2062                         return ret;
2063                 }
2064         }
2065
2066         dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2067         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2068         platform_set_drvdata(pdev, &ourport->port);
2069
2070         /*
2071          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2072          * so that a potential re-enablement through the pm-callback overlaps
2073          * and keeps the clock enabled in this case.
2074          */
2075         clk_disable_unprepare(ourport->clk);
2076         if (!IS_ERR(ourport->baudclk))
2077                 clk_disable_unprepare(ourport->baudclk);
2078
2079         ret = s3c24xx_serial_cpufreq_register(ourport);
2080         if (ret < 0)
2081                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2082
2083         probe_index++;
2084
2085         return 0;
2086 }
2087
2088 static int s3c24xx_serial_remove(struct platform_device *dev)
2089 {
2090         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2091
2092         if (port) {
2093                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2094                 uart_remove_one_port(&s3c24xx_uart_drv, port);
2095         }
2096
2097         uart_unregister_driver(&s3c24xx_uart_drv);
2098
2099         return 0;
2100 }
2101
2102 /* UART power management code */
2103 #ifdef CONFIG_PM_SLEEP
2104 static int s3c24xx_serial_suspend(struct device *dev)
2105 {
2106         struct uart_port *port = s3c24xx_dev_to_port(dev);
2107
2108         if (port)
2109                 uart_suspend_port(&s3c24xx_uart_drv, port);
2110
2111         return 0;
2112 }
2113
2114 static int s3c24xx_serial_resume(struct device *dev)
2115 {
2116         struct uart_port *port = s3c24xx_dev_to_port(dev);
2117         struct s3c24xx_uart_port *ourport = to_ourport(port);
2118
2119         if (port) {
2120                 clk_prepare_enable(ourport->clk);
2121                 if (!IS_ERR(ourport->baudclk))
2122                         clk_prepare_enable(ourport->baudclk);
2123                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2124                 if (!IS_ERR(ourport->baudclk))
2125                         clk_disable_unprepare(ourport->baudclk);
2126                 clk_disable_unprepare(ourport->clk);
2127
2128                 uart_resume_port(&s3c24xx_uart_drv, port);
2129         }
2130
2131         return 0;
2132 }
2133
2134 static int s3c24xx_serial_resume_noirq(struct device *dev)
2135 {
2136         struct uart_port *port = s3c24xx_dev_to_port(dev);
2137         struct s3c24xx_uart_port *ourport = to_ourport(port);
2138
2139         if (port) {
2140                 /* restore IRQ mask */
2141                 if (s3c24xx_serial_has_interrupt_mask(port)) {
2142                         unsigned int uintm = 0xf;
2143
2144                         if (ourport->tx_enabled)
2145                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2146                         if (ourport->rx_enabled)
2147                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2148                         clk_prepare_enable(ourport->clk);
2149                         if (!IS_ERR(ourport->baudclk))
2150                                 clk_prepare_enable(ourport->baudclk);
2151                         wr_regl(port, S3C64XX_UINTM, uintm);
2152                         if (!IS_ERR(ourport->baudclk))
2153                                 clk_disable_unprepare(ourport->baudclk);
2154                         clk_disable_unprepare(ourport->clk);
2155                 }
2156         }
2157
2158         return 0;
2159 }
2160
2161 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2162         .suspend = s3c24xx_serial_suspend,
2163         .resume = s3c24xx_serial_resume,
2164         .resume_noirq = s3c24xx_serial_resume_noirq,
2165 };
2166 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
2167
2168 #else /* !CONFIG_PM_SLEEP */
2169
2170 #define SERIAL_SAMSUNG_PM_OPS   NULL
2171 #endif /* CONFIG_PM_SLEEP */
2172
2173 /* Console code */
2174
2175 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2176
2177 static struct uart_port *cons_uart;
2178
2179 static int
2180 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2181 {
2182         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2183         unsigned long ufstat, utrstat;
2184
2185         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2186                 /* fifo mode - check amount of data in fifo registers... */
2187
2188                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2189                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2190         }
2191
2192         /* in non-fifo mode, we go and use the tx buffer empty */
2193
2194         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2195         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2196 }
2197
2198 static bool
2199 s3c24xx_port_configured(unsigned int ucon)
2200 {
2201         /* consider the serial port configured if the tx/rx mode set */
2202         return (ucon & 0xf) != 0;
2203 }
2204
2205 #ifdef CONFIG_CONSOLE_POLL
2206 /*
2207  * Console polling routines for writing and reading from the uart while
2208  * in an interrupt or debug context.
2209  */
2210
2211 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2212 {
2213         struct s3c24xx_uart_port *ourport = to_ourport(port);
2214         unsigned int ufstat;
2215
2216         ufstat = rd_regl(port, S3C2410_UFSTAT);
2217         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2218                 return NO_POLL_CHAR;
2219
2220         return rd_reg(port, S3C2410_URXH);
2221 }
2222
2223 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2224                 unsigned char c)
2225 {
2226         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2227         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2228
2229         /* not possible to xmit on unconfigured port */
2230         if (!s3c24xx_port_configured(ucon))
2231                 return;
2232
2233         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2234                 cpu_relax();
2235         wr_reg(port, S3C2410_UTXH, c);
2236 }
2237
2238 #endif /* CONFIG_CONSOLE_POLL */
2239
2240 static void
2241 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2242 {
2243         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2244
2245         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2246                 cpu_relax();
2247         wr_reg(port, S3C2410_UTXH, ch);
2248 }
2249
2250 static void
2251 s3c24xx_serial_console_write(struct console *co, const char *s,
2252                              unsigned int count)
2253 {
2254         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2255
2256         /* not possible to xmit on unconfigured port */
2257         if (!s3c24xx_port_configured(ucon))
2258                 return;
2259
2260         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2261 }
2262
2263 static void __init
2264 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2265                            int *parity, int *bits)
2266 {
2267         struct clk *clk;
2268         unsigned int ulcon;
2269         unsigned int ucon;
2270         unsigned int ubrdiv;
2271         unsigned long rate;
2272         unsigned int clk_sel;
2273         char clk_name[MAX_CLK_NAME_LENGTH];
2274
2275         ulcon  = rd_regl(port, S3C2410_ULCON);
2276         ucon   = rd_regl(port, S3C2410_UCON);
2277         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2278
2279         if (s3c24xx_port_configured(ucon)) {
2280                 switch (ulcon & S3C2410_LCON_CSMASK) {
2281                 case S3C2410_LCON_CS5:
2282                         *bits = 5;
2283                         break;
2284                 case S3C2410_LCON_CS6:
2285                         *bits = 6;
2286                         break;
2287                 case S3C2410_LCON_CS7:
2288                         *bits = 7;
2289                         break;
2290                 case S3C2410_LCON_CS8:
2291                 default:
2292                         *bits = 8;
2293                         break;
2294                 }
2295
2296                 switch (ulcon & S3C2410_LCON_PMASK) {
2297                 case S3C2410_LCON_PEVEN:
2298                         *parity = 'e';
2299                         break;
2300
2301                 case S3C2410_LCON_PODD:
2302                         *parity = 'o';
2303                         break;
2304
2305                 case S3C2410_LCON_PNONE:
2306                 default:
2307                         *parity = 'n';
2308                 }
2309
2310                 /* now calculate the baud rate */
2311
2312                 clk_sel = s3c24xx_serial_getsource(port);
2313                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2314
2315                 clk = clk_get(port->dev, clk_name);
2316                 if (!IS_ERR(clk))
2317                         rate = clk_get_rate(clk);
2318                 else
2319                         rate = 1;
2320
2321                 *baud = rate / (16 * (ubrdiv + 1));
2322                 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2323         }
2324 }
2325
2326 static int __init
2327 s3c24xx_serial_console_setup(struct console *co, char *options)
2328 {
2329         struct uart_port *port;
2330         int baud = 9600;
2331         int bits = 8;
2332         int parity = 'n';
2333         int flow = 'n';
2334
2335         /* is this a valid port */
2336
2337         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2338                 co->index = 0;
2339
2340         port = &s3c24xx_serial_ports[co->index].port;
2341
2342         /* is the port configured? */
2343
2344         if (port->mapbase == 0x0)
2345                 return -ENODEV;
2346
2347         cons_uart = port;
2348
2349         /*
2350          * Check whether an invalid uart number has been specified, and
2351          * if so, search for the first available port that does have
2352          * console support.
2353          */
2354         if (options)
2355                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2356         else
2357                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2358
2359         dev_dbg(port->dev, "baud %d\n", baud);
2360
2361         return uart_set_options(port, co, baud, parity, bits, flow);
2362 }
2363
2364 static struct console s3c24xx_serial_console = {
2365         .name           = S3C24XX_SERIAL_NAME,
2366         .device         = uart_console_device,
2367         .flags          = CON_PRINTBUFFER,
2368         .index          = -1,
2369         .write          = s3c24xx_serial_console_write,
2370         .setup          = s3c24xx_serial_console_setup,
2371         .data           = &s3c24xx_uart_drv,
2372 };
2373 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2374
2375 #ifdef CONFIG_CPU_S3C2410
2376 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2377         .info = &(struct s3c24xx_uart_info) {
2378                 .name           = "Samsung S3C2410 UART",
2379                 .type           = PORT_S3C2410,
2380                 .fifosize       = 16,
2381                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2382                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2383                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2384                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2385                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2386                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2387                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2388                 .num_clks       = 2,
2389                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2390                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2391         },
2392         .def_cfg = &(struct s3c2410_uartcfg) {
2393                 .ucon           = S3C2410_UCON_DEFAULT,
2394                 .ufcon          = S3C2410_UFCON_DEFAULT,
2395         },
2396 };
2397 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2398 #else
2399 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2400 #endif
2401
2402 #ifdef CONFIG_CPU_S3C2412
2403 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2404         .info = &(struct s3c24xx_uart_info) {
2405                 .name           = "Samsung S3C2412 UART",
2406                 .type           = PORT_S3C2412,
2407                 .fifosize       = 64,
2408                 .has_divslot    = 1,
2409                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2410                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2411                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2412                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2413                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2414                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2415                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2416                 .num_clks       = 4,
2417                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2418                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2419         },
2420         .def_cfg = &(struct s3c2410_uartcfg) {
2421                 .ucon           = S3C2410_UCON_DEFAULT,
2422                 .ufcon          = S3C2410_UFCON_DEFAULT,
2423         },
2424 };
2425 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2426 #else
2427 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2428 #endif
2429
2430 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2431         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2432 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2433         .info = &(struct s3c24xx_uart_info) {
2434                 .name           = "Samsung S3C2440 UART",
2435                 .type           = PORT_S3C2440,
2436                 .fifosize       = 64,
2437                 .has_divslot    = 1,
2438                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2439                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2440                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2441                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2442                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2443                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2444                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2445                 .num_clks       = 4,
2446                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2447                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2448         },
2449         .def_cfg = &(struct s3c2410_uartcfg) {
2450                 .ucon           = S3C2410_UCON_DEFAULT,
2451                 .ufcon          = S3C2410_UFCON_DEFAULT,
2452         },
2453 };
2454 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2455 #else
2456 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2457 #endif
2458
2459 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2460 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2461         .info = &(struct s3c24xx_uart_info) {
2462                 .name           = "Samsung S3C6400 UART",
2463                 .type           = PORT_S3C6400,
2464                 .fifosize       = 64,
2465                 .has_divslot    = 1,
2466                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2467                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2468                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2469                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2470                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2471                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2472                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2473                 .num_clks       = 4,
2474                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2475                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2476         },
2477         .def_cfg = &(struct s3c2410_uartcfg) {
2478                 .ucon           = S3C2410_UCON_DEFAULT,
2479                 .ufcon          = S3C2410_UFCON_DEFAULT,
2480         },
2481 };
2482 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2483 #else
2484 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2485 #endif
2486
2487 #ifdef CONFIG_CPU_S5PV210
2488 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2489         .info = &(struct s3c24xx_uart_info) {
2490                 .name           = "Samsung S5PV210 UART",
2491                 .type           = PORT_S3C6400,
2492                 .has_divslot    = 1,
2493                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2494                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2495                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2496                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2497                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2498                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2499                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2500                 .num_clks       = 2,
2501                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2502                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2503         },
2504         .def_cfg = &(struct s3c2410_uartcfg) {
2505                 .ucon           = S5PV210_UCON_DEFAULT,
2506                 .ufcon          = S5PV210_UFCON_DEFAULT,
2507         },
2508         .fifosize = { 256, 64, 16, 16 },
2509 };
2510 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2511 #else
2512 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2513 #endif
2514
2515 #if defined(CONFIG_ARCH_EXYNOS)
2516 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2517         .info = &(struct s3c24xx_uart_info) {                   \
2518                 .name           = "Samsung Exynos UART",        \
2519                 .type           = PORT_S3C6400,                 \
2520                 .has_divslot    = 1,                            \
2521                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2522                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2523                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2524                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2525                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2526                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2527                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2528                 .num_clks       = 1,                            \
2529                 .clksel_mask    = 0,                            \
2530                 .clksel_shift   = 0,                            \
2531         },                                                      \
2532         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2533                 .ucon           = S5PV210_UCON_DEFAULT,         \
2534                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2535                 .has_fracval    = 1,                            \
2536         }                                                       \
2537
2538 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2539         EXYNOS_COMMON_SERIAL_DRV_DATA,
2540         .fifosize = { 256, 64, 16, 16 },
2541 };
2542
2543 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2544         EXYNOS_COMMON_SERIAL_DRV_DATA,
2545         .fifosize = { 64, 256, 16, 256 },
2546 };
2547
2548 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2549 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2550 #else
2551 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2552 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2553 #endif
2554
2555 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2556         {
2557                 .name           = "s3c2410-uart",
2558                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2559         }, {
2560                 .name           = "s3c2412-uart",
2561                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2562         }, {
2563                 .name           = "s3c2440-uart",
2564                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2565         }, {
2566                 .name           = "s3c6400-uart",
2567                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2568         }, {
2569                 .name           = "s5pv210-uart",
2570                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2571         }, {
2572                 .name           = "exynos4210-uart",
2573                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2574         }, {
2575                 .name           = "exynos5433-uart",
2576                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2577         },
2578         { },
2579 };
2580 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2581
2582 #ifdef CONFIG_OF
2583 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2584         { .compatible = "samsung,s3c2410-uart",
2585                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2586         { .compatible = "samsung,s3c2412-uart",
2587                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2588         { .compatible = "samsung,s3c2440-uart",
2589                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2590         { .compatible = "samsung,s3c6400-uart",
2591                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2592         { .compatible = "samsung,s5pv210-uart",
2593                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2594         { .compatible = "samsung,exynos4210-uart",
2595                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2596         { .compatible = "samsung,exynos5433-uart",
2597                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2598         {},
2599 };
2600 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2601 #endif
2602
2603 static struct platform_driver samsung_serial_driver = {
2604         .probe          = s3c24xx_serial_probe,
2605         .remove         = s3c24xx_serial_remove,
2606         .id_table       = s3c24xx_serial_driver_ids,
2607         .driver         = {
2608                 .name   = "samsung-uart",
2609                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2610                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2611         },
2612 };
2613
2614 module_platform_driver(samsung_serial_driver);
2615
2616 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2617 /*
2618  * Early console.
2619  */
2620
2621 static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
2622 {
2623         switch (port->iotype) {
2624         case UPIO_MEM:
2625                 writeb(val, portaddr(port, reg));
2626                 break;
2627         case UPIO_MEM32:
2628                 writel(val, portaddr(port, reg));
2629                 break;
2630         }
2631 }
2632
2633 struct samsung_early_console_data {
2634         u32 txfull_mask;
2635 };
2636
2637 static void samsung_early_busyuart(struct uart_port *port)
2638 {
2639         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2640                 ;
2641 }
2642
2643 static void samsung_early_busyuart_fifo(struct uart_port *port)
2644 {
2645         struct samsung_early_console_data *data = port->private_data;
2646
2647         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2648                 ;
2649 }
2650
2651 static void samsung_early_putc(struct uart_port *port, int c)
2652 {
2653         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2654                 samsung_early_busyuart_fifo(port);
2655         else
2656                 samsung_early_busyuart(port);
2657
2658         wr_reg_barrier(port, S3C2410_UTXH, c);
2659 }
2660
2661 static void samsung_early_write(struct console *con, const char *s,
2662                                 unsigned int n)
2663 {
2664         struct earlycon_device *dev = con->data;
2665
2666         uart_console_write(&dev->port, s, n, samsung_early_putc);
2667 }
2668
2669 static int __init samsung_early_console_setup(struct earlycon_device *device,
2670                                               const char *opt)
2671 {
2672         if (!device->port.membase)
2673                 return -ENODEV;
2674
2675         device->con->write = samsung_early_write;
2676         return 0;
2677 }
2678
2679 /* S3C2410 */
2680 static struct samsung_early_console_data s3c2410_early_console_data = {
2681         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2682 };
2683
2684 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2685                                               const char *opt)
2686 {
2687         device->port.private_data = &s3c2410_early_console_data;
2688         return samsung_early_console_setup(device, opt);
2689 }
2690
2691 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2692                         s3c2410_early_console_setup);
2693
2694 /* S3C2412, S3C2440, S3C64xx */
2695 static struct samsung_early_console_data s3c2440_early_console_data = {
2696         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2697 };
2698
2699 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2700                                               const char *opt)
2701 {
2702         device->port.private_data = &s3c2440_early_console_data;
2703         return samsung_early_console_setup(device, opt);
2704 }
2705
2706 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2707                         s3c2440_early_console_setup);
2708 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2709                         s3c2440_early_console_setup);
2710 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2711                         s3c2440_early_console_setup);
2712
2713 /* S5PV210, Exynos */
2714 static struct samsung_early_console_data s5pv210_early_console_data = {
2715         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2716 };
2717
2718 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2719                                               const char *opt)
2720 {
2721         device->port.private_data = &s5pv210_early_console_data;
2722         return samsung_early_console_setup(device, opt);
2723 }
2724
2725 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2726                         s5pv210_early_console_setup);
2727 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2728                         s5pv210_early_console_setup);
2729 #endif
2730
2731 MODULE_ALIAS("platform:samsung-uart");
2732 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2733 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2734 MODULE_LICENSE("GPL v2");