2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/ioport.h>
37 #include <linux/platform_device.h>
38 #include <linux/init.h>
39 #include <linux/sysrq.h>
40 #include <linux/console.h>
41 #include <linux/tty.h>
42 #include <linux/tty_flip.h>
43 #include <linux/serial_core.h>
44 #include <linux/serial.h>
45 #include <linux/serial_s3c.h>
46 #include <linux/delay.h>
47 #include <linux/clk.h>
48 #include <linux/cpufreq.h>
55 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
58 extern void printascii(const char *);
61 static void dbg(const char *fmt, ...)
67 vscnprintf(buff, sizeof(buff), fmt, va);
74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
77 /* UART name and device definitions */
79 #define S3C24XX_SERIAL_NAME "ttySAC"
80 #define S3C24XX_SERIAL_MAJOR 204
81 #define S3C24XX_SERIAL_MINOR 64
83 #define S3C24XX_TX_PIO 1
84 #define S3C24XX_TX_DMA 2
85 #define S3C24XX_RX_PIO 1
86 #define S3C24XX_RX_DMA 2
87 /* macros to change one thing to another */
89 #define tx_enabled(port) ((port)->unused[0])
90 #define rx_enabled(port) ((port)->unused[1])
92 /* flag to ignore all characters coming in */
93 #define RXSTAT_DUMMY_READ (0x10000000)
95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
97 return container_of(port, struct s3c24xx_uart_port, port);
100 /* translate a port to the device name */
102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
104 return to_platform_device(port->dev)->name;
107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
109 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
113 * s3c64xx and later SoC's include the interrupt mask and status registers in
114 * the controller itself, unlike the s3c24xx SoC's which have these registers
115 * in the interrupt controller. Check if the port type is s3c64xx or higher.
117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
119 return to_ourport(port)->info->type == PORT_S3C6400;
122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
125 unsigned int ucon, ufcon;
128 spin_lock_irqsave(&port->lock, flags);
130 while (--count && !s3c24xx_serial_txempty_nofifo(port))
133 ufcon = rd_regl(port, S3C2410_UFCON);
134 ufcon |= S3C2410_UFCON_RESETRX;
135 wr_regl(port, S3C2410_UFCON, ufcon);
137 ucon = rd_regl(port, S3C2410_UCON);
138 ucon |= S3C2410_UCON_RXIRQMODE;
139 wr_regl(port, S3C2410_UCON, ucon);
141 rx_enabled(port) = 1;
142 spin_unlock_irqrestore(&port->lock, flags);
145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
150 spin_lock_irqsave(&port->lock, flags);
152 ucon = rd_regl(port, S3C2410_UCON);
153 ucon &= ~S3C2410_UCON_RXIRQMODE;
154 wr_regl(port, S3C2410_UCON, ucon);
156 rx_enabled(port) = 0;
157 spin_unlock_irqrestore(&port->lock, flags);
160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
162 struct s3c24xx_uart_port *ourport = to_ourport(port);
163 struct s3c24xx_uart_dma *dma = ourport->dma;
164 struct circ_buf *xmit = &port->state->xmit;
165 struct dma_tx_state state;
168 if (!tx_enabled(port))
171 if (s3c24xx_serial_has_interrupt_mask(port))
172 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
174 disable_irq_nosync(ourport->tx_irq);
176 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
177 dmaengine_pause(dma->tx_chan);
178 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
179 dmaengine_terminate_all(dma->tx_chan);
180 dma_sync_single_for_cpu(ourport->port.dev,
181 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
182 async_tx_ack(dma->tx_desc);
183 count = dma->tx_bytes_requested - state.residue;
184 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
185 port->icount.tx += count;
188 tx_enabled(port) = 0;
189 ourport->tx_in_progress = 0;
191 if (port->flags & UPF_CONS_FLOW)
192 s3c24xx_serial_rx_enable(port);
194 ourport->tx_mode = 0;
197 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
199 static void s3c24xx_serial_tx_dma_complete(void *args)
201 struct s3c24xx_uart_port *ourport = args;
202 struct uart_port *port = &ourport->port;
203 struct circ_buf *xmit = &port->state->xmit;
204 struct s3c24xx_uart_dma *dma = ourport->dma;
205 struct dma_tx_state state;
210 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
211 count = dma->tx_bytes_requested - state.residue;
212 async_tx_ack(dma->tx_desc);
214 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
215 dma->tx_size, DMA_TO_DEVICE);
217 spin_lock_irqsave(&port->lock, flags);
219 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
220 port->icount.tx += count;
221 ourport->tx_in_progress = 0;
223 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
224 uart_write_wakeup(port);
226 s3c24xx_serial_start_next_tx(ourport);
227 spin_unlock_irqrestore(&port->lock, flags);
230 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
232 struct uart_port *port = &ourport->port;
235 /* Mask Tx interrupt */
236 if (s3c24xx_serial_has_interrupt_mask(port))
237 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
239 disable_irq_nosync(ourport->tx_irq);
241 /* Enable tx dma mode */
242 ucon = rd_regl(port, S3C2410_UCON);
243 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
244 ucon |= S3C64XX_UCON_TXBURST_1;
245 ucon |= S3C64XX_UCON_TXMODE_DMA;
246 wr_regl(port, S3C2410_UCON, ucon);
248 ourport->tx_mode = S3C24XX_TX_DMA;
251 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
253 struct uart_port *port = &ourport->port;
256 /* Set ufcon txtrig */
257 ourport->tx_in_progress = S3C24XX_TX_PIO;
258 ufcon = rd_regl(port, S3C2410_UFCON);
259 wr_regl(port, S3C2410_UFCON, ufcon);
261 /* Enable tx pio mode */
262 ucon = rd_regl(port, S3C2410_UCON);
263 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
264 ucon |= S3C64XX_UCON_TXMODE_CPU;
265 wr_regl(port, S3C2410_UCON, ucon);
267 /* Unmask Tx interrupt */
268 if (s3c24xx_serial_has_interrupt_mask(port))
269 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
272 enable_irq(ourport->tx_irq);
274 ourport->tx_mode = S3C24XX_TX_PIO;
277 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
279 if (ourport->tx_mode != S3C24XX_TX_PIO)
280 enable_tx_pio(ourport);
283 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
286 struct uart_port *port = &ourport->port;
287 struct circ_buf *xmit = &port->state->xmit;
288 struct s3c24xx_uart_dma *dma = ourport->dma;
291 if (ourport->tx_mode != S3C24XX_TX_DMA)
292 enable_tx_dma(ourport);
294 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
295 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
297 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
298 dma->tx_size, DMA_TO_DEVICE);
300 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
301 dma->tx_transfer_addr, dma->tx_size,
302 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
304 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
308 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
309 dma->tx_desc->callback_param = ourport;
310 dma->tx_bytes_requested = dma->tx_size;
312 ourport->tx_in_progress = S3C24XX_TX_DMA;
313 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
314 dma_async_issue_pending(dma->tx_chan);
318 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
320 struct uart_port *port = &ourport->port;
321 struct circ_buf *xmit = &port->state->xmit;
324 /* Get data size up to the end of buffer */
325 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
328 s3c24xx_serial_stop_tx(port);
332 if (!ourport->dma || !ourport->dma->tx_chan ||
333 count < ourport->min_dma_size ||
334 xmit->tail & (dma_get_cache_alignment() - 1))
335 s3c24xx_serial_start_tx_pio(ourport);
337 s3c24xx_serial_start_tx_dma(ourport, count);
340 static void s3c24xx_serial_start_tx(struct uart_port *port)
342 struct s3c24xx_uart_port *ourport = to_ourport(port);
343 struct circ_buf *xmit = &port->state->xmit;
345 if (!tx_enabled(port)) {
346 if (port->flags & UPF_CONS_FLOW)
347 s3c24xx_serial_rx_disable(port);
349 tx_enabled(port) = 1;
350 if (!ourport->dma || !ourport->dma->tx_chan)
351 s3c24xx_serial_start_tx_pio(ourport);
354 if (ourport->dma && ourport->dma->tx_chan) {
355 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
356 s3c24xx_serial_start_next_tx(ourport);
360 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
361 struct tty_port *tty, int count)
363 struct s3c24xx_uart_dma *dma = ourport->dma;
369 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
370 dma->rx_size, DMA_FROM_DEVICE);
372 ourport->port.icount.rx += count;
374 dev_err(ourport->port.dev, "No tty port\n");
377 copied = tty_insert_flip_string(tty,
378 ((unsigned char *)(ourport->dma->rx_buf)), count);
379 if (copied != count) {
381 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
385 static void s3c24xx_serial_stop_rx(struct uart_port *port)
387 struct s3c24xx_uart_port *ourport = to_ourport(port);
388 struct s3c24xx_uart_dma *dma = ourport->dma;
389 struct tty_port *t = &port->state->port;
390 struct dma_tx_state state;
391 enum dma_status dma_status;
392 unsigned int received;
394 if (rx_enabled(port)) {
395 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
396 if (s3c24xx_serial_has_interrupt_mask(port))
397 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
400 disable_irq_nosync(ourport->rx_irq);
401 rx_enabled(port) = 0;
403 if (dma && dma->rx_chan) {
404 dmaengine_pause(dma->tx_chan);
405 dma_status = dmaengine_tx_status(dma->rx_chan,
406 dma->rx_cookie, &state);
407 if (dma_status == DMA_IN_PROGRESS ||
408 dma_status == DMA_PAUSED) {
409 received = dma->rx_bytes_requested - state.residue;
410 dmaengine_terminate_all(dma->rx_chan);
411 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
416 static inline struct s3c24xx_uart_info
417 *s3c24xx_port_to_info(struct uart_port *port)
419 return to_ourport(port)->info;
422 static inline struct s3c2410_uartcfg
423 *s3c24xx_port_to_cfg(struct uart_port *port)
425 struct s3c24xx_uart_port *ourport;
427 if (port->dev == NULL)
430 ourport = container_of(port, struct s3c24xx_uart_port, port);
434 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
435 unsigned long ufstat)
437 struct s3c24xx_uart_info *info = ourport->info;
439 if (ufstat & info->rx_fifofull)
440 return ourport->port.fifosize;
442 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
445 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
446 static void s3c24xx_serial_rx_dma_complete(void *args)
448 struct s3c24xx_uart_port *ourport = args;
449 struct uart_port *port = &ourport->port;
451 struct s3c24xx_uart_dma *dma = ourport->dma;
452 struct tty_port *t = &port->state->port;
453 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
455 struct dma_tx_state state;
459 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
460 received = dma->rx_bytes_requested - state.residue;
461 async_tx_ack(dma->rx_desc);
463 spin_lock_irqsave(&port->lock, flags);
466 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
469 tty_flip_buffer_push(t);
473 s3c64xx_start_rx_dma(ourport);
475 spin_unlock_irqrestore(&port->lock, flags);
478 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
480 struct s3c24xx_uart_dma *dma = ourport->dma;
482 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
483 dma->rx_size, DMA_FROM_DEVICE);
485 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
486 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
489 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
493 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
494 dma->rx_desc->callback_param = ourport;
495 dma->rx_bytes_requested = dma->rx_size;
497 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
498 dma_async_issue_pending(dma->rx_chan);
501 /* ? - where has parity gone?? */
502 #define S3C2410_UERSTAT_PARITY (0x1000)
504 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
506 struct uart_port *port = &ourport->port;
509 /* set Rx mode to DMA mode */
510 ucon = rd_regl(port, S3C2410_UCON);
511 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
512 S3C64XX_UCON_TIMEOUT_MASK |
513 S3C64XX_UCON_EMPTYINT_EN |
514 S3C64XX_UCON_DMASUS_EN |
515 S3C64XX_UCON_TIMEOUT_EN |
516 S3C64XX_UCON_RXMODE_MASK);
517 ucon |= S3C64XX_UCON_RXBURST_1 |
518 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
519 S3C64XX_UCON_EMPTYINT_EN |
520 S3C64XX_UCON_TIMEOUT_EN |
521 S3C64XX_UCON_RXMODE_DMA;
522 wr_regl(port, S3C2410_UCON, ucon);
524 ourport->rx_mode = S3C24XX_RX_DMA;
527 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
529 struct uart_port *port = &ourport->port;
532 /* set Rx mode to DMA mode */
533 ucon = rd_regl(port, S3C2410_UCON);
534 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
535 S3C64XX_UCON_EMPTYINT_EN |
536 S3C64XX_UCON_DMASUS_EN |
537 S3C64XX_UCON_TIMEOUT_EN |
538 S3C64XX_UCON_RXMODE_MASK);
539 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
540 S3C64XX_UCON_TIMEOUT_EN |
541 S3C64XX_UCON_RXMODE_CPU;
542 wr_regl(port, S3C2410_UCON, ucon);
544 ourport->rx_mode = S3C24XX_RX_PIO;
547 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
549 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
551 unsigned int utrstat, ufstat, received;
552 struct s3c24xx_uart_port *ourport = dev_id;
553 struct uart_port *port = &ourport->port;
554 struct s3c24xx_uart_dma *dma = ourport->dma;
555 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
556 struct tty_port *t = &port->state->port;
558 struct dma_tx_state state;
560 utrstat = rd_regl(port, S3C2410_UTRSTAT);
561 ufstat = rd_regl(port, S3C2410_UFSTAT);
563 spin_lock_irqsave(&port->lock, flags);
565 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
566 s3c64xx_start_rx_dma(ourport);
567 if (ourport->rx_mode == S3C24XX_RX_PIO)
568 enable_rx_dma(ourport);
572 if (ourport->rx_mode == S3C24XX_RX_DMA) {
573 dmaengine_pause(dma->rx_chan);
574 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
575 dmaengine_terminate_all(dma->rx_chan);
576 received = dma->rx_bytes_requested - state.residue;
577 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
579 enable_rx_pio(ourport);
582 s3c24xx_serial_rx_drain_fifo(ourport);
585 tty_flip_buffer_push(t);
589 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
592 spin_unlock_irqrestore(&port->lock, flags);
597 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
599 struct uart_port *port = &ourport->port;
600 unsigned int ufcon, ch, flag, ufstat, uerstat;
601 unsigned int fifocnt = 0;
602 int max_count = port->fifosize;
604 while (max_count-- > 0) {
606 * Receive all characters known to be in FIFO
607 * before reading FIFO level again
610 ufstat = rd_regl(port, S3C2410_UFSTAT);
611 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
617 uerstat = rd_regl(port, S3C2410_UERSTAT);
618 ch = rd_regb(port, S3C2410_URXH);
620 if (port->flags & UPF_CONS_FLOW) {
621 int txe = s3c24xx_serial_txempty_nofifo(port);
623 if (rx_enabled(port)) {
625 rx_enabled(port) = 0;
630 ufcon = rd_regl(port, S3C2410_UFCON);
631 ufcon |= S3C2410_UFCON_RESETRX;
632 wr_regl(port, S3C2410_UFCON, ufcon);
633 rx_enabled(port) = 1;
640 /* insert the character into the buffer */
645 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
646 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
649 /* check for break */
650 if (uerstat & S3C2410_UERSTAT_BREAK) {
653 if (uart_handle_break(port))
654 continue; /* Ignore character */
657 if (uerstat & S3C2410_UERSTAT_FRAME)
658 port->icount.frame++;
659 if (uerstat & S3C2410_UERSTAT_OVERRUN)
660 port->icount.overrun++;
662 uerstat &= port->read_status_mask;
664 if (uerstat & S3C2410_UERSTAT_BREAK)
666 else if (uerstat & S3C2410_UERSTAT_PARITY)
668 else if (uerstat & (S3C2410_UERSTAT_FRAME |
669 S3C2410_UERSTAT_OVERRUN))
673 if (uart_handle_sysrq_char(port, ch))
674 continue; /* Ignore character */
676 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
680 tty_flip_buffer_push(&port->state->port);
683 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
685 struct s3c24xx_uart_port *ourport = dev_id;
686 struct uart_port *port = &ourport->port;
689 spin_lock_irqsave(&port->lock, flags);
690 s3c24xx_serial_rx_drain_fifo(ourport);
691 spin_unlock_irqrestore(&port->lock, flags);
697 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
699 struct s3c24xx_uart_port *ourport = dev_id;
701 if (ourport->dma && ourport->dma->rx_chan)
702 return s3c24xx_serial_rx_chars_dma(dev_id);
703 return s3c24xx_serial_rx_chars_pio(dev_id);
706 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
708 struct s3c24xx_uart_port *ourport = id;
709 struct uart_port *port = &ourport->port;
710 struct circ_buf *xmit = &port->state->xmit;
712 int count, dma_count = 0;
714 spin_lock_irqsave(&port->lock, flags);
716 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
718 if (ourport->dma && ourport->dma->tx_chan &&
719 count >= ourport->min_dma_size) {
720 int align = dma_get_cache_alignment() -
721 (xmit->tail & (dma_get_cache_alignment() - 1));
722 if (count-align >= ourport->min_dma_size) {
723 dma_count = count-align;
729 wr_regb(port, S3C2410_UTXH, port->x_char);
735 /* if there isn't anything more to transmit, or the uart is now
736 * stopped, disable the uart and exit
739 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
740 s3c24xx_serial_stop_tx(port);
744 /* try and drain the buffer... */
746 if (count > port->fifosize) {
747 count = port->fifosize;
751 while (!uart_circ_empty(xmit) && count > 0) {
752 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
755 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
756 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
761 if (!count && dma_count) {
762 s3c24xx_serial_start_tx_dma(ourport, dma_count);
766 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
767 uart_write_wakeup(port);
769 if (uart_circ_empty(xmit))
770 s3c24xx_serial_stop_tx(port);
773 spin_unlock_irqrestore(&port->lock, flags);
777 /* interrupt handler for s3c64xx and later SoC's.*/
778 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
780 struct s3c24xx_uart_port *ourport = id;
781 struct uart_port *port = &ourport->port;
782 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
783 irqreturn_t ret = IRQ_HANDLED;
785 if (pend & S3C64XX_UINTM_RXD_MSK) {
786 ret = s3c24xx_serial_rx_chars(irq, id);
787 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
789 if (pend & S3C64XX_UINTM_TXD_MSK) {
790 ret = s3c24xx_serial_tx_chars(irq, id);
791 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
796 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
798 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
799 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
800 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
802 if (ufcon & S3C2410_UFCON_FIFOMODE) {
803 if ((ufstat & info->tx_fifomask) != 0 ||
804 (ufstat & info->tx_fifofull))
810 return s3c24xx_serial_txempty_nofifo(port);
813 /* no modem control lines */
814 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
816 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
818 if (umstat & S3C2410_UMSTAT_CTS)
819 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
821 return TIOCM_CAR | TIOCM_DSR;
824 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
826 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
828 if (mctrl & TIOCM_RTS)
829 umcon |= S3C2410_UMCOM_RTS_LOW;
831 umcon &= ~S3C2410_UMCOM_RTS_LOW;
833 wr_regl(port, S3C2410_UMCON, umcon);
836 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
841 spin_lock_irqsave(&port->lock, flags);
843 ucon = rd_regl(port, S3C2410_UCON);
846 ucon |= S3C2410_UCON_SBREAK;
848 ucon &= ~S3C2410_UCON_SBREAK;
850 wr_regl(port, S3C2410_UCON, ucon);
852 spin_unlock_irqrestore(&port->lock, flags);
855 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
857 struct s3c24xx_uart_dma *dma = p->dma;
860 /* Default slave configuration parameters */
861 dma->rx_conf.direction = DMA_DEV_TO_MEM;
862 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
863 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
864 dma->rx_conf.src_maxburst = 1;
866 dma->tx_conf.direction = DMA_MEM_TO_DEV;
867 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
868 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
869 dma->tx_conf.dst_maxburst = 1;
871 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
873 if (IS_ERR(dma->rx_chan))
874 return PTR_ERR(dma->rx_chan);
876 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
878 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
879 if (IS_ERR(dma->tx_chan)) {
880 ret = PTR_ERR(dma->tx_chan);
884 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
887 dma->rx_size = PAGE_SIZE;
889 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
895 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
896 dma->rx_size, DMA_FROM_DEVICE);
897 if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
903 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
904 UART_XMIT_SIZE, DMA_TO_DEVICE);
905 if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
913 dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
918 dma_release_channel(dma->tx_chan);
920 dma_release_channel(dma->rx_chan);
924 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
926 struct s3c24xx_uart_dma *dma = p->dma;
929 dmaengine_terminate_all(dma->rx_chan);
930 dma_unmap_single(p->port.dev, dma->rx_addr,
931 dma->rx_size, DMA_FROM_DEVICE);
933 dma_release_channel(dma->rx_chan);
938 dmaengine_terminate_all(dma->tx_chan);
939 dma_unmap_single(p->port.dev, dma->tx_addr,
940 UART_XMIT_SIZE, DMA_TO_DEVICE);
941 dma_release_channel(dma->tx_chan);
946 static void s3c24xx_serial_shutdown(struct uart_port *port)
948 struct s3c24xx_uart_port *ourport = to_ourport(port);
950 if (ourport->tx_claimed) {
951 if (!s3c24xx_serial_has_interrupt_mask(port))
952 free_irq(ourport->tx_irq, ourport);
953 tx_enabled(port) = 0;
954 ourport->tx_claimed = 0;
955 ourport->tx_mode = 0;
958 if (ourport->rx_claimed) {
959 if (!s3c24xx_serial_has_interrupt_mask(port))
960 free_irq(ourport->rx_irq, ourport);
961 ourport->rx_claimed = 0;
962 rx_enabled(port) = 0;
965 /* Clear pending interrupts and mask all interrupts */
966 if (s3c24xx_serial_has_interrupt_mask(port)) {
967 free_irq(port->irq, ourport);
969 wr_regl(port, S3C64XX_UINTP, 0xf);
970 wr_regl(port, S3C64XX_UINTM, 0xf);
974 s3c24xx_serial_release_dma(ourport);
976 ourport->tx_in_progress = 0;
979 static int s3c24xx_serial_startup(struct uart_port *port)
981 struct s3c24xx_uart_port *ourport = to_ourport(port);
984 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
985 port, (unsigned long long)port->mapbase, port->membase);
987 rx_enabled(port) = 1;
989 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
990 s3c24xx_serial_portname(port), ourport);
993 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
997 ourport->rx_claimed = 1;
999 dbg("requesting tx irq...\n");
1001 tx_enabled(port) = 1;
1003 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1004 s3c24xx_serial_portname(port), ourport);
1007 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1011 ourport->tx_claimed = 1;
1013 dbg("s3c24xx_serial_startup ok\n");
1015 /* the port reset code should have done the correct
1016 * register setup for the port controls */
1021 s3c24xx_serial_shutdown(port);
1025 static int s3c64xx_serial_startup(struct uart_port *port)
1027 struct s3c24xx_uart_port *ourport = to_ourport(port);
1028 unsigned long flags;
1032 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1033 port, (unsigned long long)port->mapbase, port->membase);
1035 wr_regl(port, S3C64XX_UINTM, 0xf);
1037 ret = s3c24xx_serial_request_dma(ourport);
1040 "DMA request failed, DMA will not be used\n");
1041 devm_kfree(port->dev, ourport->dma);
1042 ourport->dma = NULL;
1046 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1047 s3c24xx_serial_portname(port), ourport);
1049 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1053 /* For compatibility with s3c24xx Soc's */
1054 rx_enabled(port) = 1;
1055 ourport->rx_claimed = 1;
1056 tx_enabled(port) = 0;
1057 ourport->tx_claimed = 1;
1059 spin_lock_irqsave(&port->lock, flags);
1061 ufcon = rd_regl(port, S3C2410_UFCON);
1062 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1063 if (!uart_console(port))
1064 ufcon |= S3C2410_UFCON_RESETTX;
1065 wr_regl(port, S3C2410_UFCON, ufcon);
1067 enable_rx_pio(ourport);
1069 spin_unlock_irqrestore(&port->lock, flags);
1071 /* Enable Rx Interrupt */
1072 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1074 dbg("s3c64xx_serial_startup ok\n");
1078 /* power power management control */
1080 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1083 struct s3c24xx_uart_port *ourport = to_ourport(port);
1084 int timeout = 10000;
1086 ourport->pm_level = level;
1090 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1093 if (!IS_ERR(ourport->baudclk))
1094 clk_disable_unprepare(ourport->baudclk);
1096 clk_disable_unprepare(ourport->clk);
1100 clk_prepare_enable(ourport->clk);
1102 if (!IS_ERR(ourport->baudclk))
1103 clk_prepare_enable(ourport->baudclk);
1107 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1111 /* baud rate calculation
1113 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1114 * of different sources, including the peripheral clock ("pclk") and an
1115 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1116 * with a programmable extra divisor.
1118 * The following code goes through the clock sources, and calculates the
1119 * baud clocks (and the resultant actual baud rates) and then tries to
1120 * pick the closest one and select that.
1124 #define MAX_CLK_NAME_LENGTH 15
1126 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1128 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1131 if (info->num_clks == 1)
1134 ucon = rd_regl(port, S3C2410_UCON);
1135 ucon &= info->clksel_mask;
1136 return ucon >> info->clksel_shift;
1139 static void s3c24xx_serial_setsource(struct uart_port *port,
1140 unsigned int clk_sel)
1142 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1145 if (info->num_clks == 1)
1148 ucon = rd_regl(port, S3C2410_UCON);
1149 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1152 ucon &= ~info->clksel_mask;
1153 ucon |= clk_sel << info->clksel_shift;
1154 wr_regl(port, S3C2410_UCON, ucon);
1157 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1158 unsigned int req_baud, struct clk **best_clk,
1159 unsigned int *clk_num)
1161 struct s3c24xx_uart_info *info = ourport->info;
1164 unsigned int cnt, baud, quot, best_quot = 0;
1165 char clkname[MAX_CLK_NAME_LENGTH];
1166 int calc_deviation, deviation = (1 << 30) - 1;
1168 for (cnt = 0; cnt < info->num_clks; cnt++) {
1169 /* Keep selected clock if provided */
1170 if (ourport->cfg->clk_sel &&
1171 !(ourport->cfg->clk_sel & (1 << cnt)))
1174 sprintf(clkname, "clk_uart_baud%d", cnt);
1175 clk = clk_get(ourport->port.dev, clkname);
1179 rate = clk_get_rate(clk);
1181 dev_err(ourport->port.dev,
1182 "Failed to get clock rate for %s.\n", clkname);
1187 if (ourport->info->has_divslot) {
1188 unsigned long div = rate / req_baud;
1190 /* The UDIVSLOT register on the newer UARTs allows us to
1191 * get a divisor adjustment of 1/16th on the baud clock.
1193 * We don't keep the UDIVSLOT value (the 16ths we
1194 * calculated by not multiplying the baud by 16) as it
1195 * is easy enough to recalculate.
1201 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1202 baud = rate / (quot * 16);
1206 calc_deviation = req_baud - baud;
1207 if (calc_deviation < 0)
1208 calc_deviation = -calc_deviation;
1210 if (calc_deviation < deviation) {
1212 * If we find a better clk, release the previous one, if
1215 if (!IS_ERR(*best_clk))
1220 deviation = calc_deviation;
1231 * This table takes the fractional value of the baud divisor and gives
1232 * the recommended setting for the UDIVSLOT register.
1234 static u16 udivslot_table[16] = {
1253 static void s3c24xx_serial_set_termios(struct uart_port *port,
1254 struct ktermios *termios,
1255 struct ktermios *old)
1257 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1258 struct s3c24xx_uart_port *ourport = to_ourport(port);
1259 struct clk *clk = ERR_PTR(-EINVAL);
1260 unsigned long flags;
1261 unsigned int baud, quot, clk_sel = 0;
1264 unsigned int udivslot = 0;
1267 * We don't support modem control lines.
1269 termios->c_cflag &= ~(HUPCL | CMSPAR);
1270 termios->c_cflag |= CLOCAL;
1273 * Ask the core to calculate the divisor for us.
1276 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1277 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1278 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1279 quot = port->custom_divisor;
1283 /* check to see if we need to change clock source */
1285 if (ourport->baudclk != clk) {
1286 clk_prepare_enable(clk);
1288 s3c24xx_serial_setsource(port, clk_sel);
1290 if (!IS_ERR(ourport->baudclk)) {
1291 clk_disable_unprepare(ourport->baudclk);
1292 ourport->baudclk = ERR_PTR(-EINVAL);
1295 ourport->baudclk = clk;
1296 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1299 if (ourport->info->has_divslot) {
1300 unsigned int div = ourport->baudclk_rate / baud;
1302 if (cfg->has_fracval) {
1303 udivslot = (div & 15);
1304 dbg("fracval = %04x\n", udivslot);
1306 udivslot = udivslot_table[div & 15];
1307 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1311 switch (termios->c_cflag & CSIZE) {
1313 dbg("config: 5bits/char\n");
1314 ulcon = S3C2410_LCON_CS5;
1317 dbg("config: 6bits/char\n");
1318 ulcon = S3C2410_LCON_CS6;
1321 dbg("config: 7bits/char\n");
1322 ulcon = S3C2410_LCON_CS7;
1326 dbg("config: 8bits/char\n");
1327 ulcon = S3C2410_LCON_CS8;
1331 /* preserve original lcon IR settings */
1332 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1334 if (termios->c_cflag & CSTOPB)
1335 ulcon |= S3C2410_LCON_STOPB;
1337 if (termios->c_cflag & PARENB) {
1338 if (termios->c_cflag & PARODD)
1339 ulcon |= S3C2410_LCON_PODD;
1341 ulcon |= S3C2410_LCON_PEVEN;
1343 ulcon |= S3C2410_LCON_PNONE;
1346 spin_lock_irqsave(&port->lock, flags);
1348 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1349 ulcon, quot, udivslot);
1351 wr_regl(port, S3C2410_ULCON, ulcon);
1352 wr_regl(port, S3C2410_UBRDIV, quot);
1354 port->status &= ~UPSTAT_AUTOCTS;
1356 umcon = rd_regl(port, S3C2410_UMCON);
1357 if (termios->c_cflag & CRTSCTS) {
1358 umcon |= S3C2410_UMCOM_AFC;
1359 /* Disable RTS when RX FIFO contains 63 bytes */
1360 umcon &= ~S3C2412_UMCON_AFC_8;
1361 port->status = UPSTAT_AUTOCTS;
1363 umcon &= ~S3C2410_UMCOM_AFC;
1365 wr_regl(port, S3C2410_UMCON, umcon);
1367 if (ourport->info->has_divslot)
1368 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1370 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1371 rd_regl(port, S3C2410_ULCON),
1372 rd_regl(port, S3C2410_UCON),
1373 rd_regl(port, S3C2410_UFCON));
1376 * Update the per-port timeout.
1378 uart_update_timeout(port, termios->c_cflag, baud);
1381 * Which character status flags are we interested in?
1383 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1384 if (termios->c_iflag & INPCK)
1385 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1386 S3C2410_UERSTAT_PARITY;
1388 * Which character status flags should we ignore?
1390 port->ignore_status_mask = 0;
1391 if (termios->c_iflag & IGNPAR)
1392 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1393 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1394 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1397 * Ignore all characters if CREAD is not set.
1399 if ((termios->c_cflag & CREAD) == 0)
1400 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1402 spin_unlock_irqrestore(&port->lock, flags);
1405 static const char *s3c24xx_serial_type(struct uart_port *port)
1407 switch (port->type) {
1415 return "S3C6400/10";
1421 #define MAP_SIZE (0x100)
1423 static void s3c24xx_serial_release_port(struct uart_port *port)
1425 release_mem_region(port->mapbase, MAP_SIZE);
1428 static int s3c24xx_serial_request_port(struct uart_port *port)
1430 const char *name = s3c24xx_serial_portname(port);
1431 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1434 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1436 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1438 if (flags & UART_CONFIG_TYPE &&
1439 s3c24xx_serial_request_port(port) == 0)
1440 port->type = info->type;
1444 * verify the new serial_struct (for TIOCSSERIAL).
1447 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1449 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1451 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1458 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1460 static struct console s3c24xx_serial_console;
1462 static int __init s3c24xx_serial_console_init(void)
1464 register_console(&s3c24xx_serial_console);
1467 console_initcall(s3c24xx_serial_console_init);
1469 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1471 #define S3C24XX_SERIAL_CONSOLE NULL
1474 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1475 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1476 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1480 static struct uart_ops s3c24xx_serial_ops = {
1481 .pm = s3c24xx_serial_pm,
1482 .tx_empty = s3c24xx_serial_tx_empty,
1483 .get_mctrl = s3c24xx_serial_get_mctrl,
1484 .set_mctrl = s3c24xx_serial_set_mctrl,
1485 .stop_tx = s3c24xx_serial_stop_tx,
1486 .start_tx = s3c24xx_serial_start_tx,
1487 .stop_rx = s3c24xx_serial_stop_rx,
1488 .break_ctl = s3c24xx_serial_break_ctl,
1489 .startup = s3c24xx_serial_startup,
1490 .shutdown = s3c24xx_serial_shutdown,
1491 .set_termios = s3c24xx_serial_set_termios,
1492 .type = s3c24xx_serial_type,
1493 .release_port = s3c24xx_serial_release_port,
1494 .request_port = s3c24xx_serial_request_port,
1495 .config_port = s3c24xx_serial_config_port,
1496 .verify_port = s3c24xx_serial_verify_port,
1497 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1498 .poll_get_char = s3c24xx_serial_get_poll_char,
1499 .poll_put_char = s3c24xx_serial_put_poll_char,
1503 static struct uart_driver s3c24xx_uart_drv = {
1504 .owner = THIS_MODULE,
1505 .driver_name = "s3c2410_serial",
1506 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1507 .cons = S3C24XX_SERIAL_CONSOLE,
1508 .dev_name = S3C24XX_SERIAL_NAME,
1509 .major = S3C24XX_SERIAL_MAJOR,
1510 .minor = S3C24XX_SERIAL_MINOR,
1513 #define __PORT_LOCK_UNLOCKED(i) \
1514 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1515 static struct s3c24xx_uart_port
1516 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1519 .lock = __PORT_LOCK_UNLOCKED(0),
1523 .ops = &s3c24xx_serial_ops,
1524 .flags = UPF_BOOT_AUTOCONF,
1530 .lock = __PORT_LOCK_UNLOCKED(1),
1534 .ops = &s3c24xx_serial_ops,
1535 .flags = UPF_BOOT_AUTOCONF,
1539 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1543 .lock = __PORT_LOCK_UNLOCKED(2),
1547 .ops = &s3c24xx_serial_ops,
1548 .flags = UPF_BOOT_AUTOCONF,
1553 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1556 .lock = __PORT_LOCK_UNLOCKED(3),
1560 .ops = &s3c24xx_serial_ops,
1561 .flags = UPF_BOOT_AUTOCONF,
1567 #undef __PORT_LOCK_UNLOCKED
1569 /* s3c24xx_serial_resetport
1571 * reset the fifos and other the settings.
1574 static void s3c24xx_serial_resetport(struct uart_port *port,
1575 struct s3c2410_uartcfg *cfg)
1577 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1578 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1579 unsigned int ucon_mask;
1581 ucon_mask = info->clksel_mask;
1582 if (info->type == PORT_S3C2440)
1583 ucon_mask |= S3C2440_UCON0_DIVMASK;
1586 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1588 /* reset both fifos */
1589 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1590 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1592 /* some delay is required after fifo reset */
1597 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1599 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1600 unsigned long val, void *data)
1602 struct s3c24xx_uart_port *port;
1603 struct uart_port *uport;
1605 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1606 uport = &port->port;
1608 /* check to see if port is enabled */
1610 if (port->pm_level != 0)
1613 /* try and work out if the baudrate is changing, we can detect
1614 * a change in rate, but we do not have support for detecting
1615 * a disturbance in the clock-rate over the change.
1618 if (IS_ERR(port->baudclk))
1621 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1624 if (val == CPUFREQ_PRECHANGE) {
1625 /* we should really shut the port down whilst the
1626 * frequency change is in progress. */
1628 } else if (val == CPUFREQ_POSTCHANGE) {
1629 struct ktermios *termios;
1630 struct tty_struct *tty;
1632 if (uport->state == NULL)
1635 tty = uport->state->port.tty;
1640 termios = &tty->termios;
1642 if (termios == NULL) {
1643 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1647 s3c24xx_serial_set_termios(uport, termios, NULL);
1655 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1657 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1659 return cpufreq_register_notifier(&port->freq_transition,
1660 CPUFREQ_TRANSITION_NOTIFIER);
1664 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1666 cpufreq_unregister_notifier(&port->freq_transition,
1667 CPUFREQ_TRANSITION_NOTIFIER);
1672 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1678 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1683 /* s3c24xx_serial_init_port
1685 * initialise a single serial port from the platform device given
1688 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1689 struct platform_device *platdev)
1691 struct uart_port *port = &ourport->port;
1692 struct s3c2410_uartcfg *cfg = ourport->cfg;
1693 struct resource *res;
1696 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1698 if (platdev == NULL)
1701 if (port->mapbase != 0)
1704 /* setup info for port */
1705 port->dev = &platdev->dev;
1707 /* Startup sequence is different for s3c64xx and higher SoC's */
1708 if (s3c24xx_serial_has_interrupt_mask(port))
1709 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1713 if (cfg->uart_flags & UPF_CONS_FLOW) {
1714 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1715 port->flags |= UPF_CONS_FLOW;
1718 /* sort our the physical and virtual addresses for each UART */
1720 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1722 dev_err(port->dev, "failed to find memory resource for uart\n");
1726 dbg("resource %pR)\n", res);
1728 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1729 if (!port->membase) {
1730 dev_err(port->dev, "failed to remap controller address\n");
1734 port->mapbase = res->start;
1735 ret = platform_get_irq(platdev, 0);
1740 ourport->rx_irq = ret;
1741 ourport->tx_irq = ret + 1;
1744 if (!s3c24xx_serial_has_interrupt_mask(port)) {
1745 ret = platform_get_irq(platdev, 1);
1747 ourport->tx_irq = ret;
1750 * DMA is currently supported only on DT platforms, if DMA properties
1753 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1755 ourport->dma = devm_kzalloc(port->dev,
1756 sizeof(*ourport->dma),
1758 if (!ourport->dma) {
1764 ourport->clk = clk_get(&platdev->dev, "uart");
1765 if (IS_ERR(ourport->clk)) {
1766 pr_err("%s: Controller clock not found\n",
1767 dev_name(&platdev->dev));
1768 ret = PTR_ERR(ourport->clk);
1772 ret = clk_prepare_enable(ourport->clk);
1774 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1775 clk_put(ourport->clk);
1779 /* Keep all interrupts masked and cleared */
1780 if (s3c24xx_serial_has_interrupt_mask(port)) {
1781 wr_regl(port, S3C64XX_UINTM, 0xf);
1782 wr_regl(port, S3C64XX_UINTP, 0xf);
1783 wr_regl(port, S3C64XX_UINTSP, 0xf);
1786 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1787 &port->mapbase, port->membase, port->irq,
1788 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1790 /* reset the fifos (and setup the uart) */
1791 s3c24xx_serial_resetport(port, cfg);
1800 /* Device driver serial port probe */
1802 static const struct of_device_id s3c24xx_uart_dt_match[];
1803 static int probe_index;
1805 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1806 struct platform_device *pdev)
1809 if (pdev->dev.of_node) {
1810 const struct of_device_id *match;
1811 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1812 return (struct s3c24xx_serial_drv_data *)match->data;
1815 return (struct s3c24xx_serial_drv_data *)
1816 platform_get_device_id(pdev)->driver_data;
1819 static int s3c24xx_serial_probe(struct platform_device *pdev)
1821 struct device_node *np = pdev->dev.of_node;
1822 struct s3c24xx_uart_port *ourport;
1823 int index = probe_index;
1827 ret = of_alias_get_id(np, "serial");
1832 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1834 if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1835 dev_err(&pdev->dev, "serial%d out of range\n", index);
1838 ourport = &s3c24xx_serial_ports[index];
1840 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1841 if (!ourport->drv_data) {
1842 dev_err(&pdev->dev, "could not find driver data\n");
1846 ourport->baudclk = ERR_PTR(-EINVAL);
1847 ourport->info = ourport->drv_data->info;
1848 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1849 dev_get_platdata(&pdev->dev) :
1850 ourport->drv_data->def_cfg;
1853 of_property_read_u32(np,
1854 "samsung,uart-fifosize", &ourport->port.fifosize);
1856 if (ourport->drv_data->fifosize[index])
1857 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1858 else if (ourport->info->fifosize)
1859 ourport->port.fifosize = ourport->info->fifosize;
1862 * DMA transfers must be aligned at least to cache line size,
1863 * so find minimal transfer size suitable for DMA mode
1865 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1866 dma_get_cache_alignment());
1868 dbg("%s: initialising port %p...\n", __func__, ourport);
1870 ret = s3c24xx_serial_init_port(ourport, pdev);
1874 if (!s3c24xx_uart_drv.state) {
1875 ret = uart_register_driver(&s3c24xx_uart_drv);
1877 pr_err("Failed to register Samsung UART driver\n");
1882 dbg("%s: adding port\n", __func__);
1883 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1884 platform_set_drvdata(pdev, &ourport->port);
1887 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1888 * so that a potential re-enablement through the pm-callback overlaps
1889 * and keeps the clock enabled in this case.
1891 clk_disable_unprepare(ourport->clk);
1893 ret = s3c24xx_serial_cpufreq_register(ourport);
1895 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1902 static int s3c24xx_serial_remove(struct platform_device *dev)
1904 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1907 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1908 uart_remove_one_port(&s3c24xx_uart_drv, port);
1911 uart_unregister_driver(&s3c24xx_uart_drv);
1916 /* UART power management code */
1917 #ifdef CONFIG_PM_SLEEP
1918 static int s3c24xx_serial_suspend(struct device *dev)
1920 struct uart_port *port = s3c24xx_dev_to_port(dev);
1923 uart_suspend_port(&s3c24xx_uart_drv, port);
1928 static int s3c24xx_serial_resume(struct device *dev)
1930 struct uart_port *port = s3c24xx_dev_to_port(dev);
1931 struct s3c24xx_uart_port *ourport = to_ourport(port);
1934 clk_prepare_enable(ourport->clk);
1935 if (!IS_ERR(ourport->baudclk))
1936 clk_prepare_enable(ourport->baudclk);
1937 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1938 if (!IS_ERR(ourport->baudclk))
1939 clk_disable_unprepare(ourport->baudclk);
1940 clk_disable_unprepare(ourport->clk);
1942 uart_resume_port(&s3c24xx_uart_drv, port);
1948 static int s3c24xx_serial_resume_noirq(struct device *dev)
1950 struct uart_port *port = s3c24xx_dev_to_port(dev);
1951 struct s3c24xx_uart_port *ourport = to_ourport(port);
1954 /* restore IRQ mask */
1955 if (s3c24xx_serial_has_interrupt_mask(port)) {
1956 unsigned int uintm = 0xf;
1957 if (tx_enabled(port))
1958 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1959 if (rx_enabled(port))
1960 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1961 clk_prepare_enable(ourport->clk);
1962 if (!IS_ERR(ourport->baudclk))
1963 clk_prepare_enable(ourport->baudclk);
1964 wr_regl(port, S3C64XX_UINTM, uintm);
1965 if (!IS_ERR(ourport->baudclk))
1966 clk_disable_unprepare(ourport->baudclk);
1967 clk_disable_unprepare(ourport->clk);
1974 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1975 .suspend = s3c24xx_serial_suspend,
1976 .resume = s3c24xx_serial_resume,
1977 .resume_noirq = s3c24xx_serial_resume_noirq,
1979 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1981 #else /* !CONFIG_PM_SLEEP */
1983 #define SERIAL_SAMSUNG_PM_OPS NULL
1984 #endif /* CONFIG_PM_SLEEP */
1988 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1990 static struct uart_port *cons_uart;
1993 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1995 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1996 unsigned long ufstat, utrstat;
1998 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1999 /* fifo mode - check amount of data in fifo registers... */
2001 ufstat = rd_regl(port, S3C2410_UFSTAT);
2002 return (ufstat & info->tx_fifofull) ? 0 : 1;
2005 /* in non-fifo mode, we go and use the tx buffer empty */
2007 utrstat = rd_regl(port, S3C2410_UTRSTAT);
2008 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2012 s3c24xx_port_configured(unsigned int ucon)
2014 /* consider the serial port configured if the tx/rx mode set */
2015 return (ucon & 0xf) != 0;
2018 #ifdef CONFIG_CONSOLE_POLL
2020 * Console polling routines for writing and reading from the uart while
2021 * in an interrupt or debug context.
2024 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2026 struct s3c24xx_uart_port *ourport = to_ourport(port);
2027 unsigned int ufstat;
2029 ufstat = rd_regl(port, S3C2410_UFSTAT);
2030 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2031 return NO_POLL_CHAR;
2033 return rd_regb(port, S3C2410_URXH);
2036 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2039 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2040 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2042 /* not possible to xmit on unconfigured port */
2043 if (!s3c24xx_port_configured(ucon))
2046 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2048 wr_regb(port, S3C2410_UTXH, c);
2051 #endif /* CONFIG_CONSOLE_POLL */
2054 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2056 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2058 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2060 wr_regb(port, S3C2410_UTXH, ch);
2064 s3c24xx_serial_console_write(struct console *co, const char *s,
2067 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2069 /* not possible to xmit on unconfigured port */
2070 if (!s3c24xx_port_configured(ucon))
2073 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2077 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2078 int *parity, int *bits)
2083 unsigned int ubrdiv;
2085 unsigned int clk_sel;
2086 char clk_name[MAX_CLK_NAME_LENGTH];
2088 ulcon = rd_regl(port, S3C2410_ULCON);
2089 ucon = rd_regl(port, S3C2410_UCON);
2090 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2092 dbg("s3c24xx_serial_get_options: port=%p\n"
2093 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2094 port, ulcon, ucon, ubrdiv);
2096 if (s3c24xx_port_configured(ucon)) {
2097 switch (ulcon & S3C2410_LCON_CSMASK) {
2098 case S3C2410_LCON_CS5:
2101 case S3C2410_LCON_CS6:
2104 case S3C2410_LCON_CS7:
2107 case S3C2410_LCON_CS8:
2113 switch (ulcon & S3C2410_LCON_PMASK) {
2114 case S3C2410_LCON_PEVEN:
2118 case S3C2410_LCON_PODD:
2122 case S3C2410_LCON_PNONE:
2127 /* now calculate the baud rate */
2129 clk_sel = s3c24xx_serial_getsource(port);
2130 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2132 clk = clk_get(port->dev, clk_name);
2134 rate = clk_get_rate(clk);
2138 *baud = rate / (16 * (ubrdiv + 1));
2139 dbg("calculated baud %d\n", *baud);
2145 s3c24xx_serial_console_setup(struct console *co, char *options)
2147 struct uart_port *port;
2153 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2154 co, co->index, options);
2156 /* is this a valid port */
2158 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2161 port = &s3c24xx_serial_ports[co->index].port;
2163 /* is the port configured? */
2165 if (port->mapbase == 0x0)
2170 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2173 * Check whether an invalid uart number has been specified, and
2174 * if so, search for the first available port that does have
2178 uart_parse_options(options, &baud, &parity, &bits, &flow);
2180 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2182 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2184 return uart_set_options(port, co, baud, parity, bits, flow);
2187 static struct console s3c24xx_serial_console = {
2188 .name = S3C24XX_SERIAL_NAME,
2189 .device = uart_console_device,
2190 .flags = CON_PRINTBUFFER,
2192 .write = s3c24xx_serial_console_write,
2193 .setup = s3c24xx_serial_console_setup,
2194 .data = &s3c24xx_uart_drv,
2196 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2198 #ifdef CONFIG_CPU_S3C2410
2199 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2200 .info = &(struct s3c24xx_uart_info) {
2201 .name = "Samsung S3C2410 UART",
2202 .type = PORT_S3C2410,
2204 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2205 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2206 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2207 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2208 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2209 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2210 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2212 .clksel_mask = S3C2410_UCON_CLKMASK,
2213 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2215 .def_cfg = &(struct s3c2410_uartcfg) {
2216 .ucon = S3C2410_UCON_DEFAULT,
2217 .ufcon = S3C2410_UFCON_DEFAULT,
2220 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2222 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2225 #ifdef CONFIG_CPU_S3C2412
2226 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2227 .info = &(struct s3c24xx_uart_info) {
2228 .name = "Samsung S3C2412 UART",
2229 .type = PORT_S3C2412,
2232 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2233 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2234 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2235 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2236 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2237 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2238 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2240 .clksel_mask = S3C2412_UCON_CLKMASK,
2241 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2243 .def_cfg = &(struct s3c2410_uartcfg) {
2244 .ucon = S3C2410_UCON_DEFAULT,
2245 .ufcon = S3C2410_UFCON_DEFAULT,
2248 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2250 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2253 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2254 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2255 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2256 .info = &(struct s3c24xx_uart_info) {
2257 .name = "Samsung S3C2440 UART",
2258 .type = PORT_S3C2440,
2261 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2262 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2263 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2264 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2265 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2266 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2267 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2269 .clksel_mask = S3C2412_UCON_CLKMASK,
2270 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2272 .def_cfg = &(struct s3c2410_uartcfg) {
2273 .ucon = S3C2410_UCON_DEFAULT,
2274 .ufcon = S3C2410_UFCON_DEFAULT,
2277 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2279 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2282 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2283 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2284 .info = &(struct s3c24xx_uart_info) {
2285 .name = "Samsung S3C6400 UART",
2286 .type = PORT_S3C6400,
2289 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2290 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2291 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2292 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2293 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2294 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2295 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2297 .clksel_mask = S3C6400_UCON_CLKMASK,
2298 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2300 .def_cfg = &(struct s3c2410_uartcfg) {
2301 .ucon = S3C2410_UCON_DEFAULT,
2302 .ufcon = S3C2410_UFCON_DEFAULT,
2305 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2307 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2310 #ifdef CONFIG_CPU_S5PV210
2311 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2312 .info = &(struct s3c24xx_uart_info) {
2313 .name = "Samsung S5PV210 UART",
2314 .type = PORT_S3C6400,
2316 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2317 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2318 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2319 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2320 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2321 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2322 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2324 .clksel_mask = S5PV210_UCON_CLKMASK,
2325 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2327 .def_cfg = &(struct s3c2410_uartcfg) {
2328 .ucon = S5PV210_UCON_DEFAULT,
2329 .ufcon = S5PV210_UFCON_DEFAULT,
2331 .fifosize = { 256, 64, 16, 16 },
2333 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2335 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2338 #if defined(CONFIG_ARCH_EXYNOS)
2339 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2340 .info = &(struct s3c24xx_uart_info) { \
2341 .name = "Samsung Exynos UART", \
2342 .type = PORT_S3C6400, \
2344 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2345 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2346 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2347 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2348 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2349 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2350 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2353 .clksel_shift = 0, \
2355 .def_cfg = &(struct s3c2410_uartcfg) { \
2356 .ucon = S5PV210_UCON_DEFAULT, \
2357 .ufcon = S5PV210_UFCON_DEFAULT, \
2361 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2362 EXYNOS_COMMON_SERIAL_DRV_DATA,
2363 .fifosize = { 256, 64, 16, 16 },
2366 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2367 EXYNOS_COMMON_SERIAL_DRV_DATA,
2368 .fifosize = { 64, 256, 16, 256 },
2371 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2372 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2374 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2375 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2378 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2380 .name = "s3c2410-uart",
2381 .driver_data = S3C2410_SERIAL_DRV_DATA,
2383 .name = "s3c2412-uart",
2384 .driver_data = S3C2412_SERIAL_DRV_DATA,
2386 .name = "s3c2440-uart",
2387 .driver_data = S3C2440_SERIAL_DRV_DATA,
2389 .name = "s3c6400-uart",
2390 .driver_data = S3C6400_SERIAL_DRV_DATA,
2392 .name = "s5pv210-uart",
2393 .driver_data = S5PV210_SERIAL_DRV_DATA,
2395 .name = "exynos4210-uart",
2396 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2398 .name = "exynos5433-uart",
2399 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2403 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2406 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2407 { .compatible = "samsung,s3c2410-uart",
2408 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2409 { .compatible = "samsung,s3c2412-uart",
2410 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2411 { .compatible = "samsung,s3c2440-uart",
2412 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2413 { .compatible = "samsung,s3c6400-uart",
2414 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2415 { .compatible = "samsung,s5pv210-uart",
2416 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2417 { .compatible = "samsung,exynos4210-uart",
2418 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2419 { .compatible = "samsung,exynos5433-uart",
2420 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2423 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2426 static struct platform_driver samsung_serial_driver = {
2427 .probe = s3c24xx_serial_probe,
2428 .remove = s3c24xx_serial_remove,
2429 .id_table = s3c24xx_serial_driver_ids,
2431 .name = "samsung-uart",
2432 .pm = SERIAL_SAMSUNG_PM_OPS,
2433 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2437 module_platform_driver(samsung_serial_driver);
2439 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2444 struct samsung_early_console_data {
2448 static void samsung_early_busyuart(struct uart_port *port)
2450 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2454 static void samsung_early_busyuart_fifo(struct uart_port *port)
2456 struct samsung_early_console_data *data = port->private_data;
2458 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2462 static void samsung_early_putc(struct uart_port *port, int c)
2464 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2465 samsung_early_busyuart_fifo(port);
2467 samsung_early_busyuart(port);
2469 writeb(c, port->membase + S3C2410_UTXH);
2472 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2474 struct earlycon_device *dev = con->data;
2476 uart_console_write(&dev->port, s, n, samsung_early_putc);
2479 static int __init samsung_early_console_setup(struct earlycon_device *device,
2482 if (!device->port.membase)
2485 device->con->write = samsung_early_write;
2490 static struct samsung_early_console_data s3c2410_early_console_data = {
2491 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2494 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2497 device->port.private_data = &s3c2410_early_console_data;
2498 return samsung_early_console_setup(device, opt);
2500 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2501 s3c2410_early_console_setup);
2503 /* S3C2412, S3C2440, S3C64xx */
2504 static struct samsung_early_console_data s3c2440_early_console_data = {
2505 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2508 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2511 device->port.private_data = &s3c2440_early_console_data;
2512 return samsung_early_console_setup(device, opt);
2514 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2515 s3c2440_early_console_setup);
2516 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2517 s3c2440_early_console_setup);
2518 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2519 s3c2440_early_console_setup);
2521 /* S5PV210, EXYNOS */
2522 static struct samsung_early_console_data s5pv210_early_console_data = {
2523 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2526 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2529 device->port.private_data = &s5pv210_early_console_data;
2530 return samsung_early_console_setup(device, opt);
2532 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2533 s5pv210_early_console_setup);
2534 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2535 s5pv210_early_console_setup);
2538 MODULE_ALIAS("platform:samsung-uart");
2539 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2540 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2541 MODULE_LICENSE("GPL v2");