drivers/tty/serial/samsung.c

   1 /*
   2  * Driver core for Samsung SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /* Hote on 2410 error handling
  13  *
  14  * The s3c2410 manual has a love/hate affair with the contents of the
  15  * UERSTAT register in the UART blocks, and keeps marking some of the
  16  * error bits as reserved. Having checked with the s3c2410x01,
  17  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  18  * feature from the latter versions of the manual.
  19  *
  20  * If it becomes aparrent that latter versions of the 2410 remove these
  21  * bits, then action will have to be taken to differentiate the versions
  22  * and change the policy on BREAK
  23  *
  24  * BJD, 04-Nov-2004
  25 */
  26
  27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28 #define SUPPORT_SYSRQ
  29 #endif
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/ioport.h>
  36 #include <linux/io.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/init.h>
  39 #include <linux/sysrq.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42 #include <linux/tty_flip.h>
  43 #include <linux/serial_core.h>
  44 #include <linux/serial.h>
  45 #include <linux/serial_s3c.h>
  46 #include <linux/delay.h>
  47 #include <linux/clk.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/of.h>
  50
  51 #include <asm/irq.h>
  52
  53 #include "samsung.h"
  54
  55 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  56         !defined(MODULE)
  57
  58 extern void printascii(const char *);
  59
  60 __printf(1, 2)
  61 static void dbg(const char *fmt, ...)
  62 {
  63         va_list va;
  64         char buff[256];
  65
  66         va_start(va, fmt);
  67         vscnprintf(buff, sizeof(buff), fmt, va);
  68         va_end(va);
  69
  70         printascii(buff);
  71 }
  72
  73 #else
  74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  75 #endif
  76
  77 /* UART name and device definitions */
  78
  79 #define S3C24XX_SERIAL_NAME     "ttySAC"
  80 #define S3C24XX_SERIAL_MAJOR    204
  81 #define S3C24XX_SERIAL_MINOR    64
  82
  83 #define S3C24XX_TX_PIO                  1
  84 #define S3C24XX_TX_DMA                  2
  85 #define S3C24XX_RX_PIO                  1
  86 #define S3C24XX_RX_DMA                  2
  87 /* macros to change one thing to another */
  88
  89 #define tx_enabled(port) ((port)->unused[0])
  90 #define rx_enabled(port) ((port)->unused[1])
  91
  92 /* flag to ignore all characters coming in */
  93 #define RXSTAT_DUMMY_READ (0x10000000)
  94
  95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  96 {
  97         return container_of(port, struct s3c24xx_uart_port, port);
  98 }
  99
 100 /* translate a port to the device name */
 101
 102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 103 {
 104         return to_platform_device(port->dev)->name;
 105 }
 106
 107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 108 {
 109         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 110 }
 111
 112 /*
 113  * s3c64xx and later SoC's include the interrupt mask and status registers in
 114  * the controller itself, unlike the s3c24xx SoC's which have these registers
 115  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 116  */
 117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 118 {
 119         return to_ourport(port)->info->type == PORT_S3C6400;
 120 }
 121
 122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 123 {
 124         unsigned long flags;
 125         unsigned int ucon, ufcon;
 126         int count = 10000;
 127
 128         spin_lock_irqsave(&port->lock, flags);
 129
 130         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 131                 udelay(100);
 132
 133         ufcon = rd_regl(port, S3C2410_UFCON);
 134         ufcon |= S3C2410_UFCON_RESETRX;
 135         wr_regl(port, S3C2410_UFCON, ufcon);
 136
 137         ucon = rd_regl(port, S3C2410_UCON);
 138         ucon |= S3C2410_UCON_RXIRQMODE;
 139         wr_regl(port, S3C2410_UCON, ucon);
 140
 141         rx_enabled(port) = 1;
 142         spin_unlock_irqrestore(&port->lock, flags);
 143 }
 144
 145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 146 {
 147         unsigned long flags;
 148         unsigned int ucon;
 149
 150         spin_lock_irqsave(&port->lock, flags);
 151
 152         ucon = rd_regl(port, S3C2410_UCON);
 153         ucon &= ~S3C2410_UCON_RXIRQMODE;
 154         wr_regl(port, S3C2410_UCON, ucon);
 155
 156         rx_enabled(port) = 0;
 157         spin_unlock_irqrestore(&port->lock, flags);
 158 }
 159
 160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 161 {
 162         struct s3c24xx_uart_port *ourport = to_ourport(port);
 163         struct s3c24xx_uart_dma *dma = ourport->dma;
 164         struct circ_buf *xmit = &port->state->xmit;
 165         struct dma_tx_state state;
 166         int count;
 167
 168         if (!tx_enabled(port))
 169                 return;
 170
 171         if (s3c24xx_serial_has_interrupt_mask(port))
 172                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 173         else
 174                 disable_irq_nosync(ourport->tx_irq);
 175
 176         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 177                 dmaengine_pause(dma->tx_chan);
 178                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 179                 dmaengine_terminate_all(dma->tx_chan);
 180                 dma_sync_single_for_cpu(ourport->port.dev,
 181                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 182                 async_tx_ack(dma->tx_desc);
 183                 count = dma->tx_bytes_requested - state.residue;
 184                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 185                 port->icount.tx += count;
 186         }
 187
 188         tx_enabled(port) = 0;
 189         ourport->tx_in_progress = 0;
 190
 191         if (port->flags & UPF_CONS_FLOW)
 192                 s3c24xx_serial_rx_enable(port);
 193
 194         ourport->tx_mode = 0;
 195 }
 196
 197 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 198
 199 static void s3c24xx_serial_tx_dma_complete(void *args)
 200 {
 201         struct s3c24xx_uart_port *ourport = args;
 202         struct uart_port *port = &ourport->port;
 203         struct circ_buf *xmit = &port->state->xmit;
 204         struct s3c24xx_uart_dma *dma = ourport->dma;
 205         struct dma_tx_state state;
 206         unsigned long flags;
 207         int count;
 208
 209
 210         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 211         count = dma->tx_bytes_requested - state.residue;
 212         async_tx_ack(dma->tx_desc);
 213
 214         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 215                                 dma->tx_size, DMA_TO_DEVICE);
 216
 217         spin_lock_irqsave(&port->lock, flags);
 218
 219         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 220         port->icount.tx += count;
 221         ourport->tx_in_progress = 0;
 222
 223         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 224                 uart_write_wakeup(port);
 225
 226         s3c24xx_serial_start_next_tx(ourport);
 227         spin_unlock_irqrestore(&port->lock, flags);
 228 }
 229
 230 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 231 {
 232         struct uart_port *port = &ourport->port;
 233         u32 ucon;
 234
 235         /* Mask Tx interrupt */
 236         if (s3c24xx_serial_has_interrupt_mask(port))
 237                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 238         else
 239                 disable_irq_nosync(ourport->tx_irq);
 240
 241         /* Enable tx dma mode */
 242         ucon = rd_regl(port, S3C2410_UCON);
 243         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 244         ucon |= (dma_get_cache_alignment() >= 16) ?
 245                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 246         ucon |= S3C64XX_UCON_TXMODE_DMA;
 247         wr_regl(port,  S3C2410_UCON, ucon);
 248
 249         ourport->tx_mode = S3C24XX_TX_DMA;
 250 }
 251
 252 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 253 {
 254         struct uart_port *port = &ourport->port;
 255         u32 ucon, ufcon;
 256
 257         /* Set ufcon txtrig */
 258         ourport->tx_in_progress = S3C24XX_TX_PIO;
 259         ufcon = rd_regl(port, S3C2410_UFCON);
 260         wr_regl(port,  S3C2410_UFCON, ufcon);
 261
 262         /* Enable tx pio mode */
 263         ucon = rd_regl(port, S3C2410_UCON);
 264         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 265         ucon |= S3C64XX_UCON_TXMODE_CPU;
 266         wr_regl(port,  S3C2410_UCON, ucon);
 267
 268         /* Unmask Tx interrupt */
 269         if (s3c24xx_serial_has_interrupt_mask(port))
 270                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 271                                   S3C64XX_UINTM);
 272         else
 273                 enable_irq(ourport->tx_irq);
 274
 275         ourport->tx_mode = S3C24XX_TX_PIO;
 276 }
 277
 278 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 279 {
 280         if (ourport->tx_mode != S3C24XX_TX_PIO)
 281                 enable_tx_pio(ourport);
 282 }
 283
 284 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 285                                       unsigned int count)
 286 {
 287         struct uart_port *port = &ourport->port;
 288         struct circ_buf *xmit = &port->state->xmit;
 289         struct s3c24xx_uart_dma *dma = ourport->dma;
 290
 291
 292         if (ourport->tx_mode != S3C24XX_TX_DMA)
 293                 enable_tx_dma(ourport);
 294
 295         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 296         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 297
 298         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 299                                 dma->tx_size, DMA_TO_DEVICE);
 300
 301         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 302                                 dma->tx_transfer_addr, dma->tx_size,
 303                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 304         if (!dma->tx_desc) {
 305                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 306                 return -EIO;
 307         }
 308
 309         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 310         dma->tx_desc->callback_param = ourport;
 311         dma->tx_bytes_requested = dma->tx_size;
 312
 313         ourport->tx_in_progress = S3C24XX_TX_DMA;
 314         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 315         dma_async_issue_pending(dma->tx_chan);
 316         return 0;
 317 }
 318
 319 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 320 {
 321         struct uart_port *port = &ourport->port;
 322         struct circ_buf *xmit = &port->state->xmit;
 323         unsigned long count;
 324
 325         /* Get data size up to the end of buffer */
 326         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 327
 328         if (!count) {
 329                 s3c24xx_serial_stop_tx(port);
 330                 return;
 331         }
 332
 333         if (!ourport->dma || !ourport->dma->tx_chan ||
 334             count < ourport->min_dma_size ||
 335             xmit->tail & (dma_get_cache_alignment() - 1))
 336                 s3c24xx_serial_start_tx_pio(ourport);
 337         else
 338                 s3c24xx_serial_start_tx_dma(ourport, count);
 339 }
 340
 341 static void s3c24xx_serial_start_tx(struct uart_port *port)
 342 {
 343         struct s3c24xx_uart_port *ourport = to_ourport(port);
 344         struct circ_buf *xmit = &port->state->xmit;
 345
 346         if (!tx_enabled(port)) {
 347                 if (port->flags & UPF_CONS_FLOW)
 348                         s3c24xx_serial_rx_disable(port);
 349
 350                 tx_enabled(port) = 1;
 351                 if (!ourport->dma || !ourport->dma->tx_chan)
 352                         s3c24xx_serial_start_tx_pio(ourport);
 353         }
 354
 355         if (ourport->dma && ourport->dma->tx_chan) {
 356                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 357                         s3c24xx_serial_start_next_tx(ourport);
 358         }
 359 }
 360
 361 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 362                 struct tty_port *tty, int count)
 363 {
 364         struct s3c24xx_uart_dma *dma = ourport->dma;
 365         int copied;
 366
 367         if (!count)
 368                 return;
 369
 370         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 371                                 dma->rx_size, DMA_FROM_DEVICE);
 372
 373         ourport->port.icount.rx += count;
 374         if (!tty) {
 375                 dev_err(ourport->port.dev, "No tty port\n");
 376                 return;
 377         }
 378         copied = tty_insert_flip_string(tty,
 379                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 380         if (copied != count) {
 381                 WARN_ON(1);
 382                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 383         }
 384 }
 385
 386 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 387 {
 388         struct s3c24xx_uart_port *ourport = to_ourport(port);
 389         struct s3c24xx_uart_dma *dma = ourport->dma;
 390         struct tty_port *t = &port->state->port;
 391         struct dma_tx_state state;
 392         enum dma_status dma_status;
 393         unsigned int received;
 394
 395         if (rx_enabled(port)) {
 396                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 397                 if (s3c24xx_serial_has_interrupt_mask(port))
 398                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 399                                         S3C64XX_UINTM);
 400                 else
 401                         disable_irq_nosync(ourport->rx_irq);
 402                 rx_enabled(port) = 0;
 403         }
 404         if (dma && dma->rx_chan) {
 405                 dmaengine_pause(dma->tx_chan);
 406                 dma_status = dmaengine_tx_status(dma->rx_chan,
 407                                 dma->rx_cookie, &state);
 408                 if (dma_status == DMA_IN_PROGRESS ||
 409                         dma_status == DMA_PAUSED) {
 410                         received = dma->rx_bytes_requested - state.residue;
 411                         dmaengine_terminate_all(dma->rx_chan);
 412                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 413                 }
 414         }
 415 }
 416
 417 static inline struct s3c24xx_uart_info
 418         *s3c24xx_port_to_info(struct uart_port *port)
 419 {
 420         return to_ourport(port)->info;
 421 }
 422
 423 static inline struct s3c2410_uartcfg
 424         *s3c24xx_port_to_cfg(struct uart_port *port)
 425 {
 426         struct s3c24xx_uart_port *ourport;
 427
 428         if (port->dev == NULL)
 429                 return NULL;
 430
 431         ourport = container_of(port, struct s3c24xx_uart_port, port);
 432         return ourport->cfg;
 433 }
 434
 435 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 436                                      unsigned long ufstat)
 437 {
 438         struct s3c24xx_uart_info *info = ourport->info;
 439
 440         if (ufstat & info->rx_fifofull)
 441                 return ourport->port.fifosize;
 442
 443         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 444 }
 445
 446 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 447 static void s3c24xx_serial_rx_dma_complete(void *args)
 448 {
 449         struct s3c24xx_uart_port *ourport = args;
 450         struct uart_port *port = &ourport->port;
 451
 452         struct s3c24xx_uart_dma *dma = ourport->dma;
 453         struct tty_port *t = &port->state->port;
 454         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 455
 456         struct dma_tx_state state;
 457         unsigned long flags;
 458         int received;
 459
 460         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 461         received  = dma->rx_bytes_requested - state.residue;
 462         async_tx_ack(dma->rx_desc);
 463
 464         spin_lock_irqsave(&port->lock, flags);
 465
 466         if (received)
 467                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 468
 469         if (tty) {
 470                 tty_flip_buffer_push(t);
 471                 tty_kref_put(tty);
 472         }
 473
 474         s3c64xx_start_rx_dma(ourport);
 475
 476         spin_unlock_irqrestore(&port->lock, flags);
 477 }
 478
 479 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 480 {
 481         struct s3c24xx_uart_dma *dma = ourport->dma;
 482
 483         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 484                                 dma->rx_size, DMA_FROM_DEVICE);
 485
 486         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 487                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 488                                 DMA_PREP_INTERRUPT);
 489         if (!dma->rx_desc) {
 490                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 491                 return;
 492         }
 493
 494         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 495         dma->rx_desc->callback_param = ourport;
 496         dma->rx_bytes_requested = dma->rx_size;
 497
 498         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 499         dma_async_issue_pending(dma->rx_chan);
 500 }
 501
 502 /* ? - where has parity gone?? */
 503 #define S3C2410_UERSTAT_PARITY (0x1000)
 504
 505 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 506 {
 507         struct uart_port *port = &ourport->port;
 508         unsigned int ucon;
 509
 510         /* set Rx mode to DMA mode */
 511         ucon = rd_regl(port, S3C2410_UCON);
 512         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 513                         S3C64XX_UCON_TIMEOUT_MASK |
 514                         S3C64XX_UCON_EMPTYINT_EN |
 515                         S3C64XX_UCON_DMASUS_EN |
 516                         S3C64XX_UCON_TIMEOUT_EN |
 517                         S3C64XX_UCON_RXMODE_MASK);
 518         ucon |= S3C64XX_UCON_RXBURST_16 |
 519                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 520                         S3C64XX_UCON_EMPTYINT_EN |
 521                         S3C64XX_UCON_TIMEOUT_EN |
 522                         S3C64XX_UCON_RXMODE_DMA;
 523         wr_regl(port, S3C2410_UCON, ucon);
 524
 525         ourport->rx_mode = S3C24XX_RX_DMA;
 526 }
 527
 528 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 529 {
 530         struct uart_port *port = &ourport->port;
 531         unsigned int ucon;
 532
 533         /* set Rx mode to DMA mode */
 534         ucon = rd_regl(port, S3C2410_UCON);
 535         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 536                         S3C64XX_UCON_EMPTYINT_EN |
 537                         S3C64XX_UCON_DMASUS_EN |
 538                         S3C64XX_UCON_TIMEOUT_EN |
 539                         S3C64XX_UCON_RXMODE_MASK);
 540         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 541                         S3C64XX_UCON_TIMEOUT_EN |
 542                         S3C64XX_UCON_RXMODE_CPU;
 543         wr_regl(port, S3C2410_UCON, ucon);
 544
 545         ourport->rx_mode = S3C24XX_RX_PIO;
 546 }
 547
 548 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 549
 550 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 551 {
 552         unsigned int utrstat, ufstat, received;
 553         struct s3c24xx_uart_port *ourport = dev_id;
 554         struct uart_port *port = &ourport->port;
 555         struct s3c24xx_uart_dma *dma = ourport->dma;
 556         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 557         struct tty_port *t = &port->state->port;
 558         unsigned long flags;
 559         struct dma_tx_state state;
 560
 561         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 562         ufstat = rd_regl(port, S3C2410_UFSTAT);
 563
 564         spin_lock_irqsave(&port->lock, flags);
 565
 566         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 567                 s3c64xx_start_rx_dma(ourport);
 568                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 569                         enable_rx_dma(ourport);
 570                 goto finish;
 571         }
 572
 573         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 574                 dmaengine_pause(dma->rx_chan);
 575                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 576                 dmaengine_terminate_all(dma->rx_chan);
 577                 received = dma->rx_bytes_requested - state.residue;
 578                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 579
 580                 enable_rx_pio(ourport);
 581         }
 582
 583         s3c24xx_serial_rx_drain_fifo(ourport);
 584
 585         if (tty) {
 586                 tty_flip_buffer_push(t);
 587                 tty_kref_put(tty);
 588         }
 589
 590         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 591
 592 finish:
 593         spin_unlock_irqrestore(&port->lock, flags);
 594
 595         return IRQ_HANDLED;
 596 }
 597
 598 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 599 {
 600         struct uart_port *port = &ourport->port;
 601         unsigned int ufcon, ch, flag, ufstat, uerstat;
 602         unsigned int fifocnt = 0;
 603         int max_count = port->fifosize;
 604
 605         while (max_count-- > 0) {
 606                 /*
 607                  * Receive all characters known to be in FIFO
 608                  * before reading FIFO level again
 609                  */
 610                 if (fifocnt == 0) {
 611                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 612                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 613                         if (fifocnt == 0)
 614                                 break;
 615                 }
 616                 fifocnt--;
 617
 618                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 619                 ch = rd_regb(port, S3C2410_URXH);
 620
 621                 if (port->flags & UPF_CONS_FLOW) {
 622                         int txe = s3c24xx_serial_txempty_nofifo(port);
 623
 624                         if (rx_enabled(port)) {
 625                                 if (!txe) {
 626                                         rx_enabled(port) = 0;
 627                                         continue;
 628                                 }
 629                         } else {
 630                                 if (txe) {
 631                                         ufcon = rd_regl(port, S3C2410_UFCON);
 632                                         ufcon |= S3C2410_UFCON_RESETRX;
 633                                         wr_regl(port, S3C2410_UFCON, ufcon);
 634                                         rx_enabled(port) = 1;
 635                                         return;
 636                                 }
 637                                 continue;
 638                         }
 639                 }
 640
 641                 /* insert the character into the buffer */
 642
 643                 flag = TTY_NORMAL;
 644                 port->icount.rx++;
 645
 646                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 647                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 648                             ch, uerstat);
 649
 650                         /* check for break */
 651                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 652                                 dbg("break!\n");
 653                                 port->icount.brk++;
 654                                 if (uart_handle_break(port))
 655                                         continue; /* Ignore character */
 656                         }
 657
 658                         if (uerstat & S3C2410_UERSTAT_FRAME)
 659                                 port->icount.frame++;
 660                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 661                                 port->icount.overrun++;
 662
 663                         uerstat &= port->read_status_mask;
 664
 665                         if (uerstat & S3C2410_UERSTAT_BREAK)
 666                                 flag = TTY_BREAK;
 667                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 668                                 flag = TTY_PARITY;
 669                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 670                                             S3C2410_UERSTAT_OVERRUN))
 671                                 flag = TTY_FRAME;
 672                 }
 673
 674                 if (uart_handle_sysrq_char(port, ch))
 675                         continue; /* Ignore character */
 676
 677                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 678                                  ch, flag);
 679         }
 680
 681         tty_flip_buffer_push(&port->state->port);
 682 }
 683
 684 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 685 {
 686         struct s3c24xx_uart_port *ourport = dev_id;
 687         struct uart_port *port = &ourport->port;
 688         unsigned long flags;
 689
 690         spin_lock_irqsave(&port->lock, flags);
 691         s3c24xx_serial_rx_drain_fifo(ourport);
 692         spin_unlock_irqrestore(&port->lock, flags);
 693
 694         return IRQ_HANDLED;
 695 }
 696
 697
 698 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 699 {
 700         struct s3c24xx_uart_port *ourport = dev_id;
 701
 702         if (ourport->dma && ourport->dma->rx_chan)
 703                 return s3c24xx_serial_rx_chars_dma(dev_id);
 704         return s3c24xx_serial_rx_chars_pio(dev_id);
 705 }
 706
 707 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 708 {
 709         struct s3c24xx_uart_port *ourport = id;
 710         struct uart_port *port = &ourport->port;
 711         struct circ_buf *xmit = &port->state->xmit;
 712         unsigned long flags;
 713         int count, dma_count = 0;
 714
 715         spin_lock_irqsave(&port->lock, flags);
 716
 717         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 718
 719         if (ourport->dma && ourport->dma->tx_chan &&
 720             count >= ourport->min_dma_size) {
 721                 int align = dma_get_cache_alignment() -
 722                         (xmit->tail & (dma_get_cache_alignment() - 1));
 723                 if (count-align >= ourport->min_dma_size) {
 724                         dma_count = count-align;
 725                         count = align;
 726                 }
 727         }
 728
 729         if (port->x_char) {
 730                 wr_regb(port, S3C2410_UTXH, port->x_char);
 731                 port->icount.tx++;
 732                 port->x_char = 0;
 733                 goto out;
 734         }
 735
 736         /* if there isn't anything more to transmit, or the uart is now
 737          * stopped, disable the uart and exit
 738         */
 739
 740         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 741                 s3c24xx_serial_stop_tx(port);
 742                 goto out;
 743         }
 744
 745         /* try and drain the buffer... */
 746
 747         if (count > port->fifosize) {
 748                 count = port->fifosize;
 749                 dma_count = 0;
 750         }
 751
 752         while (!uart_circ_empty(xmit) && count > 0) {
 753                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 754                         break;
 755
 756                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 757                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 758                 port->icount.tx++;
 759                 count--;
 760         }
 761
 762         if (!count && dma_count) {
 763                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 764                 goto out;
 765         }
 766
 767         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 768                 spin_unlock(&port->lock);
 769                 uart_write_wakeup(port);
 770                 spin_lock(&port->lock);
 771         }
 772
 773         if (uart_circ_empty(xmit))
 774                 s3c24xx_serial_stop_tx(port);
 775
 776 out:
 777         spin_unlock_irqrestore(&port->lock, flags);
 778         return IRQ_HANDLED;
 779 }
 780
 781 /* interrupt handler for s3c64xx and later SoC's.*/
 782 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 783 {
 784         struct s3c24xx_uart_port *ourport = id;
 785         struct uart_port *port = &ourport->port;
 786         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 787         irqreturn_t ret = IRQ_HANDLED;
 788
 789         if (pend & S3C64XX_UINTM_RXD_MSK) {
 790                 ret = s3c24xx_serial_rx_chars(irq, id);
 791                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 792         }
 793         if (pend & S3C64XX_UINTM_TXD_MSK) {
 794                 ret = s3c24xx_serial_tx_chars(irq, id);
 795                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 796         }
 797         return ret;
 798 }
 799
 800 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 801 {
 802         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 803         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 804         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 805
 806         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 807                 if ((ufstat & info->tx_fifomask) != 0 ||
 808                     (ufstat & info->tx_fifofull))
 809                         return 0;
 810
 811                 return 1;
 812         }
 813
 814         return s3c24xx_serial_txempty_nofifo(port);
 815 }
 816
 817 /* no modem control lines */
 818 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 819 {
 820         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 821
 822         if (umstat & S3C2410_UMSTAT_CTS)
 823                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 824         else
 825                 return TIOCM_CAR | TIOCM_DSR;
 826 }
 827
 828 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 829 {
 830         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 831
 832         if (mctrl & TIOCM_RTS)
 833                 umcon |= S3C2410_UMCOM_RTS_LOW;
 834         else
 835                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 836
 837         wr_regl(port, S3C2410_UMCON, umcon);
 838 }
 839
 840 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 841 {
 842         unsigned long flags;
 843         unsigned int ucon;
 844
 845         spin_lock_irqsave(&port->lock, flags);
 846
 847         ucon = rd_regl(port, S3C2410_UCON);
 848
 849         if (break_state)
 850                 ucon |= S3C2410_UCON_SBREAK;
 851         else
 852                 ucon &= ~S3C2410_UCON_SBREAK;
 853
 854         wr_regl(port, S3C2410_UCON, ucon);
 855
 856         spin_unlock_irqrestore(&port->lock, flags);
 857 }
 858
 859 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 860 {
 861         struct s3c24xx_uart_dma *dma = p->dma;
 862         dma_cap_mask_t mask;
 863         unsigned long flags;
 864
 865         /* Default slave configuration parameters */
 866         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 867         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 868         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 869         dma->rx_conf.src_maxburst       = 1;
 870
 871         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 872         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 873         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 874         dma->tx_conf.dst_maxburst       = 1;
 875
 876         dma_cap_zero(mask);
 877         dma_cap_set(DMA_SLAVE, mask);
 878
 879         dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 880                                         dma->rx_param, p->port.dev, "rx");
 881         if (!dma->rx_chan)
 882                 return -ENODEV;
 883
 884         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 885
 886         dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 887                                         dma->tx_param, p->port.dev, "tx");
 888         if (!dma->tx_chan) {
 889                 dma_release_channel(dma->rx_chan);
 890                 return -ENODEV;
 891         }
 892
 893         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 894
 895         /* RX buffer */
 896         dma->rx_size = PAGE_SIZE;
 897
 898         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 899
 900         if (!dma->rx_buf) {
 901                 dma_release_channel(dma->rx_chan);
 902                 dma_release_channel(dma->tx_chan);
 903                 return -ENOMEM;
 904         }
 905
 906         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
 907                                 dma->rx_size, DMA_FROM_DEVICE);
 908
 909         spin_lock_irqsave(&p->port.lock, flags);
 910
 911         /* TX buffer */
 912         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
 913                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 914
 915         spin_unlock_irqrestore(&p->port.lock, flags);
 916
 917         return 0;
 918 }
 919
 920 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 921 {
 922         struct s3c24xx_uart_dma *dma = p->dma;
 923
 924         if (dma->rx_chan) {
 925                 dmaengine_terminate_all(dma->rx_chan);
 926                 dma_unmap_single(p->port.dev, dma->rx_addr,
 927                                 dma->rx_size, DMA_FROM_DEVICE);
 928                 kfree(dma->rx_buf);
 929                 dma_release_channel(dma->rx_chan);
 930                 dma->rx_chan = NULL;
 931         }
 932
 933         if (dma->tx_chan) {
 934                 dmaengine_terminate_all(dma->tx_chan);
 935                 dma_unmap_single(p->port.dev, dma->tx_addr,
 936                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 937                 dma_release_channel(dma->tx_chan);
 938                 dma->tx_chan = NULL;
 939         }
 940 }
 941
 942 static void s3c24xx_serial_shutdown(struct uart_port *port)
 943 {
 944         struct s3c24xx_uart_port *ourport = to_ourport(port);
 945
 946         if (ourport->tx_claimed) {
 947                 if (!s3c24xx_serial_has_interrupt_mask(port))
 948                         free_irq(ourport->tx_irq, ourport);
 949                 tx_enabled(port) = 0;
 950                 ourport->tx_claimed = 0;
 951                 ourport->tx_mode = 0;
 952         }
 953
 954         if (ourport->rx_claimed) {
 955                 if (!s3c24xx_serial_has_interrupt_mask(port))
 956                         free_irq(ourport->rx_irq, ourport);
 957                 ourport->rx_claimed = 0;
 958                 rx_enabled(port) = 0;
 959         }
 960
 961         /* Clear pending interrupts and mask all interrupts */
 962         if (s3c24xx_serial_has_interrupt_mask(port)) {
 963                 free_irq(port->irq, ourport);
 964
 965                 wr_regl(port, S3C64XX_UINTP, 0xf);
 966                 wr_regl(port, S3C64XX_UINTM, 0xf);
 967         }
 968
 969         if (ourport->dma)
 970                 s3c24xx_serial_release_dma(ourport);
 971
 972         ourport->tx_in_progress = 0;
 973 }
 974
 975 static int s3c24xx_serial_startup(struct uart_port *port)
 976 {
 977         struct s3c24xx_uart_port *ourport = to_ourport(port);
 978         int ret;
 979
 980         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
 981             port, (unsigned long long)port->mapbase, port->membase);
 982
 983         rx_enabled(port) = 1;
 984
 985         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
 986                           s3c24xx_serial_portname(port), ourport);
 987
 988         if (ret != 0) {
 989                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
 990                 return ret;
 991         }
 992
 993         ourport->rx_claimed = 1;
 994
 995         dbg("requesting tx irq...\n");
 996
 997         tx_enabled(port) = 1;
 998
 999         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1000                           s3c24xx_serial_portname(port), ourport);
1001
1002         if (ret) {
1003                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1004                 goto err;
1005         }
1006
1007         ourport->tx_claimed = 1;
1008
1009         dbg("s3c24xx_serial_startup ok\n");
1010
1011         /* the port reset code should have done the correct
1012          * register setup for the port controls */
1013
1014         return ret;
1015
1016 err:
1017         s3c24xx_serial_shutdown(port);
1018         return ret;
1019 }
1020
1021 static int s3c64xx_serial_startup(struct uart_port *port)
1022 {
1023         struct s3c24xx_uart_port *ourport = to_ourport(port);
1024         unsigned long flags;
1025         unsigned int ufcon;
1026         int ret;
1027
1028         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1029             port, (unsigned long long)port->mapbase, port->membase);
1030
1031         wr_regl(port, S3C64XX_UINTM, 0xf);
1032         if (ourport->dma) {
1033                 ret = s3c24xx_serial_request_dma(ourport);
1034                 if (ret < 0) {
1035                         dev_warn(port->dev,
1036                                  "DMA request failed, DMA will not be used\n");
1037                         devm_kfree(port->dev, ourport->dma);
1038                         ourport->dma = NULL;
1039                 }
1040         }
1041
1042         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1043                           s3c24xx_serial_portname(port), ourport);
1044         if (ret) {
1045                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1046                 return ret;
1047         }
1048
1049         /* For compatibility with s3c24xx Soc's */
1050         rx_enabled(port) = 1;
1051         ourport->rx_claimed = 1;
1052         tx_enabled(port) = 0;
1053         ourport->tx_claimed = 1;
1054
1055         spin_lock_irqsave(&port->lock, flags);
1056
1057         ufcon = rd_regl(port, S3C2410_UFCON);
1058         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1059         if (!uart_console(port))
1060                 ufcon |= S3C2410_UFCON_RESETTX;
1061         wr_regl(port, S3C2410_UFCON, ufcon);
1062
1063         enable_rx_pio(ourport);
1064
1065         spin_unlock_irqrestore(&port->lock, flags);
1066
1067         /* Enable Rx Interrupt */
1068         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1069
1070         dbg("s3c64xx_serial_startup ok\n");
1071         return ret;
1072 }
1073
1074 /* power power management control */
1075
1076 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1077                               unsigned int old)
1078 {
1079         struct s3c24xx_uart_port *ourport = to_ourport(port);
1080         int timeout = 10000;
1081
1082         ourport->pm_level = level;
1083
1084         switch (level) {
1085         case 3:
1086                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1087                         udelay(100);
1088
1089                 if (!IS_ERR(ourport->baudclk))
1090                         clk_disable_unprepare(ourport->baudclk);
1091
1092                 clk_disable_unprepare(ourport->clk);
1093                 break;
1094
1095         case 0:
1096                 clk_prepare_enable(ourport->clk);
1097
1098                 if (!IS_ERR(ourport->baudclk))
1099                         clk_prepare_enable(ourport->baudclk);
1100
1101                 break;
1102         default:
1103                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1104         }
1105 }
1106
1107 /* baud rate calculation
1108  *
1109  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1110  * of different sources, including the peripheral clock ("pclk") and an
1111  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1112  * with a programmable extra divisor.
1113  *
1114  * The following code goes through the clock sources, and calculates the
1115  * baud clocks (and the resultant actual baud rates) and then tries to
1116  * pick the closest one and select that.
1117  *
1118 */
1119
1120 #define MAX_CLK_NAME_LENGTH 15
1121
1122 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1123 {
1124         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1125         unsigned int ucon;
1126
1127         if (info->num_clks == 1)
1128                 return 0;
1129
1130         ucon = rd_regl(port, S3C2410_UCON);
1131         ucon &= info->clksel_mask;
1132         return ucon >> info->clksel_shift;
1133 }
1134
1135 static void s3c24xx_serial_setsource(struct uart_port *port,
1136                         unsigned int clk_sel)
1137 {
1138         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1139         unsigned int ucon;
1140
1141         if (info->num_clks == 1)
1142                 return;
1143
1144         ucon = rd_regl(port, S3C2410_UCON);
1145         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1146                 return;
1147
1148         ucon &= ~info->clksel_mask;
1149         ucon |= clk_sel << info->clksel_shift;
1150         wr_regl(port, S3C2410_UCON, ucon);
1151 }
1152
1153 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1154                         unsigned int req_baud, struct clk **best_clk,
1155                         unsigned int *clk_num)
1156 {
1157         struct s3c24xx_uart_info *info = ourport->info;
1158         struct clk *clk;
1159         unsigned long rate;
1160         unsigned int cnt, baud, quot, best_quot = 0;
1161         char clkname[MAX_CLK_NAME_LENGTH];
1162         int calc_deviation, deviation = (1 << 30) - 1;
1163
1164         for (cnt = 0; cnt < info->num_clks; cnt++) {
1165                 /* Keep selected clock if provided */
1166                 if (ourport->cfg->clk_sel &&
1167                         !(ourport->cfg->clk_sel & (1 << cnt)))
1168                         continue;
1169
1170                 sprintf(clkname, "clk_uart_baud%d", cnt);
1171                 clk = clk_get(ourport->port.dev, clkname);
1172                 if (IS_ERR(clk))
1173                         continue;
1174
1175                 rate = clk_get_rate(clk);
1176                 if (!rate)
1177                         continue;
1178
1179                 if (ourport->info->has_divslot) {
1180                         unsigned long div = rate / req_baud;
1181
1182                         /* The UDIVSLOT register on the newer UARTs allows us to
1183                          * get a divisor adjustment of 1/16th on the baud clock.
1184                          *
1185                          * We don't keep the UDIVSLOT value (the 16ths we
1186                          * calculated by not multiplying the baud by 16) as it
1187                          * is easy enough to recalculate.
1188                          */
1189
1190                         quot = div / 16;
1191                         baud = rate / div;
1192                 } else {
1193                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1194                         baud = rate / (quot * 16);
1195                 }
1196                 quot--;
1197
1198                 calc_deviation = req_baud - baud;
1199                 if (calc_deviation < 0)
1200                         calc_deviation = -calc_deviation;
1201
1202                 if (calc_deviation < deviation) {
1203                         *best_clk = clk;
1204                         best_quot = quot;
1205                         *clk_num = cnt;
1206                         deviation = calc_deviation;
1207                 }
1208         }
1209
1210         return best_quot;
1211 }
1212
1213 /* udivslot_table[]
1214  *
1215  * This table takes the fractional value of the baud divisor and gives
1216  * the recommended setting for the UDIVSLOT register.
1217  */
1218 static u16 udivslot_table[16] = {
1219         [0] = 0x0000,
1220         [1] = 0x0080,
1221         [2] = 0x0808,
1222         [3] = 0x0888,
1223         [4] = 0x2222,
1224         [5] = 0x4924,
1225         [6] = 0x4A52,
1226         [7] = 0x54AA,
1227         [8] = 0x5555,
1228         [9] = 0xD555,
1229         [10] = 0xD5D5,
1230         [11] = 0xDDD5,
1231         [12] = 0xDDDD,
1232         [13] = 0xDFDD,
1233         [14] = 0xDFDF,
1234         [15] = 0xFFDF,
1235 };
1236
1237 static void s3c24xx_serial_set_termios(struct uart_port *port,
1238                                        struct ktermios *termios,
1239                                        struct ktermios *old)
1240 {
1241         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1242         struct s3c24xx_uart_port *ourport = to_ourport(port);
1243         struct clk *clk = ERR_PTR(-EINVAL);
1244         unsigned long flags;
1245         unsigned int baud, quot, clk_sel = 0;
1246         unsigned int ulcon;
1247         unsigned int umcon;
1248         unsigned int udivslot = 0;
1249
1250         /*
1251          * We don't support modem control lines.
1252          */
1253         termios->c_cflag &= ~(HUPCL | CMSPAR);
1254         termios->c_cflag |= CLOCAL;
1255
1256         /*
1257          * Ask the core to calculate the divisor for us.
1258          */
1259
1260         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1261         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1262         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1263                 quot = port->custom_divisor;
1264         if (IS_ERR(clk))
1265                 return;
1266
1267         /* check to see if we need  to change clock source */
1268
1269         if (ourport->baudclk != clk) {
1270                 clk_prepare_enable(clk);
1271
1272                 s3c24xx_serial_setsource(port, clk_sel);
1273
1274                 if (!IS_ERR(ourport->baudclk)) {
1275                         clk_disable_unprepare(ourport->baudclk);
1276                         ourport->baudclk = ERR_PTR(-EINVAL);
1277                 }
1278
1279                 ourport->baudclk = clk;
1280                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1281         }
1282
1283         if (ourport->info->has_divslot) {
1284                 unsigned int div = ourport->baudclk_rate / baud;
1285
1286                 if (cfg->has_fracval) {
1287                         udivslot = (div & 15);
1288                         dbg("fracval = %04x\n", udivslot);
1289                 } else {
1290                         udivslot = udivslot_table[div & 15];
1291                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1292                 }
1293         }
1294
1295         switch (termios->c_cflag & CSIZE) {
1296         case CS5:
1297                 dbg("config: 5bits/char\n");
1298                 ulcon = S3C2410_LCON_CS5;
1299                 break;
1300         case CS6:
1301                 dbg("config: 6bits/char\n");
1302                 ulcon = S3C2410_LCON_CS6;
1303                 break;
1304         case CS7:
1305                 dbg("config: 7bits/char\n");
1306                 ulcon = S3C2410_LCON_CS7;
1307                 break;
1308         case CS8:
1309         default:
1310                 dbg("config: 8bits/char\n");
1311                 ulcon = S3C2410_LCON_CS8;
1312                 break;
1313         }
1314
1315         /* preserve original lcon IR settings */
1316         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1317
1318         if (termios->c_cflag & CSTOPB)
1319                 ulcon |= S3C2410_LCON_STOPB;
1320
1321         if (termios->c_cflag & PARENB) {
1322                 if (termios->c_cflag & PARODD)
1323                         ulcon |= S3C2410_LCON_PODD;
1324                 else
1325                         ulcon |= S3C2410_LCON_PEVEN;
1326         } else {
1327                 ulcon |= S3C2410_LCON_PNONE;
1328         }
1329
1330         spin_lock_irqsave(&port->lock, flags);
1331
1332         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1333             ulcon, quot, udivslot);
1334
1335         wr_regl(port, S3C2410_ULCON, ulcon);
1336         wr_regl(port, S3C2410_UBRDIV, quot);
1337
1338         port->status &= ~UPSTAT_AUTOCTS;
1339
1340         umcon = rd_regl(port, S3C2410_UMCON);
1341         if (termios->c_cflag & CRTSCTS) {
1342                 umcon |= S3C2410_UMCOM_AFC;
1343                 /* Disable RTS when RX FIFO contains 63 bytes */
1344                 umcon &= ~S3C2412_UMCON_AFC_8;
1345                 port->status = UPSTAT_AUTOCTS;
1346         } else {
1347                 umcon &= ~S3C2410_UMCOM_AFC;
1348         }
1349         wr_regl(port, S3C2410_UMCON, umcon);
1350
1351         if (ourport->info->has_divslot)
1352                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1353
1354         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1355             rd_regl(port, S3C2410_ULCON),
1356             rd_regl(port, S3C2410_UCON),
1357             rd_regl(port, S3C2410_UFCON));
1358
1359         /*
1360          * Update the per-port timeout.
1361          */
1362         uart_update_timeout(port, termios->c_cflag, baud);
1363
1364         /*
1365          * Which character status flags are we interested in?
1366          */
1367         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1368         if (termios->c_iflag & INPCK)
1369                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1370                         S3C2410_UERSTAT_PARITY;
1371         /*
1372          * Which character status flags should we ignore?
1373          */
1374         port->ignore_status_mask = 0;
1375         if (termios->c_iflag & IGNPAR)
1376                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1377         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1378                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1379
1380         /*
1381          * Ignore all characters if CREAD is not set.
1382          */
1383         if ((termios->c_cflag & CREAD) == 0)
1384                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1385
1386         spin_unlock_irqrestore(&port->lock, flags);
1387 }
1388
1389 static const char *s3c24xx_serial_type(struct uart_port *port)
1390 {
1391         switch (port->type) {
1392         case PORT_S3C2410:
1393                 return "S3C2410";
1394         case PORT_S3C2440:
1395                 return "S3C2440";
1396         case PORT_S3C2412:
1397                 return "S3C2412";
1398         case PORT_S3C6400:
1399                 return "S3C6400/10";
1400         default:
1401                 return NULL;
1402         }
1403 }
1404
1405 #define MAP_SIZE (0x100)
1406
1407 static void s3c24xx_serial_release_port(struct uart_port *port)
1408 {
1409         release_mem_region(port->mapbase, MAP_SIZE);
1410 }
1411
1412 static int s3c24xx_serial_request_port(struct uart_port *port)
1413 {
1414         const char *name = s3c24xx_serial_portname(port);
1415         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1416 }
1417
1418 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1419 {
1420         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1421
1422         if (flags & UART_CONFIG_TYPE &&
1423             s3c24xx_serial_request_port(port) == 0)
1424                 port->type = info->type;
1425 }
1426
1427 /*
1428  * verify the new serial_struct (for TIOCSSERIAL).
1429  */
1430 static int
1431 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1432 {
1433         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1434
1435         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1436                 return -EINVAL;
1437
1438         return 0;
1439 }
1440
1441
1442 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1443
1444 static struct console s3c24xx_serial_console;
1445
1446 static int __init s3c24xx_serial_console_init(void)
1447 {
1448         register_console(&s3c24xx_serial_console);
1449         return 0;
1450 }
1451 console_initcall(s3c24xx_serial_console_init);
1452
1453 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1454 #else
1455 #define S3C24XX_SERIAL_CONSOLE NULL
1456 #endif
1457
1458 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1459 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1460 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1461                          unsigned char c);
1462 #endif
1463
1464 static struct uart_ops s3c24xx_serial_ops = {
1465         .pm             = s3c24xx_serial_pm,
1466         .tx_empty       = s3c24xx_serial_tx_empty,
1467         .get_mctrl      = s3c24xx_serial_get_mctrl,
1468         .set_mctrl      = s3c24xx_serial_set_mctrl,
1469         .stop_tx        = s3c24xx_serial_stop_tx,
1470         .start_tx       = s3c24xx_serial_start_tx,
1471         .stop_rx        = s3c24xx_serial_stop_rx,
1472         .break_ctl      = s3c24xx_serial_break_ctl,
1473         .startup        = s3c24xx_serial_startup,
1474         .shutdown       = s3c24xx_serial_shutdown,
1475         .set_termios    = s3c24xx_serial_set_termios,
1476         .type           = s3c24xx_serial_type,
1477         .release_port   = s3c24xx_serial_release_port,
1478         .request_port   = s3c24xx_serial_request_port,
1479         .config_port    = s3c24xx_serial_config_port,
1480         .verify_port    = s3c24xx_serial_verify_port,
1481 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1482         .poll_get_char = s3c24xx_serial_get_poll_char,
1483         .poll_put_char = s3c24xx_serial_put_poll_char,
1484 #endif
1485 };
1486
1487 static struct uart_driver s3c24xx_uart_drv = {
1488         .owner          = THIS_MODULE,
1489         .driver_name    = "s3c2410_serial",
1490         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1491         .cons           = S3C24XX_SERIAL_CONSOLE,
1492         .dev_name       = S3C24XX_SERIAL_NAME,
1493         .major          = S3C24XX_SERIAL_MAJOR,
1494         .minor          = S3C24XX_SERIAL_MINOR,
1495 };
1496
1497 #define __PORT_LOCK_UNLOCKED(i) \
1498         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1499 static struct s3c24xx_uart_port
1500 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1501         [0] = {
1502                 .port = {
1503                         .lock           = __PORT_LOCK_UNLOCKED(0),
1504                         .iotype         = UPIO_MEM,
1505                         .uartclk        = 0,
1506                         .fifosize       = 16,
1507                         .ops            = &s3c24xx_serial_ops,
1508                         .flags          = UPF_BOOT_AUTOCONF,
1509                         .line           = 0,
1510                 }
1511         },
1512         [1] = {
1513                 .port = {
1514                         .lock           = __PORT_LOCK_UNLOCKED(1),
1515                         .iotype         = UPIO_MEM,
1516                         .uartclk        = 0,
1517                         .fifosize       = 16,
1518                         .ops            = &s3c24xx_serial_ops,
1519                         .flags          = UPF_BOOT_AUTOCONF,
1520                         .line           = 1,
1521                 }
1522         },
1523 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1524
1525         [2] = {
1526                 .port = {
1527                         .lock           = __PORT_LOCK_UNLOCKED(2),
1528                         .iotype         = UPIO_MEM,
1529                         .uartclk        = 0,
1530                         .fifosize       = 16,
1531                         .ops            = &s3c24xx_serial_ops,
1532                         .flags          = UPF_BOOT_AUTOCONF,
1533                         .line           = 2,
1534                 }
1535         },
1536 #endif
1537 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1538         [3] = {
1539                 .port = {
1540                         .lock           = __PORT_LOCK_UNLOCKED(3),
1541                         .iotype         = UPIO_MEM,
1542                         .uartclk        = 0,
1543                         .fifosize       = 16,
1544                         .ops            = &s3c24xx_serial_ops,
1545                         .flags          = UPF_BOOT_AUTOCONF,
1546                         .line           = 3,
1547                 }
1548         }
1549 #endif
1550 };
1551 #undef __PORT_LOCK_UNLOCKED
1552
1553 /* s3c24xx_serial_resetport
1554  *
1555  * reset the fifos and other the settings.
1556 */
1557
1558 static void s3c24xx_serial_resetport(struct uart_port *port,
1559                                    struct s3c2410_uartcfg *cfg)
1560 {
1561         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1562         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1563         unsigned int ucon_mask;
1564
1565         ucon_mask = info->clksel_mask;
1566         if (info->type == PORT_S3C2440)
1567                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1568
1569         ucon &= ucon_mask;
1570         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1571
1572         /* reset both fifos */
1573         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1574         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1575
1576         /* some delay is required after fifo reset */
1577         udelay(1);
1578 }
1579
1580
1581 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1582
1583 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1584                                              unsigned long val, void *data)
1585 {
1586         struct s3c24xx_uart_port *port;
1587         struct uart_port *uport;
1588
1589         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1590         uport = &port->port;
1591
1592         /* check to see if port is enabled */
1593
1594         if (port->pm_level != 0)
1595                 return 0;
1596
1597         /* try and work out if the baudrate is changing, we can detect
1598          * a change in rate, but we do not have support for detecting
1599          * a disturbance in the clock-rate over the change.
1600          */
1601
1602         if (IS_ERR(port->baudclk))
1603                 goto exit;
1604
1605         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1606                 goto exit;
1607
1608         if (val == CPUFREQ_PRECHANGE) {
1609                 /* we should really shut the port down whilst the
1610                  * frequency change is in progress. */
1611
1612         } else if (val == CPUFREQ_POSTCHANGE) {
1613                 struct ktermios *termios;
1614                 struct tty_struct *tty;
1615
1616                 if (uport->state == NULL)
1617                         goto exit;
1618
1619                 tty = uport->state->port.tty;
1620
1621                 if (tty == NULL)
1622                         goto exit;
1623
1624                 termios = &tty->termios;
1625
1626                 if (termios == NULL) {
1627                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1628                         goto exit;
1629                 }
1630
1631                 s3c24xx_serial_set_termios(uport, termios, NULL);
1632         }
1633
1634 exit:
1635         return 0;
1636 }
1637
1638 static inline int
1639 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1640 {
1641         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1642
1643         return cpufreq_register_notifier(&port->freq_transition,
1644                                          CPUFREQ_TRANSITION_NOTIFIER);
1645 }
1646
1647 static inline void
1648 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1649 {
1650         cpufreq_unregister_notifier(&port->freq_transition,
1651                                     CPUFREQ_TRANSITION_NOTIFIER);
1652 }
1653
1654 #else
1655 static inline int
1656 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1657 {
1658         return 0;
1659 }
1660
1661 static inline void
1662 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1663 {
1664 }
1665 #endif
1666
1667 /* s3c24xx_serial_init_port
1668  *
1669  * initialise a single serial port from the platform device given
1670  */
1671
1672 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1673                                     struct platform_device *platdev)
1674 {
1675         struct uart_port *port = &ourport->port;
1676         struct s3c2410_uartcfg *cfg = ourport->cfg;
1677         struct resource *res;
1678         int ret;
1679
1680         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1681
1682         if (platdev == NULL)
1683                 return -ENODEV;
1684
1685         if (port->mapbase != 0)
1686                 return -EINVAL;
1687
1688         /* setup info for port */
1689         port->dev       = &platdev->dev;
1690
1691         /* Startup sequence is different for s3c64xx and higher SoC's */
1692         if (s3c24xx_serial_has_interrupt_mask(port))
1693                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1694
1695         port->uartclk = 1;
1696
1697         if (cfg->uart_flags & UPF_CONS_FLOW) {
1698                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1699                 port->flags |= UPF_CONS_FLOW;
1700         }
1701
1702         /* sort our the physical and virtual addresses for each UART */
1703
1704         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1705         if (res == NULL) {
1706                 dev_err(port->dev, "failed to find memory resource for uart\n");
1707                 return -EINVAL;
1708         }
1709
1710         dbg("resource %pR)\n", res);
1711
1712         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1713         if (!port->membase) {
1714                 dev_err(port->dev, "failed to remap controller address\n");
1715                 return -EBUSY;
1716         }
1717
1718         port->mapbase = res->start;
1719         ret = platform_get_irq(platdev, 0);
1720         if (ret < 0)
1721                 port->irq = 0;
1722         else {
1723                 port->irq = ret;
1724                 ourport->rx_irq = ret;
1725                 ourport->tx_irq = ret + 1;
1726         }
1727
1728         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1729                 ret = platform_get_irq(platdev, 1);
1730                 if (ret > 0)
1731                         ourport->tx_irq = ret;
1732         }
1733         /*
1734          * DMA is currently supported only on DT platforms, if DMA properties
1735          * are specified.
1736          */
1737         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1738                                                      "dmas", NULL)) {
1739                 ourport->dma = devm_kzalloc(port->dev,
1740                                             sizeof(*ourport->dma),
1741                                             GFP_KERNEL);
1742                 if (!ourport->dma) {
1743                         ret = -ENOMEM;
1744                         goto err;
1745                 }
1746         }
1747
1748         ourport->clk    = clk_get(&platdev->dev, "uart");
1749         if (IS_ERR(ourport->clk)) {
1750                 pr_err("%s: Controller clock not found\n",
1751                                 dev_name(&platdev->dev));
1752                 ret = PTR_ERR(ourport->clk);
1753                 goto err;
1754         }
1755
1756         ret = clk_prepare_enable(ourport->clk);
1757         if (ret) {
1758                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1759                 clk_put(ourport->clk);
1760                 goto err;
1761         }
1762
1763         /* Keep all interrupts masked and cleared */
1764         if (s3c24xx_serial_has_interrupt_mask(port)) {
1765                 wr_regl(port, S3C64XX_UINTM, 0xf);
1766                 wr_regl(port, S3C64XX_UINTP, 0xf);
1767                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1768         }
1769
1770         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1771             &port->mapbase, port->membase, port->irq,
1772             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1773
1774         /* reset the fifos (and setup the uart) */
1775         s3c24xx_serial_resetport(port, cfg);
1776
1777         return 0;
1778
1779 err:
1780         port->mapbase = 0;
1781         return ret;
1782 }
1783
1784 /* Device driver serial port probe */
1785
1786 static const struct of_device_id s3c24xx_uart_dt_match[];
1787 static int probe_index;
1788
1789 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1790                         struct platform_device *pdev)
1791 {
1792 #ifdef CONFIG_OF
1793         if (pdev->dev.of_node) {
1794                 const struct of_device_id *match;
1795                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1796                 return (struct s3c24xx_serial_drv_data *)match->data;
1797         }
1798 #endif
1799         return (struct s3c24xx_serial_drv_data *)
1800                         platform_get_device_id(pdev)->driver_data;
1801 }
1802
1803 static int s3c24xx_serial_probe(struct platform_device *pdev)
1804 {
1805         struct device_node *np = pdev->dev.of_node;
1806         struct s3c24xx_uart_port *ourport;
1807         int index = probe_index;
1808         int ret;
1809
1810         if (np) {
1811                 ret = of_alias_get_id(np, "serial");
1812                 if (ret >= 0)
1813                         index = ret;
1814         }
1815
1816         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1817
1818         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1819                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1820                 return -EINVAL;
1821         }
1822         ourport = &s3c24xx_serial_ports[index];
1823
1824         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1825         if (!ourport->drv_data) {
1826                 dev_err(&pdev->dev, "could not find driver data\n");
1827                 return -ENODEV;
1828         }
1829
1830         ourport->baudclk = ERR_PTR(-EINVAL);
1831         ourport->info = ourport->drv_data->info;
1832         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1833                         dev_get_platdata(&pdev->dev) :
1834                         ourport->drv_data->def_cfg;
1835
1836         if (np)
1837                 of_property_read_u32(np,
1838                         "samsung,uart-fifosize", &ourport->port.fifosize);
1839
1840         if (ourport->drv_data->fifosize[index])
1841                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1842         else if (ourport->info->fifosize)
1843                 ourport->port.fifosize = ourport->info->fifosize;
1844
1845         /*
1846          * DMA transfers must be aligned at least to cache line size,
1847          * so find minimal transfer size suitable for DMA mode
1848          */
1849         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1850                                     dma_get_cache_alignment());
1851
1852         dbg("%s: initialising port %p...\n", __func__, ourport);
1853
1854         ret = s3c24xx_serial_init_port(ourport, pdev);
1855         if (ret < 0)
1856                 return ret;
1857
1858         if (!s3c24xx_uart_drv.state) {
1859                 ret = uart_register_driver(&s3c24xx_uart_drv);
1860                 if (ret < 0) {
1861                         pr_err("Failed to register Samsung UART driver\n");
1862                         return ret;
1863                 }
1864         }
1865
1866         dbg("%s: adding port\n", __func__);
1867         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1868         platform_set_drvdata(pdev, &ourport->port);
1869
1870         /*
1871          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1872          * so that a potential re-enablement through the pm-callback overlaps
1873          * and keeps the clock enabled in this case.
1874          */
1875         clk_disable_unprepare(ourport->clk);
1876
1877         ret = s3c24xx_serial_cpufreq_register(ourport);
1878         if (ret < 0)
1879                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1880
1881         probe_index++;
1882
1883         return 0;
1884 }
1885
1886 static int s3c24xx_serial_remove(struct platform_device *dev)
1887 {
1888         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1889
1890         if (port) {
1891                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1892                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1893         }
1894
1895         uart_unregister_driver(&s3c24xx_uart_drv);
1896
1897         return 0;
1898 }
1899
1900 /* UART power management code */
1901 #ifdef CONFIG_PM_SLEEP
1902 static int s3c24xx_serial_suspend(struct device *dev)
1903 {
1904         struct uart_port *port = s3c24xx_dev_to_port(dev);
1905
1906         if (port)
1907                 uart_suspend_port(&s3c24xx_uart_drv, port);
1908
1909         return 0;
1910 }
1911
1912 static int s3c24xx_serial_resume(struct device *dev)
1913 {
1914         struct uart_port *port = s3c24xx_dev_to_port(dev);
1915         struct s3c24xx_uart_port *ourport = to_ourport(port);
1916
1917         if (port) {
1918                 clk_prepare_enable(ourport->clk);
1919                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1920                 clk_disable_unprepare(ourport->clk);
1921
1922                 uart_resume_port(&s3c24xx_uart_drv, port);
1923         }
1924
1925         return 0;
1926 }
1927
1928 static int s3c24xx_serial_resume_noirq(struct device *dev)
1929 {
1930         struct uart_port *port = s3c24xx_dev_to_port(dev);
1931
1932         if (port) {
1933                 /* restore IRQ mask */
1934                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1935                         unsigned int uintm = 0xf;
1936                         if (tx_enabled(port))
1937                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1938                         if (rx_enabled(port))
1939                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1940                         wr_regl(port, S3C64XX_UINTM, uintm);
1941                 }
1942         }
1943
1944         return 0;
1945 }
1946
1947 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1948         .suspend = s3c24xx_serial_suspend,
1949         .resume = s3c24xx_serial_resume,
1950         .resume_noirq = s3c24xx_serial_resume_noirq,
1951 };
1952 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1953
1954 #else /* !CONFIG_PM_SLEEP */
1955
1956 #define SERIAL_SAMSUNG_PM_OPS   NULL
1957 #endif /* CONFIG_PM_SLEEP */
1958
1959 /* Console code */
1960
1961 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1962
1963 static struct uart_port *cons_uart;
1964
1965 static int
1966 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1967 {
1968         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1969         unsigned long ufstat, utrstat;
1970
1971         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1972                 /* fifo mode - check amount of data in fifo registers... */
1973
1974                 ufstat = rd_regl(port, S3C2410_UFSTAT);
1975                 return (ufstat & info->tx_fifofull) ? 0 : 1;
1976         }
1977
1978         /* in non-fifo mode, we go and use the tx buffer empty */
1979
1980         utrstat = rd_regl(port, S3C2410_UTRSTAT);
1981         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1982 }
1983
1984 static bool
1985 s3c24xx_port_configured(unsigned int ucon)
1986 {
1987         /* consider the serial port configured if the tx/rx mode set */
1988         return (ucon & 0xf) != 0;
1989 }
1990
1991 #ifdef CONFIG_CONSOLE_POLL
1992 /*
1993  * Console polling routines for writing and reading from the uart while
1994  * in an interrupt or debug context.
1995  */
1996
1997 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1998 {
1999         struct s3c24xx_uart_port *ourport = to_ourport(port);
2000         unsigned int ufstat;
2001
2002         ufstat = rd_regl(port, S3C2410_UFSTAT);
2003         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2004                 return NO_POLL_CHAR;
2005
2006         return rd_regb(port, S3C2410_URXH);
2007 }
2008
2009 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2010                 unsigned char c)
2011 {
2012         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2013         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2014
2015         /* not possible to xmit on unconfigured port */
2016         if (!s3c24xx_port_configured(ucon))
2017                 return;
2018
2019         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2020                 cpu_relax();
2021         wr_regb(port, S3C2410_UTXH, c);
2022 }
2023
2024 #endif /* CONFIG_CONSOLE_POLL */
2025
2026 static void
2027 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2028 {
2029         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2030
2031         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2032                 cpu_relax();
2033         wr_regb(port, S3C2410_UTXH, ch);
2034 }
2035
2036 static void
2037 s3c24xx_serial_console_write(struct console *co, const char *s,
2038                              unsigned int count)
2039 {
2040         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2041
2042         /* not possible to xmit on unconfigured port */
2043         if (!s3c24xx_port_configured(ucon))
2044                 return;
2045
2046         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2047 }
2048
2049 static void __init
2050 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2051                            int *parity, int *bits)
2052 {
2053         struct clk *clk;
2054         unsigned int ulcon;
2055         unsigned int ucon;
2056         unsigned int ubrdiv;
2057         unsigned long rate;
2058         unsigned int clk_sel;
2059         char clk_name[MAX_CLK_NAME_LENGTH];
2060
2061         ulcon  = rd_regl(port, S3C2410_ULCON);
2062         ucon   = rd_regl(port, S3C2410_UCON);
2063         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2064
2065         dbg("s3c24xx_serial_get_options: port=%p\n"
2066             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2067             port, ulcon, ucon, ubrdiv);
2068
2069         if (s3c24xx_port_configured(ucon)) {
2070                 switch (ulcon & S3C2410_LCON_CSMASK) {
2071                 case S3C2410_LCON_CS5:
2072                         *bits = 5;
2073                         break;
2074                 case S3C2410_LCON_CS6:
2075                         *bits = 6;
2076                         break;
2077                 case S3C2410_LCON_CS7:
2078                         *bits = 7;
2079                         break;
2080                 case S3C2410_LCON_CS8:
2081                 default:
2082                         *bits = 8;
2083                         break;
2084                 }
2085
2086                 switch (ulcon & S3C2410_LCON_PMASK) {
2087                 case S3C2410_LCON_PEVEN:
2088                         *parity = 'e';
2089                         break;
2090
2091                 case S3C2410_LCON_PODD:
2092                         *parity = 'o';
2093                         break;
2094
2095                 case S3C2410_LCON_PNONE:
2096                 default:
2097                         *parity = 'n';
2098                 }
2099
2100                 /* now calculate the baud rate */
2101
2102                 clk_sel = s3c24xx_serial_getsource(port);
2103                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2104
2105                 clk = clk_get(port->dev, clk_name);
2106                 if (!IS_ERR(clk))
2107                         rate = clk_get_rate(clk);
2108                 else
2109                         rate = 1;
2110
2111                 *baud = rate / (16 * (ubrdiv + 1));
2112                 dbg("calculated baud %d\n", *baud);
2113         }
2114
2115 }
2116
2117 static int __init
2118 s3c24xx_serial_console_setup(struct console *co, char *options)
2119 {
2120         struct uart_port *port;
2121         int baud = 9600;
2122         int bits = 8;
2123         int parity = 'n';
2124         int flow = 'n';
2125
2126         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2127             co, co->index, options);
2128
2129         /* is this a valid port */
2130
2131         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2132                 co->index = 0;
2133
2134         port = &s3c24xx_serial_ports[co->index].port;
2135
2136         /* is the port configured? */
2137
2138         if (port->mapbase == 0x0)
2139                 return -ENODEV;
2140
2141         cons_uart = port;
2142
2143         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2144
2145         /*
2146          * Check whether an invalid uart number has been specified, and
2147          * if so, search for the first available port that does have
2148          * console support.
2149          */
2150         if (options)
2151                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2152         else
2153                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2154
2155         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2156
2157         return uart_set_options(port, co, baud, parity, bits, flow);
2158 }
2159
2160 static struct console s3c24xx_serial_console = {
2161         .name           = S3C24XX_SERIAL_NAME,
2162         .device         = uart_console_device,
2163         .flags          = CON_PRINTBUFFER,
2164         .index          = -1,
2165         .write          = s3c24xx_serial_console_write,
2166         .setup          = s3c24xx_serial_console_setup,
2167         .data           = &s3c24xx_uart_drv,
2168 };
2169 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2170
2171 #ifdef CONFIG_CPU_S3C2410
2172 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2173         .info = &(struct s3c24xx_uart_info) {
2174                 .name           = "Samsung S3C2410 UART",
2175                 .type           = PORT_S3C2410,
2176                 .fifosize       = 16,
2177                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2178                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2179                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2180                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2181                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2182                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2183                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2184                 .num_clks       = 2,
2185                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2186                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2187         },
2188         .def_cfg = &(struct s3c2410_uartcfg) {
2189                 .ucon           = S3C2410_UCON_DEFAULT,
2190                 .ufcon          = S3C2410_UFCON_DEFAULT,
2191         },
2192 };
2193 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2194 #else
2195 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2196 #endif
2197
2198 #ifdef CONFIG_CPU_S3C2412
2199 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2200         .info = &(struct s3c24xx_uart_info) {
2201                 .name           = "Samsung S3C2412 UART",
2202                 .type           = PORT_S3C2412,
2203                 .fifosize       = 64,
2204                 .has_divslot    = 1,
2205                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2206                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2207                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2208                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2209                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2210                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2211                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2212                 .num_clks       = 4,
2213                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2214                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2215         },
2216         .def_cfg = &(struct s3c2410_uartcfg) {
2217                 .ucon           = S3C2410_UCON_DEFAULT,
2218                 .ufcon          = S3C2410_UFCON_DEFAULT,
2219         },
2220 };
2221 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2222 #else
2223 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2224 #endif
2225
2226 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2227         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2228 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2229         .info = &(struct s3c24xx_uart_info) {
2230                 .name           = "Samsung S3C2440 UART",
2231                 .type           = PORT_S3C2440,
2232                 .fifosize       = 64,
2233                 .has_divslot    = 1,
2234                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2235                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2236                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2237                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2238                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2239                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2240                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2241                 .num_clks       = 4,
2242                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2243                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2244         },
2245         .def_cfg = &(struct s3c2410_uartcfg) {
2246                 .ucon           = S3C2410_UCON_DEFAULT,
2247                 .ufcon          = S3C2410_UFCON_DEFAULT,
2248         },
2249 };
2250 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2251 #else
2252 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2253 #endif
2254
2255 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2256 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2257         .info = &(struct s3c24xx_uart_info) {
2258                 .name           = "Samsung S3C6400 UART",
2259                 .type           = PORT_S3C6400,
2260                 .fifosize       = 64,
2261                 .has_divslot    = 1,
2262                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2263                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2264                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2265                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2266                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2267                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2268                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2269                 .num_clks       = 4,
2270                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2271                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2272         },
2273         .def_cfg = &(struct s3c2410_uartcfg) {
2274                 .ucon           = S3C2410_UCON_DEFAULT,
2275                 .ufcon          = S3C2410_UFCON_DEFAULT,
2276         },
2277 };
2278 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2279 #else
2280 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2281 #endif
2282
2283 #ifdef CONFIG_CPU_S5PV210
2284 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2285         .info = &(struct s3c24xx_uart_info) {
2286                 .name           = "Samsung S5PV210 UART",
2287                 .type           = PORT_S3C6400,
2288                 .has_divslot    = 1,
2289                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2290                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2291                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2292                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2293                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2294                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2295                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2296                 .num_clks       = 2,
2297                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2298                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2299         },
2300         .def_cfg = &(struct s3c2410_uartcfg) {
2301                 .ucon           = S5PV210_UCON_DEFAULT,
2302                 .ufcon          = S5PV210_UFCON_DEFAULT,
2303         },
2304         .fifosize = { 256, 64, 16, 16 },
2305 };
2306 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2307 #else
2308 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2309 #endif
2310
2311 #if defined(CONFIG_ARCH_EXYNOS)
2312 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2313         .info = &(struct s3c24xx_uart_info) {                   \
2314                 .name           = "Samsung Exynos UART",        \
2315                 .type           = PORT_S3C6400,                 \
2316                 .has_divslot    = 1,                            \
2317                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2318                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2319                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2320                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2321                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2322                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2323                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2324                 .num_clks       = 1,                            \
2325                 .clksel_mask    = 0,                            \
2326                 .clksel_shift   = 0,                            \
2327         },                                                      \
2328         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2329                 .ucon           = S5PV210_UCON_DEFAULT,         \
2330                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2331                 .has_fracval    = 1,                            \
2332         }                                                       \
2333
2334 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2335         EXYNOS_COMMON_SERIAL_DRV_DATA,
2336         .fifosize = { 256, 64, 16, 16 },
2337 };
2338
2339 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2340         EXYNOS_COMMON_SERIAL_DRV_DATA,
2341         .fifosize = { 64, 256, 16, 256 },
2342 };
2343
2344 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2345 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2346 #else
2347 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2348 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2349 #endif
2350
2351 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2352         {
2353                 .name           = "s3c2410-uart",
2354                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2355         }, {
2356                 .name           = "s3c2412-uart",
2357                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2358         }, {
2359                 .name           = "s3c2440-uart",
2360                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2361         }, {
2362                 .name           = "s3c6400-uart",
2363                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2364         }, {
2365                 .name           = "s5pv210-uart",
2366                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2367         }, {
2368                 .name           = "exynos4210-uart",
2369                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2370         }, {
2371                 .name           = "exynos5433-uart",
2372                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2373         },
2374         { },
2375 };
2376 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2377
2378 #ifdef CONFIG_OF
2379 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2380         { .compatible = "samsung,s3c2410-uart",
2381                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2382         { .compatible = "samsung,s3c2412-uart",
2383                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2384         { .compatible = "samsung,s3c2440-uart",
2385                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2386         { .compatible = "samsung,s3c6400-uart",
2387                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2388         { .compatible = "samsung,s5pv210-uart",
2389                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2390         { .compatible = "samsung,exynos4210-uart",
2391                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2392         { .compatible = "samsung,exynos5433-uart",
2393                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2394         {},
2395 };
2396 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2397 #endif
2398
2399 static struct platform_driver samsung_serial_driver = {
2400         .probe          = s3c24xx_serial_probe,
2401         .remove         = s3c24xx_serial_remove,
2402         .id_table       = s3c24xx_serial_driver_ids,
2403         .driver         = {
2404                 .name   = "samsung-uart",
2405                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2406                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2407         },
2408 };
2409
2410 module_platform_driver(samsung_serial_driver);
2411
2412 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2413 /*
2414  * Early console.
2415  */
2416
2417 struct samsung_early_console_data {
2418         u32 txfull_mask;
2419 };
2420
2421 static void samsung_early_busyuart(struct uart_port *port)
2422 {
2423         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2424                 ;
2425 }
2426
2427 static void samsung_early_busyuart_fifo(struct uart_port *port)
2428 {
2429         struct samsung_early_console_data *data = port->private_data;
2430
2431         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2432                 ;
2433 }
2434
2435 static void samsung_early_putc(struct uart_port *port, int c)
2436 {
2437         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2438                 samsung_early_busyuart_fifo(port);
2439         else
2440                 samsung_early_busyuart(port);
2441
2442         writeb(c, port->membase + S3C2410_UTXH);
2443 }
2444
2445 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2446 {
2447         struct earlycon_device *dev = con->data;
2448
2449         uart_console_write(&dev->port, s, n, samsung_early_putc);
2450 }
2451
2452 static int __init samsung_early_console_setup(struct earlycon_device *device,
2453                                               const char *opt)
2454 {
2455         if (!device->port.membase)
2456                 return -ENODEV;
2457
2458         device->con->write = samsung_early_write;
2459         return 0;
2460 }
2461
2462 /* S3C2410 */
2463 static struct samsung_early_console_data s3c2410_early_console_data = {
2464         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2465 };
2466
2467 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2468                                               const char *opt)
2469 {
2470         device->port.private_data = &s3c2410_early_console_data;
2471         return samsung_early_console_setup(device, opt);
2472 }
2473 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2474                         s3c2410_early_console_setup);
2475
2476 /* S3C2412, S3C2440, S3C64xx */
2477 static struct samsung_early_console_data s3c2440_early_console_data = {
2478         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2479 };
2480
2481 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2482                                               const char *opt)
2483 {
2484         device->port.private_data = &s3c2440_early_console_data;
2485         return samsung_early_console_setup(device, opt);
2486 }
2487 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2488                         s3c2440_early_console_setup);
2489 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2490                         s3c2440_early_console_setup);
2491 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2492                         s3c2440_early_console_setup);
2493
2494 /* S5PV210, EXYNOS */
2495 static struct samsung_early_console_data s5pv210_early_console_data = {
2496         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2497 };
2498
2499 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2500                                               const char *opt)
2501 {
2502         device->port.private_data = &s5pv210_early_console_data;
2503         return samsung_early_console_setup(device, opt);
2504 }
2505 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2506                         s5pv210_early_console_setup);
2507 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2508                         s5pv210_early_console_setup);
2509 #endif
2510
2511 MODULE_ALIAS("platform:samsung-uart");
2512 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2513 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2514 MODULE_LICENSE("GPL v2");