drivers/tty/serial/samsung.c

   1 /*
   2  * Driver core for Samsung SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /* Hote on 2410 error handling
  13  *
  14  * The s3c2410 manual has a love/hate affair with the contents of the
  15  * UERSTAT register in the UART blocks, and keeps marking some of the
  16  * error bits as reserved. Having checked with the s3c2410x01,
  17  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  18  * feature from the latter versions of the manual.
  19  *
  20  * If it becomes aparrent that latter versions of the 2410 remove these
  21  * bits, then action will have to be taken to differentiate the versions
  22  * and change the policy on BREAK
  23  *
  24  * BJD, 04-Nov-2004
  25 */
  26
  27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28 #define SUPPORT_SYSRQ
  29 #endif
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/ioport.h>
  36 #include <linux/io.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/init.h>
  39 #include <linux/sysrq.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42 #include <linux/tty_flip.h>
  43 #include <linux/serial_core.h>
  44 #include <linux/serial.h>
  45 #include <linux/serial_s3c.h>
  46 #include <linux/delay.h>
  47 #include <linux/clk.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/of.h>
  50
  51 #include <asm/irq.h>
  52
  53 #include "samsung.h"
  54
  55 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  56         !defined(MODULE)
  57
  58 extern void printascii(const char *);
  59
  60 __printf(1, 2)
  61 static void dbg(const char *fmt, ...)
  62 {
  63         va_list va;
  64         char buff[256];
  65
  66         va_start(va, fmt);
  67         vscnprintf(buff, sizeof(buff), fmt, va);
  68         va_end(va);
  69
  70         printascii(buff);
  71 }
  72
  73 #else
  74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  75 #endif
  76
  77 /* UART name and device definitions */
  78
  79 #define S3C24XX_SERIAL_NAME     "ttySAC"
  80 #define S3C24XX_SERIAL_MAJOR    204
  81 #define S3C24XX_SERIAL_MINOR    64
  82
  83 #define S3C24XX_TX_PIO                  1
  84 #define S3C24XX_TX_DMA                  2
  85 #define S3C24XX_RX_PIO                  1
  86 #define S3C24XX_RX_DMA                  2
  87 /* macros to change one thing to another */
  88
  89 #define tx_enabled(port) ((port)->unused[0])
  90 #define rx_enabled(port) ((port)->unused[1])
  91
  92 /* flag to ignore all characters coming in */
  93 #define RXSTAT_DUMMY_READ (0x10000000)
  94
  95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  96 {
  97         return container_of(port, struct s3c24xx_uart_port, port);
  98 }
  99
 100 /* translate a port to the device name */
 101
 102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 103 {
 104         return to_platform_device(port->dev)->name;
 105 }
 106
 107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 108 {
 109         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 110 }
 111
 112 /*
 113  * s3c64xx and later SoC's include the interrupt mask and status registers in
 114  * the controller itself, unlike the s3c24xx SoC's which have these registers
 115  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 116  */
 117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 118 {
 119         return to_ourport(port)->info->type == PORT_S3C6400;
 120 }
 121
 122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 123 {
 124         unsigned long flags;
 125         unsigned int ucon, ufcon;
 126         int count = 10000;
 127
 128         spin_lock_irqsave(&port->lock, flags);
 129
 130         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 131                 udelay(100);
 132
 133         ufcon = rd_regl(port, S3C2410_UFCON);
 134         ufcon |= S3C2410_UFCON_RESETRX;
 135         wr_regl(port, S3C2410_UFCON, ufcon);
 136
 137         ucon = rd_regl(port, S3C2410_UCON);
 138         ucon |= S3C2410_UCON_RXIRQMODE;
 139         wr_regl(port, S3C2410_UCON, ucon);
 140
 141         rx_enabled(port) = 1;
 142         spin_unlock_irqrestore(&port->lock, flags);
 143 }
 144
 145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 146 {
 147         unsigned long flags;
 148         unsigned int ucon;
 149
 150         spin_lock_irqsave(&port->lock, flags);
 151
 152         ucon = rd_regl(port, S3C2410_UCON);
 153         ucon &= ~S3C2410_UCON_RXIRQMODE;
 154         wr_regl(port, S3C2410_UCON, ucon);
 155
 156         rx_enabled(port) = 0;
 157         spin_unlock_irqrestore(&port->lock, flags);
 158 }
 159
 160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 161 {
 162         struct s3c24xx_uart_port *ourport = to_ourport(port);
 163         struct s3c24xx_uart_dma *dma = ourport->dma;
 164         struct circ_buf *xmit = &port->state->xmit;
 165         struct dma_tx_state state;
 166         int count;
 167
 168         if (!tx_enabled(port))
 169                 return;
 170
 171         if (s3c24xx_serial_has_interrupt_mask(port))
 172                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 173         else
 174                 disable_irq_nosync(ourport->tx_irq);
 175
 176         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 177                 dmaengine_pause(dma->tx_chan);
 178                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 179                 dmaengine_terminate_all(dma->tx_chan);
 180                 dma_sync_single_for_cpu(ourport->port.dev,
 181                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 182                 async_tx_ack(dma->tx_desc);
 183                 count = dma->tx_bytes_requested - state.residue;
 184                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 185                 port->icount.tx += count;
 186         }
 187
 188         tx_enabled(port) = 0;
 189         ourport->tx_in_progress = 0;
 190
 191         if (port->flags & UPF_CONS_FLOW)
 192                 s3c24xx_serial_rx_enable(port);
 193
 194         ourport->tx_mode = 0;
 195 }
 196
 197 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 198
 199 static void s3c24xx_serial_tx_dma_complete(void *args)
 200 {
 201         struct s3c24xx_uart_port *ourport = args;
 202         struct uart_port *port = &ourport->port;
 203         struct circ_buf *xmit = &port->state->xmit;
 204         struct s3c24xx_uart_dma *dma = ourport->dma;
 205         struct dma_tx_state state;
 206         unsigned long flags;
 207         int count;
 208
 209
 210         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 211         count = dma->tx_bytes_requested - state.residue;
 212         async_tx_ack(dma->tx_desc);
 213
 214         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 215                                 dma->tx_size, DMA_TO_DEVICE);
 216
 217         spin_lock_irqsave(&port->lock, flags);
 218
 219         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 220         port->icount.tx += count;
 221         ourport->tx_in_progress = 0;
 222
 223         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 224                 uart_write_wakeup(port);
 225
 226         s3c24xx_serial_start_next_tx(ourport);
 227         spin_unlock_irqrestore(&port->lock, flags);
 228 }
 229
 230 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 231 {
 232         struct uart_port *port = &ourport->port;
 233         u32 ucon;
 234
 235         /* Mask Tx interrupt */
 236         if (s3c24xx_serial_has_interrupt_mask(port))
 237                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 238         else
 239                 disable_irq_nosync(ourport->tx_irq);
 240
 241         /* Enable tx dma mode */
 242         ucon = rd_regl(port, S3C2410_UCON);
 243         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 244         ucon |= S3C64XX_UCON_TXBURST_1;
 245         ucon |= S3C64XX_UCON_TXMODE_DMA;
 246         wr_regl(port,  S3C2410_UCON, ucon);
 247
 248         ourport->tx_mode = S3C24XX_TX_DMA;
 249 }
 250
 251 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 252 {
 253         struct uart_port *port = &ourport->port;
 254         u32 ucon, ufcon;
 255
 256         /* Set ufcon txtrig */
 257         ourport->tx_in_progress = S3C24XX_TX_PIO;
 258         ufcon = rd_regl(port, S3C2410_UFCON);
 259         wr_regl(port,  S3C2410_UFCON, ufcon);
 260
 261         /* Enable tx pio mode */
 262         ucon = rd_regl(port, S3C2410_UCON);
 263         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 264         ucon |= S3C64XX_UCON_TXMODE_CPU;
 265         wr_regl(port,  S3C2410_UCON, ucon);
 266
 267         /* Unmask Tx interrupt */
 268         if (s3c24xx_serial_has_interrupt_mask(port))
 269                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 270                                   S3C64XX_UINTM);
 271         else
 272                 enable_irq(ourport->tx_irq);
 273
 274         ourport->tx_mode = S3C24XX_TX_PIO;
 275 }
 276
 277 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 278 {
 279         if (ourport->tx_mode != S3C24XX_TX_PIO)
 280                 enable_tx_pio(ourport);
 281 }
 282
 283 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 284                                       unsigned int count)
 285 {
 286         struct uart_port *port = &ourport->port;
 287         struct circ_buf *xmit = &port->state->xmit;
 288         struct s3c24xx_uart_dma *dma = ourport->dma;
 289
 290
 291         if (ourport->tx_mode != S3C24XX_TX_DMA)
 292                 enable_tx_dma(ourport);
 293
 294         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 295         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 296
 297         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 298                                 dma->tx_size, DMA_TO_DEVICE);
 299
 300         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 301                                 dma->tx_transfer_addr, dma->tx_size,
 302                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 303         if (!dma->tx_desc) {
 304                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 305                 return -EIO;
 306         }
 307
 308         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 309         dma->tx_desc->callback_param = ourport;
 310         dma->tx_bytes_requested = dma->tx_size;
 311
 312         ourport->tx_in_progress = S3C24XX_TX_DMA;
 313         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 314         dma_async_issue_pending(dma->tx_chan);
 315         return 0;
 316 }
 317
 318 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 319 {
 320         struct uart_port *port = &ourport->port;
 321         struct circ_buf *xmit = &port->state->xmit;
 322         unsigned long count;
 323
 324         /* Get data size up to the end of buffer */
 325         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 326
 327         if (!count) {
 328                 s3c24xx_serial_stop_tx(port);
 329                 return;
 330         }
 331
 332         if (!ourport->dma || !ourport->dma->tx_chan ||
 333             count < ourport->min_dma_size ||
 334             xmit->tail & (dma_get_cache_alignment() - 1))
 335                 s3c24xx_serial_start_tx_pio(ourport);
 336         else
 337                 s3c24xx_serial_start_tx_dma(ourport, count);
 338 }
 339
 340 static void s3c24xx_serial_start_tx(struct uart_port *port)
 341 {
 342         struct s3c24xx_uart_port *ourport = to_ourport(port);
 343         struct circ_buf *xmit = &port->state->xmit;
 344
 345         if (!tx_enabled(port)) {
 346                 if (port->flags & UPF_CONS_FLOW)
 347                         s3c24xx_serial_rx_disable(port);
 348
 349                 tx_enabled(port) = 1;
 350                 if (!ourport->dma || !ourport->dma->tx_chan)
 351                         s3c24xx_serial_start_tx_pio(ourport);
 352         }
 353
 354         if (ourport->dma && ourport->dma->tx_chan) {
 355                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 356                         s3c24xx_serial_start_next_tx(ourport);
 357         }
 358 }
 359
 360 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 361                 struct tty_port *tty, int count)
 362 {
 363         struct s3c24xx_uart_dma *dma = ourport->dma;
 364         int copied;
 365
 366         if (!count)
 367                 return;
 368
 369         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 370                                 dma->rx_size, DMA_FROM_DEVICE);
 371
 372         ourport->port.icount.rx += count;
 373         if (!tty) {
 374                 dev_err(ourport->port.dev, "No tty port\n");
 375                 return;
 376         }
 377         copied = tty_insert_flip_string(tty,
 378                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 379         if (copied != count) {
 380                 WARN_ON(1);
 381                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 382         }
 383 }
 384
 385 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 386 {
 387         struct s3c24xx_uart_port *ourport = to_ourport(port);
 388         struct s3c24xx_uart_dma *dma = ourport->dma;
 389         struct tty_port *t = &port->state->port;
 390         struct dma_tx_state state;
 391         enum dma_status dma_status;
 392         unsigned int received;
 393
 394         if (rx_enabled(port)) {
 395                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 396                 if (s3c24xx_serial_has_interrupt_mask(port))
 397                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 398                                         S3C64XX_UINTM);
 399                 else
 400                         disable_irq_nosync(ourport->rx_irq);
 401                 rx_enabled(port) = 0;
 402         }
 403         if (dma && dma->rx_chan) {
 404                 dmaengine_pause(dma->tx_chan);
 405                 dma_status = dmaengine_tx_status(dma->rx_chan,
 406                                 dma->rx_cookie, &state);
 407                 if (dma_status == DMA_IN_PROGRESS ||
 408                         dma_status == DMA_PAUSED) {
 409                         received = dma->rx_bytes_requested - state.residue;
 410                         dmaengine_terminate_all(dma->rx_chan);
 411                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 412                 }
 413         }
 414 }
 415
 416 static inline struct s3c24xx_uart_info
 417         *s3c24xx_port_to_info(struct uart_port *port)
 418 {
 419         return to_ourport(port)->info;
 420 }
 421
 422 static inline struct s3c2410_uartcfg
 423         *s3c24xx_port_to_cfg(struct uart_port *port)
 424 {
 425         struct s3c24xx_uart_port *ourport;
 426
 427         if (port->dev == NULL)
 428                 return NULL;
 429
 430         ourport = container_of(port, struct s3c24xx_uart_port, port);
 431         return ourport->cfg;
 432 }
 433
 434 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 435                                      unsigned long ufstat)
 436 {
 437         struct s3c24xx_uart_info *info = ourport->info;
 438
 439         if (ufstat & info->rx_fifofull)
 440                 return ourport->port.fifosize;
 441
 442         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 443 }
 444
 445 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 446 static void s3c24xx_serial_rx_dma_complete(void *args)
 447 {
 448         struct s3c24xx_uart_port *ourport = args;
 449         struct uart_port *port = &ourport->port;
 450
 451         struct s3c24xx_uart_dma *dma = ourport->dma;
 452         struct tty_port *t = &port->state->port;
 453         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 454
 455         struct dma_tx_state state;
 456         unsigned long flags;
 457         int received;
 458
 459         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 460         received  = dma->rx_bytes_requested - state.residue;
 461         async_tx_ack(dma->rx_desc);
 462
 463         spin_lock_irqsave(&port->lock, flags);
 464
 465         if (received)
 466                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 467
 468         if (tty) {
 469                 tty_flip_buffer_push(t);
 470                 tty_kref_put(tty);
 471         }
 472
 473         s3c64xx_start_rx_dma(ourport);
 474
 475         spin_unlock_irqrestore(&port->lock, flags);
 476 }
 477
 478 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 479 {
 480         struct s3c24xx_uart_dma *dma = ourport->dma;
 481
 482         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 483                                 dma->rx_size, DMA_FROM_DEVICE);
 484
 485         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 486                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 487                                 DMA_PREP_INTERRUPT);
 488         if (!dma->rx_desc) {
 489                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 490                 return;
 491         }
 492
 493         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 494         dma->rx_desc->callback_param = ourport;
 495         dma->rx_bytes_requested = dma->rx_size;
 496
 497         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 498         dma_async_issue_pending(dma->rx_chan);
 499 }
 500
 501 /* ? - where has parity gone?? */
 502 #define S3C2410_UERSTAT_PARITY (0x1000)
 503
 504 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 505 {
 506         struct uart_port *port = &ourport->port;
 507         unsigned int ucon;
 508
 509         /* set Rx mode to DMA mode */
 510         ucon = rd_regl(port, S3C2410_UCON);
 511         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 512                         S3C64XX_UCON_TIMEOUT_MASK |
 513                         S3C64XX_UCON_EMPTYINT_EN |
 514                         S3C64XX_UCON_DMASUS_EN |
 515                         S3C64XX_UCON_TIMEOUT_EN |
 516                         S3C64XX_UCON_RXMODE_MASK);
 517         ucon |= S3C64XX_UCON_RXBURST_1 |
 518                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 519                         S3C64XX_UCON_EMPTYINT_EN |
 520                         S3C64XX_UCON_TIMEOUT_EN |
 521                         S3C64XX_UCON_RXMODE_DMA;
 522         wr_regl(port, S3C2410_UCON, ucon);
 523
 524         ourport->rx_mode = S3C24XX_RX_DMA;
 525 }
 526
 527 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 528 {
 529         struct uart_port *port = &ourport->port;
 530         unsigned int ucon;
 531
 532         /* set Rx mode to DMA mode */
 533         ucon = rd_regl(port, S3C2410_UCON);
 534         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 535                         S3C64XX_UCON_EMPTYINT_EN |
 536                         S3C64XX_UCON_DMASUS_EN |
 537                         S3C64XX_UCON_TIMEOUT_EN |
 538                         S3C64XX_UCON_RXMODE_MASK);
 539         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 540                         S3C64XX_UCON_TIMEOUT_EN |
 541                         S3C64XX_UCON_RXMODE_CPU;
 542         wr_regl(port, S3C2410_UCON, ucon);
 543
 544         ourport->rx_mode = S3C24XX_RX_PIO;
 545 }
 546
 547 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 548
 549 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 550 {
 551         unsigned int utrstat, ufstat, received;
 552         struct s3c24xx_uart_port *ourport = dev_id;
 553         struct uart_port *port = &ourport->port;
 554         struct s3c24xx_uart_dma *dma = ourport->dma;
 555         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 556         struct tty_port *t = &port->state->port;
 557         unsigned long flags;
 558         struct dma_tx_state state;
 559
 560         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 561         ufstat = rd_regl(port, S3C2410_UFSTAT);
 562
 563         spin_lock_irqsave(&port->lock, flags);
 564
 565         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 566                 s3c64xx_start_rx_dma(ourport);
 567                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 568                         enable_rx_dma(ourport);
 569                 goto finish;
 570         }
 571
 572         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 573                 dmaengine_pause(dma->rx_chan);
 574                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 575                 dmaengine_terminate_all(dma->rx_chan);
 576                 received = dma->rx_bytes_requested - state.residue;
 577                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 578
 579                 enable_rx_pio(ourport);
 580         }
 581
 582         s3c24xx_serial_rx_drain_fifo(ourport);
 583
 584         if (tty) {
 585                 tty_flip_buffer_push(t);
 586                 tty_kref_put(tty);
 587         }
 588
 589         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 590
 591 finish:
 592         spin_unlock_irqrestore(&port->lock, flags);
 593
 594         return IRQ_HANDLED;
 595 }
 596
 597 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 598 {
 599         struct uart_port *port = &ourport->port;
 600         unsigned int ufcon, ch, flag, ufstat, uerstat;
 601         unsigned int fifocnt = 0;
 602         int max_count = port->fifosize;
 603
 604         while (max_count-- > 0) {
 605                 /*
 606                  * Receive all characters known to be in FIFO
 607                  * before reading FIFO level again
 608                  */
 609                 if (fifocnt == 0) {
 610                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 611                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 612                         if (fifocnt == 0)
 613                                 break;
 614                 }
 615                 fifocnt--;
 616
 617                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 618                 ch = rd_regb(port, S3C2410_URXH);
 619
 620                 if (port->flags & UPF_CONS_FLOW) {
 621                         int txe = s3c24xx_serial_txempty_nofifo(port);
 622
 623                         if (rx_enabled(port)) {
 624                                 if (!txe) {
 625                                         rx_enabled(port) = 0;
 626                                         continue;
 627                                 }
 628                         } else {
 629                                 if (txe) {
 630                                         ufcon = rd_regl(port, S3C2410_UFCON);
 631                                         ufcon |= S3C2410_UFCON_RESETRX;
 632                                         wr_regl(port, S3C2410_UFCON, ufcon);
 633                                         rx_enabled(port) = 1;
 634                                         return;
 635                                 }
 636                                 continue;
 637                         }
 638                 }
 639
 640                 /* insert the character into the buffer */
 641
 642                 flag = TTY_NORMAL;
 643                 port->icount.rx++;
 644
 645                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 646                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 647                             ch, uerstat);
 648
 649                         /* check for break */
 650                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 651                                 dbg("break!\n");
 652                                 port->icount.brk++;
 653                                 if (uart_handle_break(port))
 654                                         continue; /* Ignore character */
 655                         }
 656
 657                         if (uerstat & S3C2410_UERSTAT_FRAME)
 658                                 port->icount.frame++;
 659                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 660                                 port->icount.overrun++;
 661
 662                         uerstat &= port->read_status_mask;
 663
 664                         if (uerstat & S3C2410_UERSTAT_BREAK)
 665                                 flag = TTY_BREAK;
 666                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 667                                 flag = TTY_PARITY;
 668                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 669                                             S3C2410_UERSTAT_OVERRUN))
 670                                 flag = TTY_FRAME;
 671                 }
 672
 673                 if (uart_handle_sysrq_char(port, ch))
 674                         continue; /* Ignore character */
 675
 676                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 677                                  ch, flag);
 678         }
 679
 680         tty_flip_buffer_push(&port->state->port);
 681 }
 682
 683 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 684 {
 685         struct s3c24xx_uart_port *ourport = dev_id;
 686         struct uart_port *port = &ourport->port;
 687         unsigned long flags;
 688
 689         spin_lock_irqsave(&port->lock, flags);
 690         s3c24xx_serial_rx_drain_fifo(ourport);
 691         spin_unlock_irqrestore(&port->lock, flags);
 692
 693         return IRQ_HANDLED;
 694 }
 695
 696
 697 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 698 {
 699         struct s3c24xx_uart_port *ourport = dev_id;
 700
 701         if (ourport->dma && ourport->dma->rx_chan)
 702                 return s3c24xx_serial_rx_chars_dma(dev_id);
 703         return s3c24xx_serial_rx_chars_pio(dev_id);
 704 }
 705
 706 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 707 {
 708         struct s3c24xx_uart_port *ourport = id;
 709         struct uart_port *port = &ourport->port;
 710         struct circ_buf *xmit = &port->state->xmit;
 711         unsigned long flags;
 712         int count, dma_count = 0;
 713
 714         spin_lock_irqsave(&port->lock, flags);
 715
 716         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 717
 718         if (ourport->dma && ourport->dma->tx_chan &&
 719             count >= ourport->min_dma_size) {
 720                 int align = dma_get_cache_alignment() -
 721                         (xmit->tail & (dma_get_cache_alignment() - 1));
 722                 if (count-align >= ourport->min_dma_size) {
 723                         dma_count = count-align;
 724                         count = align;
 725                 }
 726         }
 727
 728         if (port->x_char) {
 729                 wr_regb(port, S3C2410_UTXH, port->x_char);
 730                 port->icount.tx++;
 731                 port->x_char = 0;
 732                 goto out;
 733         }
 734
 735         /* if there isn't anything more to transmit, or the uart is now
 736          * stopped, disable the uart and exit
 737         */
 738
 739         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 740                 s3c24xx_serial_stop_tx(port);
 741                 goto out;
 742         }
 743
 744         /* try and drain the buffer... */
 745
 746         if (count > port->fifosize) {
 747                 count = port->fifosize;
 748                 dma_count = 0;
 749         }
 750
 751         while (!uart_circ_empty(xmit) && count > 0) {
 752                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 753                         break;
 754
 755                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 756                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 757                 port->icount.tx++;
 758                 count--;
 759         }
 760
 761         if (!count && dma_count) {
 762                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 763                 goto out;
 764         }
 765
 766         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 767                 uart_write_wakeup(port);
 768
 769         if (uart_circ_empty(xmit))
 770                 s3c24xx_serial_stop_tx(port);
 771
 772 out:
 773         spin_unlock_irqrestore(&port->lock, flags);
 774         return IRQ_HANDLED;
 775 }
 776
 777 /* interrupt handler for s3c64xx and later SoC's.*/
 778 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 779 {
 780         struct s3c24xx_uart_port *ourport = id;
 781         struct uart_port *port = &ourport->port;
 782         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 783         irqreturn_t ret = IRQ_HANDLED;
 784
 785         if (pend & S3C64XX_UINTM_RXD_MSK) {
 786                 ret = s3c24xx_serial_rx_chars(irq, id);
 787                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 788         }
 789         if (pend & S3C64XX_UINTM_TXD_MSK) {
 790                 ret = s3c24xx_serial_tx_chars(irq, id);
 791                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 792         }
 793         return ret;
 794 }
 795
 796 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 797 {
 798         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 799         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 800         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 801
 802         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 803                 if ((ufstat & info->tx_fifomask) != 0 ||
 804                     (ufstat & info->tx_fifofull))
 805                         return 0;
 806
 807                 return 1;
 808         }
 809
 810         return s3c24xx_serial_txempty_nofifo(port);
 811 }
 812
 813 /* no modem control lines */
 814 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 815 {
 816         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 817
 818         if (umstat & S3C2410_UMSTAT_CTS)
 819                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 820         else
 821                 return TIOCM_CAR | TIOCM_DSR;
 822 }
 823
 824 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 825 {
 826         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 827
 828         if (mctrl & TIOCM_RTS)
 829                 umcon |= S3C2410_UMCOM_RTS_LOW;
 830         else
 831                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 832
 833         wr_regl(port, S3C2410_UMCON, umcon);
 834 }
 835
 836 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 837 {
 838         unsigned long flags;
 839         unsigned int ucon;
 840
 841         spin_lock_irqsave(&port->lock, flags);
 842
 843         ucon = rd_regl(port, S3C2410_UCON);
 844
 845         if (break_state)
 846                 ucon |= S3C2410_UCON_SBREAK;
 847         else
 848                 ucon &= ~S3C2410_UCON_SBREAK;
 849
 850         wr_regl(port, S3C2410_UCON, ucon);
 851
 852         spin_unlock_irqrestore(&port->lock, flags);
 853 }
 854
 855 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 856 {
 857         struct s3c24xx_uart_dma *dma = p->dma;
 858         dma_cap_mask_t mask;
 859         unsigned long flags;
 860
 861         /* Default slave configuration parameters */
 862         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 863         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 864         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 865         dma->rx_conf.src_maxburst       = 1;
 866
 867         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 868         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 869         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 870         dma->tx_conf.dst_maxburst       = 1;
 871
 872         dma_cap_zero(mask);
 873         dma_cap_set(DMA_SLAVE, mask);
 874
 875         dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 876                                         dma->rx_param, p->port.dev, "rx");
 877         if (!dma->rx_chan)
 878                 return -ENODEV;
 879
 880         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 881
 882         dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
 883                                         dma->tx_param, p->port.dev, "tx");
 884         if (!dma->tx_chan) {
 885                 dma_release_channel(dma->rx_chan);
 886                 return -ENODEV;
 887         }
 888
 889         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 890
 891         /* RX buffer */
 892         dma->rx_size = PAGE_SIZE;
 893
 894         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 895
 896         if (!dma->rx_buf) {
 897                 dma_release_channel(dma->rx_chan);
 898                 dma_release_channel(dma->tx_chan);
 899                 return -ENOMEM;
 900         }
 901
 902         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
 903                                 dma->rx_size, DMA_FROM_DEVICE);
 904
 905         spin_lock_irqsave(&p->port.lock, flags);
 906
 907         /* TX buffer */
 908         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
 909                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 910
 911         spin_unlock_irqrestore(&p->port.lock, flags);
 912
 913         return 0;
 914 }
 915
 916 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 917 {
 918         struct s3c24xx_uart_dma *dma = p->dma;
 919
 920         if (dma->rx_chan) {
 921                 dmaengine_terminate_all(dma->rx_chan);
 922                 dma_unmap_single(p->port.dev, dma->rx_addr,
 923                                 dma->rx_size, DMA_FROM_DEVICE);
 924                 kfree(dma->rx_buf);
 925                 dma_release_channel(dma->rx_chan);
 926                 dma->rx_chan = NULL;
 927         }
 928
 929         if (dma->tx_chan) {
 930                 dmaengine_terminate_all(dma->tx_chan);
 931                 dma_unmap_single(p->port.dev, dma->tx_addr,
 932                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 933                 dma_release_channel(dma->tx_chan);
 934                 dma->tx_chan = NULL;
 935         }
 936 }
 937
 938 static void s3c24xx_serial_shutdown(struct uart_port *port)
 939 {
 940         struct s3c24xx_uart_port *ourport = to_ourport(port);
 941
 942         if (ourport->tx_claimed) {
 943                 if (!s3c24xx_serial_has_interrupt_mask(port))
 944                         free_irq(ourport->tx_irq, ourport);
 945                 tx_enabled(port) = 0;
 946                 ourport->tx_claimed = 0;
 947                 ourport->tx_mode = 0;
 948         }
 949
 950         if (ourport->rx_claimed) {
 951                 if (!s3c24xx_serial_has_interrupt_mask(port))
 952                         free_irq(ourport->rx_irq, ourport);
 953                 ourport->rx_claimed = 0;
 954                 rx_enabled(port) = 0;
 955         }
 956
 957         /* Clear pending interrupts and mask all interrupts */
 958         if (s3c24xx_serial_has_interrupt_mask(port)) {
 959                 free_irq(port->irq, ourport);
 960
 961                 wr_regl(port, S3C64XX_UINTP, 0xf);
 962                 wr_regl(port, S3C64XX_UINTM, 0xf);
 963         }
 964
 965         if (ourport->dma)
 966                 s3c24xx_serial_release_dma(ourport);
 967
 968         ourport->tx_in_progress = 0;
 969 }
 970
 971 static int s3c24xx_serial_startup(struct uart_port *port)
 972 {
 973         struct s3c24xx_uart_port *ourport = to_ourport(port);
 974         int ret;
 975
 976         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
 977             port, (unsigned long long)port->mapbase, port->membase);
 978
 979         rx_enabled(port) = 1;
 980
 981         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
 982                           s3c24xx_serial_portname(port), ourport);
 983
 984         if (ret != 0) {
 985                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
 986                 return ret;
 987         }
 988
 989         ourport->rx_claimed = 1;
 990
 991         dbg("requesting tx irq...\n");
 992
 993         tx_enabled(port) = 1;
 994
 995         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
 996                           s3c24xx_serial_portname(port), ourport);
 997
 998         if (ret) {
 999                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1000                 goto err;
1001         }
1002
1003         ourport->tx_claimed = 1;
1004
1005         dbg("s3c24xx_serial_startup ok\n");
1006
1007         /* the port reset code should have done the correct
1008          * register setup for the port controls */
1009
1010         return ret;
1011
1012 err:
1013         s3c24xx_serial_shutdown(port);
1014         return ret;
1015 }
1016
1017 static int s3c64xx_serial_startup(struct uart_port *port)
1018 {
1019         struct s3c24xx_uart_port *ourport = to_ourport(port);
1020         unsigned long flags;
1021         unsigned int ufcon;
1022         int ret;
1023
1024         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1025             port, (unsigned long long)port->mapbase, port->membase);
1026
1027         wr_regl(port, S3C64XX_UINTM, 0xf);
1028         if (ourport->dma) {
1029                 ret = s3c24xx_serial_request_dma(ourport);
1030                 if (ret < 0) {
1031                         dev_warn(port->dev,
1032                                  "DMA request failed, DMA will not be used\n");
1033                         devm_kfree(port->dev, ourport->dma);
1034                         ourport->dma = NULL;
1035                 }
1036         }
1037
1038         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1039                           s3c24xx_serial_portname(port), ourport);
1040         if (ret) {
1041                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1042                 return ret;
1043         }
1044
1045         /* For compatibility with s3c24xx Soc's */
1046         rx_enabled(port) = 1;
1047         ourport->rx_claimed = 1;
1048         tx_enabled(port) = 0;
1049         ourport->tx_claimed = 1;
1050
1051         spin_lock_irqsave(&port->lock, flags);
1052
1053         ufcon = rd_regl(port, S3C2410_UFCON);
1054         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1055         if (!uart_console(port))
1056                 ufcon |= S3C2410_UFCON_RESETTX;
1057         wr_regl(port, S3C2410_UFCON, ufcon);
1058
1059         enable_rx_pio(ourport);
1060
1061         spin_unlock_irqrestore(&port->lock, flags);
1062
1063         /* Enable Rx Interrupt */
1064         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1065
1066         dbg("s3c64xx_serial_startup ok\n");
1067         return ret;
1068 }
1069
1070 /* power power management control */
1071
1072 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1073                               unsigned int old)
1074 {
1075         struct s3c24xx_uart_port *ourport = to_ourport(port);
1076         int timeout = 10000;
1077
1078         ourport->pm_level = level;
1079
1080         switch (level) {
1081         case 3:
1082                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1083                         udelay(100);
1084
1085                 if (!IS_ERR(ourport->baudclk))
1086                         clk_disable_unprepare(ourport->baudclk);
1087
1088                 clk_disable_unprepare(ourport->clk);
1089                 break;
1090
1091         case 0:
1092                 clk_prepare_enable(ourport->clk);
1093
1094                 if (!IS_ERR(ourport->baudclk))
1095                         clk_prepare_enable(ourport->baudclk);
1096
1097                 break;
1098         default:
1099                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1100         }
1101 }
1102
1103 /* baud rate calculation
1104  *
1105  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1106  * of different sources, including the peripheral clock ("pclk") and an
1107  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1108  * with a programmable extra divisor.
1109  *
1110  * The following code goes through the clock sources, and calculates the
1111  * baud clocks (and the resultant actual baud rates) and then tries to
1112  * pick the closest one and select that.
1113  *
1114 */
1115
1116 #define MAX_CLK_NAME_LENGTH 15
1117
1118 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1119 {
1120         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1121         unsigned int ucon;
1122
1123         if (info->num_clks == 1)
1124                 return 0;
1125
1126         ucon = rd_regl(port, S3C2410_UCON);
1127         ucon &= info->clksel_mask;
1128         return ucon >> info->clksel_shift;
1129 }
1130
1131 static void s3c24xx_serial_setsource(struct uart_port *port,
1132                         unsigned int clk_sel)
1133 {
1134         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1135         unsigned int ucon;
1136
1137         if (info->num_clks == 1)
1138                 return;
1139
1140         ucon = rd_regl(port, S3C2410_UCON);
1141         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1142                 return;
1143
1144         ucon &= ~info->clksel_mask;
1145         ucon |= clk_sel << info->clksel_shift;
1146         wr_regl(port, S3C2410_UCON, ucon);
1147 }
1148
1149 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1150                         unsigned int req_baud, struct clk **best_clk,
1151                         unsigned int *clk_num)
1152 {
1153         struct s3c24xx_uart_info *info = ourport->info;
1154         struct clk *clk;
1155         unsigned long rate;
1156         unsigned int cnt, baud, quot, best_quot = 0;
1157         char clkname[MAX_CLK_NAME_LENGTH];
1158         int calc_deviation, deviation = (1 << 30) - 1;
1159
1160         for (cnt = 0; cnt < info->num_clks; cnt++) {
1161                 /* Keep selected clock if provided */
1162                 if (ourport->cfg->clk_sel &&
1163                         !(ourport->cfg->clk_sel & (1 << cnt)))
1164                         continue;
1165
1166                 sprintf(clkname, "clk_uart_baud%d", cnt);
1167                 clk = clk_get(ourport->port.dev, clkname);
1168                 if (IS_ERR(clk))
1169                         continue;
1170
1171                 rate = clk_get_rate(clk);
1172                 if (!rate)
1173                         continue;
1174
1175                 if (ourport->info->has_divslot) {
1176                         unsigned long div = rate / req_baud;
1177
1178                         /* The UDIVSLOT register on the newer UARTs allows us to
1179                          * get a divisor adjustment of 1/16th on the baud clock.
1180                          *
1181                          * We don't keep the UDIVSLOT value (the 16ths we
1182                          * calculated by not multiplying the baud by 16) as it
1183                          * is easy enough to recalculate.
1184                          */
1185
1186                         quot = div / 16;
1187                         baud = rate / div;
1188                 } else {
1189                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1190                         baud = rate / (quot * 16);
1191                 }
1192                 quot--;
1193
1194                 calc_deviation = req_baud - baud;
1195                 if (calc_deviation < 0)
1196                         calc_deviation = -calc_deviation;
1197
1198                 if (calc_deviation < deviation) {
1199                         *best_clk = clk;
1200                         best_quot = quot;
1201                         *clk_num = cnt;
1202                         deviation = calc_deviation;
1203                 }
1204         }
1205
1206         return best_quot;
1207 }
1208
1209 /* udivslot_table[]
1210  *
1211  * This table takes the fractional value of the baud divisor and gives
1212  * the recommended setting for the UDIVSLOT register.
1213  */
1214 static u16 udivslot_table[16] = {
1215         [0] = 0x0000,
1216         [1] = 0x0080,
1217         [2] = 0x0808,
1218         [3] = 0x0888,
1219         [4] = 0x2222,
1220         [5] = 0x4924,
1221         [6] = 0x4A52,
1222         [7] = 0x54AA,
1223         [8] = 0x5555,
1224         [9] = 0xD555,
1225         [10] = 0xD5D5,
1226         [11] = 0xDDD5,
1227         [12] = 0xDDDD,
1228         [13] = 0xDFDD,
1229         [14] = 0xDFDF,
1230         [15] = 0xFFDF,
1231 };
1232
1233 static void s3c24xx_serial_set_termios(struct uart_port *port,
1234                                        struct ktermios *termios,
1235                                        struct ktermios *old)
1236 {
1237         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1238         struct s3c24xx_uart_port *ourport = to_ourport(port);
1239         struct clk *clk = ERR_PTR(-EINVAL);
1240         unsigned long flags;
1241         unsigned int baud, quot, clk_sel = 0;
1242         unsigned int ulcon;
1243         unsigned int umcon;
1244         unsigned int udivslot = 0;
1245
1246         /*
1247          * We don't support modem control lines.
1248          */
1249         termios->c_cflag &= ~(HUPCL | CMSPAR);
1250         termios->c_cflag |= CLOCAL;
1251
1252         /*
1253          * Ask the core to calculate the divisor for us.
1254          */
1255
1256         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1257         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1258         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1259                 quot = port->custom_divisor;
1260         if (IS_ERR(clk))
1261                 return;
1262
1263         /* check to see if we need  to change clock source */
1264
1265         if (ourport->baudclk != clk) {
1266                 clk_prepare_enable(clk);
1267
1268                 s3c24xx_serial_setsource(port, clk_sel);
1269
1270                 if (!IS_ERR(ourport->baudclk)) {
1271                         clk_disable_unprepare(ourport->baudclk);
1272                         ourport->baudclk = ERR_PTR(-EINVAL);
1273                 }
1274
1275                 ourport->baudclk = clk;
1276                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1277         }
1278
1279         if (ourport->info->has_divslot) {
1280                 unsigned int div = ourport->baudclk_rate / baud;
1281
1282                 if (cfg->has_fracval) {
1283                         udivslot = (div & 15);
1284                         dbg("fracval = %04x\n", udivslot);
1285                 } else {
1286                         udivslot = udivslot_table[div & 15];
1287                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1288                 }
1289         }
1290
1291         switch (termios->c_cflag & CSIZE) {
1292         case CS5:
1293                 dbg("config: 5bits/char\n");
1294                 ulcon = S3C2410_LCON_CS5;
1295                 break;
1296         case CS6:
1297                 dbg("config: 6bits/char\n");
1298                 ulcon = S3C2410_LCON_CS6;
1299                 break;
1300         case CS7:
1301                 dbg("config: 7bits/char\n");
1302                 ulcon = S3C2410_LCON_CS7;
1303                 break;
1304         case CS8:
1305         default:
1306                 dbg("config: 8bits/char\n");
1307                 ulcon = S3C2410_LCON_CS8;
1308                 break;
1309         }
1310
1311         /* preserve original lcon IR settings */
1312         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1313
1314         if (termios->c_cflag & CSTOPB)
1315                 ulcon |= S3C2410_LCON_STOPB;
1316
1317         if (termios->c_cflag & PARENB) {
1318                 if (termios->c_cflag & PARODD)
1319                         ulcon |= S3C2410_LCON_PODD;
1320                 else
1321                         ulcon |= S3C2410_LCON_PEVEN;
1322         } else {
1323                 ulcon |= S3C2410_LCON_PNONE;
1324         }
1325
1326         spin_lock_irqsave(&port->lock, flags);
1327
1328         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1329             ulcon, quot, udivslot);
1330
1331         wr_regl(port, S3C2410_ULCON, ulcon);
1332         wr_regl(port, S3C2410_UBRDIV, quot);
1333
1334         port->status &= ~UPSTAT_AUTOCTS;
1335
1336         umcon = rd_regl(port, S3C2410_UMCON);
1337         if (termios->c_cflag & CRTSCTS) {
1338                 umcon |= S3C2410_UMCOM_AFC;
1339                 /* Disable RTS when RX FIFO contains 63 bytes */
1340                 umcon &= ~S3C2412_UMCON_AFC_8;
1341                 port->status = UPSTAT_AUTOCTS;
1342         } else {
1343                 umcon &= ~S3C2410_UMCOM_AFC;
1344         }
1345         wr_regl(port, S3C2410_UMCON, umcon);
1346
1347         if (ourport->info->has_divslot)
1348                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1349
1350         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1351             rd_regl(port, S3C2410_ULCON),
1352             rd_regl(port, S3C2410_UCON),
1353             rd_regl(port, S3C2410_UFCON));
1354
1355         /*
1356          * Update the per-port timeout.
1357          */
1358         uart_update_timeout(port, termios->c_cflag, baud);
1359
1360         /*
1361          * Which character status flags are we interested in?
1362          */
1363         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1364         if (termios->c_iflag & INPCK)
1365                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1366                         S3C2410_UERSTAT_PARITY;
1367         /*
1368          * Which character status flags should we ignore?
1369          */
1370         port->ignore_status_mask = 0;
1371         if (termios->c_iflag & IGNPAR)
1372                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1373         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1374                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1375
1376         /*
1377          * Ignore all characters if CREAD is not set.
1378          */
1379         if ((termios->c_cflag & CREAD) == 0)
1380                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1381
1382         spin_unlock_irqrestore(&port->lock, flags);
1383 }
1384
1385 static const char *s3c24xx_serial_type(struct uart_port *port)
1386 {
1387         switch (port->type) {
1388         case PORT_S3C2410:
1389                 return "S3C2410";
1390         case PORT_S3C2440:
1391                 return "S3C2440";
1392         case PORT_S3C2412:
1393                 return "S3C2412";
1394         case PORT_S3C6400:
1395                 return "S3C6400/10";
1396         default:
1397                 return NULL;
1398         }
1399 }
1400
1401 #define MAP_SIZE (0x100)
1402
1403 static void s3c24xx_serial_release_port(struct uart_port *port)
1404 {
1405         release_mem_region(port->mapbase, MAP_SIZE);
1406 }
1407
1408 static int s3c24xx_serial_request_port(struct uart_port *port)
1409 {
1410         const char *name = s3c24xx_serial_portname(port);
1411         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1412 }
1413
1414 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1415 {
1416         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1417
1418         if (flags & UART_CONFIG_TYPE &&
1419             s3c24xx_serial_request_port(port) == 0)
1420                 port->type = info->type;
1421 }
1422
1423 /*
1424  * verify the new serial_struct (for TIOCSSERIAL).
1425  */
1426 static int
1427 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1428 {
1429         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1430
1431         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1432                 return -EINVAL;
1433
1434         return 0;
1435 }
1436
1437
1438 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1439
1440 static struct console s3c24xx_serial_console;
1441
1442 static int __init s3c24xx_serial_console_init(void)
1443 {
1444         register_console(&s3c24xx_serial_console);
1445         return 0;
1446 }
1447 console_initcall(s3c24xx_serial_console_init);
1448
1449 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1450 #else
1451 #define S3C24XX_SERIAL_CONSOLE NULL
1452 #endif
1453
1454 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1455 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1456 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1457                          unsigned char c);
1458 #endif
1459
1460 static struct uart_ops s3c24xx_serial_ops = {
1461         .pm             = s3c24xx_serial_pm,
1462         .tx_empty       = s3c24xx_serial_tx_empty,
1463         .get_mctrl      = s3c24xx_serial_get_mctrl,
1464         .set_mctrl      = s3c24xx_serial_set_mctrl,
1465         .stop_tx        = s3c24xx_serial_stop_tx,
1466         .start_tx       = s3c24xx_serial_start_tx,
1467         .stop_rx        = s3c24xx_serial_stop_rx,
1468         .break_ctl      = s3c24xx_serial_break_ctl,
1469         .startup        = s3c24xx_serial_startup,
1470         .shutdown       = s3c24xx_serial_shutdown,
1471         .set_termios    = s3c24xx_serial_set_termios,
1472         .type           = s3c24xx_serial_type,
1473         .release_port   = s3c24xx_serial_release_port,
1474         .request_port   = s3c24xx_serial_request_port,
1475         .config_port    = s3c24xx_serial_config_port,
1476         .verify_port    = s3c24xx_serial_verify_port,
1477 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1478         .poll_get_char = s3c24xx_serial_get_poll_char,
1479         .poll_put_char = s3c24xx_serial_put_poll_char,
1480 #endif
1481 };
1482
1483 static struct uart_driver s3c24xx_uart_drv = {
1484         .owner          = THIS_MODULE,
1485         .driver_name    = "s3c2410_serial",
1486         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1487         .cons           = S3C24XX_SERIAL_CONSOLE,
1488         .dev_name       = S3C24XX_SERIAL_NAME,
1489         .major          = S3C24XX_SERIAL_MAJOR,
1490         .minor          = S3C24XX_SERIAL_MINOR,
1491 };
1492
1493 #define __PORT_LOCK_UNLOCKED(i) \
1494         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1495 static struct s3c24xx_uart_port
1496 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1497         [0] = {
1498                 .port = {
1499                         .lock           = __PORT_LOCK_UNLOCKED(0),
1500                         .iotype         = UPIO_MEM,
1501                         .uartclk        = 0,
1502                         .fifosize       = 16,
1503                         .ops            = &s3c24xx_serial_ops,
1504                         .flags          = UPF_BOOT_AUTOCONF,
1505                         .line           = 0,
1506                 }
1507         },
1508         [1] = {
1509                 .port = {
1510                         .lock           = __PORT_LOCK_UNLOCKED(1),
1511                         .iotype         = UPIO_MEM,
1512                         .uartclk        = 0,
1513                         .fifosize       = 16,
1514                         .ops            = &s3c24xx_serial_ops,
1515                         .flags          = UPF_BOOT_AUTOCONF,
1516                         .line           = 1,
1517                 }
1518         },
1519 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1520
1521         [2] = {
1522                 .port = {
1523                         .lock           = __PORT_LOCK_UNLOCKED(2),
1524                         .iotype         = UPIO_MEM,
1525                         .uartclk        = 0,
1526                         .fifosize       = 16,
1527                         .ops            = &s3c24xx_serial_ops,
1528                         .flags          = UPF_BOOT_AUTOCONF,
1529                         .line           = 2,
1530                 }
1531         },
1532 #endif
1533 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1534         [3] = {
1535                 .port = {
1536                         .lock           = __PORT_LOCK_UNLOCKED(3),
1537                         .iotype         = UPIO_MEM,
1538                         .uartclk        = 0,
1539                         .fifosize       = 16,
1540                         .ops            = &s3c24xx_serial_ops,
1541                         .flags          = UPF_BOOT_AUTOCONF,
1542                         .line           = 3,
1543                 }
1544         }
1545 #endif
1546 };
1547 #undef __PORT_LOCK_UNLOCKED
1548
1549 /* s3c24xx_serial_resetport
1550  *
1551  * reset the fifos and other the settings.
1552 */
1553
1554 static void s3c24xx_serial_resetport(struct uart_port *port,
1555                                    struct s3c2410_uartcfg *cfg)
1556 {
1557         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1558         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1559         unsigned int ucon_mask;
1560
1561         ucon_mask = info->clksel_mask;
1562         if (info->type == PORT_S3C2440)
1563                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1564
1565         ucon &= ucon_mask;
1566         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1567
1568         /* reset both fifos */
1569         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1570         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1571
1572         /* some delay is required after fifo reset */
1573         udelay(1);
1574 }
1575
1576
1577 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1578
1579 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1580                                              unsigned long val, void *data)
1581 {
1582         struct s3c24xx_uart_port *port;
1583         struct uart_port *uport;
1584
1585         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1586         uport = &port->port;
1587
1588         /* check to see if port is enabled */
1589
1590         if (port->pm_level != 0)
1591                 return 0;
1592
1593         /* try and work out if the baudrate is changing, we can detect
1594          * a change in rate, but we do not have support for detecting
1595          * a disturbance in the clock-rate over the change.
1596          */
1597
1598         if (IS_ERR(port->baudclk))
1599                 goto exit;
1600
1601         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1602                 goto exit;
1603
1604         if (val == CPUFREQ_PRECHANGE) {
1605                 /* we should really shut the port down whilst the
1606                  * frequency change is in progress. */
1607
1608         } else if (val == CPUFREQ_POSTCHANGE) {
1609                 struct ktermios *termios;
1610                 struct tty_struct *tty;
1611
1612                 if (uport->state == NULL)
1613                         goto exit;
1614
1615                 tty = uport->state->port.tty;
1616
1617                 if (tty == NULL)
1618                         goto exit;
1619
1620                 termios = &tty->termios;
1621
1622                 if (termios == NULL) {
1623                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1624                         goto exit;
1625                 }
1626
1627                 s3c24xx_serial_set_termios(uport, termios, NULL);
1628         }
1629
1630 exit:
1631         return 0;
1632 }
1633
1634 static inline int
1635 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1636 {
1637         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1638
1639         return cpufreq_register_notifier(&port->freq_transition,
1640                                          CPUFREQ_TRANSITION_NOTIFIER);
1641 }
1642
1643 static inline void
1644 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1645 {
1646         cpufreq_unregister_notifier(&port->freq_transition,
1647                                     CPUFREQ_TRANSITION_NOTIFIER);
1648 }
1649
1650 #else
1651 static inline int
1652 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1653 {
1654         return 0;
1655 }
1656
1657 static inline void
1658 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1659 {
1660 }
1661 #endif
1662
1663 /* s3c24xx_serial_init_port
1664  *
1665  * initialise a single serial port from the platform device given
1666  */
1667
1668 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1669                                     struct platform_device *platdev)
1670 {
1671         struct uart_port *port = &ourport->port;
1672         struct s3c2410_uartcfg *cfg = ourport->cfg;
1673         struct resource *res;
1674         int ret;
1675
1676         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1677
1678         if (platdev == NULL)
1679                 return -ENODEV;
1680
1681         if (port->mapbase != 0)
1682                 return -EINVAL;
1683
1684         /* setup info for port */
1685         port->dev       = &platdev->dev;
1686
1687         /* Startup sequence is different for s3c64xx and higher SoC's */
1688         if (s3c24xx_serial_has_interrupt_mask(port))
1689                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1690
1691         port->uartclk = 1;
1692
1693         if (cfg->uart_flags & UPF_CONS_FLOW) {
1694                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1695                 port->flags |= UPF_CONS_FLOW;
1696         }
1697
1698         /* sort our the physical and virtual addresses for each UART */
1699
1700         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1701         if (res == NULL) {
1702                 dev_err(port->dev, "failed to find memory resource for uart\n");
1703                 return -EINVAL;
1704         }
1705
1706         dbg("resource %pR)\n", res);
1707
1708         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1709         if (!port->membase) {
1710                 dev_err(port->dev, "failed to remap controller address\n");
1711                 return -EBUSY;
1712         }
1713
1714         port->mapbase = res->start;
1715         ret = platform_get_irq(platdev, 0);
1716         if (ret < 0)
1717                 port->irq = 0;
1718         else {
1719                 port->irq = ret;
1720                 ourport->rx_irq = ret;
1721                 ourport->tx_irq = ret + 1;
1722         }
1723
1724         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1725                 ret = platform_get_irq(platdev, 1);
1726                 if (ret > 0)
1727                         ourport->tx_irq = ret;
1728         }
1729         /*
1730          * DMA is currently supported only on DT platforms, if DMA properties
1731          * are specified.
1732          */
1733         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1734                                                      "dmas", NULL)) {
1735                 ourport->dma = devm_kzalloc(port->dev,
1736                                             sizeof(*ourport->dma),
1737                                             GFP_KERNEL);
1738                 if (!ourport->dma) {
1739                         ret = -ENOMEM;
1740                         goto err;
1741                 }
1742         }
1743
1744         ourport->clk    = clk_get(&platdev->dev, "uart");
1745         if (IS_ERR(ourport->clk)) {
1746                 pr_err("%s: Controller clock not found\n",
1747                                 dev_name(&platdev->dev));
1748                 ret = PTR_ERR(ourport->clk);
1749                 goto err;
1750         }
1751
1752         ret = clk_prepare_enable(ourport->clk);
1753         if (ret) {
1754                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1755                 clk_put(ourport->clk);
1756                 goto err;
1757         }
1758
1759         /* Keep all interrupts masked and cleared */
1760         if (s3c24xx_serial_has_interrupt_mask(port)) {
1761                 wr_regl(port, S3C64XX_UINTM, 0xf);
1762                 wr_regl(port, S3C64XX_UINTP, 0xf);
1763                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1764         }
1765
1766         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1767             &port->mapbase, port->membase, port->irq,
1768             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1769
1770         /* reset the fifos (and setup the uart) */
1771         s3c24xx_serial_resetport(port, cfg);
1772
1773         return 0;
1774
1775 err:
1776         port->mapbase = 0;
1777         return ret;
1778 }
1779
1780 /* Device driver serial port probe */
1781
1782 static const struct of_device_id s3c24xx_uart_dt_match[];
1783 static int probe_index;
1784
1785 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1786                         struct platform_device *pdev)
1787 {
1788 #ifdef CONFIG_OF
1789         if (pdev->dev.of_node) {
1790                 const struct of_device_id *match;
1791                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1792                 return (struct s3c24xx_serial_drv_data *)match->data;
1793         }
1794 #endif
1795         return (struct s3c24xx_serial_drv_data *)
1796                         platform_get_device_id(pdev)->driver_data;
1797 }
1798
1799 static int s3c24xx_serial_probe(struct platform_device *pdev)
1800 {
1801         struct device_node *np = pdev->dev.of_node;
1802         struct s3c24xx_uart_port *ourport;
1803         int index = probe_index;
1804         int ret;
1805
1806         if (np) {
1807                 ret = of_alias_get_id(np, "serial");
1808                 if (ret >= 0)
1809                         index = ret;
1810         }
1811
1812         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1813
1814         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1815                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1816                 return -EINVAL;
1817         }
1818         ourport = &s3c24xx_serial_ports[index];
1819
1820         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1821         if (!ourport->drv_data) {
1822                 dev_err(&pdev->dev, "could not find driver data\n");
1823                 return -ENODEV;
1824         }
1825
1826         ourport->baudclk = ERR_PTR(-EINVAL);
1827         ourport->info = ourport->drv_data->info;
1828         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1829                         dev_get_platdata(&pdev->dev) :
1830                         ourport->drv_data->def_cfg;
1831
1832         if (np)
1833                 of_property_read_u32(np,
1834                         "samsung,uart-fifosize", &ourport->port.fifosize);
1835
1836         if (ourport->drv_data->fifosize[index])
1837                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1838         else if (ourport->info->fifosize)
1839                 ourport->port.fifosize = ourport->info->fifosize;
1840
1841         /*
1842          * DMA transfers must be aligned at least to cache line size,
1843          * so find minimal transfer size suitable for DMA mode
1844          */
1845         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1846                                     dma_get_cache_alignment());
1847
1848         dbg("%s: initialising port %p...\n", __func__, ourport);
1849
1850         ret = s3c24xx_serial_init_port(ourport, pdev);
1851         if (ret < 0)
1852                 return ret;
1853
1854         if (!s3c24xx_uart_drv.state) {
1855                 ret = uart_register_driver(&s3c24xx_uart_drv);
1856                 if (ret < 0) {
1857                         pr_err("Failed to register Samsung UART driver\n");
1858                         return ret;
1859                 }
1860         }
1861
1862         dbg("%s: adding port\n", __func__);
1863         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1864         platform_set_drvdata(pdev, &ourport->port);
1865
1866         /*
1867          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1868          * so that a potential re-enablement through the pm-callback overlaps
1869          * and keeps the clock enabled in this case.
1870          */
1871         clk_disable_unprepare(ourport->clk);
1872
1873         ret = s3c24xx_serial_cpufreq_register(ourport);
1874         if (ret < 0)
1875                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1876
1877         probe_index++;
1878
1879         return 0;
1880 }
1881
1882 static int s3c24xx_serial_remove(struct platform_device *dev)
1883 {
1884         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1885
1886         if (port) {
1887                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1888                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1889         }
1890
1891         uart_unregister_driver(&s3c24xx_uart_drv);
1892
1893         return 0;
1894 }
1895
1896 /* UART power management code */
1897 #ifdef CONFIG_PM_SLEEP
1898 static int s3c24xx_serial_suspend(struct device *dev)
1899 {
1900         struct uart_port *port = s3c24xx_dev_to_port(dev);
1901
1902         if (port)
1903                 uart_suspend_port(&s3c24xx_uart_drv, port);
1904
1905         return 0;
1906 }
1907
1908 static int s3c24xx_serial_resume(struct device *dev)
1909 {
1910         struct uart_port *port = s3c24xx_dev_to_port(dev);
1911         struct s3c24xx_uart_port *ourport = to_ourport(port);
1912
1913         if (port) {
1914                 clk_prepare_enable(ourport->clk);
1915                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1916                 clk_disable_unprepare(ourport->clk);
1917
1918                 uart_resume_port(&s3c24xx_uart_drv, port);
1919         }
1920
1921         return 0;
1922 }
1923
1924 static int s3c24xx_serial_resume_noirq(struct device *dev)
1925 {
1926         struct uart_port *port = s3c24xx_dev_to_port(dev);
1927
1928         if (port) {
1929                 /* restore IRQ mask */
1930                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1931                         unsigned int uintm = 0xf;
1932                         if (tx_enabled(port))
1933                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1934                         if (rx_enabled(port))
1935                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1936                         wr_regl(port, S3C64XX_UINTM, uintm);
1937                 }
1938         }
1939
1940         return 0;
1941 }
1942
1943 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1944         .suspend = s3c24xx_serial_suspend,
1945         .resume = s3c24xx_serial_resume,
1946         .resume_noirq = s3c24xx_serial_resume_noirq,
1947 };
1948 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1949
1950 #else /* !CONFIG_PM_SLEEP */
1951
1952 #define SERIAL_SAMSUNG_PM_OPS   NULL
1953 #endif /* CONFIG_PM_SLEEP */
1954
1955 /* Console code */
1956
1957 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1958
1959 static struct uart_port *cons_uart;
1960
1961 static int
1962 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1963 {
1964         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1965         unsigned long ufstat, utrstat;
1966
1967         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1968                 /* fifo mode - check amount of data in fifo registers... */
1969
1970                 ufstat = rd_regl(port, S3C2410_UFSTAT);
1971                 return (ufstat & info->tx_fifofull) ? 0 : 1;
1972         }
1973
1974         /* in non-fifo mode, we go and use the tx buffer empty */
1975
1976         utrstat = rd_regl(port, S3C2410_UTRSTAT);
1977         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1978 }
1979
1980 static bool
1981 s3c24xx_port_configured(unsigned int ucon)
1982 {
1983         /* consider the serial port configured if the tx/rx mode set */
1984         return (ucon & 0xf) != 0;
1985 }
1986
1987 #ifdef CONFIG_CONSOLE_POLL
1988 /*
1989  * Console polling routines for writing and reading from the uart while
1990  * in an interrupt or debug context.
1991  */
1992
1993 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1994 {
1995         struct s3c24xx_uart_port *ourport = to_ourport(port);
1996         unsigned int ufstat;
1997
1998         ufstat = rd_regl(port, S3C2410_UFSTAT);
1999         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2000                 return NO_POLL_CHAR;
2001
2002         return rd_regb(port, S3C2410_URXH);
2003 }
2004
2005 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2006                 unsigned char c)
2007 {
2008         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2009         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2010
2011         /* not possible to xmit on unconfigured port */
2012         if (!s3c24xx_port_configured(ucon))
2013                 return;
2014
2015         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2016                 cpu_relax();
2017         wr_regb(port, S3C2410_UTXH, c);
2018 }
2019
2020 #endif /* CONFIG_CONSOLE_POLL */
2021
2022 static void
2023 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2024 {
2025         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2026
2027         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2028                 cpu_relax();
2029         wr_regb(port, S3C2410_UTXH, ch);
2030 }
2031
2032 static void
2033 s3c24xx_serial_console_write(struct console *co, const char *s,
2034                              unsigned int count)
2035 {
2036         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2037
2038         /* not possible to xmit on unconfigured port */
2039         if (!s3c24xx_port_configured(ucon))
2040                 return;
2041
2042         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2043 }
2044
2045 static void __init
2046 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2047                            int *parity, int *bits)
2048 {
2049         struct clk *clk;
2050         unsigned int ulcon;
2051         unsigned int ucon;
2052         unsigned int ubrdiv;
2053         unsigned long rate;
2054         unsigned int clk_sel;
2055         char clk_name[MAX_CLK_NAME_LENGTH];
2056
2057         ulcon  = rd_regl(port, S3C2410_ULCON);
2058         ucon   = rd_regl(port, S3C2410_UCON);
2059         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2060
2061         dbg("s3c24xx_serial_get_options: port=%p\n"
2062             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2063             port, ulcon, ucon, ubrdiv);
2064
2065         if (s3c24xx_port_configured(ucon)) {
2066                 switch (ulcon & S3C2410_LCON_CSMASK) {
2067                 case S3C2410_LCON_CS5:
2068                         *bits = 5;
2069                         break;
2070                 case S3C2410_LCON_CS6:
2071                         *bits = 6;
2072                         break;
2073                 case S3C2410_LCON_CS7:
2074                         *bits = 7;
2075                         break;
2076                 case S3C2410_LCON_CS8:
2077                 default:
2078                         *bits = 8;
2079                         break;
2080                 }
2081
2082                 switch (ulcon & S3C2410_LCON_PMASK) {
2083                 case S3C2410_LCON_PEVEN:
2084                         *parity = 'e';
2085                         break;
2086
2087                 case S3C2410_LCON_PODD:
2088                         *parity = 'o';
2089                         break;
2090
2091                 case S3C2410_LCON_PNONE:
2092                 default:
2093                         *parity = 'n';
2094                 }
2095
2096                 /* now calculate the baud rate */
2097
2098                 clk_sel = s3c24xx_serial_getsource(port);
2099                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2100
2101                 clk = clk_get(port->dev, clk_name);
2102                 if (!IS_ERR(clk))
2103                         rate = clk_get_rate(clk);
2104                 else
2105                         rate = 1;
2106
2107                 *baud = rate / (16 * (ubrdiv + 1));
2108                 dbg("calculated baud %d\n", *baud);
2109         }
2110
2111 }
2112
2113 static int __init
2114 s3c24xx_serial_console_setup(struct console *co, char *options)
2115 {
2116         struct uart_port *port;
2117         int baud = 9600;
2118         int bits = 8;
2119         int parity = 'n';
2120         int flow = 'n';
2121
2122         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2123             co, co->index, options);
2124
2125         /* is this a valid port */
2126
2127         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2128                 co->index = 0;
2129
2130         port = &s3c24xx_serial_ports[co->index].port;
2131
2132         /* is the port configured? */
2133
2134         if (port->mapbase == 0x0)
2135                 return -ENODEV;
2136
2137         cons_uart = port;
2138
2139         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2140
2141         /*
2142          * Check whether an invalid uart number has been specified, and
2143          * if so, search for the first available port that does have
2144          * console support.
2145          */
2146         if (options)
2147                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2148         else
2149                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2150
2151         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2152
2153         return uart_set_options(port, co, baud, parity, bits, flow);
2154 }
2155
2156 static struct console s3c24xx_serial_console = {
2157         .name           = S3C24XX_SERIAL_NAME,
2158         .device         = uart_console_device,
2159         .flags          = CON_PRINTBUFFER,
2160         .index          = -1,
2161         .write          = s3c24xx_serial_console_write,
2162         .setup          = s3c24xx_serial_console_setup,
2163         .data           = &s3c24xx_uart_drv,
2164 };
2165 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2166
2167 #ifdef CONFIG_CPU_S3C2410
2168 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2169         .info = &(struct s3c24xx_uart_info) {
2170                 .name           = "Samsung S3C2410 UART",
2171                 .type           = PORT_S3C2410,
2172                 .fifosize       = 16,
2173                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2174                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2175                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2176                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2177                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2178                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2179                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2180                 .num_clks       = 2,
2181                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2182                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2183         },
2184         .def_cfg = &(struct s3c2410_uartcfg) {
2185                 .ucon           = S3C2410_UCON_DEFAULT,
2186                 .ufcon          = S3C2410_UFCON_DEFAULT,
2187         },
2188 };
2189 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2190 #else
2191 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2192 #endif
2193
2194 #ifdef CONFIG_CPU_S3C2412
2195 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2196         .info = &(struct s3c24xx_uart_info) {
2197                 .name           = "Samsung S3C2412 UART",
2198                 .type           = PORT_S3C2412,
2199                 .fifosize       = 64,
2200                 .has_divslot    = 1,
2201                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2202                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2203                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2204                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2205                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2206                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2207                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2208                 .num_clks       = 4,
2209                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2210                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2211         },
2212         .def_cfg = &(struct s3c2410_uartcfg) {
2213                 .ucon           = S3C2410_UCON_DEFAULT,
2214                 .ufcon          = S3C2410_UFCON_DEFAULT,
2215         },
2216 };
2217 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2218 #else
2219 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2220 #endif
2221
2222 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2223         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2224 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2225         .info = &(struct s3c24xx_uart_info) {
2226                 .name           = "Samsung S3C2440 UART",
2227                 .type           = PORT_S3C2440,
2228                 .fifosize       = 64,
2229                 .has_divslot    = 1,
2230                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2231                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2232                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2233                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2234                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2235                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2236                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2237                 .num_clks       = 4,
2238                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2239                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2240         },
2241         .def_cfg = &(struct s3c2410_uartcfg) {
2242                 .ucon           = S3C2410_UCON_DEFAULT,
2243                 .ufcon          = S3C2410_UFCON_DEFAULT,
2244         },
2245 };
2246 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2247 #else
2248 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2249 #endif
2250
2251 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2252 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2253         .info = &(struct s3c24xx_uart_info) {
2254                 .name           = "Samsung S3C6400 UART",
2255                 .type           = PORT_S3C6400,
2256                 .fifosize       = 64,
2257                 .has_divslot    = 1,
2258                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2259                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2260                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2261                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2262                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2263                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2264                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2265                 .num_clks       = 4,
2266                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2267                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2268         },
2269         .def_cfg = &(struct s3c2410_uartcfg) {
2270                 .ucon           = S3C2410_UCON_DEFAULT,
2271                 .ufcon          = S3C2410_UFCON_DEFAULT,
2272         },
2273 };
2274 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2275 #else
2276 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2277 #endif
2278
2279 #ifdef CONFIG_CPU_S5PV210
2280 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2281         .info = &(struct s3c24xx_uart_info) {
2282                 .name           = "Samsung S5PV210 UART",
2283                 .type           = PORT_S3C6400,
2284                 .has_divslot    = 1,
2285                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2286                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2287                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2288                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2289                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2290                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2291                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2292                 .num_clks       = 2,
2293                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2294                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2295         },
2296         .def_cfg = &(struct s3c2410_uartcfg) {
2297                 .ucon           = S5PV210_UCON_DEFAULT,
2298                 .ufcon          = S5PV210_UFCON_DEFAULT,
2299         },
2300         .fifosize = { 256, 64, 16, 16 },
2301 };
2302 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2303 #else
2304 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2305 #endif
2306
2307 #if defined(CONFIG_ARCH_EXYNOS)
2308 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2309         .info = &(struct s3c24xx_uart_info) {                   \
2310                 .name           = "Samsung Exynos UART",        \
2311                 .type           = PORT_S3C6400,                 \
2312                 .has_divslot    = 1,                            \
2313                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2314                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2315                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2316                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2317                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2318                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2319                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2320                 .num_clks       = 1,                            \
2321                 .clksel_mask    = 0,                            \
2322                 .clksel_shift   = 0,                            \
2323         },                                                      \
2324         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2325                 .ucon           = S5PV210_UCON_DEFAULT,         \
2326                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2327                 .has_fracval    = 1,                            \
2328         }                                                       \
2329
2330 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2331         EXYNOS_COMMON_SERIAL_DRV_DATA,
2332         .fifosize = { 256, 64, 16, 16 },
2333 };
2334
2335 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2336         EXYNOS_COMMON_SERIAL_DRV_DATA,
2337         .fifosize = { 64, 256, 16, 256 },
2338 };
2339
2340 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2341 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2342 #else
2343 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2344 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2345 #endif
2346
2347 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2348         {
2349                 .name           = "s3c2410-uart",
2350                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2351         }, {
2352                 .name           = "s3c2412-uart",
2353                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2354         }, {
2355                 .name           = "s3c2440-uart",
2356                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2357         }, {
2358                 .name           = "s3c6400-uart",
2359                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2360         }, {
2361                 .name           = "s5pv210-uart",
2362                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2363         }, {
2364                 .name           = "exynos4210-uart",
2365                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2366         }, {
2367                 .name           = "exynos5433-uart",
2368                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2369         },
2370         { },
2371 };
2372 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2373
2374 #ifdef CONFIG_OF
2375 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2376         { .compatible = "samsung,s3c2410-uart",
2377                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2378         { .compatible = "samsung,s3c2412-uart",
2379                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2380         { .compatible = "samsung,s3c2440-uart",
2381                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2382         { .compatible = "samsung,s3c6400-uart",
2383                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2384         { .compatible = "samsung,s5pv210-uart",
2385                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2386         { .compatible = "samsung,exynos4210-uart",
2387                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2388         { .compatible = "samsung,exynos5433-uart",
2389                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2390         {},
2391 };
2392 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2393 #endif
2394
2395 static struct platform_driver samsung_serial_driver = {
2396         .probe          = s3c24xx_serial_probe,
2397         .remove         = s3c24xx_serial_remove,
2398         .id_table       = s3c24xx_serial_driver_ids,
2399         .driver         = {
2400                 .name   = "samsung-uart",
2401                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2402                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2403         },
2404 };
2405
2406 module_platform_driver(samsung_serial_driver);
2407
2408 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2409 /*
2410  * Early console.
2411  */
2412
2413 struct samsung_early_console_data {
2414         u32 txfull_mask;
2415 };
2416
2417 static void samsung_early_busyuart(struct uart_port *port)
2418 {
2419         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2420                 ;
2421 }
2422
2423 static void samsung_early_busyuart_fifo(struct uart_port *port)
2424 {
2425         struct samsung_early_console_data *data = port->private_data;
2426
2427         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2428                 ;
2429 }
2430
2431 static void samsung_early_putc(struct uart_port *port, int c)
2432 {
2433         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2434                 samsung_early_busyuart_fifo(port);
2435         else
2436                 samsung_early_busyuart(port);
2437
2438         writeb(c, port->membase + S3C2410_UTXH);
2439 }
2440
2441 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2442 {
2443         struct earlycon_device *dev = con->data;
2444
2445         uart_console_write(&dev->port, s, n, samsung_early_putc);
2446 }
2447
2448 static int __init samsung_early_console_setup(struct earlycon_device *device,
2449                                               const char *opt)
2450 {
2451         if (!device->port.membase)
2452                 return -ENODEV;
2453
2454         device->con->write = samsung_early_write;
2455         return 0;
2456 }
2457
2458 /* S3C2410 */
2459 static struct samsung_early_console_data s3c2410_early_console_data = {
2460         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2461 };
2462
2463 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2464                                               const char *opt)
2465 {
2466         device->port.private_data = &s3c2410_early_console_data;
2467         return samsung_early_console_setup(device, opt);
2468 }
2469 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2470                         s3c2410_early_console_setup);
2471
2472 /* S3C2412, S3C2440, S3C64xx */
2473 static struct samsung_early_console_data s3c2440_early_console_data = {
2474         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2475 };
2476
2477 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2478                                               const char *opt)
2479 {
2480         device->port.private_data = &s3c2440_early_console_data;
2481         return samsung_early_console_setup(device, opt);
2482 }
2483 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2484                         s3c2440_early_console_setup);
2485 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2486                         s3c2440_early_console_setup);
2487 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2488                         s3c2440_early_console_setup);
2489
2490 /* S5PV210, EXYNOS */
2491 static struct samsung_early_console_data s5pv210_early_console_data = {
2492         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2493 };
2494
2495 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2496                                               const char *opt)
2497 {
2498         device->port.private_data = &s5pv210_early_console_data;
2499         return samsung_early_console_setup(device, opt);
2500 }
2501 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2502                         s5pv210_early_console_setup);
2503 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2504                         s5pv210_early_console_setup);
2505 #endif
2506
2507 MODULE_ALIAS("platform:samsung-uart");
2508 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2509 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2510 MODULE_LICENSE("GPL v2");