drivers/tty/serial/samsung.c

   1 /*
   2  * Driver core for Samsung SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /* Hote on 2410 error handling
  13  *
  14  * The s3c2410 manual has a love/hate affair with the contents of the
  15  * UERSTAT register in the UART blocks, and keeps marking some of the
  16  * error bits as reserved. Having checked with the s3c2410x01,
  17  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  18  * feature from the latter versions of the manual.
  19  *
  20  * If it becomes aparrent that latter versions of the 2410 remove these
  21  * bits, then action will have to be taken to differentiate the versions
  22  * and change the policy on BREAK
  23  *
  24  * BJD, 04-Nov-2004
  25 */
  26
  27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28 #define SUPPORT_SYSRQ
  29 #endif
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/ioport.h>
  36 #include <linux/io.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/init.h>
  39 #include <linux/sysrq.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42 #include <linux/tty_flip.h>
  43 #include <linux/serial_core.h>
  44 #include <linux/serial.h>
  45 #include <linux/serial_s3c.h>
  46 #include <linux/delay.h>
  47 #include <linux/clk.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/of.h>
  50
  51 #include <asm/irq.h>
  52
  53 #include "samsung.h"
  54
  55 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  56         !defined(MODULE)
  57
  58 extern void printascii(const char *);
  59
  60 __printf(1, 2)
  61 static void dbg(const char *fmt, ...)
  62 {
  63         va_list va;
  64         char buff[256];
  65
  66         va_start(va, fmt);
  67         vscnprintf(buff, sizeof(buff), fmt, va);
  68         va_end(va);
  69
  70         printascii(buff);
  71 }
  72
  73 #else
  74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  75 #endif
  76
  77 /* UART name and device definitions */
  78
  79 #define S3C24XX_SERIAL_NAME     "ttySAC"
  80 #define S3C24XX_SERIAL_MAJOR    204
  81 #define S3C24XX_SERIAL_MINOR    64
  82
  83 #define S3C24XX_TX_PIO                  1
  84 #define S3C24XX_TX_DMA                  2
  85 #define S3C24XX_RX_PIO                  1
  86 #define S3C24XX_RX_DMA                  2
  87 /* macros to change one thing to another */
  88
  89 #define tx_enabled(port) ((port)->unused[0])
  90 #define rx_enabled(port) ((port)->unused[1])
  91
  92 /* flag to ignore all characters coming in */
  93 #define RXSTAT_DUMMY_READ (0x10000000)
  94
  95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  96 {
  97         return container_of(port, struct s3c24xx_uart_port, port);
  98 }
  99
 100 /* translate a port to the device name */
 101
 102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 103 {
 104         return to_platform_device(port->dev)->name;
 105 }
 106
 107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 108 {
 109         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 110 }
 111
 112 /*
 113  * s3c64xx and later SoC's include the interrupt mask and status registers in
 114  * the controller itself, unlike the s3c24xx SoC's which have these registers
 115  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 116  */
 117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 118 {
 119         return to_ourport(port)->info->type == PORT_S3C6400;
 120 }
 121
 122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 123 {
 124         unsigned long flags;
 125         unsigned int ucon, ufcon;
 126         int count = 10000;
 127
 128         spin_lock_irqsave(&port->lock, flags);
 129
 130         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 131                 udelay(100);
 132
 133         ufcon = rd_regl(port, S3C2410_UFCON);
 134         ufcon |= S3C2410_UFCON_RESETRX;
 135         wr_regl(port, S3C2410_UFCON, ufcon);
 136
 137         ucon = rd_regl(port, S3C2410_UCON);
 138         ucon |= S3C2410_UCON_RXIRQMODE;
 139         wr_regl(port, S3C2410_UCON, ucon);
 140
 141         rx_enabled(port) = 1;
 142         spin_unlock_irqrestore(&port->lock, flags);
 143 }
 144
 145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 146 {
 147         unsigned long flags;
 148         unsigned int ucon;
 149
 150         spin_lock_irqsave(&port->lock, flags);
 151
 152         ucon = rd_regl(port, S3C2410_UCON);
 153         ucon &= ~S3C2410_UCON_RXIRQMODE;
 154         wr_regl(port, S3C2410_UCON, ucon);
 155
 156         rx_enabled(port) = 0;
 157         spin_unlock_irqrestore(&port->lock, flags);
 158 }
 159
 160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 161 {
 162         struct s3c24xx_uart_port *ourport = to_ourport(port);
 163         struct s3c24xx_uart_dma *dma = ourport->dma;
 164         struct circ_buf *xmit = &port->state->xmit;
 165         struct dma_tx_state state;
 166         int count;
 167
 168         if (!tx_enabled(port))
 169                 return;
 170
 171         if (s3c24xx_serial_has_interrupt_mask(port))
 172                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 173         else
 174                 disable_irq_nosync(ourport->tx_irq);
 175
 176         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 177                 dmaengine_pause(dma->tx_chan);
 178                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 179                 dmaengine_terminate_all(dma->tx_chan);
 180                 dma_sync_single_for_cpu(ourport->port.dev,
 181                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 182                 async_tx_ack(dma->tx_desc);
 183                 count = dma->tx_bytes_requested - state.residue;
 184                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 185                 port->icount.tx += count;
 186         }
 187
 188         tx_enabled(port) = 0;
 189         ourport->tx_in_progress = 0;
 190
 191         if (port->flags & UPF_CONS_FLOW)
 192                 s3c24xx_serial_rx_enable(port);
 193
 194         ourport->tx_mode = 0;
 195 }
 196
 197 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 198
 199 static void s3c24xx_serial_tx_dma_complete(void *args)
 200 {
 201         struct s3c24xx_uart_port *ourport = args;
 202         struct uart_port *port = &ourport->port;
 203         struct circ_buf *xmit = &port->state->xmit;
 204         struct s3c24xx_uart_dma *dma = ourport->dma;
 205         struct dma_tx_state state;
 206         unsigned long flags;
 207         int count;
 208
 209
 210         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 211         count = dma->tx_bytes_requested - state.residue;
 212         async_tx_ack(dma->tx_desc);
 213
 214         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 215                                 dma->tx_size, DMA_TO_DEVICE);
 216
 217         spin_lock_irqsave(&port->lock, flags);
 218
 219         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 220         port->icount.tx += count;
 221         ourport->tx_in_progress = 0;
 222
 223         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 224                 uart_write_wakeup(port);
 225
 226         s3c24xx_serial_start_next_tx(ourport);
 227         spin_unlock_irqrestore(&port->lock, flags);
 228 }
 229
 230 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 231 {
 232         struct uart_port *port = &ourport->port;
 233         u32 ucon;
 234
 235         /* Mask Tx interrupt */
 236         if (s3c24xx_serial_has_interrupt_mask(port))
 237                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 238         else
 239                 disable_irq_nosync(ourport->tx_irq);
 240
 241         /* Enable tx dma mode */
 242         ucon = rd_regl(port, S3C2410_UCON);
 243         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 244         ucon |= S3C64XX_UCON_TXBURST_1;
 245         ucon |= S3C64XX_UCON_TXMODE_DMA;
 246         wr_regl(port,  S3C2410_UCON, ucon);
 247
 248         ourport->tx_mode = S3C24XX_TX_DMA;
 249 }
 250
 251 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 252 {
 253         struct uart_port *port = &ourport->port;
 254         u32 ucon, ufcon;
 255
 256         /* Set ufcon txtrig */
 257         ourport->tx_in_progress = S3C24XX_TX_PIO;
 258         ufcon = rd_regl(port, S3C2410_UFCON);
 259         wr_regl(port,  S3C2410_UFCON, ufcon);
 260
 261         /* Enable tx pio mode */
 262         ucon = rd_regl(port, S3C2410_UCON);
 263         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 264         ucon |= S3C64XX_UCON_TXMODE_CPU;
 265         wr_regl(port,  S3C2410_UCON, ucon);
 266
 267         /* Unmask Tx interrupt */
 268         if (s3c24xx_serial_has_interrupt_mask(port))
 269                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 270                                   S3C64XX_UINTM);
 271         else
 272                 enable_irq(ourport->tx_irq);
 273
 274         ourport->tx_mode = S3C24XX_TX_PIO;
 275 }
 276
 277 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 278 {
 279         if (ourport->tx_mode != S3C24XX_TX_PIO)
 280                 enable_tx_pio(ourport);
 281 }
 282
 283 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 284                                       unsigned int count)
 285 {
 286         struct uart_port *port = &ourport->port;
 287         struct circ_buf *xmit = &port->state->xmit;
 288         struct s3c24xx_uart_dma *dma = ourport->dma;
 289
 290
 291         if (ourport->tx_mode != S3C24XX_TX_DMA)
 292                 enable_tx_dma(ourport);
 293
 294         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 295         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 296
 297         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 298                                 dma->tx_size, DMA_TO_DEVICE);
 299
 300         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 301                                 dma->tx_transfer_addr, dma->tx_size,
 302                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 303         if (!dma->tx_desc) {
 304                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 305                 return -EIO;
 306         }
 307
 308         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 309         dma->tx_desc->callback_param = ourport;
 310         dma->tx_bytes_requested = dma->tx_size;
 311
 312         ourport->tx_in_progress = S3C24XX_TX_DMA;
 313         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 314         dma_async_issue_pending(dma->tx_chan);
 315         return 0;
 316 }
 317
 318 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 319 {
 320         struct uart_port *port = &ourport->port;
 321         struct circ_buf *xmit = &port->state->xmit;
 322         unsigned long count;
 323
 324         /* Get data size up to the end of buffer */
 325         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 326
 327         if (!count) {
 328                 s3c24xx_serial_stop_tx(port);
 329                 return;
 330         }
 331
 332         if (!ourport->dma || !ourport->dma->tx_chan ||
 333             count < ourport->min_dma_size ||
 334             xmit->tail & (dma_get_cache_alignment() - 1))
 335                 s3c24xx_serial_start_tx_pio(ourport);
 336         else
 337                 s3c24xx_serial_start_tx_dma(ourport, count);
 338 }
 339
 340 static void s3c24xx_serial_start_tx(struct uart_port *port)
 341 {
 342         struct s3c24xx_uart_port *ourport = to_ourport(port);
 343         struct circ_buf *xmit = &port->state->xmit;
 344
 345         if (!tx_enabled(port)) {
 346                 if (port->flags & UPF_CONS_FLOW)
 347                         s3c24xx_serial_rx_disable(port);
 348
 349                 tx_enabled(port) = 1;
 350                 if (!ourport->dma || !ourport->dma->tx_chan)
 351                         s3c24xx_serial_start_tx_pio(ourport);
 352         }
 353
 354         if (ourport->dma && ourport->dma->tx_chan) {
 355                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 356                         s3c24xx_serial_start_next_tx(ourport);
 357         }
 358 }
 359
 360 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 361                 struct tty_port *tty, int count)
 362 {
 363         struct s3c24xx_uart_dma *dma = ourport->dma;
 364         int copied;
 365
 366         if (!count)
 367                 return;
 368
 369         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 370                                 dma->rx_size, DMA_FROM_DEVICE);
 371
 372         ourport->port.icount.rx += count;
 373         if (!tty) {
 374                 dev_err(ourport->port.dev, "No tty port\n");
 375                 return;
 376         }
 377         copied = tty_insert_flip_string(tty,
 378                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 379         if (copied != count) {
 380                 WARN_ON(1);
 381                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 382         }
 383 }
 384
 385 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 386 {
 387         struct s3c24xx_uart_port *ourport = to_ourport(port);
 388         struct s3c24xx_uart_dma *dma = ourport->dma;
 389         struct tty_port *t = &port->state->port;
 390         struct dma_tx_state state;
 391         enum dma_status dma_status;
 392         unsigned int received;
 393
 394         if (rx_enabled(port)) {
 395                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 396                 if (s3c24xx_serial_has_interrupt_mask(port))
 397                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 398                                         S3C64XX_UINTM);
 399                 else
 400                         disable_irq_nosync(ourport->rx_irq);
 401                 rx_enabled(port) = 0;
 402         }
 403         if (dma && dma->rx_chan) {
 404                 dmaengine_pause(dma->tx_chan);
 405                 dma_status = dmaengine_tx_status(dma->rx_chan,
 406                                 dma->rx_cookie, &state);
 407                 if (dma_status == DMA_IN_PROGRESS ||
 408                         dma_status == DMA_PAUSED) {
 409                         received = dma->rx_bytes_requested - state.residue;
 410                         dmaengine_terminate_all(dma->rx_chan);
 411                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 412                 }
 413         }
 414 }
 415
 416 static inline struct s3c24xx_uart_info
 417         *s3c24xx_port_to_info(struct uart_port *port)
 418 {
 419         return to_ourport(port)->info;
 420 }
 421
 422 static inline struct s3c2410_uartcfg
 423         *s3c24xx_port_to_cfg(struct uart_port *port)
 424 {
 425         struct s3c24xx_uart_port *ourport;
 426
 427         if (port->dev == NULL)
 428                 return NULL;
 429
 430         ourport = container_of(port, struct s3c24xx_uart_port, port);
 431         return ourport->cfg;
 432 }
 433
 434 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 435                                      unsigned long ufstat)
 436 {
 437         struct s3c24xx_uart_info *info = ourport->info;
 438
 439         if (ufstat & info->rx_fifofull)
 440                 return ourport->port.fifosize;
 441
 442         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 443 }
 444
 445 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 446 static void s3c24xx_serial_rx_dma_complete(void *args)
 447 {
 448         struct s3c24xx_uart_port *ourport = args;
 449         struct uart_port *port = &ourport->port;
 450
 451         struct s3c24xx_uart_dma *dma = ourport->dma;
 452         struct tty_port *t = &port->state->port;
 453         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 454
 455         struct dma_tx_state state;
 456         unsigned long flags;
 457         int received;
 458
 459         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 460         received  = dma->rx_bytes_requested - state.residue;
 461         async_tx_ack(dma->rx_desc);
 462
 463         spin_lock_irqsave(&port->lock, flags);
 464
 465         if (received)
 466                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 467
 468         if (tty) {
 469                 tty_flip_buffer_push(t);
 470                 tty_kref_put(tty);
 471         }
 472
 473         s3c64xx_start_rx_dma(ourport);
 474
 475         spin_unlock_irqrestore(&port->lock, flags);
 476 }
 477
 478 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 479 {
 480         struct s3c24xx_uart_dma *dma = ourport->dma;
 481
 482         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 483                                 dma->rx_size, DMA_FROM_DEVICE);
 484
 485         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 486                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 487                                 DMA_PREP_INTERRUPT);
 488         if (!dma->rx_desc) {
 489                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 490                 return;
 491         }
 492
 493         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 494         dma->rx_desc->callback_param = ourport;
 495         dma->rx_bytes_requested = dma->rx_size;
 496
 497         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 498         dma_async_issue_pending(dma->rx_chan);
 499 }
 500
 501 /* ? - where has parity gone?? */
 502 #define S3C2410_UERSTAT_PARITY (0x1000)
 503
 504 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 505 {
 506         struct uart_port *port = &ourport->port;
 507         unsigned int ucon;
 508
 509         /* set Rx mode to DMA mode */
 510         ucon = rd_regl(port, S3C2410_UCON);
 511         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 512                         S3C64XX_UCON_TIMEOUT_MASK |
 513                         S3C64XX_UCON_EMPTYINT_EN |
 514                         S3C64XX_UCON_DMASUS_EN |
 515                         S3C64XX_UCON_TIMEOUT_EN |
 516                         S3C64XX_UCON_RXMODE_MASK);
 517         ucon |= S3C64XX_UCON_RXBURST_1 |
 518                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 519                         S3C64XX_UCON_EMPTYINT_EN |
 520                         S3C64XX_UCON_TIMEOUT_EN |
 521                         S3C64XX_UCON_RXMODE_DMA;
 522         wr_regl(port, S3C2410_UCON, ucon);
 523
 524         ourport->rx_mode = S3C24XX_RX_DMA;
 525 }
 526
 527 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 528 {
 529         struct uart_port *port = &ourport->port;
 530         unsigned int ucon;
 531
 532         /* set Rx mode to DMA mode */
 533         ucon = rd_regl(port, S3C2410_UCON);
 534         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 535                         S3C64XX_UCON_EMPTYINT_EN |
 536                         S3C64XX_UCON_DMASUS_EN |
 537                         S3C64XX_UCON_TIMEOUT_EN |
 538                         S3C64XX_UCON_RXMODE_MASK);
 539         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 540                         S3C64XX_UCON_TIMEOUT_EN |
 541                         S3C64XX_UCON_RXMODE_CPU;
 542         wr_regl(port, S3C2410_UCON, ucon);
 543
 544         ourport->rx_mode = S3C24XX_RX_PIO;
 545 }
 546
 547 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 548
 549 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 550 {
 551         unsigned int utrstat, ufstat, received;
 552         struct s3c24xx_uart_port *ourport = dev_id;
 553         struct uart_port *port = &ourport->port;
 554         struct s3c24xx_uart_dma *dma = ourport->dma;
 555         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 556         struct tty_port *t = &port->state->port;
 557         unsigned long flags;
 558         struct dma_tx_state state;
 559
 560         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 561         ufstat = rd_regl(port, S3C2410_UFSTAT);
 562
 563         spin_lock_irqsave(&port->lock, flags);
 564
 565         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 566                 s3c64xx_start_rx_dma(ourport);
 567                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 568                         enable_rx_dma(ourport);
 569                 goto finish;
 570         }
 571
 572         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 573                 dmaengine_pause(dma->rx_chan);
 574                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 575                 dmaengine_terminate_all(dma->rx_chan);
 576                 received = dma->rx_bytes_requested - state.residue;
 577                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 578
 579                 enable_rx_pio(ourport);
 580         }
 581
 582         s3c24xx_serial_rx_drain_fifo(ourport);
 583
 584         if (tty) {
 585                 tty_flip_buffer_push(t);
 586                 tty_kref_put(tty);
 587         }
 588
 589         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 590
 591 finish:
 592         spin_unlock_irqrestore(&port->lock, flags);
 593
 594         return IRQ_HANDLED;
 595 }
 596
 597 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 598 {
 599         struct uart_port *port = &ourport->port;
 600         unsigned int ufcon, ch, flag, ufstat, uerstat;
 601         unsigned int fifocnt = 0;
 602         int max_count = port->fifosize;
 603
 604         while (max_count-- > 0) {
 605                 /*
 606                  * Receive all characters known to be in FIFO
 607                  * before reading FIFO level again
 608                  */
 609                 if (fifocnt == 0) {
 610                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 611                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 612                         if (fifocnt == 0)
 613                                 break;
 614                 }
 615                 fifocnt--;
 616
 617                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 618                 ch = rd_regb(port, S3C2410_URXH);
 619
 620                 if (port->flags & UPF_CONS_FLOW) {
 621                         int txe = s3c24xx_serial_txempty_nofifo(port);
 622
 623                         if (rx_enabled(port)) {
 624                                 if (!txe) {
 625                                         rx_enabled(port) = 0;
 626                                         continue;
 627                                 }
 628                         } else {
 629                                 if (txe) {
 630                                         ufcon = rd_regl(port, S3C2410_UFCON);
 631                                         ufcon |= S3C2410_UFCON_RESETRX;
 632                                         wr_regl(port, S3C2410_UFCON, ufcon);
 633                                         rx_enabled(port) = 1;
 634                                         return;
 635                                 }
 636                                 continue;
 637                         }
 638                 }
 639
 640                 /* insert the character into the buffer */
 641
 642                 flag = TTY_NORMAL;
 643                 port->icount.rx++;
 644
 645                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 646                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 647                             ch, uerstat);
 648
 649                         /* check for break */
 650                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 651                                 dbg("break!\n");
 652                                 port->icount.brk++;
 653                                 if (uart_handle_break(port))
 654                                         continue; /* Ignore character */
 655                         }
 656
 657                         if (uerstat & S3C2410_UERSTAT_FRAME)
 658                                 port->icount.frame++;
 659                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 660                                 port->icount.overrun++;
 661
 662                         uerstat &= port->read_status_mask;
 663
 664                         if (uerstat & S3C2410_UERSTAT_BREAK)
 665                                 flag = TTY_BREAK;
 666                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 667                                 flag = TTY_PARITY;
 668                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 669                                             S3C2410_UERSTAT_OVERRUN))
 670                                 flag = TTY_FRAME;
 671                 }
 672
 673                 if (uart_handle_sysrq_char(port, ch))
 674                         continue; /* Ignore character */
 675
 676                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 677                                  ch, flag);
 678         }
 679
 680         tty_flip_buffer_push(&port->state->port);
 681 }
 682
 683 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 684 {
 685         struct s3c24xx_uart_port *ourport = dev_id;
 686         struct uart_port *port = &ourport->port;
 687         unsigned long flags;
 688
 689         spin_lock_irqsave(&port->lock, flags);
 690         s3c24xx_serial_rx_drain_fifo(ourport);
 691         spin_unlock_irqrestore(&port->lock, flags);
 692
 693         return IRQ_HANDLED;
 694 }
 695
 696
 697 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 698 {
 699         struct s3c24xx_uart_port *ourport = dev_id;
 700
 701         if (ourport->dma && ourport->dma->rx_chan)
 702                 return s3c24xx_serial_rx_chars_dma(dev_id);
 703         return s3c24xx_serial_rx_chars_pio(dev_id);
 704 }
 705
 706 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 707 {
 708         struct s3c24xx_uart_port *ourport = id;
 709         struct uart_port *port = &ourport->port;
 710         struct circ_buf *xmit = &port->state->xmit;
 711         unsigned long flags;
 712         int count, dma_count = 0;
 713
 714         spin_lock_irqsave(&port->lock, flags);
 715
 716         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 717
 718         if (ourport->dma && ourport->dma->tx_chan &&
 719             count >= ourport->min_dma_size) {
 720                 int align = dma_get_cache_alignment() -
 721                         (xmit->tail & (dma_get_cache_alignment() - 1));
 722                 if (count-align >= ourport->min_dma_size) {
 723                         dma_count = count-align;
 724                         count = align;
 725                 }
 726         }
 727
 728         if (port->x_char) {
 729                 wr_regb(port, S3C2410_UTXH, port->x_char);
 730                 port->icount.tx++;
 731                 port->x_char = 0;
 732                 goto out;
 733         }
 734
 735         /* if there isn't anything more to transmit, or the uart is now
 736          * stopped, disable the uart and exit
 737         */
 738
 739         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 740                 s3c24xx_serial_stop_tx(port);
 741                 goto out;
 742         }
 743
 744         /* try and drain the buffer... */
 745
 746         if (count > port->fifosize) {
 747                 count = port->fifosize;
 748                 dma_count = 0;
 749         }
 750
 751         while (!uart_circ_empty(xmit) && count > 0) {
 752                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 753                         break;
 754
 755                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 756                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 757                 port->icount.tx++;
 758                 count--;
 759         }
 760
 761         if (!count && dma_count) {
 762                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 763                 goto out;
 764         }
 765
 766         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 767                 uart_write_wakeup(port);
 768
 769         if (uart_circ_empty(xmit))
 770                 s3c24xx_serial_stop_tx(port);
 771
 772 out:
 773         spin_unlock_irqrestore(&port->lock, flags);
 774         return IRQ_HANDLED;
 775 }
 776
 777 /* interrupt handler for s3c64xx and later SoC's.*/
 778 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 779 {
 780         struct s3c24xx_uart_port *ourport = id;
 781         struct uart_port *port = &ourport->port;
 782         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 783         irqreturn_t ret = IRQ_HANDLED;
 784
 785         if (pend & S3C64XX_UINTM_RXD_MSK) {
 786                 ret = s3c24xx_serial_rx_chars(irq, id);
 787                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 788         }
 789         if (pend & S3C64XX_UINTM_TXD_MSK) {
 790                 ret = s3c24xx_serial_tx_chars(irq, id);
 791                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 792         }
 793         return ret;
 794 }
 795
 796 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 797 {
 798         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 799         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 800         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 801
 802         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 803                 if ((ufstat & info->tx_fifomask) != 0 ||
 804                     (ufstat & info->tx_fifofull))
 805                         return 0;
 806
 807                 return 1;
 808         }
 809
 810         return s3c24xx_serial_txempty_nofifo(port);
 811 }
 812
 813 /* no modem control lines */
 814 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 815 {
 816         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 817
 818         if (umstat & S3C2410_UMSTAT_CTS)
 819                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 820         else
 821                 return TIOCM_CAR | TIOCM_DSR;
 822 }
 823
 824 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 825 {
 826         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 827
 828         if (mctrl & TIOCM_RTS)
 829                 umcon |= S3C2410_UMCOM_RTS_LOW;
 830         else
 831                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 832
 833         wr_regl(port, S3C2410_UMCON, umcon);
 834 }
 835
 836 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 837 {
 838         unsigned long flags;
 839         unsigned int ucon;
 840
 841         spin_lock_irqsave(&port->lock, flags);
 842
 843         ucon = rd_regl(port, S3C2410_UCON);
 844
 845         if (break_state)
 846                 ucon |= S3C2410_UCON_SBREAK;
 847         else
 848                 ucon &= ~S3C2410_UCON_SBREAK;
 849
 850         wr_regl(port, S3C2410_UCON, ucon);
 851
 852         spin_unlock_irqrestore(&port->lock, flags);
 853 }
 854
 855 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 856 {
 857         struct s3c24xx_uart_dma *dma = p->dma;
 858         int ret;
 859
 860         /* Default slave configuration parameters */
 861         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 862         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 863         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 864         dma->rx_conf.src_maxburst       = 1;
 865
 866         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 867         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 868         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 869         dma->tx_conf.dst_maxburst       = 1;
 870
 871         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 872
 873         if (IS_ERR(dma->rx_chan))
 874                 return PTR_ERR(dma->rx_chan);
 875
 876         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 877
 878         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
 879         if (IS_ERR(dma->tx_chan)) {
 880                 ret = PTR_ERR(dma->tx_chan);
 881                 goto err_release_rx;
 882         }
 883
 884         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 885
 886         /* RX buffer */
 887         dma->rx_size = PAGE_SIZE;
 888
 889         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 890         if (!dma->rx_buf) {
 891                 ret = -ENOMEM;
 892                 goto err_release_tx;
 893         }
 894
 895         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
 896                                 dma->rx_size, DMA_FROM_DEVICE);
 897         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
 898                 ret = -EIO;
 899                 goto err_free_rx;
 900         }
 901
 902         /* TX buffer */
 903         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
 904                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 905         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
 906                 ret = -EIO;
 907                 goto err_unmap_rx;
 908         }
 909
 910         return 0;
 911
 912 err_unmap_rx:
 913         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
 914                          DMA_FROM_DEVICE);
 915 err_free_rx:
 916         kfree(dma->rx_buf);
 917 err_release_tx:
 918         dma_release_channel(dma->tx_chan);
 919 err_release_rx:
 920         dma_release_channel(dma->rx_chan);
 921         return ret;
 922 }
 923
 924 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 925 {
 926         struct s3c24xx_uart_dma *dma = p->dma;
 927
 928         if (dma->rx_chan) {
 929                 dmaengine_terminate_all(dma->rx_chan);
 930                 dma_unmap_single(p->port.dev, dma->rx_addr,
 931                                 dma->rx_size, DMA_FROM_DEVICE);
 932                 kfree(dma->rx_buf);
 933                 dma_release_channel(dma->rx_chan);
 934                 dma->rx_chan = NULL;
 935         }
 936
 937         if (dma->tx_chan) {
 938                 dmaengine_terminate_all(dma->tx_chan);
 939                 dma_unmap_single(p->port.dev, dma->tx_addr,
 940                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 941                 dma_release_channel(dma->tx_chan);
 942                 dma->tx_chan = NULL;
 943         }
 944 }
 945
 946 static void s3c24xx_serial_shutdown(struct uart_port *port)
 947 {
 948         struct s3c24xx_uart_port *ourport = to_ourport(port);
 949
 950         if (ourport->tx_claimed) {
 951                 if (!s3c24xx_serial_has_interrupt_mask(port))
 952                         free_irq(ourport->tx_irq, ourport);
 953                 tx_enabled(port) = 0;
 954                 ourport->tx_claimed = 0;
 955                 ourport->tx_mode = 0;
 956         }
 957
 958         if (ourport->rx_claimed) {
 959                 if (!s3c24xx_serial_has_interrupt_mask(port))
 960                         free_irq(ourport->rx_irq, ourport);
 961                 ourport->rx_claimed = 0;
 962                 rx_enabled(port) = 0;
 963         }
 964
 965         /* Clear pending interrupts and mask all interrupts */
 966         if (s3c24xx_serial_has_interrupt_mask(port)) {
 967                 free_irq(port->irq, ourport);
 968
 969                 wr_regl(port, S3C64XX_UINTP, 0xf);
 970                 wr_regl(port, S3C64XX_UINTM, 0xf);
 971         }
 972
 973         if (ourport->dma)
 974                 s3c24xx_serial_release_dma(ourport);
 975
 976         ourport->tx_in_progress = 0;
 977 }
 978
 979 static int s3c24xx_serial_startup(struct uart_port *port)
 980 {
 981         struct s3c24xx_uart_port *ourport = to_ourport(port);
 982         int ret;
 983
 984         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
 985             port, (unsigned long long)port->mapbase, port->membase);
 986
 987         rx_enabled(port) = 1;
 988
 989         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
 990                           s3c24xx_serial_portname(port), ourport);
 991
 992         if (ret != 0) {
 993                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
 994                 return ret;
 995         }
 996
 997         ourport->rx_claimed = 1;
 998
 999         dbg("requesting tx irq...\n");
1000
1001         tx_enabled(port) = 1;
1002
1003         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1004                           s3c24xx_serial_portname(port), ourport);
1005
1006         if (ret) {
1007                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1008                 goto err;
1009         }
1010
1011         ourport->tx_claimed = 1;
1012
1013         dbg("s3c24xx_serial_startup ok\n");
1014
1015         /* the port reset code should have done the correct
1016          * register setup for the port controls */
1017
1018         return ret;
1019
1020 err:
1021         s3c24xx_serial_shutdown(port);
1022         return ret;
1023 }
1024
1025 static int s3c64xx_serial_startup(struct uart_port *port)
1026 {
1027         struct s3c24xx_uart_port *ourport = to_ourport(port);
1028         unsigned long flags;
1029         unsigned int ufcon;
1030         int ret;
1031
1032         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1033             port, (unsigned long long)port->mapbase, port->membase);
1034
1035         wr_regl(port, S3C64XX_UINTM, 0xf);
1036         if (ourport->dma) {
1037                 ret = s3c24xx_serial_request_dma(ourport);
1038                 if (ret < 0) {
1039                         dev_warn(port->dev,
1040                                  "DMA request failed, DMA will not be used\n");
1041                         devm_kfree(port->dev, ourport->dma);
1042                         ourport->dma = NULL;
1043                 }
1044         }
1045
1046         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1047                           s3c24xx_serial_portname(port), ourport);
1048         if (ret) {
1049                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1050                 return ret;
1051         }
1052
1053         /* For compatibility with s3c24xx Soc's */
1054         rx_enabled(port) = 1;
1055         ourport->rx_claimed = 1;
1056         tx_enabled(port) = 0;
1057         ourport->tx_claimed = 1;
1058
1059         spin_lock_irqsave(&port->lock, flags);
1060
1061         ufcon = rd_regl(port, S3C2410_UFCON);
1062         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1063         if (!uart_console(port))
1064                 ufcon |= S3C2410_UFCON_RESETTX;
1065         wr_regl(port, S3C2410_UFCON, ufcon);
1066
1067         enable_rx_pio(ourport);
1068
1069         spin_unlock_irqrestore(&port->lock, flags);
1070
1071         /* Enable Rx Interrupt */
1072         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1073
1074         dbg("s3c64xx_serial_startup ok\n");
1075         return ret;
1076 }
1077
1078 /* power power management control */
1079
1080 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1081                               unsigned int old)
1082 {
1083         struct s3c24xx_uart_port *ourport = to_ourport(port);
1084         int timeout = 10000;
1085
1086         ourport->pm_level = level;
1087
1088         switch (level) {
1089         case 3:
1090                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1091                         udelay(100);
1092
1093                 if (!IS_ERR(ourport->baudclk))
1094                         clk_disable_unprepare(ourport->baudclk);
1095
1096                 clk_disable_unprepare(ourport->clk);
1097                 break;
1098
1099         case 0:
1100                 clk_prepare_enable(ourport->clk);
1101
1102                 if (!IS_ERR(ourport->baudclk))
1103                         clk_prepare_enable(ourport->baudclk);
1104
1105                 break;
1106         default:
1107                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1108         }
1109 }
1110
1111 /* baud rate calculation
1112  *
1113  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1114  * of different sources, including the peripheral clock ("pclk") and an
1115  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1116  * with a programmable extra divisor.
1117  *
1118  * The following code goes through the clock sources, and calculates the
1119  * baud clocks (and the resultant actual baud rates) and then tries to
1120  * pick the closest one and select that.
1121  *
1122 */
1123
1124 #define MAX_CLK_NAME_LENGTH 15
1125
1126 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1127 {
1128         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1129         unsigned int ucon;
1130
1131         if (info->num_clks == 1)
1132                 return 0;
1133
1134         ucon = rd_regl(port, S3C2410_UCON);
1135         ucon &= info->clksel_mask;
1136         return ucon >> info->clksel_shift;
1137 }
1138
1139 static void s3c24xx_serial_setsource(struct uart_port *port,
1140                         unsigned int clk_sel)
1141 {
1142         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1143         unsigned int ucon;
1144
1145         if (info->num_clks == 1)
1146                 return;
1147
1148         ucon = rd_regl(port, S3C2410_UCON);
1149         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1150                 return;
1151
1152         ucon &= ~info->clksel_mask;
1153         ucon |= clk_sel << info->clksel_shift;
1154         wr_regl(port, S3C2410_UCON, ucon);
1155 }
1156
1157 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1158                         unsigned int req_baud, struct clk **best_clk,
1159                         unsigned int *clk_num)
1160 {
1161         struct s3c24xx_uart_info *info = ourport->info;
1162         struct clk *clk;
1163         unsigned long rate;
1164         unsigned int cnt, baud, quot, best_quot = 0;
1165         char clkname[MAX_CLK_NAME_LENGTH];
1166         int calc_deviation, deviation = (1 << 30) - 1;
1167
1168         for (cnt = 0; cnt < info->num_clks; cnt++) {
1169                 /* Keep selected clock if provided */
1170                 if (ourport->cfg->clk_sel &&
1171                         !(ourport->cfg->clk_sel & (1 << cnt)))
1172                         continue;
1173
1174                 sprintf(clkname, "clk_uart_baud%d", cnt);
1175                 clk = clk_get(ourport->port.dev, clkname);
1176                 if (IS_ERR(clk))
1177                         continue;
1178
1179                 rate = clk_get_rate(clk);
1180                 if (!rate) {
1181                         dev_err(ourport->port.dev,
1182                                 "Failed to get clock rate for %s.\n", clkname);
1183                         clk_put(clk);
1184                         continue;
1185                 }
1186
1187                 if (ourport->info->has_divslot) {
1188                         unsigned long div = rate / req_baud;
1189
1190                         /* The UDIVSLOT register on the newer UARTs allows us to
1191                          * get a divisor adjustment of 1/16th on the baud clock.
1192                          *
1193                          * We don't keep the UDIVSLOT value (the 16ths we
1194                          * calculated by not multiplying the baud by 16) as it
1195                          * is easy enough to recalculate.
1196                          */
1197
1198                         quot = div / 16;
1199                         baud = rate / div;
1200                 } else {
1201                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1202                         baud = rate / (quot * 16);
1203                 }
1204                 quot--;
1205
1206                 calc_deviation = req_baud - baud;
1207                 if (calc_deviation < 0)
1208                         calc_deviation = -calc_deviation;
1209
1210                 if (calc_deviation < deviation) {
1211                         /*
1212                          * If we find a better clk, release the previous one, if
1213                          * any.
1214                          */
1215                         if (!IS_ERR(*best_clk))
1216                                 clk_put(*best_clk);
1217                         *best_clk = clk;
1218                         best_quot = quot;
1219                         *clk_num = cnt;
1220                         deviation = calc_deviation;
1221                 } else {
1222                         clk_put(clk);
1223                 }
1224         }
1225
1226         return best_quot;
1227 }
1228
1229 /* udivslot_table[]
1230  *
1231  * This table takes the fractional value of the baud divisor and gives
1232  * the recommended setting for the UDIVSLOT register.
1233  */
1234 static u16 udivslot_table[16] = {
1235         [0] = 0x0000,
1236         [1] = 0x0080,
1237         [2] = 0x0808,
1238         [3] = 0x0888,
1239         [4] = 0x2222,
1240         [5] = 0x4924,
1241         [6] = 0x4A52,
1242         [7] = 0x54AA,
1243         [8] = 0x5555,
1244         [9] = 0xD555,
1245         [10] = 0xD5D5,
1246         [11] = 0xDDD5,
1247         [12] = 0xDDDD,
1248         [13] = 0xDFDD,
1249         [14] = 0xDFDF,
1250         [15] = 0xFFDF,
1251 };
1252
1253 static void s3c24xx_serial_set_termios(struct uart_port *port,
1254                                        struct ktermios *termios,
1255                                        struct ktermios *old)
1256 {
1257         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1258         struct s3c24xx_uart_port *ourport = to_ourport(port);
1259         struct clk *clk = ERR_PTR(-EINVAL);
1260         unsigned long flags;
1261         unsigned int baud, quot, clk_sel = 0;
1262         unsigned int ulcon;
1263         unsigned int umcon;
1264         unsigned int udivslot = 0;
1265
1266         /*
1267          * We don't support modem control lines.
1268          */
1269         termios->c_cflag &= ~(HUPCL | CMSPAR);
1270         termios->c_cflag |= CLOCAL;
1271
1272         /*
1273          * Ask the core to calculate the divisor for us.
1274          */
1275
1276         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1277         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1278         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1279                 quot = port->custom_divisor;
1280         if (IS_ERR(clk))
1281                 return;
1282
1283         /* check to see if we need  to change clock source */
1284
1285         if (ourport->baudclk != clk) {
1286                 clk_prepare_enable(clk);
1287
1288                 s3c24xx_serial_setsource(port, clk_sel);
1289
1290                 if (!IS_ERR(ourport->baudclk)) {
1291                         clk_disable_unprepare(ourport->baudclk);
1292                         ourport->baudclk = ERR_PTR(-EINVAL);
1293                 }
1294
1295                 ourport->baudclk = clk;
1296                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1297         }
1298
1299         if (ourport->info->has_divslot) {
1300                 unsigned int div = ourport->baudclk_rate / baud;
1301
1302                 if (cfg->has_fracval) {
1303                         udivslot = (div & 15);
1304                         dbg("fracval = %04x\n", udivslot);
1305                 } else {
1306                         udivslot = udivslot_table[div & 15];
1307                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1308                 }
1309         }
1310
1311         switch (termios->c_cflag & CSIZE) {
1312         case CS5:
1313                 dbg("config: 5bits/char\n");
1314                 ulcon = S3C2410_LCON_CS5;
1315                 break;
1316         case CS6:
1317                 dbg("config: 6bits/char\n");
1318                 ulcon = S3C2410_LCON_CS6;
1319                 break;
1320         case CS7:
1321                 dbg("config: 7bits/char\n");
1322                 ulcon = S3C2410_LCON_CS7;
1323                 break;
1324         case CS8:
1325         default:
1326                 dbg("config: 8bits/char\n");
1327                 ulcon = S3C2410_LCON_CS8;
1328                 break;
1329         }
1330
1331         /* preserve original lcon IR settings */
1332         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1333
1334         if (termios->c_cflag & CSTOPB)
1335                 ulcon |= S3C2410_LCON_STOPB;
1336
1337         if (termios->c_cflag & PARENB) {
1338                 if (termios->c_cflag & PARODD)
1339                         ulcon |= S3C2410_LCON_PODD;
1340                 else
1341                         ulcon |= S3C2410_LCON_PEVEN;
1342         } else {
1343                 ulcon |= S3C2410_LCON_PNONE;
1344         }
1345
1346         spin_lock_irqsave(&port->lock, flags);
1347
1348         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1349             ulcon, quot, udivslot);
1350
1351         wr_regl(port, S3C2410_ULCON, ulcon);
1352         wr_regl(port, S3C2410_UBRDIV, quot);
1353
1354         port->status &= ~UPSTAT_AUTOCTS;
1355
1356         umcon = rd_regl(port, S3C2410_UMCON);
1357         if (termios->c_cflag & CRTSCTS) {
1358                 umcon |= S3C2410_UMCOM_AFC;
1359                 /* Disable RTS when RX FIFO contains 63 bytes */
1360                 umcon &= ~S3C2412_UMCON_AFC_8;
1361                 port->status = UPSTAT_AUTOCTS;
1362         } else {
1363                 umcon &= ~S3C2410_UMCOM_AFC;
1364         }
1365         wr_regl(port, S3C2410_UMCON, umcon);
1366
1367         if (ourport->info->has_divslot)
1368                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1369
1370         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1371             rd_regl(port, S3C2410_ULCON),
1372             rd_regl(port, S3C2410_UCON),
1373             rd_regl(port, S3C2410_UFCON));
1374
1375         /*
1376          * Update the per-port timeout.
1377          */
1378         uart_update_timeout(port, termios->c_cflag, baud);
1379
1380         /*
1381          * Which character status flags are we interested in?
1382          */
1383         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1384         if (termios->c_iflag & INPCK)
1385                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1386                         S3C2410_UERSTAT_PARITY;
1387         /*
1388          * Which character status flags should we ignore?
1389          */
1390         port->ignore_status_mask = 0;
1391         if (termios->c_iflag & IGNPAR)
1392                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1393         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1394                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1395
1396         /*
1397          * Ignore all characters if CREAD is not set.
1398          */
1399         if ((termios->c_cflag & CREAD) == 0)
1400                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1401
1402         spin_unlock_irqrestore(&port->lock, flags);
1403 }
1404
1405 static const char *s3c24xx_serial_type(struct uart_port *port)
1406 {
1407         switch (port->type) {
1408         case PORT_S3C2410:
1409                 return "S3C2410";
1410         case PORT_S3C2440:
1411                 return "S3C2440";
1412         case PORT_S3C2412:
1413                 return "S3C2412";
1414         case PORT_S3C6400:
1415                 return "S3C6400/10";
1416         default:
1417                 return NULL;
1418         }
1419 }
1420
1421 #define MAP_SIZE (0x100)
1422
1423 static void s3c24xx_serial_release_port(struct uart_port *port)
1424 {
1425         release_mem_region(port->mapbase, MAP_SIZE);
1426 }
1427
1428 static int s3c24xx_serial_request_port(struct uart_port *port)
1429 {
1430         const char *name = s3c24xx_serial_portname(port);
1431         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1432 }
1433
1434 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1435 {
1436         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1437
1438         if (flags & UART_CONFIG_TYPE &&
1439             s3c24xx_serial_request_port(port) == 0)
1440                 port->type = info->type;
1441 }
1442
1443 /*
1444  * verify the new serial_struct (for TIOCSSERIAL).
1445  */
1446 static int
1447 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1448 {
1449         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1450
1451         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1452                 return -EINVAL;
1453
1454         return 0;
1455 }
1456
1457
1458 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1459
1460 static struct console s3c24xx_serial_console;
1461
1462 static int __init s3c24xx_serial_console_init(void)
1463 {
1464         register_console(&s3c24xx_serial_console);
1465         return 0;
1466 }
1467 console_initcall(s3c24xx_serial_console_init);
1468
1469 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1470 #else
1471 #define S3C24XX_SERIAL_CONSOLE NULL
1472 #endif
1473
1474 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1475 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1476 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1477                          unsigned char c);
1478 #endif
1479
1480 static struct uart_ops s3c24xx_serial_ops = {
1481         .pm             = s3c24xx_serial_pm,
1482         .tx_empty       = s3c24xx_serial_tx_empty,
1483         .get_mctrl      = s3c24xx_serial_get_mctrl,
1484         .set_mctrl      = s3c24xx_serial_set_mctrl,
1485         .stop_tx        = s3c24xx_serial_stop_tx,
1486         .start_tx       = s3c24xx_serial_start_tx,
1487         .stop_rx        = s3c24xx_serial_stop_rx,
1488         .break_ctl      = s3c24xx_serial_break_ctl,
1489         .startup        = s3c24xx_serial_startup,
1490         .shutdown       = s3c24xx_serial_shutdown,
1491         .set_termios    = s3c24xx_serial_set_termios,
1492         .type           = s3c24xx_serial_type,
1493         .release_port   = s3c24xx_serial_release_port,
1494         .request_port   = s3c24xx_serial_request_port,
1495         .config_port    = s3c24xx_serial_config_port,
1496         .verify_port    = s3c24xx_serial_verify_port,
1497 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1498         .poll_get_char = s3c24xx_serial_get_poll_char,
1499         .poll_put_char = s3c24xx_serial_put_poll_char,
1500 #endif
1501 };
1502
1503 static struct uart_driver s3c24xx_uart_drv = {
1504         .owner          = THIS_MODULE,
1505         .driver_name    = "s3c2410_serial",
1506         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1507         .cons           = S3C24XX_SERIAL_CONSOLE,
1508         .dev_name       = S3C24XX_SERIAL_NAME,
1509         .major          = S3C24XX_SERIAL_MAJOR,
1510         .minor          = S3C24XX_SERIAL_MINOR,
1511 };
1512
1513 #define __PORT_LOCK_UNLOCKED(i) \
1514         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1515 static struct s3c24xx_uart_port
1516 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1517         [0] = {
1518                 .port = {
1519                         .lock           = __PORT_LOCK_UNLOCKED(0),
1520                         .iotype         = UPIO_MEM,
1521                         .uartclk        = 0,
1522                         .fifosize       = 16,
1523                         .ops            = &s3c24xx_serial_ops,
1524                         .flags          = UPF_BOOT_AUTOCONF,
1525                         .line           = 0,
1526                 }
1527         },
1528         [1] = {
1529                 .port = {
1530                         .lock           = __PORT_LOCK_UNLOCKED(1),
1531                         .iotype         = UPIO_MEM,
1532                         .uartclk        = 0,
1533                         .fifosize       = 16,
1534                         .ops            = &s3c24xx_serial_ops,
1535                         .flags          = UPF_BOOT_AUTOCONF,
1536                         .line           = 1,
1537                 }
1538         },
1539 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1540
1541         [2] = {
1542                 .port = {
1543                         .lock           = __PORT_LOCK_UNLOCKED(2),
1544                         .iotype         = UPIO_MEM,
1545                         .uartclk        = 0,
1546                         .fifosize       = 16,
1547                         .ops            = &s3c24xx_serial_ops,
1548                         .flags          = UPF_BOOT_AUTOCONF,
1549                         .line           = 2,
1550                 }
1551         },
1552 #endif
1553 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1554         [3] = {
1555                 .port = {
1556                         .lock           = __PORT_LOCK_UNLOCKED(3),
1557                         .iotype         = UPIO_MEM,
1558                         .uartclk        = 0,
1559                         .fifosize       = 16,
1560                         .ops            = &s3c24xx_serial_ops,
1561                         .flags          = UPF_BOOT_AUTOCONF,
1562                         .line           = 3,
1563                 }
1564         }
1565 #endif
1566 };
1567 #undef __PORT_LOCK_UNLOCKED
1568
1569 /* s3c24xx_serial_resetport
1570  *
1571  * reset the fifos and other the settings.
1572 */
1573
1574 static void s3c24xx_serial_resetport(struct uart_port *port,
1575                                    struct s3c2410_uartcfg *cfg)
1576 {
1577         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1578         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1579         unsigned int ucon_mask;
1580
1581         ucon_mask = info->clksel_mask;
1582         if (info->type == PORT_S3C2440)
1583                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1584
1585         ucon &= ucon_mask;
1586         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1587
1588         /* reset both fifos */
1589         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1590         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1591
1592         /* some delay is required after fifo reset */
1593         udelay(1);
1594 }
1595
1596
1597 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1598
1599 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1600                                              unsigned long val, void *data)
1601 {
1602         struct s3c24xx_uart_port *port;
1603         struct uart_port *uport;
1604
1605         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1606         uport = &port->port;
1607
1608         /* check to see if port is enabled */
1609
1610         if (port->pm_level != 0)
1611                 return 0;
1612
1613         /* try and work out if the baudrate is changing, we can detect
1614          * a change in rate, but we do not have support for detecting
1615          * a disturbance in the clock-rate over the change.
1616          */
1617
1618         if (IS_ERR(port->baudclk))
1619                 goto exit;
1620
1621         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1622                 goto exit;
1623
1624         if (val == CPUFREQ_PRECHANGE) {
1625                 /* we should really shut the port down whilst the
1626                  * frequency change is in progress. */
1627
1628         } else if (val == CPUFREQ_POSTCHANGE) {
1629                 struct ktermios *termios;
1630                 struct tty_struct *tty;
1631
1632                 if (uport->state == NULL)
1633                         goto exit;
1634
1635                 tty = uport->state->port.tty;
1636
1637                 if (tty == NULL)
1638                         goto exit;
1639
1640                 termios = &tty->termios;
1641
1642                 if (termios == NULL) {
1643                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1644                         goto exit;
1645                 }
1646
1647                 s3c24xx_serial_set_termios(uport, termios, NULL);
1648         }
1649
1650 exit:
1651         return 0;
1652 }
1653
1654 static inline int
1655 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1656 {
1657         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1658
1659         return cpufreq_register_notifier(&port->freq_transition,
1660                                          CPUFREQ_TRANSITION_NOTIFIER);
1661 }
1662
1663 static inline void
1664 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1665 {
1666         cpufreq_unregister_notifier(&port->freq_transition,
1667                                     CPUFREQ_TRANSITION_NOTIFIER);
1668 }
1669
1670 #else
1671 static inline int
1672 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1673 {
1674         return 0;
1675 }
1676
1677 static inline void
1678 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1679 {
1680 }
1681 #endif
1682
1683 /* s3c24xx_serial_init_port
1684  *
1685  * initialise a single serial port from the platform device given
1686  */
1687
1688 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1689                                     struct platform_device *platdev)
1690 {
1691         struct uart_port *port = &ourport->port;
1692         struct s3c2410_uartcfg *cfg = ourport->cfg;
1693         struct resource *res;
1694         int ret;
1695
1696         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1697
1698         if (platdev == NULL)
1699                 return -ENODEV;
1700
1701         if (port->mapbase != 0)
1702                 return -EINVAL;
1703
1704         /* setup info for port */
1705         port->dev       = &platdev->dev;
1706
1707         /* Startup sequence is different for s3c64xx and higher SoC's */
1708         if (s3c24xx_serial_has_interrupt_mask(port))
1709                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1710
1711         port->uartclk = 1;
1712
1713         if (cfg->uart_flags & UPF_CONS_FLOW) {
1714                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1715                 port->flags |= UPF_CONS_FLOW;
1716         }
1717
1718         /* sort our the physical and virtual addresses for each UART */
1719
1720         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1721         if (res == NULL) {
1722                 dev_err(port->dev, "failed to find memory resource for uart\n");
1723                 return -EINVAL;
1724         }
1725
1726         dbg("resource %pR)\n", res);
1727
1728         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1729         if (!port->membase) {
1730                 dev_err(port->dev, "failed to remap controller address\n");
1731                 return -EBUSY;
1732         }
1733
1734         port->mapbase = res->start;
1735         ret = platform_get_irq(platdev, 0);
1736         if (ret < 0)
1737                 port->irq = 0;
1738         else {
1739                 port->irq = ret;
1740                 ourport->rx_irq = ret;
1741                 ourport->tx_irq = ret + 1;
1742         }
1743
1744         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1745                 ret = platform_get_irq(platdev, 1);
1746                 if (ret > 0)
1747                         ourport->tx_irq = ret;
1748         }
1749         /*
1750          * DMA is currently supported only on DT platforms, if DMA properties
1751          * are specified.
1752          */
1753         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1754                                                      "dmas", NULL)) {
1755                 ourport->dma = devm_kzalloc(port->dev,
1756                                             sizeof(*ourport->dma),
1757                                             GFP_KERNEL);
1758                 if (!ourport->dma) {
1759                         ret = -ENOMEM;
1760                         goto err;
1761                 }
1762         }
1763
1764         ourport->clk    = clk_get(&platdev->dev, "uart");
1765         if (IS_ERR(ourport->clk)) {
1766                 pr_err("%s: Controller clock not found\n",
1767                                 dev_name(&platdev->dev));
1768                 ret = PTR_ERR(ourport->clk);
1769                 goto err;
1770         }
1771
1772         ret = clk_prepare_enable(ourport->clk);
1773         if (ret) {
1774                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1775                 clk_put(ourport->clk);
1776                 goto err;
1777         }
1778
1779         /* Keep all interrupts masked and cleared */
1780         if (s3c24xx_serial_has_interrupt_mask(port)) {
1781                 wr_regl(port, S3C64XX_UINTM, 0xf);
1782                 wr_regl(port, S3C64XX_UINTP, 0xf);
1783                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1784         }
1785
1786         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1787             &port->mapbase, port->membase, port->irq,
1788             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1789
1790         /* reset the fifos (and setup the uart) */
1791         s3c24xx_serial_resetport(port, cfg);
1792
1793         return 0;
1794
1795 err:
1796         port->mapbase = 0;
1797         return ret;
1798 }
1799
1800 /* Device driver serial port probe */
1801
1802 static const struct of_device_id s3c24xx_uart_dt_match[];
1803 static int probe_index;
1804
1805 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1806                         struct platform_device *pdev)
1807 {
1808 #ifdef CONFIG_OF
1809         if (pdev->dev.of_node) {
1810                 const struct of_device_id *match;
1811                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1812                 return (struct s3c24xx_serial_drv_data *)match->data;
1813         }
1814 #endif
1815         return (struct s3c24xx_serial_drv_data *)
1816                         platform_get_device_id(pdev)->driver_data;
1817 }
1818
1819 static int s3c24xx_serial_probe(struct platform_device *pdev)
1820 {
1821         struct device_node *np = pdev->dev.of_node;
1822         struct s3c24xx_uart_port *ourport;
1823         int index = probe_index;
1824         int ret;
1825
1826         if (np) {
1827                 ret = of_alias_get_id(np, "serial");
1828                 if (ret >= 0)
1829                         index = ret;
1830         }
1831
1832         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1833
1834         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1835                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1836                 return -EINVAL;
1837         }
1838         ourport = &s3c24xx_serial_ports[index];
1839
1840         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1841         if (!ourport->drv_data) {
1842                 dev_err(&pdev->dev, "could not find driver data\n");
1843                 return -ENODEV;
1844         }
1845
1846         ourport->baudclk = ERR_PTR(-EINVAL);
1847         ourport->info = ourport->drv_data->info;
1848         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1849                         dev_get_platdata(&pdev->dev) :
1850                         ourport->drv_data->def_cfg;
1851
1852         if (np)
1853                 of_property_read_u32(np,
1854                         "samsung,uart-fifosize", &ourport->port.fifosize);
1855
1856         if (ourport->drv_data->fifosize[index])
1857                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1858         else if (ourport->info->fifosize)
1859                 ourport->port.fifosize = ourport->info->fifosize;
1860
1861         /*
1862          * DMA transfers must be aligned at least to cache line size,
1863          * so find minimal transfer size suitable for DMA mode
1864          */
1865         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1866                                     dma_get_cache_alignment());
1867
1868         dbg("%s: initialising port %p...\n", __func__, ourport);
1869
1870         ret = s3c24xx_serial_init_port(ourport, pdev);
1871         if (ret < 0)
1872                 return ret;
1873
1874         if (!s3c24xx_uart_drv.state) {
1875                 ret = uart_register_driver(&s3c24xx_uart_drv);
1876                 if (ret < 0) {
1877                         pr_err("Failed to register Samsung UART driver\n");
1878                         return ret;
1879                 }
1880         }
1881
1882         dbg("%s: adding port\n", __func__);
1883         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1884         platform_set_drvdata(pdev, &ourport->port);
1885
1886         /*
1887          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1888          * so that a potential re-enablement through the pm-callback overlaps
1889          * and keeps the clock enabled in this case.
1890          */
1891         clk_disable_unprepare(ourport->clk);
1892
1893         ret = s3c24xx_serial_cpufreq_register(ourport);
1894         if (ret < 0)
1895                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1896
1897         probe_index++;
1898
1899         return 0;
1900 }
1901
1902 static int s3c24xx_serial_remove(struct platform_device *dev)
1903 {
1904         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1905
1906         if (port) {
1907                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1908                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1909         }
1910
1911         uart_unregister_driver(&s3c24xx_uart_drv);
1912
1913         return 0;
1914 }
1915
1916 /* UART power management code */
1917 #ifdef CONFIG_PM_SLEEP
1918 static int s3c24xx_serial_suspend(struct device *dev)
1919 {
1920         struct uart_port *port = s3c24xx_dev_to_port(dev);
1921
1922         if (port)
1923                 uart_suspend_port(&s3c24xx_uart_drv, port);
1924
1925         return 0;
1926 }
1927
1928 static int s3c24xx_serial_resume(struct device *dev)
1929 {
1930         struct uart_port *port = s3c24xx_dev_to_port(dev);
1931         struct s3c24xx_uart_port *ourport = to_ourport(port);
1932
1933         if (port) {
1934                 clk_prepare_enable(ourport->clk);
1935                 if (!IS_ERR(ourport->baudclk))
1936                         clk_prepare_enable(ourport->baudclk);
1937                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1938                 if (!IS_ERR(ourport->baudclk))
1939                         clk_disable_unprepare(ourport->baudclk);
1940                 clk_disable_unprepare(ourport->clk);
1941
1942                 uart_resume_port(&s3c24xx_uart_drv, port);
1943         }
1944
1945         return 0;
1946 }
1947
1948 static int s3c24xx_serial_resume_noirq(struct device *dev)
1949 {
1950         struct uart_port *port = s3c24xx_dev_to_port(dev);
1951         struct s3c24xx_uart_port *ourport = to_ourport(port);
1952
1953         if (port) {
1954                 /* restore IRQ mask */
1955                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1956                         unsigned int uintm = 0xf;
1957                         if (tx_enabled(port))
1958                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1959                         if (rx_enabled(port))
1960                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1961                         clk_prepare_enable(ourport->clk);
1962                         if (!IS_ERR(ourport->baudclk))
1963                                 clk_prepare_enable(ourport->baudclk);
1964                         wr_regl(port, S3C64XX_UINTM, uintm);
1965                         if (!IS_ERR(ourport->baudclk))
1966                                 clk_disable_unprepare(ourport->baudclk);
1967                         clk_disable_unprepare(ourport->clk);
1968                 }
1969         }
1970
1971         return 0;
1972 }
1973
1974 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1975         .suspend = s3c24xx_serial_suspend,
1976         .resume = s3c24xx_serial_resume,
1977         .resume_noirq = s3c24xx_serial_resume_noirq,
1978 };
1979 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1980
1981 #else /* !CONFIG_PM_SLEEP */
1982
1983 #define SERIAL_SAMSUNG_PM_OPS   NULL
1984 #endif /* CONFIG_PM_SLEEP */
1985
1986 /* Console code */
1987
1988 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1989
1990 static struct uart_port *cons_uart;
1991
1992 static int
1993 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1994 {
1995         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1996         unsigned long ufstat, utrstat;
1997
1998         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1999                 /* fifo mode - check amount of data in fifo registers... */
2000
2001                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2002                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2003         }
2004
2005         /* in non-fifo mode, we go and use the tx buffer empty */
2006
2007         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2008         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2009 }
2010
2011 static bool
2012 s3c24xx_port_configured(unsigned int ucon)
2013 {
2014         /* consider the serial port configured if the tx/rx mode set */
2015         return (ucon & 0xf) != 0;
2016 }
2017
2018 #ifdef CONFIG_CONSOLE_POLL
2019 /*
2020  * Console polling routines for writing and reading from the uart while
2021  * in an interrupt or debug context.
2022  */
2023
2024 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2025 {
2026         struct s3c24xx_uart_port *ourport = to_ourport(port);
2027         unsigned int ufstat;
2028
2029         ufstat = rd_regl(port, S3C2410_UFSTAT);
2030         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2031                 return NO_POLL_CHAR;
2032
2033         return rd_regb(port, S3C2410_URXH);
2034 }
2035
2036 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2037                 unsigned char c)
2038 {
2039         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2040         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2041
2042         /* not possible to xmit on unconfigured port */
2043         if (!s3c24xx_port_configured(ucon))
2044                 return;
2045
2046         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2047                 cpu_relax();
2048         wr_regb(port, S3C2410_UTXH, c);
2049 }
2050
2051 #endif /* CONFIG_CONSOLE_POLL */
2052
2053 static void
2054 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2055 {
2056         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2057
2058         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2059                 cpu_relax();
2060         wr_regb(port, S3C2410_UTXH, ch);
2061 }
2062
2063 static void
2064 s3c24xx_serial_console_write(struct console *co, const char *s,
2065                              unsigned int count)
2066 {
2067         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2068
2069         /* not possible to xmit on unconfigured port */
2070         if (!s3c24xx_port_configured(ucon))
2071                 return;
2072
2073         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2074 }
2075
2076 static void __init
2077 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2078                            int *parity, int *bits)
2079 {
2080         struct clk *clk;
2081         unsigned int ulcon;
2082         unsigned int ucon;
2083         unsigned int ubrdiv;
2084         unsigned long rate;
2085         unsigned int clk_sel;
2086         char clk_name[MAX_CLK_NAME_LENGTH];
2087
2088         ulcon  = rd_regl(port, S3C2410_ULCON);
2089         ucon   = rd_regl(port, S3C2410_UCON);
2090         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2091
2092         dbg("s3c24xx_serial_get_options: port=%p\n"
2093             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2094             port, ulcon, ucon, ubrdiv);
2095
2096         if (s3c24xx_port_configured(ucon)) {
2097                 switch (ulcon & S3C2410_LCON_CSMASK) {
2098                 case S3C2410_LCON_CS5:
2099                         *bits = 5;
2100                         break;
2101                 case S3C2410_LCON_CS6:
2102                         *bits = 6;
2103                         break;
2104                 case S3C2410_LCON_CS7:
2105                         *bits = 7;
2106                         break;
2107                 case S3C2410_LCON_CS8:
2108                 default:
2109                         *bits = 8;
2110                         break;
2111                 }
2112
2113                 switch (ulcon & S3C2410_LCON_PMASK) {
2114                 case S3C2410_LCON_PEVEN:
2115                         *parity = 'e';
2116                         break;
2117
2118                 case S3C2410_LCON_PODD:
2119                         *parity = 'o';
2120                         break;
2121
2122                 case S3C2410_LCON_PNONE:
2123                 default:
2124                         *parity = 'n';
2125                 }
2126
2127                 /* now calculate the baud rate */
2128
2129                 clk_sel = s3c24xx_serial_getsource(port);
2130                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2131
2132                 clk = clk_get(port->dev, clk_name);
2133                 if (!IS_ERR(clk))
2134                         rate = clk_get_rate(clk);
2135                 else
2136                         rate = 1;
2137
2138                 *baud = rate / (16 * (ubrdiv + 1));
2139                 dbg("calculated baud %d\n", *baud);
2140         }
2141
2142 }
2143
2144 static int __init
2145 s3c24xx_serial_console_setup(struct console *co, char *options)
2146 {
2147         struct uart_port *port;
2148         int baud = 9600;
2149         int bits = 8;
2150         int parity = 'n';
2151         int flow = 'n';
2152
2153         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2154             co, co->index, options);
2155
2156         /* is this a valid port */
2157
2158         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2159                 co->index = 0;
2160
2161         port = &s3c24xx_serial_ports[co->index].port;
2162
2163         /* is the port configured? */
2164
2165         if (port->mapbase == 0x0)
2166                 return -ENODEV;
2167
2168         cons_uart = port;
2169
2170         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2171
2172         /*
2173          * Check whether an invalid uart number has been specified, and
2174          * if so, search for the first available port that does have
2175          * console support.
2176          */
2177         if (options)
2178                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2179         else
2180                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2181
2182         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2183
2184         return uart_set_options(port, co, baud, parity, bits, flow);
2185 }
2186
2187 static struct console s3c24xx_serial_console = {
2188         .name           = S3C24XX_SERIAL_NAME,
2189         .device         = uart_console_device,
2190         .flags          = CON_PRINTBUFFER,
2191         .index          = -1,
2192         .write          = s3c24xx_serial_console_write,
2193         .setup          = s3c24xx_serial_console_setup,
2194         .data           = &s3c24xx_uart_drv,
2195 };
2196 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2197
2198 #ifdef CONFIG_CPU_S3C2410
2199 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2200         .info = &(struct s3c24xx_uart_info) {
2201                 .name           = "Samsung S3C2410 UART",
2202                 .type           = PORT_S3C2410,
2203                 .fifosize       = 16,
2204                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2205                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2206                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2207                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2208                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2209                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2210                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2211                 .num_clks       = 2,
2212                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2213                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2214         },
2215         .def_cfg = &(struct s3c2410_uartcfg) {
2216                 .ucon           = S3C2410_UCON_DEFAULT,
2217                 .ufcon          = S3C2410_UFCON_DEFAULT,
2218         },
2219 };
2220 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2221 #else
2222 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2223 #endif
2224
2225 #ifdef CONFIG_CPU_S3C2412
2226 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2227         .info = &(struct s3c24xx_uart_info) {
2228                 .name           = "Samsung S3C2412 UART",
2229                 .type           = PORT_S3C2412,
2230                 .fifosize       = 64,
2231                 .has_divslot    = 1,
2232                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2233                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2234                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2235                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2236                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2237                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2238                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2239                 .num_clks       = 4,
2240                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2241                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2242         },
2243         .def_cfg = &(struct s3c2410_uartcfg) {
2244                 .ucon           = S3C2410_UCON_DEFAULT,
2245                 .ufcon          = S3C2410_UFCON_DEFAULT,
2246         },
2247 };
2248 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2249 #else
2250 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2251 #endif
2252
2253 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2254         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2255 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2256         .info = &(struct s3c24xx_uart_info) {
2257                 .name           = "Samsung S3C2440 UART",
2258                 .type           = PORT_S3C2440,
2259                 .fifosize       = 64,
2260                 .has_divslot    = 1,
2261                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2262                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2263                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2264                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2265                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2266                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2267                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2268                 .num_clks       = 4,
2269                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2270                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2271         },
2272         .def_cfg = &(struct s3c2410_uartcfg) {
2273                 .ucon           = S3C2410_UCON_DEFAULT,
2274                 .ufcon          = S3C2410_UFCON_DEFAULT,
2275         },
2276 };
2277 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2278 #else
2279 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2280 #endif
2281
2282 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2283 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2284         .info = &(struct s3c24xx_uart_info) {
2285                 .name           = "Samsung S3C6400 UART",
2286                 .type           = PORT_S3C6400,
2287                 .fifosize       = 64,
2288                 .has_divslot    = 1,
2289                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2290                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2291                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2292                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2293                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2294                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2295                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2296                 .num_clks       = 4,
2297                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2298                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2299         },
2300         .def_cfg = &(struct s3c2410_uartcfg) {
2301                 .ucon           = S3C2410_UCON_DEFAULT,
2302                 .ufcon          = S3C2410_UFCON_DEFAULT,
2303         },
2304 };
2305 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2306 #else
2307 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2308 #endif
2309
2310 #ifdef CONFIG_CPU_S5PV210
2311 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2312         .info = &(struct s3c24xx_uart_info) {
2313                 .name           = "Samsung S5PV210 UART",
2314                 .type           = PORT_S3C6400,
2315                 .has_divslot    = 1,
2316                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2317                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2318                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2319                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2320                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2321                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2322                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2323                 .num_clks       = 2,
2324                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2325                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2326         },
2327         .def_cfg = &(struct s3c2410_uartcfg) {
2328                 .ucon           = S5PV210_UCON_DEFAULT,
2329                 .ufcon          = S5PV210_UFCON_DEFAULT,
2330         },
2331         .fifosize = { 256, 64, 16, 16 },
2332 };
2333 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2334 #else
2335 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2336 #endif
2337
2338 #if defined(CONFIG_ARCH_EXYNOS)
2339 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2340         .info = &(struct s3c24xx_uart_info) {                   \
2341                 .name           = "Samsung Exynos UART",        \
2342                 .type           = PORT_S3C6400,                 \
2343                 .has_divslot    = 1,                            \
2344                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2345                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2346                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2347                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2348                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2349                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2350                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2351                 .num_clks       = 1,                            \
2352                 .clksel_mask    = 0,                            \
2353                 .clksel_shift   = 0,                            \
2354         },                                                      \
2355         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2356                 .ucon           = S5PV210_UCON_DEFAULT,         \
2357                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2358                 .has_fracval    = 1,                            \
2359         }                                                       \
2360
2361 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2362         EXYNOS_COMMON_SERIAL_DRV_DATA,
2363         .fifosize = { 256, 64, 16, 16 },
2364 };
2365
2366 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2367         EXYNOS_COMMON_SERIAL_DRV_DATA,
2368         .fifosize = { 64, 256, 16, 256 },
2369 };
2370
2371 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2372 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2373 #else
2374 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2375 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2376 #endif
2377
2378 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2379         {
2380                 .name           = "s3c2410-uart",
2381                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2382         }, {
2383                 .name           = "s3c2412-uart",
2384                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2385         }, {
2386                 .name           = "s3c2440-uart",
2387                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2388         }, {
2389                 .name           = "s3c6400-uart",
2390                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2391         }, {
2392                 .name           = "s5pv210-uart",
2393                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2394         }, {
2395                 .name           = "exynos4210-uart",
2396                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2397         }, {
2398                 .name           = "exynos5433-uart",
2399                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2400         },
2401         { },
2402 };
2403 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2404
2405 #ifdef CONFIG_OF
2406 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2407         { .compatible = "samsung,s3c2410-uart",
2408                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2409         { .compatible = "samsung,s3c2412-uart",
2410                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2411         { .compatible = "samsung,s3c2440-uart",
2412                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2413         { .compatible = "samsung,s3c6400-uart",
2414                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2415         { .compatible = "samsung,s5pv210-uart",
2416                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2417         { .compatible = "samsung,exynos4210-uart",
2418                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2419         { .compatible = "samsung,exynos5433-uart",
2420                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2421         {},
2422 };
2423 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2424 #endif
2425
2426 static struct platform_driver samsung_serial_driver = {
2427         .probe          = s3c24xx_serial_probe,
2428         .remove         = s3c24xx_serial_remove,
2429         .id_table       = s3c24xx_serial_driver_ids,
2430         .driver         = {
2431                 .name   = "samsung-uart",
2432                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2433                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2434         },
2435 };
2436
2437 module_platform_driver(samsung_serial_driver);
2438
2439 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2440 /*
2441  * Early console.
2442  */
2443
2444 struct samsung_early_console_data {
2445         u32 txfull_mask;
2446 };
2447
2448 static void samsung_early_busyuart(struct uart_port *port)
2449 {
2450         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2451                 ;
2452 }
2453
2454 static void samsung_early_busyuart_fifo(struct uart_port *port)
2455 {
2456         struct samsung_early_console_data *data = port->private_data;
2457
2458         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2459                 ;
2460 }
2461
2462 static void samsung_early_putc(struct uart_port *port, int c)
2463 {
2464         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2465                 samsung_early_busyuart_fifo(port);
2466         else
2467                 samsung_early_busyuart(port);
2468
2469         writeb(c, port->membase + S3C2410_UTXH);
2470 }
2471
2472 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2473 {
2474         struct earlycon_device *dev = con->data;
2475
2476         uart_console_write(&dev->port, s, n, samsung_early_putc);
2477 }
2478
2479 static int __init samsung_early_console_setup(struct earlycon_device *device,
2480                                               const char *opt)
2481 {
2482         if (!device->port.membase)
2483                 return -ENODEV;
2484
2485         device->con->write = samsung_early_write;
2486         return 0;
2487 }
2488
2489 /* S3C2410 */
2490 static struct samsung_early_console_data s3c2410_early_console_data = {
2491         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2492 };
2493
2494 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2495                                               const char *opt)
2496 {
2497         device->port.private_data = &s3c2410_early_console_data;
2498         return samsung_early_console_setup(device, opt);
2499 }
2500 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2501                         s3c2410_early_console_setup);
2502
2503 /* S3C2412, S3C2440, S3C64xx */
2504 static struct samsung_early_console_data s3c2440_early_console_data = {
2505         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2506 };
2507
2508 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2509                                               const char *opt)
2510 {
2511         device->port.private_data = &s3c2440_early_console_data;
2512         return samsung_early_console_setup(device, opt);
2513 }
2514 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2515                         s3c2440_early_console_setup);
2516 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2517                         s3c2440_early_console_setup);
2518 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2519                         s3c2440_early_console_setup);
2520
2521 /* S5PV210, EXYNOS */
2522 static struct samsung_early_console_data s5pv210_early_console_data = {
2523         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2524 };
2525
2526 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2527                                               const char *opt)
2528 {
2529         device->port.private_data = &s5pv210_early_console_data;
2530         return samsung_early_console_setup(device, opt);
2531 }
2532 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2533                         s5pv210_early_console_setup);
2534 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2535                         s5pv210_early_console_setup);
2536 #endif
2537
2538 MODULE_ALIAS("platform:samsung-uart");
2539 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2540 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2541 MODULE_LICENSE("GPL v2");