drivers/tty/serial/samsung.c

   1 /*
   2  * Driver core for Samsung SoC onboard UARTs.
   3  *
   4  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 /* Hote on 2410 error handling
  13  *
  14  * The s3c2410 manual has a love/hate affair with the contents of the
  15  * UERSTAT register in the UART blocks, and keeps marking some of the
  16  * error bits as reserved. Having checked with the s3c2410x01,
  17  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  18  * feature from the latter versions of the manual.
  19  *
  20  * If it becomes aparrent that latter versions of the 2410 remove these
  21  * bits, then action will have to be taken to differentiate the versions
  22  * and change the policy on BREAK
  23  *
  24  * BJD, 04-Nov-2004
  25 */
  26
  27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  28 #define SUPPORT_SYSRQ
  29 #endif
  30
  31 #include <linux/dmaengine.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/module.h>
  35 #include <linux/ioport.h>
  36 #include <linux/io.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/init.h>
  39 #include <linux/sysrq.h>
  40 #include <linux/console.h>
  41 #include <linux/tty.h>
  42 #include <linux/tty_flip.h>
  43 #include <linux/serial_core.h>
  44 #include <linux/serial.h>
  45 #include <linux/serial_s3c.h>
  46 #include <linux/delay.h>
  47 #include <linux/clk.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/of.h>
  50
  51 #include <asm/irq.h>
  52
  53 #include "samsung.h"
  54
  55 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  56         !defined(MODULE)
  57
  58 extern void printascii(const char *);
  59
  60 __printf(1, 2)
  61 static void dbg(const char *fmt, ...)
  62 {
  63         va_list va;
  64         char buff[256];
  65
  66         va_start(va, fmt);
  67         vscnprintf(buff, sizeof(buff), fmt, va);
  68         va_end(va);
  69
  70         printascii(buff);
  71 }
  72
  73 #else
  74 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  75 #endif
  76
  77 /* UART name and device definitions */
  78
  79 #define S3C24XX_SERIAL_NAME     "ttySAC"
  80 #define S3C24XX_SERIAL_MAJOR    204
  81 #define S3C24XX_SERIAL_MINOR    64
  82
  83 #define S3C24XX_TX_PIO                  1
  84 #define S3C24XX_TX_DMA                  2
  85 #define S3C24XX_RX_PIO                  1
  86 #define S3C24XX_RX_DMA                  2
  87 /* macros to change one thing to another */
  88
  89 #define tx_enabled(port) ((port)->unused[0])
  90 #define rx_enabled(port) ((port)->unused[1])
  91
  92 /* flag to ignore all characters coming in */
  93 #define RXSTAT_DUMMY_READ (0x10000000)
  94
  95 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  96 {
  97         return container_of(port, struct s3c24xx_uart_port, port);
  98 }
  99
 100 /* translate a port to the device name */
 101
 102 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 103 {
 104         return to_platform_device(port->dev)->name;
 105 }
 106
 107 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 108 {
 109         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 110 }
 111
 112 /*
 113  * s3c64xx and later SoC's include the interrupt mask and status registers in
 114  * the controller itself, unlike the s3c24xx SoC's which have these registers
 115  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 116  */
 117 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 118 {
 119         return to_ourport(port)->info->type == PORT_S3C6400;
 120 }
 121
 122 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 123 {
 124         unsigned long flags;
 125         unsigned int ucon, ufcon;
 126         int count = 10000;
 127
 128         spin_lock_irqsave(&port->lock, flags);
 129
 130         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 131                 udelay(100);
 132
 133         ufcon = rd_regl(port, S3C2410_UFCON);
 134         ufcon |= S3C2410_UFCON_RESETRX;
 135         wr_regl(port, S3C2410_UFCON, ufcon);
 136
 137         ucon = rd_regl(port, S3C2410_UCON);
 138         ucon |= S3C2410_UCON_RXIRQMODE;
 139         wr_regl(port, S3C2410_UCON, ucon);
 140
 141         rx_enabled(port) = 1;
 142         spin_unlock_irqrestore(&port->lock, flags);
 143 }
 144
 145 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 146 {
 147         unsigned long flags;
 148         unsigned int ucon;
 149
 150         spin_lock_irqsave(&port->lock, flags);
 151
 152         ucon = rd_regl(port, S3C2410_UCON);
 153         ucon &= ~S3C2410_UCON_RXIRQMODE;
 154         wr_regl(port, S3C2410_UCON, ucon);
 155
 156         rx_enabled(port) = 0;
 157         spin_unlock_irqrestore(&port->lock, flags);
 158 }
 159
 160 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 161 {
 162         struct s3c24xx_uart_port *ourport = to_ourport(port);
 163         struct s3c24xx_uart_dma *dma = ourport->dma;
 164         struct circ_buf *xmit = &port->state->xmit;
 165         struct dma_tx_state state;
 166         int count;
 167
 168         if (!tx_enabled(port))
 169                 return;
 170
 171         if (s3c24xx_serial_has_interrupt_mask(port))
 172                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 173         else
 174                 disable_irq_nosync(ourport->tx_irq);
 175
 176         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 177                 dmaengine_pause(dma->tx_chan);
 178                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 179                 dmaengine_terminate_all(dma->tx_chan);
 180                 dma_sync_single_for_cpu(ourport->port.dev,
 181                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 182                 async_tx_ack(dma->tx_desc);
 183                 count = dma->tx_bytes_requested - state.residue;
 184                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 185                 port->icount.tx += count;
 186         }
 187
 188         tx_enabled(port) = 0;
 189         ourport->tx_in_progress = 0;
 190
 191         if (port->flags & UPF_CONS_FLOW)
 192                 s3c24xx_serial_rx_enable(port);
 193
 194         ourport->tx_mode = 0;
 195 }
 196
 197 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 198
 199 static void s3c24xx_serial_tx_dma_complete(void *args)
 200 {
 201         struct s3c24xx_uart_port *ourport = args;
 202         struct uart_port *port = &ourport->port;
 203         struct circ_buf *xmit = &port->state->xmit;
 204         struct s3c24xx_uart_dma *dma = ourport->dma;
 205         struct dma_tx_state state;
 206         unsigned long flags;
 207         int count;
 208
 209
 210         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 211         count = dma->tx_bytes_requested - state.residue;
 212         async_tx_ack(dma->tx_desc);
 213
 214         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 215                                 dma->tx_size, DMA_TO_DEVICE);
 216
 217         spin_lock_irqsave(&port->lock, flags);
 218
 219         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 220         port->icount.tx += count;
 221         ourport->tx_in_progress = 0;
 222
 223         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 224                 uart_write_wakeup(port);
 225
 226         s3c24xx_serial_start_next_tx(ourport);
 227         spin_unlock_irqrestore(&port->lock, flags);
 228 }
 229
 230 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 231 {
 232         struct uart_port *port = &ourport->port;
 233         u32 ucon;
 234
 235         /* Mask Tx interrupt */
 236         if (s3c24xx_serial_has_interrupt_mask(port))
 237                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 238         else
 239                 disable_irq_nosync(ourport->tx_irq);
 240
 241         /* Enable tx dma mode */
 242         ucon = rd_regl(port, S3C2410_UCON);
 243         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 244         ucon |= (dma_get_cache_alignment() >= 16) ?
 245                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 246         ucon |= S3C64XX_UCON_TXMODE_DMA;
 247         wr_regl(port,  S3C2410_UCON, ucon);
 248
 249         ourport->tx_mode = S3C24XX_TX_DMA;
 250 }
 251
 252 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 253 {
 254         struct uart_port *port = &ourport->port;
 255         u32 ucon, ufcon;
 256
 257         /* Set ufcon txtrig */
 258         ourport->tx_in_progress = S3C24XX_TX_PIO;
 259         ufcon = rd_regl(port, S3C2410_UFCON);
 260         wr_regl(port,  S3C2410_UFCON, ufcon);
 261
 262         /* Enable tx pio mode */
 263         ucon = rd_regl(port, S3C2410_UCON);
 264         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 265         ucon |= S3C64XX_UCON_TXMODE_CPU;
 266         wr_regl(port,  S3C2410_UCON, ucon);
 267
 268         /* Unmask Tx interrupt */
 269         if (s3c24xx_serial_has_interrupt_mask(port))
 270                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 271                                   S3C64XX_UINTM);
 272         else
 273                 enable_irq(ourport->tx_irq);
 274
 275         ourport->tx_mode = S3C24XX_TX_PIO;
 276 }
 277
 278 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 279 {
 280         if (ourport->tx_mode != S3C24XX_TX_PIO)
 281                 enable_tx_pio(ourport);
 282 }
 283
 284 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 285                                       unsigned int count)
 286 {
 287         struct uart_port *port = &ourport->port;
 288         struct circ_buf *xmit = &port->state->xmit;
 289         struct s3c24xx_uart_dma *dma = ourport->dma;
 290
 291
 292         if (ourport->tx_mode != S3C24XX_TX_DMA)
 293                 enable_tx_dma(ourport);
 294
 295         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 296         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 297
 298         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 299                                 dma->tx_size, DMA_TO_DEVICE);
 300
 301         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 302                                 dma->tx_transfer_addr, dma->tx_size,
 303                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 304         if (!dma->tx_desc) {
 305                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 306                 return -EIO;
 307         }
 308
 309         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 310         dma->tx_desc->callback_param = ourport;
 311         dma->tx_bytes_requested = dma->tx_size;
 312
 313         ourport->tx_in_progress = S3C24XX_TX_DMA;
 314         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 315         dma_async_issue_pending(dma->tx_chan);
 316         return 0;
 317 }
 318
 319 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 320 {
 321         struct uart_port *port = &ourport->port;
 322         struct circ_buf *xmit = &port->state->xmit;
 323         unsigned long count;
 324
 325         /* Get data size up to the end of buffer */
 326         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 327
 328         if (!count) {
 329                 s3c24xx_serial_stop_tx(port);
 330                 return;
 331         }
 332
 333         if (!ourport->dma || !ourport->dma->tx_chan ||
 334             count < ourport->min_dma_size ||
 335             xmit->tail & (dma_get_cache_alignment() - 1))
 336                 s3c24xx_serial_start_tx_pio(ourport);
 337         else
 338                 s3c24xx_serial_start_tx_dma(ourport, count);
 339 }
 340
 341 static void s3c24xx_serial_start_tx(struct uart_port *port)
 342 {
 343         struct s3c24xx_uart_port *ourport = to_ourport(port);
 344         struct circ_buf *xmit = &port->state->xmit;
 345
 346         if (!tx_enabled(port)) {
 347                 if (port->flags & UPF_CONS_FLOW)
 348                         s3c24xx_serial_rx_disable(port);
 349
 350                 tx_enabled(port) = 1;
 351                 if (!ourport->dma || !ourport->dma->tx_chan)
 352                         s3c24xx_serial_start_tx_pio(ourport);
 353         }
 354
 355         if (ourport->dma && ourport->dma->tx_chan) {
 356                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 357                         s3c24xx_serial_start_next_tx(ourport);
 358         }
 359 }
 360
 361 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 362                 struct tty_port *tty, int count)
 363 {
 364         struct s3c24xx_uart_dma *dma = ourport->dma;
 365         int copied;
 366
 367         if (!count)
 368                 return;
 369
 370         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 371                                 dma->rx_size, DMA_FROM_DEVICE);
 372
 373         ourport->port.icount.rx += count;
 374         if (!tty) {
 375                 dev_err(ourport->port.dev, "No tty port\n");
 376                 return;
 377         }
 378         copied = tty_insert_flip_string(tty,
 379                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 380         if (copied != count) {
 381                 WARN_ON(1);
 382                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 383         }
 384 }
 385
 386 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 387 {
 388         struct s3c24xx_uart_port *ourport = to_ourport(port);
 389         struct s3c24xx_uart_dma *dma = ourport->dma;
 390         struct tty_port *t = &port->state->port;
 391         struct dma_tx_state state;
 392         enum dma_status dma_status;
 393         unsigned int received;
 394
 395         if (rx_enabled(port)) {
 396                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 397                 if (s3c24xx_serial_has_interrupt_mask(port))
 398                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 399                                         S3C64XX_UINTM);
 400                 else
 401                         disable_irq_nosync(ourport->rx_irq);
 402                 rx_enabled(port) = 0;
 403         }
 404         if (dma && dma->rx_chan) {
 405                 dmaengine_pause(dma->tx_chan);
 406                 dma_status = dmaengine_tx_status(dma->rx_chan,
 407                                 dma->rx_cookie, &state);
 408                 if (dma_status == DMA_IN_PROGRESS ||
 409                         dma_status == DMA_PAUSED) {
 410                         received = dma->rx_bytes_requested - state.residue;
 411                         dmaengine_terminate_all(dma->rx_chan);
 412                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 413                 }
 414         }
 415 }
 416
 417 static inline struct s3c24xx_uart_info
 418         *s3c24xx_port_to_info(struct uart_port *port)
 419 {
 420         return to_ourport(port)->info;
 421 }
 422
 423 static inline struct s3c2410_uartcfg
 424         *s3c24xx_port_to_cfg(struct uart_port *port)
 425 {
 426         struct s3c24xx_uart_port *ourport;
 427
 428         if (port->dev == NULL)
 429                 return NULL;
 430
 431         ourport = container_of(port, struct s3c24xx_uart_port, port);
 432         return ourport->cfg;
 433 }
 434
 435 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 436                                      unsigned long ufstat)
 437 {
 438         struct s3c24xx_uart_info *info = ourport->info;
 439
 440         if (ufstat & info->rx_fifofull)
 441                 return ourport->port.fifosize;
 442
 443         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 444 }
 445
 446 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 447 static void s3c24xx_serial_rx_dma_complete(void *args)
 448 {
 449         struct s3c24xx_uart_port *ourport = args;
 450         struct uart_port *port = &ourport->port;
 451
 452         struct s3c24xx_uart_dma *dma = ourport->dma;
 453         struct tty_port *t = &port->state->port;
 454         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 455
 456         struct dma_tx_state state;
 457         unsigned long flags;
 458         int received;
 459
 460         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 461         received  = dma->rx_bytes_requested - state.residue;
 462         async_tx_ack(dma->rx_desc);
 463
 464         spin_lock_irqsave(&port->lock, flags);
 465
 466         if (received)
 467                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 468
 469         if (tty) {
 470                 tty_flip_buffer_push(t);
 471                 tty_kref_put(tty);
 472         }
 473
 474         s3c64xx_start_rx_dma(ourport);
 475
 476         spin_unlock_irqrestore(&port->lock, flags);
 477 }
 478
 479 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 480 {
 481         struct s3c24xx_uart_dma *dma = ourport->dma;
 482
 483         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 484                                 dma->rx_size, DMA_FROM_DEVICE);
 485
 486         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 487                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 488                                 DMA_PREP_INTERRUPT);
 489         if (!dma->rx_desc) {
 490                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 491                 return;
 492         }
 493
 494         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 495         dma->rx_desc->callback_param = ourport;
 496         dma->rx_bytes_requested = dma->rx_size;
 497
 498         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 499         dma_async_issue_pending(dma->rx_chan);
 500 }
 501
 502 /* ? - where has parity gone?? */
 503 #define S3C2410_UERSTAT_PARITY (0x1000)
 504
 505 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 506 {
 507         struct uart_port *port = &ourport->port;
 508         unsigned int ucon;
 509
 510         /* set Rx mode to DMA mode */
 511         ucon = rd_regl(port, S3C2410_UCON);
 512         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 513                         S3C64XX_UCON_TIMEOUT_MASK |
 514                         S3C64XX_UCON_EMPTYINT_EN |
 515                         S3C64XX_UCON_DMASUS_EN |
 516                         S3C64XX_UCON_TIMEOUT_EN |
 517                         S3C64XX_UCON_RXMODE_MASK);
 518         ucon |= S3C64XX_UCON_RXBURST_16 |
 519                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 520                         S3C64XX_UCON_EMPTYINT_EN |
 521                         S3C64XX_UCON_TIMEOUT_EN |
 522                         S3C64XX_UCON_RXMODE_DMA;
 523         wr_regl(port, S3C2410_UCON, ucon);
 524
 525         ourport->rx_mode = S3C24XX_RX_DMA;
 526 }
 527
 528 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 529 {
 530         struct uart_port *port = &ourport->port;
 531         unsigned int ucon;
 532
 533         /* set Rx mode to DMA mode */
 534         ucon = rd_regl(port, S3C2410_UCON);
 535         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 536                         S3C64XX_UCON_EMPTYINT_EN |
 537                         S3C64XX_UCON_DMASUS_EN |
 538                         S3C64XX_UCON_TIMEOUT_EN |
 539                         S3C64XX_UCON_RXMODE_MASK);
 540         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 541                         S3C64XX_UCON_TIMEOUT_EN |
 542                         S3C64XX_UCON_RXMODE_CPU;
 543         wr_regl(port, S3C2410_UCON, ucon);
 544
 545         ourport->rx_mode = S3C24XX_RX_PIO;
 546 }
 547
 548 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 549
 550 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 551 {
 552         unsigned int utrstat, ufstat, received;
 553         struct s3c24xx_uart_port *ourport = dev_id;
 554         struct uart_port *port = &ourport->port;
 555         struct s3c24xx_uart_dma *dma = ourport->dma;
 556         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 557         struct tty_port *t = &port->state->port;
 558         unsigned long flags;
 559         struct dma_tx_state state;
 560
 561         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 562         ufstat = rd_regl(port, S3C2410_UFSTAT);
 563
 564         spin_lock_irqsave(&port->lock, flags);
 565
 566         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 567                 s3c64xx_start_rx_dma(ourport);
 568                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 569                         enable_rx_dma(ourport);
 570                 goto finish;
 571         }
 572
 573         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 574                 dmaengine_pause(dma->rx_chan);
 575                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 576                 dmaengine_terminate_all(dma->rx_chan);
 577                 received = dma->rx_bytes_requested - state.residue;
 578                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 579
 580                 enable_rx_pio(ourport);
 581         }
 582
 583         s3c24xx_serial_rx_drain_fifo(ourport);
 584
 585         if (tty) {
 586                 tty_flip_buffer_push(t);
 587                 tty_kref_put(tty);
 588         }
 589
 590         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 591
 592 finish:
 593         spin_unlock_irqrestore(&port->lock, flags);
 594
 595         return IRQ_HANDLED;
 596 }
 597
 598 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 599 {
 600         struct uart_port *port = &ourport->port;
 601         unsigned int ufcon, ch, flag, ufstat, uerstat;
 602         unsigned int fifocnt = 0;
 603         int max_count = port->fifosize;
 604
 605         while (max_count-- > 0) {
 606                 /*
 607                  * Receive all characters known to be in FIFO
 608                  * before reading FIFO level again
 609                  */
 610                 if (fifocnt == 0) {
 611                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 612                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 613                         if (fifocnt == 0)
 614                                 break;
 615                 }
 616                 fifocnt--;
 617
 618                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 619                 ch = rd_regb(port, S3C2410_URXH);
 620
 621                 if (port->flags & UPF_CONS_FLOW) {
 622                         int txe = s3c24xx_serial_txempty_nofifo(port);
 623
 624                         if (rx_enabled(port)) {
 625                                 if (!txe) {
 626                                         rx_enabled(port) = 0;
 627                                         continue;
 628                                 }
 629                         } else {
 630                                 if (txe) {
 631                                         ufcon = rd_regl(port, S3C2410_UFCON);
 632                                         ufcon |= S3C2410_UFCON_RESETRX;
 633                                         wr_regl(port, S3C2410_UFCON, ufcon);
 634                                         rx_enabled(port) = 1;
 635                                         return;
 636                                 }
 637                                 continue;
 638                         }
 639                 }
 640
 641                 /* insert the character into the buffer */
 642
 643                 flag = TTY_NORMAL;
 644                 port->icount.rx++;
 645
 646                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 647                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 648                             ch, uerstat);
 649
 650                         /* check for break */
 651                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 652                                 dbg("break!\n");
 653                                 port->icount.brk++;
 654                                 if (uart_handle_break(port))
 655                                         continue; /* Ignore character */
 656                         }
 657
 658                         if (uerstat & S3C2410_UERSTAT_FRAME)
 659                                 port->icount.frame++;
 660                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 661                                 port->icount.overrun++;
 662
 663                         uerstat &= port->read_status_mask;
 664
 665                         if (uerstat & S3C2410_UERSTAT_BREAK)
 666                                 flag = TTY_BREAK;
 667                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 668                                 flag = TTY_PARITY;
 669                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 670                                             S3C2410_UERSTAT_OVERRUN))
 671                                 flag = TTY_FRAME;
 672                 }
 673
 674                 if (uart_handle_sysrq_char(port, ch))
 675                         continue; /* Ignore character */
 676
 677                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 678                                  ch, flag);
 679         }
 680
 681         tty_flip_buffer_push(&port->state->port);
 682 }
 683
 684 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 685 {
 686         struct s3c24xx_uart_port *ourport = dev_id;
 687         struct uart_port *port = &ourport->port;
 688         unsigned long flags;
 689
 690         spin_lock_irqsave(&port->lock, flags);
 691         s3c24xx_serial_rx_drain_fifo(ourport);
 692         spin_unlock_irqrestore(&port->lock, flags);
 693
 694         return IRQ_HANDLED;
 695 }
 696
 697
 698 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 699 {
 700         struct s3c24xx_uart_port *ourport = dev_id;
 701
 702         if (ourport->dma && ourport->dma->rx_chan)
 703                 return s3c24xx_serial_rx_chars_dma(dev_id);
 704         return s3c24xx_serial_rx_chars_pio(dev_id);
 705 }
 706
 707 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 708 {
 709         struct s3c24xx_uart_port *ourport = id;
 710         struct uart_port *port = &ourport->port;
 711         struct circ_buf *xmit = &port->state->xmit;
 712         unsigned long flags;
 713         int count, dma_count = 0;
 714
 715         spin_lock_irqsave(&port->lock, flags);
 716
 717         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 718
 719         if (ourport->dma && ourport->dma->tx_chan &&
 720             count >= ourport->min_dma_size) {
 721                 int align = dma_get_cache_alignment() -
 722                         (xmit->tail & (dma_get_cache_alignment() - 1));
 723                 if (count-align >= ourport->min_dma_size) {
 724                         dma_count = count-align;
 725                         count = align;
 726                 }
 727         }
 728
 729         if (port->x_char) {
 730                 wr_regb(port, S3C2410_UTXH, port->x_char);
 731                 port->icount.tx++;
 732                 port->x_char = 0;
 733                 goto out;
 734         }
 735
 736         /* if there isn't anything more to transmit, or the uart is now
 737          * stopped, disable the uart and exit
 738         */
 739
 740         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 741                 s3c24xx_serial_stop_tx(port);
 742                 goto out;
 743         }
 744
 745         /* try and drain the buffer... */
 746
 747         if (count > port->fifosize) {
 748                 count = port->fifosize;
 749                 dma_count = 0;
 750         }
 751
 752         while (!uart_circ_empty(xmit) && count > 0) {
 753                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 754                         break;
 755
 756                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 757                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 758                 port->icount.tx++;
 759                 count--;
 760         }
 761
 762         if (!count && dma_count) {
 763                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 764                 goto out;
 765         }
 766
 767         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 768                 spin_unlock(&port->lock);
 769                 uart_write_wakeup(port);
 770                 spin_lock(&port->lock);
 771         }
 772
 773         if (uart_circ_empty(xmit))
 774                 s3c24xx_serial_stop_tx(port);
 775
 776 out:
 777         spin_unlock_irqrestore(&port->lock, flags);
 778         return IRQ_HANDLED;
 779 }
 780
 781 /* interrupt handler for s3c64xx and later SoC's.*/
 782 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 783 {
 784         struct s3c24xx_uart_port *ourport = id;
 785         struct uart_port *port = &ourport->port;
 786         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 787         irqreturn_t ret = IRQ_HANDLED;
 788
 789         if (pend & S3C64XX_UINTM_RXD_MSK) {
 790                 ret = s3c24xx_serial_rx_chars(irq, id);
 791                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 792         }
 793         if (pend & S3C64XX_UINTM_TXD_MSK) {
 794                 ret = s3c24xx_serial_tx_chars(irq, id);
 795                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 796         }
 797         return ret;
 798 }
 799
 800 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 801 {
 802         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 803         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 804         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 805
 806         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 807                 if ((ufstat & info->tx_fifomask) != 0 ||
 808                     (ufstat & info->tx_fifofull))
 809                         return 0;
 810
 811                 return 1;
 812         }
 813
 814         return s3c24xx_serial_txempty_nofifo(port);
 815 }
 816
 817 /* no modem control lines */
 818 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 819 {
 820         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 821
 822         if (umstat & S3C2410_UMSTAT_CTS)
 823                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 824         else
 825                 return TIOCM_CAR | TIOCM_DSR;
 826 }
 827
 828 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 829 {
 830         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 831
 832         if (mctrl & TIOCM_RTS)
 833                 umcon |= S3C2410_UMCOM_RTS_LOW;
 834         else
 835                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 836
 837         wr_regl(port, S3C2410_UMCON, umcon);
 838 }
 839
 840 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 841 {
 842         unsigned long flags;
 843         unsigned int ucon;
 844
 845         spin_lock_irqsave(&port->lock, flags);
 846
 847         ucon = rd_regl(port, S3C2410_UCON);
 848
 849         if (break_state)
 850                 ucon |= S3C2410_UCON_SBREAK;
 851         else
 852                 ucon &= ~S3C2410_UCON_SBREAK;
 853
 854         wr_regl(port, S3C2410_UCON, ucon);
 855
 856         spin_unlock_irqrestore(&port->lock, flags);
 857 }
 858
 859 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 860 {
 861         struct s3c24xx_uart_dma *dma = p->dma;
 862         int ret;
 863
 864         /* Default slave configuration parameters */
 865         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 866         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 867         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 868         dma->rx_conf.src_maxburst       = 1;
 869
 870         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 871         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 872         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 873         dma->tx_conf.dst_maxburst       = 1;
 874
 875         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 876
 877         if (IS_ERR(dma->rx_chan))
 878                 return PTR_ERR(dma->rx_chan);
 879
 880         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 881
 882         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
 883         if (IS_ERR(dma->tx_chan)) {
 884                 ret = PTR_ERR(dma->tx_chan);
 885                 goto err_release_rx;
 886         }
 887
 888         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 889
 890         /* RX buffer */
 891         dma->rx_size = PAGE_SIZE;
 892
 893         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 894         if (!dma->rx_buf) {
 895                 ret = -ENOMEM;
 896                 goto err_release_tx;
 897         }
 898
 899         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
 900                                 dma->rx_size, DMA_FROM_DEVICE);
 901         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
 902                 ret = -EIO;
 903                 goto err_free_rx;
 904         }
 905
 906         /* TX buffer */
 907         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
 908                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 909         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
 910                 ret = -EIO;
 911                 goto err_unmap_rx;
 912         }
 913
 914         return 0;
 915
 916 err_unmap_rx:
 917         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
 918                          DMA_FROM_DEVICE);
 919 err_free_rx:
 920         kfree(dma->rx_buf);
 921 err_release_tx:
 922         dma_release_channel(dma->tx_chan);
 923 err_release_rx:
 924         dma_release_channel(dma->rx_chan);
 925         return ret;
 926 }
 927
 928 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 929 {
 930         struct s3c24xx_uart_dma *dma = p->dma;
 931
 932         if (dma->rx_chan) {
 933                 dmaengine_terminate_all(dma->rx_chan);
 934                 dma_unmap_single(p->port.dev, dma->rx_addr,
 935                                 dma->rx_size, DMA_FROM_DEVICE);
 936                 kfree(dma->rx_buf);
 937                 dma_release_channel(dma->rx_chan);
 938                 dma->rx_chan = NULL;
 939         }
 940
 941         if (dma->tx_chan) {
 942                 dmaengine_terminate_all(dma->tx_chan);
 943                 dma_unmap_single(p->port.dev, dma->tx_addr,
 944                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 945                 dma_release_channel(dma->tx_chan);
 946                 dma->tx_chan = NULL;
 947         }
 948 }
 949
 950 static void s3c24xx_serial_shutdown(struct uart_port *port)
 951 {
 952         struct s3c24xx_uart_port *ourport = to_ourport(port);
 953
 954         if (ourport->tx_claimed) {
 955                 if (!s3c24xx_serial_has_interrupt_mask(port))
 956                         free_irq(ourport->tx_irq, ourport);
 957                 tx_enabled(port) = 0;
 958                 ourport->tx_claimed = 0;
 959                 ourport->tx_mode = 0;
 960         }
 961
 962         if (ourport->rx_claimed) {
 963                 if (!s3c24xx_serial_has_interrupt_mask(port))
 964                         free_irq(ourport->rx_irq, ourport);
 965                 ourport->rx_claimed = 0;
 966                 rx_enabled(port) = 0;
 967         }
 968
 969         /* Clear pending interrupts and mask all interrupts */
 970         if (s3c24xx_serial_has_interrupt_mask(port)) {
 971                 free_irq(port->irq, ourport);
 972
 973                 wr_regl(port, S3C64XX_UINTP, 0xf);
 974                 wr_regl(port, S3C64XX_UINTM, 0xf);
 975         }
 976
 977         if (ourport->dma)
 978                 s3c24xx_serial_release_dma(ourport);
 979
 980         ourport->tx_in_progress = 0;
 981 }
 982
 983 static int s3c24xx_serial_startup(struct uart_port *port)
 984 {
 985         struct s3c24xx_uart_port *ourport = to_ourport(port);
 986         int ret;
 987
 988         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
 989             port, (unsigned long long)port->mapbase, port->membase);
 990
 991         rx_enabled(port) = 1;
 992
 993         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
 994                           s3c24xx_serial_portname(port), ourport);
 995
 996         if (ret != 0) {
 997                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
 998                 return ret;
 999         }
1000
1001         ourport->rx_claimed = 1;
1002
1003         dbg("requesting tx irq...\n");
1004
1005         tx_enabled(port) = 1;
1006
1007         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1008                           s3c24xx_serial_portname(port), ourport);
1009
1010         if (ret) {
1011                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1012                 goto err;
1013         }
1014
1015         ourport->tx_claimed = 1;
1016
1017         dbg("s3c24xx_serial_startup ok\n");
1018
1019         /* the port reset code should have done the correct
1020          * register setup for the port controls */
1021
1022         return ret;
1023
1024 err:
1025         s3c24xx_serial_shutdown(port);
1026         return ret;
1027 }
1028
1029 static int s3c64xx_serial_startup(struct uart_port *port)
1030 {
1031         struct s3c24xx_uart_port *ourport = to_ourport(port);
1032         unsigned long flags;
1033         unsigned int ufcon;
1034         int ret;
1035
1036         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1037             port, (unsigned long long)port->mapbase, port->membase);
1038
1039         wr_regl(port, S3C64XX_UINTM, 0xf);
1040         if (ourport->dma) {
1041                 ret = s3c24xx_serial_request_dma(ourport);
1042                 if (ret < 0) {
1043                         dev_warn(port->dev,
1044                                  "DMA request failed, DMA will not be used\n");
1045                         devm_kfree(port->dev, ourport->dma);
1046                         ourport->dma = NULL;
1047                 }
1048         }
1049
1050         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1051                           s3c24xx_serial_portname(port), ourport);
1052         if (ret) {
1053                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1054                 return ret;
1055         }
1056
1057         /* For compatibility with s3c24xx Soc's */
1058         rx_enabled(port) = 1;
1059         ourport->rx_claimed = 1;
1060         tx_enabled(port) = 0;
1061         ourport->tx_claimed = 1;
1062
1063         spin_lock_irqsave(&port->lock, flags);
1064
1065         ufcon = rd_regl(port, S3C2410_UFCON);
1066         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1067         if (!uart_console(port))
1068                 ufcon |= S3C2410_UFCON_RESETTX;
1069         wr_regl(port, S3C2410_UFCON, ufcon);
1070
1071         enable_rx_pio(ourport);
1072
1073         spin_unlock_irqrestore(&port->lock, flags);
1074
1075         /* Enable Rx Interrupt */
1076         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1077
1078         dbg("s3c64xx_serial_startup ok\n");
1079         return ret;
1080 }
1081
1082 /* power power management control */
1083
1084 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1085                               unsigned int old)
1086 {
1087         struct s3c24xx_uart_port *ourport = to_ourport(port);
1088         int timeout = 10000;
1089
1090         ourport->pm_level = level;
1091
1092         switch (level) {
1093         case 3:
1094                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1095                         udelay(100);
1096
1097                 if (!IS_ERR(ourport->baudclk))
1098                         clk_disable_unprepare(ourport->baudclk);
1099
1100                 clk_disable_unprepare(ourport->clk);
1101                 break;
1102
1103         case 0:
1104                 clk_prepare_enable(ourport->clk);
1105
1106                 if (!IS_ERR(ourport->baudclk))
1107                         clk_prepare_enable(ourport->baudclk);
1108
1109                 break;
1110         default:
1111                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1112         }
1113 }
1114
1115 /* baud rate calculation
1116  *
1117  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1118  * of different sources, including the peripheral clock ("pclk") and an
1119  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1120  * with a programmable extra divisor.
1121  *
1122  * The following code goes through the clock sources, and calculates the
1123  * baud clocks (and the resultant actual baud rates) and then tries to
1124  * pick the closest one and select that.
1125  *
1126 */
1127
1128 #define MAX_CLK_NAME_LENGTH 15
1129
1130 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1131 {
1132         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1133         unsigned int ucon;
1134
1135         if (info->num_clks == 1)
1136                 return 0;
1137
1138         ucon = rd_regl(port, S3C2410_UCON);
1139         ucon &= info->clksel_mask;
1140         return ucon >> info->clksel_shift;
1141 }
1142
1143 static void s3c24xx_serial_setsource(struct uart_port *port,
1144                         unsigned int clk_sel)
1145 {
1146         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1147         unsigned int ucon;
1148
1149         if (info->num_clks == 1)
1150                 return;
1151
1152         ucon = rd_regl(port, S3C2410_UCON);
1153         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1154                 return;
1155
1156         ucon &= ~info->clksel_mask;
1157         ucon |= clk_sel << info->clksel_shift;
1158         wr_regl(port, S3C2410_UCON, ucon);
1159 }
1160
1161 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1162                         unsigned int req_baud, struct clk **best_clk,
1163                         unsigned int *clk_num)
1164 {
1165         struct s3c24xx_uart_info *info = ourport->info;
1166         struct clk *clk;
1167         unsigned long rate;
1168         unsigned int cnt, baud, quot, best_quot = 0;
1169         char clkname[MAX_CLK_NAME_LENGTH];
1170         int calc_deviation, deviation = (1 << 30) - 1;
1171
1172         for (cnt = 0; cnt < info->num_clks; cnt++) {
1173                 /* Keep selected clock if provided */
1174                 if (ourport->cfg->clk_sel &&
1175                         !(ourport->cfg->clk_sel & (1 << cnt)))
1176                         continue;
1177
1178                 sprintf(clkname, "clk_uart_baud%d", cnt);
1179                 clk = clk_get(ourport->port.dev, clkname);
1180                 if (IS_ERR(clk))
1181                         continue;
1182
1183                 rate = clk_get_rate(clk);
1184                 if (!rate)
1185                         continue;
1186
1187                 if (ourport->info->has_divslot) {
1188                         unsigned long div = rate / req_baud;
1189
1190                         /* The UDIVSLOT register on the newer UARTs allows us to
1191                          * get a divisor adjustment of 1/16th on the baud clock.
1192                          *
1193                          * We don't keep the UDIVSLOT value (the 16ths we
1194                          * calculated by not multiplying the baud by 16) as it
1195                          * is easy enough to recalculate.
1196                          */
1197
1198                         quot = div / 16;
1199                         baud = rate / div;
1200                 } else {
1201                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1202                         baud = rate / (quot * 16);
1203                 }
1204                 quot--;
1205
1206                 calc_deviation = req_baud - baud;
1207                 if (calc_deviation < 0)
1208                         calc_deviation = -calc_deviation;
1209
1210                 if (calc_deviation < deviation) {
1211                         *best_clk = clk;
1212                         best_quot = quot;
1213                         *clk_num = cnt;
1214                         deviation = calc_deviation;
1215                 }
1216         }
1217
1218         return best_quot;
1219 }
1220
1221 /* udivslot_table[]
1222  *
1223  * This table takes the fractional value of the baud divisor and gives
1224  * the recommended setting for the UDIVSLOT register.
1225  */
1226 static u16 udivslot_table[16] = {
1227         [0] = 0x0000,
1228         [1] = 0x0080,
1229         [2] = 0x0808,
1230         [3] = 0x0888,
1231         [4] = 0x2222,
1232         [5] = 0x4924,
1233         [6] = 0x4A52,
1234         [7] = 0x54AA,
1235         [8] = 0x5555,
1236         [9] = 0xD555,
1237         [10] = 0xD5D5,
1238         [11] = 0xDDD5,
1239         [12] = 0xDDDD,
1240         [13] = 0xDFDD,
1241         [14] = 0xDFDF,
1242         [15] = 0xFFDF,
1243 };
1244
1245 static void s3c24xx_serial_set_termios(struct uart_port *port,
1246                                        struct ktermios *termios,
1247                                        struct ktermios *old)
1248 {
1249         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1250         struct s3c24xx_uart_port *ourport = to_ourport(port);
1251         struct clk *clk = ERR_PTR(-EINVAL);
1252         unsigned long flags;
1253         unsigned int baud, quot, clk_sel = 0;
1254         unsigned int ulcon;
1255         unsigned int umcon;
1256         unsigned int udivslot = 0;
1257
1258         /*
1259          * We don't support modem control lines.
1260          */
1261         termios->c_cflag &= ~(HUPCL | CMSPAR);
1262         termios->c_cflag |= CLOCAL;
1263
1264         /*
1265          * Ask the core to calculate the divisor for us.
1266          */
1267
1268         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1269         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1270         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1271                 quot = port->custom_divisor;
1272         if (IS_ERR(clk))
1273                 return;
1274
1275         /* check to see if we need  to change clock source */
1276
1277         if (ourport->baudclk != clk) {
1278                 clk_prepare_enable(clk);
1279
1280                 s3c24xx_serial_setsource(port, clk_sel);
1281
1282                 if (!IS_ERR(ourport->baudclk)) {
1283                         clk_disable_unprepare(ourport->baudclk);
1284                         ourport->baudclk = ERR_PTR(-EINVAL);
1285                 }
1286
1287                 ourport->baudclk = clk;
1288                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1289         }
1290
1291         if (ourport->info->has_divslot) {
1292                 unsigned int div = ourport->baudclk_rate / baud;
1293
1294                 if (cfg->has_fracval) {
1295                         udivslot = (div & 15);
1296                         dbg("fracval = %04x\n", udivslot);
1297                 } else {
1298                         udivslot = udivslot_table[div & 15];
1299                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1300                 }
1301         }
1302
1303         switch (termios->c_cflag & CSIZE) {
1304         case CS5:
1305                 dbg("config: 5bits/char\n");
1306                 ulcon = S3C2410_LCON_CS5;
1307                 break;
1308         case CS6:
1309                 dbg("config: 6bits/char\n");
1310                 ulcon = S3C2410_LCON_CS6;
1311                 break;
1312         case CS7:
1313                 dbg("config: 7bits/char\n");
1314                 ulcon = S3C2410_LCON_CS7;
1315                 break;
1316         case CS8:
1317         default:
1318                 dbg("config: 8bits/char\n");
1319                 ulcon = S3C2410_LCON_CS8;
1320                 break;
1321         }
1322
1323         /* preserve original lcon IR settings */
1324         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1325
1326         if (termios->c_cflag & CSTOPB)
1327                 ulcon |= S3C2410_LCON_STOPB;
1328
1329         if (termios->c_cflag & PARENB) {
1330                 if (termios->c_cflag & PARODD)
1331                         ulcon |= S3C2410_LCON_PODD;
1332                 else
1333                         ulcon |= S3C2410_LCON_PEVEN;
1334         } else {
1335                 ulcon |= S3C2410_LCON_PNONE;
1336         }
1337
1338         spin_lock_irqsave(&port->lock, flags);
1339
1340         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1341             ulcon, quot, udivslot);
1342
1343         wr_regl(port, S3C2410_ULCON, ulcon);
1344         wr_regl(port, S3C2410_UBRDIV, quot);
1345
1346         port->status &= ~UPSTAT_AUTOCTS;
1347
1348         umcon = rd_regl(port, S3C2410_UMCON);
1349         if (termios->c_cflag & CRTSCTS) {
1350                 umcon |= S3C2410_UMCOM_AFC;
1351                 /* Disable RTS when RX FIFO contains 63 bytes */
1352                 umcon &= ~S3C2412_UMCON_AFC_8;
1353                 port->status = UPSTAT_AUTOCTS;
1354         } else {
1355                 umcon &= ~S3C2410_UMCOM_AFC;
1356         }
1357         wr_regl(port, S3C2410_UMCON, umcon);
1358
1359         if (ourport->info->has_divslot)
1360                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1361
1362         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1363             rd_regl(port, S3C2410_ULCON),
1364             rd_regl(port, S3C2410_UCON),
1365             rd_regl(port, S3C2410_UFCON));
1366
1367         /*
1368          * Update the per-port timeout.
1369          */
1370         uart_update_timeout(port, termios->c_cflag, baud);
1371
1372         /*
1373          * Which character status flags are we interested in?
1374          */
1375         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1376         if (termios->c_iflag & INPCK)
1377                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1378                         S3C2410_UERSTAT_PARITY;
1379         /*
1380          * Which character status flags should we ignore?
1381          */
1382         port->ignore_status_mask = 0;
1383         if (termios->c_iflag & IGNPAR)
1384                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1385         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1386                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1387
1388         /*
1389          * Ignore all characters if CREAD is not set.
1390          */
1391         if ((termios->c_cflag & CREAD) == 0)
1392                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1393
1394         spin_unlock_irqrestore(&port->lock, flags);
1395 }
1396
1397 static const char *s3c24xx_serial_type(struct uart_port *port)
1398 {
1399         switch (port->type) {
1400         case PORT_S3C2410:
1401                 return "S3C2410";
1402         case PORT_S3C2440:
1403                 return "S3C2440";
1404         case PORT_S3C2412:
1405                 return "S3C2412";
1406         case PORT_S3C6400:
1407                 return "S3C6400/10";
1408         default:
1409                 return NULL;
1410         }
1411 }
1412
1413 #define MAP_SIZE (0x100)
1414
1415 static void s3c24xx_serial_release_port(struct uart_port *port)
1416 {
1417         release_mem_region(port->mapbase, MAP_SIZE);
1418 }
1419
1420 static int s3c24xx_serial_request_port(struct uart_port *port)
1421 {
1422         const char *name = s3c24xx_serial_portname(port);
1423         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1424 }
1425
1426 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1427 {
1428         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1429
1430         if (flags & UART_CONFIG_TYPE &&
1431             s3c24xx_serial_request_port(port) == 0)
1432                 port->type = info->type;
1433 }
1434
1435 /*
1436  * verify the new serial_struct (for TIOCSSERIAL).
1437  */
1438 static int
1439 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1440 {
1441         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1442
1443         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1444                 return -EINVAL;
1445
1446         return 0;
1447 }
1448
1449
1450 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1451
1452 static struct console s3c24xx_serial_console;
1453
1454 static int __init s3c24xx_serial_console_init(void)
1455 {
1456         register_console(&s3c24xx_serial_console);
1457         return 0;
1458 }
1459 console_initcall(s3c24xx_serial_console_init);
1460
1461 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1462 #else
1463 #define S3C24XX_SERIAL_CONSOLE NULL
1464 #endif
1465
1466 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1467 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1468 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1469                          unsigned char c);
1470 #endif
1471
1472 static struct uart_ops s3c24xx_serial_ops = {
1473         .pm             = s3c24xx_serial_pm,
1474         .tx_empty       = s3c24xx_serial_tx_empty,
1475         .get_mctrl      = s3c24xx_serial_get_mctrl,
1476         .set_mctrl      = s3c24xx_serial_set_mctrl,
1477         .stop_tx        = s3c24xx_serial_stop_tx,
1478         .start_tx       = s3c24xx_serial_start_tx,
1479         .stop_rx        = s3c24xx_serial_stop_rx,
1480         .break_ctl      = s3c24xx_serial_break_ctl,
1481         .startup        = s3c24xx_serial_startup,
1482         .shutdown       = s3c24xx_serial_shutdown,
1483         .set_termios    = s3c24xx_serial_set_termios,
1484         .type           = s3c24xx_serial_type,
1485         .release_port   = s3c24xx_serial_release_port,
1486         .request_port   = s3c24xx_serial_request_port,
1487         .config_port    = s3c24xx_serial_config_port,
1488         .verify_port    = s3c24xx_serial_verify_port,
1489 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1490         .poll_get_char = s3c24xx_serial_get_poll_char,
1491         .poll_put_char = s3c24xx_serial_put_poll_char,
1492 #endif
1493 };
1494
1495 static struct uart_driver s3c24xx_uart_drv = {
1496         .owner          = THIS_MODULE,
1497         .driver_name    = "s3c2410_serial",
1498         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1499         .cons           = S3C24XX_SERIAL_CONSOLE,
1500         .dev_name       = S3C24XX_SERIAL_NAME,
1501         .major          = S3C24XX_SERIAL_MAJOR,
1502         .minor          = S3C24XX_SERIAL_MINOR,
1503 };
1504
1505 #define __PORT_LOCK_UNLOCKED(i) \
1506         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1507 static struct s3c24xx_uart_port
1508 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1509         [0] = {
1510                 .port = {
1511                         .lock           = __PORT_LOCK_UNLOCKED(0),
1512                         .iotype         = UPIO_MEM,
1513                         .uartclk        = 0,
1514                         .fifosize       = 16,
1515                         .ops            = &s3c24xx_serial_ops,
1516                         .flags          = UPF_BOOT_AUTOCONF,
1517                         .line           = 0,
1518                 }
1519         },
1520         [1] = {
1521                 .port = {
1522                         .lock           = __PORT_LOCK_UNLOCKED(1),
1523                         .iotype         = UPIO_MEM,
1524                         .uartclk        = 0,
1525                         .fifosize       = 16,
1526                         .ops            = &s3c24xx_serial_ops,
1527                         .flags          = UPF_BOOT_AUTOCONF,
1528                         .line           = 1,
1529                 }
1530         },
1531 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1532
1533         [2] = {
1534                 .port = {
1535                         .lock           = __PORT_LOCK_UNLOCKED(2),
1536                         .iotype         = UPIO_MEM,
1537                         .uartclk        = 0,
1538                         .fifosize       = 16,
1539                         .ops            = &s3c24xx_serial_ops,
1540                         .flags          = UPF_BOOT_AUTOCONF,
1541                         .line           = 2,
1542                 }
1543         },
1544 #endif
1545 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1546         [3] = {
1547                 .port = {
1548                         .lock           = __PORT_LOCK_UNLOCKED(3),
1549                         .iotype         = UPIO_MEM,
1550                         .uartclk        = 0,
1551                         .fifosize       = 16,
1552                         .ops            = &s3c24xx_serial_ops,
1553                         .flags          = UPF_BOOT_AUTOCONF,
1554                         .line           = 3,
1555                 }
1556         }
1557 #endif
1558 };
1559 #undef __PORT_LOCK_UNLOCKED
1560
1561 /* s3c24xx_serial_resetport
1562  *
1563  * reset the fifos and other the settings.
1564 */
1565
1566 static void s3c24xx_serial_resetport(struct uart_port *port,
1567                                    struct s3c2410_uartcfg *cfg)
1568 {
1569         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1570         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1571         unsigned int ucon_mask;
1572
1573         ucon_mask = info->clksel_mask;
1574         if (info->type == PORT_S3C2440)
1575                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1576
1577         ucon &= ucon_mask;
1578         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1579
1580         /* reset both fifos */
1581         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1582         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1583
1584         /* some delay is required after fifo reset */
1585         udelay(1);
1586 }
1587
1588
1589 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1590
1591 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1592                                              unsigned long val, void *data)
1593 {
1594         struct s3c24xx_uart_port *port;
1595         struct uart_port *uport;
1596
1597         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1598         uport = &port->port;
1599
1600         /* check to see if port is enabled */
1601
1602         if (port->pm_level != 0)
1603                 return 0;
1604
1605         /* try and work out if the baudrate is changing, we can detect
1606          * a change in rate, but we do not have support for detecting
1607          * a disturbance in the clock-rate over the change.
1608          */
1609
1610         if (IS_ERR(port->baudclk))
1611                 goto exit;
1612
1613         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1614                 goto exit;
1615
1616         if (val == CPUFREQ_PRECHANGE) {
1617                 /* we should really shut the port down whilst the
1618                  * frequency change is in progress. */
1619
1620         } else if (val == CPUFREQ_POSTCHANGE) {
1621                 struct ktermios *termios;
1622                 struct tty_struct *tty;
1623
1624                 if (uport->state == NULL)
1625                         goto exit;
1626
1627                 tty = uport->state->port.tty;
1628
1629                 if (tty == NULL)
1630                         goto exit;
1631
1632                 termios = &tty->termios;
1633
1634                 if (termios == NULL) {
1635                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1636                         goto exit;
1637                 }
1638
1639                 s3c24xx_serial_set_termios(uport, termios, NULL);
1640         }
1641
1642 exit:
1643         return 0;
1644 }
1645
1646 static inline int
1647 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1648 {
1649         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1650
1651         return cpufreq_register_notifier(&port->freq_transition,
1652                                          CPUFREQ_TRANSITION_NOTIFIER);
1653 }
1654
1655 static inline void
1656 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1657 {
1658         cpufreq_unregister_notifier(&port->freq_transition,
1659                                     CPUFREQ_TRANSITION_NOTIFIER);
1660 }
1661
1662 #else
1663 static inline int
1664 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1665 {
1666         return 0;
1667 }
1668
1669 static inline void
1670 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1671 {
1672 }
1673 #endif
1674
1675 /* s3c24xx_serial_init_port
1676  *
1677  * initialise a single serial port from the platform device given
1678  */
1679
1680 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1681                                     struct platform_device *platdev)
1682 {
1683         struct uart_port *port = &ourport->port;
1684         struct s3c2410_uartcfg *cfg = ourport->cfg;
1685         struct resource *res;
1686         int ret;
1687
1688         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1689
1690         if (platdev == NULL)
1691                 return -ENODEV;
1692
1693         if (port->mapbase != 0)
1694                 return -EINVAL;
1695
1696         /* setup info for port */
1697         port->dev       = &platdev->dev;
1698
1699         /* Startup sequence is different for s3c64xx and higher SoC's */
1700         if (s3c24xx_serial_has_interrupt_mask(port))
1701                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1702
1703         port->uartclk = 1;
1704
1705         if (cfg->uart_flags & UPF_CONS_FLOW) {
1706                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1707                 port->flags |= UPF_CONS_FLOW;
1708         }
1709
1710         /* sort our the physical and virtual addresses for each UART */
1711
1712         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1713         if (res == NULL) {
1714                 dev_err(port->dev, "failed to find memory resource for uart\n");
1715                 return -EINVAL;
1716         }
1717
1718         dbg("resource %pR)\n", res);
1719
1720         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1721         if (!port->membase) {
1722                 dev_err(port->dev, "failed to remap controller address\n");
1723                 return -EBUSY;
1724         }
1725
1726         port->mapbase = res->start;
1727         ret = platform_get_irq(platdev, 0);
1728         if (ret < 0)
1729                 port->irq = 0;
1730         else {
1731                 port->irq = ret;
1732                 ourport->rx_irq = ret;
1733                 ourport->tx_irq = ret + 1;
1734         }
1735
1736         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1737                 ret = platform_get_irq(platdev, 1);
1738                 if (ret > 0)
1739                         ourport->tx_irq = ret;
1740         }
1741         /*
1742          * DMA is currently supported only on DT platforms, if DMA properties
1743          * are specified.
1744          */
1745         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1746                                                      "dmas", NULL)) {
1747                 ourport->dma = devm_kzalloc(port->dev,
1748                                             sizeof(*ourport->dma),
1749                                             GFP_KERNEL);
1750                 if (!ourport->dma) {
1751                         ret = -ENOMEM;
1752                         goto err;
1753                 }
1754         }
1755
1756         ourport->clk    = clk_get(&platdev->dev, "uart");
1757         if (IS_ERR(ourport->clk)) {
1758                 pr_err("%s: Controller clock not found\n",
1759                                 dev_name(&platdev->dev));
1760                 ret = PTR_ERR(ourport->clk);
1761                 goto err;
1762         }
1763
1764         ret = clk_prepare_enable(ourport->clk);
1765         if (ret) {
1766                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1767                 clk_put(ourport->clk);
1768                 goto err;
1769         }
1770
1771         /* Keep all interrupts masked and cleared */
1772         if (s3c24xx_serial_has_interrupt_mask(port)) {
1773                 wr_regl(port, S3C64XX_UINTM, 0xf);
1774                 wr_regl(port, S3C64XX_UINTP, 0xf);
1775                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1776         }
1777
1778         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1779             &port->mapbase, port->membase, port->irq,
1780             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1781
1782         /* reset the fifos (and setup the uart) */
1783         s3c24xx_serial_resetport(port, cfg);
1784
1785         return 0;
1786
1787 err:
1788         port->mapbase = 0;
1789         return ret;
1790 }
1791
1792 /* Device driver serial port probe */
1793
1794 static const struct of_device_id s3c24xx_uart_dt_match[];
1795 static int probe_index;
1796
1797 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1798                         struct platform_device *pdev)
1799 {
1800 #ifdef CONFIG_OF
1801         if (pdev->dev.of_node) {
1802                 const struct of_device_id *match;
1803                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1804                 return (struct s3c24xx_serial_drv_data *)match->data;
1805         }
1806 #endif
1807         return (struct s3c24xx_serial_drv_data *)
1808                         platform_get_device_id(pdev)->driver_data;
1809 }
1810
1811 static int s3c24xx_serial_probe(struct platform_device *pdev)
1812 {
1813         struct device_node *np = pdev->dev.of_node;
1814         struct s3c24xx_uart_port *ourport;
1815         int index = probe_index;
1816         int ret;
1817
1818         if (np) {
1819                 ret = of_alias_get_id(np, "serial");
1820                 if (ret >= 0)
1821                         index = ret;
1822         }
1823
1824         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1825
1826         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1827                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1828                 return -EINVAL;
1829         }
1830         ourport = &s3c24xx_serial_ports[index];
1831
1832         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1833         if (!ourport->drv_data) {
1834                 dev_err(&pdev->dev, "could not find driver data\n");
1835                 return -ENODEV;
1836         }
1837
1838         ourport->baudclk = ERR_PTR(-EINVAL);
1839         ourport->info = ourport->drv_data->info;
1840         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1841                         dev_get_platdata(&pdev->dev) :
1842                         ourport->drv_data->def_cfg;
1843
1844         if (np)
1845                 of_property_read_u32(np,
1846                         "samsung,uart-fifosize", &ourport->port.fifosize);
1847
1848         if (ourport->drv_data->fifosize[index])
1849                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1850         else if (ourport->info->fifosize)
1851                 ourport->port.fifosize = ourport->info->fifosize;
1852
1853         /*
1854          * DMA transfers must be aligned at least to cache line size,
1855          * so find minimal transfer size suitable for DMA mode
1856          */
1857         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1858                                     dma_get_cache_alignment());
1859
1860         dbg("%s: initialising port %p...\n", __func__, ourport);
1861
1862         ret = s3c24xx_serial_init_port(ourport, pdev);
1863         if (ret < 0)
1864                 return ret;
1865
1866         if (!s3c24xx_uart_drv.state) {
1867                 ret = uart_register_driver(&s3c24xx_uart_drv);
1868                 if (ret < 0) {
1869                         pr_err("Failed to register Samsung UART driver\n");
1870                         return ret;
1871                 }
1872         }
1873
1874         dbg("%s: adding port\n", __func__);
1875         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1876         platform_set_drvdata(pdev, &ourport->port);
1877
1878         /*
1879          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1880          * so that a potential re-enablement through the pm-callback overlaps
1881          * and keeps the clock enabled in this case.
1882          */
1883         clk_disable_unprepare(ourport->clk);
1884
1885         ret = s3c24xx_serial_cpufreq_register(ourport);
1886         if (ret < 0)
1887                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1888
1889         probe_index++;
1890
1891         return 0;
1892 }
1893
1894 static int s3c24xx_serial_remove(struct platform_device *dev)
1895 {
1896         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1897
1898         if (port) {
1899                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1900                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1901         }
1902
1903         uart_unregister_driver(&s3c24xx_uart_drv);
1904
1905         return 0;
1906 }
1907
1908 /* UART power management code */
1909 #ifdef CONFIG_PM_SLEEP
1910 static int s3c24xx_serial_suspend(struct device *dev)
1911 {
1912         struct uart_port *port = s3c24xx_dev_to_port(dev);
1913
1914         if (port)
1915                 uart_suspend_port(&s3c24xx_uart_drv, port);
1916
1917         return 0;
1918 }
1919
1920 static int s3c24xx_serial_resume(struct device *dev)
1921 {
1922         struct uart_port *port = s3c24xx_dev_to_port(dev);
1923         struct s3c24xx_uart_port *ourport = to_ourport(port);
1924
1925         if (port) {
1926                 clk_prepare_enable(ourport->clk);
1927                 if (!IS_ERR(ourport->baudclk))
1928                         clk_prepare_enable(ourport->baudclk);
1929                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1930                 if (!IS_ERR(ourport->baudclk))
1931                         clk_disable_unprepare(ourport->baudclk);
1932                 clk_disable_unprepare(ourport->clk);
1933
1934                 uart_resume_port(&s3c24xx_uart_drv, port);
1935         }
1936
1937         return 0;
1938 }
1939
1940 static int s3c24xx_serial_resume_noirq(struct device *dev)
1941 {
1942         struct uart_port *port = s3c24xx_dev_to_port(dev);
1943         struct s3c24xx_uart_port *ourport = to_ourport(port);
1944
1945         if (port) {
1946                 /* restore IRQ mask */
1947                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1948                         unsigned int uintm = 0xf;
1949                         if (tx_enabled(port))
1950                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1951                         if (rx_enabled(port))
1952                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1953                         clk_prepare_enable(ourport->clk);
1954                         if (!IS_ERR(ourport->baudclk))
1955                                 clk_prepare_enable(ourport->baudclk);
1956                         wr_regl(port, S3C64XX_UINTM, uintm);
1957                         if (!IS_ERR(ourport->baudclk))
1958                                 clk_disable_unprepare(ourport->baudclk);
1959                         clk_disable_unprepare(ourport->clk);
1960                 }
1961         }
1962
1963         return 0;
1964 }
1965
1966 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1967         .suspend = s3c24xx_serial_suspend,
1968         .resume = s3c24xx_serial_resume,
1969         .resume_noirq = s3c24xx_serial_resume_noirq,
1970 };
1971 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1972
1973 #else /* !CONFIG_PM_SLEEP */
1974
1975 #define SERIAL_SAMSUNG_PM_OPS   NULL
1976 #endif /* CONFIG_PM_SLEEP */
1977
1978 /* Console code */
1979
1980 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1981
1982 static struct uart_port *cons_uart;
1983
1984 static int
1985 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1986 {
1987         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1988         unsigned long ufstat, utrstat;
1989
1990         if (ufcon & S3C2410_UFCON_FIFOMODE) {
1991                 /* fifo mode - check amount of data in fifo registers... */
1992
1993                 ufstat = rd_regl(port, S3C2410_UFSTAT);
1994                 return (ufstat & info->tx_fifofull) ? 0 : 1;
1995         }
1996
1997         /* in non-fifo mode, we go and use the tx buffer empty */
1998
1999         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2000         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2001 }
2002
2003 static bool
2004 s3c24xx_port_configured(unsigned int ucon)
2005 {
2006         /* consider the serial port configured if the tx/rx mode set */
2007         return (ucon & 0xf) != 0;
2008 }
2009
2010 #ifdef CONFIG_CONSOLE_POLL
2011 /*
2012  * Console polling routines for writing and reading from the uart while
2013  * in an interrupt or debug context.
2014  */
2015
2016 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2017 {
2018         struct s3c24xx_uart_port *ourport = to_ourport(port);
2019         unsigned int ufstat;
2020
2021         ufstat = rd_regl(port, S3C2410_UFSTAT);
2022         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2023                 return NO_POLL_CHAR;
2024
2025         return rd_regb(port, S3C2410_URXH);
2026 }
2027
2028 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2029                 unsigned char c)
2030 {
2031         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2032         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2033
2034         /* not possible to xmit on unconfigured port */
2035         if (!s3c24xx_port_configured(ucon))
2036                 return;
2037
2038         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2039                 cpu_relax();
2040         wr_regb(port, S3C2410_UTXH, c);
2041 }
2042
2043 #endif /* CONFIG_CONSOLE_POLL */
2044
2045 static void
2046 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2047 {
2048         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2049
2050         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2051                 cpu_relax();
2052         wr_regb(port, S3C2410_UTXH, ch);
2053 }
2054
2055 static void
2056 s3c24xx_serial_console_write(struct console *co, const char *s,
2057                              unsigned int count)
2058 {
2059         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2060
2061         /* not possible to xmit on unconfigured port */
2062         if (!s3c24xx_port_configured(ucon))
2063                 return;
2064
2065         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2066 }
2067
2068 static void __init
2069 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2070                            int *parity, int *bits)
2071 {
2072         struct clk *clk;
2073         unsigned int ulcon;
2074         unsigned int ucon;
2075         unsigned int ubrdiv;
2076         unsigned long rate;
2077         unsigned int clk_sel;
2078         char clk_name[MAX_CLK_NAME_LENGTH];
2079
2080         ulcon  = rd_regl(port, S3C2410_ULCON);
2081         ucon   = rd_regl(port, S3C2410_UCON);
2082         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2083
2084         dbg("s3c24xx_serial_get_options: port=%p\n"
2085             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2086             port, ulcon, ucon, ubrdiv);
2087
2088         if (s3c24xx_port_configured(ucon)) {
2089                 switch (ulcon & S3C2410_LCON_CSMASK) {
2090                 case S3C2410_LCON_CS5:
2091                         *bits = 5;
2092                         break;
2093                 case S3C2410_LCON_CS6:
2094                         *bits = 6;
2095                         break;
2096                 case S3C2410_LCON_CS7:
2097                         *bits = 7;
2098                         break;
2099                 case S3C2410_LCON_CS8:
2100                 default:
2101                         *bits = 8;
2102                         break;
2103                 }
2104
2105                 switch (ulcon & S3C2410_LCON_PMASK) {
2106                 case S3C2410_LCON_PEVEN:
2107                         *parity = 'e';
2108                         break;
2109
2110                 case S3C2410_LCON_PODD:
2111                         *parity = 'o';
2112                         break;
2113
2114                 case S3C2410_LCON_PNONE:
2115                 default:
2116                         *parity = 'n';
2117                 }
2118
2119                 /* now calculate the baud rate */
2120
2121                 clk_sel = s3c24xx_serial_getsource(port);
2122                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2123
2124                 clk = clk_get(port->dev, clk_name);
2125                 if (!IS_ERR(clk))
2126                         rate = clk_get_rate(clk);
2127                 else
2128                         rate = 1;
2129
2130                 *baud = rate / (16 * (ubrdiv + 1));
2131                 dbg("calculated baud %d\n", *baud);
2132         }
2133
2134 }
2135
2136 static int __init
2137 s3c24xx_serial_console_setup(struct console *co, char *options)
2138 {
2139         struct uart_port *port;
2140         int baud = 9600;
2141         int bits = 8;
2142         int parity = 'n';
2143         int flow = 'n';
2144
2145         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2146             co, co->index, options);
2147
2148         /* is this a valid port */
2149
2150         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2151                 co->index = 0;
2152
2153         port = &s3c24xx_serial_ports[co->index].port;
2154
2155         /* is the port configured? */
2156
2157         if (port->mapbase == 0x0)
2158                 return -ENODEV;
2159
2160         cons_uart = port;
2161
2162         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2163
2164         /*
2165          * Check whether an invalid uart number has been specified, and
2166          * if so, search for the first available port that does have
2167          * console support.
2168          */
2169         if (options)
2170                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2171         else
2172                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2173
2174         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2175
2176         return uart_set_options(port, co, baud, parity, bits, flow);
2177 }
2178
2179 static struct console s3c24xx_serial_console = {
2180         .name           = S3C24XX_SERIAL_NAME,
2181         .device         = uart_console_device,
2182         .flags          = CON_PRINTBUFFER,
2183         .index          = -1,
2184         .write          = s3c24xx_serial_console_write,
2185         .setup          = s3c24xx_serial_console_setup,
2186         .data           = &s3c24xx_uart_drv,
2187 };
2188 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2189
2190 #ifdef CONFIG_CPU_S3C2410
2191 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2192         .info = &(struct s3c24xx_uart_info) {
2193                 .name           = "Samsung S3C2410 UART",
2194                 .type           = PORT_S3C2410,
2195                 .fifosize       = 16,
2196                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2197                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2198                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2199                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2200                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2201                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2202                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2203                 .num_clks       = 2,
2204                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2205                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2206         },
2207         .def_cfg = &(struct s3c2410_uartcfg) {
2208                 .ucon           = S3C2410_UCON_DEFAULT,
2209                 .ufcon          = S3C2410_UFCON_DEFAULT,
2210         },
2211 };
2212 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2213 #else
2214 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2215 #endif
2216
2217 #ifdef CONFIG_CPU_S3C2412
2218 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2219         .info = &(struct s3c24xx_uart_info) {
2220                 .name           = "Samsung S3C2412 UART",
2221                 .type           = PORT_S3C2412,
2222                 .fifosize       = 64,
2223                 .has_divslot    = 1,
2224                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2225                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2226                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2227                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2228                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2229                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2230                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2231                 .num_clks       = 4,
2232                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2233                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2234         },
2235         .def_cfg = &(struct s3c2410_uartcfg) {
2236                 .ucon           = S3C2410_UCON_DEFAULT,
2237                 .ufcon          = S3C2410_UFCON_DEFAULT,
2238         },
2239 };
2240 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2241 #else
2242 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2243 #endif
2244
2245 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2246         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2247 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2248         .info = &(struct s3c24xx_uart_info) {
2249                 .name           = "Samsung S3C2440 UART",
2250                 .type           = PORT_S3C2440,
2251                 .fifosize       = 64,
2252                 .has_divslot    = 1,
2253                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2254                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2255                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2256                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2257                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2258                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2259                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2260                 .num_clks       = 4,
2261                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2262                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2263         },
2264         .def_cfg = &(struct s3c2410_uartcfg) {
2265                 .ucon           = S3C2410_UCON_DEFAULT,
2266                 .ufcon          = S3C2410_UFCON_DEFAULT,
2267         },
2268 };
2269 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2270 #else
2271 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2272 #endif
2273
2274 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2275 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2276         .info = &(struct s3c24xx_uart_info) {
2277                 .name           = "Samsung S3C6400 UART",
2278                 .type           = PORT_S3C6400,
2279                 .fifosize       = 64,
2280                 .has_divslot    = 1,
2281                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2282                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2283                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2284                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2285                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2286                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2287                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2288                 .num_clks       = 4,
2289                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2290                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2291         },
2292         .def_cfg = &(struct s3c2410_uartcfg) {
2293                 .ucon           = S3C2410_UCON_DEFAULT,
2294                 .ufcon          = S3C2410_UFCON_DEFAULT,
2295         },
2296 };
2297 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2298 #else
2299 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2300 #endif
2301
2302 #ifdef CONFIG_CPU_S5PV210
2303 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2304         .info = &(struct s3c24xx_uart_info) {
2305                 .name           = "Samsung S5PV210 UART",
2306                 .type           = PORT_S3C6400,
2307                 .has_divslot    = 1,
2308                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2309                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2310                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2311                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2312                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2313                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2314                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2315                 .num_clks       = 2,
2316                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2317                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2318         },
2319         .def_cfg = &(struct s3c2410_uartcfg) {
2320                 .ucon           = S5PV210_UCON_DEFAULT,
2321                 .ufcon          = S5PV210_UFCON_DEFAULT,
2322         },
2323         .fifosize = { 256, 64, 16, 16 },
2324 };
2325 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2326 #else
2327 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2328 #endif
2329
2330 #if defined(CONFIG_ARCH_EXYNOS)
2331 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2332         .info = &(struct s3c24xx_uart_info) {                   \
2333                 .name           = "Samsung Exynos UART",        \
2334                 .type           = PORT_S3C6400,                 \
2335                 .has_divslot    = 1,                            \
2336                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2337                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2338                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2339                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2340                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2341                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2342                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2343                 .num_clks       = 1,                            \
2344                 .clksel_mask    = 0,                            \
2345                 .clksel_shift   = 0,                            \
2346         },                                                      \
2347         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2348                 .ucon           = S5PV210_UCON_DEFAULT,         \
2349                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2350                 .has_fracval    = 1,                            \
2351         }                                                       \
2352
2353 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2354         EXYNOS_COMMON_SERIAL_DRV_DATA,
2355         .fifosize = { 256, 64, 16, 16 },
2356 };
2357
2358 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2359         EXYNOS_COMMON_SERIAL_DRV_DATA,
2360         .fifosize = { 64, 256, 16, 256 },
2361 };
2362
2363 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2364 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2365 #else
2366 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2367 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2368 #endif
2369
2370 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2371         {
2372                 .name           = "s3c2410-uart",
2373                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2374         }, {
2375                 .name           = "s3c2412-uart",
2376                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2377         }, {
2378                 .name           = "s3c2440-uart",
2379                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2380         }, {
2381                 .name           = "s3c6400-uart",
2382                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2383         }, {
2384                 .name           = "s5pv210-uart",
2385                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2386         }, {
2387                 .name           = "exynos4210-uart",
2388                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2389         }, {
2390                 .name           = "exynos5433-uart",
2391                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2392         },
2393         { },
2394 };
2395 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2396
2397 #ifdef CONFIG_OF
2398 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2399         { .compatible = "samsung,s3c2410-uart",
2400                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2401         { .compatible = "samsung,s3c2412-uart",
2402                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2403         { .compatible = "samsung,s3c2440-uart",
2404                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2405         { .compatible = "samsung,s3c6400-uart",
2406                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2407         { .compatible = "samsung,s5pv210-uart",
2408                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2409         { .compatible = "samsung,exynos4210-uart",
2410                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2411         { .compatible = "samsung,exynos5433-uart",
2412                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2413         {},
2414 };
2415 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2416 #endif
2417
2418 static struct platform_driver samsung_serial_driver = {
2419         .probe          = s3c24xx_serial_probe,
2420         .remove         = s3c24xx_serial_remove,
2421         .id_table       = s3c24xx_serial_driver_ids,
2422         .driver         = {
2423                 .name   = "samsung-uart",
2424                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2425                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2426         },
2427 };
2428
2429 module_platform_driver(samsung_serial_driver);
2430
2431 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2432 /*
2433  * Early console.
2434  */
2435
2436 struct samsung_early_console_data {
2437         u32 txfull_mask;
2438 };
2439
2440 static void samsung_early_busyuart(struct uart_port *port)
2441 {
2442         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2443                 ;
2444 }
2445
2446 static void samsung_early_busyuart_fifo(struct uart_port *port)
2447 {
2448         struct samsung_early_console_data *data = port->private_data;
2449
2450         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2451                 ;
2452 }
2453
2454 static void samsung_early_putc(struct uart_port *port, int c)
2455 {
2456         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2457                 samsung_early_busyuart_fifo(port);
2458         else
2459                 samsung_early_busyuart(port);
2460
2461         writeb(c, port->membase + S3C2410_UTXH);
2462 }
2463
2464 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2465 {
2466         struct earlycon_device *dev = con->data;
2467
2468         uart_console_write(&dev->port, s, n, samsung_early_putc);
2469 }
2470
2471 static int __init samsung_early_console_setup(struct earlycon_device *device,
2472                                               const char *opt)
2473 {
2474         if (!device->port.membase)
2475                 return -ENODEV;
2476
2477         device->con->write = samsung_early_write;
2478         return 0;
2479 }
2480
2481 /* S3C2410 */
2482 static struct samsung_early_console_data s3c2410_early_console_data = {
2483         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2484 };
2485
2486 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2487                                               const char *opt)
2488 {
2489         device->port.private_data = &s3c2410_early_console_data;
2490         return samsung_early_console_setup(device, opt);
2491 }
2492 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2493                         s3c2410_early_console_setup);
2494
2495 /* S3C2412, S3C2440, S3C64xx */
2496 static struct samsung_early_console_data s3c2440_early_console_data = {
2497         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2498 };
2499
2500 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2501                                               const char *opt)
2502 {
2503         device->port.private_data = &s3c2440_early_console_data;
2504         return samsung_early_console_setup(device, opt);
2505 }
2506 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2507                         s3c2440_early_console_setup);
2508 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2509                         s3c2440_early_console_setup);
2510 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2511                         s3c2440_early_console_setup);
2512
2513 /* S5PV210, EXYNOS */
2514 static struct samsung_early_console_data s5pv210_early_console_data = {
2515         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2516 };
2517
2518 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2519                                               const char *opt)
2520 {
2521         device->port.private_data = &s5pv210_early_console_data;
2522         return samsung_early_console_setup(device, opt);
2523 }
2524 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2525                         s5pv210_early_console_setup);
2526 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2527                         s5pv210_early_console_setup);
2528 #endif
2529
2530 MODULE_ALIAS("platform:samsung-uart");
2531 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2532 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2533 MODULE_LICENSE("GPL v2");